diff --git a/.gitignore b/.gitignore index cef857a69e..14d84ddc79 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ *.idb *.ilk *.old +*.crf build Debug documentation/html diff --git a/bsp/Vango_V85xx/.config b/bsp/Vango_V85xx/.config new file mode 100644 index 0000000000..a126fcbfae --- /dev/null +++ b/bsp/Vango_V85xx/.config @@ -0,0 +1,596 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set +CONFIG_SOC_SERIES_V85XX=y +CONFIG_SOC_V85XX=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_RTC is not set diff --git a/bsp/Vango_V85xx/.ignore_format.yml b/bsp/Vango_V85xx/.ignore_format.yml new file mode 100644 index 0000000000..9ca31ca955 --- /dev/null +++ b/bsp/Vango_V85xx/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- Libraries/VangoV85xx_standard_peripheral diff --git a/bsp/Vango_V85xx/Kconfig b/bsp/Vango_V85xx/Kconfig new file mode 100644 index 0000000000..df8194d747 --- /dev/null +++ b/bsp/Vango_V85xx/Kconfig @@ -0,0 +1,109 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default: "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_SERIES_V85XX + bool + default y + +config SOC_V85XX + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select SOC_SERIES_V85XX + default y + +menu "On-chip Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "using uart0" + default n + config BSP_USING_UART1 + bool "using uart1" + default n + config BSP_USING_UART2 + bool "using uart2" + default y + config BSP_USING_UART3 + bool "using uart3" + default n + config BSP_USING_UART4 + bool "using uart4" + default n + endif + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "using adc0" + default n + config BSP_USING_ADC1 + bool "using adc1" + default n + endif + menuconfig BSP_USING_HWTIMER + bool "Enable hwtimer" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_HWTIMER0 + bool "using hwtimer0" + default n + config BSP_USING_HWTIMER1 + bool "using hwtimer1" + default n + config BSP_USING_HWTIMER2 + bool "using hwtimer2" + default n + config BSP_USING_HWTIMER3 + bool "using hwtimer3" + default n + config BSP_USING_HWTIMER4 + bool "using hwtimer4" + default n + config BSP_USING_HWTIMER5 + bool "using hwtimer5" + default n + config BSP_USING_HWTIMER6 + bool "using hwtimer6" + default n + config BSP_USING_HWTIMER7 + bool "using hwtimer7" + default n + endif + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_RTC + bool "using internal rtc" + default n + select RT_USING_RTC + +endmenu diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h new file mode 100644 index 0000000000..1ee13c34ea --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h @@ -0,0 +1,46 @@ +/** + ****************************************************************************** + * @file lib_CodeRAM.h + * @author Application Team + * @version V4.4.0 + * @date 2019-01-18 + * @brief Codes executed in SRAM. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CODERAM_H +#define __LIB_CODERAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +#ifndef __GNUC__ + +#ifdef __ICCARM__ /* EWARM */ + #define __RAM_FUNC __ramfunc +#endif + +#ifdef __CC_ARM /* MDK-ARM */ + #define __RAM_FUNC __attribute__((used)) +#endif + +/* Exported Functions ------------------------------------------------------- */ + +__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void); + +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CODERAM_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h new file mode 100644 index 0000000000..e28cad6b66 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h @@ -0,0 +1,231 @@ +/** + ****************************************************************************** + * @file lib_LoadNVR.h + * @author Application Team + * @version V4.7.0 + * @date 2019-12-12 + * @brief Load information from NVR. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_LOADNVR_H +#define __LIB_LOADNVR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + +/* BAT measure result */ +typedef struct +{ + float BATRESResult; // BAT Resistor division Measure Result + float BATCAPResult; // BATRTC Cap division Measure Result +} NVR_BATMEARES; + +/* Power Measure Result */ +typedef struct +{ + uint32_t AVCCMEAResult; // LDO33 Measure Result + uint32_t DVCCMEAResult; // LDO15 Measure Result + uint32_t BGPMEAResult; // BGP Measure Result + uint32_t RCLMEAResult; // RCL Measure Result + uint32_t RCHMEAResult; // RCH Measure Result +} NVR_MISCGain; + +/* Chip ID */ +typedef struct +{ + uint32_t ChipID0; // ID word 0 + uint32_t ChipID1; // ID word 1 +} NVR_CHIPID; + +/* Temperature information */ +typedef struct +{ + float TempOffset; +} NVR_TEMPINFO; + +/* LCD information */ +typedef struct +{ + uint32_t MEALCDLDO; // Measure LCD LDO pre trim value + uint32_t MEALCDVol; // VLCD setting +} NVR_LCDINFO; + +/* RTC(temp) information */ +typedef struct +{ + int16_t RTCTempP0; //P0 + int16_t RTCTempP1; //P1 + int32_t RTCTempP2; //P2 + int16_t RTCTempP4; //P4 + int16_t RTCTempP5; //P5 + int16_t RTCTempP6; //P6 + int16_t RTCTempP7; //P7 + int16_t RTCTempK1; //K1 + int16_t RTCTempK2; //K2 + int16_t RTCTempK3; //K3 + int16_t RTCTempK4; //K4 + int16_t RTCTempK5; //K5 + int16_t RTCACTI; //Center temperature + uint32_t RTCACKTemp; //section X temperature + int16_t RTCTempDelta; //Temperature delta + uint32_t RTCACF200; //RTC_ACF200 + uint32_t APBClock; //APB clock +} NVR_RTCINFO; + +/* ADC Voltage Parameters */ +typedef struct +{ + float aParameter; + float bParameter; +} NVR_ADCVOLPARA; +//Mode +#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None +#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive +#define NVR_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive +#define NVR_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive +#define NVR_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive +#define NVR_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive +#define NVR_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive +#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None +#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive +#define NVR_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive +#define NVR_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive +#define NVR_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive +#define NVR_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive +#define NVR_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive +#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\ + ((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == NVR_3V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == NVR_3V_VDD_RESDIV) ||\ + ((__MODE__) == NVR_3V_VDD_CAPDIV) ||\ + ((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\ + ((__MODE__) == NVR_3V_BATRTC_CAPDIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == NVR_5V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == NVR_5V_VDD_RESDIV) ||\ + ((__MODE__) == NVR_5V_VDD_CAPDIV) ||\ + ((__MODE__) == NVR_5V_BATRTC_RESDIV) ||\ + ((__MODE__) == NVR_5V_BATRTC_CAPDIV)) + +/********** NVR Address **********/ +//ADC Voltage Parameters +#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x40400) +#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x40440) +#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x40480) +#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x404C0) +//RTC DATA +//P4 +#define NVR_RTC1_P4 (__IO uint32_t *)(0x40800) +#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x40804) +#define NVR_RTC2_P4 (__IO uint32_t *)(0x40808) +#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x4080C) +//ACK1~ACK5 +#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x40810) +#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x40814) +#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x40818) +#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x4081C) +#define NVR_RTC1_ACK5 (__IO uint32_t *)(0x40820) +#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x40824) +#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x40828) +#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x4082C) +#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x40830) +#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x40834) +#define NVR_RTC2_ACK5 (__IO uint32_t *)(0x40838) +#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x4083C) +//ACTI +#define NVR_RTC1_ACTI (__IO uint32_t *)(0x40840) +#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x40844) +#define NVR_RTC2_ACTI (__IO uint32_t *)(0x40848) +#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x4084C) +//ACKTEMP +#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x40850) +#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x40854) +#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x40858) +#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x4085C) +//Analog trim data +#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x40DC0) +#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x40DC4) +#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x40DC8) +#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x40DCC) +#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x40DD0) +#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x40DD4) +#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x40DD8) +#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x40DDC) +//BAT Measure Result +#define NVR_BAT_R1 (__IO uint32_t *)(0x40CE0) +#define NVR_BAT_C1 (__IO uint32_t *)(0x40CE4) +#define NVR_BATMEA_CHECHSUM1 (__IO uint32_t *)(0x40CE8) +#define NVR_BAT_R2 (__IO uint32_t *)(0x40CF0) +#define NVR_BAT_C2 (__IO uint32_t *)(0x40CF4) +#define NVR_BATMEA_CHECHSUM2 (__IO uint32_t *)(0x40CF8) +//RTC AutoCal Px pramameters +#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x40D00) +#define NVR_RTC1_P2 (__IO uint32_t *)(0x40D04) +#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x40D08) +#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x40D0C) +#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x40D10) +#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x40D14) +#define NVR_RTC2_P2 (__IO uint32_t *)(0x40D18) +#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x40D1C) +#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x40D20) +#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x40D24) +//Power Measure Result +#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x40D28) +#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x40D2C) +#define NVR_BGP_MEA1 (__IO uint32_t *)(0x40D30) +#define NVR_RCL_MEA1 (__IO uint32_t *)(0x40D34) +#define NVR_RCH_MEA1 (__IO uint32_t *)(0x40D38) +#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x40D3C) +#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x40D40) +#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x40D44) +#define NVR_BGP_MEA2 (__IO uint32_t *)(0x40D48) +#define NVR_RCL_MEA2 (__IO uint32_t *)(0x40D4C) +#define NVR_RCH_MEA2 (__IO uint32_t *)(0x40D50) +#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x40D54) +//Chip ID +#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x40D58) +#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x40D5C) +#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x40D60) +#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x40D64) +#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x40D68) +#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x40D6C) +//Temperature information +#define NVR_REALTEMP1 (__IO uint32_t *)(0x40D70) +#define NVR_MEATEMP1 (__IO uint32_t *)(0x40D74) +#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x40D78) +#define NVR_REALTEMP2 (__IO uint32_t *)(0x40D7C) +#define NVR_MEATEMP2 (__IO uint32_t *)(0x40D80) +#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x40D84) +//LCD Information +#define NVR_LCD_LDO1 (__IO uint32_t *)(0x40D90) +#define NVR_LCD_VOL1 (__IO uint32_t *)(0x40D94) +#define NVR_LCD_CHECKSUM1 (__IO uint32_t *)(0x40D98) +#define NVR_LCD_LDO2 (__IO uint32_t *)(0x40D9C) +#define NVR_LCD_VOL2 (__IO uint32_t *)(0x40DA0) +#define NVR_LCD_CHECKSUM2 (__IO uint32_t *)(0x40DA4) + + +uint32_t NVR_LoadANADataManual(void); +uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter); +uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult); +uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData); +uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult); +uint32_t NVR_GetChipID(NVR_CHIPID *ChipID); +uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_LOADNVR_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h new file mode 100644 index 0000000000..a536dfc6d9 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file lib_conf.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Dirver configuration. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CONF_H +#define __LIB_CONF_H + +/* ########################## Assert Selection ############################## */ + +//#define ASSERT_NDEBUG 1 + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#include "lib_ana.h" +#include "lib_adc.h" +#include "lib_adc_tiny.h" +#include "lib_clk.h" +#include "lib_comp.h" +#include "lib_crypt.h" +#include "lib_dma.h" +#include "lib_flash.h" +#include "lib_gpio.h" +#include "lib_i2c.h" +#include "lib_iso7816.h" +#include "lib_lcd.h" +#include "lib_misc.h" +#include "lib_pmu.h" +#include "lib_pwm.h" +#include "lib_rtc.h" +#include "lib_spi.h" +#include "lib_tmr.h" +#include "lib_u32k.h" +#include "lib_uart.h" +#include "lib_version.h" +#include "lib_wdt.h" +#include "lib_LoadNVR.h" +#include "lib_CodeRAM.h" +#include "lib_cortex.h" + +/* Exported macro ------------------------------------------------------------*/ +#ifndef ASSERT_NDEBUG + #define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_errhandler(uint8_t* file, uint32_t line); +#else + #define assert_parameters(expr) ((void)0U) +#endif /* ASSERT_NDEBUG */ + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h new file mode 100644 index 0000000000..d7c1994cfc --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h @@ -0,0 +1,48 @@ +/** + ****************************************************************************** + * @file lib_Cortex.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Cortex module driver. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __LIB_CORTEX_H +#define __LIB_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "target.h" + + +#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) + +/* Exported Functions ------------------------------------------------------- */ +void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority); + +void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn); +uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn); +void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority); +void CORTEX_NVIC_SystemReset(void); +uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CORTEX_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h new file mode 100644 index 0000000000..c897151964 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h @@ -0,0 +1,41 @@ +/** + ****************************************************************************** + * @file system_target.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief system source file. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __SYSTEM_TARGET_H +#define __SYSTEM_TARGET_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "type_def.h" + +#define NVR_REGINFOCOUNT1 (0x80400) +#define NVR_REGINFOBAKOFFSET (0x100) + +/* ########################### System Configuration ######################### */ + +extern void SystemInit(void); +extern void SystemUpdate(void); + + +#ifdef USE_TARGET_DRIVER + #include "lib_conf.h" +#endif /* USE_TARGET_DRIVER */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_TARGET_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h new file mode 100644 index 0000000000..7199c552fb --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/target.h @@ -0,0 +1,4994 @@ +/** +******************************************************************************** +* @file target.h +* @author Application Team +* @version V4.4.0 +* @date 2018-09-27 +* @brief Register define +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, XXXXX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +******************************************************************************** +*/ +#ifndef __TARGET_H +#define __TARGET_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define __Vendor_SysTickConfig 0 /*!< target uses systick config */ +#define __NVIC_PRIO_BITS 2 /*!< target uses 2 Bits for the Priority Levels */ + +typedef enum {ERROR = 0, SUCCESS = !ERROR, RESET = 0, SET = !RESET, DISABLE = 0, ENABLE = !DISABLE} TypeState, EventStatus, ControlStatus, FlagStatus, ErrStatus; + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NMI_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** target specific Interrupt Numbers ********************************************************************/ + PMU_IRQn = 0, /*!< Power Management Unit Interrupt */ + RTC_IRQn = 1, /*!< RTC global Interrupt */ + U32K0_IRQn = 2, /*!< U32K0 global Interrupt */ + U32K1_IRQn = 3, /*!< U32K1 global Interrupt */ + I2C_IRQn = 4, /*!< I2C global Interrupt */ + SPI1_IRQn = 5, /*!< SPI1 global Interrupt */ + UART0_IRQn = 6, /*!< UART0 global Interrupt */ + UART1_IRQn = 7, /*!< UART1 global Interrupt */ + UART2_IRQn = 8, /*!< UART2 global Interrupt */ + UART3_IRQn = 9, /*!< UART3 global Interrupt */ + UART4_IRQn = 10, /*!< UART4 global Interrupt */ + UART5_IRQn = 11, /*!< UART5 global Interrupt */ + ISO78160_IRQn = 12, /*!< ISO78160 global Interrupt */ + ISO78161_IRQn = 13, /*!< ISO78161 global Interrupt */ + TMR0_IRQn = 14, /*!< Timer0 global Interrupt */ + TMR1_IRQn = 15, /*!< Timer1 global Interrupt */ + TMR2_IRQn = 16, /*!< Timer2 global Interrupt */ + TMR3_IRQn = 17, /*!< Timer3 global Interrupt */ + PWM0_IRQn = 18, /*!< PWM0 global Interrupt */ + PWM1_IRQn = 19, /*!< PWM1 global Interrupt */ + PWM2_IRQn = 20, /*!< PWM2 global Interrupt */ + PWM3_IRQn = 21, /*!< PWM3 global Interrupt */ + DMA_IRQn = 22, /*!< DMA global Interrupt */ + FLASH_IRQn = 23, /*!< FLASH global Interrupt */ + ANA_IRQn = 24, /*!< ANA global Interrupt */ + SPI2_IRQn = 27, /*!< SPI2 global Interrupt */ +} IRQn_Type; + +#include "core_cm0.h" +#include "type_def.h" + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Power Management Unit Controller + */ + +typedef struct +{ + __IO uint32_t DSLEEPEN; /*!< PMU deep sleep enable register, Address offset: 0x00 */ + __IO uint32_t DSLEEPPASS; /*!< PMU deep sleep password register, Address offset: 0x04 */ + __IO uint32_t CONTROL; /*!< PMU control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< PMU Status register, Address offset: 0x0C */ + __IO uint32_t IOAOEN; /*!< IOA output enable register, Address offset: 0x10 */ + __IO uint32_t IOAIE; /*!< IOA input enable register, Address offset: 0x14 */ + __IO uint32_t IOADAT; /*!< IOA data register, Address offset: 0x18 */ + __IO uint32_t IOAATT; /*!< IOA attribute register, Address offset: 0x1C */ + __IO uint32_t IOAWKUEN; /*!< IOA input status register, Address offset: 0x20 */ + __IO uint32_t IOASTS; /*!< IOA input status register, Address offset: 0x24 */ + __IO uint32_t IOAINTSTS; /*!< IOA input status register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< Reserved, 0x2C */ + uint32_t RESERVED2; /*!< Reserved, 0x30 */ + uint32_t RESERVED3; /*!< Reserved, 0x34 */ + __IO uint32_t IOASEL; /*!< IOA special function select register, Address offset: 0x38 */ + __IO uint32_t VERSIONID_; /*!< Version ID of chip, Address offset: 0x3C */ + __IO uint32_t WDTPASS; /*!< Watch dog timing unlock register, Address offset: 0x40 */ + __IO uint32_t WDTEN; /*!< Watch dog timer enable register, Address offset: 0x44 */ + __IO uint32_t WDTCLR; /*!< Watch dog timer clear register, Address offset: 0x48 */ +// __IO uint32_t WDTSTS; /*!< Watch dog timer status register, Address offset: 0x4C */ + uint32_t RESERVED4; /*!< Reserved, 0x4C */ + __IO uint32_t IOANODEG; /*!< IOA de-glitch circuit control, Address offset: 0x50 */ +}PMU_TypeDef; + +/** + * @brief Power Management Unit Retention RAM + */ + +typedef struct +{ + __IO uint32_t RAM[64]; /*!< PMU 32 bits Retention RAM 0-63, Address offset: 0x00-0xFC */ +}PMU_RETRAM_TypeDef; + +/** + * @brief Analog control register + */ + +typedef struct +{ + __IO uint32_t REG0; /*!< Analog control register 0, Address offset:0x00 */ + __IO uint32_t REG1; /*!< Analog control register 1, Address offset:0x04 */ + __IO uint32_t REG2; /*!< Analog control register 2, Address offset:0x08 */ + __IO uint32_t REG3; /*!< Analog control register 3, Address offset:0x0C */ + __IO uint32_t REG4; /*!< Analog control register 4, Address offset:0x10 */ + __IO uint32_t REG5; /*!< Analog control register 5, Address offset:0x14 */ + __IO uint32_t REG6; /*!< Analog control register 6, Address offset:0x18 */ + __IO uint32_t REG7; /*!< Analog control register 7, Address offset:0x1C */ + __IO uint32_t REG8; /*!< Analog control register 8, Address offset:0x20 */ + __IO uint32_t REG9; /*!< Analog control register 9, Address offset:0x24 */ + __IO uint32_t REGA; /*!< Analog control register 10, Address offset:0x28 */ + __IO uint32_t REGB; /*!< Analog control register 11, Address offset:0x2C */ + __IO uint32_t REGC; /*!< Analog control register 12, Address offset:0x30 */ + __IO uint32_t REGD; /*!< Analog control register 13, Address offset:0x34 */ + __IO uint32_t REGE; /*!< Analog control register 14, Address offset:0x38 */ + __IO uint32_t REGF; /*!< Analog control register 15, Address offset:0x3C */ +// __IO uint32_t REG10; /*!< Analog control register 16, Address offset:0x40 */ +// __IO uint32_t REG11; /*!< Analog control register 17, Address offset:0x44 */ +// __IO uint32_t REG12; /*!< Analog control register 18, Address offset:0x48 */ + uint32_t RESERVED1; /*!< Reserved, 0x40 */ + uint32_t RESERVED2; /*!< Reserved, 0x44 */ + uint32_t RESERVED3; /*!< Reserved, 0x48 */ + uint32_t RESERVED4; /*!< Reserved, 0x4C */ + __IO uint32_t CTRL; /*!< Analog misc. control register, Address offset:0x50 */ + __IO uint32_t COMPOUT; /*!< Comparator result register, Address offset:0x54 */ + //__IO uint32_t VERSION; /*!< Analog IP version register, Address offset:0x58 */ + //__IO uint32_t ADCSTATE; /*!< ADC State register, Address offset:0x5C */ + uint32_t RESERVED5; /*!< Reserved, */ + uint32_t RESERVED6; /*!< Reserved, */ + __IO uint32_t INTSTS; /*!< Analog interrupt status register, Address offset:0x60 */ + __IO uint32_t INTEN; /*!< Analog interrupt enable register, Address offset:0x64 */ + __IO uint32_t ADCCTRL; /*!< ADC control register, Address offset:0x68 */ + uint32_t RESERVED7; /*!< Reserved, 0x6C */ + __IO uint32_t ADCDATA0; /*!< ADC channel 0 data register, Address offset:0x70 */ + __IO uint32_t ADCDATA1; /*!< ADC channel 1 data register, Address offset:0x74 */ + __IO uint32_t ADCDATA2; /*!< ADC channel 2 data register, Address offset:0x78 */ + __IO uint32_t ADCDATA3; /*!< ADC channel 3 data register, Address offset:0x7C */ + __IO uint32_t ADCDATA4; /*!< ADC channel 4 data register, Address offset:0x80 */ + __IO uint32_t ADCDATA5; /*!< ADC channel 5 data register, Address offset:0x84 */ + __IO uint32_t ADCDATA6; /*!< ADC channel 6 data register, Address offset:0x88 */ + __IO uint32_t ADCDATA7; /*!< ADC channel 7 data register, Address offset:0x8C */ + __IO uint32_t ADCDATA8; /*!< ADC channel 8 data register, Address offset:0x90 */ + __IO uint32_t ADCDATA9; /*!< ADC channel 9 data register, Address offset:0x94 */ + __IO uint32_t ADCDATAA; /*!< ADC channel 10 data register, Address offset:0x98 */ + __IO uint32_t ADCDATAB; /*!< ADC channel 11 data register, Address offset:0x9C */ +// __IO uint32_t ADCDATAC; /*!< ADC channel 12 data register, Address offset:0xA0 */ +// __IO uint32_t ADCDATAD; /*!< ADC channel 13 data register, Address offset:0xA4 */ +// __IO uint32_t ADCDATAE; /*!< ADC channel 14 data register, Address offset:0xA8 */ +// __IO uint32_t ADCDATAF; /*!< ADC channel 15 data register, Address offset:0xAC */ + uint32_t RESERVED8; /*!< Reserved, 0xA0 */ + uint32_t RESERVED9; /*!< Reserved, 0xA4 */ + uint32_t RESERVED10; /*!< Reserved, 0xA8 */ + uint32_t RESERVED11; /*!< Reserved, 0xAC */ + __IO uint32_t CMPCNT1; /*!< Comparator 1 counter, Address offset:0xB0 */ + __IO uint32_t CMPCNT2; /*!< Comparator 2 counter, Address offset:0xB4 */ + __IO uint32_t MISC_A; /*!< MISC, Address offset:0xB8 */ +} ANA_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t SEC; /*!< RTC second register, Address offset: 0x00 */ + __IO uint32_t MIN; /*!< RTC minute register, Address offset: 0x04 */ + __IO uint32_t HOUR; /*!< RTC hour register, Address offset: 0x08 */ + __IO uint32_t DAY; /*!< RTC day register, Address offset: 0x0C */ + __IO uint32_t WEEK; /*!< RTC week-day register, Address offset: 0x10 */ + __IO uint32_t MON; /*!< RTC month register, Address offset: 0x14 */ + __IO uint32_t YEAR; /*!< RTC year register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUSEC; /*!< RTC wake-up second register, Address offset: 0x20 */ + __IO uint32_t WKUMIN; /*!< RTC wake-up minute register, Address offset: 0x24 */ + __IO uint32_t WKUHOUR; /*!< RTC wake-up hour register, Address offset: 0x28 */ + __IO uint32_t WKUCNT; /*!< RTC wake-up counter register, Address offset: 0x2C */ + __IO uint32_t CAL; /*!< RTC calibration register, Address offset: 0x30 */ + __IO uint32_t DIV; /*!< RTC PLL divider register, Address offset: 0x34 */ + __IO uint32_t CTL; /*!< RTC PLL divider control register, Address offset: 0x38 */ + uint32_t RESERVED2; + uint32_t RESERVED3; + //__IO uint32_t ITV; /*!< RTC wake-up interval control, Address offset: 0x3C */ + //__IO uint32_t SITV; /*!< RTC wake-up second interval control, Address offset: 0x40 */ + __IO uint32_t PWD; /*!< RTC password control register, Address offset: 0x44 */ + __IO uint32_t CE; /*!< RTC write enable control register, Address offset: 0x48 */ + __IO uint32_t LOAD; /*!< RTC read enable control register, Address offset: 0x4C */ + __IO uint32_t INTSTS; /*!< RTC interrupt status control register, Address offset: 0x50 */ + __IO uint32_t INTEN; /*!< RTC interrupt enable control register, Address offset: 0x54 */ + __IO uint32_t PSCA; /*!< RTC clock pre-scaler control register, Address offset: 0x58 */ + uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x5C-0x7C */ + __IO uint32_t ACCTRL; /*!< RTC auto-calibration control register, Address offset: 0x80 */ + __IO uint32_t ACTI; /*!< RTC auto-calibration center temperature control register, Address offset: 0x84 */ + __IO uint32_t ACF200; /*!< RTC auto-calibration 200*frequency control register, Address offset: 0x88 */ + __IO uint32_t ACADCW; /*!< RTC auto-calibration manual ADC value control register, Address offset: 0x8C */ + __IO uint32_t ACP0; /*!< RTC auto-calibration parameter 0 control register, Address offset: 0x90 */ + __IO uint32_t ACP1; /*!< RTC auto-calibration parameter 1 control register, Address offset: 0x94 */ + __IO uint32_t ACP2; /*!< RTC auto-calibration parameter 2 control register, Address offset: 0x98 */ + __IO uint32_t ACP3; /*!< RTC auto-calibration parameter 3 control register, Address offset: 0x9C */ + __IO uint32_t ACP4; /*!< RTC auto-calibration parameter 4 control register, Address offset: 0xA0 */ + __IO uint32_t ACP5; /*!< RTC auto-calibration parameter 5 control register, Address offset: 0xA4 */ + __IO uint32_t ACP6; /*!< RTC auto-calibration parameter 6 control register, Address offset: 0xA8 */ + __IO uint32_t ACP7; /*!< RTC auto-calibration parameter 7 control register, Address offset: 0xAC */ + __IO uint32_t ACK1; /*!< RTC auto-calibration parameter k1 control register, Address offset: 0xB0 */ + __IO uint32_t ACK2; /*!< RTC auto-calibration parameter k2 control register, Address offset: 0xB4 */ + __IO uint32_t ACK3; /*!< RTC auto-calibration parameter k3 control register, Address offset: 0xB8 */ + __IO uint32_t ACK4; /*!< RTC auto-calibration parameter k4 control register, Address offset: 0xBC */ + __IO uint32_t ACK5; /*!< RTC auto-calibration parameter k5 control register, Address offset: 0xC0 */ + __IO uint32_t ACTEMP; /*!< RTC auto-calibration calculated temperature register, Address offset: 0xC4 */ + __IO uint32_t ACPPM; /*!< RTC auto-calibration calculated PPM register, Address offset: 0xC8 */ + __IO uint32_t WKUCNTR; /*!< RTC current WKUCNT counter value read-out register., Address offset: 0xCC */ + __IO uint32_t ACKTEMP; /*!< RTC auto-calibration k temperature section control register,Address offset: 0xD0 */ + //uint32_t RESERVED37[128+15];/*!< Reserved, Address offset: 0xD4-0x3FC */ + //__IO uint32_t RTC_ACOP0_63[64]; /*!< RTC auto-calibration OP0-OP63 register (only for FPGA), Address offset: 0x400-0x4FC */ +} RTC_TypeDef; + +/** + * @brief FLASH + */ +typedef struct +{ + __IO uint32_t STS; /*!< , Address offset: 0x00 */ + __IO uint32_t NVRPASS; /*!< FLASH NVR sector password register, Address offset: 0x04 */ + __IO uint32_t BDPASS; /*!< FLASH Back door register, Address offset: 0x08 */ + __IO uint32_t KEY; /*!< FLASH key register, Address offset: 0x0C */ + __IO uint32_t INT; /*!< FLASH Checksum interrupt status, Address offset: 0x10 */ + __IO uint32_t CSSADDR; /*!< FLASH Checksum start address, Address offset: 0x14 */ + __IO uint32_t CSEADDR; /*!< FLASH Checksum end address, Address offset: 0x18 */ + __IO uint32_t CSVALUE; /*!< FLASH Checksum value register, Address offset: 0x1C */ + __IO uint32_t CSCVALUE; /*!< FLASH Checksum compare value register, Address offset: 0x20 */ + __IO uint32_t PASS; /*!< FLASH password register, Address offset: 0x24 */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x28 */ + __IO uint32_t PGADDR; /*!< FLASH program address register, Address offset: 0x2C */ + __IO uint32_t PGDATA; /*!< FLASH program word data register, Address offset: 0x30 */ + __IO uint32_t CONF; /*!< FLASH configuration read/write register, Address offset: 0x34 */ + __IO uint32_t SERASE; /*!< FLASH sector erase control register, Address offset: 0x38 */ + __IO uint32_t CERASE; /*!< FLASH chip erase control register, Address offset: 0x3C */ + __IO uint32_t DSTB; /*!< FLASH deep standby control register, Address offset: 0x40 */ +} FLASH_TypeDef; + + +/** + * @brief General Purpose IO (GPIOB~GPIOF) + */ + +typedef struct +{ + __IO uint32_t OEN; /*!< IOx output enable register, Address offset: 0x00 */ + __IO uint32_t IE; /*!< IOx input enable register, Address offset: 0x04 */ + __IO uint32_t DAT; /*!< IOx data register, Address offset: 0x08 */ + __IO uint32_t ATT; /*!< IOx attribute register, Address offset: 0x0C */ + __IO uint32_t STS; /*!< IOx input status register, Address offset: 0x10 */ +}GPIO_TypeDef; + +/** + * @brief General Purpose IO (GPIOA) + */ +typedef struct +{ + __IO uint32_t OEN; + __IO uint32_t IE; + __IO uint32_t DAT; + __IO uint32_t ATT; + __IO uint32_t WKUEN; + __IO uint32_t STS; + __IO uint32_t INT; + uint32_t RESERVED1; + uint32_t RESERVED2; + uint32_t RESERVED3; + __IO uint32_t SEL; + uint32_t RESERVED[5]; + __IO uint32_t IOANODEG; +} GPIOA_TypeDef; + +/** + * @brief General Purpose IO special function + */ + +typedef struct +{ + __IO uint32_t SELB; /*!< IOB special function select register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved, 0x04 */ + uint32_t RESERVED2; /*!< Reserved, 0x08 */ + __IO uint32_t SELE; /*!< IOE special function select register, Address offset: 0x0C */ + uint32_t RESERVED3; /*!< Reserved, 0x10 */ + uint32_t RESERVED4; /*!< Reserved, 0x14 */ + uint32_t RESERVED5; /*!< Reserved, 0x18 */ + uint32_t RESERVED6; /*!< Reserved, 0x1C */ + __IO uint32_t _MISC; /*!< IO misc control register, Address offset: 0x20 */ +}GPIO_AF_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t IE; /*!< DMA interrupt enable register, Address offset:0x00 */ + __IO uint32_t STS; /*!< DMA status register, Address offset:0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t C0CTL; /*!< DMA channel 0 control register, Address offset:0x10 */ + __IO uint32_t C0SRC; /*!< DMA channel 0 source register, Address offset:0x14 */ + __IO uint32_t C0DST; /*!< DMA channel 0 destination register, Address offset:0x18 */ + __IO uint32_t C0LEN; /*!< DMA channel 0 transfer length register, Address offset:0x1C */ + __IO uint32_t C1CTL; /*!< DMA channel 1 control register, Address offset:0x20 */ + __IO uint32_t C1SRC; /*!< DMA channel 1 source register, Address offset:0x24 */ + __IO uint32_t C1DST; /*!< DMA channel 1 destination register, Address offset:0x28 */ + __IO uint32_t C1LEN; /*!< DMA channel 1 transfer length register, Address offset:0x2C */ + __IO uint32_t C2CTL; /*!< DMA channel 2 control register, Address offset:0x30 */ + __IO uint32_t C2SRC; /*!< DMA channel 2 source register, Address offset:0x34 */ + __IO uint32_t C2DST; /*!< DMA channel 2 destination register, Address offset:0x38 */ + __IO uint32_t C2LEN; /*!< DMA channel 2 transfer length register, Address offset:0x3C */ + __IO uint32_t C3CTL; /*!< DMA channel 3 control register, Address offset:0x40 */ + __IO uint32_t C3SRC; /*!< DMA channel 3 source register, Address offset:0x44 */ + __IO uint32_t C3DST; /*!< DMA channel 3 destination register, Address offset:0x48 */ + __IO uint32_t C3LEN; /*!< DMA channel 3 transfer length register, Address offset:0x4C */ + __IO uint32_t AESCTL; /*!< DMA AES control register, Address offset:0x50 */ + uint32_t RESERVED3[3]; /*!< Reserved, 0x54-0x5C */ + __IO uint32_t AESKEY0; /*!< DMA AES key 0 register, Address offset:0x60 */ + __IO uint32_t AESKEY1; /*!< DMA AES key 1 register, Address offset:0x64 */ + __IO uint32_t AESKEY2; /*!< DMA AES key 2 register, Address offset:0x68 */ + __IO uint32_t AESKEY3; /*!< DMA AES key 3 register, Address offset:0x6C */ + __IO uint32_t AESKEY4; /*!< DMA AES key 4 register, Address offset:0x70 */ + __IO uint32_t AESKEY5; /*!< DMA AES key 5 register, Address offset:0x74 */ + __IO uint32_t AESKEY6; /*!< DMA AES key 6 register, Address offset:0x78 */ + __IO uint32_t AESKEY7; /*!< DMA AES key 7 register, Address offset:0x7C */ +} DMA_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t DATA; /*!< UARTx data register, Address offset: 0x00 */ + __IO uint32_t STATE; /*!< UARTx status register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< UARTx control register, Address offset: 0x08 */ + __IO uint32_t INTSTS; /*!< UARTx interrupt status register, Address offset: 0x0C */ + __IO uint32_t BAUDDIV; /*!< UARTx baud rate divide register, Address offset: 0x10 */ + __IO uint32_t CTRL2; /*!< UARTx control register 2, Address offset: 0x14 */ +} UART_TypeDef; + +/** + * @brief UART 32K Controller + */ +typedef struct +{ + __IO uint32_t CTRL0; /*!< UART 32K x control register 0, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< UART 32K x control register 1, Address offset: 0x04 */ + __IO uint32_t PHASE; /*!< UART 32K x baud rate control register, Address offset: 0x08 */ + __IO uint32_t DATA; /*!< UART 32K x receive data buffer, Address offset: 0x0C */ + __IO uint32_t STS; /*!< UART 32K x interrupt status register, Address offset: 0x10 */ +} U32K_TypeDef; + +/** + * @brief ISO7816 Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, 0x00 */ + __IO uint32_t BAUDDIVL; /*!< ISO7816 x baud-rate low byte register, Address offset: 0x04 */ + __IO uint32_t BAUDDIVH; /*!< ISO7816 x baud-rate high byte register, Address offset: 0x08 */ + __IO uint32_t DATA; /*!< ISO7816 x data register, Address offset: 0x0C */ + __IO uint32_t INFO; /*!< ISO7816 x information register, Address offset: 0x10 */ + __IO uint32_t CFG; /*!< ISO7816 x control register, Address offset: 0x14 */ + __IO uint32_t CLK; /*!< ISO7816 x clock divider register, Address offset: 0x1C */ +} ISO7816_TypeDef; + +/** + * @brief Timer Controller + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Timer x��s control register, Address offset: 0x00 */ + __IO uint32_t VALUE; /*!< Timer x��s current count register, Address offset: 0x04 */ + __IO uint32_t RELOAD; /*!< Timer x��s reload register, Address offset: 0x08 */ + __IO uint32_t INT; /*!< Timer x��s interrupt status register, Address offset: 0x0C */ +} TMR_TypeDef; + +/** + * @brief PWM Controller + */ +typedef struct +{ + __IO uint32_t CTL; /*!< PWM Timer x��s control register, Address offset: 0x00 */ + __IO uint32_t TAR; /*!< PWM Timer x��s current count register, Address offset: 0x04 */ + __IO uint32_t CCTL0; /*!< PWM Timer x��s compare/capture control register 0, Address offset: 0x08 */ + __IO uint32_t CCTL1; /*!< PWM Timer x��s compare/capture control register 1, Address offset: 0x0C */ + __IO uint32_t CCTL2; /*!< PWM Timer x��s compare/capture control register 2, Address offset: 0x10 */ + __IO uint32_t CCR0; /*!< PWM Timer x��s compare/capture data register 0, Address offset: 0x14 */ + __IO uint32_t CCR1; /*!< PWM Timer x��s compare/capture data register 1, Address offset: 0x18 */ + __IO uint32_t CCR2; /*!< PWM Timer x��s compare/capture data register 2, Address offset: 0x1C */ +} PWM_TypeDef; + +/** + * @brief PWMx selection register + */ +typedef struct +{ + __IO uint32_t OSEL; /*!< PWM output selection register, Address offset: 0x00 */ +// __IO uint32_t ISEL01; /*!< PWM0 and PWM1��s input selection register, Address offset: 0x04 */ +// __IO uint32_t ISEL23; /*!< PWM2 and PWM3��s input selection register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< RESERVED0, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x08 */ +} PWM_MUX_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t FB[40]; /*!< LCD Frame buffer 0~39 register, Address offset: 0x00-0x9C */ + uint32_t RESERVED1[24]; /*!< Reserved, 0xA0-0xFC */ + __IO uint32_t CTRL; /*!< LCD control register, Address offset: 0x100 */ + __IO uint32_t CTRL2; /*!< LCD control register 2, Address offset: 0x104 */ + __IO uint32_t SEGCTRL0; /*!< LCD segment enable control register 0, Address offset: 0x108 */ + __IO uint32_t SEGCTRL1; /*!< LCD segment enable control register 1, Address offset: 0x10C */ + __IO uint32_t SEGCTRL2; /*!< LCD segment enable control register 2, Address offset: 0x110 */ +}LCD_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< SPI x Control Register, Address offset: 0x00 */ + __IO uint32_t TXSTS; /*!< SPI x Transmit Status Register, Address offset: 0x04 */ + __IO uint32_t TXDAT; /*!< SPI x Transmit FIFO register, Address offset: 0x08 */ + __IO uint32_t RXSTS; /*!< SPI x Receive Status Register, Address offset: 0x0C */ + __IO uint32_t RXDAT; /*!< SPI x Receive FIFO Register, Address offset: 0x10 */ + __IO uint32_t MISC_; /*!< SPI x Misc Control Register, Address offset: 0x14 */ +} SPI_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t DATA; /*!< I2C data register, Address offset: 0x00 */ + __IO uint32_t ADDR; /*!< I2C address register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< I2C control/status register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< I2C status register, Address offset: 0x0C */ + uint32_t RESERVED1; /*!< Reserved, 0x10 */ + uint32_t RESERVED2; /*!< Reserved, 0x14 */ + __IO uint32_t CTRL2; /*!< I2C interrupt enable register, Address offset: 0x18 */ +}I2C_TypeDef; + +/** + * @brief MISC Controller + */ +typedef struct +{ + __IO uint32_t SRAMINT; /*!< SRAM Parity Error Interrupt, Address offset: 0x00 */ + __IO uint32_t SRAMINIT; /*!< SRAM initialize register, Address offset: 0x04 */ + __IO uint32_t PARERR; /*!< SRAM Parity Error address register, Address offset: 0x08 */ + __IO uint32_t IREN; /*!< IR enable control register, Address offset: 0x0C */ + __IO uint32_t DUTYL; /*!< IR Duty low pulse control register, Address offset: 0x10 */ + __IO uint32_t DUTYH; /*!< IR Duty high pulse control register, Address offset: 0x14 */ + __IO uint32_t IRQLAT; /*!< Cortex M0 IRQ latency control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t HIADDR; /*!< AHB invalid access address, Address offset: 0x20 */ + __IO uint32_t PIADDR; /*!< APB invalid access address, Address offset: 0x24 */ +} MISC_TypeDef; + +/** + * @brief MISC2 Controller + */ +typedef struct +{ + __IO uint32_t FLASHWC; /*!< Flash wait cycle register, Address offset: 0x00 */ + __IO uint32_t CLKSEL; /*!< Clock selection register, Address offset: 0x04 */ + __IO uint32_t CLKDIVH; /*!< AHB clock divider control register, Address offset: 0x08 */ + __IO uint32_t CLKDIVP; /*!< APB clock divider control register, Address offset: 0x0C */ + __IO uint32_t HCLKEN; /*!< AHB clock enanle control register, Address offset: 0x10 */ + __IO uint32_t PCLKEN; /*!< APB clock enanle control register, Address offset: 0x14 */ +} MISC2_TypeDef; + +/** + * @brief CRYPT Controller + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< CRYPT control register, Address offset: 0x00 */ + __IO uint32_t PTRA; /*!< CRYPT pointer A, Address offset: 0x04 */ + __IO uint32_t PTRB; /*!< CRYPT pointer B, Address offset: 0x08 */ + __IO uint32_t PTRO; /*!< CRYPT pointer O, Address offset: 0x0C */ + __IO uint32_t CARRY; /*!< CRYPT carry/borrow bit register, Address offset: 0x10 */ +} CRYPT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x00000000U) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0003FFFFU) /*!< FLASH END address of bank1 */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ + +/*!< Peripheral memory map */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00000000U) +#define APBPERIPH_BASE (PERIPH_BASE + 0x00010000U) + +/*!< FLASH */ +#define FLASHSFR_BASE (FLASH_BASE + 0x000FFFBC) + +/*!< AHB peripherals */ +#define GPIO_BASE (AHBPERIPH_BASE + 0x00000000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000020) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000040) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000060) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00000080) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x000000A0) +#define GPIOAF_BASE (AHBPERIPH_BASE + 0x000000C0) +#define LCD_BASE (AHBPERIPH_BASE + 0x00002000) +#define CRYPT_BASE (AHBPERIPH_BASE + 0x00006000) + +/*!< APB peripherals */ +#define DMA_BASE (APBPERIPH_BASE + 0x00000000) +#define I2C_BASE (APBPERIPH_BASE + 0x00000800) +#define SPI1_BASE (APBPERIPH_BASE + 0x00001000) +#define UART0_BASE (APBPERIPH_BASE + 0x00001800) +#define UART1_BASE (APBPERIPH_BASE + 0x00001820) +#define UART2_BASE (APBPERIPH_BASE + 0x00001840) +#define UART3_BASE (APBPERIPH_BASE + 0x00001860) +#define UART4_BASE (APBPERIPH_BASE + 0x00001880) +#define UART5_BASE (APBPERIPH_BASE + 0x000018A0) +#define ISO78160_BASE (APBPERIPH_BASE + 0x00002000) +#define ISO78161_BASE (APBPERIPH_BASE + 0x00002040) +#define TMR0_BASE (APBPERIPH_BASE + 0x00002800) +#define TMR1_BASE (APBPERIPH_BASE + 0x00002820) +#define TMR2_BASE (APBPERIPH_BASE + 0x00002840) +#define TMR3_BASE (APBPERIPH_BASE + 0x00002860) +#define PWM0_BASE (APBPERIPH_BASE + 0x00002900) +#define PWM1_BASE (APBPERIPH_BASE + 0x00002920) +#define PWM2_BASE (APBPERIPH_BASE + 0x00002940) +#define PWM3_BASE (APBPERIPH_BASE + 0x00002960) +#define PWMMUX_BASE (APBPERIPH_BASE + 0x000029F0) +#define MISC_BASE (APBPERIPH_BASE + 0x00003000) +#define MISC2_BASE (APBPERIPH_BASE + 0x00003E00) +#define PMU_BASE (APBPERIPH_BASE + 0x00004000) +#define GPIOA_BASE (APBPERIPH_BASE + 0x00004010) +#define PMU_RETRAM_BASE (APBPERIPH_BASE + 0x00004400) +#define U32K0_BASE (APBPERIPH_BASE + 0x00004100) +#define U32K1_BASE (APBPERIPH_BASE + 0x00004180) +#define ANA_BASE (APBPERIPH_BASE + 0x00004200) +#define RETRAM_BASE (APBPERIPH_BASE + 0x00004400) +#define RTC_BASE (APBPERIPH_BASE + 0x00004800) +#define SPI2_BASE (APBPERIPH_BASE + 0x00005800) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define PMU ((PMU_TypeDef *) PMU_BASE) +#define PMU_RETRAM ((PMU_RETRAM_TypeDef *) PMU_RETRAM_BASE) +#define ANA ((ANA_TypeDef *) ANA_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASHSFR_BASE) +#define GPIOA ((GPIOA_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOAF ((GPIO_AF_TypeDef *) GPIOAF_BASE) +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define UART3 ((UART_TypeDef *) UART3_BASE) +#define UART4 ((UART_TypeDef *) UART4_BASE) +#define UART5 ((UART_TypeDef *) UART5_BASE) +#define U32K0 ((U32K_TypeDef *) U32K0_BASE) +#define U32K1 ((U32K_TypeDef *) U32K1_BASE) +#define ISO78160 ((ISO7816_TypeDef *) ISO78160_BASE) +#define ISO78161 ((ISO7816_TypeDef *) ISO78161_BASE) +#define TMR0 ((TMR_TypeDef *) TMR0_BASE) +#define TMR1 ((TMR_TypeDef *) TMR1_BASE) +#define TMR2 ((TMR_TypeDef *) TMR2_BASE) +#define TMR3 ((TMR_TypeDef *) TMR3_BASE) +#define PWM0 ((PWM_TypeDef *) PWM0_BASE) +#define PWM1 ((PWM_TypeDef *) PWM1_BASE) +#define PWM2 ((PWM_TypeDef *) PWM2_BASE) +#define PWM3 ((PWM_TypeDef *) PWM3_BASE) +#define PWMMUX ((PWM_MUX_TypeDef *) PWMMUX_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define I2C ((I2C_TypeDef *) I2C_BASE) +#define MISC ((MISC_TypeDef *) MISC_BASE) +#define MISC2 ((MISC2_TypeDef *) MISC2_BASE) +#define CRYPT ((CRYPT_TypeDef *) CRYPT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Power Management Unit (PMU) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for PMU_DSLEEPEN register ******************/ +#define PMU_DSLEEPEN_DSLEEP_Pos (0U) +#define PMU_DSLEEPEN_DSLEEP_Msk (0x1U << PMU_DSLEEPEN_DSLEEP_Pos) /*!< 0x00000001 */ +#define PMU_DSLEEPEN_DSLEEP PMU_DSLEEPEN_DSLEEP_Msk /*!< This bit indicates the deep-sleep mode has been entry */ +#define PMU_DSLEEPEN_WKU_Pos (31U) +#define PMU_DSLEEPEN_WKU_Msk (0x1U << PMU_DSLEEPEN_WKU_Pos) /*!< 0x80000000 */ +#define PMU_DSLEEPEN_WKU PMU_DSLEEPEN_WKU_Msk /*!< Current wake-up signal status, this bit reflect the wake-up status receive by PMU controller */ + +/************** Bits definition for PMU_DSLEEPPASS register ******************/ +#define PMU_DSLEEPPASS_UNLOCK_Pos (0U) +#define PMU_DSLEEPPASS_UNLOCK_Msk (0x1U << PMU_DSLEEPPASS_UNLOCK_Pos) /*!< 0x00000001 */ +#define PMU_DSLEEPPASS_UNLOCK PMU_DSLEEPPASS_UNLOCK_Msk /*!< This bit indicates the entry of deep-sleep mode has been unlocked and is ready to entry deep-sleep mode */ + +/************** Bits definition for PMU_CONTROL register ******************/ +#define PMU_CONTROL_INT_IOA_EN_Pos (0U) +#define PMU_CONTROL_INT_IOA_EN_Msk (0x1U << PMU_CONTROL_INT_IOA_EN_Pos) /*!< 0x00000001 */ +#define PMU_CONTROL_INT_IOA_EN PMU_CONTROL_INT_IOA_EN_Msk /*!< PMU��s interrupt enable register. This bit is used to control the interrupt signal output to CPU */ +#define PMU_CONTROL_RTCLK_SEL_Pos (1U) +#define PMU_CONTROL_RTCLK_SEL_Msk (0x1U << PMU_CONTROL_RTCLK_SEL_Pos) /*!< 0x00000002 */ +#define PMU_CONTROL_RTCLK_SEL PMU_CONTROL_RTCLK_SEL_Msk /*!< RTC Clock selection */ +#define PMU_CONTROL_INT_32K_EN_Pos (2U) +#define PMU_CONTROL_INT_32K_EN_Msk (0x1U << PMU_CONTROL_INT_32K_EN_Pos) /*!< 0x00000004 */ +#define PMU_CONTROL_INT_32K_EN PMU_CONTROL_INT_32K_EN_Msk /*!< 32K XTAL absent interrupt enable register. This bit is used to control the interrupt signal output to CPU */ +#define PMU_CONTROL_INT_6M_EN_Pos (3U) +#define PMU_CONTROL_INT_6M_EN_Msk (0x1U << PMU_CONTROL_INT_6M_EN_Pos) /*!< 0x00000008 */ +#define PMU_CONTROL_INT_6M_EN PMU_CONTROL_INT_6M_EN_Msk /*!< 6.5536M XTAL absent interrupt enable register */ +#define PMU_CONTROL_PLLH_SEL_Pos (4U) +#define PMU_CONTROL_PLLH_SEL_Msk (0x1U << PMU_CONTROL_PLLH_SEL_Pos) /*!< 0x00000010 */ +#define PMU_CONTROL_PLLH_SEL PMU_CONTROL_PLLH_SEL_Msk /*!< High speed PLL input clock selection */ +#define PMU_CONTROL_PLLL_SEL_Pos (5U) +#define PMU_CONTROL_PLLL_SEL_Msk (0x1U << PMU_CONTROL_PLLL_SEL_Pos) /*!< 0x00000020 */ +#define PMU_CONTROL_PLLL_SEL PMU_CONTROL_PLLL_SEL_Msk /*!< Low speed PLL input clock selection */ +//#define PMU_CONTROL_PD_WKUEN_Pos (6U) +//#define PMU_CONTROL_PD_WKUEN_Msk (0x1U << PMU_CONTROL_PD_WKUEN_Pos) /*!< 0x00000040 */ +//#define PMU_CONTROL_PD_WKUEN PMU_CONTROL_PD_WKUEN_Msk /*!< Wake-up enable/disable when main power is off */ +//#define PMU_CONTROL_PWUPCYC_Pos (8U) +//#define PMU_CONTROL_PWUPCYC_Msk (0xFFU << PMU_CONTROL_PWUPCYC_Pos) /*!< 0x0000FF00 */ +//#define PMU_CONTROL_PWUPCYC PMU_CONTROL_PWUPCYC_Msk /*!< Power-up cycle count, this register control the power-up wait time when a wake-up even is received. The unit is 32K clock period */ +//#define PMU_CONTROL_NOWAITLOCK_Pos (17U) +//#define PMU_CONTROL_NOWAITLOCK_Msk (0x1U << PMU_CONTROL_NOWAITLOCK_Pos) /*!< 0x00020000 */ +//#define PMU_CONTROL_NOWAITLOCK PMU_CONTROL_NOWAITLOCK_Msk /*!< if the hardware will wait for PLLL��s lock signal when switch clock source to PLLL/PLLH */ + +/************** Bits definition for PMU_STS register ******************/ +#define PMU_STS_INT_32K_Pos (0U) +#define PMU_STS_INT_32K_Msk (0x1U << PMU_STS_INT_32K_Pos) /*!< 0x00000001 */ +#define PMU_STS_INT_32K PMU_STS_INT_32K_Msk /*!< This bit represents the 32K crystal absent interrupt status. When this bit is set to 1, it means the 32K crystal is removed or broken. Write 1 to this bit can clear this flag to 0 */ +#define PMU_STS_INT_6M_Pos (1U) +#define PMU_STS_INT_6M_Msk (0x1U << PMU_STS_INT_6M_Pos) /*!< 0x00000002 */ +#define PMU_STS_INT_6M PMU_STS_INT_6M_Msk /*!< This bit represents the 6.55364M crystal absent interrupt status. When this bit is set to 1, it means the 6.55364M crystal is removed or broken. Write 1 to this bit can clear this flag to 0 */ +#define PMU_STS_EXIST_32K_Pos (2U) +#define PMU_STS_EXIST_32K_Msk (0x1U << PMU_STS_EXIST_32K_Pos) /*!< 0x00000004 */ +#define PMU_STS_EXIST_32K PMU_STS_EXIST_32K_Msk /*!< 32K XTAL exist status register. This bit is represent 32K XTAL is existed or absent */ +#define PMU_STS_EXIST_6M_Pos (3U) +#define PMU_STS_EXIST_6M_Msk (0x1U << PMU_STS_EXIST_6M_Pos) /*!< 0x00000008 */ +#define PMU_STS_EXIST_6M PMU_STS_EXIST_6M_Msk /*!< 6.5536M XTAL exist status register. This bit is represent 6.5536M XTAL is existed or absent */ +#define PMU_STS_EXTRST_Pos (4U) +#define PMU_STS_EXTRST_Msk (0x1U << PMU_STS_EXTRST_Pos) /*!< 0x00000010 */ +#define PMU_STS_EXTRST PMU_STS_EXTRST_Msk /*!< This bit indicated if the last interrupt is cause by external reset signal. Write 1 to clear this bit */ +#define PMU_STS_PORST_Pos (5U) +#define PMU_STS_PORST_Msk (0x1U << PMU_STS_PORST_Pos) /*!< 0x00000020 */ +#define PMU_STS_PORST PMU_STS_PORST_Msk /*!< This bit indicated if the last reset is cause by internal power-on reset signal. Write 1 to clear this bit */ +#define PMU_STS_DPORST_Pos (6U) +#define PMU_STS_DPORST_Msk (0x1U << PMU_STS_DPORST_Pos) /*!< 0x00000040 */ +#define PMU_STS_DPORST PMU_STS_DPORST_Msk /*!< This bit indicated if the last reset is cause by internal digital power-on reset signal. Write 1 to clear this bit */ +#define PMU_STS_MODE_Pos (24U) +#define PMU_STS_MODE_Msk (0x1U << PMU_STS_MODE_Pos) /*!< 0x01000000 */ +#define PMU_STS_MODE PMU_STS_MODE_Msk /*!< This register shows the current status of MODE pin */ + +/************** Bits definition for PMU_IOAOEN register ******************/ +#define PMU_IOAOEN_Pos (0U) +#define PMU_IOAOEN_Msk (0xFFFFU << PMU_IOAOEN_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAOEN_IOAOEN PMU_IOAOEN_Msk /*!< Each bit control the IOA��s output enable signal */ + +/************** Bits definition for PMU_IOAIE register ******************/ +#define PMU_IOAIE_Pos (0U) +#define PMU_IOAIE_Msk (0xFFFFU << PMU_IOAIE_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAIE_IOAIE PMU_IOAIE_Msk /*!< Each bit control the IOA��s input enable signal */ + +/************** Bits definition for PMU_IOADAT register ******************/ +#define PMU_IOADAT_Pos (0U) +#define PMU_IOADAT_Msk (0xFFFFU << PMU_IOADAT_Pos) /*!< 0x0000FFFF */ +#define PMU_IOADAT_IOADAT PMU_IOADAT_Msk /*!< Each bit control the IOA��s output data and pull low/high function */ + +/************** Bits definition for PMU_IOAATT register ******************/ +#define PMU_IOAATT_Pos (0U) +#define PMU_IOAATT_Msk (0xFFFFU << PMU_IOAATT_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAATT_IOAATT PMU_IOAATT_Msk /*!< Each bit control the IOA��s attribute and pull low/high function */ + +/************** Bits definition for PMU_IOAWKUEN register ******************/ +#define PMU_IOAWKUEN_Pos (0U) +#define PMU_IOAWKUEN_Msk (0xFFFFFFFFU << PMU_IOAWKUEN_Pos) /*!< 0xFFFFFFFF */ +#define PMU_IOAWKUEN_IOAWKUEN PMU_IOAWKUEN_Msk /*!< Every 2 bits control the IOA��s wake up function */ + +/************** Bits definition for PMU_IOASTS register ******************/ +#define PMU_IOASTS_Pos (0U) +#define PMU_IOASTS_Msk (0xFFFFU << PMU_IOASTS_Pos) /*!< 0x0000FFFF */ +#define PMU_IOASTS_IOASTS PMU_IOASTS_Msk /*!< Each bit represents the current IOA��s input data value */ + +/************** Bits definition for PMU_IOAINT register ******************/ +#define PMU_IOAINT_Pos (0U) +#define PMU_IOAINT_Msk (0xFFFFU << PMU_IOAINT_Pos) /*!< 0x0000FFFF */ +#define PMU_IOAINT_IOAINT PMU_IOAINT_Msk /*!< Each bit represents the IOA��s interrupt status. The corresponded bit will be set to 1 when corresponded wake-up event is detected. This register can be clear to 0 by writing corresponded bit to 1 */ + +/************** Bits definition for PMU_IOADR register ******************/ +#define PMU_IOADR_IOA0DR_Pos (0U) +#define PMU_IOADR_IOA0DR_Msk (0x1U << PMU_IOADR_IOA0DR_Pos) /*!< 0x00000001 */ +#define PMU_IOADR_IOA0DR PMU_IOADR_IOA0DR_Msk /*!< IOA0��s driving strength setting, change to this register will change all setting of IOA0~IOA15 */ +#define PMU_IOADR_IOAXDR_Pos (1U) +#define PMU_IOADR_IOAXDR_Msk (0x7FFFU << PMU_IOADR_IOAXDR_Pos) /*!< 0x0000FFFE */ +#define PMU_IOADR_IOAXDR PMU_IOADR_IOAXDR_Msk /*!< Each bit represent the current driving strength setting of IOA1~IOA15 */ + +/************** Bits definition for PMU_IOASEL register ******************/ +#define PMU_IOASEL_SEL3_Pos (3U) +#define PMU_IOASEL_SEL3_Msk (0x1U << PMU_IOASEL_SEL3_Pos) /*!< 0x00000008 */ +#define PMU_IOASEL_SEL3 PMU_IOASEL_SEL3_Msk /*!< IOA3 special function select register */ +#define PMU_IOASEL_SEL6_Pos (6U) +#define PMU_IOASEL_SEL6_Msk (0x1U << PMU_IOASEL_SEL6_Pos) /*!< 0x00000040 */ +#define PMU_IOASEL_SEL6 PMU_IOASEL_SEL6_Msk /*!< IOA6 special function select register */ +#define PMU_IOASEL_SEL7_Pos (7U) +#define PMU_IOASEL_SEL7_Msk (0x1U << PMU_IOASEL_SEL7_Pos) /*!< 0x00000080 */ +#define PMU_IOASEL_SEL7 PMU_IOASEL_SEL7_Msk /*!< IOA7 special function select register */ + +/************** Bits definition for PMU_WDTPASS register ******************/ +#define PMU_WDTPASS_UNLOCK_Pos (0U) +#define PMU_WDTPASS_UNLOCK_Msk (0x1U << PMU_WDTPASS_UNLOCK_Pos) /*!< 0x00000001 */ +#define PMU_WDTPASS_UNLOCK PMU_WDTPASS_UNLOCK_Msk /*!< This bit indicates the watch dog timer enable register has been unlocked and is ready to change the watch dog enable control register */ + +/************** Bits definition for PMU_WDTEN register ******************/ +#define PMU_WDTEN_WDTEN_Pos (0U) +#define PMU_WDTEN_WDTEN_Msk (0x1U << PMU_WDTEN_WDTEN_Pos) /*!< 0x00000001 */ +#define PMU_WDTEN_WDTEN PMU_WDTEN_WDTEN_Msk /*!< This bit indicates the watch dog timer is enable. To change the value of this register, UNLOCK bit of MISC_WDTPASS should be set to 1 first */ +#define PMU_WDTEN_WDTSEL_Pos (2U) +#define PMU_WDTEN_WDTSEL_Msk (0x3U << PMU_WDTEN_WDTSEL_Pos) /*!< 0x0000000C */ +#define PMU_WDTEN_WDTSEL PMU_WDTEN_WDTSEL_Msk /*!< This register is used to control the WDT counting period */ +#define PMU_WDTEN_WDTSEL_0 (0x0U << PMU_WDTEN_WDTSEL_Pos) +#define PMU_WDTEN_WDTSEL_1 (0x1U << PMU_WDTEN_WDTSEL_Pos) +#define PMU_WDTEN_WDTSEL_2 (0x2U << PMU_WDTEN_WDTSEL_Pos) +#define PMU_WDTEN_WDTSEL_3 (0x3U << PMU_WDTEN_WDTSEL_Pos) + + +/************** Bits definition for PMU_WDTCLR register ******************/ +#define PMU_WDTCLR_WDTCNT_Pos (0U) +#define PMU_WDTCLR_WDTCNT_Msk (0xFFFFU << PMU_WDTCLR_WDTCNT_Pos) /*!< 0x0000FFFF */ +#define PMU_WDTCLR_WDTCNT PMU_WDTCLR_WDTCNT_Msk /*!< This register shows the current counter value of wat dog timer. When this timer count to limit value set by WDTSEL, the WDT will issue a system reset */ + +/************** Bits definition for PMU_WDTSTS register ******************/ +//#define PMU_WDTSTS_WDTSTS_Pos (0U) +//#define PMU_WDTSTS_WDTSTS_Msk (0x1U << PMU_WDTSTS_WDTSTS_Pos) /*!< 0x00000001 */ +//#define PMU_WDTSTS_WDTSTS PMU_WDTSTS_WDTSTS_Msk /*!< This register indicates that a WDT reset has happened. Programmer can read this bit to know if this time is the WDT reset. Write 1 to this bit can clear this flag */ + +/******************************************************************************/ +/* */ +/* Embedded 256 Bytes Retention SRAM (PMU_RAM) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for PMU_RAMx register ******************/ +#define PMU_RAM_RAM_Pos (0U) +#define PMU_RAM_RAM_Msk (0xFFFFFFFFU << PMU_RAM_RAM_Pos) /*!< 0xFFFFFFFF */ +#define PMU_RAM_RAM PMU_RAM_RAM_Msk /*!< There is a 256 bytes (64x32) SRAM embedded in the PMU controller. This RAM can keep data during deep-sleep mode. Only word access is allowed to these ports */ + +/******************************************************************************/ +/* */ +/* Analog controller (ANA) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for ANA_REG0 register ******************/ +//#define ANA_REG0_CURRIT_Pos (0U) +//#define ANA_REG0_CURRIT_Msk (0x3U << ANA_REG0_CURRIT_Pos) /*!< 0x00000003 */ +//#define ANA_REG0_CURRIT ANA_REG0_CURRIT_Msk /*!< ADC overall bias current trim */ +//#define ANA_REG0_CURRIT_0 (0x0U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_CURRIT_1 (0x1U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_CURRIT_2 (0x2U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_CURRIT_3 (0x3U << ANA_REG0_CURRIT_Pos) +//#define ANA_REG0_ADIT1_Pos (2U) +//#define ANA_REG0_ADIT1_Msk (0x3U << ANA_REG0_ADIT1_Pos) /*!< 0x0000000C */ +//#define ANA_REG0_ADIT1 ANA_REG0_ADIT1_Msk /*!< Current trim for 1st stage of ADC */ +//#define ANA_REG0_ADIT1_0 (0x0U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT1_1 (0x1U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT1_2 (0x2U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT1_3 (0x3U << ANA_REG0_ADIT1_Pos) +//#define ANA_REG0_ADIT2_Pos (4U) +//#define ANA_REG0_ADIT2_Msk (0x3U << ANA_REG0_ADIT2_Pos) /*!< 0x00000030 */ +//#define ANA_REG0_ADIT2 ANA_REG0_ADIT2_Msk /*!< Current trim for 2st stage of ADC */ +//#define ANA_REG0_ADIT2_0 (0x0U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_ADIT2_1 (0x1U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_ADIT2_2 (0x2U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_ADIT2_3 (0x3U << ANA_REG0_ADIT2_Pos) +//#define ANA_REG0_REFBIT_Pos (6U) +//#define ANA_REG0_REFBIT_Msk (0x1U << ANA_REG0_REFBIT_Pos) /*!< 0x00000040 */ +//#define ANA_REG0_REFBIT ANA_REG0_REFBIT_Msk /*!< Current trim for ADC ref buffer */ +//#define ANA_REG0_ADQIT_Pos (7U) +//#define ANA_REG0_ADQIT_Msk (0x1U << ANA_REG0_ADQIT_Pos) /*!< 0x00000080 */ +//#define ANA_REG0_ADQIT ANA_REG0_ADQIT_Msk /*!< Current trim for ADC CMP */ + +/************** Bits definition for ANA_REG1 register ******************/ +//#define ANA_REG1_ADC_SEL_Pos (0U) +//#define ANA_REG1_ADC_SEL_Msk (0xFU << ANA_REG1_ADC_SEL_Pos) /*!< 0x0000000F */ +//#define ANA_REG1_ADC_SEL ANA_REG1_ADC_SEL_Msk /*!< This register represents current ADC sampling channels. The ADC sampling channels are controlled by ADC controller */ +//#define ANA_REG1_ADC_SEL_0 (0x0U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_1 (0x1U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_2 (0x2U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_3 (0x3U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_4 (0x4U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_5 (0x5U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_6 (0x6U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_7 (0x7U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_8 (0x8U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_9 (0x9U << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_10 (0xAU << ANA_REG1_ADC_SEL_Pos) +//#define ANA_REG1_ADC_SEL_11 (0xBU << ANA_REG1_ADC_SEL_Pos) +#define ANA_REG1_RESDIV_Pos (4U) +#define ANA_REG1_RESDIV_Msk (0x1U << ANA_REG1_RESDIV_Pos) /*!< 0x00000010 */ +#define ANA_REG1_RESDIV ANA_REG1_RESDIV_Msk /*!< Enable resistor division for M ADC��s input signal */ +#define ANA_REG1_GDE4_Pos (5U) +#define ANA_REG1_GDE4_Msk (0x1U << ANA_REG1_GDE4_Pos) /*!< 0x00000020 */ +#define ANA_REG1_GDE4 ANA_REG1_GDE4_Msk /*!< Enable cap division for M ADC��s input signal */ +//#define ANA_REG1_PRES_EN_Pos (6U) +//#define ANA_REG1_PRES_EN_Msk (0x1U << ANA_REG1_PRES_EN_Pos) /*!< 0x00000040 */ +//#define ANA_REG1_PRES_EN ANA_REG1_PRES_EN_Msk /*!< Enable pull down resistor for M ADC��s input signal */ +//#define ANA_REG1_ADCRSTM_Pos (7U) +//#define ANA_REG1_ADCRSTM_Msk (0x1U << ANA_REG1_ADCRSTM_Pos) /*!< 0x00000080 */ +//#define ANA_REG1_ADCRSTM ANA_REG1_ADCRSTM_Msk /*!< */ + +/************** Bits definition for ANA_REG2 register ******************/ +#define ANA_REG2_CMP1_SEL_Pos (0U) +#define ANA_REG2_CMP1_SEL_Msk (0x3U << ANA_REG2_CMP1_SEL_Pos) /*!< 0x00000003 */ +#define ANA_REG2_CMP1_SEL ANA_REG2_CMP1_SEL_Msk /*!< Signal source selection of comparator A */ +#define ANA_REG2_CMP1_SEL_0 (0x0U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP1_SEL_1 (0x1U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP1_SEL_2 (0x2U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP1_SEL_3 (0x3U << ANA_REG2_CMP1_SEL_Pos) +#define ANA_REG2_CMP2_SEL_Pos (2U) +#define ANA_REG2_CMP2_SEL_Msk (0x3U << ANA_REG2_CMP2_SEL_Pos) /*!< 0x0000000C */ +#define ANA_REG2_CMP2_SEL ANA_REG2_CMP2_SEL_Msk /*!< Signal source selection of comparator B */ +#define ANA_REG2_REFSEL_CMP1_Pos (4U) +#define ANA_REG2_REFSEL_CMP1_Msk (0x1U << ANA_REG2_REFSEL_CMP1_Pos) /*!< 0x00000010 */ +#define ANA_REG2_REFSEL_CMP1 ANA_REG2_REFSEL_CMP1_Msk /*!< REF selection of CMP1 */ +#define ANA_REG2_REFSEL_CMP2_Pos (5U) +#define ANA_REG2_REFSEL_CMP2_Msk (0x1U << ANA_REG2_REFSEL_CMP2_Pos) /*!< 0x00000020 */ +#define ANA_REG2_REFSEL_CMP2 ANA_REG2_REFSEL_CMP2_Msk /*!< REF selection of CMP2 */ +//#define ANA_REG2_TEMPPDN_Pos (6U) +//#define ANA_REG2_TEMPPDN_Msk (0x1U << ANA_REG2_TEMPPDN_Pos) /*!< 0x00000040 */ +//#define ANA_REG2_TEMPPDN ANA_REG2_TEMPPDN_Msk /*!< Temperature sensor power down control */ +//#define ANA_REG2_XOLPD_Pos (7U) +//#define ANA_REG2_XOLPD_Msk (0x1U << ANA_REG2_XOLPD_Pos) /*!< 0x00000080 */ +//#define ANA_REG2_XOLPD ANA_REG2_XOLPD_Msk /*!< 32K crystal pad (XOL) power down control */ + +/************** Bits definition for ANA_REG3 register ******************/ +#define ANA_REG3_ADCPDN_Pos (0U) +#define ANA_REG3_ADCPDN_Msk (0x1U << ANA_REG3_ADCPDN_Pos) /*!< 0x00000001 */ +#define ANA_REG3_ADCPDN ANA_REG3_ADCPDN_Msk /*!< ADC power down control signal */ +#define ANA_REG3_CMP1PDN_Pos (1U) +#define ANA_REG3_CMP1PDN_Msk (0x1U << ANA_REG3_CMP1PDN_Pos) /*!< 0x00000002 */ +#define ANA_REG3_CMP1PDN ANA_REG3_CMP1PDN_Msk /*!< CMP1 power down control signal */ +#define ANA_REG3_CMP2PDN_Pos (2U) +#define ANA_REG3_CMP2PDN_Msk (0x1U << ANA_REG3_CMP2PDN_Pos) /*!< 0x00000004 */ +#define ANA_REG3_CMP2PDN ANA_REG3_CMP2PDN_Msk /*!< CMP2 power down control signal */ +#define ANA_REG3_BGPPD_Pos (3U) +#define ANA_REG3_BGPPD_Msk (0x1U << ANA_REG3_BGPPD_Pos) /*!< 0x00000008 */ +#define ANA_REG3_BGPPD ANA_REG3_BGPPD_Msk /*!< BGP power down control signal */ +#define ANA_REG3_RCHPD_Pos (4U) +#define ANA_REG3_RCHPD_Msk (0x1U << ANA_REG3_RCHPD_Pos) /*!< 0x00000010 */ +#define ANA_REG3_RCHPD ANA_REG3_RCHPD_Msk /*!< RCH (6.5536M ROSC) power down control signal */ +#define ANA_REG3_PLLLPDN_Pos (5U) +#define ANA_REG3_PLLLPDN_Msk (0x1U << ANA_REG3_PLLLPDN_Pos) /*!< 0x00000020 */ +#define ANA_REG3_PLLLPDN ANA_REG3_PLLLPDN_Msk /*!< PLLL (32768Hz input PLL) power down control signal */ +#define ANA_REG3_PLLHPDN_Pos (6U) +#define ANA_REG3_PLLHPDN_Msk (0x1U << ANA_REG3_PLLHPDN_Pos) /*!< 0x00000040 */ +#define ANA_REG3_PLLHPDN ANA_REG3_PLLHPDN_Msk /*!< PLLL (6.55364MHz input PLL) power down control signal */ +#define ANA_REG3_XOHPDN_Pos (7U) +#define ANA_REG3_XOHPDN_Msk (0x1U << ANA_REG3_XOHPDN_Pos) /*!< 0x00000080 */ +#define ANA_REG3_XOHPDN ANA_REG3_XOHPDN_Msk /*!< Turn on signal of 6.5536M crystal */ + +/************** Bits definition for ANA_REG4 register ******************/ +//#define ANA_REG4_XRSEL_Pos (0U) +//#define ANA_REG4_XRSEL_Msk (0x3U << ANA_REG4_XRSEL_Pos) /*!< 0x00000003 */ +//#define ANA_REG4_XRSEL ANA_REG4_XRSEL_Msk /*!< After power up, set this register to 0x3 for low power operation */ +//#define ANA_REG4_XOLLP_Pos (2U) +//#define ANA_REG4_XOLLP_Msk (0x1U << ANA_REG4_XOLLP_Pos) /*!< 0x00000004 */ +//#define ANA_REG4_XOLLP ANA_REG4_XOLLP_Msk /*!< 32K crystal pad low power mode, set this bit to 1 after power-up for low power operation */ +//#define ANA_REG4_XCSEL_Pos (3U) +//#define ANA_REG4_XCSEL_Msk (0x1U << ANA_REG4_XCSEL_Pos) /*!< 0x00000008 */ +//#define ANA_REG4_XCSEL ANA_REG4_XCSEL_Msk /*!< 32K crystal capacitance trimming */ +//#define ANA_REG4_XRSEL_H_Pos (4U) +//#define ANA_REG4_XRSEL_H_Msk (0x3U << ANA_REG4_XRSEL_H_Pos) /*!< 0x00000030 */ +//#define ANA_REG4_XRSEL_H ANA_REG4_XRSEL_H_Msk /*!< */ +//#define ANA_REG4_XCSEL_H_Pos (6U) +//#define ANA_REG4_XCSEL_H_Msk (0x3U << ANA_REG4_XCSEL_H_Pos) /*!< 0x000000C0 */ +//#define ANA_REG4_XCSEL_H ANA_REG4_XCSEL_H_Msk /*!< */ + +/************** Bits definition for ANA_REG5 register ******************/ +#define ANA_REG5_IT_CMP1_Pos (0U) +#define ANA_REG5_IT_CMP1_Msk (0x3U << ANA_REG5_IT_CMP1_Pos) /*!< 0x00000003 */ +#define ANA_REG5_IT_CMP1 ANA_REG5_IT_CMP1_Msk /*!< Bias current selection of CMP1 */ +#define ANA_REG5_IT_CMP1_0 (0x0U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP1_1 (0x1U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP1_2 (0x2U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP1_3 (0x3U << ANA_REG5_IT_CMP1_Pos) +#define ANA_REG5_IT_CMP2_Pos (2U) +#define ANA_REG5_IT_CMP2_Msk (0x3U << ANA_REG5_IT_CMP2_Pos) /*!< 0x0000000C */ +#define ANA_REG5_IT_CMP2 ANA_REG5_IT_CMP2_Msk /*!< Bias current selection of CMP2 */ +//#define ANA_REG5_CMP_HYS_Pos (4U) +//#define ANA_REG5_CMP_HYS_Msk (0x1U << ANA_REG5_CMP_HYS_Pos) /*!< 0x00000010 */ +//#define ANA_REG5_CMP_HYS ANA_REG5_CMP_HYS_Msk /*!< HYS voltage selection */ +//#define ANA_REG5_PW2M_EN_Pos (5U) +//#define ANA_REG5_PW2M_EN_Msk (0x1U << ANA_REG5_PW2M_EN_Pos) /*!< 0x00000020 */ +//#define ANA_REG5_PW2M_EN ANA_REG5_PW2M_EN_Msk /*!< Enable power supply to RTC */ +#define ANA_REG5_PD_AVCCDET_Pos (6U) +#define ANA_REG5_PD_AVCCDET_Msk (0x1U << ANA_REG5_PD_AVCCDET_Pos) /*!< 0x00000040 */ +#define ANA_REG5_PD_AVCCDET ANA_REG5_PD_AVCCDET_Msk /*!< Power down low voltage detector */ +//#define ANA_REG5_RTCLDOPD_EN_Pos (7U) +//#define ANA_REG5_RTCLDOPD_EN_Msk (0x1U << ANA_REG5_RTCLDOPD_EN_Pos) /*!< 0x00000080 */ +//#define ANA_REG5_RTCLDOPD_EN ANA_REG5_RTCLDOPD_EN_Msk /*!< Enable PD RTCLDO when main power is on */ + +/************** Bits definition for ANA_REG6 register ******************/ +#define ANA_REG6_LCD_BMODE_Pos (0U) +#define ANA_REG6_LCD_BMODE_Msk (0x1U << ANA_REG6_LCD_BMODE_Pos) /*!< 0x00000001 */ +#define ANA_REG6_LCD_BMODE ANA_REG6_LCD_BMODE_Msk /*!< LCD BIAS mode selection */ +#define ANA_REG6_VLCD_Pos (1U) +#define ANA_REG6_VLCD_Msk (0xFU << ANA_REG6_VLCD_Pos) /*!< 0x0000001E */ +#define ANA_REG6_VLCD ANA_REG6_VLCD_Msk /*!< LCD driving voltage */ +#define ANA_REG6_VLCD_0 (0x0U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_1 (0x1U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_2 (0x2U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_3 (0x3U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_4 (0x4U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_5 (0x5U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_6 (0x6U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_7 (0x7U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_8 (0x8U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_9 (0x9U << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_A (0xAU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_B (0xBU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_C (0xCU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_D (0xDU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_E (0xEU << ANA_REG6_VLCD_Pos) +#define ANA_REG6_VLCD_F (0xFU << ANA_REG6_VLCD_Pos) +//#define ANA_REG6_LCDVOUT_Pos (5U) +//#define ANA_REG6_LCDVOUT_Msk (0x1U << ANA_REG6_LCDVOUT_Pos) /*!< 0x00000020 */ +//#define ANA_REG6_LCDVOUT ANA_REG6_LCDVOUT_Msk /*!< LCD voltage output enable */ +//#define ANA_REG6_BAT1DISC_Pos (6U) +//#define ANA_REG6_BAT1DISC_Msk (0x1U << ANA_REG6_BAT1DISC_Pos) /*!< 0x00000040 */ +//#define ANA_REG6_BAT1DISC ANA_REG6_BAT1DISC_Msk /*!< Discharge the BAT1 battery */ +#define ANA_REG6_BATRTCDISC_Pos (7U) +#define ANA_REG6_BATRTCDISC_Msk (0x1U << ANA_REG6_BATRTCDISC_Pos) /*!< 0x00000080 */ +#define ANA_REG6_BATRTCDISC ANA_REG6_BATRTCDISC_Msk /*!< Discharge the RTCBAT battery */ + +/************** Bits definition for ANA_REG7 register ******************/ +//#define ANA_REG7_ANAOUT_EN_Pos (0U) +//#define ANA_REG7_ANAOUT_EN_Msk (0x1U << ANA_REG7_ANAOUT_EN_Pos) /*!< 0x00000001 */ +//#define ANA_REG7_ANAOUT_EN ANA_REG7_ANAOUT_EN_Msk /*!< Enable analog signal out */ +//#define ANA_REG7_P10ENN_Pos (1U) +//#define ANA_REG7_P10ENN_Msk (0x1U << ANA_REG7_P10ENN_Pos) /*!< 0x00000002 */ +//#define ANA_REG7_P10ENN ANA_REG7_P10ENN_Msk /*!< */ +//#define ANA_REG7_MADCHOPN_Pos (2U) +//#define ANA_REG7_MADCHOPN_Msk (0x1U << ANA_REG7_MADCHOPN_Pos) /*!< 0x00000004 */ +//#define ANA_REG7_MADCHOPN ANA_REG7_MADCHOPN_Msk /*!< */ +//#define ANA_REG7_TMPCKOFF_Pos (3U) +//#define ANA_REG7_TMPCKOFF_Msk (0x1U << ANA_REG7_TMPCKOFF_Pos) /*!< 0x00000008 */ +//#define ANA_REG7_TMPCKOFF ANA_REG7_TMPCKOFF_Msk /*!< */ +//#define ANA_REG7_LDOISEL_Pos (4U) +//#define ANA_REG7_LDOISEL_Msk (0x1U << ANA_REG7_LDOISEL_Pos) /*!< 0x00000010 */ +//#define ANA_REG7_LDOISEL ANA_REG7_LDOISEL_Msk /*!< */ +//#define ANA_REG7_SWT2VDD_Pos (5U) +//#define ANA_REG7_SWT2VDD_Msk (0x1U << ANA_REG7_SWT2VDD_Pos) /*!< 0x00000020 */ +//#define ANA_REG7_SWT2VDD ANA_REG7_SWT2VDD_Msk /*!< */ +//#define ANA_REG7_X32KIN_EN_Pos (6U) +//#define ANA_REG7_X32KIN_EN_Msk (0x1U << ANA_REG7_X32KIN_EN_Pos) /*!< 0x00000040 */ +//#define ANA_REG7_X32KIN_EN ANA_REG7_X32KIN_EN_Msk /*!< Additional X32K pad input enable */ +//#define ANA_REG7_CLKOSEL_Pos (7U) +//#define ANA_REG7_CLKOSEL_Msk (0x1U << ANA_REG7_CLKOSEL_Pos) /*!< 0x00000080 */ +//#define ANA_REG7_CLKOSEL ANA_REG7_CLKOSEL_Msk /*!< */ + +/************** Bits definition for ANA_REG8 register ******************/ +//#define ANA_REG8_DVCCSEL_Pos (0U) +//#define ANA_REG8_DVCCSEL_Msk (0x3U << ANA_REG8_DVCCSEL_Pos) /*!< 0x00000003 */ +//#define ANA_REG8_DVCCSEL ANA_REG8_DVCCSEL_Msk /*!< Trimming of DVCC */ +//#define ANA_REG8_DVCCSEL_0 (0x0U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_DVCCSEL_1 (0x1U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_DVCCSEL_2 (0x2U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_DVCCSEL_3 (0x3U << ANA_REG8_DVCCSEL_Pos) +//#define ANA_REG8_AVCCSEL_Pos (2U) +//#define ANA_REG8_AVCCSEL_Msk (0x3U << ANA_REG8_AVCCSEL_Pos) /*!< 0x0000000C */ +//#define ANA_REG8_AVCCSEL ANA_REG8_AVCCSEL_Msk /*!< Trimming of AVCC */ +#define ANA_REG8_VDDPVDSEL_Pos (4U) +#define ANA_REG8_VDDPVDSEL_Msk (0x7U << ANA_REG8_VDDPVDSEL_Pos) /*!< 0x00000070 */ +#define ANA_REG8_VDDPVDSEL ANA_REG8_VDDPVDSEL_Msk /*!< Voltage selection of power detector, the setting in this register will affect the status of QPWRDN */ +#define ANA_REG8_VDDPVDSEL_0 (0x0U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_1 (0x1U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_2 (0x2U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_3 (0x3U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_4 (0x4U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_5 (0x5U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_6 (0x6U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_VDDPVDSEL_7 (0x7U << ANA_REG8_VDDPVDSEL_Pos) +#define ANA_REG8_PD_AVCCLDO_Pos (7U) +#define ANA_REG8_PD_AVCCLDO_Msk (0x1U << ANA_REG8_PD_AVCCLDO_Pos) /*!< 0x00000080 */ +#define ANA_REG8_PD_AVCCLDO ANA_REG8_PD_AVCCLDO_Msk /*!< AVCCLDO Power-down control signal */ + +/************** Bits definition for ANA_REG9 register ******************/ +#define ANA_REG9_PLLLSEL_Pos (0U) +#define ANA_REG9_PLLLSEL_Msk (0x7U << ANA_REG9_PLLLSEL_Pos) /*!< 0x00000007 */ +#define ANA_REG9_PLLLSEL ANA_REG9_PLLLSEL_Msk /*!< Clk frequency selection of PLLL */ +#define ANA_REG9_PLLLSEL_26M (0x0U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_13M (0x1U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_6_5M (0x2U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_3_2M (0x3U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_800K (0x5U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_400K (0x6U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLLSEL_200K (0x7U << ANA_REG9_PLLLSEL_Pos) +#define ANA_REG9_PLLHSEL_Pos (3U) +#define ANA_REG9_PLLHSEL_Msk (0xFU << ANA_REG9_PLLHSEL_Pos) /*!< 0x00000078 */ +#define ANA_REG9_PLLHSEL ANA_REG9_PLLHSEL_Msk /*!< Clk frequency selection of PLLH */ +#define ANA_REG9_PLLHSEL_X2 (0xCU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X2_5 (0xDU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X3 (0xEU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X3_5 (0xFU << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X4 (0x0U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X4_5 (0x1U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X5 (0x2U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X6 (0x4U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X6_5 (0x5U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X7 (0x6U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PLLHSEL_X7_5 (0x7U << ANA_REG9_PLLHSEL_Pos) +#define ANA_REG9_PDDET_Pos (7U) +#define ANA_REG9_PDDET_Msk (0x1U << ANA_REG9_PDDET_Pos) /*!< 0x00000080 */ +#define ANA_REG9_PDDET ANA_REG9_PDDET_Msk /*!< */ + +/************** Bits definition for ANA_REGA register ******************/ +//#define ANA_REGA_VDD2_OFF_Pos (0U) +//#define ANA_REGA_VDD2_OFF_Msk (0x1U << ANA_REGA_VDD2_OFF_Pos) /*!< 0x00000001 */ +//#define ANA_REGA_VDD2_OFF ANA_REGA_VDD2_OFF_Msk /*!< This register is controlled by hardware and should be set to 0 for all the time */ +//#define ANA_REGA_VDD3_OFF_Pos (1U) +//#define ANA_REGA_VDD3_OFF_Msk (0x1U << ANA_REGA_VDD3_OFF_Pos) /*!< 0x00000002 */ +//#define ANA_REGA_VDD3_OFF ANA_REGA_VDD3_OFF_Msk /*!< This register is controlled by hardware and should be set to 0 for all the time */ +////#define ANA_REGA_RTCVSEL_Pos (2U) +//#define ANA_REGA_RTCVSEL_Msk (0x1U << ANA_REGA_RTCVSEL_Pos) /*!< 0x00000004 */ +//#define ANA_REGA_RTCVSEL ANA_REGA_RTCVSEL_Msk /*!< RTC LDO voltage selection */ +//#define ANA_REGA_SWT2BAT1_Pos (3U) +//#define ANA_REGA_SWT2BAT1_Msk (0x1U << ANA_REGA_SWT2BAT1_Pos) /*!< 0x00000008 */ +//#define ANA_REGA_SWT2BAT1 ANA_REGA_SWT2BAT1_Msk /*!< Switching from VDCIN to BAT1 manually */ +//#define ANA_REGA_PSLSEL_Pos (4U) +//#define ANA_REGA_PSLSEL_Msk (0x1U << ANA_REGA_PSLSEL_Pos) /*!< 0x00000010 */ +//#define ANA_REGA_PSLSEL ANA_REGA_PSLSEL_Msk /*!< power switch level selection */ +//#define ANA_REGA_PD_PORH_Pos (5U) +//#define ANA_REGA_PD_PORH_Msk (0x1U << ANA_REGA_PD_PORH_Pos) /*!< 0x00000020 */ +//#define ANA_REGA_PD_PORH ANA_REGA_PD_PORH_Msk /*!< PD POR_H module, output ��1�� when PD */ +//#define ANA_REGA_PD_RCL_Pos (6U) +//#define ANA_REGA_PD_RCL_Msk (0x1U << ANA_REGA_PD_RCL_Pos) /*!< 0x00000040 */ +//#define ANA_REGA_PD_RCL ANA_REGA_PD_RCL_Msk /*!< PD 32K RC module */ +#define ANA_REGA_PD_VDCINDET_Pos (7U) +#define ANA_REGA_PD_VDCINDET_Msk (0x1U << ANA_REGA_PD_VDCINDET_Pos) /*!< 0x00000080 */ +#define ANA_REGA_PD_VDCINDET ANA_REGA_PD_VDCINDET_Msk /*!< PD VDCIN detector */ + +/************** Bits definition for ANA_REGB register ******************/ +#define ANA_REGB_RCLTRIM_Pos (0U) +#define ANA_REGB_RCLTRIM_Msk (0x1FU << ANA_REGB_RCLTRIM_Pos) /*!< 0x0000001F */ +#define ANA_REGB_RCLTRIM ANA_REGB_RCLTRIM_Msk /*!< Trimming of 32kHz RC */ +#define ANA_REGB_RCLTRIM_0 (0x00U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_1 (0x01U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_2 (0x02U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_3 (0x03U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_4 (0x04U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_5 (0x05U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_6 (0x06U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_7 (0x07U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_8 (0x08U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_9 (0x09U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_10 (0x0AU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_11 (0x0BU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_12 (0x0CU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_13 (0x0DU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_14 (0x0EU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_15 (0x0FU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_16 (0x10U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_17 (0x11U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_18 (0x12U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_19 (0x13U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_20 (0x14U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_21 (0x15U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_22 (0x16U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_23 (0x17U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_24 (0x18U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_25 (0x19U << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_26 (0x1AU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_27 (0x1BU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_28 (0x1CU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_29 (0x1DU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_30 (0x1EU << ANA_REGB_RCLTRIM_Pos) +#define ANA_REGB_RCLTRIM_31 (0x1FU << ANA_REGB_RCLTRIM_Pos) + +/************** Bits definition for ANA_REGC register ******************/ +#define ANA_REGC_RCHTRIM_Pos (0U) +#define ANA_REGC_RCHTRIM_Msk (0x3FU << ANA_REGC_RCHTRIM_Pos) /*!< 0x0000003F */ +#define ANA_REGC_RCHTRIM ANA_REGC_RCHTRIM_Msk /*!< Trimming of 6.55364MHz RC */ +#define ANA_REGC_RCHTRIM_0 (0x00U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_1 (0x01U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_2 (0x02U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_3 (0x03U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_4 (0x04U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_5 (0x05U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_6 (0x06U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_7 (0x07U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_8 (0x08U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_9 (0x09U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_10 (0x0AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_11 (0x0BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_12 (0x0CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_13 (0x0DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_14 (0x0EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_15 (0x0FU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_16 (0x10U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_17 (0x11U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_18 (0x12U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_19 (0x13U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_20 (0x14U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_21 (0x15U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_22 (0x16U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_23 (0x17U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_24 (0x18U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_25 (0x19U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_26 (0x1AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_27 (0x1BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_28 (0x1CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_29 (0x1DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_30 (0x1EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_31 (0x1FU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_32 (0x20U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_33 (0x21U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_34 (0x22U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_35 (0x23U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_36 (0x24U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_37 (0x25U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_38 (0x26U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_39 (0x27U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_40 (0x28U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_41 (0x29U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_42 (0x2AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_43 (0x2BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_44 (0x2CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_45 (0x2DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_46 (0x2EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_47 (0x2FU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_48 (0x30U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_49 (0x31U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_50 (0x32U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_51 (0x33U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_52 (0x34U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_53 (0x35U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_54 (0x36U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_55 (0x37U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_56 (0x38U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_57 (0x39U << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_58 (0x3AU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_59 (0x3BU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_60 (0x3CU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_61 (0x3DU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_62 (0x3EU << ANA_REGC_RCHTRIM_Pos) +#define ANA_REGC_RCHTRIM_63 (0x3FU << ANA_REGC_RCHTRIM_Pos) + +/************** Bits definition for ANA_REGD register ******************/ +#define ANA_REGD_DVCCTRIM_Pos (0U) +#define ANA_REGD_DVCCTRIM_Msk (0x7U << ANA_REGD_DVCCTRIM_Pos) /*!< 0x00000007 */ +#define ANA_REGD_DVCCTRIM ANA_REGD_DVCCTRIM_Msk /*!< Trimming of DVCC */ +#define ANA_REGD_DVCCTRIM_0 (0x0U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_1 (0x1U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_2 (0x2U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_3 (0x3U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_4 (0x4U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_5 (0x5U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_6 (0x6U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_DVCCTRIM_7 (0x7U << ANA_REGD_DVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_Pos (3U) +#define ANA_REGD_AVCCTRIM_Msk (0x7U << ANA_REGD_AVCCTRIM_Pos) /*!< 0x00000038 */ +#define ANA_REGD_AVCCTRIM ANA_REGD_AVCCTRIM_Msk /*!< Trimming of AVCC */ +#define ANA_REGD_AVCCTRIM_0 (0x0U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_1 (0x1U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_2 (0x2U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_3 (0x3U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_4 (0x4U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_5 (0x5U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_6 (0x6U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_AVCCTRIM_7 (0x7U << ANA_REGD_AVCCTRIM_Pos) +#define ANA_REGD_VREFTRIM_Pos (6U) +#define ANA_REGD_VREFTRIM_Msk (0x3U << ANA_REGD_VREFTRIM_Pos) /*!< 0x000000C0 */ +#define ANA_REGD_VREFTRIM ANA_REGD_VREFTRIM_Msk /*!< Trimming of VREF, which will affect DVCC/33��s output by same ratio */ +#define ANA_REGD_VREFTRIM_0 (0x0U << ANA_REGD_VREFTRIM_Pos) +#define ANA_REGD_VREFTRIM_1 (0x1U << ANA_REGD_VREFTRIM_Pos) +#define ANA_REGD_VREFTRIM_2 (0x2U << ANA_REGD_VREFTRIM_Pos) +#define ANA_REGD_VREFTRIM_3 (0x3U << ANA_REGD_VREFTRIM_Pos) + +/************** Bits definition for ANA_REGE register ******************/ +#define ANA_REGE_REST_Pos (0U) +#define ANA_REGE_REST_Msk (0x7U << ANA_REGE_REST_Pos) /*!< 0x00000007 */ +#define ANA_REGE_REST ANA_REGE_REST_Msk /*!< Fine trimming of bandgap */ +#define ANA_REGE_REST_0 (0x0U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_1 (0x1U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_2 (0x2U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_3 (0x3U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_4 (0x4U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_5 (0x5U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_6 (0x6U << ANA_REGE_REST_Pos) +#define ANA_REGE_REST_7 (0x7U << ANA_REGE_REST_Pos) +#define ANA_REGE_RESTL_Pos (4U) +#define ANA_REGE_RESTL_Msk (0x3U << ANA_REGE_RESTL_Pos) /*!< 0x00000018 */ +#define ANA_REGE_RESTL ANA_REGE_RESTL_Msk /*!< Coarse trimming of bandgap */ +#define ANA_REGE_RESTL_0 (0x0U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTL_1 (0x1U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTL_2 (0x2U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTL_3 (0x3U << ANA_REGE_RESTL_Pos) +#define ANA_REGE_RESTD_Pos (6U) +#define ANA_REGE_RESTD_Msk (0x1U << ANA_REGE_RESTD_Pos) +#define ANA_REGE_RESTD ANA_REGE_RESTD_Msk +/************** Bits definition for ANA_REGF register ******************/ +//#define ANA_REGF_TRB_Pos (0U) +//#define ANA_REGF_TRB_Msk (0x3U << ANA_REGF_TRB_Pos) /*!< 0x00000003 */ +//#define ANA_REGF_TRB ANA_REGF_TRB_Msk /*!< Bias voltage trim for ADCs */ +#define ANA_REGF_AVCCO_EN_Pos (2U) +#define ANA_REGF_AVCCO_EN_Msk (0x1U << ANA_REGF_AVCCO_EN_Pos) +#define ANA_REGF_AVCCO_EN ANA_REGF_AVCCO_EN_Msk +#define ANA_REGF_PDNADT_Pos (3U) +#define ANA_REGF_PDNADT_Msk (0x1U << ANA_REGF_PDNADT_Pos) +#define ANA_REGF_PDNADT ANA_REGF_PDNADT_Msk +#define ANA_REGF_SELADT_Pos (4U) +#define ANA_REGF_SELADT_Msk (0x1U << ANA_REGF_SELADT_Pos) +#define ANA_REGF_SELADT ANA_REGF_SELADT_Msk +#define ANA_REGF_ADTREF1SEL_Pos (5U) +#define ANA_REGF_ADTREF1SEL_Msk (0x1U << ANA_REGF_ADTREF1SEL_Pos) +#define ANA_REGF_ADTREF1SEL ANA_REGF_ADTREF1SEL_Msk +#define ANA_REGF_ADTREF2SEL_Pos (6U) +#define ANA_REGF_ADTREF2SEL_Msk (0x1U << ANA_REGF_ADTREF2SEL_Pos) +#define ANA_REGF_ADTREF2SEL ANA_REGF_ADTREF2SEL_Msk +#define ANA_REGF_ADTREF3SEL_Pos (7U) +#define ANA_REGF_ADTREF3SEL_Msk (0x1U << ANA_REGF_ADTREF3SEL_Pos) +#define ANA_REGF_ADTREF3SEL ANA_REGF_ADTREF3SEL_Msk +///************** Bits definition for ANA_REG10 register ******************/ +//#define ANA_REG10_Pos (0U) +//#define ANA_REG10_Msk (0xFFU << ANA_REG10_Pos) /*!< 0x000000FF */ +//#define ANA_REG10 ANA_REG10_Msk /*!< Analog control register 16 */ +// +///************** Bits definition for ANA_REG11 register ******************/ +//#define ANA_REG11_Pos (0U) +//#define ANA_REG11_Msk (0xFFU << ANA_REG11_Pos) /*!< 0x000000FF */ +//#define ANA_REG11 ANA_REG11_Msk /*!< Analog control register 17 */ +// +///************** Bits definition for ANA_REG12 register ******************/ +//#define ANA_REG12_Pos (0U) +//#define ANA_REG12_Msk (0xFFU << ANA_REG12_Pos) /*!< 0x000000FF */ +//#define ANA_REG12 ANA_REG12_Msk /*!< Analog control register 18 */ + +/************** Bits definition for ANA_CTRL register ******************/ +#define ANA_CTRL_COMP1_SEL_Pos (0U) +#define ANA_CTRL_COMP1_SEL_Msk (0x3U << ANA_CTRL_COMP1_SEL_Pos) /*!< 0x00000003 */ +#define ANA_CTRL_COMP1_SEL ANA_CTRL_COMP1_SEL_Msk /*!< This register is used to control the interrupt and wake-up signal generation of COMP1 */ +#define ANA_CTRL_COMP1_SEL_0 (0x0U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP1_SEL_1 (0x1U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP1_SEL_2 (0x2U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP1_SEL_3 (0x3U << ANA_CTRL_COMP1_SEL_Pos) +#define ANA_CTRL_COMP2_SEL_Pos (2U) +#define ANA_CTRL_COMP2_SEL_Msk (0x3U << ANA_CTRL_COMP2_SEL_Pos) /*!< 0x0000000C */ +#define ANA_CTRL_COMP2_SEL ANA_CTRL_COMP2_SEL_Msk /*!< This register is used to control the interrupt and wake-up signal generation of COMP2 */ +//#define ANA_CTRL_PORLOFF_Pos (4U) +//#define ANA_CTRL_PORLOFF_Msk (0x1U << ANA_CTRL_PORLOFF_Pos) /*!< 0x00000010 */ +//#define ANA_CTRL_PORLOFF ANA_CTRL_PORLOFF_Msk /*!< This register can disable the PORL reset */ +//#define ANA_CTRL_PORHOFF_Pos (5U) +//#define ANA_CTRL_PORHOFF_Msk (0x1U << ANA_CTRL_PORHOFF_Pos) /*!< 0x00000020 */ +//#define ANA_CTRL_PORHOFF ANA_CTRL_PORHOFF_Msk /*!< This register can disable the PORH reset */ +#define ANA_CTRL_PDNS_Pos (6U) +#define ANA_CTRL_PDNS_Msk (0x1U << ANA_CTRL_PDNS_Pos) /*!< 0x00000040 */ +#define ANA_CTRL_PDNS ANA_CTRL_PDNS_Msk /*!< This register is used to set the deep sleep behavior when VDCIN is not drop */ +//#define ANA_CTRL_DVCCSW_Pos (7U) +//#define ANA_CTRL_DVCCSW_Msk (0x1U << ANA_CTRL_DVCCSW_Pos) /*!< 0x00000080 */ +//#define ANA_CTRL_DVCCSW ANA_CTRL_DVCCSW_Msk /*!< DVCC auto switch enable at sleep or deep-sleep mode */ +#define ANA_CTRL_RCHTGT_Pos (8U) +#define ANA_CTRL_RCHTGT_Msk (0xFFU << ANA_CTRL_RCHTGT_Pos) /*!< 0x0000FF00 */ +#define ANA_CTRL_RCHTGT ANA_CTRL_RCHTGT_Msk /*!< RCH auto0calibration target register. This register is used to store the target value of RCH */ +//#define ANA_CTRL_DVCCSWSEL_Pos (16U) +//#define ANA_CTRL_DVCCSWSEL_Msk (0x3U << ANA_CTRL_DVCCSWSEL_Pos) /*!< 0x00030000 */ +//#define ANA_CTRL_DVCCSWSEL ANA_CTRL_DVCCSWSEL_Msk /*!< DVCC auto-switching setting at sleep mode or deep-sleep mode */ +//#define ANA_CTRL_DVCCSWSEL_0 (0x0U << ANA_CTRL_DVCCSWSEL_Pos) +//#define ANA_CTRL_DVCCSWSEL_1 (0x1U << ANA_CTRL_DVCCSWSEL_Pos) +//#define ANA_CTRL_DVCCSWSEL_2 (0x2U << ANA_CTRL_DVCCSWSEL_Pos) +//#define ANA_CTRL_DVCCSWSEL_3 (0x3U << ANA_CTRL_DVCCSWSEL_Pos) +#define ANA_CTRL_CMP1DEB_Pos (20U) +#define ANA_CTRL_CMP1DEB_Msk (0x3U << ANA_CTRL_CMP1DEB_Pos) /*!< 0x00300000 */ +#define ANA_CTRL_CMP1DEB ANA_CTRL_CMP1DEB_Msk /*!< Comparator 1 de-bounce control register */ +#define ANA_CTRL_CMP1DEB_0 (0x0U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP1DEB_1 (0x1U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP1DEB_2 (0x2U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP1DEB_3 (0x3U << ANA_CTRL_CMP1DEB_Pos) +#define ANA_CTRL_CMP2DEB_Pos (22U) +#define ANA_CTRL_CMP2DEB_Msk (0x3U << ANA_CTRL_CMP2DEB_Pos) /*!< 0x00C00000 */ +#define ANA_CTRL_CMP2DEB ANA_CTRL_CMP2DEB_Msk /*!< Comparator 2 de-bounce control register */ +#define ANA_CTRL_PWRDROPDEB_Pos (24U) +#define ANA_CTRL_PWRDROPDEB_Msk (0x3U << ANA_CTRL_PWRDROPDEB_Pos) /*!< 0x03000000 */ +#define ANA_CTRL_PWRDROPDEB ANA_CTRL_PWRDROPDEB_Msk /*!< Power drop de-bounce control register */ +#define ANA_CTRL_PWRDROPDEB_0 (0x0U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PWRDROPDEB_1 (0x1U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PWRDROPDEB_2 (0x2U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PWRDROPDEB_3 (0x3U << ANA_CTRL_PWRDROPDEB_Pos) +#define ANA_CTRL_PDNS2_Pos (26U) +#define ANA_CTRL_PDNS2_Msk (0x1U << ANA_CTRL_PDNS2_Pos) /*!< 0x04000000 */ +#define ANA_CTRL_PDNS2 ANA_CTRL_PDNS2_Msk /*!< This register is used to set the deep sleep behavior when VDD is not drop */ +//#define ANA_CTRL_ANATEST_Pos (28U) +//#define ANA_CTRL_ANATEST_Msk (0xFU << ANA_CTRL_ANATEST_Pos) /*!< 0xF0000000 */ +//#define ANA_CTRL_ANATEST ANA_CTRL_ANATEST_Msk /*!< This register is used to control the internal analog test signal. When one of the internal signal is selected, the hardware will use IOA[15] as input to simulation the behavior of the internal signal */ + +/************** Bits definition for ANA_COMPOUT register ******************/ +#define ANA_COMPOUT_LOCKH_Pos (0U) +#define ANA_COMPOUT_LOCKH_Msk (0x1U << ANA_COMPOUT_LOCKH_Pos) /*!< 0x00000001 */ +#define ANA_COMPOUT_LOCKH ANA_COMPOUT_LOCKH_Msk /*!< PLLH lock status */ +#define ANA_COMPOUT_LOCKL_Pos (1U) +#define ANA_COMPOUT_LOCKL_Msk (0x1U << ANA_COMPOUT_LOCKL_Pos) /*!< 0x00000002 */ +#define ANA_COMPOUT_LOCKL ANA_COMPOUT_LOCKL_Msk /*!< PLLL lock status */ +#define ANA_COMPOUT_COMP1_Pos (2U) +#define ANA_COMPOUT_COMP1_Msk (0x1U << ANA_COMPOUT_COMP1_Pos) /*!< 0x00000004 */ +#define ANA_COMPOUT_COMP1 ANA_COMPOUT_COMP1_Msk /*!< This bit shows the output of comparator 1 */ +#define ANA_COMPOUT_COMP2_Pos (3U) +#define ANA_COMPOUT_COMP2_Msk (0x1U << ANA_COMPOUT_COMP2_Pos) /*!< 0x00000008 */ +#define ANA_COMPOUT_COMP2 ANA_COMPOUT_COMP2_Msk /*!< This bit shows the output of comparator 2 */ +//#define ANA_COMPOUT_MAINPDN_Pos (4U) +//#define ANA_COMPOUT_MAINPDN_Msk (0x1U << ANA_COMPOUT_MAINPDN_Pos) /*!< 0x00000010 */ +//#define ANA_COMPOUT_MAINPDN ANA_COMPOUT_MAINPDN_Msk /*!< Main power power-down status */ +//#define ANA_COMPOUT_BATRTCPDN_Pos (5U) +//#define ANA_COMPOUT_BATRTCPDN_Msk (0x1U << ANA_COMPOUT_BATRTCPDN_Pos) /*!< 0x00000020 */ +//#define ANA_COMPOUT_BATRTCPDN ANA_COMPOUT_BATRTCPDN_Msk /*!< RTC power power-down status */ +//#define ANA_COMPOUT_MAINPRSTS_Pos (6U) +//#define ANA_COMPOUT_MAINPRSTS_Msk (0x1U << ANA_COMPOUT_MAINPRSTS_Pos) /*!< 0x00000040 */ +//#define ANA_COMPOUT_MAINPRSTS ANA_COMPOUT_MAINPRSTS_Msk /*!< This bit show the status of MAINPRSTS */ +#define ANA_COMPOUT_VDDALARM_Pos (7U) +#define ANA_COMPOUT_VDDALARM_Msk (0x1U << ANA_COMPOUT_VDDALARM_Pos) /*!< 0x00000080 */ +#define ANA_COMPOUT_VDDALARM ANA_COMPOUT_VDDALARM_Msk /*!< This bit shows the output of POWALARM */ +#define ANA_COMPOUT_VDCINDROP_Pos (8U) +#define ANA_COMPOUT_VDCINDROP_Msk (0x1U << ANA_COMPOUT_VDCINDROP_Pos) /*!< 0x00000100 */ +#define ANA_COMPOUT_VDCINDROP ANA_COMPOUT_VDCINDROP_Msk /*!< VDCIN drop status */ +#define ANA_COMPOUT_AVCCLV_Pos (10U) +#define ANA_COMPOUT_AVCCLV_Msk (0x1U << ANA_COMPOUT_AVCCLV_Pos) /*!< 0x00000400 */ +#define ANA_COMPOUT_AVCCLV ANA_COMPOUT_AVCCLV_Msk /*!< AVCC low power status */ +#define ANA_COMPOUT_TADCO_Pos (14UL) +#define ANA_COMPOUT_TADCO_Msk (0x03UL << ANA_COMPOUT_TADCO_Pos) +#define ANA_COMPOUT_TADCO ANA_COMPOUT_TADCO_Msk + +///************** Bits definition for ANA_VERSION register ******************/ +//#define ANA_VERSION_VERSION_Pos (0U) +//#define ANA_VERSION_VERSION_Msk (0x3U << ANA_VERSION_VERSION_Pos) /*!< 0x00000003 */ +//#define ANA_VERSION_VERSION ANA_VERSION_VERSION_Msk /*!< This bit shows the version information of analog module */ + +///************** Bits definition for ANA_ADCSTATE register ******************/ +//#define ANA_ADCSTATE_ADCSTATE_Pos (0U) +//#define ANA_ADCSTATE_ADCSTATE_Msk (0x7U << ANA_ADCSTATE_ADCSTATE_Pos) /*!< 0x00000007 */ +//#define ANA_ADCSTATE_ADCSTATE ANA_ADCSTATE_ADCSTATE_Msk /*!< This bit shows the ADC state of ADC CIC filter */ + +/************** Bits definition for ANA_INTSTS register ******************/ +#define ANA_INTSTS_Msk (0x1DFFUL) +#define ANA_INTSTS_INTSTS0_Pos (0U) +#define ANA_INTSTS_INTSTS0_Msk (0x1U << ANA_INTSTS_INTSTS0_Pos) /*!< 0x00000001 */ +#define ANA_INTSTS_INTSTS0 ANA_INTSTS_INTSTS0_Msk /*!< Interrupt flag of manual ADC conversion done */ +#define ANA_INTSTS_INTSTS1_Pos (1U) +#define ANA_INTSTS_INTSTS1_Msk (0x1U << ANA_INTSTS_INTSTS1_Pos) /*!< 0x00000002 */ +#define ANA_INTSTS_INTSTS1 ANA_INTSTS_INTSTS1_Msk /*!< Interrupt flag of auto ADC conversion done */ +#define ANA_INTSTS_INTSTS2_Pos (2U) +#define ANA_INTSTS_INTSTS2_Msk (0x1U << ANA_INTSTS_INTSTS2_Pos) /*!< 0x00000004 */ +#define ANA_INTSTS_INTSTS2 ANA_INTSTS_INTSTS2_Msk /*!< Interrupt flag of COMP1, the interrupt generate condition is controlled by COMP1_SEL */ +#define ANA_INTSTS_INTSTS3_Pos (3U) +#define ANA_INTSTS_INTSTS3_Msk (0x1U << ANA_INTSTS_INTSTS3_Pos) /*!< 0x00000008 */ +#define ANA_INTSTS_INTSTS3 ANA_INTSTS_INTSTS3_Msk /*!< Interrupt flag of COMP2, the interrupt generate condition is controlled by COMP2_SEL */ +//#define ANA_INTSTS_INTSTS4_Pos (4U) +//#define ANA_INTSTS_INTSTS4_Msk (0x1U << ANA_INTSTS_INTSTS4_Pos) /*!< 0x00000010 */ +//#define ANA_INTSTS_INTSTS4 ANA_INTSTS_INTSTS4_Msk /*!< Interrupt flag of MAINPDN, this interrupt will be generated when MAINPDN rising or falling */ +//#define ANA_INTSTS_INTSTS5_Pos (5U) +//#define ANA_INTSTS_INTSTS5_Msk (0x1U << ANA_INTSTS_INTSTS5_Pos) /*!< 0x00000020 */ +//#define ANA_INTSTS_INTSTS5 ANA_INTSTS_INTSTS5_Msk /*!< Interrupt flag of RTCPDN, this interrupt will be generated when RTCPDN rising or falling */ +//#define ANA_INTSTS_INTSTS6_Pos (6U) +//#define ANA_INTSTS_INTSTS6_Msk (0x1U << ANA_INTSTS_INTSTS6_Pos) /*!< 0x00000040 */ +//#define ANA_INTSTS_INTSTS6 ANA_INTSTS_INTSTS6_Msk /*!< Interrupt flag of SWT2BAT, this interrupt will be generated when SWT2BAT rising or falling */ +#define ANA_INTSTS_INTSTS7_Pos (7U) +#define ANA_INTSTS_INTSTS7_Msk (0x1U << ANA_INTSTS_INTSTS7_Pos) /*!< 0x00000080 */ +#define ANA_INTSTS_INTSTS7 ANA_INTSTS_INTSTS7_Msk /*!< Interrupt flag of POWALARMQPWRDN, this interrupt will be generated when POWALARM QPWRDN rising or falling */ +#define ANA_INTSTS_INTSTS8_Pos (8U) +#define ANA_INTSTS_INTSTS8_Msk (0x1U << ANA_INTSTS_INTSTS8_Pos) /*!< 0x00000100 */ +#define ANA_INTSTS_INTSTS8 ANA_INTSTS_INTSTS8_Msk /*!< Interrupt flag of PWRDROP, this interrupt will be generated when PWRDOP rising or falling */ +#define ANA_INTSTS_INTSTS10_Pos (10U) +#define ANA_INTSTS_INTSTS10_Msk (0x1U << ANA_INTSTS_INTSTS10_Pos) /*!< 0x00000400 */ +#define ANA_INTSTS_INTSTS10 ANA_INTSTS_INTSTS10_Msk /*!< Interrupt flag of POWLV, this interrupt will be generated when POWLV rising or falling */ +#define ANA_INTSTS_INTSTS11_Pos (11U) +#define ANA_INTSTS_INTSTS11_Msk (0x1U << ANA_INTSTS_INTSTS11_Pos) /*!< 0x00000800 */ +#define ANA_INTSTS_INTSTS11 ANA_INTSTS_INTSTS11_Msk /*!< Interrupt flag of sleep mode entry under PWRDROP is 0(i.e. VDCIN higher than threshold), this interrupt will be generated when PWRDROP is 0 and the entry of sleep or deep-sleep modes are detected. Programmer can enable this interrupt to force CPU wake-up from sleep or deep-sleep mode when PWRDROP is 0 */ +#define ANA_INTSTS_INTSTS12_Pos (12U) +#define ANA_INTSTS_INTSTS12_Msk (0x1U << ANA_INTSTS_INTSTS12_Pos) /*!< 0x00001000 */ +#define ANA_INTSTS_INTSTS12 ANA_INTSTS_INTSTS12_Msk /*!< ANA_REGx error flag. This interrupt is used to detect the error status of ANA_REGx, an automatically check0sum and parity check is applied to ANA_REGx, when external noise cause by ESD or other problem affect the setting of ANA_REGx, this interrupt will be asserted and programmer can use this flag to determine if it is necessary to recover the setting in the ANA_REGx */ +#define ANA_INTSTS_INTSTS13_Pos (13U) +#define ANA_INTSTS_INTSTS13_Msk (0x1U << ANA_INTSTS_INTSTS13_Pos) +#define ANA_INTSTS_INTSTS13 ANA_INTSTS_INTSTS13_Msk + +/************** Bits definition for ANA_INTEN register ******************/ +#define ANA_INTEN_INTEN0_Pos (0U) +#define ANA_INTEN_INTEN0_Msk (0x1U << ANA_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define ANA_INTEN_INTEN0 ANA_INTEN_INTEN0_Msk /*!< Interrupt enable control of manual ADC conversion done */ +#define ANA_INTEN_INTEN1_Pos (1U) +#define ANA_INTEN_INTEN1_Msk (0x1U << ANA_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define ANA_INTEN_INTEN1 ANA_INTEN_INTEN1_Msk /*!< Interrupt enable control of auto ADC conversion done */ +#define ANA_INTEN_INTEN2_Pos (2U) +#define ANA_INTEN_INTEN2_Msk (0x1U << ANA_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define ANA_INTEN_INTEN2 ANA_INTEN_INTEN2_Msk /*!< Interrupt and wake-up enable control of COMP1 */ +#define ANA_INTEN_INTEN3_Pos (3U) +#define ANA_INTEN_INTEN3_Msk (0x1U << ANA_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define ANA_INTEN_INTEN3 ANA_INTEN_INTEN3_Msk /*!< Interrupt and wake-up enable control of COMP2 */ +//#define ANA_INTEN_INTEN4_Pos (4U) +//#define ANA_INTEN_INTEN4_Msk (0x1U << ANA_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +//#define ANA_INTEN_INTEN4 ANA_INTEN_INTEN4_Msk /*!< Interrupt and wake-up enable control of MAINPDN falling */ +//#define ANA_INTEN_INTEN5_Pos (5U) +//#define ANA_INTEN_INTEN5_Msk (0x1U << ANA_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +//#define ANA_INTEN_INTEN5 ANA_INTEN_INTEN5_Msk /*!< Interrupt and wake-up enable control of RTCPDN falling */ +//#define ANA_INTEN_INTEN6_Pos (6U) +//#define ANA_INTEN_INTEN6_Msk (0x1U << ANA_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +//#define ANA_INTEN_INTEN6 ANA_INTEN_INTEN6_Msk /*!< Interrupt and wake-up enable control of SWT2BAT */ +#define ANA_INTEN_INTEN7_Pos (7U) +#define ANA_INTEN_INTEN7_Msk (0x1U << ANA_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define ANA_INTEN_INTEN7 ANA_INTEN_INTEN7_Msk /*!< Interrupt and wake-up enable control of POWALARM */ +#define ANA_INTEN_INTEN8_Pos (8U) +#define ANA_INTEN_INTEN8_Msk (0x1U << ANA_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define ANA_INTEN_INTEN8 ANA_INTEN_INTEN8_Msk /*!< Interrupt and wake-up enable control of PWRDROP */ +#define ANA_INTEN_INTEN10_Pos (10U) +#define ANA_INTEN_INTEN10_Msk (0x1U << ANA_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define ANA_INTEN_INTEN10 ANA_INTEN_INTEN10_Msk /*!< Interrupt and wake-up enable control of POWLV */ +#define ANA_INTEN_INTEN11_Pos (11U) +#define ANA_INTEN_INTEN11_Msk (0x1U << ANA_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define ANA_INTEN_INTEN11 ANA_INTEN_INTEN11_Msk /*!< Interrupt and wake-up enable control of sleep mode entry */ +#define ANA_INTEN_INTEN12_Pos (12U) +#define ANA_INTEN_INTEN12_Msk (0x1U << ANA_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define ANA_INTEN_INTEN12 ANA_INTEN_INTEN12_Msk /*!< Interrupt and wake-up enable control of ANA_REGx error */ +#define ANA_INTEN_INTEN13_Pos (13U) +#define ANA_INTEN_INTEN13_Msk (0x1U << ANA_INTEN_INTEN13_Pos) /*!< 0x00001000 */ +#define ANA_INTEN_INTEN13 ANA_INTEN_INTEN13_Msk + +/************** Bits definition for ANA_ADCCTRL register ******************/ +#define ANA_ADCCTRL_MCH_Pos (0U) +#define ANA_ADCCTRL_MCH_Msk (0xFU << ANA_ADCCTRL_MCH_Pos) /*!< 0x0000000F */ +#define ANA_ADCCTRL_MCH ANA_ADCCTRL_MCH_Msk /*!< Manual ADC channel control */ +#define ANA_ADCCTRL_ACH_Pos (4U) +#define ANA_ADCCTRL_ACH_Msk (0xFU << ANA_ADCCTRL_ACH_Pos) /*!< 0x000000F0 */ +#define ANA_ADCCTRL_ACH ANA_ADCCTRL_ACH_Msk /*!< Auto ADC channel control */ +#define ANA_ADCCTRL_CLKDIV_Pos (8U) +#define ANA_ADCCTRL_CLKDIV_Msk (0xFU << ANA_ADCCTRL_CLKDIV_Pos) /*!< 0x00000700 */ +#define ANA_ADCCTRL_CLKDIV ANA_ADCCTRL_CLKDIV_Msk /*!< ADC clock divider, the ADC main clock is necessary to be 3.2768MHz, so when different clock source is selected, it is necessary to set correct clock division rate to generate ADC clock */ +#define ANA_ADCCTRL_CLKDIV_1 (0x0U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_2 (0x1U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_3 (0x2U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_4 (0x3U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_5 (0x4U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_6 (0x5U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_7 (0x6U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_8 (0x7U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_9 (0x8U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_10 (0x9U << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_11 (0xAU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_12 (0xBU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_13 (0xCU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_14 (0xDU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_15 (0xEU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKDIV_16 (0xFU << ANA_ADCCTRL_CLKDIV_Pos) +#define ANA_ADCCTRL_CLKSEL_Pos (12U) +#define ANA_ADCCTRL_CLKSEL_Msk (0x1U << ANA_ADCCTRL_CLKSEL_Pos) /*!< 0x00001000 */ +#define ANA_ADCCTRL_CLKSEL ANA_ADCCTRL_CLKSEL_Msk /*!< ADC clock source selection */ +#define ANA_ADCCTRL_AEN_Pos (16U) +#define ANA_ADCCTRL_AEN_Msk (0x7U << ANA_ADCCTRL_AEN_Pos) /*!< 0x00070000 */ +#define ANA_ADCCTRL_AEN ANA_ADCCTRL_AEN_Msk /*!< Auto ADC conversion enable control register */ +#define ANA_ADCCTRL_AEN_OFF (0x0U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR0 (0x4U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR1 (0x5U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR2 (0x6U << ANA_ADCCTRL_AEN_Pos) +#define ANA_ADCCTRL_AEN_TMR3 (0x7U << ANA_ADCCTRL_AEN_Pos) +//#define ANA_ADCCTRL_STOP_Pos (19U) +//#define ANA_ADCCTRL_STOP_Msk (0x1U << ANA_ADCCTRL_STOP_Pos) /*!< 0x00080000 */ +//#define ANA_ADCCTRL_STOP ANA_ADCCTRL_STOP_Msk /*!< Force stop current ADC conversion process */ +#define ANA_ADCCTRL_MMODE_Pos (20U) +#define ANA_ADCCTRL_MMODE_Msk (0x1U << ANA_ADCCTRL_MMODE_Pos) /*!< 0x00100000 */ +#define ANA_ADCCTRL_MMODE ANA_ADCCTRL_MMODE_Msk /*!< Manual ADC mode control */ +#define ANA_ADCCTRL_AMODE_Pos (21U) +#define ANA_ADCCTRL_AMODE_Msk (0x1U << ANA_ADCCTRL_AMODE_Pos) /*!< 0x00200000 */ +#define ANA_ADCCTRL_AMODE ANA_ADCCTRL_AMODE_Msk /*!< Auto ADC mode control */ +#define ANA_ADCCTRL_DSRSEL_Pos (22U) +#define ANA_ADCCTRL_DSRSEL_Msk (0x3U << ANA_ADCCTRL_DSRSEL_Pos) /*!< 0x00C00000 */ +#define ANA_ADCCTRL_DSRSEL ANA_ADCCTRL_DSRSEL_Msk /*!< CIC down sampling rate control register. The higher down-sampling rate, the higher output data stability, and also lower sampling rate */ +#define ANA_ADCCTRL_DSRSEL_512 (0x0U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_DSRSEL_256 (0x1U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_DSRSEL_128 (0x2U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_DSRSEL_64 (0x3U << ANA_ADCCTRL_DSRSEL_Pos) +#define ANA_ADCCTRL_CICSKIP_Pos (24U) +#define ANA_ADCCTRL_CICSKIP_Msk (0x7U << ANA_ADCCTRL_CICSKIP_Pos) /*!< 0x07000000 */ +#define ANA_ADCCTRL_CICSKIP ANA_ADCCTRL_CICSKIP_Msk /*!< CIC output skip control register. This register is used to control how many samples will be skipped at the beginning of ADC sample. If CICAON is 1 and the ADC channel is not changed, the CIC output will not be skipped by the ADC controller, this can be used for high speed capture to single channel */ +#define ANA_ADCCTRL_CICSKIP_4 (0x0U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_5 (0x1U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_6 (0x2U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_7 (0x3U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_0 (0x4U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_1 (0x5U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_2 (0x6U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSKIP_3 (0x7U << ANA_ADCCTRL_CICSKIP_Pos) +#define ANA_ADCCTRL_CICSCA_Pos (27U) +#define ANA_ADCCTRL_CICSCA_Msk (0x1U << ANA_ADCCTRL_CICSCA_Pos) /*!< 0x08000000 */ +#define ANA_ADCCTRL_CICSCA ANA_ADCCTRL_CICSCA_Msk /*!< CIC output scale-down selection */ +#define ANA_ADCCTRL_CICINV_Pos (28U) +#define ANA_ADCCTRL_CICINV_Msk (0x1U << ANA_ADCCTRL_CICINV_Pos) /*!< 0x10000000 */ +#define ANA_ADCCTRL_CICINV ANA_ADCCTRL_CICINV_Msk /*!< CIC filter input inversion */ +#define ANA_ADCCTRL_CICAON_Pos (29U) +#define ANA_ADCCTRL_CICAON_Msk (0x1U << ANA_ADCCTRL_CICAON_Pos) /*!< 0x20000000 */ +#define ANA_ADCCTRL_CICAON ANA_ADCCTRL_CICAON_Msk /*!< CIC filter always on control register */ +//#define ANA_ADCCTRL_16CH_Pos (30U) +//#define ANA_ADCCTRL_16CH_Msk (0x1U << ANA_ADCCTRL_16CH_Pos) /*!< 0x40000000 */ +//#define ANA_ADCCTRL_16CH ANA_ADCCTRL_16CH_Msk /*!< ADC multi channels scan control register */ +#define ANA_ADCCTRL_MTRIG_Pos (31U) +#define ANA_ADCCTRL_MTRIG_Msk (0x1U << ANA_ADCCTRL_MTRIG_Pos) /*!< 0x80000000 */ +#define ANA_ADCCTRL_MTRIG ANA_ADCCTRL_MTRIG_Msk /*!< Manual ADC trigger */ + +/************** Bits definition for ANA_ADCDATAx register ******************/ +#define ANA_ADCDATA_Pos (0U) +#define ANA_ADCDATA_Msk (0xFFFFU << ANA_ADCDATA_Pos) /*!< 0x0000FFFF */ +#define ANA_ADCDATA ANA_ADCDATA_Msk /*!< The result of ADC conversion will be stored in these registers */ + +/************** Bits definition for ANA_CMPCNTx register ******************/ +#define ANA_CMPCNT_CNT_Pos (0U) +#define ANA_CMPCNT_CNT_Msk (0xFFFFFFFFU << ANA_CMPCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define ANA_CMPCNT_CNT ANA_CMPCNT_CNT_Msk /*!< This register store the happen times of comparator x according to the setting in COMPx_SEL */ + +/************** Bits definition for ANA_MISC register ******************/ +//#define ANA_MISC_FORCEPWR2MP_Pos (1U) +//#define ANA_MISC_FORCEPWR2MP_Msk (0x1U << ANA_MISC_FORCEPWR2MP_Pos) /*!< 0x00000002 */ +//#define ANA_MISC_FORCEPWR2MP ANA_MISC_FORCEPWR2MP_Msk /*!< Force BATRTC feed into VDDIO function when doing RTC auto-calibration control */ +#define ANA_MISC_TADCTH_Pos (4U) +#define ANA_MISC_TADCTH_Msk (0x03UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH ANA_MISC_TADCTH_Msk +#define ANA_MISC_TADCTH_0 (0x00UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH_1 (0x01UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH_2 (0x02UL << ANA_MISC_TADCTH_Pos) +#define ANA_MISC_TADCTH_3 (0x03UL << ANA_MISC_TADCTH_Pos) + +/******************************************************************************/ +/* */ +/* RTC controller (RTC) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for RTC_SEC register ******************/ +#define RTC_SEC_Pos (0U) +#define RTC_SEC_Msk (0x7FU << RTC_SEC_Pos) /*!< 0x0000007F */ +#define RTC_SEC_SEC RTC_SEC_Msk /*!< RTC second register */ + +/************** Bits definition for RTC_MIN register ******************/ +#define RTC_MIN_Pos (0U) +#define RTC_MIN_Msk (0x7FU << RTC_MIN_Pos) /*!< 0x0000007F */ +#define RTC_MIN_MIN RTC_MIN_Msk /*!< RTC minute register */ + +/************** Bits definition for RTC_HOUR register ******************/ +#define RTC_HOUR_Pos (0U) +#define RTC_HOUR_Msk (0x3FU << RTC_HOUR_Pos) /*!< 0x0000003F */ +#define RTC_HOUR_HOUR RTC_HOUR_Msk /*!< RTC hour register */ + +/************** Bits definition for RTC_DAY register ******************/ +#define RTC_DAY_Pos (0U) +#define RTC_DAY_Msk (0x3FU << RTC_DAY_Pos) /*!< 0x0000003F */ +#define RTC_DAY_DAY RTC_DAY_Msk /*!< RTC day register */ + +/************** Bits definition for RTC_WEEK register ******************/ +#define RTC_WEEK_Pos (0U) +#define RTC_WEEK_Msk (0x7U << RTC_WEEK_Pos) /*!< 0x00000007 */ +#define RTC_WEEK_WEEK RTC_WEEK_Msk /*!< RTC week-day register */ + +/************** Bits definition for RTC_MON register ******************/ +#define RTC_MON_Pos (0U) +#define RTC_MON_Msk (0x1FU << RTC_MON_Pos) /*!< 0x0000001F */ +#define RTC_MON_MON RTC_MON_Msk /*!< RTC month register */ + +/************** Bits definition for RTC_YEAR register ******************/ +#define RTC_YEAR_Pos (0U) +#define RTC_YEAR_Msk (0xFFU << RTC_YEAR_Pos) /*!< 0x000000FF */ +#define RTC_YEAR_YEAR RTC_YEAR_Msk /*!< RTC year register */ + +/************** Bits definition for RTC_WKUSEC register ******************/ +#define RTC_WKUSEC_Pos (0U) +#define RTC_WKUSEC_Msk (0x3FU << RTC_WKUSEC_Pos) /*!< 0x0000003F */ +#define RTC_WKUSEC_WKUSEC RTC_WKUSEC_Msk /*!< This register is used to control the multi-second wake-up function. The wake-up period is (WKUSEC + 1)*1 second */ + +/************** Bits definition for RTC_WKUMIN register ******************/ +#define RTC_WKUMIN_Pos (0U) +#define RTC_WKUMIN_Msk (0x3FU << RTC_WKUMIN_Pos) /*!< 0x0000003F */ +#define RTC_WKUMIN_WKUMIN RTC_WKUMIN_Msk /*!< This register is used to control the multi-minute wake-up function. The wake-up period is (WKUMIN + 1)*1 minute */ + +/************** Bits definition for RTC_WKUHOUR register ******************/ +#define RTC_WKUHOUR_Pos (0U) +#define RTC_WKUHOUR_Msk (0x1FU << RTC_WKUHOUR_Pos) /*!< 0x0000001F */ +#define RTC_WKUHOUR_WKUHOUR RTC_WKUHOUR_Msk /*!< This register is used to control the multi-hour wake-up function. The wake-up period is (WKUHOUR + 1)*1 hour */ + +/************** Bits definition for RTC_WKUCNT register ******************/ +#define RTC_WKUCNT_WKUCNT_Pos (0U) +#define RTC_WKUCNT_WKUCNT_Msk (0xFFFFFFU << RTC_WKUCNT_WKUCNT_Pos) /*!< 0x00FFFFFF */ +#define RTC_WKUCNT_WKUCNT RTC_WKUCNT_WKUCNT_Msk /*!< This register is used to control the 32K counter wake-up function. The wake-up period is (WKUCNT + 1)*Counter Clock */ +#define RTC_WKUCNT_CNTSEL_Pos (24U) +#define RTC_WKUCNT_CNTSEL_Msk (0x3U << RTC_WKUCNT_CNTSEL_Pos) /*!< 0x03000000 */ +#define RTC_WKUCNT_CNTSEL RTC_WKUCNT_CNTSEL_Msk /*!< This is register is used to set the counter clock of WKUCNT */ +#define RTC_WKUCNT_CNTSEL_0 (0x0U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_1 (0x1U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_2 (0x2U << RTC_WKUCNT_CNTSEL_Pos) +#define RTC_WKUCNT_CNTSEL_3 (0x3U << RTC_WKUCNT_CNTSEL_Pos) + +/************** Bits definition for RTC_CAL register ******************/ +#define RTC_CAL_Pos (0U) +#define RTC_CAL_Msk (0x3FFFU << RTC_CAL_Pos) /*!< 0x00003FFF */ +#define RTC_CAL_CAL RTC_CAL_Msk /*!< RTC 32768 calibration register, the RTC engine will do calibration for every 30 seconds, the internal counter will count 32768 times during 1~29 second. At the 30 second, it will count [32768-(CAL-1)] for a second, so it can let the average 1 second pulse in 30 seconds become an accurate 1 second pulse */ + +/************** Bits definition for RTC_DIV register ******************/ +#define RTC_DIV_RTCDIV_Pos (0U) +#define RTC_DIV_RTCDIV_Msk (0x3FFFFFFU << RTC_DIV_RTCDIV_Pos) /*!< 0x03FFFFFF */ +#define RTC_DIV_RTCDIV RTC_DIV_RTCDIV_Msk /*!< This register is used to store capture value during capture mode of used to generate divider output during generation mode. The output frequency is PCLK/(2*(RTCDIV+1)) */ + +/************** Bits definition for RTC_CTL register ******************/ +//#define RTC_CTL_MODE_Pos (0U) +//#define RTC_CTL_MODE_Msk (0x3U << RTC_CTL_MODE_Pos) /*!< 0x00000003 */ +//#define RTC_CTL_MODE RTC_CTL_MODE_Msk /*!< This register is used to control the capture/divider mode of high frequency divider */ +//#define RTC_CTL_MODE_0 (0x0U << RTC_CTL_MODE_Pos) +//#define RTC_CTL_MODE_1 (0x1U << RTC_CTL_MODE_Pos) +//#define RTC_CTL_MODE_2 (0x2U << RTC_CTL_MODE_Pos) +//#define RTC_CTL_MODE_3 (0x3U << RTC_CTL_MODE_Pos) +#define RTC_CTL_RTCPLLOE_Pos (2U) +#define RTC_CTL_RTCPLLOE_Msk (0x1U << RTC_CTL_RTCPLLOE_Pos) /*!< 0x00000004 */ +#define RTC_CTL_RTCPLLOE RTC_CTL_RTCPLLOE_Msk /*!< RTCPLL Divider output enable, this register is used to control the RTCPLL divider output */ +//#define RTC_CTL_SPOE_Pos (3U) +//#define RTC_CTL_SPOE_Msk (0x1U << RTC_CTL_SPOE_Pos) /*!< 0x00000008 */ +//#define RTC_CTL_SPOE RTC_CTL_SPOE_Msk /*!< RTC second pulse output enable, this register is used to control the RTC second pulse output */ + +///************** Bits definition for RTC_ITV register ******************/ +//#define RTC_ITV_ITV_Pos (0U) +//#define RTC_ITV_ITV_Msk (0x7U << RTC_ITV_ITV_Pos) /*!< 0x00000007 */ +//#define RTC_ITV_ITV RTC_ITV_ITV_Msk /*!< This register is used to control wake-up and interrupt interval of RTC. This register operates independently with RTC_WKUSEC and RTC_WKUMIN and RTC_WKUHOUR */ +//#define RTC_ITV_ITV_0 (0x0U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_1 (0x1U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_2 (0x2U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_3 (0x3U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_4 (0x4U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_5 (0x5U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_6 (0x6U << RTC_ITV_ITV_Pos) +//#define RTC_ITV_ITV_7 (0x7U << RTC_ITV_ITV_Pos) +// +///************** Bits definition for RTC_SITV register ******************/ +//#define RTC_SITV_SITV_Pos (0U) +//#define RTC_SITV_SITV_Msk (0x3FU << RTC_SITV_SITV_Pos) /*!< 0x0000003F */ +//#define RTC_SITV_SITV RTC_SITV_SITV_Msk /*!< Multi second wake-up interval control register. This register is valid only when ITV is 7 and SITVEN is 1 */ +//#define RTC_SITV_SITVEN_Pos (6U) +//#define RTC_SITV_SITVEN_Msk (0x1U << RTC_SITV_SITVEN_Pos) /*!< 0x00000040 */ +//#define RTC_SITV_SITVEN RTC_SITV_SITVEN_Msk /*!< Multi Second interval enable register, this register is valid only when ITV is set to 7 */ + +/************** Bits definition for RTC_PWD register ******************/ +#define RTC_PWD_PWDEN_Pos (0U) +#define RTC_PWD_PWDEN_Msk (0x1U << RTC_PWD_PWDEN_Pos) /*!< 0x00000001 */ +#define RTC_PWD_PWDEN RTC_PWD_PWDEN_Msk /*!< This register is used to protect the RTC_CE port��s access. Before access the RTC_CE, programmer should write 0x5AA55AA5 to this port, and the PWDEN will be set to 1. This bit will be cleared automatically after any write to RTC_CE port. Which means programmer should write to this port again before next access to RTC_CE port */ + +/************** Bits definition for RTC_CE register ******************/ +#define RTC_CE_CE_Pos (0U) +#define RTC_CE_CE_Msk (0x1U << RTC_CE_CE_Pos) /*!< 0x00000001 */ +#define RTC_CE_CE RTC_CE_CE_Msk /*!< This register is used to unlock the access to RTC register. This register can be only when PWDEN is set to 1 and 0xA55AA55B is written to this register. After this bit is set to 1, the RTC register can be programmed, but the actual update to RTC core will be start after this bit is cleared to 0. To clear this bit, the PWDEN should be set to 1 and 0xA55AA55A should be written to this register */ +#define RTC_CE_BSY_Pos (1U) +#define RTC_CE_BSY_Msk (0x1U << RTC_CE_BSY_Pos) /*!< 0x00000002 */ +#define RTC_CE_BSY RTC_CE_BSY_Msk /*!< This flag is used to indicated the RTC update procedure or RTC read procedure is ongoing. This bit will be set immediately after the CE is cleared from 1 to 0 or when RTC_LOAD port is read by CPU. This bit will cleared automatically after the read or write procedure is done. Programmer can polling this bit to know if the RTC update is done or not. The update or read procedure take around 3 32K period, which is around 100 us */ + +/************** Bits definition for RTC_LOAD register ******************/ +#define RTC_LOAD_LOAD_Pos (0U) +#define RTC_LOAD_LOAD_Msk (0xFFFFFFFFU << RTC_LOAD_LOAD_Pos) /*!< 0xFFFFFFFF */ +#define RTC_LOAD_LOAD RTC_LOAD_LOAD_Msk /*!< This register is used to let RTC engine read data from RTC core. When programmer read from this port, the current time will be latched and programmer can read data from RTC_SEC ~ RTC_YEAR register. The read procedure will takes 3 32K cycles, programmer can check the BSY bit to know if the procedure is done. The read data from this port is invalid */ + +/************** Bits definition for RTC_INTSTS register ******************/ +//#define RTC_INTSTS_INTSTS0_Pos (0U) +//#define RTC_INTSTS_INTSTS0_Msk (0x1U << RTC_INTSTS_INTSTS0_Pos) /*!< 0x00000001 */ +//#define RTC_INTSTS_INTSTS0 RTC_INTSTS_INTSTS0_Msk /*!< Interrupt status 0, this interrupt is controlled by ITV and SITV. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS1_Pos (1U) +#define RTC_INTSTS_INTSTS1_Msk (0x1U << RTC_INTSTS_INTSTS1_Pos) /*!< 0x00000002 */ +#define RTC_INTSTS_INTSTS1 RTC_INTSTS_INTSTS1_Msk /*!< Interrupt status 1, this interrupt will be set when illegal time format is written into RTC core. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS2_Pos (2U) +#define RTC_INTSTS_INTSTS2_Msk (0x1U << RTC_INTSTS_INTSTS2_Pos) /*!< 0x00000004 */ +#define RTC_INTSTS_INTSTS2 RTC_INTSTS_INTSTS2_Msk /*!< Interrupt status 2, this interrupt will be set when multi-second interrupt period set by WKUSEC is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS3_Pos (3U) +#define RTC_INTSTS_INTSTS3_Msk (0x1U << RTC_INTSTS_INTSTS3_Pos) /*!< 0x00000008 */ +#define RTC_INTSTS_INTSTS3 RTC_INTSTS_INTSTS3_Msk /*!< Interrupt status 3, this interrupt will be set when multi-minute interrupt period set by WKUMIN is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS4_Pos (4U) +#define RTC_INTSTS_INTSTS4_Msk (0x1U << RTC_INTSTS_INTSTS4_Pos) /*!< 0x00000010 */ +#define RTC_INTSTS_INTSTS4 RTC_INTSTS_INTSTS4_Msk /*!< Interrupt status 4, this interrupt will be set when multi-hour interrupt period set by WKUHOUR is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS5_Pos (5U) +#define RTC_INTSTS_INTSTS5_Msk (0x1U << RTC_INTSTS_INTSTS5_Pos) /*!< 0x00000020 */ +#define RTC_INTSTS_INTSTS5 RTC_INTSTS_INTSTS5_Msk /*!< Interrupt status 5, this interrupt will be set when mid-night (00:00) is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS6_Pos (6U) +#define RTC_INTSTS_INTSTS6_Msk (0x1U << RTC_INTSTS_INTSTS6_Pos) /*!< 0x00000040 */ +#define RTC_INTSTS_INTSTS6 RTC_INTSTS_INTSTS6_Msk /*!< Interrupt status 6, this interrupt will be set when 32K counter interrupt period set by WKUCNT is reach. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS7_Pos (7U) +#define RTC_INTSTS_INTSTS7_Msk (0x1U << RTC_INTSTS_INTSTS7_Pos) /*!< 0x00000080 */ +#define RTC_INTSTS_INTSTS7 RTC_INTSTS_INTSTS7_Msk /*!< Interrupt status 7, this interrupt will be set when an auto calibration is done. Write 1 to clear this bit */ +#define RTC_INTSTS_INTSTS8_Pos (8U) +#define RTC_INTSTS_INTSTS8_Msk (0x1U << RTC_INTSTS_INTSTS8_Pos) /*!< 0x00000100 */ +#define RTC_INTSTS_INTSTS8 RTC_INTSTS_INTSTS8_Msk /*!< Interrupt status 8, this interrupt will be set when an illegal write to CE register is happened. The illegal write means the BSY bit is still 1 but CE is set to 1 again or RTC_LOAD port is read again. Write 1 to clear this bit */ +#define RTC_INTSTS_ACBSY_Pos (9U) +#define RTC_INTSTS_ACBSY_Msk (0x1U << RTC_INTSTS_ACBSY_Pos) /*!< 0x00000200 */ +#define RTC_INTSTS_ACBSY RTC_INTSTS_ACBSY_Msk /*!< Auto-calibration busy flag */ + +/************** Bits definition for RTC_INTEN register ******************/ +//#define RTC_INTEN_INTEN0_Pos (0U) +//#define RTC_INTEN_INTEN0_Msk (0x1U << RTC_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +//#define RTC_INTEN_INTEN0 RTC_INTEN_INTEN0_Msk /*!< Interrupt enable 0, when this bit is 1, the INTSTS0 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN1_Pos (1U) +#define RTC_INTEN_INTEN1_Msk (0x1U << RTC_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define RTC_INTEN_INTEN1 RTC_INTEN_INTEN1_Msk /*!< Interrupt enable 1, when this bit is 1, the INTSTS1 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN2_Pos (2U) +#define RTC_INTEN_INTEN2_Msk (0x1U << RTC_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define RTC_INTEN_INTEN2 RTC_INTEN_INTEN2_Msk /*!< Interrupt enable 2, when this bit is 1, the INTSTS2 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN3_Pos (3U) +#define RTC_INTEN_INTEN3_Msk (0x1U << RTC_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define RTC_INTEN_INTEN3 RTC_INTEN_INTEN3_Msk /*!< Interrupt enable 3, when this bit is 1, the INTSTS3 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN4_Pos (4U) +#define RTC_INTEN_INTEN4_Msk (0x1U << RTC_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define RTC_INTEN_INTEN4 RTC_INTEN_INTEN4_Msk /*!< Interrupt enable 4, when this bit is 1, the INTSTS3 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN5_Pos (5U) +#define RTC_INTEN_INTEN5_Msk (0x1U << RTC_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define RTC_INTEN_INTEN5 RTC_INTEN_INTEN5_Msk /*!< Interrupt enable 5, when this bit is 1, the INTSTS5 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN6_Pos (6U) +#define RTC_INTEN_INTEN6_Msk (0x1U << RTC_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define RTC_INTEN_INTEN6 RTC_INTEN_INTEN6_Msk /*!< Interrupt enable 6, when this bit is 1, the INTSTS6 interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN7_Pos (7U) +#define RTC_INTEN_INTEN7_Msk (0x1U << RTC_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define RTC_INTEN_INTEN7 RTC_INTEN_INTEN7_Msk /*!< Interrupt enable 7, when this bit is 1, the INTSTS7 can be set, and interrupt will be asserted to CPU and wake-up signal will be asserted to PMU controller */ +#define RTC_INTEN_INTEN8_Pos (8U) +#define RTC_INTEN_INTEN8_Msk (0x1U << RTC_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define RTC_INTEN_INTEN8 RTC_INTEN_INTEN8_Msk /*!< Interrupt enable 8, when this bit is 1 and INTSTS86 is set, and interrupt will be asserted to CPU */ + +/************** Bits definition for RTC_PSCA register ******************/ +#define RTC_PSCA_PSCA_Pos (0U) +#define RTC_PSCA_PSCA_Msk (0x3U << RTC_PSCA_PSCA_Pos) /*!< 0x00000003 */ +#define RTC_PSCA_PSCA RTC_PSCA_PSCA_Msk /*!< This register is used to control the RTC clock pre-scaler. When slow down the RTC clock, it can significantly reduce the power under sleep or deep-sleep mode */ +#define RTC_PSCA_PSCA_0 (0x0U << RTC_PSCA_PSCA_Pos) +#define RTC_PSCA_PSCA_1 (0x1U << RTC_PSCA_PSCA_Pos) +//#define RTC_PSCA_PSCA_2 (0x2U << RTC_PSCA_PSCA_Pos) +//#define RTC_PSCA_PSCA_3 (0x3U << RTC_PSCA_PSCA_Pos) + +/************** Bits definition for RTC_ACCTRL register ******************/ +#define RTC_ACCTRL_ACEN_Pos (0U) +#define RTC_ACCTRL_ACEN_Msk (0x1U << RTC_ACCTRL_ACEN_Pos) /*!< 0x00000001 */ +#define RTC_ACCTRL_ACEN RTC_ACCTRL_ACEN_Msk /*!< Auto-calibration enable control register */ +#define RTC_ACCTRL_MANU_Pos (1U) +#define RTC_ACCTRL_MANU_Msk (0x1U << RTC_ACCTRL_MANU_Pos) /*!< 0x00000002 */ +#define RTC_ACCTRL_MANU RTC_ACCTRL_MANU_Msk /*!< Auto-calibration manual trigger function. Write 1 to this register will trigger an auto-calibration procedure. This bit will be cleared to 0 when the procedure is done */ +#define RTC_ACCTRL_ADCSEL_Pos (3U) +#define RTC_ACCTRL_ADCSEL_Msk (0x1U << RTC_ACCTRL_ADCSEL_Pos) /*!< 0x00000008 */ +#define RTC_ACCTRL_ADCSEL RTC_ACCTRL_ADCSEL_Msk /*!< ADC source select register */ +#define RTC_ACCTRL_ACCLK_Pos (4U) +#define RTC_ACCTRL_ACCLK_Msk (0x3U << RTC_ACCTRL_ACCLK_Pos) /*!< 0x00000030 */ +#define RTC_ACCTRL_ACCLK RTC_ACCTRL_ACCLK_Msk /*!< Auto-trigger clock source selection */ +#define RTC_ACCTRL_ACCLK_0 (0x0U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACCLK_1 (0x1U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACCLK_2 (0x2U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACCLK_3 (0x3U << RTC_ACCTRL_ACCLK_Pos) +#define RTC_ACCTRL_ACDEL_Pos (6U) +#define RTC_ACCTRL_ACDEL_Msk (0x3U << RTC_ACCTRL_ACDEL_Pos) /*!< 0x000000C0 */ +#define RTC_ACCTRL_ACDEL RTC_ACCTRL_ACDEL_Msk /*!< Auto-calibration delay period selection, before doing auto-calibration, a specified delay will be applied to ensure the main power is stable */ +#define RTC_ACCTRL_ACDEL_0 (0x0U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACDEL_1 (0x1U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACDEL_2 (0x2U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACDEL_3 (0x3U << RTC_ACCTRL_ACDEL_Pos) +#define RTC_ACCTRL_ACPER_Pos (8U) +#define RTC_ACCTRL_ACPER_Msk (0x3FU << RTC_ACCTRL_ACPER_Pos) /*!< 0x00003F00 */ +#define RTC_ACCTRL_ACPER RTC_ACCTRL_ACPER_Msk /*!< Auto trigger period control register, the actual period is controlled by (ACPER + 1)*ACCLK. For example, when ACCLK is set to 2 (1 minute), and ACPER is set to 5, then the auto trigger period is (5+1)*1 minute = 6 minutes */ + +/************** Bits definition for RTC_ACTI register ******************/ +#define RTC_ACTI_ACTI_Pos (0U) +#define RTC_ACTI_ACTI_Msk (0x3FFFU << RTC_ACTI_ACTI_Pos) /*!< 0x00003FFF */ +#define RTC_ACTI_ACTI RTC_ACTI_ACTI_Msk /*!< Auto-calibration Ti control register. This register is used to store the Ti value which is used as the center temperature during calibration. This register is 8 bits integer and 8 bits fraction value. For example, 0x1880 means 24.5 degree. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ + +/************** Bits definition for RTC_ACF200 register ******************/ +#define RTC_ACF200_F200_Pos (0U) +#define RTC_ACF200_F200_Msk (0x3FFFFFFU << RTC_ACF200_F200_Pos) /*!< 0x03FFFFFF */ +#define RTC_ACF200_F200 RTC_ACF200_F200_Msk /*!< Auto-calibration F200 control register. This register is used to store the current PCLK speed value which is used for the calculation of PLLDIV value. This register is 26 bits integer */ + +/************** Bits definition for RTC_ACADCW register ******************/ +#define RTC_ACADCW_ADCW_Pos (0U) +#define RTC_ACADCW_ADCW_Msk (0xFFFU << RTC_ACADCW_ADCW_Pos) /*!< 0x00000FFF */ +#define RTC_ACADCW_ADCW RTC_ACADCW_ADCW_Msk /*!< Auto-calibration manual ADC value control register. This register is used to store the manual ADC value which is used for the calculation for temperature. By default, the auto-calibration engine will read the ADC value automatically, but if programmer wishes to control the ADC value manually, this register can be used to control the ADC value read by the engine. This register is 12 bits integer. This register is valid only when ADCSEL is set to 1 */ + +/************** Bits definition for RTC_ACP0 register ******************/ +#define RTC_ACP_P0_Pos (0U) +#define RTC_ACP_P0_Msk (0xFFFF << RTC_ACP_P0_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P0 RTC_ACP_P0_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP1 register ******************/ +#define RTC_ACP_P1_Pos (0U) +#define RTC_ACP_P1_Msk (0xFFFF << RTC_ACP_P1_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P1 RTC_ACP_P1_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP2 register ******************/ +#define RTC_ACP_P2_Pos (0U) +#define RTC_ACP_P2_Msk (0xFFFFFFFF << RTC_ACP_P2_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ACP_P2 RTC_ACP_P2_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP3 register ******************/ +#define RTC_ACP_P3_Pos (0U) +#define RTC_ACP_P3_Msk (0xFFFF << RTC_ACP_P3_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P3 RTC_ACP_P3_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP4 register ******************/ +#define RTC_ACP_P4_Pos (0U) +#define RTC_ACP_P4_Msk (0xFFFF << RTC_ACP_P4_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P4 RTC_ACP_P4_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP5 register ******************/ +#define RTC_ACP_P5_Pos (0U) +#define RTC_ACP_P5_Msk (0xFFFF << RTC_ACP_P5_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P5 RTC_ACP_P5_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP6 register ******************/ +#define RTC_ACP_P6_Pos (0U) +#define RTC_ACP_P6_Msk (0xFFFF << RTC_ACP_P6_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P6 RTC_ACP_P6_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACP7 register ******************/ +#define RTC_ACP_P7_Pos (0U) +#define RTC_ACP_P7_Msk (0xFFFF << RTC_ACP_P7_Pos) /*!< 0x0000FFFF */ +#define RTC_ACP_P7 RTC_ACP_P7_Msk /*!< The P0~P7 registers are used for auto-calibration. Only P2 is 32 bits signed value, other P0~P7 is 16 bits signed value */ + +/************** Bits definition for RTC_ACK1 register ******************/ +#define RTC_ACK_K1_Pos (0U) +#define RTC_ACK_K1_Msk (0xFFFFU << RTC_ACK_K1_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K1 RTC_ACK_K1_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK2 register ******************/ +#define RTC_ACK_K2_Pos (0U) +#define RTC_ACK_K2_Msk (0xFFFFU << RTC_ACK_K2_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K2 RTC_ACK_K2_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK3 register ******************/ +#define RTC_ACK_K3_Pos (0U) +#define RTC_ACK_K3_Msk (0xFFFFU << RTC_ACK_K3_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K3 RTC_ACK_K3_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK4 register ******************/ +#define RTC_ACK_K4_Pos (0U) +#define RTC_ACK_K4_Msk (0xFFFFU << RTC_ACK_K4_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K4 RTC_ACK_K4_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACK5 register ******************/ +#define RTC_ACK_K5_Pos (0U) +#define RTC_ACK_K5_Msk (0xFFFFU << RTC_ACK_K5_Pos) /*!< 0x0000FFFF */ +#define RTC_ACK_K5 RTC_ACK_K5_Msk /*!< The K1~K5 registers are used for auto-calibration. These registers are 16 bits signed register. Hardware will auto select a suitable Kx according to calculated temperature and represent on P3 */ + +/************** Bits definition for RTC_ACTEMP register ******************/ +#define RTC_ACTEMP_TEMP_Pos (0U) +#define RTC_ACTEMP_TEMP_Msk (0xFFFFU << RTC_ACTEMP_TEMP_Pos) /*!< 0x0000FFFF */ +#define RTC_ACTEMP_TEMP RTC_ACTEMP_TEMP_Msk /*!< This register is used to store the calculated result of current temperature. This register will be updated automatically after the auto-calibration procedure is done */ + +/************** Bits definition for RTC_ACPPM register ******************/ +#define RTC_ACPPM_PPM_Pos (0U) +#define RTC_ACPPM_PPM_Msk (0xFFFFU << RTC_ACPPM_PPM_Pos) /*!< 0x0000FFFF */ +#define RTC_ACPPM_PPM RTC_ACPPM_PPM_Msk /*!< This register is used to store the calculated result of current temperature. This register will be updated automatically after the auto-calibration procedure is done. This register is a 16 bits signed value and the unit of this register is 0.1 PPM */ + +/************** Bits definition for RTC_ACADCR register ******************/ +#define RTC_ACADCR_ADCR_Pos (0U) +#define RTC_ACADCR_ADCR_Msk (0xFFFFU << RTC_ACADCR_ADCR_Pos) /*!< 0x0000FFFF */ +#define RTC_ACADCR_ADCR RTC_ACADCR_ADCR_Msk /*!< This register is used to represent the ADC value used by the auto-calibration engine, the value of this register is the 12 bits ADC value * 8. When the ADCSEL is 0, it will store the value read from ADC and multiplied by 8, when ADCSEL is 1, this value will equal to ADCW *8 */ + +/************** Bits definition for RTC_ACKTEMP register ******************/ +#define RTC_ACKTEMP_KTEMP1_Pos (0U) +#define RTC_ACKTEMP_KTEMP1_Msk (0xFFU << RTC_ACKTEMP_KTEMP1_Pos) /*!< 0x000000FF */ +#define RTC_ACKTEMP_KTEMP1 RTC_ACKTEMP_KTEMP1_Msk /*!< This register is used to control the section 1 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ +#define RTC_ACKTEMP_KTEMP2_Pos (8U) +#define RTC_ACKTEMP_KTEMP2_Msk (0xFFU << RTC_ACKTEMP_KTEMP2_Pos) /*!< 0x0000FF00 */ +#define RTC_ACKTEMP_KTEMP2 RTC_ACKTEMP_KTEMP2_Msk /*!< This register is used to control the section 2 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ +#define RTC_ACKTEMP_KTEMP3_Pos (16U) +#define RTC_ACKTEMP_KTEMP3_Msk (0xFFU << RTC_ACKTEMP_KTEMP3_Pos) /*!< 0x00FF0000 */ +#define RTC_ACKTEMP_KTEMP3 RTC_ACKTEMP_KTEMP3_Msk /*!< This register is used to control the section 3 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ +#define RTC_ACKTEMP_KTEMP4_Pos (24U) +#define RTC_ACKTEMP_KTEMP4_Msk (0xFFU << RTC_ACKTEMP_KTEMP4_Pos) /*!< 0xFF000000 */ +#define RTC_ACKTEMP_KTEMP4 RTC_ACKTEMP_KTEMP4_Msk /*!< This register is used to control the section 3 temperature. This is a signed 8 bits value. This register can be updated only when CE is 1, and should be fixed value when ACEN is 1 */ + +/************** Bits definition for RTC_ACOPx register ******************/ +#define RTC_ACOP_OP_Pos (0U) +#define RTC_ACOP_OP_Msk (0x1FFU << RTC_ACOP_OP_Pos) /*!< 0x000001FF */ +#define RTC_ACOP_OP RTC_ACOP_OP_Msk /*!< The OP0~OP63 register is valid only for FPGA. These Ops are used for internal ALU to calculate the auto-calibration data. Before the auto-calibration procedure, all necessary OP should be program correctly into these registers. For real chip, this part will become ROM table and no longer be able to read/write by CPU */ + +/******************************************************************************/ +/* */ +/* FLASH controller (FLASH) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for FLASH_STS register ******************/ +#define FLASH_STS_Pos (0U) +#define FLASH_STS_Msk (0x1U << FLASH_STS_Pos) /*!< 0x00000001 */ +#define FLASH_STS FLASH_STS_Msk /*!< */ + +/************** Bits definition for FLASH_NVRPASS register ******************/ +#define FLASH_NVRPASS_Pos (0U) +#define FLASH_NVRPASS_Msk (0xFFFFFFFFU << FLASH_NVRPASS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_NVRPASS_NVRPASS FLASH_NVRPASS_Msk /*!< programmer should write 0xAA5555AA to this register */ +#define FLASH_NVRPASS_NVRUNLOCK_Pos (0U) +#define FLASH_NVRPASS_NVRUNLOCK_Msk (0x1U << FLASH_NVRPASS_NVRUNLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_NVRPASS_NVRUNLOCK FLASH_NVRPASS_NVRUNLOCK_Msk /*!< The NVRUNLOCK bit is used to indicate the NVR sector program has been unlocked or not */ + +/************** Bits definition for FLASH_BDPASS register ******************/ +//#define FLASH_BDPASS_BDEN_Pos (0U) +//#define FLASH_BDPASS_BDEN_Msk (0x1U << FLASH_BDPASS_BDEN_Pos) /*!< 0x00000001 */ +//#define FLASH_BDPASS_BDEN FLASH_BDPASS_BDEN_Msk /*!< This register is not opened for customer */ + +/************** Bits definition for FLASH_KEY register ******************/ +#define FLASH_KEY_Pos (0U) +#define FLASH_KEY_Msk (0xFFFFFFFFU << FLASH_KEY_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEY_KEY FLASH_KEY_Msk /*!< The KEY register is used to unlock those blocked function */ + +/************** Bits definition for FLASH_INT register ******************/ +#define FLASH_INT_CSERR_Pos (0U) +#define FLASH_INT_CSERR_Msk (0x1U << FLASH_INT_CSERR_Pos) /*!< 0x00000001 */ +#define FLASH_INT_CSERR FLASH_INT_CSERR_Msk /*!< Checksum error status bit */ + +/************** Bits definition for FLASH_CSSADDR register ******************/ +#define FLASH_CSSADDR_Pos (0U) +#define FLASH_CSSADDR_Msk (0x3FFFFU << FLASH_CSSADDR_Pos) /*!< 0x0003FFFF */ +#define FLASH_CSSADDR_CSSADDR FLASH_CSSADDR_Msk /*!< Checksum start address register */ + +/************** Bits definition for FLASH_CSEADDR register ******************/ +#define FLASH_CSEADDR_Pos (0U) +#define FLASH_CSEADDR_Msk (0x3FFFFU << FLASH_CSEADDR_Pos) /*!< 0x0003FFFF */ +#define FLASH_CSEADDR_CSEADDR FLASH_CSEADDR_Msk /*!< Checksum end address register */ + +/************** Bits definition for FLASH_CSVALUE register ******************/ +#define FLASH_CSVALUE_Pos (0U) +#define FLASH_CSVALUE_Msk (0xFFFFFFFFU << FLASH_CSVALUE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CSVALUE_CSVALUE FLASH_CSVALUE_Msk /*!< Checksum latched value register */ + +/************** Bits definition for FLASH_CSCVALUE register ******************/ +#define FLASH_CSCVALUE_Pos (0U) +#define FLASH_CSCVALUE_Msk (0xFFFFFFFFU << FLASH_CSCVALUE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CSCVALUE_CSCVALUE FLASH_CSCVALUE_Msk /*!< Checksum compare value register */ + +/************** Bits definition for FLASH_PASS register ******************/ +#define FLASH_PASS_Pos (0U) +#define FLASH_PASS_Msk (0xFFFFFFFFU << FLASH_PASS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PASS_PASS FLASH_PASS_Msk /*!< programmer should write 0x55AAAA55 to this register */ +#define FLASH_PASS_UNLOCK_Pos (0U) +#define FLASH_PASS_UNLOCK_Msk (0x1U << FLASH_PASS_UNLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_PASS_UNLOCK FLASH_PASS_UNLOCK_Msk /*!< The UNLOCK bit is used to indicate the Flash program has been unlocked or not */ + +/************** Bits definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_CSMODE_Pos (0U) +#define FLASH_CTRL_CSMODE_Msk (0x3U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000003 */ +#define FLASH_CTRL_CSMODE FLASH_CTRL_CSMODE_Msk /*!< This register is used to control the checksum mode */ +#define FLASH_CTRL_CSMODE_DISABLE (0x0U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000000 */ +#define FLASH_CTRL_CSMODE_ALWAYSON (0x1U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_CSMODE_TIM2OV (0x2U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_CSMODE_RTC (0x3U << FLASH_CTRL_CSMODE_Pos) /*!< 0x00000003 */ +#define FLASH_CTRL_CSINTEN_Pos (2U) +#define FLASH_CTRL_CSINTEN_Msk (0x1U << FLASH_CTRL_CSINTEN_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_CSINTEN FLASH_CTRL_CSINTEN_Msk /*!< This register is used to control the interrupt enable of checksum error */ +//#define FLASH_CTRL_READM0_Pos (4U) +//#define FLASH_CTRL_READM0_Msk (0x1U << FLASH_CTRL_READM0_Pos) /*!< 0x00000010 */ +//#define FLASH_CTRL_READM0 FLASH_CTRL_READM0_Msk /*!< This bit is used to control the READM0 pin of Flash IP */ +//#define FLASH_CTRL_READM1_Pos (5U) +//#define FLASH_CTRL_READM1_Msk (0x1U << FLASH_CTRL_READM1_Pos) /*!< 0x00000020 */ +//#define FLASH_CTRL_READM1 FLASH_CTRL_READM1_Msk /*!< This bit is used to control the READM1 pin of Flash IP */ +//#define FLASH_CTRL_NVR_Pos (6U) +//#define FLASH_CTRL_NVR_Msk (0x1U << FLASH_CTRL_NVR_Pos) /*!< 0x00000040 */ +//#define FLASH_CTRL_NVR FLASH_CTRL_NVR_Msk /*!< This register is used to control the NVR program */ +//#define FLASH_CTRL_SFTRST_Pos (7U) +//#define FLASH_CTRL_SFTRST_Msk (0x1U << FLASH_CTRL_SFTRST_Pos) /*!< 0x00000080 */ +//#define FLASH_CTRL_SFTRST FLASH_CTRL_SFTRST_Msk /*!< This register is used to reset the internal FIFO, just for test usage */ +//#define FLASH_CTRL_FORCESWAP_Pos (8U) +//#define FLASH_CTRL_FORCESWAP_Msk (0x1U << FLASH_CTRL_FORCESWAP_Pos) /*!< 0x00000100 */ +//#define FLASH_CTRL_FORCESWAP FLASH_CTRL_FORCESWAP_Msk /*!< This register is used to control the swap function in-between normal sector and NVR sector */ + +/************** Bits definition for FLASH_PGADDR register ******************/ +#define FLASH_PGADDR_Pos (0U) +#define FLASH_PGADDR_Msk (0x3FFFFU << FLASH_PGADDR_Pos) /*!< 0x0003FFFF */ +#define FLASH_PGADDR_PGADDR FLASH_PGADDR_Msk /*!< This register is used to control the program address before doing program */ + +/************** Bits definition for FLASH_PGDATA register ******************/ +#define FLASH_PGDATA_Pos (0U) +#define FLASH_PGDATA_Msk (0xFFFFFFFFU << FLASH_PGDATA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PGDATA_PGDATA FLASH_PGDATA_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB0 register ******************/ +#define FLASH_PGDB0_Pos (0U) +#define FLASH_PGDB0_Msk (0xFFU << FLASH_PGDB0_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB0 FLASH_PGDB0_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB1 register ******************/ +#define FLASH_PGDB1_Pos (0U) +#define FLASH_PGDB1_Msk (0xFFU << FLASH_PGDB1_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB1 FLASH_PGDB1_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB2 register ******************/ +#define FLASH_PGDB2_Pos (0U) +#define FLASH_PGDB2_Msk (0xFFU << FLASH_PGDB2_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB2 FLASH_PGDB2_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDB3 register ******************/ +#define FLASH_PGDB3_Pos (0U) +#define FLASH_PGDB3_Msk (0xFFU << FLASH_PGDB3_Pos) /*!< 0x000000FF */ +#define FLASH_PGDB3 FLASH_PGDB3_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDHW0 register ******************/ +#define FLASH_PGDHW0_Pos (0U) +#define FLASH_PGDHW0_Msk (0xFFFFU << FLASH_PGDHW0_Pos) /*!< 0x0000FFFF */ +#define FLASH_PGDHW0 FLASH_PGDHW0_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_PGDHW1 register ******************/ +#define FLASH_PGDHW1_Pos (0U) +#define FLASH_PGDHW1_Msk (0xFFFFU << FLASH_PGDHW1_Pos) /*!< 0x0000FFFF */ +#define FLASH_PGDHW1 FLASH_PGDHW1_Msk /*!< This register is used to control the program data */ + +/************** Bits definition for FLASH_CONF register ******************/ +//#define FLASH_CONF_Pos (0U) +//#define FLASH_CONF_Msk (0xFFFFFFFFU << FLASH_CONF_Pos) /*!< 0xFFFFFFFF */ +//#define FLASH_CONF_CONF FLASH_CONF_Msk /*!< This register is used to read/write the Flash IP��s configuration register */ + +/************** Bits definition for FLASH_SERASE register ******************/ +#define FLASH_SERASE_Pos (0U) +#define FLASH_SERASE_Msk (0xFFFFFFFFU << FLASH_SERASE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_SERASE_SERASE FLASH_SERASE_Msk /*!< This bit can be set when UNLOCK is 1 and programmer write 0xAA5555AA to this register */ +#define FLASH_SERASE_BIT0_Pos (0U) +#define FLASH_SERASE_BIT0_Msk (0x1U << FLASH_SERASE_BIT0_Pos) /*!< 0x00000001 */ +#define FLASH_SERASE_BIT0 FLASH_SERASE_BIT0_Msk /*!< This bit is used to indicate if the sector erase is ongoing or not */ + +/************** Bits definition for FLASH_CERASE register ******************/ +#define FLASH_CERASE_Pos (0U) +#define FLASH_CERASE_Msk (0xFFFFFFFFU << FLASH_CERASE_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CERASE_CERASE FLASH_CERASE_Msk /*!< This bit can be set when UNLOCK is 1 and programmer write 0xAA5555AA to this register */ +#define FLASH_CERASE_BIT0_Pos (0U) +#define FLASH_CERASE_BIT0_Msk (0x1U << FLASH_CERASE_BIT0_Pos) /*!< 0x00000001 */ +#define FLASH_CERASE_BIT0 FLASH_CERASE_BIT0_Msk /*!< This bit is used to indicate if the chip erase is ongoing or not */ + +/************** Bits definition for FLASH_DSTB register ******************/ +#define FLASH_DSTB_Pos (0U) +#define FLASH_DSTB_Msk (0xFFFFFFFFU << FLASH_DSTB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_DSTB_DSTB FLASH_DSTB_Msk /*!< This bit can be set when UNLOCK is 1 and programmer write 0xAA5555AA to this register */ +#define FLASH_DSTB_BIT0_Pos (0U) +#define FLASH_DSTB_BIT0_Msk (0x1U << FLASH_DSTB_BIT0_Pos) /*!< 0x00000001 */ +#define FLASH_DSTB_BIT0 FLASH_DSTB_BIT0_Msk /*!< This bit is used to indicate if the Flash IP is entering deep standby */ + + +/******************************************************************************/ +/* */ +/* GPIO controller (GPIO) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for IOx_OEN register ******************/ +#define IOx_OEN_IOXOEN_Pos (0U) +#define IOx_OEN_IOXOEN_Msk (0xFFFFU << IOx_OEN_IOXOEN_Pos) /*!< 0x0000FFFF */ +#define IOx_OEN_IOXOEN IOx_OEN_IOXOEN_Msk /*!< Each bit control the IOX��s output enable signal */ + +/************** Bits definition for IOx_IE register ******************/ +#define IOx_IE_IOXIE_Pos (0U) +#define IOx_IE_IOXIE_Msk (0xFFFFU << IOx_IE_IOXIE_Pos) /*!< 0x0000FFFF */ +#define IOx_IE_IOXIE IOx_IE_IOXIE_Msk /*!< Each bit control the IOX��s input enable signal */ + +/************** Bits definition for IOx_DAT register ******************/ +#define IOx_DAT_IOXDAT_Pos (0U) +#define IOx_DAT_IOXDAT_Msk (0xFFFFU << IOx_DAT_IOXDAT_Pos) /*!< 0x0000FFFF */ +#define IOx_DAT_IOXDAT IOx_DAT_IOXDAT_Msk /*!< Each bit control the IOX��s output data and pull low/high function */ + +/************** Bits definition for IOx_ATT register ******************/ +#define IOx_ATT_IOXATT_Pos (0U) +#define IOx_ATT_IOXATT_Msk (0xFFFFU << IOx_ATT_IOXATT_Pos) /*!< 0x0000FFFF */ +#define IOx_ATT_IOXATT IOx_ATT_IOXATT_Msk /*!< Each bit control the IOX��s attribute and pull low/high function */ + +/************** Bits definition for IOx_STS register ******************/ +#define IOx_STS_IOXSTS_Pos (0U) +#define IOx_STS_IOXSTS_Msk (0xFFFFU << IOx_STS_IOXSTS_Pos) /*!< 0x0000FFFF */ +#define IOx_STS_IOXSTS IOx_STS_IOXSTS_Msk /*!< Each bit represents the current IOX��s input data value */ + +///************** Bits definition for IOx_CM register ******************/ +//#define IOx_CM_IOXCM0_Pos (0U) +//#define IOx_CM_IOXCM0_Msk (0x1U << IOx_CM_IOXCM0_Pos) /*!< 0x00000001 */ +//#define IOx_CM_IOXCM0 IOx_CM_IOXCM0_Msk /*!< IOX0��s Schmitt trigger setting, change to this register will change all setting of IOX0~IOX7 */ +//#define IOx_CM_IOXCM1_7_Pos (1U) +//#define IOx_CM_IOXCM1_7_Msk (0x7FU << IOx_CM_IOXCM1_7_Pos) /*!< 0x000000FE */ +//#define IOx_CM_IOXCM1_7 IOx_CM_IOXCM1_7_Msk /*!< Each bit represent the current Schmitt trigger setting of IOX1~IOX7 */ +//#define IOx_CM_IOXCM8_Pos (8U) +//#define IOx_CM_IOXCM8_Msk (0x1U << IOx_CM_IOXCM8_Pos) /*!< 0x00000100 */ +//#define IOx_CM_IOXCM8 IOx_CM_IOXCM8_Msk /*!< IOX8��s Schmitt trigger setting, change to this register will change all setting of IOX8~IOX15 */ +//#define IOx_CM_IOXCM9_15_Pos (9U) +//#define IOx_CM_IOXCM9_15_Msk (0x7FU << IOx_CM_IOXCM9_15_Pos) /*!< 0x0000FE00 */ +//#define IOx_CM_IOXCM9_15 IOx_CM_IOXCM9_15_Msk /*!< Each bit represent the current Schmitt trigger setting of IOX9~IOX15 */ +// +///************** Bits definition for IOx_SR register ******************/ +//#define IOx_SR_IOXSR0_Pos (0U) +//#define IOx_SR_IOXSR0_Msk (0x1U << IOx_SR_IOXSR0_Pos) /*!< 0x00000001 */ +//#define IOx_SR_IOXSR0 IOx_SR_IOXSR0_Msk /*!< IOX0��s slew rate setting, change to this register will change all setting of IOX0~IOX7 */ +//#define IOx_SR_IOXSR1_7_Pos (1U) +//#define IOx_SR_IOXSR1_7_Msk (0x7FU << IOx_SR_IOXSR1_7_Pos) /*!< 0x000000FE */ +//#define IOx_SR_IOXSR1_7 IOx_SR_IOXSR1_7_Msk /*!< Each bit represent the current slew rate setting of IOX1~IOX7 */ +//#define IOx_SR_IOXSR8_Pos (8U) +//#define IOx_SR_IOXSR8_Msk (0x1U << IOx_SR_IOXSR8_Pos) /*!< 0x00000100 */ +//#define IOx_SR_IOXSR8 IOx_SR_IOXSR8_Msk /*!< IOX8��s slew rate setting, change to this register will change all setting of IOX8~IOX15 */ +//#define IOx_SR_IOXSR9_15_Pos (9U) +//#define IOx_SR_IOXSR9_15_Msk (0x7FU << IOx_SR_IOXSR9_15_Pos) /*!< 0x0000FE00 */ +//#define IOx_SR_IOXSR9_15 IOx_SR_IOXSR9_15_Msk /*!< Each bit represent the current slew rate setting of IOX9~IOX15 */ +// +///************** Bits definition for IOx_DR register ******************/ +//#define IOx_DR_IOXDR0_Pos (0U) +//#define IOx_DR_IOXDR0_Msk (0x1U << IOx_DR_IOXDR0_Pos) /*!< 0x00000001 */ +//#define IOx_DR_IOXDR0 IOx_DR_IOXDR0_Msk /*!< IOX0��s driving strength setting, change to this register will change all setting of IOX0~IOX7 */ +//#define IOx_DR_IOXDR1_7_Pos (1U) +//#define IOx_DR_IOXDR1_7_Msk (0x7FU << IOx_DR_IOXDR1_7_Pos) /*!< 0x000000FE */ +//#define IOx_DR_IOXDR1_7 IOx_DR_IOXDR1_7_Msk /*!< Each bit represent the current driving strength setting of IOX1~IOX7 */ +//#define IOx_DR_IOXDR8_Pos (8U) +//#define IOx_DR_IOXDR8_Msk (0x1U << IOx_DR_IOXDR8_Pos) /*!< 0x00000100 */ +//#define IOx_DR_IOXDR8 IOx_DR_IOXDR8_Msk /*!< IOX8��s driving strength setting, change to this register will change all setting of IOX8~IOX15 */ +//#define IOx_DR_IOXDR9_15_Pos (9U) +//#define IOx_DR_IOXDR9_15_Msk (0x7FU << IOx_DR_IOXDR9_15_Pos) /*!< 0x0000FE00 */ +//#define IOx_DR_IOXDR9_15 IOx_DR_IOXDR9_15_Msk /*!< Each bit represent the current driving strength setting of IOX9~IOX15 */ + +/************** Bits definition for IOB_SEL register ******************/ +#define IOB_SEL_SEL1_Pos (1U) +#define IOB_SEL_SEL1_Msk (0x1U << IOB_SEL_SEL1_Pos) /*!< 0x00000002 */ +#define IOB_SEL_SEL1 IOB_SEL_SEL1_Msk /*!< IOB1 special function select register */ +#define IOB_SEL_SEL2_Pos (2U) +#define IOB_SEL_SEL2_Msk (0x1U << IOB_SEL_SEL2_Pos) /*!< 0x00000004 */ +#define IOB_SEL_SEL2 IOB_SEL_SEL2_Msk /*!< IOB2 special function select register */ +#define IOB_SEL_SEL6_Pos (6U) +#define IOB_SEL_SEL6_Msk (0x1U << IOB_SEL_SEL6_Pos) /*!< 0x00000040 */ +#define IOB_SEL_SEL6 IOB_SEL_SEL6_Msk /*!< IOB6 special function select register */ + + +/************** Bits definition for IOE_SEL register ******************/ +#define IOE_SEL_SEL7_Pos (7U) +#define IOE_SEL_SEL7_Msk (0x1U << IOE_SEL_SEL7_Pos) /*!< 0x00000080 */ +#define IOE_SEL_SEL7 IOE_SEL_SEL7_Msk /*!< IOE7 special function select register */ + +/************** Bits definition for IO_MISC register ******************/ +#define IO_MISC_PLLHDIV_Pos (0U) +#define IO_MISC_PLLHDIV_Msk (0x7U << IO_MISC_PLLHDIV_Pos) /*!< 0x00000007 */ +#define IO_MISC_PLLHDIV IO_MISC_PLLHDIV_Msk /*!< When IOB1 is selected to special function 3, this register is used to control the divide ratio of PLLH��s output */ +#define IO_MISC_PLLHDIV_1 (0x0U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_2 (0x1U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_4 (0x2U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_8 (0x3U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_PLLHDIV_16 (0x4U << IO_MISC_PLLHDIV_Pos) +#define IO_MISC_I2CIOC_Pos (5U) +#define IO_MISC_I2CIOC_Msk (0x1U << IO_MISC_I2CIOC_Pos) /*!< 0x00000020 */ +#define IO_MISC_I2CIOC IO_MISC_I2CIOC_Msk /*!< This register is used to control the I2C function is at IOB or IOC */ + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for DMA_IE register ******************/ +#define DMA_IE_C0PEIE_Pos (0U) +#define DMA_IE_C0PEIE_Msk (0x1U << DMA_IE_C0PEIE_Pos) /*!< 0x00000001 */ +#define DMA_IE_C0PEIE DMA_IE_C0PEIE_Msk /*!< Channel 0 package end interrupt enable */ +#define DMA_IE_C1PEIE_Pos (1U) +#define DMA_IE_C1PEIE_Msk (0x1U << DMA_IE_C1PEIE_Pos) /*!< 0x00000002 */ +#define DMA_IE_C1PEIE DMA_IE_C1PEIE_Msk /*!< Channel 1 package end interrupt enable */ +#define DMA_IE_C2PEIE_Pos (2U) +#define DMA_IE_C2PEIE_Msk (0x1U << DMA_IE_C2PEIE_Pos) /*!< 0x00000004 */ +#define DMA_IE_C2PEIE DMA_IE_C2PEIE_Msk /*!< Channel 2 package end interrupt enable */ +#define DMA_IE_C3PEIE_Pos (3U) +#define DMA_IE_C3PEIE_Msk (0x1U << DMA_IE_C3PEIE_Pos) /*!< 0x00000008 */ +#define DMA_IE_C3PEIE DMA_IE_C3PEIE_Msk /*!< Channel 3 package end interrupt enable */ +#define DMA_IE_C0FEIE_Pos (4U) +#define DMA_IE_C0FEIE_Msk (0x1U << DMA_IE_C0FEIE_Pos) /*!< 0x00000010 */ +#define DMA_IE_C0FEIE DMA_IE_C0FEIE_Msk /*!< Channel 0 frame end interrupt enable */ +#define DMA_IE_C1FEIE_Pos (5U) +#define DMA_IE_C1FEIE_Msk (0x1U << DMA_IE_C1FEIE_Pos) /*!< 0x00000020 */ +#define DMA_IE_C1FEIE DMA_IE_C1FEIE_Msk /*!< Channel 1 frame end interrupt enable */ +#define DMA_IE_C2FEIE_Pos (6U) +#define DMA_IE_C2FEIE_Msk (0x1U << DMA_IE_C2FEIE_Pos) /*!< 0x00000040 */ +#define DMA_IE_C2FEIE DMA_IE_C2FEIE_Msk /*!< Channel 2 frame end interrupt enable */ +#define DMA_IE_C3FEIE_Pos (7U) +#define DMA_IE_C3FEIE_Msk (0x1U << DMA_IE_C3FEIE_Pos) /*!< 0x00000080 */ +#define DMA_IE_C3FEIE DMA_IE_C3FEIE_Msk /*!< Channel 3 frame end interrupt enable */ +#define DMA_IE_C0DAIE_Pos (8U) +#define DMA_IE_C0DAIE_Msk (0x1U << DMA_IE_C0DAIE_Pos) /*!< 0x00000100 */ +#define DMA_IE_C0DAIE DMA_IE_C0DAIE_Msk /*!< Channel 0 data about interrupt enable */ +#define DMA_IE_C1DAIE_Pos (9U) +#define DMA_IE_C1DAIE_Msk (0x1U << DMA_IE_C1DAIE_Pos) /*!< 0x00000200 */ +#define DMA_IE_C1DAIE DMA_IE_C1DAIE_Msk /*!< Channel 1 data about interrupt enable */ +#define DMA_IE_C2DAIE_Pos (10U) +#define DMA_IE_C2DAIE_Msk (0x1U << DMA_IE_C2DAIE_Pos) /*!< 0x00000400 */ +#define DMA_IE_C2DAIE DMA_IE_C2DAIE_Msk /*!< Channel 2 data about interrupt enable */ +#define DMA_IE_C3DAIE_Pos (11U) +#define DMA_IE_C3DAIE_Msk (0x1U << DMA_IE_C3DAIE_Pos) /*!< 0x00000800 */ +#define DMA_IE_C3DAIE DMA_IE_C3DAIE_Msk /*!< Channel 3 data about interrupt enable */ + +/************** Bits definition for DMA_STS register ******************/ +#define DMA_STS_C0BUSY_Pos (0U) +#define DMA_STS_C0BUSY_Msk (0x1U << DMA_STS_C0BUSY_Pos) /*!< 0x00000001 */ +#define DMA_STS_C0BUSY DMA_STS_C0BUSY_Msk /*!< DMA channel 0 busy register */ +#define DMA_STS_C1BUSY_Pos (1U) +#define DMA_STS_C1BUSY_Msk (0x1U << DMA_STS_C1BUSY_Pos) /*!< 0x00000002 */ +#define DMA_STS_C1BUSY DMA_STS_C1BUSY_Msk /*!< DMA channel 1 busy register */ +#define DMA_STS_C2BUSY_Pos (2U) +#define DMA_STS_C2BUSY_Msk (0x1U << DMA_STS_C2BUSY_Pos) /*!< 0x00000004 */ +#define DMA_STS_C2BUSY DMA_STS_C2BUSY_Msk /*!< DMA channel 2 busy register */ +#define DMA_STS_C3BUSY_Pos (3U) +#define DMA_STS_C3BUSY_Msk (0x1U << DMA_STS_C3BUSY_Pos) /*!< 0x00000008 */ +#define DMA_STS_C3BUSY DMA_STS_C3BUSY_Msk /*!< DMA channel 3 busy register */ +#define DMA_STS_C0PE_Pos (4U) +#define DMA_STS_C0PE_Msk (0x1U << DMA_STS_C0PE_Pos) /*!< 0x00000010 */ +#define DMA_STS_C0PE DMA_STS_C0PE_Msk /*!< Channel 0 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C1PE_Pos (5U) +#define DMA_STS_C1PE_Msk (0x1U << DMA_STS_C1PE_Pos) /*!< 0x00000020 */ +#define DMA_STS_C1PE DMA_STS_C1PE_Msk /*!< Channel 1 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C2PE_Pos (6U) +#define DMA_STS_C2PE_Msk (0x1U << DMA_STS_C2PE_Pos) /*!< 0x00000040 */ +#define DMA_STS_C2PE DMA_STS_C2PE_Msk /*!< Channel 2 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C3PE_Pos (7U) +#define DMA_STS_C3PE_Msk (0x1U << DMA_STS_C3PE_Pos) /*!< 0x00000080 */ +#define DMA_STS_C3PE DMA_STS_C3PE_Msk /*!< Channel 3 package end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C0FE_Pos (8U) +#define DMA_STS_C0FE_Msk (0x1U << DMA_STS_C0FE_Pos) /*!< 0x00000100 */ +#define DMA_STS_C0FE DMA_STS_C0FE_Msk /*!< Channel 0 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C1FE_Pos (9U) +#define DMA_STS_C1FE_Msk (0x1U << DMA_STS_C1FE_Pos) /*!< 0x00000200 */ +#define DMA_STS_C1FE DMA_STS_C1FE_Msk /*!< Channel 1 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C2FE_Pos (10U) +#define DMA_STS_C2FE_Msk (0x1U << DMA_STS_C2FE_Pos) /*!< 0x00000400 */ +#define DMA_STS_C2FE DMA_STS_C2FE_Msk /*!< Channel 2 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C3FE_Pos (11U) +#define DMA_STS_C3FE_Msk (0x1U << DMA_STS_C3FE_Pos) /*!< 0x00000800 */ +#define DMA_STS_C3FE DMA_STS_C3FE_Msk /*!< Channel 3 frame end interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C0DA_Pos (12U) +#define DMA_STS_C0DA_Msk (0x1U << DMA_STS_C0DA_Pos) /*!< 0x00001000 */ +#define DMA_STS_C0DA DMA_STS_C0DA_Msk /*!< Channel 0 data about interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C1DA_Pos (13U) +#define DMA_STS_C1DA_Msk (0x1U << DMA_STS_C1DA_Pos) /*!< 0x00002000 */ +#define DMA_STS_C1DA DMA_STS_C1DA_Msk /*!< Channel 1 data about interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C2DA_Pos (14U) +#define DMA_STS_C2DA_Msk (0x1U << DMA_STS_C2DA_Pos) /*!< 0x00004000 */ +#define DMA_STS_C2DA DMA_STS_C2DA_Msk /*!< Channel 2 data about interrupt flag, write 1 to clear this flag */ +#define DMA_STS_C3DA_Pos (15U) +#define DMA_STS_C3DA_Msk (0x1U << DMA_STS_C3DA_Pos) /*!< 0x00008000 */ +#define DMA_STS_C3DA DMA_STS_C3DA_Msk /*!< Channel 3 data about interrupt flag, write 1 to clear this flag */ + +/************** Bits definition for DMA_CxCTL register ******************/ +#define DMA_CxCTL_EN_Pos (0U) +#define DMA_CxCTL_EN_Msk (0x1U << DMA_CxCTL_EN_Pos) /*!< 0x00000001 */ +#define DMA_CxCTL_EN DMA_CxCTL_EN_Msk /*!< DMA channel enable register */ +#define DMA_CxCTL_SIZE_Pos (1U) +#define DMA_CxCTL_SIZE_Msk (0x3U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000006 */ +#define DMA_CxCTL_SIZE DMA_CxCTL_SIZE_Msk /*!< Transfer size mode */ +#define DMA_CxCTL_SIZE_BYTE (0x0U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000000 */ +#define DMA_CxCTL_SIZE_HWORD (0x1U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000002 */ +#define DMA_CxCTL_SIZE_WORD (0x2U << DMA_CxCTL_SIZE_Pos) /*!< 0x00000004 */ +#define DMA_CxCTL_SMODE_Pos (3U) +#define DMA_CxCTL_SMODE_Msk (0x3U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000018 */ +#define DMA_CxCTL_SMODE DMA_CxCTL_SMODE_Msk /*!< Source address mode */ +#define DMA_CxCTL_SMODE_FIX (0x0U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000000 */ +#define DMA_CxCTL_SMODE_PEND (0x1U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000080 */ +#define DMA_CxCTL_SMODE_FEND (0x2U << DMA_CxCTL_SMODE_Pos) /*!< 0x00000010 */ +#define DMA_CxCTL_DMODE_Pos (5U) +#define DMA_CxCTL_DMODE_Msk (0x3U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000060 */ +#define DMA_CxCTL_DMODE DMA_CxCTL_DMODE_Msk /*!< Destination address mode */ +#define DMA_CxCTL_DMODE_FIX (0x0U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000000 */ +#define DMA_CxCTL_DMODE_PEND (0x1U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000020 */ +#define DMA_CxCTL_DMODE_FEND (0x2U << DMA_CxCTL_DMODE_Pos) /*!< 0x00000040 */ +#define DMA_CTL_DMASEL_Pos (7U) +#define DMA_CTL_DMASEL_Msk (0x1FU << DMA_CTL_DMASEL_Pos) /*!< 0x00000F80 */ +#define DMA_CTL_DMASEL DMA_CTL_DMASEL_Msk /*!< DMA request source selection */ +#define DMA_CTL_DMASEL_SOFT (0x0U << DMA_CTL_DMASEL_Pos) /*!< 0x00000000 */ +#define DMA_CTL_DMASEL_UART0TX (0x2U << DMA_CTL_DMASEL_Pos) /*!< 0x00000100 */ +#define DMA_CTL_DMASEL_UART0RX (0x3U << DMA_CTL_DMASEL_Pos) /*!< 0x00000180 */ +#define DMA_CTL_DMASEL_UART1TX (0x4U << DMA_CTL_DMASEL_Pos) /*!< 0x00000200 */ +#define DMA_CTL_DMASEL_UART1RX (0x5U << DMA_CTL_DMASEL_Pos) /*!< 0x00000280 */ +#define DMA_CTL_DMASEL_UART2TX (0x6U << DMA_CTL_DMASEL_Pos) /*!< 0x00000300 */ +#define DMA_CTL_DMASEL_UART2RX (0x7U << DMA_CTL_DMASEL_Pos) /*!< 0x00000380 */ +#define DMA_CTL_DMASEL_UART3TX (0x8U << DMA_CTL_DMASEL_Pos) /*!< 0x00000400 */ +#define DMA_CTL_DMASEL_UART3RX (0x9U << DMA_CTL_DMASEL_Pos) /*!< 0x00000480 */ +#define DMA_CTL_DMASEL_UART4TX (0xAU << DMA_CTL_DMASEL_Pos) /*!< 0x00000500 */ +#define DMA_CTL_DMASEL_UART4RX (0xBU << DMA_CTL_DMASEL_Pos) /*!< 0x00000580 */ +#define DMA_CTL_DMASEL_UART5TX (0xCU << DMA_CTL_DMASEL_Pos) /*!< 0x00000600 */ +#define DMA_CTL_DMASEL_UART5RX (0xDU << DMA_CTL_DMASEL_Pos) /*!< 0x00000680 */ +#define DMA_CTL_DMASEL_ISO78160TX (0xEU << DMA_CTL_DMASEL_Pos) /*!< 0x00000700 */ +#define DMA_CTL_DMASEL_ISO78160RX (0xFU << DMA_CTL_DMASEL_Pos) /*!< 0x00000780 */ +#define DMA_CTL_DMASEL_ISO78161TX (0x10U << DMA_CTL_DMASEL_Pos) /*!< 0x00000800 */ +#define DMA_CTL_DMASEL_ISO78161RX (0x11U << DMA_CTL_DMASEL_Pos) /*!< 0x00000880 */ +#define DMA_CTL_DMASEL_TIMER0 (0x12U << DMA_CTL_DMASEL_Pos) /*!< 0x00000900 */ +#define DMA_CTL_DMASEL_TIMER1 (0x13U << DMA_CTL_DMASEL_Pos) /*!< 0x00000980 */ +#define DMA_CTL_DMASEL_TIMER2 (0x14U << DMA_CTL_DMASEL_Pos) /*!< 0x00000A00 */ +#define DMA_CTL_DMASEL_TIMER3 (0x15U << DMA_CTL_DMASEL_Pos) /*!< 0x00000A80 */ +#define DMA_CTL_DMASEL_SPI1TX (0x16U << DMA_CTL_DMASEL_Pos) /*!< 0x00000B00 */ +#define DMA_CTL_DMASEL_SPI1RX (0x17U << DMA_CTL_DMASEL_Pos) /*!< 0x00000B80 */ +#define DMA_CTL_DMASEL_U32K0 (0x18U << DMA_CTL_DMASEL_Pos) /*!< 0x00000C00 */ +#define DMA_CTL_DMASEL_U32K1 (0x19U << DMA_CTL_DMASEL_Pos) /*!< 0x00000C80 */ +#define DMA_CTL_DMASEL_CMP1 (0x1AU << DMA_CTL_DMASEL_Pos) /*!< 0x00000D00 */ +#define DMA_CTL_DMASEL_CMP2 (0x1BU << DMA_CTL_DMASEL_Pos) /*!< 0x00000D80 */ +//#define DMA_CTL_DMASEL_DSPPROG (0x1CU << DMA_CTL_DMASEL_Pos) /*!< 0x00000E00 */ +//#define DMA_CTL_DMASEL_DSPHBF (0x1DU << DMA_CTL_DMASEL_Pos) /*!< 0x00000E80 */ +#define DMA_CTL_DMASEL_SPI2TX (0x1EU << DMA_CTL_DMASEL_Pos) /*!< 0x00000F00 */ +#define DMA_CTL_DMASEL_SPI2RX (0x1FU << DMA_CTL_DMASEL_Pos) /*!< 0x00000F80 */ +#define DMA_CTL_TMODE_Pos (12U) +#define DMA_CTL_TMODE_Msk (0x1U << DMA_CTL_TMODE_Pos) /*!< 0x00001000 */ +#define DMA_CTL_TMODE DMA_CTL_TMODE_Msk /*!< Transfer mode selection register */ +#define DMA_CTL_CONT_Pos (13U) +#define DMA_CTL_CONT_Msk (0x1U << DMA_CTL_CONT_Pos) /*!< 0x00002000 */ +#define DMA_CTL_CONT DMA_CTL_CONT_Msk /*!< Continuous mode, DMA transfer will not stop until STOP bit is set to 1 */ +#define DMA_CTL_AESEN_Pos (14U) +#define DMA_CTL_AESEN_Msk (0x1U << DMA_CTL_AESEN_Pos) /*!< 0x00004000 */ +#define DMA_CTL_AESEN DMA_CTL_AESEN_Msk /*!< Enable AES encrypt/decrypt function of DMA channel */ +#define DMA_CTL_STOP_Pos (15U) +#define DMA_CTL_STOP_Msk (0x1U << DMA_CTL_STOP_Pos) /*!< 0x00008000 */ +#define DMA_CTL_STOP DMA_CTL_STOP_Msk /*!< Force stop DMA transfer */ +#define DMA_CTL_PLEN_Pos (16U) +#define DMA_CTL_PLEN_Msk (0xFFU << DMA_CTL_PLEN_Pos) /*!< 0x00FF0000 */ +#define DMA_CTL_PLEN DMA_CTL_PLEN_Msk /*!< Package length register, actual transfer package length is (PLEN + 1) */ +#define DMA_CTL_FLEN_Pos (24U) +#define DMA_CTL_FLEN_Msk (0xFFU << DMA_CTL_FLEN_Pos) /*!< 0xFF000000 */ +#define DMA_CTL_FLEN DMA_CTL_FLEN_Msk /*!< Frame length register, actual transfer frame length is (FLEN + 1) */ + +/************** Bits definition for DMA_CxSRC register ******************/ +#define DMA_CxSRC_SRC_Pos (0U) +#define DMA_CxSRC_SRC_Msk (0xFFFFFFFFU << DMA_CxSRC_SRC_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CxSRC_SRC DMA_CxSRC_SRC_Msk /*!< DMA source address register */ + +/************** Bits definition for DMA_CxDST register ******************/ +#define DMA_CxDST_DST_Pos (0U) +#define DMA_CxDST_DST_Msk (0xFFFFFFFFU << DMA_CxDST_DST_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CxDST_DST DMA_CxDST_DST_Msk /*!< DMA destination address register */ + +/************** Bits definition for DMA_CxLEN register ******************/ +#define DMA_CxLEN_CPLEN_Pos (0U) +#define DMA_CxLEN_CPLEN_Msk (0xFFU << DMA_CxLEN_CPLEN_Pos) /*!< 0x000000FF */ +#define DMA_CxLEN_CPLEN DMA_CxLEN_CPLEN_Msk /*!< Current package transferred length */ +#define DMA_CxLEN_CFLEN_Pos (8U) +#define DMA_CxLEN_CFLEN_Msk (0xFFU << DMA_CxLEN_CFLEN_Pos) /*!< 0x0000FF00 */ +#define DMA_CxLEN_CFLEN DMA_CxLEN_CFLEN_Msk /*!< Current frame transferred length */ + +/************** Bits definition for DMA_AESCTL register ******************/ +#define DMA_AESCTL_ENC_Pos (0U) +#define DMA_AESCTL_ENC_Msk (0x1U << DMA_AESCTL_ENC_Pos) /*!< 0x00000001 */ +#define DMA_AESCTL_ENC DMA_AESCTL_ENC_Msk /*!< AES encode/decode selection register */ +#define DMA_AESCTL_MODE_Pos (2U) +#define DMA_AESCTL_MODE_Msk (0x3U << DMA_AESCTL_MODE_Pos) /*!< 0x0000000C */ +#define DMA_AESCTL_MODE DMA_AESCTL_MODE_Msk /*!< AES mode selection register */ +#define DMA_AESCTL_MODE_AES128 (0x0U << DMA_AESCTL_MODE_Pos) /*!< 0x00000000 */ +#define DMA_AESCTL_MODE_AES192 (0x1U << DMA_AESCTL_MODE_Pos) /*!< 0x00000004 */ +#define DMA_AESCTL_MODE_AES256 (0x2U << DMA_AESCTL_MODE_Pos) /*!< 0x00000008 */ + +/************** Bits definition for DMA_AESKEY0 register ******************/ +#define DMA_AESKEY0_Pos (0U) +#define DMA_AESKEY0_Msk (0xFFFFFFFFU << DMA_AESKEY0_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY0_KEY0 DMA_AESKEY0_Msk /*!< AES KEY register 0 */ + +/************** Bits definition for DMA_AESKEY1 register ******************/ +#define DMA_AESKEY1_Pos (0U) +#define DMA_AESKEY1_Msk (0xFFFFFFFFU << DMA_AESKEY1_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY1_KEY1 DMA_AESKEY1_Msk /*!< AES KEY register 1 */ + +/************** Bits definition for DMA_AESKEY2 register ******************/ +#define DMA_AESKEY2_Pos (0U) +#define DMA_AESKEY2_Msk (0xFFFFFFFFU << DMA_AESKEY2_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY2_KEY2 DMA_AESKEY2_Msk /*!< AES KEY register 2 */ + +/************** Bits definition for DMA_AESKEY3 register ******************/ +#define DMA_AESKEY3_Pos (0U) +#define DMA_AESKEY3_Msk (0xFFFFFFFFU << DMA_AESKEY3_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY3_KEY3 DMA_AESKEY3_Msk /*!< AES KEY register 3 */ + +/************** Bits definition for DMA_AESKEY4 register ******************/ +#define DMA_AESKEY4_Pos (0U) +#define DMA_AESKEY4_Msk (0xFFFFFFFFU << DMA_AESKEY4_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY4_KEY4 DMA_AESKEY4_Msk /*!< AES KEY register 4 */ + +/************** Bits definition for DMA_AESKEY5 register ******************/ +#define DMA_AESKEY5_Pos (0U) +#define DMA_AESKEY5_Msk (0xFFFFFFFFU << DMA_AESKEY5_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY5_KEY5 DMA_AESKEY5_Msk /*!< AES KEY register 5 */ + +/************** Bits definition for DMA_AESKEY6 register ******************/ +#define DMA_AESKEY6_Pos (0U) +#define DMA_AESKEY6_Msk (0xFFFFFFFFU << DMA_AESKEY6_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY6_KEY6 DMA_AESKEY6_Msk /*!< AES KEY register 6 */ + +/************** Bits definition for DMA_AESKEY7 register ******************/ +#define DMA_AESKEY7_Pos (0U) +#define DMA_AESKEY7_Msk (0xFFFFFFFFU << DMA_AESKEY7_Pos) /*!< 0xFFFFFFFF */ +#define DMA_AESKEY7_KEY7 DMA_AESKEY7_Msk /*!< AES KEY register 7 */ + +/******************************************************************************/ +/* */ +/* UART controller (UART) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for UARTx_DATA register ******************/ +#define UART_DATA_Pos (0U) +#define UART_DATA_Msk (0xFFU << UART_DATA_Pos) /*!< 0x000000FF */ +#define UART_DATA UART_DATA_Msk /*!< Receive data and Transmit data */ + +/************** Bits definition for UARTx_STATE register ******************/ +//#define UART_STATE_TXFULL_Pos (0U) +//#define UART_STATE_TXFULL_Msk (0x1U << UART_STATE_TXFULL_Pos) /*!< 0x00000001 */ +//#define UART_STATE_TXFULL UART_STATE_TXFULL_Msk /*!< Transmit buffer full register */ +#define UART_STATE_RXFULL_Pos (1U) +#define UART_STATE_RXFULL_Msk (0x1U << UART_STATE_RXFULL_Pos) /*!< 0x00000002 */ +#define UART_STATE_RXFULL UART_STATE_RXFULL_Msk /*!< Receive buffer full register */ +#define UART_STATE_TXOV_Pos (2U) +#define UART_STATE_TXOV_Msk (0x1U << UART_STATE_TXOV_Pos) /*!< 0x00000004 */ +#define UART_STATE_TXOV UART_STATE_TXOV_Msk /*!< Transmit buffer overrun flag */ +#define UART_STATE_RXOV_Pos (3U) +#define UART_STATE_RXOV_Msk (0x1U << UART_STATE_RXOV_Pos) /*!< 0x00000008 */ +#define UART_STATE_RXOV UART_STATE_RXOV_Msk /*!< Receive buffer overrun flag */ +#define UART_STATE_RXPE_Pos (4U) +#define UART_STATE_RXPE_Msk (0x1U << UART_STATE_RXPE_Pos) /*!< 0x00000010 */ +#define UART_STATE_RXPE UART_STATE_RXPE_Msk /*!< Receive parity error flag */ +#define UART_STATE_TXDONE_Pos (5U) +#define UART_STATE_TXDONE_Msk (0x1U << UART_STATE_TXDONE_Pos) /*!< 0x00000020 */ +#define UART_STATE_TXDONE UART_STATE_TXDONE_Msk /*!< Transmit done flag */ +#define UART_STATE_RXPSTS_Pos (6U) +#define UART_STATE_RXPSTS_Msk (0x1U << UART_STATE_RXPSTS_Pos) /*!< 0x00000040 */ +#define UART_STATE_RXPSTS UART_STATE_RXPSTS_Msk /*!< Receive parity data flag */ + +/************** Bits definition for UARTx_CTRL register ******************/ +#define UART_CTRL_TXEN_Pos (0U) +#define UART_CTRL_TXEN_Msk (0x1U << UART_CTRL_TXEN_Pos) /*!< 0x00000001 */ +#define UART_CTRL_TXEN UART_CTRL_TXEN_Msk /*!< Transmit engine enable register */ +#define UART_CTRL_RXEN_Pos (1U) +#define UART_CTRL_RXEN_Msk (0x1U << UART_CTRL_RXEN_Pos) /*!< 0x00000002 */ +#define UART_CTRL_RXEN UART_CTRL_RXEN_Msk /*!< Receive engine enable register */ +//#define UART_CTRL_TXIE_Pos (2U) +//#define UART_CTRL_TXIE_Msk (0x1U << UART_CTRL_TXIE_Pos) /*!< 0x00000004 */ +//#define UART_CTRL_TXIE UART_CTRL_TXIE_Msk /*!< Transmit interrupt enable register */ +#define UART_CTRL_RXIE_Pos (3U) +#define UART_CTRL_RXIE_Msk (0x1U << UART_CTRL_RXIE_Pos) /*!< 0x00000008 */ +#define UART_CTRL_RXIE UART_CTRL_RXIE_Msk /*!< Receive interrupt enable register */ +#define UART_CTRL_TXOVIE_Pos (4U) +#define UART_CTRL_TXOVIE_Msk (0x1U << UART_CTRL_TXOVIE_Pos) /*!< 0x00000010 */ +#define UART_CTRL_TXOVIE UART_CTRL_TXOVIE_Msk /*!< Transmit overrun interrupt enable register */ +#define UART_CTRL_RXOVIE_Pos (5U) +#define UART_CTRL_RXOVIE_Msk (0x1U << UART_CTRL_RXOVIE_Pos) /*!< 0x00000020 */ +#define UART_CTRL_RXOVIE UART_CTRL_RXOVIE_Msk /*!< Receive overrun interrupt enable register */ +//#define UART_CTRL_TEST_Pos (6U) +//#define UART_CTRL_TEST_Msk (0x1U << UART_CTRL_TEST_Pos) /*!< 0x00000040 */ +//#define UART_CTRL_TEST UART_CTRL_TEST_Msk /*!< High speed test mode for TX only */ +#define UART_CTRL_RXPEIE_Pos (7U) +#define UART_CTRL_RXPEIE_Msk (0x1U << UART_CTRL_RXPEIE_Pos) /*!< 0x00000080 */ +#define UART_CTRL_RXPEIE UART_CTRL_RXPEIE_Msk /*!< Receive parity error interrupt enable register */ +#define UART_CTRL_TXDONEIE_Pos (8U) +#define UART_CTRL_TXDONEIE_Msk (0x1U << UART_CTRL_TXDONEIE_Pos) /*!< 0x00000100 */ +#define UART_CTRL_TXDONEIE UART_CTRL_TXDONEIE_Msk /*!< Transmit done interrupt enable register */ + +/************** Bits definition for UARTx_INTSTS register ******************/ +//#define UART_INTSTS_TXIF_Pos (0U) +//#define UART_INTSTS_TXIF_Msk (0x1U << UART_INTSTS_TXIF_Pos) /*!< 0x00000001 */ +//#define UART_INTSTS_TXIF UART_INTSTS_TXIF_Msk /*!< Transmit interrupt flag */ +#define UART_INTSTS_RXIF_Pos (1U) +#define UART_INTSTS_RXIF_Msk (0x1U << UART_INTSTS_RXIF_Pos) /*!< 0x00000002 */ +#define UART_INTSTS_RXIF UART_INTSTS_RXIF_Msk /*!< Receive interrupt flag */ +#define UART_INTSTS_TXOVIF_Pos (2U) +#define UART_INTSTS_TXOVIF_Msk (0x1U << UART_INTSTS_TXOVIF_Pos) /*!< 0x00000004 */ +#define UART_INTSTS_TXOVIF UART_INTSTS_TXOVIF_Msk /*!< Transmit buffer overrun flag */ +#define UART_INTSTS_RXOVIF_Pos (3U) +#define UART_INTSTS_RXOVIF_Msk (0x1U << UART_INTSTS_RXOVIF_Pos) /*!< 0x00000008 */ +#define UART_INTSTS_RXOVIF UART_INTSTS_RXOVIF_Msk /*!< Receive buffer overrun flag */ +#define UART_INTSTS_RXPEIF_Pos (4U) +#define UART_INTSTS_RXPEIF_Msk (0x1U << UART_INTSTS_RXPEIF_Pos) /*!< 0x00000010 */ +#define UART_INTSTS_RXPEIF UART_INTSTS_RXPEIF_Msk /*!< Receive parity error flag */ +#define UART_INTSTS_TXDONEIF_Pos (5U) +#define UART_INTSTS_TXDONEIF_Msk (0x1U << UART_INTSTS_TXDONEIF_Pos) /*!< 0x00000020 */ +#define UART_INTSTS_TXDONEIF UART_INTSTS_TXDONEIF_Msk /*!< Transmit done flag */ + +/************** Bits definition for UARTx_BAUDDIV register ******************/ +#define UART_BAUDDIV_Pos (0U) +#define UART_BAUDDIV_Msk (0xFFFFFU << UART_BAUDDIV_Pos) /*!< 0x000FFFFF */ +#define UART_BAUDDIV UART_BAUDDIV_Msk /*!< Baud rate divider register */ + +/************** Bits definition for UARTx_CTRL2 register ******************/ +#define UART_CTRL2_MSB_Pos (0U) +#define UART_CTRL2_MSB_Msk (0x1U << UART_CTRL2_MSB_Pos) /*!< 0x00000001 */ +#define UART_CTRL2_MSB UART_CTRL2_MSB_Msk /*!< LSB/MSB transmit order control register */ +#define UART_CTRL2_MODE_Pos (1U) +#define UART_CTRL2_MODE_Msk (0x1U << UART_CTRL2_MODE_Pos) /*!< 0x00000002 */ +#define UART_CTRL2_MODE UART_CTRL2_MODE_Msk /*!< UART mode control register */ +#define UART_CTRL2_PMODE_Pos (2U) +#define UART_CTRL2_PMODE_Msk (0x3U << UART_CTRL2_PMODE_Pos) /*!< 0x0000000C */ +#define UART_CTRL2_PMODE UART_CTRL2_PMODE_Msk /*!< Parity mode control register */ +#define UART_CTRL2_PMODE_EVEN (0x0U << UART_CTRL2_PMODE_Pos) /*!< 0x00000000 */ +#define UART_CTRL2_PMODE_ODD (0x1U << UART_CTRL2_PMODE_Pos) /*!< 0x00000004 */ +#define UART_CTRL2_PMODE_0 (0x2U << UART_CTRL2_PMODE_Pos) /*!< 0x00000008 */ +#define UART_CTRL2_PMODE_1 (0x3U << UART_CTRL2_PMODE_Pos) /*!< 0x0000000C */ + + +/******************************************************************************/ +/* */ +/* U32K controller (U32K) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for U32Kx_CTRL0 register ******************/ +#define U32K_CTRL0_EN_Pos (0U) +#define U32K_CTRL0_EN_Msk (0x1U << U32K_CTRL0_EN_Pos) /*!< 0x00000001 */ +#define U32K_CTRL0_EN U32K_CTRL0_EN_Msk /*!< UART 32K controller enable register */ +#define U32K_CTRL0_ACOFF_Pos (1U) +#define U32K_CTRL0_ACOFF_Msk (0x1U << U32K_CTRL0_ACOFF_Pos) /*!< 0x00000002 */ +#define U32K_CTRL0_ACOFF U32K_CTRL0_ACOFF_Msk /*!< Auto-calibration off control register */ +#define U32K_CTRL0_MSB_Pos (2U) +#define U32K_CTRL0_MSB_Msk (0x1U << U32K_CTRL0_MSB_Pos) /*!< 0x00000004 */ +#define U32K_CTRL0_MSB U32K_CTRL0_MSB_Msk /*!< UART receive order control register */ +#define U32K_CTRL0_MODE_Pos (3U) +#define U32K_CTRL0_MODE_Msk (0x1U << U32K_CTRL0_MODE_Pos) /*!< 0x00000008 */ +#define U32K_CTRL0_MODE U32K_CTRL0_MODE_Msk /*!< UART mode control register */ +#define U32K_CTRL0_PMODE_Pos (4U) +#define U32K_CTRL0_PMODE_Msk (0x3U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000030 */ +#define U32K_CTRL0_PMODE U32K_CTRL0_PMODE_Msk /*!< Parity mode control register */ +#define U32K_CTRL0_PMODE_EVEN (0x0U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000000 */ +#define U32K_CTRL0_PMODE_ODD (0x1U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000010 */ +#define U32K_CTRL0_PMODE_0 (0x2U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000020 */ +#define U32K_CTRL0_PMODE_1 (0x3U << U32K_CTRL0_PMODE_Pos) /*!< 0x00000030 */ +#define U32K_CTRL0_DEBSEL_Pos (6U) +#define U32K_CTRL0_DEBSEL_Msk (0x3U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x000000C0 */ +#define U32K_CTRL0_DEBSEL U32K_CTRL0_DEBSEL_Msk /*!< De-bounce control register */ +#define U32K_CTRL0_DEBSEL_0 (0x0U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000000 */ +#define U32K_CTRL0_DEBSEL_1 (0x1U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000040 */ +#define U32K_CTRL0_DEBSEL_2 (0x2U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x00000080 */ +#define U32K_CTRL0_DEBSEL_3 (0x3U << U32K_CTRL0_DEBSEL_Pos) /*!< 0x000000C0 */ +#define U32K_CTRL0_WKUMODE_Pos (8U) +#define U32K_CTRL0_WKUMODE_Msk (0x1U << U32K_CTRL0_WKUMODE_Pos) /*!< 0x00000100 */ +#define U32K_CTRL0_WKUMODE U32K_CTRL0_WKUMODE_Msk /*!< Wake-up mode control register */ + +/************** Bits definition for U32Kx_CTRL1 register ******************/ +#define U32K_CTRL1_RXIE_Pos (0U) +#define U32K_CTRL1_RXIE_Msk (0x1U << U32K_CTRL1_RXIE_Pos) /*!< 0x00000001 */ +#define U32K_CTRL1_RXIE U32K_CTRL1_RXIE_Msk /*!< Receive interrupt/wake-up enable register */ +#define U32K_CTRL1_RXPEIE_Pos (1U) +#define U32K_CTRL1_RXPEIE_Msk (0x1U << U32K_CTRL1_RXPEIE_Pos) /*!< 0x00000002 */ +#define U32K_CTRL1_RXPEIE U32K_CTRL1_RXPEIE_Msk /*!< Receive parity error interrupt/wake-up enable register */ +#define U32K_CTRL1_RXOVIE_Pos (2U) +#define U32K_CTRL1_RXOVIE_Msk (0x1U << U32K_CTRL1_RXOVIE_Pos) /*!< 0x00000004 */ +#define U32K_CTRL1_RXOVIE U32K_CTRL1_RXOVIE_Msk /*!< Receive overrun interrupt/wake-up enable register */ +#define U32K_CTRL1_RXSEL_Pos (4U) +#define U32K_CTRL1_RXSEL_Msk (0x3U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000030 */ +#define U32K_CTRL1_RXSEL U32K_CTRL1_RXSEL_Msk /*!< Receive data select register */ +#define U32K_CTRL1_RXSEL_RX0 (0x0U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000000 */ +#define U32K_CTRL1_RXSEL_RX1 (0x1U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000010 */ +#define U32K_CTRL1_RXSEL_RX2 (0x2U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000020 */ +#define U32K_CTRL1_RXSEL_RX3 (0x3U << U32K_CTRL1_RXSEL_Pos) /*!< 0x00000030 */ + +/************** Bits definition for U32Kx_PHASE register ******************/ +#define U32K_PHASE_Pos (0U) +#define U32K_PHASE_Msk (0xFFFFU << U32K_PHASE_Pos) /*!< 0x0000FFFF */ +#define U32K_PHASE U32K_PHASE_Msk /*!< Baud rate divider register */ + +/************** Bits definition for U32Kx_DATA register ******************/ +#define U32K_DATA_Pos (0U) +#define U32K_DATA_Msk (0xFFU << U32K_DATA_Pos) /*!< 0x000000FF */ +#define U32K_DATA U32K_DATA_Msk /*!< Receive data */ + +/************** Bits definition for U32Kx_STS register ******************/ +#define U32K_STS_RCMsk (0x07UL) +#define U32K_STS_RXIF_Pos (0U) +#define U32K_STS_RXIF_Msk (0x1U << U32K_STS_RXIF_Pos) /*!< 0x00000001 */ +#define U32K_STS_RXIF U32K_STS_RXIF_Msk /*!< Receive interrupt flag */ +#define U32K_STS_RXPE_Pos (1U) +#define U32K_STS_RXPE_Msk (0x1U << U32K_STS_RXPE_Pos) /*!< 0x00000002 */ +#define U32K_STS_RXPE U32K_STS_RXPE_Msk /*!< Receive parity error flag */ +#define U32K_STS_RXOV_Pos (2U) +#define U32K_STS_RXOV_Msk (0x1U << U32K_STS_RXOV_Pos) /*!< 0x00000004 */ +#define U32K_STS_RXOV U32K_STS_RXOV_Msk /*!< Receive buffer overrun flag */ + +/******************************************************************************/ +/* */ +/* ISO7816 controller (ISO7816) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for ISO7816x_BAUDDIVL register **************/ +#define ISO7816_BAUDDIVL_Pos (0U) +#define ISO7816_BAUDDIVL_Msk (0xFFU << ISO7816_BAUDDIVL_Pos) /*!< 0x000000FF */ +#define ISO7816_BAUDDIVL ISO7816_BAUDDIVL_Msk /*!< Low byte of baud-rate divider */ + +/************** Bits definition for ISO7816x_BAUDDIVH register **************/ +#define ISO7816_BAUDDIVH_Pos (0U) +#define ISO7816_BAUDDIVH_Msk (0xFFU << ISO7816_BAUDDIVH_Pos) /*!< 0x000000FF */ +#define ISO7816_BAUDDIVH ISO7816_BAUDDIVH_Msk /*!< High byte of baud-rate divider */ + +/************** Bits definition for ISO7816x_DATA register ******************/ +#define ISO7816_DATA_Pos (0U) +#define ISO7816_DATA_Msk (0xFFU << ISO7816_DATA_Pos) /*!< 0x000000FF */ +#define ISO7816_DATA ISO7816_DATA_Msk /*!< Transmit or Receive data */ + +/************** Bits definition for ISO7816x_INFO register ******************/ +#define ISO7816_INFO_RCACK_Pos (0U) +#define ISO7816_INFO_RCACK_Msk (0x1U << ISO7816_INFO_RCACK_Pos) /*!< 0x00000001 */ +#define ISO7816_INFO_RCACK ISO7816_INFO_RCACK_Msk /*!< The received ACK at the end of transmit */ +#define ISO7816_INFO_CHKSUM_Pos (1U) +#define ISO7816_INFO_CHKSUM_Msk (0x1U << ISO7816_INFO_CHKSUM_Pos) /*!< 0x00000002 */ +#define ISO7816_INFO_CHKSUM ISO7816_INFO_CHKSUM_Msk /*!< The transmitted or received data��s check sum bit */ +#define ISO7816_INFO_RCERR_Pos (2U) +#define ISO7816_INFO_RCERR_Msk (0x1U << ISO7816_INFO_RCERR_Pos) /*!< 0x00000004 */ +#define ISO7816_INFO_RCERR ISO7816_INFO_RCERR_Msk /*!< When received data have check sum error */ +#define ISO7816_INFO_SDERR_Pos (3U) +#define ISO7816_INFO_SDERR_Msk (0x1U << ISO7816_INFO_SDERR_Pos) /*!< 0x00000008 */ +#define ISO7816_INFO_SDERR ISO7816_INFO_SDERR_Msk /*!< When the received ACK is 0 during transmit mode */ +#define ISO7816_INFO_LSB_Pos (4U) +#define ISO7816_INFO_LSB_Msk (0x1U << ISO7816_INFO_LSB_Pos) /*!< 0x00000010 */ +#define ISO7816_INFO_LSB ISO7816_INFO_LSB_Msk /*!< MSB/LSB transmit order control register */ +#define ISO7816_INFO_RCIF_Pos (5U) +#define ISO7816_INFO_RCIF_Msk (0x1U << ISO7816_INFO_RCIF_Pos) /*!< 0x00000020 */ +#define ISO7816_INFO_RCIF ISO7816_INFO_RCIF_Msk /*!< Receive interrupt flag */ +#define ISO7816_INFO_SDIF_Pos (6U) +#define ISO7816_INFO_SDIF_Msk (0x1U << ISO7816_INFO_SDIF_Pos) /*!< 0x00000040 */ +#define ISO7816_INFO_SDIF ISO7816_INFO_SDIF_Msk /*!< Transmit interrupt flag */ +#define ISO7816_INFO_OVIF_Pos (7U) +#define ISO7816_INFO_OVIF_Msk (0x1U << ISO7816_INFO_OVIF_Pos) /*!< 0x00000080 */ +#define ISO7816_INFO_OVIF ISO7816_INFO_OVIF_Msk /*!< Receive overflow flag */ + +/************** Bits definition for ISO7816x_CFG register ******************/ +#define ISO7816_CFG_EN_Pos (0U) +#define ISO7816_CFG_EN_Msk (0x1U << ISO7816_CFG_EN_Pos) /*!< 0x00000001 */ +#define ISO7816_CFG_EN ISO7816_CFG_EN_Msk /*!< ISO7816 enable register */ +#define ISO7816_CFG_CHKP_Pos (1U) +#define ISO7816_CFG_CHKP_Msk (0x1U << ISO7816_CFG_CHKP_Pos) /*!< 0x00000002 */ +#define ISO7816_CFG_CHKP ISO7816_CFG_CHKP_Msk /*!< Transmit interrupt enable register */ +//#define ISO7816_CFG_AUTORC_Pos (2U) +//#define ISO7816_CFG_AUTORC_Msk (0x1U << ISO7816_CFG_AUTORC_Pos) /*!< 0x00000004 */ +//#define ISO7816_CFG_AUTORC ISO7816_CFG_AUTORC_Msk /*!< Receive interrupt enable register */ +//#define ISO7816_CFG_AUTOSD_Pos (3U) +//#define ISO7816_CFG_AUTOSD_Msk (0x1U << ISO7816_CFG_AUTOSD_Pos) /*!< 0x00000008 */ +//#define ISO7816_CFG_AUTOSD ISO7816_CFG_AUTOSD_Msk /*!< ACK low period when receive an error data */ +#define ISO7816_CFG_ACKLEN_Pos (4U) +#define ISO7816_CFG_ACKLEN_Msk (0x1U << ISO7816_CFG_ACKLEN_Pos) /*!< 0x00000010 */ +#define ISO7816_CFG_ACKLEN ISO7816_CFG_ACKLEN_Msk /*!< Automatic re-transmit when receive ACK is 0 */ +#define ISO7816_CFG_RCIE_Pos (5U) +#define ISO7816_CFG_RCIE_Msk (0x1U << ISO7816_CFG_RCIE_Pos) /*!< 0x00000020 */ +#define ISO7816_CFG_RCIE ISO7816_CFG_RCIE_Msk /*!< Automatic response ACK as 0 when receive an error data to let transmitter re-send the data */ +#define ISO7816_CFG_SDIE_Pos (6U) +#define ISO7816_CFG_SDIE_Msk (0x1U << ISO7816_CFG_SDIE_Pos) /*!< 0x00000040 */ +#define ISO7816_CFG_SDIE ISO7816_CFG_SDIE_Msk /*!< Parity mode control register */ +#define ISO7816_CFG_OVIE_Pos (7U) +#define ISO7816_CFG_OVIE_Msk (0x1U << ISO7816_CFG_OVIE_Pos) /*!< 0x00000080 */ +#define ISO7816_CFG_OVIE ISO7816_CFG_OVIE_Msk /*!< Receive overrun interrupt enable register */ + +/************** Bits definition for ISO7816x_CLK register ******************/ +#define ISO7816_CLK_CLKDIV_Pos (0U) +#define ISO7816_CLK_CLKDIV_Msk (0x7FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007F */ +#define ISO7816_CLK_CLKDIV ISO7816_CLK_CLKDIV_Msk /*!< The ISO7816 clock divider ratio */ +#define ISO7816_CLK_CLKDIV_1 (0x0U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000000 */ +#define ISO7816_CLK_CLKDIV_2 (0x1U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000001 */ +#define ISO7816_CLK_CLKDIV_3 (0x2U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000002 */ +#define ISO7816_CLK_CLKDIV_4 (0x3U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000003 */ +#define ISO7816_CLK_CLKDIV_5 (0x4U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000004 */ +#define ISO7816_CLK_CLKDIV_6 (0x5U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000005 */ +#define ISO7816_CLK_CLKDIV_7 (0x6U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000006 */ +#define ISO7816_CLK_CLKDIV_8 (0x7U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000007 */ +#define ISO7816_CLK_CLKDIV_9 (0x8U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000008 */ +#define ISO7816_CLK_CLKDIV_10 (0x9U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000009 */ +#define ISO7816_CLK_CLKDIV_11 (0xAU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000A */ +#define ISO7816_CLK_CLKDIV_12 (0xBU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000B */ +#define ISO7816_CLK_CLKDIV_13 (0xCU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000C */ +#define ISO7816_CLK_CLKDIV_14 (0xDU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000D */ +#define ISO7816_CLK_CLKDIV_15 (0xEU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000E */ +#define ISO7816_CLK_CLKDIV_16 (0xFU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000000F */ +#define ISO7816_CLK_CLKDIV_17 (0x10U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000010 */ +#define ISO7816_CLK_CLKDIV_18 (0x11U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000011 */ +#define ISO7816_CLK_CLKDIV_19 (0x12U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000012 */ +#define ISO7816_CLK_CLKDIV_20 (0x13U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000013 */ +#define ISO7816_CLK_CLKDIV_21 (0x14U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000014 */ +#define ISO7816_CLK_CLKDIV_22 (0x15U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000015 */ +#define ISO7816_CLK_CLKDIV_23 (0x16U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000016 */ +#define ISO7816_CLK_CLKDIV_24 (0x17U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000017 */ +#define ISO7816_CLK_CLKDIV_25 (0x18U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000018 */ +#define ISO7816_CLK_CLKDIV_26 (0x19U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000019 */ +#define ISO7816_CLK_CLKDIV_27 (0x1AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001A */ +#define ISO7816_CLK_CLKDIV_28 (0x1BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001B */ +#define ISO7816_CLK_CLKDIV_29 (0x1CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001C */ +#define ISO7816_CLK_CLKDIV_30 (0x1DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001D */ +#define ISO7816_CLK_CLKDIV_31 (0x1EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001E */ +#define ISO7816_CLK_CLKDIV_32 (0x1FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000001F */ +#define ISO7816_CLK_CLKDIV_33 (0x20U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000020 */ +#define ISO7816_CLK_CLKDIV_34 (0x21U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000021 */ +#define ISO7816_CLK_CLKDIV_35 (0x22U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000022 */ +#define ISO7816_CLK_CLKDIV_36 (0x23U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000023 */ +#define ISO7816_CLK_CLKDIV_37 (0x24U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000024 */ +#define ISO7816_CLK_CLKDIV_38 (0x25U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000025 */ +#define ISO7816_CLK_CLKDIV_39 (0x26U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000026 */ +#define ISO7816_CLK_CLKDIV_40 (0x27U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000027 */ +#define ISO7816_CLK_CLKDIV_41 (0x28U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000028 */ +#define ISO7816_CLK_CLKDIV_42 (0x29U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000029 */ +#define ISO7816_CLK_CLKDIV_43 (0x2AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002A */ +#define ISO7816_CLK_CLKDIV_44 (0x2BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002B */ +#define ISO7816_CLK_CLKDIV_45 (0x2CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002C */ +#define ISO7816_CLK_CLKDIV_46 (0x2DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002D */ +#define ISO7816_CLK_CLKDIV_47 (0x2EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002E */ +#define ISO7816_CLK_CLKDIV_48 (0x2FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000002F */ +#define ISO7816_CLK_CLKDIV_49 (0x30U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000030 */ +#define ISO7816_CLK_CLKDIV_50 (0x31U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000031 */ +#define ISO7816_CLK_CLKDIV_51 (0x32U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000032 */ +#define ISO7816_CLK_CLKDIV_52 (0x33U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000033 */ +#define ISO7816_CLK_CLKDIV_53 (0x34U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000034 */ +#define ISO7816_CLK_CLKDIV_54 (0x35U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000035 */ +#define ISO7816_CLK_CLKDIV_55 (0x36U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000036 */ +#define ISO7816_CLK_CLKDIV_56 (0x37U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000037 */ +#define ISO7816_CLK_CLKDIV_57 (0x38U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000038 */ +#define ISO7816_CLK_CLKDIV_58 (0x39U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000039 */ +#define ISO7816_CLK_CLKDIV_59 (0x3AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003A */ +#define ISO7816_CLK_CLKDIV_60 (0x3BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003B */ +#define ISO7816_CLK_CLKDIV_61 (0x3CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003C */ +#define ISO7816_CLK_CLKDIV_62 (0x3DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003D */ +#define ISO7816_CLK_CLKDIV_63 (0x3EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003E */ +#define ISO7816_CLK_CLKDIV_64 (0x3FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000003F */ +#define ISO7816_CLK_CLKDIV_65 (0x40U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000040 */ +#define ISO7816_CLK_CLKDIV_66 (0x41U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000041 */ +#define ISO7816_CLK_CLKDIV_67 (0x42U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000042 */ +#define ISO7816_CLK_CLKDIV_68 (0x43U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000043 */ +#define ISO7816_CLK_CLKDIV_69 (0x44U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000044 */ +#define ISO7816_CLK_CLKDIV_70 (0x45U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000045 */ +#define ISO7816_CLK_CLKDIV_71 (0x46U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000046 */ +#define ISO7816_CLK_CLKDIV_72 (0x47U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000047 */ +#define ISO7816_CLK_CLKDIV_73 (0x48U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000048 */ +#define ISO7816_CLK_CLKDIV_74 (0x49U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000049 */ +#define ISO7816_CLK_CLKDIV_75 (0x4AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004A */ +#define ISO7816_CLK_CLKDIV_76 (0x4BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004B */ +#define ISO7816_CLK_CLKDIV_77 (0x4CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004C */ +#define ISO7816_CLK_CLKDIV_78 (0x4DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004D */ +#define ISO7816_CLK_CLKDIV_79 (0x4EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004E */ +#define ISO7816_CLK_CLKDIV_80 (0x4FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000004F */ +#define ISO7816_CLK_CLKDIV_81 (0x50U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000050 */ +#define ISO7816_CLK_CLKDIV_82 (0x51U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000051 */ +#define ISO7816_CLK_CLKDIV_83 (0x52U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000052 */ +#define ISO7816_CLK_CLKDIV_84 (0x53U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000053 */ +#define ISO7816_CLK_CLKDIV_85 (0x54U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000054 */ +#define ISO7816_CLK_CLKDIV_86 (0x55U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000055 */ +#define ISO7816_CLK_CLKDIV_87 (0x56U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000056 */ +#define ISO7816_CLK_CLKDIV_88 (0x57U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000057 */ +#define ISO7816_CLK_CLKDIV_89 (0x58U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000058 */ +#define ISO7816_CLK_CLKDIV_90 (0x59U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000059 */ +#define ISO7816_CLK_CLKDIV_91 (0x5AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005A */ +#define ISO7816_CLK_CLKDIV_92 (0x5BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005B */ +#define ISO7816_CLK_CLKDIV_93 (0x5CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005C */ +#define ISO7816_CLK_CLKDIV_94 (0x5DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005D */ +#define ISO7816_CLK_CLKDIV_95 (0x5EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005E */ +#define ISO7816_CLK_CLKDIV_96 (0x5FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000005F */ +#define ISO7816_CLK_CLKDIV_97 (0x60U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000060 */ +#define ISO7816_CLK_CLKDIV_98 (0x61U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000061 */ +#define ISO7816_CLK_CLKDIV_99 (0x62U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000062 */ +#define ISO7816_CLK_CLKDIV_100 (0x63U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000063 */ +#define ISO7816_CLK_CLKDIV_101 (0x64U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000064 */ +#define ISO7816_CLK_CLKDIV_102 (0x65U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000065 */ +#define ISO7816_CLK_CLKDIV_103 (0x66U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000066 */ +#define ISO7816_CLK_CLKDIV_104 (0x67U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000067 */ +#define ISO7816_CLK_CLKDIV_105 (0x68U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000068 */ +#define ISO7816_CLK_CLKDIV_106 (0x69U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000069 */ +#define ISO7816_CLK_CLKDIV_107 (0x6AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006A */ +#define ISO7816_CLK_CLKDIV_108 (0x6BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006B */ +#define ISO7816_CLK_CLKDIV_109 (0x6CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006C */ +#define ISO7816_CLK_CLKDIV_110 (0x6DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006D */ +#define ISO7816_CLK_CLKDIV_111 (0x6EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006E */ +#define ISO7816_CLK_CLKDIV_112 (0x6FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000006F */ +#define ISO7816_CLK_CLKDIV_113 (0x70U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000070 */ +#define ISO7816_CLK_CLKDIV_114 (0x71U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000071 */ +#define ISO7816_CLK_CLKDIV_115 (0x72U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000072 */ +#define ISO7816_CLK_CLKDIV_116 (0x73U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000073 */ +#define ISO7816_CLK_CLKDIV_117 (0x74U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000074 */ +#define ISO7816_CLK_CLKDIV_118 (0x75U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000075 */ +#define ISO7816_CLK_CLKDIV_119 (0x76U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000076 */ +#define ISO7816_CLK_CLKDIV_120 (0x77U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000077 */ +#define ISO7816_CLK_CLKDIV_121 (0x78U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000078 */ +#define ISO7816_CLK_CLKDIV_122 (0x79U << ISO7816_CLK_CLKDIV_Pos) /*!< 0x00000079 */ +#define ISO7816_CLK_CLKDIV_123 (0x7AU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007A */ +#define ISO7816_CLK_CLKDIV_124 (0x7BU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007B */ +#define ISO7816_CLK_CLKDIV_125 (0x7CU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007C */ +#define ISO7816_CLK_CLKDIV_126 (0x7DU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007D */ +#define ISO7816_CLK_CLKDIV_127 (0x7EU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007E */ +#define ISO7816_CLK_CLKDIV_128 (0x7FU << ISO7816_CLK_CLKDIV_Pos) /*!< 0x0000007F */ +#define ISO7816_CLK_CLKEN_Pos (7U) +#define ISO7816_CLK_CLKEN_Msk (0x1U << ISO7816_CLK_CLKEN_Pos) /*!< 0x00000080 */ +#define ISO7816_CLK_CLKEN ISO7816_CLK_CLKEN_Msk /*!< ISO7816 clock output enable */ + +/******************************************************************************/ +/* */ +/* Timer Controller (timer) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for TMRx_CTRL register ******************/ +#define TMR_CTRL_EN_Pos (0U) +#define TMR_CTRL_EN_Msk (0x1U << TMR_CTRL_EN_Pos) /*!< 0x00000001 */ +#define TMR_CTRL_EN TMR_CTRL_EN_Msk /*!< Timer x enable control register */ +#define TMR_CTRL_EXTEN_Pos (1U) +#define TMR_CTRL_EXTEN_Msk (0x1U << TMR_CTRL_EXTEN_Pos) /*!< 0x00000002 */ +#define TMR_CTRL_EXTEN TMR_CTRL_EXTEN_Msk /*!< Select ext_clk as clock enable */ +#define TMR_CTRL_EXTCLK_Pos (2U) +#define TMR_CTRL_EXTCLK_Msk (0x1U << TMR_CTRL_EXTCLK_Pos) /*!< 0x00000004 */ +#define TMR_CTRL_EXTCLK TMR_CTRL_EXTCLK_Msk /*!< Select ext_clk as clock source */ +#define TMR_CTRL_INTEN_Pos (3U) +#define TMR_CTRL_INTEN_Msk (0x1U << TMR_CTRL_INTEN_Pos) /*!< 0x00000008 */ +#define TMR_CTRL_INTEN TMR_CTRL_INTEN_Msk /*!< Timer x interrupt enable register */ + +/************** Bits definition for TMRx_VALUE register ******************/ +#define TMR_VALUE_VALUE_Pos (0U) +#define TMR_VALUE_VALUE_Msk (0xFFFFFFFFU << TMR_VALUE_VALUE_Pos) /*!< 0xFFFFFFFF */ +#define TMR_VALUE_VALUE TMR_VALUE_VALUE_Msk /*!< Timer x current value register */ + +/************** Bits definition for TMRx_RELOAD register ******************/ +#define TMR_RELOAD_RELOAD_Pos (0U) +#define TMR_RELOAD_RELOAD_Msk (0xFFFFFFFFU << TMR_RELOAD_RELOAD_Pos) /*!< 0xFFFFFFFF */ +#define TMR_RELOAD_RELOAD TMR_RELOAD_RELOAD_Msk /*!< Timer x reload value register. A write to this register sets the current value */ + +/************** Bits definition for TMRx_INT register ******************/ +#define TMR_INT_INT_Pos (0U) +#define TMR_INT_INT_Msk (0x1U << TMR_INT_INT_Pos) /*!< 0x00000001 */ +#define TMR_INT_INT TMR_INT_INT_Msk /*!< Timer x interrupt status register, write 1 to clear this bit. */ + +/******************************************************************************/ +/* */ +/* PWM controller (PWM) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for PWMx_CTL register ******************/ +#define PWM_CTL_IFG_Pos (0U) +#define PWM_CTL_IFG_Msk (0x1U << PWM_CTL_IFG_Pos) /*!< 0x00000001 */ +#define PWM_CTL_IFG PWM_CTL_IFG_Msk /*!< PWM Timer x��s interrupt status flag, write 1 to clear this flag to 0 */ +#define PWM_CTL_IE_Pos (1U) +#define PWM_CTL_IE_Msk (0x1U << PWM_CTL_IE_Pos) /*!< 0x00000002 */ +#define PWM_CTL_IE PWM_CTL_IE_Msk /*!< PWM Timer x��s interrupt enable register */ +#define PWM_CTL_CLR_Pos (2U) +#define PWM_CTL_CLR_Msk (0x1U << PWM_CTL_CLR_Pos) /*!< 0x00000004 */ +#define PWM_CTL_CLR PWM_CTL_CLR_Msk /*!< TAR clear register, when this bit is set to 1, the TAR will be clear to 0 */ +#define PWM_CTL_TESL_Pos (3U) +#define PWM_CTL_TESL_Msk (0x1U << PWM_CTL_TESL_Pos) /*!< 0x00000008 */ +#define PWM_CTL_TESL PWM_CTL_TESL_Msk /*!< Clock source selection */ +#define PWM_CTL_TESL_APBDIV128 (0x0U << PWM_CTL_TESL_Pos) /*!< 0x00000000 */ +#define PWM_CTL_TESL_APBDIV1 (0x1U << PWM_CTL_TESL_Pos) /*!< 0x00000008 */ +#define PWM_CTL_MC_Pos (4U) +#define PWM_CTL_MC_Msk (0x3U << PWM_CTL_MC_Pos) /*!< 0x00000030 */ +#define PWM_CTL_MC PWM_CTL_MC_Msk /*!< PWM Timer mode control */ +#define PWM_CTL_MC_STOP (0x0U << PWM_CTL_MC_Pos) /*!< 0x00000000 */ +#define PWM_CTL_MC_UP (0x1U << PWM_CTL_MC_Pos) /*!< 0x00000010 */ +#define PWM_CTL_MC_CONTINUE (0x2U << PWM_CTL_MC_Pos) /*!< 0x00000020 */ +#define PWM_CTL_MC_UPDOWN (0x3U << PWM_CTL_MC_Pos) /*!< 0x00000030 */ +#define PWM_CTL_ID_Pos (6U) +#define PWM_CTL_ID_Msk (0x3U << PWM_CTL_ID_Pos) /*!< 0x000000C0 */ +#define PWM_CTL_ID PWM_CTL_ID_Msk /*!< PWM timer x��s Input clock divider control */ +#define PWM_CTL_ID_DIV2 (0x0U << PWM_CTL_ID_Pos) /*!< 0x00000000 */ +#define PWM_CTL_ID_DIV4 (0x1U << PWM_CTL_ID_Pos) /*!< 0x00000040 */ +#define PWM_CTL_ID_DIV8 (0x2U << PWM_CTL_ID_Pos) /*!< 0x00000080 */ +#define PWM_CTL_ID_DIV16 (0x3U << PWM_CTL_ID_Pos) /*!< 0x000000C0 */ + +/************** Bits definition for PWMx_TAR register ******************/ +#define PWM_TAR_TAR_Pos (0U) +#define PWM_TAR_TAR_Msk (0xFFFFU << PWM_TAR_TAR_Pos) /*!< 0x0000FFFF */ +#define PWM_TAR_TAR PWM_TAR_TAR_Msk /*!< PWM Timer x��s current count register */ + +/************** Bits definition for PWMx_CCTLy register ******************/ +#define PWM_CCTL_CCIGG_Pos (0U) +#define PWM_CCTL_CCIGG_Msk (0x1U << PWM_CCTL_CCIGG_Pos) /*!< 0x00000001 */ +#define PWM_CCTL_CCIGG PWM_CCTL_CCIGG_Msk /*!< Under compare mode, this bit will be set when TAR=CCRx. */ +//#define PWM_CCTL_COV_Pos (1U) +//#define PWM_CCTL_COV_Msk (0x1U << PWM_CCTL_COV_Pos) /*!< 0x00000002 */ +//#define PWM_CCTL_COV PWM_CCTL_COV_Msk /*!< Capture overflow flag, this bit will be set when the CCIFG bit is 1 and another capture event is coming */ +#define PWM_CCTL_OUT_Pos (2U) +#define PWM_CCTL_OUT_Msk (0x1U << PWM_CCTL_OUT_Pos) /*!< 0x00000004 */ +#define PWM_CCTL_OUT PWM_CCTL_OUT_Msk /*!< This bit is used to control the output value of OUTx when OUTMOD is set to 0 */ +//#define PWM_CCTL_CCI_Pos (3U) +//#define PWM_CCTL_CCI_Msk (0x1U << PWM_CCTL_CCI_Pos) /*!< 0x00000008 */ +//#define PWM_CCTL_CCI PWM_CCTL_CCI_Msk /*!< The read only register shows the current status of INx��s input */ +#define PWM_CCTL_CCIE_Pos (4U) +#define PWM_CCTL_CCIE_Msk (0x1U << PWM_CCTL_CCIE_Pos) /*!< 0x00000010 */ +#define PWM_CCTL_CCIE PWM_CCTL_CCIE_Msk /*!< Compare interrupt enable register */ +#define PWM_CCTL_OUTMOD_Pos (5U) +#define PWM_CCTL_OUTMOD_Msk (0x7U << PWM_CCTL_OUTMOD_Pos) /*!< 0x000000E0 */ +#define PWM_CCTL_OUTMOD PWM_CCTL_OUTMOD_Msk /*!< Output mode selection */ +#define PWM_CCTL_OUTMOD_CONST (0x00UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_SET (0x01UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE_RESET (0x02UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_SET_RESET (0x03UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE (0x04UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_RESET (0x05UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_TOGGLE_SET (0x06UL << PWM_CCTL_OUTMOD_Pos) +#define PWM_CCTL_OUTMOD_RESET_SET (0x07UL << PWM_CCTL_OUTMOD_Pos) +//#define PWM_CCTL_CAP_Pos (8U) +//#define PWM_CCTL_CAP_Msk (0x1U << PWM_CCTL_CAP_Pos) /*!< 0x00000100 */ +//#define PWM_CCTL_CAP PWM_CCTL_CAP_Msk /*!< Capture/Compare mode selection */ +#define PWM_CCTL_OUTEN_Pos (9U) +#define PWM_CCTL_OUTEN_Msk (0x1U << PWM_CCTL_OUTEN_Pos) /*!< 0x00000200 */ +#define PWM_CCTL_OUTEN PWM_CCTL_OUTEN_Msk /*!< OUTx output enable control register */ +//#define PWM_CCTL_SCCI_Pos (10U) +//#define PWM_CCTL_SCCI_Msk (0x1U << PWM_CCTL_SCCI_Pos) /*!< 0x00000400 */ +//#define PWM_CCTL_SCCI PWM_CCTL_SCCI_Msk /*!< The read only register shows the INx��s input value when the TAR is equal to CCRx */ +//#define PWM_CCTL_CM_Pos (14U) +//#define PWM_CCTL_CM_Msk (0x3U << PWM_CCTL_CM_Pos) /*!< 0x0000C000 */ +//#define PWM_CCTL_CM PWM_CCTL_CM_Msk /*!< Capture edge selection */ +//#define PWM_CCTL_CM_DISABLE (0x0U << PWM_CCTL_CM_Pos) +//#define PWM_CCTL_CM_RISING (0x1U << PWM_CCTL_CM_Pos) +//#define PWM_CCTL_CM_FALLING (0x2U << PWM_CCTL_CM_Pos) +//#define PWM_CCTL_CM_BOTH (0x3U << PWM_CCTL_CM_Pos) + +/************** Bits definition for PWMx_CCRy register ******************/ +#define PWM_CCR_CCR_Pos (0U) +#define PWM_CCR_CCR_Msk (0xFFFFU << PWM_CCR_CCR_Pos) /*!< 0x0000FFFF */ +#define PWM_CCR_CCR PWM_CCR_CCR_Msk /*!< Compare/Capture data register */ + +/************** Bits definition for PWM_O_SEL register ******************/ +#define PWM_O_SEL_O_SEL0_Pos (0U) +#define PWM_O_SEL_O_SEL0_Msk (0xFU << PWM_O_SEL_O_SEL0_Pos) /*!< 0x0000000F */ +#define PWM_O_SEL_O_SEL0 PWM_O_SEL_O_SEL0_Msk /*!< External output PWM0��s output selection register */ +#define PWM_O_SEL_O_SEL1_Pos (4U) +#define PWM_O_SEL_O_SEL1_Msk (0xFU << PWM_O_SEL_O_SEL1_Pos) /*!< 0x000000F0 */ +#define PWM_O_SEL_O_SEL1 PWM_O_SEL_O_SEL1_Msk /*!< External output PWM1��s output selection register */ +#define PWM_O_SEL_O_SEL2_Pos (8U) +#define PWM_O_SEL_O_SEL2_Msk (0xFU << PWM_O_SEL_O_SEL2_Pos) /*!< 0x000000F00 */ +#define PWM_O_SEL_O_SEL2 PWM_O_SEL_O_SEL2_Msk /*!< External output PWM2��s output selection register */ +#define PWM_O_SEL_O_SEL3_Pos (12U) +#define PWM_O_SEL_O_SEL3_Msk (0xFU << PWM_O_SEL_O_SEL3_Pos) /*!< 0x0000F000 */ +#define PWM_O_SEL_O_SEL3 PWM_O_SEL_O_SEL3_Msk /*!< External output PWM3��s output selection register */ + +///************** Bits definition for PWM_I_SEL01 register ******************/ +//#define PWM_I_SEL01_I_SEL00_Pos (0U) +//#define PWM_I_SEL01_I_SEL00_Msk (0x3U << PWM_I_SEL01_I_SEL00_Pos) /*!< 0x00000003 */ +//#define PWM_I_SEL01_I_SEL00 PWM_I_SEL01_I_SEL00_Msk /*!< PWM0��s IN0 external input control */ +//#define PWM_I_SEL01_I_SEL01_Pos (2U) +//#define PWM_I_SEL01_I_SEL01_Msk (0x3U << PWM_I_SEL01_I_SEL01_Pos) /*!< 0x000000C */ +//#define PWM_I_SEL01_I_SEL01 PWM_I_SEL01_I_SEL01_Msk /*!< PWM0��s IN1 external input control */ +//#define PWM_I_SEL01_I_SEL02_Pos (4U) +//#define PWM_I_SEL01_I_SEL02_Msk (0x3U << PWM_I_SEL01_I_SEL02_Pos) /*!< 0x00000030 */ +//#define PWM_I_SEL01_I_SEL02 PWM_I_SEL01_I_SEL02_Msk /*!< PWM0��s IN2 external input control */ +//#define PWM_I_SEL01_I_SEL10_Pos (16U) +//#define PWM_I_SEL01_I_SEL10_Msk (0x3U << PWM_I_SEL01_I_SEL10_Pos) /*!< 0x00030000 */ +//#define PWM_I_SEL01_I_SEL10 PWM_I_SEL01_I_SEL10_Msk /*!< PWM1��s IN0 external input control */ +//#define PWM_I_SEL01_I_SEL11_Pos (18U) +//#define PWM_I_SEL01_I_SEL11_Msk (0x3U << PWM_I_SEL01_I_SEL11_Pos) /*!< 0x000C0000 */ +//#define PWM_I_SEL01_I_SEL11 PWM_I_SEL01_I_SEL11_Msk /*!< PWM1��s IN1 external input control */ +//#define PWM_I_SEL01_I_SEL12_Pos (20U) +//#define PWM_I_SEL01_I_SEL12_Msk (0x3U << PWM_I_SEL01_I_SEL12_Pos) /*!< 0x00300000 */ +//#define PWM_I_SEL01_I_SEL12 PWM_I_SEL01_I_SEL12_Msk /*!< PWM1��s IN2 external input control */ +// +///************** Bits definition for PWM_I_SEL23 register ******************/ +//#define PWM_I_SEL23_I_SEL20_Pos (0U) +//#define PWM_I_SEL23_I_SEL20_Msk (0x3U << PWM_I_SEL23_I_SEL20_Pos) /*!< 0x00000003 */ +//#define PWM_I_SEL23_I_SEL20 PWM_I_SEL23_I_SEL20_Msk /*!< PWM2��s IN0 external input control */ +//#define PWM_I_SEL23_I_SEL21_Pos (2U) +//#define PWM_I_SEL23_I_SEL21_Msk (0x3U << PWM_I_SEL23_I_SEL21_Pos) /*!< 0x0000000C */ +//#define PWM_I_SEL23_I_SEL21 PWM_I_SEL23_I_SEL21_Msk /*!< PWM2��s IN1 external input control */ +//#define PWM_I_SEL23_I_SEL22_Pos (4U) +//#define PWM_I_SEL23_I_SEL22_Msk (0x3U << PWM_I_SEL23_I_SEL22_Pos) /*!< 0x00000030 */ +//#define PWM_I_SEL23_I_SEL22 PWM_I_SEL23_I_SEL22_Msk /*!< PWM2��s IN2 external input control */ +//#define PWM_I_SEL23_I_SEL30_Pos (16U) +//#define PWM_I_SEL23_I_SEL30_Msk (0x3U << PWM_I_SEL23_I_SEL30_Pos) /*!< 0x00030000 */ +//#define PWM_I_SEL23_I_SEL30 PWM_I_SEL23_I_SEL30_Msk /*!< PWM3��s IN0 external input control */ +//#define PWM_I_SEL23_I_SEL31_Pos (18U) +//#define PWM_I_SEL23_I_SEL31_Msk (0x3U << PWM_I_SEL23_I_SEL31_Pos) /*!< 0x000C0000 */ +//#define PWM_I_SEL23_I_SEL31 PWM_I_SEL23_I_SEL31_Msk /*!< PWM3��s IN1 external input control */ +//#define PWM_I_SEL23_I_SEL32_Pos (20U) +//#define PWM_I_SEL23_I_SEL32_Msk (0x3U << PWM_I_SEL23_I_SEL32_Pos) /*!< 0x00300000 */ +//#define PWM_I_SEL23_I_SEL32 PWM_I_SEL23_I_SEL32_Msk /*!< PWM3��s IN2 external input control */ + +/******************************************************************************/ +/* */ +/* LCD controller (LCD) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for LCD_FB00~27 register ******************/ +#define LCD_FB_WORD_Pos (0U) +#define LCD_FB_WORD_Msk (0xFFFFFFFFU << LCD_FB_WORD_Pos) /*!< 0xFFFFFFFF */ +#define LCD_FB_WORD LCD_FB_WORD_Msk /*!< LCD Frame buffer x register bit0~31 */ +#define LCD_FB_BYTE0_Pos (0U) +#define LCD_FB_BYTE0_Msk (0xFFU << LCD_FB_BYTE0_Pos) /*!< 0x000000FF */ +#define LCD_FB_BYTE0 LCD_FB_BYTE0_Msk /*!< LCD Frame buffer x register bit0~7 */ +#define LCD_FB_BYTE1_Pos (8U) +#define LCD_FB_BYTE1_Msk (0xFFU << LCD_FB_BYTE1_Pos) /*!< 0x0000FF00 */ +#define LCD_FB_BYTE1 LCD_FB_BYTE1_Msk /*!< LCD Frame buffer x register bit8~15 */ +#define LCD_FB_BYTE2_Pos (16U) +#define LCD_FB_BYTE2_Msk (0xFFU << LCD_FB_BYTE2_Pos) /*!< 0x00FF0000 */ +#define LCD_FB_BYTE2 LCD_FB_BYTE2_Msk /*!< LCD Frame buffer x register bit16~23 */ +#define LCD_FB_BYTE3_Pos (24U) +#define LCD_FB_BYTE3_Msk (0xFFU << LCD_FB_BYTE3_Pos) /*!< 0xFF000000 */ +#define LCD_FB_BYTE3 LCD_FB_BYTE3_Msk /*!< LCD Frame buffer x register bit24~31 */ + +/************** Bits definition for LCD_CTRL register ******************/ +#define LCD_CTRL_FRQ_Pos (0U) +#define LCD_CTRL_FRQ_Msk (0x3U << LCD_CTRL_FRQ_Pos) /*!< 0x00000003 */ +#define LCD_CTRL_FRQ LCD_CTRL_FRQ_Msk /*!< LCD scan frequency */ +#define LCD_CTRL_FRQ_64HZ (0x0U << LCD_CTRL_FRQ_Pos) /*!< 0x00000000 */ +#define LCD_CTRL_FRQ_128HZ (0x1U << LCD_CTRL_FRQ_Pos) /*!< 0x00000001 */ +#define LCD_CTRL_FRQ_256HZ (0x2U << LCD_CTRL_FRQ_Pos) /*!< 0x00000002 */ +#define LCD_CTRL_FRQ_512HZ (0x3U << LCD_CTRL_FRQ_Pos) /*!< 0x00000003 */ +#define LCD_CTRL_DRV_Pos (2U) +#define LCD_CTRL_DRV_Msk (0x3U << LCD_CTRL_DRV_Pos) /*!< 0x0000000C */ +#define LCD_CTRL_DRV LCD_CTRL_DRV_Msk /*!< LCD driving resister control register */ +#define LCD_CTRL_DRV_300KOHM (0x0U << LCD_CTRL_DRV_Pos) /*!< 0x00000000 */ +#define LCD_CTRL_DRV_600KOHM (0x1U << LCD_CTRL_DRV_Pos) /*!< 0x00000004 */ +#define LCD_CTRL_DRV_150KOHM (0x2U << LCD_CTRL_DRV_Pos) /*!< 0x00000008 */ +#define LCD_CTRL_DRV_200KOHM (0x3U << LCD_CTRL_DRV_Pos) /*!< 0x0000000C */ +#define LCD_CTRL_TYPE_Pos (4U) +#define LCD_CTRL_TYPE_Msk (0x3U << LCD_CTRL_TYPE_Pos) /*!< 0x00000030 */ +#define LCD_CTRL_TYPE LCD_CTRL_TYPE_Msk /*!< LCD type control register */ +#define LCD_CTRL_TYPE_4COM (0x0U << LCD_CTRL_TYPE_Pos) /*!< 0x00000000 */ +#define LCD_CTRL_TYPE_6COM (0x1U << LCD_CTRL_TYPE_Pos) /*!< 0x00000010 */ +#define LCD_CTRL_TYPE_8COM (0x2U << LCD_CTRL_TYPE_Pos) /*!< 0x00000020 */ +#define LCD_CTRL_EN_Pos (7U) +#define LCD_CTRL_EN_Msk (0x1U << LCD_CTRL_EN_Pos) /*!< 0x00000080 */ +#define LCD_CTRL_EN LCD_CTRL_EN_Msk /*!< LCD controller enable register */ + +/************** Bits definition for LCD_CTRL2 register ******************/ +#define LCD_CTRL2_BKFILL_Pos (4U) +#define LCD_CTRL2_BKFILL_Msk (0x1U << LCD_CTRL2_BKFILL_Pos) /*!< 0x00000010 */ +#define LCD_CTRL2_BKFILL LCD_CTRL2_BKFILL_Msk /*!< Fill value at blank period */ +#define LCD_CTRL2_FBMODE_Pos (6U) +#define LCD_CTRL2_FBMODE_Msk (0x3U << LCD_CTRL2_FBMODE_Pos) /*!< 0x000000C0 */ +#define LCD_CTRL2_FBMODE LCD_CTRL2_FBMODE_Msk /*!< LCD frame buffer switch mode control register */ +#define LCD_CTRL2_FBMODE_BUFA (0x0U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000000 */ +#define LCD_CTRL2_FBMODE_BUFAANDBUFB (0x1U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000040 */ +#define LCD_CTRL2_FBMODE_BUFAANDBLANK (0x2U << LCD_CTRL2_FBMODE_Pos) /*!< 0x00000080 */ +#define LCD_CTRL2_SWPR_Pos (8U) +#define LCD_CTRL2_SWPR_Msk (0xFFU << LCD_CTRL2_SWPR_Pos) /*!< 0x000FF00 */ +#define LCD_CTRL2_SWPR LCD_CTRL2_SWPR_Msk /*!< Frame buffer switch period */ + +/************** Bits definition for LCD_SEGCTRL0 register ******************/ +#define LCD_SEGCTRL0_SEG0_Pos (0U) +#define LCD_SEGCTRL0_SEG0_Msk (0x1U << LCD_SEGCTRL0_SEG0_Pos) /*!< 0x00000001 */ +#define LCD_SEGCTRL0_SEG0 LCD_SEGCTRL0_SEG0_Msk /*!< SEG 0��s enable control */ +#define LCD_SEGCTRL0_SEG1_Pos (1U) +#define LCD_SEGCTRL0_SEG1_Msk (0x1U << LCD_SEGCTRL0_SEG1_Pos) /*!< 0x00000002 */ +#define LCD_SEGCTRL0_SEG1 LCD_SEGCTRL0_SEG1_Msk /*!< SEG 1��s enable control */ +#define LCD_SEGCTRL0_SEG2_Pos (2U) +#define LCD_SEGCTRL0_SEG2_Msk (0x1U << LCD_SEGCTRL0_SEG2_Pos) /*!< 0x00000004 */ +#define LCD_SEGCTRL0_SEG2 LCD_SEGCTRL0_SEG2_Msk /*!< SEG 2��s enable control */ +#define LCD_SEGCTRL0_SEG3_Pos (3U) +#define LCD_SEGCTRL0_SEG3_Msk (0x1U << LCD_SEGCTRL0_SEG3_Pos) /*!< 0x00000008 */ +#define LCD_SEGCTRL0_SEG3 LCD_SEGCTRL0_SEG3_Msk /*!< SEG 3��s enable control */ +#define LCD_SEGCTRL0_SEG4_Pos (4U) +#define LCD_SEGCTRL0_SEG4_Msk (0x1U << LCD_SEGCTRL0_SEG4_Pos) /*!< 0x00000010 */ +#define LCD_SEGCTRL0_SEG4 LCD_SEGCTRL0_SEG4_Msk /*!< SEG 4��s enable control */ +#define LCD_SEGCTRL0_SEG5_Pos (5U) +#define LCD_SEGCTRL0_SEG5_Msk (0x1U << LCD_SEGCTRL0_SEG5_Pos) /*!< 0x00000020 */ +#define LCD_SEGCTRL0_SEG5 LCD_SEGCTRL0_SEG5_Msk /*!< SEG 5��s enable control */ +#define LCD_SEGCTRL0_SEG6_Pos (6U) +#define LCD_SEGCTRL0_SEG6_Msk (0x1U << LCD_SEGCTRL0_SEG6_Pos) /*!< 0x00000040 */ +#define LCD_SEGCTRL0_SEG6 LCD_SEGCTRL0_SEG6_Msk /*!< SEG 6��s enable control */ +#define LCD_SEGCTRL0_SEG7_Pos (7U) +#define LCD_SEGCTRL0_SEG7_Msk (0x1U << LCD_SEGCTRL0_SEG7_Pos) /*!< 0x00000080 */ +#define LCD_SEGCTRL0_SEG7 LCD_SEGCTRL0_SEG7_Msk /*!< SEG 7��s enable control */ +#define LCD_SEGCTRL0_SEG8_Pos (8U) +#define LCD_SEGCTRL0_SEG8_Msk (0x1U << LCD_SEGCTRL0_SEG8_Pos) /*!< 0x00000100 */ +#define LCD_SEGCTRL0_SEG8 LCD_SEGCTRL0_SEG8_Msk /*!< SEG 8��s enable control */ +#define LCD_SEGCTRL0_SEG9_Pos (9U) +#define LCD_SEGCTRL0_SEG9_Msk (0x1U << LCD_SEGCTRL0_SEG9_Pos) /*!< 0x00000200 */ +#define LCD_SEGCTRL0_SEG9 LCD_SEGCTRL0_SEG9_Msk /*!< SEG 9��s enable control */ +#define LCD_SEGCTRL0_SEG10_Pos (10U) +#define LCD_SEGCTRL0_SEG10_Msk (0x1U << LCD_SEGCTRL0_SEG10_Pos) /*!< 0x00000400 */ +#define LCD_SEGCTRL0_SEG10 LCD_SEGCTRL0_SEG10_Msk /*!< SEG 10��s enable control */ +#define LCD_SEGCTRL0_SEG11_Pos (11U) +#define LCD_SEGCTRL0_SEG11_Msk (0x1U << LCD_SEGCTRL0_SEG11_Pos) /*!< 0x00000800 */ +#define LCD_SEGCTRL0_SEG11 LCD_SEGCTRL0_SEG11_Msk /*!< SEG 11��s enable control */ +#define LCD_SEGCTRL0_SEG12_Pos (12U) +#define LCD_SEGCTRL0_SEG12_Msk (0x1U << LCD_SEGCTRL0_SEG12_Pos) /*!< 0x00001000 */ +#define LCD_SEGCTRL0_SEG12 LCD_SEGCTRL0_SEG12_Msk /*!< SEG 12��s enable control */ +#define LCD_SEGCTRL0_SEG13_Pos (13U) +#define LCD_SEGCTRL0_SEG13_Msk (0x1U << LCD_SEGCTRL0_SEG13_Pos) /*!< 0x00002000 */ +#define LCD_SEGCTRL0_SEG13 LCD_SEGCTRL0_SEG13_Msk /*!< SEG 13��s enable control */ +#define LCD_SEGCTRL0_SEG14_Pos (14U) +#define LCD_SEGCTRL0_SEG14_Msk (0x1U << LCD_SEGCTRL0_SEG14_Pos) /*!< 0x00004000 */ +#define LCD_SEGCTRL0_SEG14 LCD_SEGCTRL0_SEG14_Msk /*!< SEG 14��s enable control */ +#define LCD_SEGCTRL0_SEG15_Pos (15U) +#define LCD_SEGCTRL0_SEG15_Msk (0x1U << LCD_SEGCTRL0_SEG15_Pos) /*!< 0x00008000 */ +#define LCD_SEGCTRL0_SEG15 LCD_SEGCTRL0_SEG15_Msk /*!< SEG 15��s enable control */ +#define LCD_SEGCTRL0_SEG16_Pos (16U) +#define LCD_SEGCTRL0_SEG16_Msk (0x1U << LCD_SEGCTRL0_SEG16_Pos) /*!< 0x00010000 */ +#define LCD_SEGCTRL0_SEG16 LCD_SEGCTRL0_SEG16_Msk /*!< SEG 16��s enable control */ +#define LCD_SEGCTRL0_SEG17_Pos (17U) +#define LCD_SEGCTRL0_SEG17_Msk (0x1U << LCD_SEGCTRL0_SEG17_Pos) /*!< 0x00020000 */ +#define LCD_SEGCTRL0_SEG17 LCD_SEGCTRL0_SEG17_Msk /*!< SEG 17��s enable control */ +#define LCD_SEGCTRL0_SEG18_Pos (18U) +#define LCD_SEGCTRL0_SEG18_Msk (0x1U << LCD_SEGCTRL0_SEG18_Pos) /*!< 0x00040000 */ +#define LCD_SEGCTRL0_SEG18 LCD_SEGCTRL0_SEG18_Msk /*!< SEG 18��s enable control */ +#define LCD_SEGCTRL0_SEG19_Pos (19U) +#define LCD_SEGCTRL0_SEG19_Msk (0x1U << LCD_SEGCTRL0_SEG19_Pos) /*!< 0x00080000 */ +#define LCD_SEGCTRL0_SEG19 LCD_SEGCTRL0_SEG19_Msk /*!< SEG 19��s enable control */ +#define LCD_SEGCTRL0_SEG20_Pos (20U) +#define LCD_SEGCTRL0_SEG20_Msk (0x1U << LCD_SEGCTRL0_SEG20_Pos) /*!< 0x00100000 */ +#define LCD_SEGCTRL0_SEG20 LCD_SEGCTRL0_SEG20_Msk /*!< SEG 20��s enable control */ +#define LCD_SEGCTRL0_SEG21_Pos (21U) +#define LCD_SEGCTRL0_SEG21_Msk (0x1U << LCD_SEGCTRL0_SEG21_Pos) /*!< 0x00200000 */ +#define LCD_SEGCTRL0_SEG21 LCD_SEGCTRL0_SEG21_Msk /*!< SEG 21��s enable control */ +#define LCD_SEGCTRL0_SEG22_Pos (22U) +#define LCD_SEGCTRL0_SEG22_Msk (0x1U << LCD_SEGCTRL0_SEG22_Pos) /*!< 0x00400000 */ +#define LCD_SEGCTRL0_SEG22 LCD_SEGCTRL0_SEG22_Msk /*!< SEG 22��s enable control */ +#define LCD_SEGCTRL0_SEG23_Pos (23U) +#define LCD_SEGCTRL0_SEG23_Msk (0x1U << LCD_SEGCTRL0_SEG23_Pos) /*!< 0x00800000 */ +#define LCD_SEGCTRL0_SEG23 LCD_SEGCTRL0_SEG23_Msk /*!< SEG 23��s enable control */ +#define LCD_SEGCTRL0_SEG24_Pos (24U) +#define LCD_SEGCTRL0_SEG24_Msk (0x1U << LCD_SEGCTRL0_SEG24_Pos) /*!< 0x01000000 */ +#define LCD_SEGCTRL0_SEG24 LCD_SEGCTRL0_SEG24_Msk /*!< SEG 24��s enable control */ +#define LCD_SEGCTRL0_SEG25_Pos (25U) +#define LCD_SEGCTRL0_SEG25_Msk (0x1U << LCD_SEGCTRL0_SEG25_Pos) /*!< 0x02000000 */ +#define LCD_SEGCTRL0_SEG25 LCD_SEGCTRL0_SEG25_Msk /*!< SEG 25��s enable control */ +#define LCD_SEGCTRL0_SEG26_Pos (26U) +#define LCD_SEGCTRL0_SEG26_Msk (0x1U << LCD_SEGCTRL0_SEG26_Pos) /*!< 0x04000000 */ +#define LCD_SEGCTRL0_SEG26 LCD_SEGCTRL0_SEG26_Msk /*!< SEG 26��s enable control */ +#define LCD_SEGCTRL0_SEG27_Pos (27U) +#define LCD_SEGCTRL0_SEG27_Msk (0x1U << LCD_SEGCTRL0_SEG27_Pos) /*!< 0x08000000 */ +#define LCD_SEGCTRL0_SEG27 LCD_SEGCTRL0_SEG27_Msk /*!< SEG 27��s enable control */ +#define LCD_SEGCTRL0_SEG28_Pos (28U) +#define LCD_SEGCTRL0_SEG28_Msk (0x1U << LCD_SEGCTRL0_SEG28_Pos) /*!< 0x10000000 */ +#define LCD_SEGCTRL0_SEG28 LCD_SEGCTRL0_SEG28_Msk /*!< SEG 28��s enable control */ +#define LCD_SEGCTRL0_SEG29_Pos (29U) +#define LCD_SEGCTRL0_SEG29_Msk (0x1U << LCD_SEGCTRL0_SEG29_Pos) /*!< 0x20000000 */ +#define LCD_SEGCTRL0_SEG29 LCD_SEGCTRL0_SEG29_Msk /*!< SEG 29��s enable control */ +#define LCD_SEGCTRL0_SEG30_Pos (30U) +#define LCD_SEGCTRL0_SEG30_Msk (0x1U << LCD_SEGCTRL0_SEG30_Pos) /*!< 0x40000000 */ +#define LCD_SEGCTRL0_SEG30 LCD_SEGCTRL0_SEG30_Msk /*!< SEG 30��s enable control */ +#define LCD_SEGCTRL0_SEG31_Pos (31U) +#define LCD_SEGCTRL0_SEG31_Msk (0x1U << LCD_SEGCTRL0_SEG31_Pos) /*!< 0x80000000 */ +#define LCD_SEGCTRL0_SEG31 LCD_SEGCTRL0_SEG31_Msk /*!< SEG 31��s enable control */ + +/************** Bits definition for LCD_SEGCTRL1 register ******************/ +#define LCD_SEGCTRL1_SEG32_Pos (0U) +#define LCD_SEGCTRL1_SEG32_Msk (0x1U << LCD_SEGCTRL1_SEG32_Pos) /*!< 0x00000001 */ +#define LCD_SEGCTRL1_SEG32 LCD_SEGCTRL1_SEG32_Msk /*!< SEG 32��s enable control */ +#define LCD_SEGCTRL1_SEG33_Pos (1U) +#define LCD_SEGCTRL1_SEG33_Msk (0x1U << LCD_SEGCTRL1_SEG33_Pos) /*!< 0x00000002 */ +#define LCD_SEGCTRL1_SEG33 LCD_SEGCTRL1_SEG33_Msk /*!< SEG 33��s enable control */ +#define LCD_SEGCTRL1_SEG34_Pos (2U) +#define LCD_SEGCTRL1_SEG34_Msk (0x1U << LCD_SEGCTRL1_SEG34_Pos) /*!< 0x00000004 */ +#define LCD_SEGCTRL1_SEG34 LCD_SEGCTRL1_SEG34_Msk /*!< SEG 34��s enable control */ +#define LCD_SEGCTRL1_SEG35_Pos (3U) +#define LCD_SEGCTRL1_SEG35_Msk (0x1U << LCD_SEGCTRL1_SEG35_Pos) /*!< 0x00000008 */ +#define LCD_SEGCTRL1_SEG35 LCD_SEGCTRL1_SEG35_Msk /*!< SEG 35��s enable control */ +#define LCD_SEGCTRL1_SEG36_Pos (4U) +#define LCD_SEGCTRL1_SEG36_Msk (0x1U << LCD_SEGCTRL1_SEG36_Pos) /*!< 0x00000010 */ +#define LCD_SEGCTRL1_SEG36 LCD_SEGCTRL1_SEG36_Msk /*!< SEG 36��s enable control */ +#define LCD_SEGCTRL1_SEG37_Pos (5U) +#define LCD_SEGCTRL1_SEG37_Msk (0x1U << LCD_SEGCTRL1_SEG37_Pos) /*!< 0x00000020 */ +#define LCD_SEGCTRL1_SEG37 LCD_SEGCTRL1_SEG37_Msk /*!< SEG 37��s enable control */ +#define LCD_SEGCTRL1_SEG38_Pos (6U) +#define LCD_SEGCTRL1_SEG38_Msk (0x1U << LCD_SEGCTRL1_SEG38_Pos) /*!< 0x00000040 */ +#define LCD_SEGCTRL1_SEG38 LCD_SEGCTRL1_SEG38_Msk /*!< SEG 38��s enable control */ +#define LCD_SEGCTRL1_SEG39_Pos (7U) +#define LCD_SEGCTRL1_SEG39_Msk (0x1U << LCD_SEGCTRL1_SEG39_Pos) /*!< 0x00000080 */ +#define LCD_SEGCTRL1_SEG39 LCD_SEGCTRL1_SEG39_Msk /*!< SEG 39��s enable control */ +#define LCD_SEGCTRL1_SEG40_Pos (8U) +#define LCD_SEGCTRL1_SEG40_Msk (0x1U << LCD_SEGCTRL1_SEG40_Pos) /*!< 0x00000100 */ +#define LCD_SEGCTRL1_SEG40 LCD_SEGCTRL1_SEG40_Msk /*!< SEG 40��s enable control */ +#define LCD_SEGCTRL1_SEG41_Pos (9U) +#define LCD_SEGCTRL1_SEG41_Msk (0x1U << LCD_SEGCTRL1_SEG41_Pos) /*!< 0x00000200 */ +#define LCD_SEGCTRL1_SEG41 LCD_SEGCTRL1_SEG41_Msk /*!< SEG 41��s enable control */ +#define LCD_SEGCTRL1_SEG42_Pos (10U) +#define LCD_SEGCTRL1_SEG42_Msk (0x1U << LCD_SEGCTRL1_SEG42_Pos) /*!< 0x00000400 */ +#define LCD_SEGCTRL1_SEG42 LCD_SEGCTRL1_SEG42_Msk /*!< SEG 42��s enable control */ +#define LCD_SEGCTRL1_SEG43_Pos (11U) +#define LCD_SEGCTRL1_SEG43_Msk (0x1U << LCD_SEGCTRL1_SEG43_Pos) /*!< 0x00000800 */ +#define LCD_SEGCTRL1_SEG43 LCD_SEGCTRL1_SEG43_Msk /*!< SEG 43��s enable control */ +#define LCD_SEGCTRL1_SEG44_Pos (12U) +#define LCD_SEGCTRL1_SEG44_Msk (0x1U << LCD_SEGCTRL1_SEG44_Pos) /*!< 0x00001000 */ +#define LCD_SEGCTRL1_SEG44 LCD_SEGCTRL1_SEG44_Msk /*!< SEG 44��s enable control */ +#define LCD_SEGCTRL1_SEG45_Pos (13U) +#define LCD_SEGCTRL1_SEG45_Msk (0x1U << LCD_SEGCTRL1_SEG45_Pos) /*!< 0x00002000 */ +#define LCD_SEGCTRL1_SEG45 LCD_SEGCTRL1_SEG45_Msk /*!< SEG 45��s enable control */ +#define LCD_SEGCTRL1_SEG46_Pos (14U) +#define LCD_SEGCTRL1_SEG46_Msk (0x1U << LCD_SEGCTRL1_SEG46_Pos) /*!< 0x00004000 */ +#define LCD_SEGCTRL1_SEG46 LCD_SEGCTRL1_SEG46_Msk /*!< SEG 46��s enable control */ +#define LCD_SEGCTRL1_SEG47_Pos (15U) +#define LCD_SEGCTRL1_SEG47_Msk (0x1U << LCD_SEGCTRL1_SEG47_Pos) /*!< 0x00008000 */ +#define LCD_SEGCTRL1_SEG47 LCD_SEGCTRL1_SEG47_Msk /*!< SEG 47��s enable control */ +#define LCD_SEGCTRL1_SEG48_Pos (16U) +#define LCD_SEGCTRL1_SEG48_Msk (0x1U << LCD_SEGCTRL1_SEG48_Pos) /*!< 0x00010000 */ +#define LCD_SEGCTRL1_SEG48 LCD_SEGCTRL1_SEG48_Msk /*!< SEG 48��s enable control */ +#define LCD_SEGCTRL1_SEG49_Pos (17U) +#define LCD_SEGCTRL1_SEG49_Msk (0x1U << LCD_SEGCTRL1_SEG49_Pos) /*!< 0x00020000 */ +#define LCD_SEGCTRL1_SEG49 LCD_SEGCTRL1_SEG49_Msk /*!< SEG 49��s enable control */ +#define LCD_SEGCTRL1_SEG50_Pos (18U) +#define LCD_SEGCTRL1_SEG50_Msk (0x1U << LCD_SEGCTRL1_SEG50_Pos) /*!< 0x00040000 */ +#define LCD_SEGCTRL1_SEG50 LCD_SEGCTRL1_SEG50_Msk /*!< SEG 50��s enable control */ +#define LCD_SEGCTRL1_SEG51_Pos (19U) +#define LCD_SEGCTRL1_SEG51_Msk (0x1U << LCD_SEGCTRL1_SEG51_Pos) /*!< 0x00080000 */ +#define LCD_SEGCTRL1_SEG51 LCD_SEGCTRL1_SEG51_Msk /*!< SEG 51��s enable control */ +#define LCD_SEGCTRL1_SEG52_Pos (20U) +#define LCD_SEGCTRL1_SEG52_Msk (0x1U << LCD_SEGCTRL1_SEG52_Pos) /*!< 0x00100000 */ +#define LCD_SEGCTRL1_SEG52 LCD_SEGCTRL1_SEG52_Msk /*!< SEG 52��s enable control */ +#define LCD_SEGCTRL1_SEG53_Pos (21U) +#define LCD_SEGCTRL1_SEG53_Msk (0x1U << LCD_SEGCTRL1_SEG53_Pos) /*!< 0x00200000 */ +#define LCD_SEGCTRL1_SEG53 LCD_SEGCTRL1_SEG53_Msk /*!< SEG 53��s enable control */ +#define LCD_SEGCTRL1_SEG54_Pos (22U) +#define LCD_SEGCTRL1_SEG54_Msk (0x1U << LCD_SEGCTRL1_SEG54_Pos) /*!< 0x00400000 */ +#define LCD_SEGCTRL1_SEG54 LCD_SEGCTRL1_SEG54_Msk /*!< SEG 54��s enable control */ +#define LCD_SEGCTRL1_SEG55_Pos (23U) +#define LCD_SEGCTRL1_SEG55_Msk (0x1U << LCD_SEGCTRL1_SEG55_Pos) /*!< 0x00800000 */ +#define LCD_SEGCTRL1_SEG55 LCD_SEGCTRL1_SEG55_Msk /*!< SEG 55��s enable control */ +#define LCD_SEGCTRL1_SEG56_Pos (24U) +#define LCD_SEGCTRL1_SEG56_Msk (0x1U << LCD_SEGCTRL1_SEG56_Pos) /*!< 0x01000000 */ +#define LCD_SEGCTRL1_SEG56 LCD_SEGCTRL1_SEG56_Msk /*!< SEG 56��s enable control */ +#define LCD_SEGCTRL1_SEG57_Pos (25U) +#define LCD_SEGCTRL1_SEG57_Msk (0x1U << LCD_SEGCTRL1_SEG57_Pos) /*!< 0x02000000 */ +#define LCD_SEGCTRL1_SEG57 LCD_SEGCTRL1_SEG57_Msk /*!< SEG 57��s enable control */ +#define LCD_SEGCTRL1_SEG58_Pos (26U) +#define LCD_SEGCTRL1_SEG58_Msk (0x1U << LCD_SEGCTRL1_SEG58_Pos) /*!< 0x04000000 */ +#define LCD_SEGCTRL1_SEG58 LCD_SEGCTRL1_SEG58_Msk /*!< SEG 58��s enable control */ +#define LCD_SEGCTRL1_SEG59_Pos (27U) +#define LCD_SEGCTRL1_SEG59_Msk (0x1U << LCD_SEGCTRL1_SEG59_Pos) /*!< 0x08000000 */ +#define LCD_SEGCTRL1_SEG59 LCD_SEGCTRL1_SEG59_Msk /*!< SEG 59��s enable control */ +#define LCD_SEGCTRL1_SEG60_Pos (28U) +#define LCD_SEGCTRL1_SEG60_Msk (0x1U << LCD_SEGCTRL1_SEG60_Pos) /*!< 0x10000000 */ +#define LCD_SEGCTRL1_SEG60 LCD_SEGCTRL1_SEG60_Msk /*!< SEG 60��s enable control */ +#define LCD_SEGCTRL1_SEG61_Pos (29U) +#define LCD_SEGCTRL1_SEG61_Msk (0x1U << LCD_SEGCTRL1_SEG61_Pos) /*!< 0x20000000 */ +#define LCD_SEGCTRL1_SEG61 LCD_SEGCTRL1_SEG61_Msk /*!< SEG 61��s enable control */ +#define LCD_SEGCTRL1_SEG62_Pos (30U) +#define LCD_SEGCTRL1_SEG62_Msk (0x1U << LCD_SEGCTRL1_SEG62_Pos) /*!< 0x40000000 */ +#define LCD_SEGCTRL1_SEG62 LCD_SEGCTRL1_SEG62_Msk /*!< SEG 62��s enable control */ +#define LCD_SEGCTRL1_SEG63_Pos (31U) +#define LCD_SEGCTRL1_SEG63_Msk (0x1U << LCD_SEGCTRL1_SEG63_Pos) /*!< 0x80000000 */ +#define LCD_SEGCTRL1_SEG63 LCD_SEGCTRL1_SEG63_Msk /*!< SEG 63��s enable control */ + +/************** Bits definition for LCD_SEGCTRL2 register ******************/ +#define LCD_SEGCTRL2_SEG64_Pos (0U) +#define LCD_SEGCTRL2_SEG64_Msk (0x1U << LCD_SEGCTRL2_SEG64_Pos) /*!< 0x00000001 */ +#define LCD_SEGCTRL2_SEG64 LCD_SEGCTRL2_SEG64_Msk /*!< SEG 64��s enable control */ +#define LCD_SEGCTRL2_SEG65_Pos (1U) +#define LCD_SEGCTRL2_SEG65_Msk (0x1U << LCD_SEGCTRL2_SEG65_Pos) /*!< 0x00000002 */ +#define LCD_SEGCTRL2_SEG65 LCD_SEGCTRL2_SEG65_Msk /*!< SEG 65��s enable control */ +#define LCD_SEGCTRL2_SEG66_Pos (2U) +#define LCD_SEGCTRL2_SEG66_Msk (0x1U << LCD_SEGCTRL2_SEG66_Pos) /*!< 0x00000004 */ +#define LCD_SEGCTRL2_SEG66 LCD_SEGCTRL2_SEG66_Msk /*!< SEG 66��s enable control */ +#define LCD_SEGCTRL2_SEG67_Pos (3U) +#define LCD_SEGCTRL2_SEG67_Msk (0x1U << LCD_SEGCTRL2_SEG67_Pos) /*!< 0x00000008 */ +#define LCD_SEGCTRL2_SEG67 LCD_SEGCTRL2_SEG67_Msk /*!< SEG 67��s enable control */ +#define LCD_SEGCTRL2_SEG68_Pos (4U) +#define LCD_SEGCTRL2_SEG68_Msk (0x1U << LCD_SEGCTRL2_SEG68_Pos) /*!< 0x00000010 */ +#define LCD_SEGCTRL2_SEG68 LCD_SEGCTRL2_SEG68_Msk /*!< SEG 68��s enable control */ +#define LCD_SEGCTRL2_SEG69_Pos (5U) +#define LCD_SEGCTRL2_SEG69_Msk (0x1U << LCD_SEGCTRL2_SEG69_Pos) /*!< 0x00000020 */ +#define LCD_SEGCTRL2_SEG69 LCD_SEGCTRL2_SEG69_Msk /*!< SEG 69��s enable control */ +#define LCD_SEGCTRL2_SEG70_Pos (6U) +#define LCD_SEGCTRL2_SEG70_Msk (0x1U << LCD_SEGCTRL2_SEG70_Pos) /*!< 0x00000040 */ +#define LCD_SEGCTRL2_SEG70 LCD_SEGCTRL2_SEG70_Msk /*!< SEG 70��s enable control */ +#define LCD_SEGCTRL2_SEG71_Pos (7U) +#define LCD_SEGCTRL2_SEG71_Msk (0x1U << LCD_SEGCTRL2_SEG71_Pos) /*!< 0x00000080 */ +#define LCD_SEGCTRL2_SEG71 LCD_SEGCTRL2_SEG71_Msk /*!< SEG 71��s enable control */ +#define LCD_SEGCTRL2_SEG72_Pos (8U) +#define LCD_SEGCTRL2_SEG72_Msk (0x1U << LCD_SEGCTRL2_SEG72_Pos) /*!< 0x00000100 */ +#define LCD_SEGCTRL2_SEG72 LCD_SEGCTRL2_SEG72_Msk /*!< SEG 72��s enable control */ +#define LCD_SEGCTRL2_SEG73_Pos (9U) +#define LCD_SEGCTRL2_SEG73_Msk (0x1U << LCD_SEGCTRL2_SEG73_Pos) /*!< 0x00000200 */ +#define LCD_SEGCTRL2_SEG73 LCD_SEGCTRL2_SEG73_Msk /*!< SEG 73��s enable control */ +#define LCD_SEGCTRL2_SEG74_Pos (10U) +#define LCD_SEGCTRL2_SEG74_Msk (0x1U << LCD_SEGCTRL2_SEG74_Pos) /*!< 0x00000400 */ +#define LCD_SEGCTRL2_SEG74 LCD_SEGCTRL2_SEG74_Msk /*!< SEG 74��s enable control */ +#define LCD_SEGCTRL2_SEG75_Pos (11U) +#define LCD_SEGCTRL2_SEG75_Msk (0x1U << LCD_SEGCTRL2_SEG75_Pos) /*!< 0x00000800 */ +#define LCD_SEGCTRL2_SEG75 LCD_SEGCTRL2_SEG75_Msk /*!< SEG 75��s enable control */ +#define LCD_SEGCTRL2_SEG76_Pos (12U) +#define LCD_SEGCTRL2_SEG76_Msk (0x1U << LCD_SEGCTRL2_SEG76_Pos) /*!< 0x00001000 */ +#define LCD_SEGCTRL2_SEG76 LCD_SEGCTRL2_SEG76_Msk /*!< SEG 76��s enable control */ +#define LCD_SEGCTRL2_SEG77_Pos (13U) +#define LCD_SEGCTRL2_SEG77_Msk (0x1U << LCD_SEGCTRL2_SEG77_Pos) /*!< 0x00002000 */ +#define LCD_SEGCTRL2_SEG77 LCD_SEGCTRL2_SEG77_Msk /*!< SEG 77��s enable control */ +#define LCD_SEGCTRL2_SEG78_Pos (14U) +#define LCD_SEGCTRL2_SEG78_Msk (0x1U << LCD_SEGCTRL2_SEG78_Pos) /*!< 0x00004000 */ +#define LCD_SEGCTRL2_SEG78 LCD_SEGCTRL2_SEG78_Msk /*!< SEG 78��s enable control */ +#define LCD_SEGCTRL2_SEG79_Pos (15U) +#define LCD_SEGCTRL2_SEG79_Msk (0x1U << LCD_SEGCTRL2_SEG79_Pos) /*!< 0x00008000 */ +#define LCD_SEGCTRL2_SEG79 LCD_SEGCTRL2_SEG79_Msk /*!< SEG 79��s enable control */ + +/******************************************************************************/ +/* */ +/* SPI controller (SPI) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for SPIx_CTRL register ******************/ +#define SPI_CTRL_SCKSEL_Pos (0U) +#define SPI_CTRL_SCKSEL_Msk (0x7U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000007 */ +#define SPI_CTRL_SCKSEL SPI_CTRL_SCKSEL_Msk /*!< Master mode clock selection */ +#define SPI_CTRL_SCKSEL_0 (0x1U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000001 */ +#define SPI_CTRL_SCKSEL_1 (0x2U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL_SCKSEL_2 (0x4U << SPI_CTRL_SCKSEL_Pos) /*!< 0x00000004 */ +#define SPI_CTRL_SCKPOL_Pos (4U) +#define SPI_CTRL_SCKPOL_Msk (0x1U << SPI_CTRL_SCKPOL_Pos) /*!< 0x00000010 */ +#define SPI_CTRL_SCKPOL SPI_CTRL_SCKPOL_Msk /*!< SPI clock polarity */ +#define SPI_CTRL_SCKPHA_Pos (5U) +#define SPI_CTRL_SCKPHA_Msk (0x1U << SPI_CTRL_SCKPHA_Pos) /*!< 0x00000020 */ +#define SPI_CTRL_SCKPHA SPI_CTRL_SCKPHA_Msk /*!< SPI clock phase */ +#define SPI_CTRL_MOD_Pos (8U) +#define SPI_CTRL_MOD_Msk (0x1U << SPI_CTRL_MOD_Pos) /*!< 0x00000100 */ +#define SPI_CTRL_MOD SPI_CTRL_MOD_Msk /*!< SPI Mode Selection register */ +#define SPI_CTRL_SWAP_Pos (9U) +#define SPI_CTRL_SWAP_Msk (0x1U << SPI_CTRL_SWAP_Pos) /*!< 0x00000200 */ +#define SPI_CTRL_SWAP SPI_CTRL_SWAP_Msk /*!< SPI MISO/MOSI swap control register */ +#define SPI_CTRL_CSGPIO_Pos (10U) +#define SPI_CTRL_CSGPIO_Msk (0x1U << SPI_CTRL_CSGPIO_Pos) /*!< 0x00000400 */ +#define SPI_CTRL_CSGPIO SPI_CTRL_CSGPIO_Msk /*!< SPI CS pin is controlled by GPIO or H/W */ +#define SPI_CTRL_SPIRST_Pos (11U) +#define SPI_CTRL_SPIRST_Msk (0x1U << SPI_CTRL_SPIRST_Pos) /*!< 0x00000800 */ +#define SPI_CTRL_SPIRST SPI_CTRL_SPIRST_Msk /*!< SPI Soft Reset */ +#define SPI_CTRL_SPIEN_Pos (15U) +#define SPI_CTRL_SPIEN_Msk (0x1U << SPI_CTRL_SPIEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL_SPIEN SPI_CTRL_SPIEN_Msk /*!< SPI enable */ + +/************** Bits definition for SPIx_TXSTS register ******************/ +#define SPI_TXSTS_TXFFLAG_Pos (0U) +#define SPI_TXSTS_TXFFLAG_Msk (0x7U << SPI_TXSTS_TXFFLAG_Pos) /*!< 0x0000000F */ +#define SPI_TXSTS_TXFFLAG SPI_TXSTS_TXFFLAG_Msk /*!< Transmit FIFO Data Level */ +#define SPI_TXSTS_TXFLEV_Pos (4U) +#define SPI_TXSTS_TXFLEV_Msk (0x7U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000070 */ +#define SPI_TXSTS_TXFLEV SPI_TXSTS_TXFLEV_Msk /*!< Transmit FIFO interrupt level register */ +#define SPI_TXSTS_TXFLEV_0 (0x1U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000010 */ +#define SPI_TXSTS_TXFLEV_1 (0x2U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000020 */ +#define SPI_TXSTS_TXFLEV_2 (0x4U << SPI_TXSTS_TXFLEV_Pos) /*!< 0x00000040 */ +#define SPI_TXSTS_TXFUR_Pos (8U) +#define SPI_TXSTS_TXFUR_Msk (0x1U << SPI_TXSTS_TXFUR_Pos) /*!< 0x00000100 */ +#define SPI_TXSTS_TXFUR SPI_TXSTS_TXFUR_Msk /*!< Transmit FIFO under run register */ +#define SPI_TXSTS_TXEMPTY_Pos (9U) +#define SPI_TXSTS_TXEMPTY_Msk (0x1U << SPI_TXSTS_TXEMPTY_Pos) /*!< 0x00000200 */ +#define SPI_TXSTS_TXEMPTY SPI_TXSTS_TXEMPTY_Msk /*!< Transmot FIFO empty register */ +#define SPI_TXSTS_TXIEN_Pos (14U) +#define SPI_TXSTS_TXIEN_Msk (0x1U << SPI_TXSTS_TXIEN_Pos) /*!< 0x00004000 */ +#define SPI_TXSTS_TXIEN SPI_TXSTS_TXIEN_Msk /*!< SPI Transmit Interrupt Enable */ +#define SPI_TXSTS_TXIF_Pos (15U) +#define SPI_TXSTS_TXIF_Msk (0x1U << SPI_TXSTS_TXIF_Pos) /*!< 0x00008000 */ +#define SPI_TXSTS_TXIF SPI_TXSTS_TXIF_Msk /*!< SPI Transmit Interrupt flag */ + +/************** Bits definition for SPIx_TXDAT register ******************/ +#define SPI_TXDAT_SPITXD_Pos (0U) +#define SPI_TXDAT_SPITXD_Msk (0xFFU << SPI_TXDAT_SPITXD_Pos) /*!< 0x000000FF */ +#define SPI_TXDAT_SPITXD SPI_TXDAT_SPITXD_Msk /*!< Write data to SPI Transmit FIFO */ + +/************** Bits definition for SPIx_RXSTS register ******************/ +#define SPI_RXSTS_RXFFLAG_Pos (0U) +#define SPI_RXSTS_RXFFLAG_Msk (0x7U << SPI_RXSTS_RXFFLAG_Pos) /*!< 0x0000000F */ +#define SPI_RXSTS_RXFFLAG SPI_RXSTS_RXFFLAG_Msk /*!< Receive FIFO Data Level */ +#define SPI_RXSTS_RXFLEV_Pos (4U) +#define SPI_RXSTS_RXFLEV_Msk (0x7U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000070 */ +#define SPI_RXSTS_RXFLEV SPI_RXSTS_RXFLEV_Msk /*!< Receive FIFO interrupt level register */ +#define SPI_RXSTS_RXFLEV_0 (0x1U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000010 */ +#define SPI_RXSTS_RXFLEV_1 (0x2U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000020 */ +#define SPI_RXSTS_RXFLEV_2 (0x4U << SPI_RXSTS_RXFLEV_Pos) /*!< 0x00000040 */ +#define SPI_RXSTS_RXFOV_Pos (8U) +#define SPI_RXSTS_RXFOV_Msk (0x1U << SPI_RXSTS_RXFOV_Pos) /*!< 0x00000100 */ +#define SPI_RXSTS_RXFOV SPI_RXSTS_RXFOV_Msk /*!< Receive FIFO over run register */ +#define SPI_RXSTS_RXFULL_Pos (9U) +#define SPI_RXSTS_RXFULL_Msk (0x1U << SPI_RXSTS_RXFULL_Pos) /*!< 0x00000200 */ +#define SPI_RXSTS_RXFULL SPI_RXSTS_RXFULL_Msk /*!< Receive FIFO full register */ +#define SPI_RXSTS_RXIEN_Pos (14U) +#define SPI_RXSTS_RXIEN_Msk (0x1U << SPI_RXSTS_RXIEN_Pos) /*!< 0x00004000 */ +#define SPI_RXSTS_RXIEN SPI_RXSTS_RXIEN_Msk /*!< SPI Receive Interrupt Enable */ +#define SPI_RXSTS_RXIF_Pos (15U) +#define SPI_RXSTS_RXIF_Msk (0x1U << SPI_RXSTS_RXIF_Pos) /*!< 0x00008000 */ +#define SPI_RXSTS_RXIF SPI_RXSTS_RXIF_Msk /*!< SPI Receive Interrupt flag */ + +/************** Bits definition for SPIx_RXDAT register ******************/ +#define SPI_RXDAT_SPIRXD_Pos (0U) +#define SPI_RXDAT_SPIRXD_Msk (0xFFU << SPI_RXDAT_SPIRXD_Pos) /*!< 0x000000FF */ +#define SPI_RXDAT_SPIRXD SPI_RXDAT_SPIRXD_Msk /*!< Read data from SPI Receive FIFO */ + +/************** Bits definition for SPIx_MISC register ******************/ +#define SPI_MISC_TFE_Pos (0U) +#define SPI_MISC_TFE_Msk (0x1U << SPI_MISC_TFE_Pos) /*!< 0x0000001 */ +#define SPI_MISC_TFE SPI_MISC_TFE_Msk /*!< Transmit FIFO Empty Flag */ +#define SPI_MISC_TNF_Pos (1U) +#define SPI_MISC_TNF_Msk (0x1U << SPI_MISC_TNF_Pos) /*!< 0x0000002 */ +#define SPI_MISC_TNF SPI_MISC_TNF_Msk /*!< Transmit FIFO Not Full Flag */ +#define SPI_MISC_RNE_Pos (2U) +#define SPI_MISC_RNE_Msk (0x1U << SPI_MISC_RNE_Pos) /*!< 0x0000004 */ +#define SPI_MISC_RNE SPI_MISC_RNE_Msk /*!< Receive FIFO Not Empty Flag */ +#define SPI_MISC_RFF_Pos (3U) +#define SPI_MISC_RFF_Msk (0x1U << SPI_MISC_RFF_Pos) /*!< 0x0000008 */ +#define SPI_MISC_RFF SPI_MISC_RFF_Msk /*!< Receive FIFO Full Flag */ +#define SPI_MISC_BSY_Pos (4U) +#define SPI_MISC_BSY_Msk (0x1U << SPI_MISC_BSY_Pos) /*!< 0x0000010 */ +#define SPI_MISC_BSY SPI_MISC_BSY_Msk /*!< SPI Controller Busy Flag */ +#define SPI_MISC_SMART_Pos (8U) +#define SPI_MISC_SMART_Msk (0x1U << SPI_MISC_SMART_Pos) /*!< 0x0000100 */ +#define SPI_MISC_SMART SPI_MISC_SMART_Msk /*!< SPI FIFO SMART Mode Register */ +#define SPI_MISC_OVER_Pos (9U) +#define SPI_MISC_OVER_Msk (0x1U << SPI_MISC_OVER_Pos) /*!< 0x0000200 */ +#define SPI_MISC_OVER SPI_MISC_OVER_Msk /*!< SPI FIFO Over Write Mode */ + +/******************************************************************************/ +/* */ +/* I2C controller (I2C) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for I2C_DATA register ******************/ +#define I2C_DATA_DATA_Pos (0U) +#define I2C_DATA_DATA_Msk (0xFFU << I2C_DATA_DATA_Pos) /*!< 0x00000FF */ +#define I2C_DATA_DATA I2C_DATA_DATA_Msk /*!< The I2C_DATA register contains a byte to be transmitted through I2C bus or a byte which has just been received through I2C bus */ + +/************** Bits definition for I2C_ADDR register ******************/ +#define I2C_ADDR_GC_Pos (0U) +#define I2C_ADDR_GC_Msk (0x1U << I2C_ADDR_GC_Pos) /*!< 0x0000001 */ +#define I2C_ADDR_GC I2C_ADDR_GC_Msk /*!< General Call Address Acknowledge */ +#define I2C_ADDR_SLA_Pos (1U) +#define I2C_ADDR_SLA_Msk (0xFEU << I2C_ADDR_SLA_Pos) /*!< 0x00000FE */ +#define I2C_ADDR_SLA I2C_ADDR_SLA_Msk /*!< Own I2C slave address (7 bit) */ + +/************** Bits definition for I2C_CTRL register ******************/ +#define I2C_CTRL_CR_Pos (0U) +#define I2C_CTRL_CR_Msk (0x83U << I2C_CTRL_CR_Pos) /*!< 0x0000083 */ +#define I2C_CTRL_CR I2C_CTRL_CR_Msk /*!< Clock rate bit0-2 */ +#define I2C_CTRL_CR_0 (0x0U << I2C_CTRL_CR_Pos) /*!< 0x0000000 */ +#define I2C_CTRL_CR_1 (0x1U << I2C_CTRL_CR_Pos) /*!< 0x0000001 */ +#define I2C_CTRL_CR_2 (0x2U << I2C_CTRL_CR_Pos) /*!< 0x0000002 */ +#define I2C_CTRL_CR_3 (0x3U << I2C_CTRL_CR_Pos) /*!< 0x0000003 */ +#define I2C_CTRL_CR_4 (0x80U << I2C_CTRL_CR_Pos) /*!< 0x0000080 */ +#define I2C_CTRL_CR_5 (0x81U << I2C_CTRL_CR_Pos) /*!< 0x0000081 */ +#define I2C_CTRL_CR_6 (0x82U << I2C_CTRL_CR_Pos) /*!< 0x0000082 */ +#define I2C_CTRL_CR_7 (0x83U << I2C_CTRL_CR_Pos) /*!< 0x0000083 */ +#define I2C_CTRL_AA_Pos (2U) +#define I2C_CTRL_AA_Msk (0x1U << I2C_CTRL_AA_Pos) /*!< 0x0000004 */ +#define I2C_CTRL_AA I2C_CTRL_AA_Msk /*!< Assert Acknowledge Flag */ +#define I2C_CTRL_SI_Pos (3U) +#define I2C_CTRL_SI_Msk (0x1U << I2C_CTRL_SI_Pos) /*!< 0x0000008 */ +#define I2C_CTRL_SI I2C_CTRL_SI_Msk /*!< Serial Interrupt Flag */ +#define I2C_CTRL_STO_Pos (4U) +#define I2C_CTRL_STO_Msk (0x1U << I2C_CTRL_STO_Pos) /*!< 0x0000010 */ +#define I2C_CTRL_STO I2C_CTRL_STO_Msk /*!< STOP Flag */ +#define I2C_CTRL_STA_Pos (5U) +#define I2C_CTRL_STA_Msk (0x1U << I2C_CTRL_STA_Pos) /*!< 0x0000020 */ +#define I2C_CTRL_STA I2C_CTRL_STA_Msk /*!< START Flag */ +#define I2C_CTRL_EN_Pos (6U) +#define I2C_CTRL_EN_Msk (0x1U << I2C_CTRL_EN_Pos) /*!< 0x0000040 */ +#define I2C_CTRL_EN I2C_CTRL_EN_Msk /*!< I2C enable bit */ + +/************** Bits definition for I2C_STS register ******************/ +#define I2C_STS_STS_Pos (3U) +#define I2C_STS_STS_Msk (0x1FU << I2C_STS_STS_Pos) /*!< 0x00000F8 */ +#define I2C_STS_STS I2C_STS_STS_Msk /*!< I2C Status Code */ +#define I2C_STS_STS_0x00 (0x0U << I2C_STS_STS_Pos) /*!< 0x0000000 */ +#define I2C_STS_STS_0x08 (0x1U << I2C_STS_STS_Pos) /*!< 0x0000008 */ +#define I2C_STS_STS_0x10 (0x2U << I2C_STS_STS_Pos) /*!< 0x0000010 */ +#define I2C_STS_STS_0x18 (0x3U << I2C_STS_STS_Pos) /*!< 0x0000018 */ +#define I2C_STS_STS_0x20 (0x4U << I2C_STS_STS_Pos) /*!< 0x0000020 */ +#define I2C_STS_STS_0x28 (0x5U << I2C_STS_STS_Pos) /*!< 0x0000028 */ +#define I2C_STS_STS_0x30 (0x6U << I2C_STS_STS_Pos) /*!< 0x0000030 */ +#define I2C_STS_STS_0x38 (0x7U << I2C_STS_STS_Pos) /*!< 0x0000038 */ +#define I2C_STS_STS_0x40 (0x8U << I2C_STS_STS_Pos) /*!< 0x0000040 */ +#define I2C_STS_STS_0x48 (0x9U << I2C_STS_STS_Pos) /*!< 0x0000048 */ +#define I2C_STS_STS_0x50 (0xAU << I2C_STS_STS_Pos) /*!< 0x0000050 */ +#define I2C_STS_STS_0x58 (0xBU << I2C_STS_STS_Pos) /*!< 0x0000058 */ +#define I2C_STS_STS_0x60 (0xCU << I2C_STS_STS_Pos) /*!< 0x0000060 */ +#define I2C_STS_STS_0x68 (0xDU << I2C_STS_STS_Pos) /*!< 0x0000068 */ +#define I2C_STS_STS_0x70 (0xEU << I2C_STS_STS_Pos) /*!< 0x0000070 */ +#define I2C_STS_STS_0x78 (0xFU << I2C_STS_STS_Pos) /*!< 0x0000078 */ +#define I2C_STS_STS_0x80 (0x10U << I2C_STS_STS_Pos) /*!< 0x0000080 */ +#define I2C_STS_STS_0x88 (0x11U << I2C_STS_STS_Pos) /*!< 0x0000088 */ +#define I2C_STS_STS_0x90 (0x12U << I2C_STS_STS_Pos) /*!< 0x0000090 */ +#define I2C_STS_STS_0x98 (0x13U << I2C_STS_STS_Pos) /*!< 0x0000098 */ +#define I2C_STS_STS_0xA0 (0x14U << I2C_STS_STS_Pos) /*!< 0x00000A0 */ +#define I2C_STS_STS_0xA8 (0x15U << I2C_STS_STS_Pos) /*!< 0x00000A8 */ +#define I2C_STS_STS_0xB0 (0x16U << I2C_STS_STS_Pos) /*!< 0x00000B0 */ +#define I2C_STS_STS_0xB8 (0x17U << I2C_STS_STS_Pos) /*!< 0x00000B8 */ +#define I2C_STS_STS_0xC0 (0x18U << I2C_STS_STS_Pos) /*!< 0x00000C0 */ +#define I2C_STS_STS_0xC8 (0x19U << I2C_STS_STS_Pos) /*!< 0x00000C8 */ +#define I2C_STS_STS_0xF8 (0x1FU << I2C_STS_STS_Pos) /*!< 0x00000F8 */ + +/************** Bits definition for I2C_CTRL2 register ******************/ +#define I2C_CTRL2_INTEN_Pos (0U) +#define I2C_CTRL2_INTEN_Msk (0x1U << I2C_CTRL2_INTEN_Pos) /*!< 0x0000001 */ +#define I2C_CTRL2_INTEN I2C_CTRL2_INTEN_Msk /*!< Interrupt enable control of I2C controller */ + +/******************************************************************************/ +/* */ +/* MISC controller (MISC) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for MISC_SRAMINT register ******************/ +#define MISC_SRAMINT_PERR_Pos (0U) +#define MISC_SRAMINT_PERR_Msk (0x1U << MISC_SRAMINT_PERR_Pos) /*!< 0x00000001 */ +#define MISC_SRAMINT_PERR MISC_SRAMINT_PERR_Msk /*!< This bit indicates that a SRAM parity error is happened during the SRAM read process */ +//#define MISC_SRAMINT_HIAL_Pos (1U) +//#define MISC_SRAMINT_HIAL_Msk (0x1U << MISC_SRAMINT_HIAL_Pos) /*!< 0x00000002 */ +//#define MISC_SRAMINT_HIAL MISC_SRAMINT_HIAL_Msk /*!< This bit indicates that an invalid align access on AHB bus is occurred */ +#define MISC_SRAMINT_HIAC_Pos (2U) +#define MISC_SRAMINT_HIAC_Msk (0x1U << MISC_SRAMINT_HIAC_Pos) /*!< 0x00000004 */ +#define MISC_SRAMINT_HIAC MISC_SRAMINT_HIAC_Msk /*!< This bit indicates that an invalid address access on AHB bus is occurred */ +#define MISC_SRAMINT_PIAC_Pos (3U) +#define MISC_SRAMINT_PIAC_Msk (0x1U << MISC_SRAMINT_PIAC_Pos) /*!< 0x00000008 */ +#define MISC_SRAMINT_PIAC MISC_SRAMINT_PIAC_Msk /*!< This bit indicates that an invalid address access on APB bus is occurred */ +#define MISC_SRAMINT_LOCKUP_Pos (4U) +#define MISC_SRAMINT_LOCKUP_Msk (0x1U << MISC_SRAMINT_LOCKUP_Pos) /*!< 0x00000010 */ +#define MISC_SRAMINT_LOCKUP MISC_SRAMINT_LOCKUP_Msk /*!< This bit indicates the CM0 lockup has happened */ + +/************** Bits definition for MISC_SRAMINIT register ******************/ +#define MISC_SRAMINIT_PEN_Pos (0U) +#define MISC_SRAMINIT_PEN_Msk (0x1U << MISC_SRAMINIT_PEN_Pos) /*!< 0x00000001 */ +#define MISC_SRAMINIT_PEN MISC_SRAMINIT_PEN_Msk /*!< Parity check enable register */ +#define MISC_SRAMINIT_PERRIE_Pos (1U) +#define MISC_SRAMINIT_PERRIE_Msk (0x1U << MISC_SRAMINIT_PERRIE_Pos) /*!< 0x00000002 */ +#define MISC_SRAMINIT_PERRIE MISC_SRAMINIT_PERRIE_Msk /*!< SRAM parity error NMI enable register */ +#define MISC_SRAMINIT_INIT_Pos (2U) +#define MISC_SRAMINIT_INIT_Msk (0x1U << MISC_SRAMINIT_INIT_Pos) /*!< 0x00000004 */ +#define MISC_SRAMINIT_INIT MISC_SRAMINIT_INIT_Msk /*!< SRAM initialize register */ +//#define MISC_SRAMINIT_HIALIE_Pos (4U) +//#define MISC_SRAMINIT_HIALIE_Msk (0x1U << MISC_SRAMINIT_HIALIE_Pos) /*!< 0x00000010 */ +//#define MISC_SRAMINIT_HIALIE MISC_SRAMINIT_HIALIE_Msk /*!< AHB invalid aligned access NMI enable register */ +#define MISC_SRAMINIT_HIACIE_Pos (5U) +#define MISC_SRAMINIT_HIACIE_Msk (0x1U << MISC_SRAMINIT_HIACIE_Pos) /*!< 0x00000020 */ +#define MISC_SRAMINIT_HIACIE MISC_SRAMINIT_HIACIE_Msk /*!< AHB invalid address access NMI enable register */ +#define MISC_SRAMINIT_PIACIE_Pos (6U) +#define MISC_SRAMINIT_PIACIE_Msk (0x1U << MISC_SRAMINIT_PIACIE_Pos) /*!< 0x00000040 */ +#define MISC_SRAMINIT_PIACIE MISC_SRAMINIT_PIACIE_Msk /*!< APB invalid address access NMI enable register */ +#define MISC_SRAMINIT_LOCKIE_Pos (7U) +#define MISC_SRAMINIT_LOCKIE_Msk (0x1U << MISC_SRAMINIT_LOCKIE_Pos) /*!< 0x00000080 */ +#define MISC_SRAMINIT_LOCKIE MISC_SRAMINIT_LOCKIE_Msk /*!< CM0 lockup NMI enable register */ + +/************** Bits definition for MISC_PARERR register ******************/ +#define MISC_PARERR_PEADDR_Pos (0U) +#define MISC_PARERR_PEADDR_Msk (0xFFFU << MISC_PARERR_PEADDR_Pos) /*!< 0x00000FFF */ +#define MISC_PARERR_PEADDR MISC_PARERR_PEADDR_Msk /*!< Parity error address */ + +/************** Bits definition for MISC_IREN register ******************/ +#define MISC_IREN_IREN_Pos (0U) +#define MISC_IREN_IREN_Msk (0x3FU << MISC_IREN_IREN_Pos) /*!< 0x0000003F */ +#define MISC_IREN_IREN MISC_IREN_IREN_Msk /*!< IR enable control register */ +#define MISC_IREN_UART0 (0x01U) +#define MISC_IREN_UART1 (0x02U) +#define MISC_IREN_UART2 (0x04U) +#define MISC_IREN_UART3 (0x08U) +#define MISC_IREN_UART4 (0x10U) +#define MISC_IREN_UART5 (0x20U) + +/************** Bits definition for MISC_DUTYL register ******************/ +#define MISC_DUTYL_DUTYL_Pos (0U) +#define MISC_DUTYL_DUTYL_Msk (0xFFFFU << MISC_DUTYL_DUTYL_Pos) /*!< 0x0000FFFF */ +#define MISC_DUTYL_DUTYL MISC_DUTYL_DUTYL_Msk /*!< IR low pulse width control register */ + +/************** Bits definition for MISC_DUTYH register ******************/ +#define MISC_DUTYH_DUTYH_Pos (0U) +#define MISC_DUTYH_DUTYH_Msk (0xFFFFU << MISC_DUTYH_DUTYH_Pos) /*!< 0x0000FFFF */ +#define MISC_DUTYH_DUTYH MISC_DUTYH_DUTYH_Msk /*!< IR high pulse width control register */ + +/************** Bits definition for MISC_IRQLAT register ******************/ +#define MISC_IRQLAT_IRQLAT_Pos (0U) +#define MISC_IRQLAT_IRQLAT_Msk (0xFFU << MISC_IRQLAT_IRQLAT_Pos) /*!< 0x000000FF */ +#define MISC_IRQLAT_IRQLAT MISC_IRQLAT_IRQLAT_Msk /*!< This register is used to control the Cortex M0 IRQ latency */ +#define MISC_IRQLAT_LOCKRESET_Pos (8U) +#define MISC_IRQLAT_LOCKRESET_Msk (0x1U << MISC_IRQLAT_LOCKRESET_Pos) /*!< 0x00000100 */ +#define MISC_IRQLAT_LOCKRESET MISC_IRQLAT_LOCKRESET_Msk /*!< This register is used to control if the lockup will issue a system reset */ +#define MISC_IRQLAT_NOHARDFAULT_Pos (9U) +#define MISC_IRQLAT_NOHARDFAULT_Msk (0x1U << MISC_IRQLAT_NOHARDFAULT_Pos) /*!< 0x00000200 */ +#define MISC_IRQLAT_NOHARDFAULT MISC_IRQLAT_NOHARDFAULT_Msk /*!< This register is used to disable the hard fault generation to CPU */ + +/************** Bits definition for MISC_HIADDR register ******************/ +#define MISC_HIADDR_Pos (0U) +#define MISC_HIADDR_Msk (0xFFFFFFFFU << MISC_HIADDR_Pos) /*!< 0xFFFFFFFF */ +#define MISC_HIADDR MISC_HIADDR_Msk /*!< AHB invalid access address */ + +/************** Bits definition for MISC_PIADDR register ******************/ +#define MISC_PIADDR_Pos (0U) +#define MISC_PIADDR_Msk (0xFFFFFFFFU << MISC_PIADDR_Pos) /*!< 0xFFFFFFFF */ +#define MISC_PIADDR MISC_PIADDR_Msk /*!< APB invalid access address */ + +/************** Bits definition for MISC2_FLASHWC register ******************/ +#define MISC2_FLASHWC_FLASHWC_Pos (0U) +#define MISC2_FLASHWC_FLASHWC_Msk (0x3U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000003 */ +#define MISC2_FLASHWC_FLASHWC MISC2_FLASHWC_FLASHWC_Msk /*!< This register is used to control wait cycle of Flash access */ +#define MISC2_FLASHWC_FLASHWC_0Wait (0x0U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000000 */ +#define MISC2_FLASHWC_FLASHWC_1Wait (0x1U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000001 */ +#define MISC2_FLASHWC_FLASHWC_2Wait (0x2U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000002 */ +#define MISC2_FLASHWC_FLASHWC_3Wait (0x3U << MISC2_FLASHWC_FLASHWC_Pos) /*!< 0x00000003 */ +#define MISC2_FLASHWC_1USCYCLE_Pos (8U) +#define MISC2_FLASHWC_1USCYCLE_Msk (0x3FU << MISC2_FLASHWC_1USCYCLE_Pos) /*!< 0x00003F00 */ +#define MISC2_FLASHWC_1USCYCLE MISC2_FLASHWC_1USCYCLE_Msk /*!< This register is used for Flash controller to calculate 1us tick from AHB clock */ + +/************** Bits definition for MISC2_CLKSEL register ******************/ +#define MISC2_CLKSEL_CLKSEL_Pos (0U) +#define MISC2_CLKSEL_CLKSEL_Msk (0x7U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000007 */ +#define MISC2_CLKSEL_CLKSEL MISC2_CLKSEL_CLKSEL_Msk /*!< This register is used to control AHB clock source */ +#define MISC2_CLKSEL_CLKSEL_RCOH (0x0U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000000 */ +#define MISC2_CLKSEL_CLKSEL_XOH (0x1U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000001 */ +#define MISC2_CLKSEL_CLKSEL_PLLH (0x2U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000002 */ +#define MISC2_CLKSEL_CLKSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000003 */ +#define MISC2_CLKSEL_CLKSEL_PLLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000004 */ + +/************** Bits definition for MISC2_CLKDIVH register ******************/ +#define MISC2_CLKDIVH_CLKDIVH_Pos (0U) +#define MISC2_CLKDIVH_CLKDIVH_Msk (0xFFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FF */ +#define MISC2_CLKDIVH_CLKDIVH MISC2_CLKDIVH_CLKDIVH_Msk /*!< This register is used to control AHB clock divider */ +#define MISC2_CLKDIVH_CLKDIVH_DIV1 (0x0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000000 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV2 (0x1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000001 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV3 (0x2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000002 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV4 (0x3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000003 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV5 (0x4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000004 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV6 (0x5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000005 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV7 (0x6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000006 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV8 (0x7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000007 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV9 (0x8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000008 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV10 (0x9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000009 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV11 (0xAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV12 (0xBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV13 (0xCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV14 (0xDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV15 (0xEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV16 (0xFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000000F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV17 (0x10U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000010 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV18 (0x11U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000011 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV19 (0x12U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000012 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV20 (0x13U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000013 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV21 (0x14U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000014 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV22 (0x15U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000015 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV23 (0x16U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000016 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV24 (0x17U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000017 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV25 (0x18U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000018 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV26 (0x19U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000019 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV27 (0x1AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV28 (0x1BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV29 (0x1CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV30 (0x1DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV31 (0x1EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV32 (0x1FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000001F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV33 (0x20U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000020 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV34 (0x21U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000021 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV35 (0x22U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000022 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV36 (0x23U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000023 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV37 (0x24U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000024 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV38 (0x25U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000025 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV39 (0x26U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000026 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV40 (0x27U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000027 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV41 (0x28U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000028 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV42 (0x29U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000029 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV43 (0x2AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV44 (0x2BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV45 (0x2CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV46 (0x2DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV47 (0x2EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV48 (0x2FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000002F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV49 (0x30U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000030 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV50 (0x31U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000031 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV51 (0x32U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000032 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV52 (0x33U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000033 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV53 (0x34U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000034 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV54 (0x35U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000035 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV55 (0x36U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000036 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV56 (0x37U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000037 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV57 (0x38U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000038 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV58 (0x39U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000039 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV59 (0x3AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV60 (0x3BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV61 (0x3CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV62 (0x3DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV63 (0x3EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV64 (0x3FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000003F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV65 (0x40U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000040 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV66 (0x41U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000041 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV67 (0x42U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000042 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV68 (0x43U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000043 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV69 (0x44U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000044 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV70 (0x45U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000045 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV71 (0x46U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000046 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV72 (0x47U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000047 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV73 (0x48U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000048 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV74 (0x49U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000049 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV75 (0x4AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV76 (0x4BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV77 (0x4CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV78 (0x4DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV79 (0x4EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV80 (0x4FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000004F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV81 (0x50U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000050 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV82 (0x51U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000051 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV83 (0x52U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000052 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV84 (0x53U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000053 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV85 (0x54U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000054 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV86 (0x55U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000055 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV87 (0x56U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000056 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV88 (0x57U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000057 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV89 (0x58U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000058 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV90 (0x59U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000059 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV91 (0x5AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV92 (0x5BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV93 (0x5CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV94 (0x5DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV95 (0x5EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV96 (0x5FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000005F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV97 (0x60U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000060 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV98 (0x61U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000061 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV99 (0x62U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000062 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV100 (0x63U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000063 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV101 (0x64U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000064 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV102 (0x65U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000065 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV103 (0x66U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000066 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV104 (0x67U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000067 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV105 (0x68U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000068 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV106 (0x69U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000069 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV107 (0x6AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV108 (0x6BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV109 (0x6CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV110 (0x6DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV111 (0x6EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV112 (0x6FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000006F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV113 (0x70U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000070 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV114 (0x71U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000071 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV115 (0x72U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000072 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV116 (0x73U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000073 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV117 (0x74U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000074 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV118 (0x75U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000075 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV119 (0x76U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000076 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV120 (0x77U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000077 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV121 (0x78U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000078 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV122 (0x79U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000079 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV123 (0x7AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV124 (0x7BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV125 (0x7CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV126 (0x7DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV127 (0x7EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV128 (0x7FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000007F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV129 (0x80U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000080 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV130 (0x81U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000081 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV131 (0x82U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000082 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV132 (0x83U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000083 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV133 (0x84U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000084 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV134 (0x85U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000085 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV135 (0x86U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000086 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV136 (0x87U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000087 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV137 (0x88U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000088 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV138 (0x89U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000089 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV139 (0x8AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV140 (0x8BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV141 (0x8CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV142 (0x8DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV143 (0x8EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV144 (0x8FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000008F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV145 (0x90U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000090 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV146 (0x91U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000091 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV147 (0x92U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000092 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV148 (0x93U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000093 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV149 (0x94U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000094 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV150 (0x95U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000095 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV151 (0x96U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000096 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV152 (0x97U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000097 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV153 (0x98U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000098 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV154 (0x99U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x00000099 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV155 (0x9AU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009A */ +#define MISC2_CLKDIVH_CLKDIVH_DIV156 (0x9BU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009B */ +#define MISC2_CLKDIVH_CLKDIVH_DIV157 (0x9CU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009C */ +#define MISC2_CLKDIVH_CLKDIVH_DIV158 (0x9DU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009D */ +#define MISC2_CLKDIVH_CLKDIVH_DIV159 (0x9EU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009E */ +#define MISC2_CLKDIVH_CLKDIVH_DIV160 (0x9FU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x0000009F */ +#define MISC2_CLKDIVH_CLKDIVH_DIV161 (0xA0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV162 (0xA1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV163 (0xA2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV164 (0xA3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV165 (0xA4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV166 (0xA5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV167 (0xA6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV168 (0xA7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV169 (0xA8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV170 (0xA9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000A9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV171 (0xAAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV172 (0xABU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV173 (0xACU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV174 (0xADU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV175 (0xAEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV176 (0xAFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000AF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV177 (0xB0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV178 (0xB1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV179 (0xB2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV180 (0xB3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV181 (0xB4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV182 (0xB5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV183 (0xB6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV184 (0xB7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV185 (0xB8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV186 (0xB9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000B9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV187 (0xBAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV188 (0xBBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV189 (0xBCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV190 (0xBDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV191 (0xBEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV192 (0xBFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000BF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV193 (0xC0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV194 (0xC1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV195 (0xC2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV196 (0xC3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV197 (0xC4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV198 (0xC5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV199 (0xC6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV200 (0xC7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV201 (0xC8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV202 (0xC9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000C9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV203 (0xCAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV204 (0xCBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV205 (0xCCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV206 (0xCDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV207 (0xCEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV208 (0xCFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000CF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV209 (0xD0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV210 (0xD1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV211 (0xD2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV212 (0xD3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV213 (0xD4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV214 (0xD5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV215 (0xD6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV216 (0xD7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV217 (0xD8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV218 (0xD9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000D9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV219 (0xDAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV220 (0xDBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV221 (0xDCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV222 (0xDDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV223 (0xDEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV224 (0xDFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000DF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV225 (0xE0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV226 (0xE1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV227 (0xE2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV228 (0xE3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV229 (0xE4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV230 (0xE5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV231 (0xE6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV232 (0xE7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV233 (0xE8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV234 (0xE9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000E9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV235 (0xEAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV236 (0xEBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV237 (0xECU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV238 (0xEDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000ED */ +#define MISC2_CLKDIVH_CLKDIVH_DIV239 (0xEEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV240 (0xEFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000EF */ +#define MISC2_CLKDIVH_CLKDIVH_DIV241 (0xF0U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F0 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV242 (0xF1U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F1 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV243 (0xF2U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F2 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV244 (0xF3U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F3 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV245 (0xF4U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F4 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV246 (0xF5U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F5 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV247 (0xF6U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F6 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV248 (0xF7U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F7 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV249 (0xF8U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F8 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV250 (0xF9U << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000F9 */ +#define MISC2_CLKDIVH_CLKDIVH_DIV251 (0xFAU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FA */ +#define MISC2_CLKDIVH_CLKDIVH_DIV252 (0xFBU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FB */ +#define MISC2_CLKDIVH_CLKDIVH_DIV253 (0xFCU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FC */ +#define MISC2_CLKDIVH_CLKDIVH_DIV254 (0xFDU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FD */ +#define MISC2_CLKDIVH_CLKDIVH_DIV255 (0xFEU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FE */ +#define MISC2_CLKDIVH_CLKDIVH_DIV256 (0xFFU << MISC2_CLKDIVH_CLKDIVH_Pos) /*!< 0x000000FF */ + +/************** Bits definition for MISC2_CLKDIVP register ******************/ +#define MISC2_CLKDIVP_CLKDIVP_Pos (0U) +#define MISC2_CLKDIVP_CLKDIVP_Msk (0xFFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FF */ +#define MISC2_CLKDIVP_CLKDIVP MISC2_CLKDIVP_CLKDIVP_Msk /*!< This register is used to control APB clock divider */ +#define MISC2_CLKDIVP_CLKDIVP_DIV1 (0x0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000000 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV2 (0x1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000001 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV3 (0x2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000002 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV4 (0x3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000003 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV5 (0x4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000004 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV6 (0x5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000005 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV7 (0x6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000006 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV8 (0x7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000007 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV9 (0x8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000008 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV10 (0x9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000009 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV11 (0xAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV12 (0xBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV13 (0xCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV14 (0xDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV15 (0xEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV16 (0xFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000000F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV17 (0x10U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000010 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV18 (0x11U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000011 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV19 (0x12U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000012 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV20 (0x13U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000013 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV21 (0x14U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000014 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV22 (0x15U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000015 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV23 (0x16U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000016 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV24 (0x17U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000017 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV25 (0x18U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000018 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV26 (0x19U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000019 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV27 (0x1AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV28 (0x1BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV29 (0x1CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV30 (0x1DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV31 (0x1EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV32 (0x1FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000001F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV33 (0x20U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000020 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV34 (0x21U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000021 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV35 (0x22U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000022 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV36 (0x23U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000023 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV37 (0x24U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000024 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV38 (0x25U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000025 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV39 (0x26U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000026 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV40 (0x27U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000027 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV41 (0x28U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000028 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV42 (0x29U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000029 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV43 (0x2AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV44 (0x2BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV45 (0x2CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV46 (0x2DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV47 (0x2EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV48 (0x2FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000002F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV49 (0x30U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000030 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV50 (0x31U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000031 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV51 (0x32U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000032 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV52 (0x33U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000033 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV53 (0x34U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000034 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV54 (0x35U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000035 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV55 (0x36U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000036 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV56 (0x37U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000037 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV57 (0x38U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000038 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV58 (0x39U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000039 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV59 (0x3AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV60 (0x3BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV61 (0x3CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV62 (0x3DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV63 (0x3EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV64 (0x3FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000003F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV65 (0x40U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000040 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV66 (0x41U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000041 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV67 (0x42U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000042 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV68 (0x43U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000043 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV69 (0x44U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000044 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV70 (0x45U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000045 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV71 (0x46U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000046 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV72 (0x47U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000047 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV73 (0x48U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000048 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV74 (0x49U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000049 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV75 (0x4AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV76 (0x4BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV77 (0x4CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV78 (0x4DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV79 (0x4EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV80 (0x4FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000004F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV81 (0x50U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000050 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV82 (0x51U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000051 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV83 (0x52U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000052 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV84 (0x53U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000053 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV85 (0x54U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000054 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV86 (0x55U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000055 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV87 (0x56U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000056 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV88 (0x57U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000057 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV89 (0x58U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000058 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV90 (0x59U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000059 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV91 (0x5AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV92 (0x5BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV93 (0x5CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV94 (0x5DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV95 (0x5EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV96 (0x5FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000005F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV97 (0x60U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000060 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV98 (0x61U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000061 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV99 (0x62U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000062 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV100 (0x63U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000063 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV101 (0x64U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000064 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV102 (0x65U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000065 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV103 (0x66U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000066 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV104 (0x67U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000067 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV105 (0x68U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000068 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV106 (0x69U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000069 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV107 (0x6AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV108 (0x6BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV109 (0x6CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV110 (0x6DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV111 (0x6EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV112 (0x6FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000006F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV113 (0x70U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000070 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV114 (0x71U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000071 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV115 (0x72U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000072 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV116 (0x73U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000073 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV117 (0x74U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000074 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV118 (0x75U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000075 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV119 (0x76U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000076 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV120 (0x77U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000077 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV121 (0x78U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000078 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV122 (0x79U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000079 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV123 (0x7AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV124 (0x7BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV125 (0x7CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV126 (0x7DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV127 (0x7EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV128 (0x7FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000007F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV129 (0x80U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000080 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV130 (0x81U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000081 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV131 (0x82U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000082 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV132 (0x83U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000083 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV133 (0x84U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000084 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV134 (0x85U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000085 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV135 (0x86U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000086 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV136 (0x87U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000087 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV137 (0x88U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000088 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV138 (0x89U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000089 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV139 (0x8AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV140 (0x8BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV141 (0x8CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV142 (0x8DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV143 (0x8EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV144 (0x8FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000008F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV145 (0x90U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000090 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV146 (0x91U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000091 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV147 (0x92U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000092 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV148 (0x93U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000093 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV149 (0x94U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000094 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV150 (0x95U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000095 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV151 (0x96U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000096 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV152 (0x97U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000097 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV153 (0x98U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000098 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV154 (0x99U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x00000099 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV155 (0x9AU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009A */ +#define MISC2_CLKDIVP_CLKDIVP_DIV156 (0x9BU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009B */ +#define MISC2_CLKDIVP_CLKDIVP_DIV157 (0x9CU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009C */ +#define MISC2_CLKDIVP_CLKDIVP_DIV158 (0x9DU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009D */ +#define MISC2_CLKDIVP_CLKDIVP_DIV159 (0x9EU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009E */ +#define MISC2_CLKDIVP_CLKDIVP_DIV160 (0x9FU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x0000009F */ +#define MISC2_CLKDIVP_CLKDIVP_DIV161 (0xA0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV162 (0xA1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV163 (0xA2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV164 (0xA3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV165 (0xA4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV166 (0xA5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV167 (0xA6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV168 (0xA7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV169 (0xA8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV170 (0xA9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000A9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV171 (0xAAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV172 (0xABU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV173 (0xACU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV174 (0xADU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV175 (0xAEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV176 (0xAFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000AF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV177 (0xB0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV178 (0xB1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV179 (0xB2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV180 (0xB3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV181 (0xB4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV182 (0xB5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV183 (0xB6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV184 (0xB7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV185 (0xB8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV186 (0xB9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000B9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV187 (0xBAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV188 (0xBBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV189 (0xBCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV190 (0xBDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV191 (0xBEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV192 (0xBFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000BF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV193 (0xC0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV194 (0xC1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV195 (0xC2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV196 (0xC3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV197 (0xC4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV198 (0xC5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV199 (0xC6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV200 (0xC7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV201 (0xC8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV202 (0xC9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000C9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV203 (0xCAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV204 (0xCBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV205 (0xCCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV206 (0xCDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV207 (0xCEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV208 (0xCFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000CF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV209 (0xD0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV210 (0xD1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV211 (0xD2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV212 (0xD3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV213 (0xD4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV214 (0xD5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV215 (0xD6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV216 (0xD7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV217 (0xD8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV218 (0xD9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000D9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV219 (0xDAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV220 (0xDBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV221 (0xDCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV222 (0xDDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV223 (0xDEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV224 (0xDFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000DF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV225 (0xE0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV226 (0xE1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV227 (0xE2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV228 (0xE3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV229 (0xE4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV230 (0xE5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV231 (0xE6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV232 (0xE7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV233 (0xE8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV234 (0xE9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000E9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV235 (0xEAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV236 (0xEBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV237 (0xECU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV238 (0xEDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000ED */ +#define MISC2_CLKDIVP_CLKDIVP_DIV239 (0xEEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV240 (0xEFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000EF */ +#define MISC2_CLKDIVP_CLKDIVP_DIV241 (0xF0U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F0 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV242 (0xF1U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F1 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV243 (0xF2U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F2 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV244 (0xF3U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F3 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV245 (0xF4U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F4 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV246 (0xF5U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F5 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV247 (0xF6U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F6 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV248 (0xF7U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F7 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV249 (0xF8U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F8 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV250 (0xF9U << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000F9 */ +#define MISC2_CLKDIVP_CLKDIVP_DIV251 (0xFAU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FA */ +#define MISC2_CLKDIVP_CLKDIVP_DIV252 (0xFBU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FB */ +#define MISC2_CLKDIVP_CLKDIVP_DIV253 (0xFCU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FC */ +#define MISC2_CLKDIVP_CLKDIVP_DIV254 (0xFDU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FD */ +#define MISC2_CLKDIVP_CLKDIVP_DIV255 (0xFEU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FE */ +#define MISC2_CLKDIVP_CLKDIVP_DIV256 (0xFFU << MISC2_CLKDIVP_CLKDIVP_Pos) /*!< 0x000000FF */ + +/************** Bits definition for MISC2_HCLKEN register ******************/ +//#define MISC2_HCLKEN_HCLKEN_Pos (0U) +//#define MISC2_HCLKEN_HCLKEN_Msk (0x1FFU << MISC2_HCLKEN_HCLKEN_Pos) /*!< 0x000001FF */ +//#define MISC2_HCLKEN_HCLKEN MISC2_HCLKEN_HCLKEN_Msk /*!< This register is used to control clock enable of each AHB module */ +//#define MISC2_HCLKEN_ARB_Pos (1U) +//#define MISC2_HCLKEN_ARB_Msk (0x1U << MISC2_HCLKEN_ARB_Pos) /*!< 0x00000002 */ +//#define MISC2_HCLKEN_ARB MISC2_HCLKEN_ARB_Msk /*!< Arbiter & Bus Matrix */ +//#define MISC2_HCLKEN_FLASH_Pos (2U) +//#define MISC2_HCLKEN_FLASH_Msk (0x1U << MISC2_HCLKEN_FLASH_Pos) /*!< 0x00000004 */ +//#define MISC2_HCLKEN_FLASH MISC2_HCLKEN_FLASH_Msk /*!< Flash Controller */ +//#define MISC2_HCLKEN_SRAM_Pos (3U) +//#define MISC2_HCLKEN_SRAM_Msk (0x1U << MISC2_HCLKEN_SRAM_Pos) /*!< 0x00000008 */ +//#define MISC2_HCLKEN_SRAM MISC2_HCLKEN_SRAM_Msk /*!< SRAM Controller */ +#define MISC2_HCLKEN_DMA_Pos (4U) +#define MISC2_HCLKEN_DMA_Msk (0x1U << MISC2_HCLKEN_DMA_Pos) /*!< 0x00000010 */ +#define MISC2_HCLKEN_DMA MISC2_HCLKEN_DMA_Msk /*!< DMA Controller */ +#define MISC2_HCLKEN_GPIO_Pos (5U) +#define MISC2_HCLKEN_GPIO_Msk (0x1U << MISC2_HCLKEN_GPIO_Pos) /*!< 0x00000020 */ +#define MISC2_HCLKEN_GPIO MISC2_HCLKEN_GPIO_Msk /*!< GPIO Controller */ +#define MISC2_HCLKEN_LCD_Pos (6U) +#define MISC2_HCLKEN_LCD_Msk (0x1U << MISC2_HCLKEN_LCD_Pos) /*!< 0x00000040 */ +#define MISC2_HCLKEN_LCD MISC2_HCLKEN_LCD_Msk /*!< LCD Controller */ +#define MISC2_HCLKEN_CRYPT_Pos (8U) +#define MISC2_HCLKEN_CRYPT_Msk (0x1U << MISC2_HCLKEN_CRYPT_Pos) /*!< 0x00000100 */ +#define MISC2_HCLKEN_CRYPT MISC2_HCLKEN_CRYPT_Msk /*!< CRYPT Controller */ + +/************** Bits definition for MISC2_PCLKEN register ******************/ +//#define MISC2_PCLKEN_PCLKEN_Pos (0U) +//#define MISC2_PCLKEN_PCLKEN_Msk (0x002FFFFFU << MISC2_PCLKEN_PCLKEN_Pos) /*!< 0x002FFFFF */ +//#define MISC2_PCLKEN_PCLKEN MISC2_PCLKEN_PCLKEN_Msk /*!< This register is used to control clock enable of each APB module */ +//#define MISC2_PCLKEN_AHB2APB_Pos (0U) +//#define MISC2_PCLKEN_AHB2APB_Msk (0x1U << MISC2_PCLKEN_AHB2APB_Pos) /*!< 0x00000001 */ +//#define MISC2_PCLKEN_AHB2APB MISC2_PCLKEN_AHB2APB_Msk /*!< AHB2APB Bridge */ +#define MISC2_PCLKEN_DMA_Pos (1U) +#define MISC2_PCLKEN_DMA_Msk (0x1U << MISC2_PCLKEN_DMA_Pos) /*!< 0x00000002 */ +#define MISC2_PCLKEN_DMA MISC2_PCLKEN_DMA_Msk /*!< DMA Controller */ +#define MISC2_PCLKEN_I2C_Pos (2U) +#define MISC2_PCLKEN_I2C_Msk (0x1U << MISC2_PCLKEN_I2C_Pos) /*!< 0x00000004 */ +#define MISC2_PCLKEN_I2C MISC2_PCLKEN_I2C_Msk /*!< I2C */ +#define MISC2_PCLKEN_SPI1_Pos (3U) +#define MISC2_PCLKEN_SPI1_Msk (0x1U << MISC2_PCLKEN_SPI1_Pos) /*!< 0x00000008 */ +#define MISC2_PCLKEN_SPI1 MISC2_PCLKEN_SPI1_Msk /*!< SPI1 */ +#define MISC2_PCLKEN_UART0_Pos (4U) +#define MISC2_PCLKEN_UART0_Msk (0x1U << MISC2_PCLKEN_UART0_Pos) /*!< 0x00000010 */ +#define MISC2_PCLKEN_UART0 MISC2_PCLKEN_UART0_Msk /*!< UART0 */ +#define MISC2_PCLKEN_UART1_Pos (5U) +#define MISC2_PCLKEN_UART1_Msk (0x1U << MISC2_PCLKEN_UART1_Pos) /*!< 0x00000020 */ +#define MISC2_PCLKEN_UART1 MISC2_PCLKEN_UART1_Msk /*!< UART1 */ +#define MISC2_PCLKEN_UART2_Pos (6U) +#define MISC2_PCLKEN_UART2_Msk (0x1U << MISC2_PCLKEN_UART2_Pos) /*!< 0x00000040 */ +#define MISC2_PCLKEN_UART2 MISC2_PCLKEN_UART2_Msk /*!< UART2 */ +#define MISC2_PCLKEN_UART3_Pos (7U) +#define MISC2_PCLKEN_UART3_Msk (0x1U << MISC2_PCLKEN_UART3_Pos) /*!< 0x00000080 */ +#define MISC2_PCLKEN_UART3 MISC2_PCLKEN_UART3_Msk /*!< UART3 */ +#define MISC2_PCLKEN_UART4_Pos (8U) +#define MISC2_PCLKEN_UART4_Msk (0x1U << MISC2_PCLKEN_UART4_Pos) /*!< 0x00000100 */ +#define MISC2_PCLKEN_UART4 MISC2_PCLKEN_UART4_Msk /*!< UART4 */ +#define MISC2_PCLKEN_UART5_Pos (9U) +#define MISC2_PCLKEN_UART5_Msk (0x1U << MISC2_PCLKEN_UART5_Pos) /*!< 0x00000200 */ +#define MISC2_PCLKEN_UART5 MISC2_PCLKEN_UART5_Msk /*!< UART5 */ +#define MISC2_PCLKEN_ISO78160_Pos (10U) +#define MISC2_PCLKEN_ISO78160_Msk (0x1U << MISC2_PCLKEN_ISO78160_Pos) /*!< 0x00000400 */ +#define MISC2_PCLKEN_ISO78160 MISC2_PCLKEN_ISO78160_Msk /*!< ISO78160 */ +#define MISC2_PCLKEN_ISO78161_Pos (11U) +#define MISC2_PCLKEN_ISO78161_Msk (0x1U << MISC2_PCLKEN_ISO78161_Pos) /*!< 0x00000800 */ +#define MISC2_PCLKEN_ISO78161 MISC2_PCLKEN_ISO78161_Msk /*!< ISO78161 */ +#define MISC2_PCLKEN_TIMER_Pos (12U) +#define MISC2_PCLKEN_TIMER_Msk (0x1U << MISC2_PCLKEN_TIMER_Pos) /*!< 0x00001000 */ +#define MISC2_PCLKEN_TIMER MISC2_PCLKEN_TIMER_Msk /*!< Timer */ +#define MISC2_PCLKEN_MISC_Pos (13U) +#define MISC2_PCLKEN_MISC_Msk (0x1U << MISC2_PCLKEN_MISC_Pos) /*!< 0x00002000 */ +#define MISC2_PCLKEN_MISC MISC2_PCLKEN_MISC_Msk /*!< MISC */ +#define MISC2_PCLKEN_MISC2_Pos (14U) +#define MISC2_PCLKEN_MISC2_Msk (0x1U << MISC2_PCLKEN_MISC2_Pos) /*!< 0x00004000 */ +#define MISC2_PCLKEN_MISC2 MISC2_PCLKEN_MISC2_Msk /*!< LCD & MISC2 */ +#define MISC2_PCLKEN_PMU_Pos (15U) +#define MISC2_PCLKEN_PMU_Msk (0x1U << MISC2_PCLKEN_PMU_Pos) /*!< 0x00008000 */ +#define MISC2_PCLKEN_PMU MISC2_PCLKEN_PMU_Msk /*!< PMU */ +#define MISC2_PCLKEN_RTC_Pos (16U) +#define MISC2_PCLKEN_RTC_Msk (0x1U << MISC2_PCLKEN_RTC_Pos) /*!< 0x00010000 */ +#define MISC2_PCLKEN_RTC MISC2_PCLKEN_RTC_Msk /*!< RTC */ +#define MISC2_PCLKEN_ANA_Pos (17U) +#define MISC2_PCLKEN_ANA_Msk (0x1U << MISC2_PCLKEN_ANA_Pos) /*!< 0x00020000 */ +#define MISC2_PCLKEN_ANA MISC2_PCLKEN_ANA_Msk /*!< ANA */ +#define MISC2_PCLKEN_U32K0_Pos (18U) +#define MISC2_PCLKEN_U32K0_Msk (0x1U << MISC2_PCLKEN_U32K0_Pos) /*!< 0x00040000 */ +#define MISC2_PCLKEN_U32K0 MISC2_PCLKEN_U32K0_Msk /*!< U32K 0 */ +#define MISC2_PCLKEN_U32K1_Pos (19U) +#define MISC2_PCLKEN_U32K1_Msk (0x1U << MISC2_PCLKEN_U32K1_Pos) /*!< 0x00080000 */ +#define MISC2_PCLKEN_U32K1 MISC2_PCLKEN_U32K1_Msk /*!< U32K 1 */ +#define MISC2_PCLKEN_SPI2_Pos (21U) +#define MISC2_PCLKEN_SPI2_Msk (0x1U << MISC2_PCLKEN_SPI2_Pos) /*!< 0x00200000 */ +#define MISC2_PCLKEN_SPI2 MISC2_PCLKEN_SPI2_Msk /*!< SPI2 */ + +/******************************************************************************/ +/* */ +/* CRYPT controller (CRYPT) */ +/* */ +/******************************************************************************/ + +/************** Bits definition for CRYPT_CTRL register ******************/ +#define CRYPT_CTRL_ACT_Pos (0U) +#define CRYPT_CTRL_ACT_Msk (0x1U << CRYPT_CTRL_ACT_Pos) /*!< 0x00000001 */ +#define CRYPT_CTRL_ACT CRYPT_CTRL_ACT_Msk /*!< Write 1 to this bit will start an operation specified in the MODE register */ +#define CRYPT_CTRL_MODE_Pos (4U) +#define CRYPT_CTRL_MODE_Msk (0x7U << CRYPT_CTRL_MODE_Pos) /*!< 0x00000070 */ +#define CRYPT_CTRL_MODE CRYPT_CTRL_MODE_Msk /*!< This register controls the operation mode of crypt engine */ +#define CRYPT_CTRL_MODE_MULTIPLY (0x0U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_ADD (0x1U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_SUB (0x2U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_MODE_RSHIFT1 (0x3U << CRYPT_CTRL_MODE_Pos) +#define CRYPT_CTRL_LENGTH_Pos (8U) +#define CRYPT_CTRL_LENGTH_Msk (0xFU << CRYPT_CTRL_LENGTH_Pos) /*!< 0x00000F00 */ +#define CRYPT_CTRL_LENGTH CRYPT_CTRL_LENGTH_Msk /*!< This bit is used to control the VLI length of current operation */ +#define CRYPT_CTRL_LENGTH_32 (0x0U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_64 (0x1U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_96 (0x2U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_128 (0x3U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_160 (0x4U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_192 (0x5U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_224 (0x6U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_256 (0x7U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_288 (0x8U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_320 (0x9U << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_352 (0xAU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_384 (0xBU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_416 (0xCU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_448 (0xDU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_480 (0xEU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_LENGTH_512 (0xFU << CRYPT_CTRL_LENGTH_Pos) +#define CRYPT_CTRL_NOSTOP_Pos (15U) +#define CRYPT_CTRL_NOSTOP_Msk (0x1U << CRYPT_CTRL_NOSTOP_Pos) /*!< 0x00008000 */ +#define CRYPT_CTRL_NOSTOP CRYPT_CTRL_NOSTOP_Msk /*!< This register is used to control if the CPU will be stop by CRYPT engine when the CRYPT engine is busy and CPU read or write CRYPT engine register */ + +/************** Bits definition for CRYPT_PTRA register ******************/ +#define CRYPT_PTRA_PTRA_Pos (0U) +#define CRYPT_PTRA_PTRA_Msk (0x7FFFU << CRYPT_PTRA_PTRA_Pos) /*!< 0x00007FFF */ +#define CRYPT_PTRA_PTRA CRYPT_PTRA_PTRA_Msk /*!< This is the PTRA register of CRYPT controller */ + +/************** Bits definition for CRYPT_PTRB register ******************/ +#define CRYPT_PTRB_PTRB_Pos (0U) +#define CRYPT_PTRB_PTRB_Msk (0x7FFFU << CRYPT_PTRB_PTRB_Pos) /*!< 0x00007FFF */ +#define CRYPT_PTRB_PTRB CRYPT_PTRB_PTRB_Msk /*!< This is the PTRB register of CRYPT controller */ + +/************** Bits definition for CRYPT_PTRO register ******************/ +#define CRYPT_PTRO_PTRO_Pos (0U) +#define CRYPT_PTRO_PTRO_Msk (0x7FFFU << CRYPT_PTRO_PTRO_Pos) /*!< 0x00007FFF */ +#define CRYPT_PTRO_PTRO CRYPT_PTRO_PTRO_Msk /*!< This is the PTRO register of CRYPT controller */ + +/************* Bits definition for CRYPT_CARRY register ******************/ +#define CRYPT_CARRY_CARRY_Pos (0U) +#define CRYPT_CARRY_CARRY_Msk (0x1U << CRYPT_CARRY_CARRY_Pos) /*!< 0x00000001 */ +#define CRYPT_CARRY_CARRY CRYPT_CARRY_CARRY_Msk /*!< This bit represent the carry bit after add operation is done */ + + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Power Management Unit (PMU) */ +/* */ +/******************************************************************************/ +#define PMU_DSLEEPEN (volatile unsigned *)(PMU_BASE + 0x0000) +#define PMU_DSLEEPPASS (volatile unsigned *)(PMU_BASE + 0x0004) +#define PMU_CONTROL (volatile unsigned *)(PMU_BASE + 0x0008) +#define PMU_STS (volatile unsigned *)(PMU_BASE + 0x000C) +#define PMU_IOAOEN (volatile unsigned *)(PMU_BASE + 0x0010) +#define PMU_IOAIE (volatile unsigned *)(PMU_BASE + 0x0014) +#define PMU_IOADAT (volatile unsigned *)(PMU_BASE + 0x0018) +#define PMU_IOAATT (volatile unsigned *)(PMU_BASE + 0x001C) +#define PMU_IOAWKUEN (volatile unsigned *)(PMU_BASE + 0x0020) +#define PMU_IOASTS (volatile unsigned *)(PMU_BASE + 0x0024) +#define PMU_IOAINTSTS (volatile unsigned *)(PMU_BASE + 0x0028) +#define PMU_IOASEL (volatile unsigned *)(PMU_BASE + 0x0038) +#define VERSIONID (volatile unsigned *)(PMU_BASE + 0x003C) +#define PMU_WDTPASS (volatile unsigned *)(PMU_BASE + 0x0040) +#define PMU_WDTEN (volatile unsigned *)(PMU_BASE + 0x0044) +#define PMU_WDTCLR (volatile unsigned *)(PMU_BASE + 0x0048) +//#define PMU_WDTSTS (volatile unsigned *)(PMU_BASE + 0x004C) +#define PMU_IOANODEG (volatile unsigned *)(PMU_BASE + 0x0050) + +#define PMU_RAM0 (volatile unsigned *)(RETRAM_BASE + 0x0000) +#define PMU_RAM1 (volatile unsigned *)(RETRAM_BASE + 0x0004) +#define PMU_RAM2 (volatile unsigned *)(RETRAM_BASE + 0x0008) +#define PMU_RAM3 (volatile unsigned *)(RETRAM_BASE + 0x000C) +#define PMU_RAM4 (volatile unsigned *)(RETRAM_BASE + 0x0010) +#define PMU_RAM5 (volatile unsigned *)(RETRAM_BASE + 0x0014) +#define PMU_RAM6 (volatile unsigned *)(RETRAM_BASE + 0x0018) +#define PMU_RAM7 (volatile unsigned *)(RETRAM_BASE + 0x001C) +#define PMU_RAM8 (volatile unsigned *)(RETRAM_BASE + 0x0020) +#define PMU_RAM9 (volatile unsigned *)(RETRAM_BASE + 0x0024) +#define PMU_RAM10 (volatile unsigned *)(RETRAM_BASE + 0x0028) +#define PMU_RAM11 (volatile unsigned *)(RETRAM_BASE + 0x002C) +#define PMU_RAM12 (volatile unsigned *)(RETRAM_BASE + 0x0030) +#define PMU_RAM13 (volatile unsigned *)(RETRAM_BASE + 0x0034) +#define PMU_RAM14 (volatile unsigned *)(RETRAM_BASE + 0x0038) +#define PMU_RAM15 (volatile unsigned *)(RETRAM_BASE + 0x003C) +#define PMU_RAM16 (volatile unsigned *)(RETRAM_BASE + 0x0040) +#define PMU_RAM17 (volatile unsigned *)(RETRAM_BASE + 0x0044) +#define PMU_RAM18 (volatile unsigned *)(RETRAM_BASE + 0x0048) +#define PMU_RAM19 (volatile unsigned *)(RETRAM_BASE + 0x004C) +#define PMU_RAM20 (volatile unsigned *)(RETRAM_BASE + 0x0050) +#define PMU_RAM21 (volatile unsigned *)(RETRAM_BASE + 0x0054) +#define PMU_RAM22 (volatile unsigned *)(RETRAM_BASE + 0x0058) +#define PMU_RAM23 (volatile unsigned *)(RETRAM_BASE + 0x005C) +#define PMU_RAM24 (volatile unsigned *)(RETRAM_BASE + 0x0060) +#define PMU_RAM25 (volatile unsigned *)(RETRAM_BASE + 0x0064) +#define PMU_RAM26 (volatile unsigned *)(RETRAM_BASE + 0x0068) +#define PMU_RAM27 (volatile unsigned *)(RETRAM_BASE + 0x006C) +#define PMU_RAM28 (volatile unsigned *)(RETRAM_BASE + 0x0070) +#define PMU_RAM29 (volatile unsigned *)(RETRAM_BASE + 0x0074) +#define PMU_RAM30 (volatile unsigned *)(RETRAM_BASE + 0x0078) +#define PMU_RAM31 (volatile unsigned *)(RETRAM_BASE + 0x007C) +#define PMU_RAM32 (volatile unsigned *)(RETRAM_BASE + 0x0080) +#define PMU_RAM33 (volatile unsigned *)(RETRAM_BASE + 0x0084) +#define PMU_RAM34 (volatile unsigned *)(RETRAM_BASE + 0x0088) +#define PMU_RAM35 (volatile unsigned *)(RETRAM_BASE + 0x008C) +#define PMU_RAM36 (volatile unsigned *)(RETRAM_BASE + 0x0090) +#define PMU_RAM37 (volatile unsigned *)(RETRAM_BASE + 0x0094) +#define PMU_RAM38 (volatile unsigned *)(RETRAM_BASE + 0x0098) +#define PMU_RAM39 (volatile unsigned *)(RETRAM_BASE + 0x009C) +#define PMU_RAM40 (volatile unsigned *)(RETRAM_BASE + 0x00A0) +#define PMU_RAM41 (volatile unsigned *)(RETRAM_BASE + 0x00A4) +#define PMU_RAM42 (volatile unsigned *)(RETRAM_BASE + 0x00A8) +#define PMU_RAM43 (volatile unsigned *)(RETRAM_BASE + 0x00AC) +#define PMU_RAM44 (volatile unsigned *)(RETRAM_BASE + 0x00B0) +#define PMU_RAM45 (volatile unsigned *)(RETRAM_BASE + 0x00B4) +#define PMU_RAM46 (volatile unsigned *)(RETRAM_BASE + 0x00B8) +#define PMU_RAM47 (volatile unsigned *)(RETRAM_BASE + 0x00BC) +#define PMU_RAM48 (volatile unsigned *)(RETRAM_BASE + 0x00C0) +#define PMU_RAM49 (volatile unsigned *)(RETRAM_BASE + 0x00C4) +#define PMU_RAM50 (volatile unsigned *)(RETRAM_BASE + 0x00C8) +#define PMU_RAM51 (volatile unsigned *)(RETRAM_BASE + 0x00CC) +#define PMU_RAM52 (volatile unsigned *)(RETRAM_BASE + 0x00D0) +#define PMU_RAM53 (volatile unsigned *)(RETRAM_BASE + 0x00D4) +#define PMU_RAM54 (volatile unsigned *)(RETRAM_BASE + 0x00D8) +#define PMU_RAM55 (volatile unsigned *)(RETRAM_BASE + 0x00DC) +#define PMU_RAM56 (volatile unsigned *)(RETRAM_BASE + 0x00E0) +#define PMU_RAM57 (volatile unsigned *)(RETRAM_BASE + 0x00E4) +#define PMU_RAM58 (volatile unsigned *)(RETRAM_BASE + 0x00E8) +#define PMU_RAM59 (volatile unsigned *)(RETRAM_BASE + 0x00EC) +#define PMU_RAM60 (volatile unsigned *)(RETRAM_BASE + 0x00F0) +#define PMU_RAM61 (volatile unsigned *)(RETRAM_BASE + 0x00F4) +#define PMU_RAM62 (volatile unsigned *)(RETRAM_BASE + 0x00F8) +#define PMU_RAM63 (volatile unsigned *)(RETRAM_BASE + 0x00FC) + +/******************************************************************************/ +/* */ +/* Analog Controller (ANA) */ +/* */ +/******************************************************************************/ +#define ANA_REG0 (volatile unsigned *)(ANA_BASE + 0x0000) +#define ANA_REG1 (volatile unsigned *)(ANA_BASE + 0x0004) +#define ANA_REG2 (volatile unsigned *)(ANA_BASE + 0x0008) +#define ANA_REG3 (volatile unsigned *)(ANA_BASE + 0x000C) +#define ANA_REG4 (volatile unsigned *)(ANA_BASE + 0x0010) +#define ANA_REG5 (volatile unsigned *)(ANA_BASE + 0x0014) +#define ANA_REG6 (volatile unsigned *)(ANA_BASE + 0x0018) +#define ANA_REG7 (volatile unsigned *)(ANA_BASE + 0x001C) +#define ANA_REG8 (volatile unsigned *)(ANA_BASE + 0x0020) +#define ANA_REG9 (volatile unsigned *)(ANA_BASE + 0x0024) +#define ANA_REGA (volatile unsigned *)(ANA_BASE + 0x0028) +#define ANA_REGB (volatile unsigned *)(ANA_BASE + 0x002C) +#define ANA_REGC (volatile unsigned *)(ANA_BASE + 0x0030) +#define ANA_REGD (volatile unsigned *)(ANA_BASE + 0x0034) +#define ANA_REGE (volatile unsigned *)(ANA_BASE + 0x0038) +#define ANA_REGF (volatile unsigned *)(ANA_BASE + 0x003C) +//#define ANA_REG10 (volatile unsigned *)(ANA_BASE + 0x0040) +//#define ANA_REG11 (volatile unsigned *)(ANA_BASE + 0x0044) +//#define ANA_REG12 (volatile unsigned *)(ANA_BASE + 0x0048) +#define ANA_CTRL (volatile unsigned *)(ANA_BASE + 0x0050) +#define ANA_CMPOUT (volatile unsigned *)(ANA_BASE + 0x0054) +//#define ANA_VERSION (volatile unsigned *)(ANA_BASE + 0x0058) +//#define ANA_ADCSTATE (volatile unsigned *)(ANA_BASE + 0x005C) +#define ANA_INTSTS (volatile unsigned *)(ANA_BASE + 0x0060) +#define ANA_INTEN (volatile unsigned *)(ANA_BASE + 0x0064) +#define ANA_ADCCTRL (volatile unsigned *)(ANA_BASE + 0x0068) +#define ANA_ADCDATA0 (volatile unsigned *)(ANA_BASE + 0x0070) +#define ANA_ADCDATA1 (volatile unsigned *)(ANA_BASE + 0x0074) +#define ANA_ADCDATA2 (volatile unsigned *)(ANA_BASE + 0x0078) +#define ANA_ADCDATA3 (volatile unsigned *)(ANA_BASE + 0x007C) +#define ANA_ADCDATA4 (volatile unsigned *)(ANA_BASE + 0x0080) +#define ANA_ADCDATA5 (volatile unsigned *)(ANA_BASE + 0x0084) +#define ANA_ADCDATA6 (volatile unsigned *)(ANA_BASE + 0x0088) +#define ANA_ADCDATA7 (volatile unsigned *)(ANA_BASE + 0x008C) +#define ANA_ADCDATA8 (volatile unsigned *)(ANA_BASE + 0x0090) +#define ANA_ADCDATA9 (volatile unsigned *)(ANA_BASE + 0x0094) +#define ANA_ADCDATAA (volatile unsigned *)(ANA_BASE + 0x0098) +#define ANA_ADCDATAB (volatile unsigned *)(ANA_BASE + 0x009C) +//#define ANA_ADCDATAC (volatile unsigned *)(ANA_BASE + 0x00A0) +//#define ANA_ADCDATAD (volatile unsigned *)(ANA_BASE + 0x00A4) +//#define ANA_ADCDATAE (volatile unsigned *)(ANA_BASE + 0x00A8) +//#define ANA_ADCDATAF (volatile unsigned *)(ANA_BASE + 0x00AC) +#define ANA_CMPCNT1 (volatile unsigned *)(ANA_BASE + 0x00B0) +#define ANA_CMPCNT2 (volatile unsigned *)(ANA_BASE + 0x00B4) +#define ANA_MISC (volatile unsigned *)(ANA_BASE + 0x00B8) + +/******************************************************************************/ +/* */ +/* RTC Controller (RTC) */ +/* */ +/******************************************************************************/ +#define RTC_SEC (volatile unsigned *)(RTC_BASE + 0x0000) +#define RTC_MIN (volatile unsigned *)(RTC_BASE + 0x0004) +#define RTC_HOUR (volatile unsigned *)(RTC_BASE + 0x0008) +#define RTC_DAY (volatile unsigned *)(RTC_BASE + 0x000C) +#define RTC_WEEK (volatile unsigned *)(RTC_BASE + 0x0010) +#define RTC_MON (volatile unsigned *)(RTC_BASE + 0x0014) +#define RTC_YEAR (volatile unsigned *)(RTC_BASE + 0x0018) +#define RTC_WKUSEC (volatile unsigned *)(RTC_BASE + 0x0020) +#define RTC_WKUMIN (volatile unsigned *)(RTC_BASE + 0x0024) +#define RTC_WKUHOUR (volatile unsigned *)(RTC_BASE + 0x0028) +#define RTC_WKUCNT (volatile unsigned *)(RTC_BASE + 0x002C) +#define RTC_CAL (volatile unsigned *)(RTC_BASE + 0x0030) +#define RTC_DIV (volatile unsigned *)(RTC_BASE + 0x0034) +#define RTC_CTL (volatile unsigned *)(RTC_BASE + 0x0038) +//#define RTC_ITV (volatile unsigned *)(RTC_BASE + 0x003C) +//#define RTC_SITV (volatile unsigned *)(RTC_BASE + 0x0040) +#define RTC_PWD (volatile unsigned *)(RTC_BASE + 0x0044) +#define RTC_CE (volatile unsigned *)(RTC_BASE + 0x0048) +#define RTC_LOAD (volatile unsigned *)(RTC_BASE + 0x004C) +#define RTC_INTSTS (volatile unsigned *)(RTC_BASE + 0x0050) +#define RTC_INTEN (volatile unsigned *)(RTC_BASE + 0x0054) +#define RTC_PSCA (volatile unsigned *)(RTC_BASE + 0x0058) +#define RTC_ACCTRL (volatile unsigned *)(RTC_BASE + 0x0080) +#define RTC_ACTI (volatile unsigned *)(RTC_BASE + 0x0084) +#define RTC_ACF200 (volatile unsigned *)(RTC_BASE + 0x0088) +#define RTC_ACADCW (volatile unsigned *)(RTC_BASE + 0x008C) +#define RTC_ACP0 (volatile unsigned *)(RTC_BASE + 0x0090) +#define RTC_ACP1 (volatile unsigned *)(RTC_BASE + 0x0094) +#define RTC_ACP2 (volatile unsigned *)(RTC_BASE + 0x0098) +#define RTC_ACP3 (volatile unsigned *)(RTC_BASE + 0x009C) +#define RTC_ACP4 (volatile unsigned *)(RTC_BASE + 0x00A0) +#define RTC_ACP5 (volatile unsigned *)(RTC_BASE + 0x00A4) +#define RTC_ACP6 (volatile unsigned *)(RTC_BASE + 0x00A8) +#define RTC_ACP7 (volatile unsigned *)(RTC_BASE + 0x00AC) +#define RTC_ACK1 (volatile unsigned *)(RTC_BASE + 0x00B0) +#define RTC_ACK2 (volatile unsigned *)(RTC_BASE + 0x00B4) +#define RTC_ACK3 (volatile unsigned *)(RTC_BASE + 0x00B8) +#define RTC_ACK4 (volatile unsigned *)(RTC_BASE + 0x00BC) +#define RTC_ACK5 (volatile unsigned *)(RTC_BASE + 0x00C0) +#define RTC_ACTEMP (volatile unsigned *)(RTC_BASE + 0x00C4) +#define RTC_ACPPM (volatile unsigned *)(RTC_BASE + 0x00C8) +#define RTC_ACADCR (volatile unsigned *)(RTC_BASE + 0x00CC) +#define RTC_ACOP0 (volatile unsigned *)(RTC_BASE + 0x0400) +#define RTC_ACOP1 (volatile unsigned *)(RTC_BASE + 0x0404) +#define RTC_ACOP2 (volatile unsigned *)(RTC_BASE + 0x0408) +#define RTC_ACOP3 (volatile unsigned *)(RTC_BASE + 0x040C) +#define RTC_ACOP4 (volatile unsigned *)(RTC_BASE + 0x0410) +#define RTC_ACOP5 (volatile unsigned *)(RTC_BASE + 0x0414) +#define RTC_ACOP6 (volatile unsigned *)(RTC_BASE + 0x0418) +#define RTC_ACOP7 (volatile unsigned *)(RTC_BASE + 0x041C) +#define RTC_ACOP8 (volatile unsigned *)(RTC_BASE + 0x0420) +#define RTC_ACOP9 (volatile unsigned *)(RTC_BASE + 0x0424) +#define RTC_ACOP10 (volatile unsigned *)(RTC_BASE + 0x0428) +#define RTC_ACOP11 (volatile unsigned *)(RTC_BASE + 0x042C) +#define RTC_ACOP12 (volatile unsigned *)(RTC_BASE + 0x0430) +#define RTC_ACOP13 (volatile unsigned *)(RTC_BASE + 0x0434) +#define RTC_ACOP14 (volatile unsigned *)(RTC_BASE + 0x0438) +#define RTC_ACOP15 (volatile unsigned *)(RTC_BASE + 0x043C) +#define RTC_ACOP16 (volatile unsigned *)(RTC_BASE + 0x0440) +#define RTC_ACOP17 (volatile unsigned *)(RTC_BASE + 0x0444) +#define RTC_ACOP18 (volatile unsigned *)(RTC_BASE + 0x0448) +#define RTC_ACOP19 (volatile unsigned *)(RTC_BASE + 0x044C) +#define RTC_ACOP20 (volatile unsigned *)(RTC_BASE + 0x0450) +#define RTC_ACOP21 (volatile unsigned *)(RTC_BASE + 0x0454) +#define RTC_ACOP22 (volatile unsigned *)(RTC_BASE + 0x0458) +#define RTC_ACOP23 (volatile unsigned *)(RTC_BASE + 0x045C) +#define RTC_ACOP24 (volatile unsigned *)(RTC_BASE + 0x0460) +#define RTC_ACOP25 (volatile unsigned *)(RTC_BASE + 0x0464) +#define RTC_ACOP26 (volatile unsigned *)(RTC_BASE + 0x0468) +#define RTC_ACOP27 (volatile unsigned *)(RTC_BASE + 0x046C) +#define RTC_ACOP28 (volatile unsigned *)(RTC_BASE + 0x0470) +#define RTC_ACOP29 (volatile unsigned *)(RTC_BASE + 0x0474) +#define RTC_ACOP30 (volatile unsigned *)(RTC_BASE + 0x0478) +#define RTC_ACOP31 (volatile unsigned *)(RTC_BASE + 0x047C) +#define RTC_ACOP32 (volatile unsigned *)(RTC_BASE + 0x0480) +#define RTC_ACOP33 (volatile unsigned *)(RTC_BASE + 0x0484) +#define RTC_ACOP34 (volatile unsigned *)(RTC_BASE + 0x0488) +#define RTC_ACOP35 (volatile unsigned *)(RTC_BASE + 0x048C) +#define RTC_ACOP36 (volatile unsigned *)(RTC_BASE + 0x0490) +#define RTC_ACOP37 (volatile unsigned *)(RTC_BASE + 0x0494) +#define RTC_ACOP38 (volatile unsigned *)(RTC_BASE + 0x0498) +#define RTC_ACOP39 (volatile unsigned *)(RTC_BASE + 0x049C) +#define RTC_ACOP40 (volatile unsigned *)(RTC_BASE + 0x04A0) +#define RTC_ACOP41 (volatile unsigned *)(RTC_BASE + 0x04A4) +#define RTC_ACOP42 (volatile unsigned *)(RTC_BASE + 0x04A8) +#define RTC_ACOP43 (volatile unsigned *)(RTC_BASE + 0x04AC) +#define RTC_ACOP44 (volatile unsigned *)(RTC_BASE + 0x04B0) +#define RTC_ACOP45 (volatile unsigned *)(RTC_BASE + 0x04B4) +#define RTC_ACOP46 (volatile unsigned *)(RTC_BASE + 0x04B8) +#define RTC_ACOP47 (volatile unsigned *)(RTC_BASE + 0x04BC) +#define RTC_ACOP48 (volatile unsigned *)(RTC_BASE + 0x04C0) +#define RTC_ACOP49 (volatile unsigned *)(RTC_BASE + 0x04C4) +#define RTC_ACOP50 (volatile unsigned *)(RTC_BASE + 0x04C8) +#define RTC_ACOP51 (volatile unsigned *)(RTC_BASE + 0x04CC) +#define RTC_ACOP52 (volatile unsigned *)(RTC_BASE + 0x04D0) +#define RTC_ACOP53 (volatile unsigned *)(RTC_BASE + 0x04D4) +#define RTC_ACOP54 (volatile unsigned *)(RTC_BASE + 0x04D8) +#define RTC_ACOP55 (volatile unsigned *)(RTC_BASE + 0x04DC) +#define RTC_ACOP56 (volatile unsigned *)(RTC_BASE + 0x04E0) +#define RTC_ACOP57 (volatile unsigned *)(RTC_BASE + 0x04E4) +#define RTC_ACOP58 (volatile unsigned *)(RTC_BASE + 0x04E8) +#define RTC_ACOP59 (volatile unsigned *)(RTC_BASE + 0x04EC) +#define RTC_ACOP60 (volatile unsigned *)(RTC_BASE + 0x04F0) +#define RTC_ACOP61 (volatile unsigned *)(RTC_BASE + 0x04F4) +#define RTC_ACOP62 (volatile unsigned *)(RTC_BASE + 0x04F8) +#define RTC_ACOP63 (volatile unsigned *)(RTC_BASE + 0x04FC) + +/******************************************************************************/ +/* */ +/* Flash Controller (Flash) */ +/* */ +/******************************************************************************/ +#define FLASH_STA (volatile unsigned *) (FLASH_BASE + 0xFFFBC) +#define FLASH_INT (volatile unsigned *) (FLASH_BASE + 0x000FFFCC) +#define FLASH_CSSADDR (volatile unsigned *) (FLASH_BASE + 0x000FFFD0) +#define FLASH_CSEADDR (volatile unsigned *) (FLASH_BASE + 0x000FFFD4) +#define FLASH_CSVALUE (volatile unsigned *) (FLASH_BASE + 0x000FFFD8) +#define FLASH_CSCVALUE (volatile unsigned *) (FLASH_BASE + 0x000FFFDC) +#define FLASH_PASS (volatile unsigned *) (FLASH_BASE + 0x000FFFE0) +#define FLASH_CTRL (volatile unsigned *) (FLASH_BASE + 0x000FFFE4) +#define FLASH_PGADDR (volatile unsigned *) (FLASH_BASE + 0x000FFFE8) +#define FLASH_PGDATA (volatile unsigned *) (FLASH_BASE + 0x000FFFEC) +#define FLASH_PGB0 (volatile unsigned char*) (FLASH_BASE + 0x000FFFEC) +#define FLASH_PGB1 (volatile unsigned char*) (FLASH_BASE + 0x000FFFED) +#define FLASH_PGB2 (volatile unsigned char*) (FLASH_BASE + 0x000FFFEE) +#define FLASH_PGB3 (volatile unsigned char*) (FLASH_BASE + 0x000FFFEF) +#define FLASH_PGHW0 (volatile unsigned short*)(FLASH_BASE + 0x000FFFEC) +#define FLASH_PGHW1 (volatile unsigned short*)(FLASH_BASE + 0x000FFFEE) +#define FLASH_CONF (volatile unsigned *) (FLASH_BASE + 0x000FFFF0) +#define FLASH_SERASE (volatile unsigned *) (FLASH_BASE + 0x000FFFF4) +#define FLASH_CERASE (volatile unsigned *) (FLASH_BASE + 0x000FFFF8) +#define FLASH_DSTB (volatile unsigned *) (FLASH_BASE + 0x000FFFFC) + +#define FLASH_NVRPASS (volatile unsigned *) (FLASH_BASE + 0xFFFC0) +#define FLASH_BDPASS (volatile unsigned *) (FLASH_BASE + 0xFFFC4) +#define FLASH_KEY (volatile unsigned *) (FLASH_BASE + 0xFFFC8) + +/******************************************************************************/ +/* */ +/* GPIO Controller (GPIO) */ +/* */ +/******************************************************************************/ +#define IOB_OEN (volatile unsigned *)(GPIO_BASE + 0x00000020) +#define IOB_IE (volatile unsigned *)(GPIO_BASE + 0x00000024) +#define IOB_DAT (volatile unsigned *)(GPIO_BASE + 0x00000028) +#define IOB_ATT (volatile unsigned *)(GPIO_BASE + 0x0000002C) +#define IOB_STS (volatile unsigned *)(GPIO_BASE + 0x00000030) +#define IOC_OEN (volatile unsigned *)(GPIO_BASE + 0x00000040) +#define IOC_IE (volatile unsigned *)(GPIO_BASE + 0x00000044) +#define IOC_DAT (volatile unsigned *)(GPIO_BASE + 0x00000048) +#define IOC_ATT (volatile unsigned *)(GPIO_BASE + 0x0000004C) +#define IOC_STS (volatile unsigned *)(GPIO_BASE + 0x00000050) +#define IOD_OEN (volatile unsigned *)(GPIO_BASE + 0x00000060) +#define IOD_IE (volatile unsigned *)(GPIO_BASE + 0x00000064) +#define IOD_DAT (volatile unsigned *)(GPIO_BASE + 0x00000068) +#define IOD_ATT (volatile unsigned *)(GPIO_BASE + 0x0000006C) +#define IOD_STS (volatile unsigned *)(GPIO_BASE + 0x00000070) +#define IOE_OEN (volatile unsigned *)(GPIO_BASE + 0x00000080) +#define IOE_IE (volatile unsigned *)(GPIO_BASE + 0x00000084) +#define IOE_DAT (volatile unsigned *)(GPIO_BASE + 0x00000088) +#define IOE_ATT (volatile unsigned *)(GPIO_BASE + 0x0000008C) +#define IOE_STS (volatile unsigned *)(GPIO_BASE + 0x00000090) +#define IOF_OEN (volatile unsigned *)(GPIO_BASE + 0x000000A0) +#define IOF_IE (volatile unsigned *)(GPIO_BASE + 0x000000A4) +#define IOF_DAT (volatile unsigned *)(GPIO_BASE + 0x000000A8) +#define IOF_ATT (volatile unsigned *)(GPIO_BASE + 0x000000AC) +#define IOF_STS (volatile unsigned *)(GPIO_BASE + 0x000000B0) +#define IOB_SEL (volatile unsigned *)(GPIO_BASE + 0x000000C0) +#define IOE_SEL (volatile unsigned *)(GPIO_BASE + 0x000000CC) +#define IO_MISC (volatile unsigned *)(GPIO_BASE + 0x000000E0) + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ +#define DMA_IE (volatile unsigned *)(DMA_BASE + 0x0000) +#define DMA_STS (volatile unsigned *)(DMA_BASE + 0x0004) +#define DMA_C0CTL (volatile unsigned *)(DMA_BASE + 0x0010) +#define DMA_C0SRC (volatile unsigned *)(DMA_BASE + 0x0014) +#define DMA_C0DST (volatile unsigned *)(DMA_BASE + 0x0018) +#define DMA_C0LEN (volatile unsigned *)(DMA_BASE + 0x001C) +#define DMA_C1CTL (volatile unsigned *)(DMA_BASE + 0x0020) +#define DMA_C1SRC (volatile unsigned *)(DMA_BASE + 0x0024) +#define DMA_C1DST (volatile unsigned *)(DMA_BASE + 0x0028) +#define DMA_C1LEN (volatile unsigned *)(DMA_BASE + 0x002C) +#define DMA_C2CTL (volatile unsigned *)(DMA_BASE + 0x0030) +#define DMA_C2SRC (volatile unsigned *)(DMA_BASE + 0x0034) +#define DMA_C2DST (volatile unsigned *)(DMA_BASE + 0x0038) +#define DMA_C2LEN (volatile unsigned *)(DMA_BASE + 0x003C) +#define DMA_C3CTL (volatile unsigned *)(DMA_BASE + 0x0040) +#define DMA_C3SRC (volatile unsigned *)(DMA_BASE + 0x0044) +#define DMA_C3DST (volatile unsigned *)(DMA_BASE + 0x0048) +#define DMA_C3LEN (volatile unsigned *)(DMA_BASE + 0x004C) +#define DMA_AESCTL (volatile unsigned *)(DMA_BASE + 0x0050) +#define DMA_AESKEY0 (volatile unsigned *)(DMA_BASE + 0x0060) +#define DMA_AESKEY1 (volatile unsigned *)(DMA_BASE + 0x0064) +#define DMA_AESKEY2 (volatile unsigned *)(DMA_BASE + 0x0068) +#define DMA_AESKEY3 (volatile unsigned *)(DMA_BASE + 0x006C) +#define DMA_AESKEY4 (volatile unsigned *)(DMA_BASE + 0x0070) +#define DMA_AESKEY5 (volatile unsigned *)(DMA_BASE + 0x0074) +#define DMA_AESKEY6 (volatile unsigned *)(DMA_BASE + 0x0078) +#define DMA_AESKEY7 (volatile unsigned *)(DMA_BASE + 0x007C) + +/******************************************************************************/ +/* */ +/* UART Controller (UART) */ +/* */ +/******************************************************************************/ +#define UART0_DATA (volatile unsigned *)(UART0_BASE + 0x0000) +#define UART0_STATE (volatile unsigned *)(UART0_BASE + 0x0004) +#define UART0_CTRL (volatile unsigned *)(UART0_BASE + 0x0008) +#define UART0_INTSTS (volatile unsigned *)(UART0_BASE + 0x000C) +#define UART0_BAUDDIV (volatile unsigned *)(UART0_BASE + 0x0010) +#define UART0_CTRL2 (volatile unsigned *)(UART0_BASE + 0x0014) +#define UART1_DATA (volatile unsigned *)(UART1_BASE + 0x0000) +#define UART1_STATE (volatile unsigned *)(UART1_BASE + 0x0004) +#define UART1_CTRL (volatile unsigned *)(UART1_BASE + 0x0008) +#define UART1_INTSTS (volatile unsigned *)(UART1_BASE + 0x000C) +#define UART1_BAUDDIV (volatile unsigned *)(UART1_BASE + 0x0010) +#define UART1_CTRL2 (volatile unsigned *)(UART1_BASE + 0x0014) +#define UART2_DATA (volatile unsigned *)(UART2_BASE + 0x0000) +#define UART2_STATE (volatile unsigned *)(UART2_BASE + 0x0004) +#define UART2_CTRL (volatile unsigned *)(UART2_BASE + 0x0008) +#define UART2_INTSTS (volatile unsigned *)(UART2_BASE + 0x000C) +#define UART2_BAUDDIV (volatile unsigned *)(UART2_BASE + 0x0010) +#define UART2_CTRL2 (volatile unsigned *)(UART2_BASE + 0x0014) +#define UART3_DATA (volatile unsigned *)(UART3_BASE + 0x0000) +#define UART3_STATE (volatile unsigned *)(UART3_BASE + 0x0004) +#define UART3_CTRL (volatile unsigned *)(UART3_BASE + 0x0008) +#define UART3_INTSTS (volatile unsigned *)(UART3_BASE + 0x000C) +#define UART3_BAUDDIV (volatile unsigned *)(UART3_BASE + 0x0010) +#define UART3_CTRL2 (volatile unsigned *)(UART3_BASE + 0x0014) +#define UART4_DATA (volatile unsigned *)(UART4_BASE + 0x0000) +#define UART4_STATE (volatile unsigned *)(UART4_BASE + 0x0004) +#define UART4_CTRL (volatile unsigned *)(UART4_BASE + 0x0008) +#define UART4_INTSTS (volatile unsigned *)(UART4_BASE + 0x000C) +#define UART4_BAUDDIV (volatile unsigned *)(UART4_BASE + 0x0010) +#define UART4_CTRL2 (volatile unsigned *)(UART4_BASE + 0x0014) +#define UART5_DATA (volatile unsigned *)(UART5_BASE + 0x0000) +#define UART5_STATE (volatile unsigned *)(UART5_BASE + 0x0004) +#define UART5_CTRL (volatile unsigned *)(UART5_BASE + 0x0008) +#define UART5_INTSTS (volatile unsigned *)(UART5_BASE + 0x000C) +#define UART5_BAUDDIV (volatile unsigned *)(UART5_BASE + 0x0010) +#define UART5_CTRL2 (volatile unsigned *)(UART5_BASE + 0x0014) + +/******************************************************************************/ +/* */ +/* UART 32K Controller (U32K) */ +/* */ +/******************************************************************************/ +#define U32K0_CTRL0 (volatile unsigned *)(U32K0_BASE + 0x0000) +#define U32K0_CTRL1 (volatile unsigned *)(U32K0_BASE + 0x0004) +#define U32K0_PHASE (volatile unsigned *)(U32K0_BASE + 0x0008) +#define U32K0_DATA (volatile unsigned *)(U32K0_BASE + 0x000C) +#define U32K0_STS (volatile unsigned *)(U32K0_BASE + 0x0010) + +#define U32K1_CTRL0 (volatile unsigned *)(U32K1_BASE + 0x0000) +#define U32K1_CTRL1 (volatile unsigned *)(U32K1_BASE + 0x0004) +#define U32K1_PHASE (volatile unsigned *)(U32K1_BASE + 0x0008) +#define U32K1_DATA (volatile unsigned *)(U32K1_BASE + 0x000C) +#define U32K1_STS (volatile unsigned *)(U32K1_BASE + 0x0010) + +/******************************************************************************/ +/* */ +/* ISO7816 Controller (ISO7816) */ +/* */ +/******************************************************************************/ +#define ISO78160_BAUDDIVL (volatile unsigned *)(ISO78160_BASE + 0x0004) +#define ISO78160_BAUDDIVH (volatile unsigned *)(ISO78160_BASE + 0x0008) +#define ISO78160_DATA (volatile unsigned *)(ISO78160_BASE + 0x000C) +#define ISO78160_INFO (volatile unsigned *)(ISO78160_BASE + 0x0010) +#define ISO78160_CFG (volatile unsigned *)(ISO78160_BASE + 0x0014) +#define ISO78160_CLK (volatile unsigned *)(ISO78160_BASE + 0x0018) +#define ISO78161_BAUDDIVL (volatile unsigned *)(ISO78161_BASE + 0x0004) +#define ISO78161_BAUDDIVH (volatile unsigned *)(ISO78161_BASE + 0x0008) +#define ISO78161_DATA (volatile unsigned *)(ISO78161_BASE + 0x000C) +#define ISO78161_INFO (volatile unsigned *)(ISO78161_BASE + 0x0010) +#define ISO78161_CFG (volatile unsigned *)(ISO78161_BASE + 0x0014) +#define ISO78161_CLK (volatile unsigned *)(ISO78161_BASE + 0x0018) + +/******************************************************************************/ +/* */ +/* Timer Controller (Timer) */ +/* */ +/******************************************************************************/ +#define TMR0_CTRL (volatile unsigned *)(TMR0_BASE + 0x0000) +#define TMR0_VALUE (volatile unsigned *)(TMR0_BASE + 0x0004) +#define TMR0_RELOAD (volatile unsigned *)(TMR0_BASE + 0x0008) +#define TMR0_INT (volatile unsigned *)(TMR0_BASE + 0x000C) +#define TMR1_CTRL (volatile unsigned *)(TMR1_BASE + 0x0000) +#define TMR1_VALUE (volatile unsigned *)(TMR1_BASE + 0x0004) +#define TMR1_RELOAD (volatile unsigned *)(TMR1_BASE + 0x0008) +#define TMR1_INT (volatile unsigned *)(TMR1_BASE + 0x000C) +#define TMR2_CTRL (volatile unsigned *)(TMR2_BASE + 0x0000) +#define TMR2_VALUE (volatile unsigned *)(TMR2_BASE + 0x0004) +#define TMR2_RELOAD (volatile unsigned *)(TMR2_BASE + 0x0008) +#define TMR2_INT (volatile unsigned *)(TMR2_BASE + 0x000C) +#define TMR3_CTRL (volatile unsigned *)(TMR3_BASE + 0x0000) +#define TMR3_VALUE (volatile unsigned *)(TMR3_BASE + 0x0004) +#define TMR3_RELOAD (volatile unsigned *)(TMR3_BASE + 0x0008) +#define TMR3_INT (volatile unsigned *)(TMR3_BASE + 0x000C) + +/******************************************************************************/ +/* */ +/* PWM Controller (PWM) */ +/* */ +/******************************************************************************/ +#define PWM0_CTL (volatile unsigned *)(PWM0_BASE + 0x0000) +#define PWM0_TAR (volatile unsigned *)(PWM0_BASE + 0x0004) +#define PWM0_CCTL0 (volatile unsigned *)(PWM0_BASE + 0x0008) +#define PWM0_CCTL1 (volatile unsigned *)(PWM0_BASE + 0x000C) +#define PWM0_CCTL2 (volatile unsigned *)(PWM0_BASE + 0x0010) +#define PWM0_CCR0 (volatile unsigned *)(PWM0_BASE + 0x0014) +#define PWM0_CCR1 (volatile unsigned *)(PWM0_BASE + 0x0018) +#define PWM0_CCR2 (volatile unsigned *)(PWM0_BASE + 0x001C) +#define PWM1_CTL (volatile unsigned *)(PWM1_BASE + 0x0000) +#define PWM1_TAR (volatile unsigned *)(PWM1_BASE + 0x0004) +#define PWM1_CCTL0 (volatile unsigned *)(PWM1_BASE + 0x0008) +#define PWM1_CCTL1 (volatile unsigned *)(PWM1_BASE + 0x000C) +#define PWM1_CCTL2 (volatile unsigned *)(PWM1_BASE + 0x0010) +#define PWM1_CCR0 (volatile unsigned *)(PWM1_BASE + 0x0014) +#define PWM1_CCR1 (volatile unsigned *)(PWM1_BASE + 0x0018) +#define PWM1_CCR2 (volatile unsigned *)(PWM1_BASE + 0x001C) +#define PWM2_CTL (volatile unsigned *)(PWM2_BASE + 0x0000) +#define PWM2_TAR (volatile unsigned *)(PWM2_BASE + 0x0004) +#define PWM2_CCTL0 (volatile unsigned *)(PWM2_BASE + 0x0008) +#define PWM2_CCTL1 (volatile unsigned *)(PWM2_BASE + 0x000C) +#define PWM2_CCTL2 (volatile unsigned *)(PWM2_BASE + 0x0010) +#define PWM2_CCR0 (volatile unsigned *)(PWM2_BASE + 0x0014) +#define PWM2_CCR1 (volatile unsigned *)(PWM2_BASE + 0x0018) +#define PWM2_CCR2 (volatile unsigned *)(PWM2_BASE + 0x001C) +#define PWM3_CTL (volatile unsigned *)(PWM3_BASE + 0x0000) +#define PWM3_TAR (volatile unsigned *)(PWM3_BASE + 0x0004) +#define PWM3_CCTL0 (volatile unsigned *)(PWM3_BASE + 0x0008) +#define PWM3_CCTL1 (volatile unsigned *)(PWM3_BASE + 0x000C) +#define PWM3_CCTL2 (volatile unsigned *)(PWM3_BASE + 0x0010) +#define PWM3_CCR0 (volatile unsigned *)(PWM3_BASE + 0x0014) +#define PWM3_CCR1 (volatile unsigned *)(PWM3_BASE + 0x0018) +#define PWM3_CCR2 (volatile unsigned *)(PWM3_BASE + 0x001C) +#define PWM_O_SEL (volatile unsigned *)(PWM0_BASE + 0x00F0) +//#define PWM_I_SEL01 (volatile unsigned *)(PWM0_BASE + 0x00F4) +//#define PWM_I_SEL23 (volatile unsigned *)(PWM0_BASE + 0x00F8) + +/******************************************************************************/ +/* */ +/* LCD Controller (LCD) */ +/* */ +/******************************************************************************/ +#define LCD_FB00 (volatile unsigned *)(LCD_BASE + 0x0000) +#define LCD_FB01 (volatile unsigned *)(LCD_BASE + 0x0004) +#define LCD_FB02 (volatile unsigned *)(LCD_BASE + 0x0008) +#define LCD_FB03 (volatile unsigned *)(LCD_BASE + 0x000C) +#define LCD_FB04 (volatile unsigned *)(LCD_BASE + 0x0010) +#define LCD_FB05 (volatile unsigned *)(LCD_BASE + 0x0014) +#define LCD_FB06 (volatile unsigned *)(LCD_BASE + 0x0018) +#define LCD_FB07 (volatile unsigned *)(LCD_BASE + 0x001C) +#define LCD_FB08 (volatile unsigned *)(LCD_BASE + 0x0020) +#define LCD_FB09 (volatile unsigned *)(LCD_BASE + 0x0024) +#define LCD_FB0A (volatile unsigned *)(LCD_BASE + 0x0028) +#define LCD_FB0B (volatile unsigned *)(LCD_BASE + 0x002C) +#define LCD_FB0C (volatile unsigned *)(LCD_BASE + 0x0030) +#define LCD_FB0D (volatile unsigned *)(LCD_BASE + 0x0034) +#define LCD_FB0E (volatile unsigned *)(LCD_BASE + 0x0038) +#define LCD_FB0F (volatile unsigned *)(LCD_BASE + 0x003C) +#define LCD_FB10 (volatile unsigned *)(LCD_BASE + 0x0040) +#define LCD_FB11 (volatile unsigned *)(LCD_BASE + 0x0044) +#define LCD_FB12 (volatile unsigned *)(LCD_BASE + 0x0048) +#define LCD_FB13 (volatile unsigned *)(LCD_BASE + 0x004C) +#define LCD_FB14 (volatile unsigned *)(LCD_BASE + 0x0050) +#define LCD_FB15 (volatile unsigned *)(LCD_BASE + 0x0054) +#define LCD_FB16 (volatile unsigned *)(LCD_BASE + 0x0058) +#define LCD_FB17 (volatile unsigned *)(LCD_BASE + 0x005C) +#define LCD_FB18 (volatile unsigned *)(LCD_BASE + 0x0060) +#define LCD_FB19 (volatile unsigned *)(LCD_BASE + 0x0064) +#define LCD_FB1A (volatile unsigned *)(LCD_BASE + 0x0068) +#define LCD_FB1B (volatile unsigned *)(LCD_BASE + 0x006C) +#define LCD_FB1C (volatile unsigned *)(LCD_BASE + 0x0070) +#define LCD_FB1D (volatile unsigned *)(LCD_BASE + 0x0074) +#define LCD_FB1E (volatile unsigned *)(LCD_BASE + 0x0078) +#define LCD_FB1F (volatile unsigned *)(LCD_BASE + 0x007C) +#define LCD_FB20 (volatile unsigned *)(LCD_BASE + 0x0080) +#define LCD_FB21 (volatile unsigned *)(LCD_BASE + 0x0084) +#define LCD_FB22 (volatile unsigned *)(LCD_BASE + 0x0088) +#define LCD_FB23 (volatile unsigned *)(LCD_BASE + 0x008C) +#define LCD_FB24 (volatile unsigned *)(LCD_BASE + 0x0090) +#define LCD_FB25 (volatile unsigned *)(LCD_BASE + 0x0094) +#define LCD_FB26 (volatile unsigned *)(LCD_BASE + 0x0098) +#define LCD_FB27 (volatile unsigned *)(LCD_BASE + 0x009C) +#define LCD_CTRL (volatile unsigned *)(LCD_BASE + 0x0100) +#define LCD_CTRL2 (volatile unsigned *)(LCD_BASE + 0x0104) +#define LCD_SEGCTRL0 (volatile unsigned *)(LCD_BASE + 0x0108) +#define LCD_SEGCTRL1 (volatile unsigned *)(LCD_BASE + 0x010C) +#define LCD_SEGCTRL2 (volatile unsigned *)(LCD_BASE + 0x0110) + +/******************************************************************************/ +/* */ +/* SPI Controller (SPI) */ +/* */ +/******************************************************************************/ +#define SPI1_CTRL (volatile unsigned *)(SPI1_BASE + 0x0000) +#define SPI1_TXSTS (volatile unsigned *)(SPI1_BASE + 0x0004) +#define SPI1_TXDATA (volatile unsigned *)(SPI1_BASE + 0x0008) +#define SPI1_RXSTS (volatile unsigned *)(SPI1_BASE + 0x000C) +#define SPI1_RXDATA (volatile unsigned *)(SPI1_BASE + 0x0010) +#define SPI1_MISC (volatile unsigned *)(SPI1_BASE + 0x0014) +#define SPI2_CTRL (volatile unsigned *)(SPI2_BASE + 0x0000) +#define SPI2_TXSTS (volatile unsigned *)(SPI2_BASE + 0x0004) +#define SPI2_TXDATA (volatile unsigned *)(SPI2_BASE + 0x0008) +#define SPI2_RXSTS (volatile unsigned *)(SPI2_BASE + 0x000C) +#define SPI2_RXDATA (volatile unsigned *)(SPI2_BASE + 0x0010) +#define SPI2_MISC (volatile unsigned *)(SPI2_BASE + 0x0014) + +/******************************************************************************/ +/* */ +/* I2C Controller (I2C) */ +/* */ +/******************************************************************************/ +#define I2C_DATA (volatile unsigned *)(I2C_BASE + 0x0000) +#define I2C_ADDR (volatile unsigned *)(I2C_BASE + 0x0004) +#define I2C_CTRL (volatile unsigned *)(I2C_BASE + 0x0008) +#define I2C_STS (volatile unsigned *)(I2C_BASE + 0x000C) +#define I2C_SMBSEL (volatile unsigned *)(I2C_BASE + 0x0010) +#define I2C_SMBDST (volatile unsigned *)(I2C_BASE + 0x0014) +#define I2C_CTRL2 (volatile unsigned *)(I2C_BASE + 0x0018) + +/******************************************************************************/ +/* */ +/* MISC Controller (MISC) */ +/* */ +/******************************************************************************/ +#define MISC_SRAMINT (volatile unsigned *)(MISC_BASE + 0x0000) +#define MISC_SRAMINIT (volatile unsigned *)(MISC_BASE + 0x0004) +#define MISC_PARERR (volatile unsigned *)(MISC_BASE + 0x0008) +#define MISC_IREN (volatile unsigned *)(MISC_BASE + 0x000C) +#define MISC_DUTYL (volatile unsigned *)(MISC_BASE + 0x0010) +#define MISC_DUTYH (volatile unsigned *)(MISC_BASE + 0x0014) +#define MISC_IRQLAT (volatile unsigned *)(MISC_BASE + 0x0018) + +#define MISC2_FLASHWC (volatile unsigned *)(MISC2_BASE + 0x0000) +#define MISC2_CLKSEL (volatile unsigned *)(MISC2_BASE + 0x0004) +#define MISC2_CLKDIVH (volatile unsigned *)(MISC2_BASE + 0x0008) +#define MISC2_CLKDIVP (volatile unsigned *)(MISC2_BASE + 0x000C) +#define MISC2_HCLKEN (volatile unsigned *)(MISC2_BASE + 0x0010) +#define MISC2_PCLKEN (volatile unsigned *)(MISC2_BASE + 0x0014) + +/******************************************************************************/ +/* */ +/* CRYPT Controller (CRYPT) */ +/* */ +/******************************************************************************/ +#define CRYPT_CTRL (volatile unsigned *)(CRYPT_BASE + 0x0000) +#define CRYPT_PTRA (volatile unsigned *)(CRYPT_BASE + 0x0004) +#define CRYPT_PTRB (volatile unsigned *)(CRYPT_BASE + 0x0008) +#define CRYPT_PTRO (volatile unsigned *)(CRYPT_BASE + 0x000C) +#define CRYPT_CARRY (volatile unsigned *)(CRYPT_BASE + 0x0010) + +/** @addtogroup Exported_macro + * @{ + */ + +/****************************** PMU Instances *********************************/ +#define IS_PMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU) + +/****************************** PMU_RETRAM Instances **************************/ +#define IS_PMU_RETRAM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU_RETRAM) + +/****************************** ANA Instances *********************************/ +#define IS_ANA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ANA) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + +/****************************** FLASH Instances *******************************/ +#define IS_FLASH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FLASH) + +/****************************** GPIO Instances ********************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOE) || \ + ((INSTANCE) == GPIOF)) + +#define IS_PMUIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPIOA) + +#define IS_GPIOAF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOE)) + +/****************************** DMA Instances *********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA) + +/****************************** UART Instances ********************************/ +#define IS_UART_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UART0) || \ + ((INSTANCE) == UART1) || \ + ((INSTANCE) == UART2) || \ + ((INSTANCE) == UART3) || \ + ((INSTANCE) == UART4) || \ + ((INSTANCE) == UART5)) + +/****************************** U32K Instances ********************************/ +#define IS_U32K_ALL_INSTANCE(INSTANCE) (((INSTANCE) == U32K0) || \ + ((INSTANCE) == U32K1)) + +/****************************** ISO7816 Instances *****************************/ +#define IS_ISO7816_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ISO78160) || \ + ((INSTANCE) == ISO78161)) + +/****************************** TMR Instances *********************************/ +#define IS_TMR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TMR0) || \ + ((INSTANCE) == TMR1) || \ + ((INSTANCE) == TMR2) || \ + ((INSTANCE) == TMR3)) + +/****************************** PWM Instances *********************************/ +#define IS_PWM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PWM0) || \ + ((INSTANCE) == PWM1) || \ + ((INSTANCE) == PWM2) || \ + ((INSTANCE) == PWM3)) + +#define IS_PWMMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PWMMUX) + +/****************************** LCD Instances *********************************/ +#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) + +/****************************** SPI Instances *********************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/****************************** I2C Instances *********************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C) + +/****************************** MISC Instances ********************************/ +#define IS_MISC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC) + +#define IS_MISC2_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MISC2) + +/****************************** CRYPT Instances *******************************/ +#define IS_CRYPT_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRYPT) + + + +#ifdef USE_TARGET_DRIVER + #include "lib_conf.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h new file mode 100644 index 0000000000..913c171790 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file type_def.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Typedef file + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +#ifndef __TYPE_DEF_H +#define __TYPE_DEF_H + +#define ENABLE 1 +#define DISABLE 0 +#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE)) + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__GNUC__) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#endif /* __TYPE_DEF_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S new file mode 100644 index 0000000000..b77a821a44 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S @@ -0,0 +1,478 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.equ __CHIPINITIAL, 1 + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/************************************************************************* +* Chip init. +* 1. Load flash configuration +* 2. Load ANA_REG(B/C/D/E) information +* 3. Load ANA_REG10 information + +**************************************************************************/ +.if (__CHIPINITIAL != 0) + .section .chipinit_section.__CHIP_INIT +__CHIP_INIT: +CONFIG1_START: + /*-------------------------------*/ + /* 1. Load flash configuration */ + /* Unlock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + /* Load configure word 0 to 7 + Compare bit[7:0] */ + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1: + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1: + /* Load configure word 8 to 11 + Compare bit 31,24,23:16,8,7:0 */ + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2: + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2: + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2: + /* Lock flash */ + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + /*-------------------------------*/ + /* 2. Load ANA_REG(B/C/D/E) information */ +CONFIG2_START: + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR: + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK: + /* ANA_REGB */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + /* ANA_REGC */ + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + /* ANA_REGD */ + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + /* ANA_REGE */ + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR: + B ANADAT_CHECKSUM2_ERR + /*-------------------------------*/ + /* 3. Load ANA_REG10 information */ +CONFIG3_START: + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR: + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK: + /* ANA_REG10 */ + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR: + B ANADAT10_CHECKSUM2_ERR +.size __CHIP_INIT, .-__CHIP_INIT +.endif + + +.if (__CHIPINITIAL != 0) + .global __CHIP_INIT + .section .chipinit_section.Reset_Handler +.else + .section .text.Reset_Handler +.endif + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.if (__CHIPINITIAL != 0) +/* Chip Initiliazation */ + bl __CHIP_INIT +/* System Initiliazation */ + bl SystemInit +.endif + +/* set stack pointer */ + ldr r0, =_estack + mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word PMU_IRQHandler /* 0: PMU */ + .word RTC_IRQHandler /* 1: RTC */ + .word U32K0_IRQHandler /* 2: U32K0 */ + .word U32K1_IRQHandler /* 3: U32K1 */ + .word I2C_IRQHandler /* 4: I2C */ + .word SPI1_IRQHandler /* 5: SPI1 */ + .word UART0_IRQHandler /* 6: UART0 */ + .word UART1_IRQHandler /* 7: UART1 */ + .word UART2_IRQHandler /* 8: UART2 */ + .word UART3_IRQHandler /* 9: UART3 */ + .word UART4_IRQHandler /* 10: UART4 */ + .word UART5_IRQHandler /* 11: UART5 */ + .word ISO78160_IRQHandler /* 12: ISO78160 */ + .word ISO78161_IRQHandler /* 13: ISO78161 */ + .word TMR0_IRQHandler /* 14: TMR0 */ + .word TMR1_IRQHandler /* 15: TMR1 */ + .word TMR2_IRQHandler /* 16: TMR2 */ + .word TMR3_IRQHandler /* 17: TMR3 */ + .word PWM0_IRQHandler /* 18: PWM0 */ + .word PWM1_IRQHandler /* 19: PWM1 */ + .word PWM2_IRQHandler /* 20: PWM2 */ + .word PWM3_IRQHandler /* 21: PWM3 */ + .word DMA_IRQHandler /* 22: DMA */ + .word FLASH_IRQHandler /* 23: FLASH */ + .word ANA_IRQHandler /* 24: ANA */ + .word 0 /* 25: Reserved */ + .word 0 /* 26: Reserved */ + .word SPI2_IRQHandler /* 27: SPI2 */ + .word SPI3_IRQHandler /* 28: SPI3 */ + .word 0 /* 29: Reserved */ + .word 0 /* 30: Reserved */ + .word 0 /* 31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PMU_IRQHandler + .thumb_set PMU_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak U32K0_IRQHandler + .thumb_set U32K0_IRQHandler,Default_Handler + + .weak U32K1_IRQHandler + .thumb_set U32K1_IRQHandler,Default_Handler + + .weak I2C_IRQHandler + .thumb_set I2C_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak UART0_IRQHandler + .thumb_set UART0_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak ISO78160_IRQHandler + .thumb_set ISO78160_IRQHandler,Default_Handler + + .weak ISO78161_IRQHandler + .thumb_set ISO78161_IRQHandler,Default_Handler + + .weak TMR0_IRQHandler + .thumb_set TMR0_IRQHandler,Default_Handler + + .weak TMR1_IRQHandler + .thumb_set TMR1_IRQHandler,Default_Handler + + .weak TMR2_IRQHandler + .thumb_set TMR2_IRQHandler,Default_Handler + + .weak TMR3_IRQHandler + .thumb_set TMR3_IRQHandler,Default_Handler + + .weak PWM0_IRQHandler + .thumb_set PWM0_IRQHandler,Default_Handler + + .weak PWM1_IRQHandler + .thumb_set PWM1_IRQHandler,Default_Handler + + .weak PWM2_IRQHandler + .thumb_set PWM2_IRQHandler,Default_Handler + + .weak PWM3_IRQHandler + .thumb_set PWM3_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak ANA_IRQHandler + .thumb_set ANA_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/keil5/startup_target.S b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/keil5/startup_target.S new file mode 100644 index 0000000000..90fd31b143 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/keil5/startup_target.S @@ -0,0 +1,450 @@ +;/** +;* @file startup_target.s +;* @author Application Team +;* @version V1.1.0 +;* @date 2019-10-28 +;* @brief Target Devices vector table. +;******************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__CHIPINITIAL EQU 1 + +Stack_Size EQU 0x000001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PMU_IRQHandler ; 0: PMU + DCD RTC_IRQHandler ; 1: RTC + DCD U32K0_IRQHandler ; 2: U32K0 + DCD U32K1_IRQHandler ; 3: U32K1 + DCD I2C_IRQHandler ; 4: I2C + DCD SPI1_IRQHandler ; 5: SPI1 + DCD UART0_IRQHandler ; 6: UART0 + DCD UART1_IRQHandler ; 7: UART1 + DCD UART2_IRQHandler ; 8: UART2 + DCD UART3_IRQHandler ; 9: UART3 + DCD UART4_IRQHandler ; 10: UART4 + DCD UART5_IRQHandler ; 11: UART5 + DCD ISO78160_IRQHandler ; 12: ISO78160 + DCD ISO78161_IRQHandler ; 13: ISO78161 + DCD TMR0_IRQHandler ; 14: TMR0 + DCD TMR1_IRQHandler ; 15: TMR1 + DCD TMR2_IRQHandler ; 16: TMR2 + DCD TMR3_IRQHandler ; 17: TMR3 + DCD PWM0_IRQHandler ; 18: PWM0 + DCD PWM1_IRQHandler ; 19: PWM1 + DCD PWM2_IRQHandler ; 20: PWM2 + DCD PWM3_IRQHandler ; 21: PWM3 + DCD DMA_IRQHandler ; 22: DMA + DCD FLASH_IRQHandler ; 23: FLASH + DCD ANA_IRQHandler ; 24: ANA + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD SPI2_IRQHandler ; 27: SPI2 + DCD SPI3_IRQHandler ; 28: SPI3 + DCD 0 ; 29: Reserved + DCD 0 ; 30: Reserved + DCD 0 ; 31: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + ELSE + AREA |.text|, CODE, READONLY + ENDIF + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + IF (__CHIPINITIAL != 0) + LDR R0, =__CHIP_INIT + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + AREA |.text|, CODE, READONLY + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PMU_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT U32K0_IRQHandler [WEAK] + EXPORT U32K1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT ISO78160_IRQHandler [WEAK] + EXPORT ISO78161_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT PWM3_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT ANA_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + +PMU_IRQHandler +RTC_IRQHandler +U32K0_IRQHandler +U32K1_IRQHandler +I2C_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +ISO78160_IRQHandler +ISO78161_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +PWM2_IRQHandler +PWM3_IRQHandler +DMA_IRQHandler +FLASH_IRQHandler +ANA_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Chip init. +;; 1. Load flash configuration +;; 2. Load ANA_REG(B/C/D/E) information +;; 3. Load ANA_REG10 information + IF (__CHIPINITIAL != 0) + AREA |.ARM.__AT_0xC0|, CODE, READONLY + +__CHIP_INIT PROC +CONFIG1_START + ;-------------------------------; + ;; 1. Load flash configuration + ; Unlock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x55AAAA55 + STR R1, [R0] + ; Load configure word 0 to 7 + ; Compare bit[7:0] + LDR R0, =0x00080E00 + LDR R1, =0x20 + LDR R2, =0x000FFFE8 + LDR R3, =0x000FFFF0 + LDR R4, =0x0 + LDR R7, =0x0FF +FLASH_CONF_START_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_AGAIN_1 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_1 + BNE FLASH_CONF_WHILELOOP_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_1 + B FLASH_CONF_START_1 +FLASH_CONF_END_1 + ; Load configure word 8 to 11 + ; Compare bit 31,24,23:16,8,7:0 + LDR R1, =0x30 + LDR R7, =0x81FF81FF +FLASH_CONF_START_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 + BNE FLASH_CONF_AGAIN_1 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_AGAIN_2 + LDR R5, [R0] + STR R4, [R2] + STR R5, [R3] + LDR R6, [R3] + ANDS R5, R7 + ANDS R6, R7 + CMP R5, R6 +FLASH_CONF_WHILELOOP_2 + BNE FLASH_CONF_WHILELOOP_2 + ADDS R4, #4 + ADDS R0, #4 + CMP R1, R4 + BEQ FLASH_CONF_END_2 + B FLASH_CONF_START_2 +FLASH_CONF_END_2 + ; Lock flash + LDR R0, =0x000FFFE0 + LDR R1, =0x0 + STR R1, [R0] + ;-------------------------------; + ;; 2. Load ANA_REG(B/C/D/E) information +CONFIG2_START + LDR R4, =0x4001422C + LDR R5, =0x40014230 + LDR R6, =0x40014234 + LDR R7, =0x40014238 + LDR R0, =0x80DC0 + LDR R0, [R0] + LDR R1, =0x80DC4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DCC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM1_OK + B ANADAT_CHECKSUM1_ERR +ANADAT_CHECKSUM1_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM1_ERR + LDR R0, =0x80DD0 + LDR R0, [R0] + LDR R1, =0x80DD4 + LDR R1, [R1] + ADDS R2, R0, R1 + ADDS R2, #0x0FFFFFFFF + MVNS R2, R2 + LDR R3, =0x80DDC + LDR R3, [R3] + CMP R3, R2 + BEQ ANADAT_CHECKSUM2_OK + B ANADAT_CHECKSUM2_ERR +ANADAT_CHECKSUM2_OK + ; ANA_REGB + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R4] + ; ANA_REGC + LDR R1, =0x0FF00 + ANDS R1, R0 + LSRS R1, R1, #8 + STR R1, [R5] + ; ANA_REGD + LDR R1, =0x0FF0000 + ANDS R1, R0 + LSRS R1, R1, #16 + STR R1, [R6] + ; ANA_REGE + LDR R1, =0x0FF000000 + ANDS R1, R0 + LSRS R1, R1, #24 + STR R1, [R7] + B CONFIG3_START +ANADAT_CHECKSUM2_ERR + B ANADAT_CHECKSUM2_ERR + ;-------------------------------; + ;; 2. Load ANA_REG10 information +CONFIG3_START + LDR R7, =0x40014240 + LDR R0, =0x80DE0 + LDR R0, [R0] + LDR R1, =0x80DE4 + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM1_OK + B ANADAT10_CHECKSUM1_ERR +ANADAT10_CHECKSUM1_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM1_ERR + LDR R0, =0x80DE8 + LDR R0, [R0] + LDR R1, =0x80DEC + LDR R1, [R1] + MVNS R1, R1 + CMP R1, R0 + BEQ ANADAT10_CHECKSUM2_OK + B ANADAT10_CHECKSUM2_ERR +ANADAT10_CHECKSUM2_OK + ; ANA_REG10 + LDR R1, =0x0FF + ANDS R1, R0 + STR R1, [R7] + BX LR +ANADAT10_CHECKSUM2_ERR + B ANADAT10_CHECKSUM2_ERR + + NOP + ENDP + ENDIF + + END + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c new file mode 100644 index 0000000000..59af288800 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c @@ -0,0 +1,35 @@ +/** + ****************************************************************************** + * @file lib_CodeRAM.c + * @author Application Team + * @version V4.4.0 + * @date 2019-01-18 + * @brief Codes executed in SRAM. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_CodeRAM.h" + +#ifndef __GNUC__ +/** + * @brief Flash deep standby, enter idle mode. + * @note This function is executed in RAM. + * @param None + * @retval None + */ +__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void) +{ + /* Flash deep standby */ + FLASH->PASS = 0x55AAAA55; + FLASH->DSTB = 0xAA5555AA; + /* Enter Idle mode */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + __WFI(); +} +#endif + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c new file mode 100644 index 0000000000..d75753b048 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c @@ -0,0 +1,648 @@ +/** + ****************************************************************************** + * @file lib_LoadNVR.c + * @author Application Team + * @version V4.7.0 + * @date 2019-12-12 + * @brief Load information from NVR. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_LoadNVR.h" + + +/** + * @breif Load Analog trim data from NVR manually. + * @note Successful Operation: + * - Load [0x40DC0] or [0x40DD0] to ANA registers(B C D E), return 0. + * Operation failed: + * - return 1. + * @param None + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_LoadANADataManual(void) +{ + uint32_t checksum; + uint32_t op_reg; + uint32_t ana_data; + uint32_t key_reg = 0xFFFFFFFF; + + /* Get Analog data1 */ + ana_data = *NVR_ANA_TRIMDATA1; + op_reg = *NVR_ANA_OPREG1; + /* Calculate checksum1 */ + checksum = ~(ana_data + op_reg + key_reg); + /* Compare checksum1 */ + if (checksum == (*NVR_ANA_CHECKSUM1)) + { + ANA->REGB = (uint8_t)(ana_data); + ANA->REGC = (uint8_t)(ana_data >> 8); + ANA->REGD = (uint8_t)(ana_data >> 16); + ANA->REGE = (uint8_t)(ana_data >> 24); + return 0; + } + + /* Get Analog data2 */ + ana_data = *NVR_ANA_TRIMDATA2; + op_reg = *NVR_ANA_OPREG2; + /* Calculate checksum2 */ + checksum = ~(ana_data + op_reg + key_reg); + /* Compare checksum2 */ + if (checksum == (*NVR_ANA_CHECKSUM2)) + { + ANA->REGB = (uint8_t)(ana_data); + ANA->REGC = (uint8_t)(ana_data >> 8); + ANA->REGD = (uint8_t)(ana_data >> 16); + ANA->REGE = (uint8_t)(ana_data >> 24); + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Get the parameters of ADC voltage measuring. + * @note Voltage(unit:V) = aParameter*ADC_DATA + bParameter + * ADC_DATA: ADC channel original data + * aParameter/bParameter: Get from this function + * @param [in]Mode: + * NVR_3V_EXTERNAL_NODIV + * NVR_3V_EXTERNAL_RESDIV + * NVR_3V_EXTERNAL_CAPDIV + * NVR_3V_VDD_RESDIV + * NVR_3V_VDD_CAPDIV + * NVR_3V_BATRTC_RESDIV + * NVR_3V_BATRTC_CAPDIV + * NVR_5V_EXTERNAL_NODIV + * NVR_5V_EXTERNAL_RESDIV + * NVR_5V_EXTERNAL_CAPDIV + * NVR_5V_VDD_RESDIV + * NVR_5V_VDD_CAPDIV + * NVR_5V_BATRTC_RESDIV + * NVR_5V_BATRTC_CAPDIV + * @param [out]Parameter: The parameters get from NVR + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter) +{ + uint32_t checksum; + uint32_t i; + int32_t tmp_int; + + /* Check the parameters */ + assert_parameters(IS_NVR_ADCVOL_MODE(Mode)); + + /*----- Power supply: 5V -----*/ + if (0x100UL & Mode) + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_5VPARA_BASEADDR1+i); + checksum = ~(checksum); + if (checksum != *(NVR_5VPARA_BASEADDR1+i)) /* Checksum1 error */ + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_5VPARA_BASEADDR2+i); + checksum = ~(checksum); + if (checksum != *(NVR_5VPARA_BASEADDR2+i)) /* Checksum2 error */ + { + return 1; + } + else + { + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } + else + { + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } + /*----- Power supply: 3.3V -----*/ + else + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_3VPARA_BASEADDR1+i); + checksum = ~(checksum); + if (checksum != *(NVR_3VPARA_BASEADDR1+i)) /* Checksum1 error */ + { + checksum = 0UL; + for (i=0; i<14; i++) + checksum += *(NVR_3VPARA_BASEADDR2+i); + checksum = ~(checksum); + if (checksum != *(NVR_3VPARA_BASEADDR2+i)) /* Checksum2 error */ + { + return 1; + } + else + { + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } + else + { + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)); + Parameter->aParameter = (float)(tmp_int / 100000000.0); + tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)+1); + Parameter->bParameter = (float)(tmp_int / 100000000.0); + return 0; + } + } +} + +/** + * @breif Get BAT Measure result. + * @param [out]MEAResult The pointer to struct NVR_BATMEARES. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult) +{ + uint32_t bat_r; + uint32_t bat_c; + uint32_t checksum; + + bat_r = *NVR_BAT_R1; + bat_c = *NVR_BAT_C1; + /* Calculate checksum1 */ + checksum = ~(bat_r + bat_c); + if (checksum == (*NVR_BATMEA_CHECHSUM1)) + { + MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0); + MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0); + return 0; + } + + bat_r = *NVR_BAT_R2; + bat_c = *NVR_BAT_C2; + /* Calculate checksum2 */ + checksum = ~(bat_r + bat_c); + if (checksum == (*NVR_BATMEA_CHECHSUM2)) + { + MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0); + MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0); + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Load RTC ACPx pramameters from NVR to RTC registers. + Get RTC pramameters. + * @param [out]RTCTempData The pointer to struct NVR_RTCINFO. + * @retval 0: Function succeeded. + !0: Function not succeeded, load default value to registers. + bit[0]=1: Temperature Measure delta information checksum error, default value is 0. + bit[1]=1: P paramters checksum error, default value as follows + [P0]-214, [P1]1060, [P2]-19746971, [P5]6444, [P6]1342, [P7]0 + bit[2]=1: P4 checksum error, default value is 0 + bit[3]=1: ACKx checksum error, default value as follows + [K1]20827, [K2]21496, [K3]22020, [K4]24517, [K5]25257 + bit[4]=1: ACTI checksum error, default value is 0x1800(24.0) + bit[5]=1: ACKTEMP checksum error, defalut value is 0x3C2800EC + */ +uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData) +{ + uint32_t real_temp, mea_temp; + uint32_t rtc_data1, rtc_data2, rtc_data3, rtc_data4; + uint32_t rtc_p4; + uint32_t rtc_ack[5]; + uint32_t rtc_acti; + uint32_t rtc_acktemp; + uint32_t checksum; + float pclk_mul; + + int16_t TempDelta; + uint32_t retval = 0; + +/*------------------------ Temperature Measure delta -------------------------*/ + real_temp = *NVR_REALTEMP1; + mea_temp = *NVR_MEATEMP1; + /* Calculate checksum1 */ + checksum = ~(real_temp + mea_temp); + if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true + { + TempDelta = (int16_t)real_temp - (int16_t)mea_temp; + } + else + { + real_temp = *NVR_REALTEMP2; + mea_temp = *NVR_MEATEMP2; + /* Calculate checksum2 */ + checksum = ~(real_temp + mea_temp); + if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true + { + TempDelta = (int16_t)real_temp - (int16_t)mea_temp; + } + else + { + TempDelta = 0; + retval |= BIT0; + } + } + /* Get Measure delta information */ + RTCTempData->RTCTempDelta = TempDelta; + +/*------------------------------ P parameters --------------------------------*/ + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Get PCLK */ + RTCTempData->APBClock = CLK_GetPCLKFreq(); + pclk_mul = RTCTempData->APBClock / 6553600.0; + + rtc_data1 = *NVR_RTC1_P1_P0; + rtc_data2 = *NVR_RTC1_P2; + rtc_data3 = *NVR_RTC1_P5_P4; + rtc_data4 = *NVR_RTC1_P7_P6; + /* Calculate checksum1 */ + checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4); + if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true + { + /* Get information */ + RTCTempData->RTCTempP0 = (int16_t)(rtc_data1); + RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16); + RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16); + RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul); + RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16); + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF); + RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF); + RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF); + RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul)); + RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF); + } + else + { + rtc_data1 = *NVR_RTC2_P1_P0; + rtc_data2 = *NVR_RTC2_P2; + rtc_data3 = *NVR_RTC2_P5_P4; + rtc_data4 = *NVR_RTC2_P7_P6; + /* Calculate checksum2 */ + checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4); + if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true + { + /* Get information */ + RTCTempData->RTCTempP0 = (int16_t)(rtc_data1); + RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16); + RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16); + RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul); + RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16); + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF); + RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF); + RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256)); + RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF); + RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul)); + RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF); + } + else + { + /* Get information */ + RTCTempData->RTCTempP0 = -214; + RTCTempData->RTCTempP1 = 1060; + RTCTempData->RTCTempP2 = -19746971 + (TempDelta*256); + RTCTempData->RTCTempP5 = 6444; + RTCTempData->RTCTempP6 = (uint32_t)((int32_t)(1342*pclk_mul)); + RTCTempData->RTCTempP7 = 0; + + /* Load data to ACPx register */ + RTC->ACP0 = (uint16_t)(-214); + RTC->ACP1 = (uint16_t)(1060); + RTC->ACP2 = (uint32_t)(-19746971 + (TempDelta*256)); + RTC->ACP5 = (uint16_t)(6444); + RTC->ACP6 = (uint16_t)((int32_t)(1342*pclk_mul)); + RTC->ACP7 = (uint16_t)(0); + + retval |= BIT1; + } + } + +/*----------------------------------- P4 -------------------------------------*/ + /* Calculate checksum1 */ + rtc_p4 = *NVR_RTC1_P4; + checksum = ~rtc_p4; + if (checksum == (*NVR_RTC1_P4_CHKSUM))//checksum1 true + { + /* Get information */ + RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4); + RTC->ACP4 = *NVR_RTC1_P4; + } + else + { + rtc_p4 = *NVR_RTC2_P4; + checksum = ~rtc_p4; + if (checksum == (*NVR_RTC2_P4_CHKSUM))//checksum2 true + { + /* Get information */ + RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4); + RTC->ACP4 = *NVR_RTC1_P4; + } + else + { + RTCTempData->RTCTempP4 = 0; + RTC->ACP4 = 0; + + retval |= BIT2; + } + } + +/*-------------------------- RTC ACKx parameters -----------------------------*/ + rtc_ack[0] = *NVR_RTC1_ACK1; + rtc_ack[1] = *NVR_RTC1_ACK2; + rtc_ack[2] = *NVR_RTC1_ACK3; + rtc_ack[3] = *NVR_RTC1_ACK4; + rtc_ack[4] = *NVR_RTC1_ACK5; + checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]); + if (checksum == (*NVR_RTC1_ACK_CHKSUM))//checksum1 true + { + /* Get information */ + RTCTempData->RTCTempK1 = rtc_ack[0]; + RTCTempData->RTCTempK2 = rtc_ack[1]; + RTCTempData->RTCTempK3 = rtc_ack[2]; + RTCTempData->RTCTempK4 = rtc_ack[3]; + RTCTempData->RTCTempK5 = rtc_ack[4]; + + /* Load data to ACKx register */ + RTC->ACK1 = rtc_ack[0]; + RTC->ACK2 = rtc_ack[1]; + RTC->ACK3 = rtc_ack[2]; + RTC->ACK4 = rtc_ack[3]; + RTC->ACK5 = rtc_ack[4]; + } + else + { + rtc_ack[0] = *NVR_RTC2_ACK1; + rtc_ack[1] = *NVR_RTC2_ACK2; + rtc_ack[2] = *NVR_RTC2_ACK3; + rtc_ack[3] = *NVR_RTC2_ACK4; + rtc_ack[4] = *NVR_RTC2_ACK5; + checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]); + if (checksum == (*NVR_RTC2_ACK_CHKSUM))//checksum2 true + { + /* Get information */ + RTCTempData->RTCTempK1 = rtc_ack[0]; + RTCTempData->RTCTempK2 = rtc_ack[1]; + RTCTempData->RTCTempK3 = rtc_ack[2]; + RTCTempData->RTCTempK4 = rtc_ack[3]; + RTCTempData->RTCTempK5 = rtc_ack[4]; + + /* Load data to ACKx register */ + RTC->ACK1 = rtc_ack[0]; + RTC->ACK2 = rtc_ack[1]; + RTC->ACK3 = rtc_ack[2]; + RTC->ACK4 = rtc_ack[3]; + RTC->ACK5 = rtc_ack[4]; + } + else + { + /* Get information */ + RTCTempData->RTCTempK1 = 20827; + RTCTempData->RTCTempK2 = 21496; + RTCTempData->RTCTempK3 = 22020; + RTCTempData->RTCTempK4 = 24517; + RTCTempData->RTCTempK5 = 25257; + + /* Load data to ACKx register */ + RTC->ACK1 = 20827; + RTC->ACK2 = 21496; + RTC->ACK3 = 22020; + RTC->ACK4 = 24517; + RTC->ACK5 = 25257; + + retval |= BIT3; + } + } + +/*-------------------------- RTC ACTI parameters -----------------------------*/ + rtc_acti = *NVR_RTC1_ACTI; + checksum = ~rtc_acti; + if (checksum == (*NVR_RTC1_ACTI_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACTI = rtc_acti; + /* Load data to ACKx register */ + RTC->ACTI = rtc_acti; + } + else + { + rtc_acti = *NVR_RTC2_ACTI; + checksum = ~rtc_acti; + if (checksum == (*NVR_RTC2_ACTI_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACTI = rtc_acti; + /* Load data to ACKx register */ + RTC->ACTI = rtc_acti; + } + else + { + /* Get information */ + RTCTempData->RTCACTI = 0x1800; + RTC->ACTI = 0x1800; + + retval |= BIT4; + } + } + +/*------------------------- RTC ACKTemp parameters ---------------------------*/ + rtc_acktemp = *NVR_RTC1_ACKTEMP; + checksum = ~rtc_acktemp; + if (checksum == (*NVR_RTC1_ACKTEMP_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACKTemp = rtc_acktemp; + /* Load data to ACKx register */ + RTC->ACKTEMP = rtc_acktemp; + } + else + { + rtc_acktemp = *NVR_RTC2_ACKTEMP; + checksum = ~rtc_acktemp; + if (checksum == (*NVR_RTC2_ACKTEMP_CHKSUM)) + { + /* Get information */ + RTCTempData->RTCACKTemp = rtc_acktemp; + /* Load data to ACKx register */ + RTC->ACKTEMP = rtc_acktemp; + } + else + { + /* Get information */ + RTCTempData->RTCACKTemp = 0x3C2800EC; + RTC->ACKTEMP = 0x3C2800EC; + + retval |= BIT5; + } + } +/*--------------------------------- ACF200 -----------------------------------*/ + RTCTempData->RTCACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000)); + RTC->ACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000)); + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + return retval; +} + +/** + * @breif Get Power/Clock Measure result. + * @param [out]MEAResult The pointer to struct NVR_PWRMEARES. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult) +{ + uint32_t avcc_data, dvcc_data, bgp_data, rcl_data, rch_data; + uint32_t checksum; + + avcc_data = *NVR_AVCC_MEA1; + dvcc_data = *NVR_DVCC_MEA1; + bgp_data = *NVR_BGP_MEA1; + rcl_data = *NVR_RCL_MEA1; + rch_data = *NVR_RCH_MEA1; + /* Calculate checksum1 */ + checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data); + if (checksum == (*NVR_PWR_CHECKSUM1)) + { + MEAResult->AVCCMEAResult = avcc_data; + MEAResult->DVCCMEAResult = dvcc_data; + MEAResult->BGPMEAResult = bgp_data; + MEAResult->RCLMEAResult = rcl_data; + MEAResult->RCHMEAResult = rch_data; + return 0; + } + + avcc_data = *NVR_AVCC_MEA2; + dvcc_data = *NVR_DVCC_MEA2; + bgp_data = *NVR_BGP_MEA2; + rcl_data = *NVR_RCL_MEA2; + rch_data = *NVR_RCH_MEA2; + /* Calculate checksum2 */ + checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data); + if (checksum == (*NVR_PWR_CHECKSUM2)) + { + MEAResult->AVCCMEAResult = avcc_data; + MEAResult->DVCCMEAResult = dvcc_data; + MEAResult->BGPMEAResult = bgp_data; + MEAResult->RCLMEAResult = rcl_data; + MEAResult->RCHMEAResult = rch_data; + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Get Chip ID. + * @param [out]ChipID The pointer to struct NVR_CHIPID. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetChipID(NVR_CHIPID *ChipID) +{ + uint32_t id0, id1; + uint32_t checksum; + + id0 = *NVR_CHIP1_ID0; + id1 = *NVR_CHIP1_ID1; + /* Calculate checksum1 */ + checksum = ~(id0 + id1); + if (checksum == (*NVR_CHIP1_CHECKSUM)) + { + ChipID->ChipID0 = id0; + ChipID->ChipID1 = id1; + return 0; + } + + id0 = *NVR_CHIP2_ID0; + id1 = *NVR_CHIP2_ID1; + /* Calculate checksum2 */ + checksum = ~(id0 + id1); + if (checksum == (*NVR_CHIP2_CHECKSUM)) + { + ChipID->ChipID0 = id0; + ChipID->ChipID1 = id1; + return 0; + } + else + { + return 1; + } +} + +/** + * @breif Get LCD information. + * @param [out]LCDInfo The pointer to struct NVR_LCDINFO. + * @retval 0: Function succeeded. + 1: Function failed(Checksum error). + */ +uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo) +{ + uint32_t lcd_ldo, lcd_vol; + uint32_t checksum; + + lcd_ldo = *NVR_LCD_LDO1; + lcd_vol = *NVR_LCD_VOL1; + /* Calculate checksum1 */ + checksum = ~(lcd_ldo + lcd_vol); + if (checksum == (*NVR_LCD_CHECKSUM1)) + { + LCDInfo->MEALCDLDO = lcd_ldo; + LCDInfo->MEALCDVol = lcd_vol; + return 0; + } + + lcd_ldo = *NVR_LCD_LDO2; + lcd_vol = *NVR_LCD_VOL2; + /* Calculate checksum2 */ + checksum = ~(lcd_ldo + lcd_vol); + if (checksum == (*NVR_LCD_CHECKSUM2)) + { + LCDInfo->MEALCDLDO = lcd_ldo; + LCDInfo->MEALCDVol = lcd_vol; + return 0; + } + else + { + return 1; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c new file mode 100644 index 0000000000..552365ff6e --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file lib_cortex.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Cortex module driver. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_cortex.h" +#include "core_cm0.h" + +/** + * @brief 1. Clears Pending of a device specific External Interrupt. + * 2. Sets Priority of a device specific External Interrupt. + * 3. Enables a device specific External Interrupt. + * @param IRQn: External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to target.h file) + * @param Priority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @retval None + */ +void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority)); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(IRQn); + /* Set Interrupt Priority */ + NVIC_SetPriority(IRQn, Priority); + /* Enable Interrupt in NVIC */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly before calling it. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Enable interrupt in NVIC */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Disable interrupt in NVIC */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void CORTEX_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Gets the Pending bit of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval 0 Interrupt status is not pending. + 1 Interrupt status is pending. + */ +uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Get priority for Cortex-M0 system or device specific interrupts */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval None + */ +void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn)); + /* Clear interrupt pending */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h)) + * @retval Interrupt Priority. Value is aligned automatically to the implemented + * priority bits of the microcontroller. + */ +uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M0 system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete target Devices IRQ Channels list, please refer to target.h file) + * @param Priority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @retval None + */ +void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority)); + /* Get priority for Cortex-M0 system or device specific interrupts */ + NVIC_SetPriority(IRQn, Priority); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum) +{ + return SysTick_Config(TicksNum); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c new file mode 100644 index 0000000000..d8dcc96787 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/system_target.c @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file system_target.c + * @author Application Team + * @version V1.1.0 + * @date 2019-10-28 + * @brief system source file. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "target.h" + +#define NVR_REGINFOCOUNT1 (0x80400) +#define NVR_REGINFOBAKOFFSET (0x100) + +/** + * @brief Setup the microcontroller system + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + uint32_t i,nCount,nValue,nAddress,nChecksum; + + nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1; + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4)) + { + nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET); + nChecksum = nCount; + nChecksum = ~nChecksum; + if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4)) + { + while(1); + } + } + + for(i=0; i=0x40014800) && (nAddress<=0x40015000)) + { + RTC_WriteRegisters(nAddress, &nValue, 1); + } + else + { + *(__IO uint32_t *)(nAddress) = nValue; + } + } +} + +/** + * @brief Initializes registers. + * @param None + * @retval None + */ +void SystemUpdate(void) +{ + +} + + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h new file mode 100644 index 0000000000..94212eb87a --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h new file mode 100644 index 0000000000..2d9db15a5d --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h b/bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h new file mode 100644 index 0000000000..f929bba07b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..4a6b5d6683 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return (__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); +#else + return (0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" : : "r"(control)); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psp\n" : "=r"(result)); + return (result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack)); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msp\n" : "=r"(result)); + return (result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack)); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" : "=r"(result)); + return (result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" : : "r"(priMask)); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri_max" : "=r"(result)); + return (result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile("MSR basepri, %0" : : "r"(value)); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask)); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile("VMRS %0, fpscr" : "=r"(result)); + return (result); +#else + return (0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr)); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/Vango_V85xx/Libraries/CMSIS/core_cmInstr.h b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..1c0b6f6b97 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/CMSIS/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + + /** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ + #define __RBIT __rbit + + + /** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + + /** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + + /** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + + /** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXB(value, ptr) __strex(value, ptr) + + + /** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXH(value, ptr) __strex(value, ptr) + + + /** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXW(value, ptr) __strex(value, ptr) + + + /** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ + #define __CLREX __clrex + + + /** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ + #define __SSAT __ssat + + + /** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ + #define __USAT __usat + + + /** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ + #define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2)); + return (op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr)); + return (result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr)); + return (result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr)); + return (result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return (result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return (result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return (result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile("clz %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/Vango_V85xx/Libraries/SConscript b/bsp/Vango_V85xx/Libraries/SConscript new file mode 100644 index 0000000000..7cbb5e7d9d --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/SConscript @@ -0,0 +1,30 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Glob('VangoV85xx_standard_peripheral/Source/*.c') +src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c'] +src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c'] +src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_cortex.c'] +src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S'] +if rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/CMSIS/Vango/V85xx/Source/Keil5/startup_target.S'] + +path = [ + cwd + '/CMSIS/Vango/V85xx/Include', + cwd + '/CMSIS', + cwd + '/VangoV85xx_standard_peripheral/Include',] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85xx','USE_TARGET_DRIVER'] + +group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h new file mode 100644 index 0000000000..1b82cb6b4c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc.h @@ -0,0 +1,249 @@ +/** + ****************************************************************************** + * @file lib_adc.h + * @author Application Team + * @version V4.6.0 + * @date 2019-06-18 + * @brief ADC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ADC_H +#define __LIB_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t TrigMode; + uint32_t ConvMode; + uint32_t ClockSource; + uint32_t ClockDivider; + uint32_t Channel; +} ADCInitType; + +//TrigMode +#define ADC_TRIGMODE_AUTO 0 +#define ADC_TRIGMODE_MANUAL ANA_ADCCTRL_MTRIG +#define IS_ADC_TRIGMODE(__TRIGMODE__) (((__TRIGMODE__) == ADC_TRIGMODE_AUTO) ||\ + ((__TRIGMODE__) == ADC_TRIGMODE_MANUAL)) + +//ConvMode +#define ADC_CONVMODE_SINGLECHANNEL 0 +#define ADC_CONVMODE_MULTICHANNEL 1 +#define IS_ADC_CONVMODE(__CONVMODE__) (((__CONVMODE__) == ADC_CONVMODE_SINGLECHANNEL) ||\ + ((__CONVMODE__) == ADC_CONVMODE_MULTICHANNEL)) + +//ClockSource +#define ADC_CLKSRC_RCH 0 +#define ADC_CLKSRC_PLLL ANA_ADCCTRL_CLKSEL +#define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\ + ((__CLKSRC__) == ADC_CLKSRC_PLLL)) + +//TrigSource +#define ADC_TRIGSOURCE_OFF ANA_ADCCTRL_AEN_OFF +#define ADC_TRIGSOURCE_TIM0 ANA_ADCCTRL_AEN_TMR0 +#define ADC_TRIGSOURCE_TIM1 ANA_ADCCTRL_AEN_TMR1 +#define ADC_TRIGSOURCE_TIM2 ANA_ADCCTRL_AEN_TMR2 +#define ADC_TRIGSOURCE_TIM3 ANA_ADCCTRL_AEN_TMR3 +#define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM0) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM1) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM2) ||\ + ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TIM3)) + +//ClockDivider +#define ADC_CLKDIV_1 ANA_ADCCTRL_CLKDIV_1 +#define ADC_CLKDIV_2 ANA_ADCCTRL_CLKDIV_2 +#define ADC_CLKDIV_3 ANA_ADCCTRL_CLKDIV_3 +#define ADC_CLKDIV_4 ANA_ADCCTRL_CLKDIV_4 +#define ADC_CLKDIV_5 ANA_ADCCTRL_CLKDIV_5 +#define ADC_CLKDIV_6 ANA_ADCCTRL_CLKDIV_6 +#define ADC_CLKDIV_7 ANA_ADCCTRL_CLKDIV_7 +#define ADC_CLKDIV_8 ANA_ADCCTRL_CLKDIV_8 +#define ADC_CLKDIV_9 ANA_ADCCTRL_CLKDIV_9 +#define ADC_CLKDIV_10 ANA_ADCCTRL_CLKDIV_10 +#define ADC_CLKDIV_11 ANA_ADCCTRL_CLKDIV_11 +#define ADC_CLKDIV_12 ANA_ADCCTRL_CLKDIV_12 +#define ADC_CLKDIV_13 ANA_ADCCTRL_CLKDIV_13 +#define ADC_CLKDIV_14 ANA_ADCCTRL_CLKDIV_14 +#define ADC_CLKDIV_15 ANA_ADCCTRL_CLKDIV_15 +#define ADC_CLKDIV_16 ANA_ADCCTRL_CLKDIV_16 +#define IS_ADC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == ADC_CLKDIV_1) ||\ + ((__CLKDIV__) == ADC_CLKDIV_2) ||\ + ((__CLKDIV__) == ADC_CLKDIV_3) ||\ + ((__CLKDIV__) == ADC_CLKDIV_4) ||\ + ((__CLKDIV__) == ADC_CLKDIV_5) ||\ + ((__CLKDIV__) == ADC_CLKDIV_6) ||\ + ((__CLKDIV__) == ADC_CLKDIV_7) ||\ + ((__CLKDIV__) == ADC_CLKDIV_8) ||\ + ((__CLKDIV__) == ADC_CLKDIV_9) ||\ + ((__CLKDIV__) == ADC_CLKDIV_10) ||\ + ((__CLKDIV__) == ADC_CLKDIV_11) ||\ + ((__CLKDIV__) == ADC_CLKDIV_12) ||\ + ((__CLKDIV__) == ADC_CLKDIV_13) ||\ + ((__CLKDIV__) == ADC_CLKDIV_14) ||\ + ((__CLKDIV__) == ADC_CLKDIV_15) ||\ + ((__CLKDIV__) == ADC_CLKDIV_16)) + +//Channel +#define ADC_CHANNEL0 0 +#define ADC_CHANNEL1 1 +#define ADC_CHANNEL2 2 +#define ADC_CHANNEL3 3 +#define ADC_CHANNEL4 4 +#define ADC_CHANNEL5 5 +#define ADC_CHANNEL6 6 +#define ADC_CHANNEL7 7 +#define ADC_CHANNEL8 8 +#define ADC_CHANNEL9 9 +#define ADC_CHANNEL10 10 +#define ADC_CHANNEL11 11 + +#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL0) ||\ + ((__CHANNEL__) == ADC_CHANNEL1) ||\ + ((__CHANNEL__) == ADC_CHANNEL2) ||\ + ((__CHANNEL__) == ADC_CHANNEL3) ||\ + ((__CHANNEL__) == ADC_CHANNEL4) ||\ + ((__CHANNEL__) == ADC_CHANNEL5) ||\ + ((__CHANNEL__) == ADC_CHANNEL6) ||\ + ((__CHANNEL__) == ADC_CHANNEL7) ||\ + ((__CHANNEL__) == ADC_CHANNEL8) ||\ + ((__CHANNEL__) == ADC_CHANNEL9) ||\ + ((__CHANNEL__) == ADC_CHANNEL10) ||\ + ((__CHANNEL__) == ADC_CHANNEL11)) + +//INTMask +#define ADC_INT_AUTODONE ANA_INTEN_INTEN1 +#define ADC_INT_MANUALDONE ANA_INTEN_INTEN0 +#define ADC_INT_Msk (ADC_INT_AUTODONE | ADC_INT_MANUALDONE) +#define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0U) &&\ + (((__INT__) & ~ADC_INT_Msk) == 0U)) + +//ScaleDown +#define ADC_SCA_NONE 0 +#define ADC_SCA_DIV2 ANA_ADCCTRL_CICSCA +#define IS_ADC_SCA(__SCA__) (((__SCA__) == ADC_SCA_NONE) || ((__SCA__) == ADC_SCA_DIV2)) + +//Skip +#define ADC_SKIP_4 ANA_ADCCTRL_CICSKIP_4 +#define ADC_SKIP_5 ANA_ADCCTRL_CICSKIP_5 +#define ADC_SKIP_6 ANA_ADCCTRL_CICSKIP_6 +#define ADC_SKIP_7 ANA_ADCCTRL_CICSKIP_7 +#define ADC_SKIP_0 ANA_ADCCTRL_CICSKIP_0 +#define ADC_SKIP_1 ANA_ADCCTRL_CICSKIP_1 +#define ADC_SKIP_2 ANA_ADCCTRL_CICSKIP_2 +#define ADC_SKIP_3 ANA_ADCCTRL_CICSKIP_3 +#define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_4) ||\ + ((__SKIP__) == ADC_SKIP_5) ||\ + ((__SKIP__) == ADC_SKIP_6) ||\ + ((__SKIP__) == ADC_SKIP_7) ||\ + ((__SKIP__) == ADC_SKIP_0) ||\ + ((__SKIP__) == ADC_SKIP_1) ||\ + ((__SKIP__) == ADC_SKIP_2) ||\ + ((__SKIP__) == ADC_SKIP_3)) + +//DSRSelection +#define ADC_SDRSEL_DIV512 ANA_ADCCTRL_DSRSEL_512 +#define ADC_SDRSEL_DIV256 ANA_ADCCTRL_DSRSEL_256 +#define ADC_SDRSEL_DIV128 ANA_ADCCTRL_DSRSEL_128 +#define ADC_SDRSEL_DIV64 ANA_ADCCTRL_DSRSEL_64 +#define IS_ADC_SDR(__SDR__) (((__SDR__) == ADC_SDRSEL_DIV512) ||\ + ((__SDR__) == ADC_SDRSEL_DIV256) ||\ + ((__SDR__) == ADC_SDRSEL_DIV128) ||\ + ((__SDR__) == ADC_SDRSEL_DIV64)) + +typedef struct +{ + float VDDVoltage; + float BATRTCVoltage; + float Temperature; +} ADC_CalResType; +//Division +#define ADC_BAT_CAPDIV (ANA_REG1_GDE4) +#define ADC_BAT_RESDIV (ANA_REG1_RESDIV) + +#define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\ + ((__BATDIV__) == ADC_BAT_RESDIV)) + +/* ADC_GetVoltage */ +//Mode +#define ADC_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None +#define ADC_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive +#define ADC_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive +#define ADC_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive +#define ADC_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive +#define ADC_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive +#define ADC_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive +#define ADC_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None +#define ADC_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive +#define ADC_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive +#define ADC_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive +#define ADC_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive +#define ADC_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive +#define ADC_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive +#define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_EXTERNAL_NODIV) ||\ + ((__MODE__) == ADC_3V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == ADC_3V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == ADC_3V_VDD_RESDIV) ||\ + ((__MODE__) == ADC_3V_VDD_CAPDIV) ||\ + ((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\ + ((__MODE__) == ADC_3V_BATRTC_CAPDIV) ||\ + ((__MODE__) == ADC_5V_EXTERNAL_NODIV) ||\ + ((__MODE__) == ADC_5V_EXTERNAL_RESDIV) ||\ + ((__MODE__) == ADC_5V_EXTERNAL_CAPDIV) ||\ + ((__MODE__) == ADC_5V_VDD_RESDIV) ||\ + ((__MODE__) == ADC_5V_VDD_CAPDIV) ||\ + ((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\ + ((__MODE__) == ADC_5V_BATRTC_CAPDIV)) + +/* Exported Functions ------------------------------------------------------- */ +/* ADC Exported Functions Group1: + (De)Initialization -------------------------*/ +void ADC_DeInit(void); +void ADC_StructInit(ADCInitType* ADC_InitStruct); +void ADC_Init(ADCInitType* ADC_InitStruct); +/* ADC Exported Functions Group2: + Get NVR Info, Calculate datas --------------*/ +uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage); +uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults); +uint32_t ADC_GetTemperature(ADC_CalResType *CalResults); +/* ADC Exported Functions Group3: + Interrupt (flag) ---------------------------*/ +int16_t ADC_GetADCConversionValue(uint32_t Channel); +void ADC_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t ADC_GetAutoDoneFlag(void); +uint8_t ADC_GetManualDoneFlag(void); +void ADC_ClearAutoDoneFlag(void); +void ADC_ClearManualDoneFlag(void); +/* ADC Exported Functions Group4: + MISC Configuration -------------------------*/ +uint32_t ADC_Cmd(uint32_t NewState); +void ADC_StartManual(void); +void ADC_WaitForManual(void); +void ADC_TrigSourceConfig(uint32_t TrigSource); +void ADC_RESDivisionCmd(uint32_t NewState); +void ADC_CAPDivisionCmd(uint32_t NewState); +//CIC Control +void ADC_CICAlwaysOnCmd(uint32_t NewState); +void ADC_CICINVCmd(uint32_t NewState); +void ADC_CICScaleDownConfig(uint32_t ScaleDown); +void ADC_CICSkipConfig(uint32_t Skip); +void ADC_CICDownSamRateConfig(uint32_t DSRSelection); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ADC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h new file mode 100644 index 0000000000..b9b8da41a3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_adc_tiny.h @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file lib_adc_tiny.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ADC_TINY library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ADC_TINY_H +#define __LIB_ADC_TINY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t SignalSel; + uint32_t ADTREF1; + uint32_t ADTREF2; + uint32_t ADTREF3; +} TADCInitType; + +//SelADT +#define ADCTINY_SIGNALSEL_IOE6 0 +#define ADCTINY_SIGNALSEL_IOE7 ANA_REGF_SELADT +#define IS_ADCTINY_SELADT(__SELADT__) (((__SELADT__) == ADCTINY_SIGNALSEL_IOE6) ||\ + ((__SELADT__) == ADCTINY_SIGNALSEL_IOE7)) + +//ADTREF1 +#define ADCTINY_REF1_0_9 0 +#define ADCTINY_REF1_0_7 ANA_REGF_ADTREF1SEL +#define IS_ADCTINY_ADTREF1(__ADTREF1__) (((__ADTREF1__) == ADCTINY_REF1_0_9) ||\ + ((__ADTREF1__) == ADCTINY_REF1_0_7)) + +//ADTREF2 +#define ADCTINY_REF2_1_8 0 +#define ADCTINY_REF2_1_6 ANA_REGF_ADTREF2SEL +#define IS_ADCTINY_ADTREF2(__ADTREF2__) (((__ADTREF2__) == ADCTINY_REF2_1_8) ||\ + ((__ADTREF2__) == ADCTINY_REF2_1_6)) + +//ADTREF3 +#define ADCTINY_REF3_2_7 0 +#define ADCTINY_REF3_2_5 ANA_REGF_ADTREF3SEL +#define IS_ADCTINY_ADTREF3(__ADTREF3__) (((__ADTREF3__) == ADCTINY_REF3_2_7) ||\ + ((__ADTREF3__) == ADCTINY_REF3_2_5)) + +//THSel +#define ADCTINY_THSEL_0 ANA_MISC_TADCTH_0 +#define ADCTINY_THSEL_1 ANA_MISC_TADCTH_1 +#define ADCTINY_THSEL_2 ANA_MISC_TADCTH_2 +#define ADCTINY_THSEL_3 ANA_MISC_TADCTH_3 +#define IS_ADCTINY_THSEL(__THSEL__) (((__THSEL__) == ADCTINY_THSEL_0) ||\ + ((__THSEL__) == ADCTINY_THSEL_1) ||\ + ((__THSEL__) == ADCTINY_THSEL_2) ||\ + ((__THSEL__) == ADCTINY_THSEL_3)) + +/* Exported Functions ------------------------------------------------------- */ +void TADC_DeInit(void); +void TADC_StructInit(TADCInitType* TADC_InitStruct); +void TADC_Init(TADCInitType* TADC_InitStruct); +void TADC_Cmd(uint32_t NewState); +uint8_t TADC_GetOutput(void); +void TADC_IntTHConfig(uint32_t THSel); +void TADC_INTConfig(uint32_t NewState); +uint8_t TADC_GetINTStatus(void); +void TADC_ClearINTStatus(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ADC_TINY_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_ana.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_ana.h new file mode 100644 index 0000000000..0a3a073074 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_ana.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file lib_ana.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Analog library. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ +#ifndef __LIB_ANA_H +#define __LIB_ANA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/***** StatusMask (ANA_GetStatus) *****/ +#define ANA_STATUS_AVCCLV ANA_COMPOUT_AVCCLV +#define ANA_STATUS_VDCINDROP ANA_COMPOUT_VDCINDROP +#define ANA_STATUS_VDDALARM ANA_COMPOUT_VDDALARM +#define ANA_STATUS_COMP2 ANA_COMPOUT_COMP2 +#define ANA_STATUS_COMP1 ANA_COMPOUT_COMP1 +#define ANA_STATUS_LOCKL ANA_COMPOUT_LOCKL +#define ANA_STATUS_LOCKH ANA_COMPOUT_LOCKH + +/***** IntMask (ANA_GetINTStatus / ANA_ClearINTStatus / ANA_INTConfig) *****/ +#define ANA_INT_TADC_OVER ANA_INTSTS_INTSTS13 +#define ANA_INT_REGERR ANA_INTSTS_INTSTS12 +#define ANA_INT_SME ANA_INTSTS_INTSTS11 +#define ANA_INT_AVCCLV ANA_INTSTS_INTSTS10 +#define ANA_INT_VDCINDROP ANA_INTSTS_INTSTS8 +#define ANA_INT_VDDALARM ANA_INTSTS_INTSTS7 +#define ANA_INT_COMP2 ANA_INTSTS_INTSTS3 +#define ANA_INT_COMP1 ANA_INTSTS_INTSTS2 +#define ANA_INT_ADCA ANA_INTSTS_INTSTS1 +#define ANA_INT_ADCM ANA_INTSTS_INTSTS0 +#define ANA_INT_Msk (0x3DEFUL) + +/* Private macros ------------------------------------------------------------*/ +#define IS_ANA_STATUS(__STATUS__) (((__STATUS__) == ANA_STATUS_AVCCLV) ||\ + ((__STATUS__) == ANA_STATUS_VDCINDROP) ||\ + ((__STATUS__) == ANA_STATUS_VDDALARM) ||\ + ((__STATUS__) == ANA_STATUS_COMP2) ||\ + ((__STATUS__) == ANA_STATUS_COMP1) ||\ + ((__STATUS__) == ANA_STATUS_LOCKL) ||\ + ((__STATUS__) == ANA_STATUS_LOCKH)) + +#define IS_ANA_INTSTSR(__INTSTSR__) (((__INTSTSR__) == ANA_INT_TADC_OVER) ||\ + ((__INTSTSR__) == ANA_INT_REGERR) ||\ + ((__INTSTSR__) == ANA_INT_SME) ||\ + ((__INTSTSR__) == ANA_INT_AVCCLV) ||\ + ((__INTSTSR__) == ANA_INT_VDCINDROP) ||\ + ((__INTSTSR__) == ANA_INT_VDDALARM) ||\ + ((__INTSTSR__) == ANA_INT_COMP2) ||\ + ((__INTSTSR__) == ANA_INT_COMP1) ||\ + ((__INTSTSR__) == ANA_INT_ADCA) ||\ + ((__INTSTSR__) == ANA_INT_ADCM)) + +#define IS_ANA_INTSTSC(__INTSTSC__) ((((__INTSTSC__) & ANA_INT_Msk) != 0U) &&\ + (((__INTSTSC__) & ~ANA_INT_Msk) == 0U)) + +#define IS_ANA_INT(__INT__) IS_ANA_INTSTSC(__INT__) + +/* Exported Functions ------------------------------------------------------- */ +uint8_t ANA_GetStatus(uint32_t StatusMask); +uint8_t ANA_GetINTStatus(uint32_t IntMask); +void ANA_ClearINTStatus(uint32_t IntMask); +void ANA_INTConfig(uint32_t IntMask, uint32_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ANA_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_clk.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_clk.h new file mode 100644 index 0000000000..5c0c2d4753 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_clk.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file lib_clk.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Clock library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_CLK_H +#define __LIB_CLK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* PLLL Configure */ +typedef struct +{ + uint32_t Source; + uint32_t State; + uint32_t Frequency; +} PLLL_ConfTypeDef; + +/* PLLH Configure */ +typedef struct +{ + uint32_t Source; + uint32_t State; + uint32_t Frequency; +} PLLH_ConfTypeDef; + +/* RCH Configure */ +typedef struct +{ + uint32_t State; +} RCH_ConfTypeDef; + +/* XTALH Configure */ +typedef struct +{ + uint32_t State; +} XTALH_ConfTypeDef; + +/* RTCCLK Configure */ +typedef struct +{ + uint32_t Source; + uint32_t Divider; +} RTCCLK_ConfTypeDef; + +/* HCLK Configure */ +typedef struct +{ + uint32_t Divider; /* 1 ~ 256 */ +} HCLK_ConfTypeDef; + +/* PCLK Configure */ +typedef struct +{ + uint32_t Divider; /* 1 ~ 256 */ +} PCLK_ConfTypeDef; + +/* Clock Configure */ +typedef struct +{ + uint32_t ClockType; /* The clock to be configured */ + + uint32_t AHBSource; + + PLLL_ConfTypeDef PLLL; + + PLLH_ConfTypeDef PLLH; + + XTALH_ConfTypeDef XTALH; + + RTCCLK_ConfTypeDef RTCCLK; + + HCLK_ConfTypeDef HCLK; + + PCLK_ConfTypeDef PCLK; + +} CLK_InitTypeDef; + +/***** ClockType *****/ +#define CLK_TYPE_Msk (0xFFUL) +#define CLK_TYPE_ALL CLK_TYPE_Msk +#define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */ +#define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */ +#define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */ +#define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */ +#define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */ +#define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */ +#define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */ + +/***** AHBSource *****/ +#define CLK_AHBSEL_6_5MRC MISC2_CLKSEL_CLKSEL_RCOH +#define CLK_AHBSEL_6_5MXTAL MISC2_CLKSEL_CLKSEL_XOH +#define CLK_AHBSEL_HSPLL MISC2_CLKSEL_CLKSEL_PLLH +#define CLK_AHBSEL_RTCCLK MISC2_CLKSEL_CLKSEL_RTCCLK +#define CLK_AHBSEL_LSPLL MISC2_CLKSEL_CLKSEL_PLLL + +/***** PLLL_ConfTypeDef PLLL *****/ +/* PLLL.Source */ +#define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL +#define CLK_PLLLSRC_XTALL (0) +/* PLLL.State */ +#define CLK_PLLL_ON ANA_REG3_PLLLPDN +#define CLK_PLLL_OFF (0) +/* PLLL.Frequency */ +#define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M +#define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M +#define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M +#define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M +#define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M +#define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K +#define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K +#define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K + +/***** PLLH_ConfTypeDef PLLH *****/ +/* PLLH.Source */ +#define CLK_PLLHSRC_RCH (0) +#define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL +/* PLLH.State */ +#define CLK_PLLH_ON ANA_REG3_PLLHPDN +#define CLK_PLLH_OFF (0) +/* PLLH.Frequency */ +#define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2 +#define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5 +#define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3 +#define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5 +#define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4 +#define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5 +#define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5 +#define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5 +#define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6 +#define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5 +#define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7 +#define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5 + +/* XTALH_ConfTypeDef XTALH */ +/* XTALH.State */ +#define CLK_XTALH_ON ANA_REG3_XOHPDN +#define CLK_XTALH_OFF (0) + +/* RTCCLK Configure */ +/* RTCCLK.Source */ +#define CLK_RTCCLKSRC_XTALL (0) +#define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCLK_SEL) +/* RTCCLK.Divider */ +#define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0) +#define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1) + +//AHB Periphral +#define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA +#define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO +#define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD +#define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT +#define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \ + |MISC2_HCLKEN_GPIO \ + |MISC2_HCLKEN_LCD \ + |MISC2_HCLKEN_CRYPT) + +//APB Periphral +#define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA +#define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C +#define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1 +#define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0 +#define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1 +#define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2 +#define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3 +#define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4 +#define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5 +#define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160 +#define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161 +#define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER +#define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC +#define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2 +#define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU +#define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC +#define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA +#define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0 +#define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1 +#define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2 +#define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \ + |MISC2_PCLKEN_I2C \ + |MISC2_PCLKEN_SPI1 \ + |MISC2_PCLKEN_UART0 \ + |MISC2_PCLKEN_UART1 \ + |MISC2_PCLKEN_UART2 \ + |MISC2_PCLKEN_UART3 \ + |MISC2_PCLKEN_UART4 \ + |MISC2_PCLKEN_UART5 \ + |MISC2_PCLKEN_ISO78160 \ + |MISC2_PCLKEN_ISO78161 \ + |MISC2_PCLKEN_TIMER \ + |MISC2_PCLKEN_MISC \ + |MISC2_PCLKEN_MISC2 \ + |MISC2_PCLKEN_PMU \ + |MISC2_PCLKEN_RTC \ + |MISC2_PCLKEN_ANA \ + |MISC2_PCLKEN_U32K0 \ + |MISC2_PCLKEN_U32K1 \ + |MISC2_PCLKEN_SPI2) + +/***** PLLStatus (CLK_GetPLLLockStatus) *****/ +#define CLK_STATUS_LOCKL ANA_COMPOUT_LOCKL +#define CLK_STATUS_LOCKH ANA_COMPOUT_LOCKH + + +/* Private macros ------------------------------------------------------------*/ +#define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_Msk) != 0UL) &&\ + (((__TYPE__) & ~CLK_TYPE_Msk) == 0UL)) + +#define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\ + ((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\ + ((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\ + ((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\ + ((__AHBSRC__) == CLK_AHBSEL_LSPLL)) + +#define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\ + ((__PLLLSRC__) == CLK_PLLLSRC_XTALL)) + +#define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\ + ((__PLLLSTA__) == CLK_PLLL_OFF)) + +#define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\ + ((__PLLLFRQ__) == CLK_PLLL_0_2048MHz)) + +#define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\ + ((__PLLHSRC__) == CLK_PLLHSRC_XTALH)) + +#define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\ + ((__PLLHSTA__) == CLK_PLLH_OFF)) + +#define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\ + ((__PLLHSRC__) == CLK_PLLH_49_152MHz)) + +#define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\ + ((__XTALHSTA__) == CLK_XTALH_OFF)) + +#define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\ + ((__RTCSRC__) == CLK_RTCCLKSRC_RCL)) + +#define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\ + ((__RTCDIV__) == CLK_RTCCLKDIV_4)) + +#define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\ + ((__HCLKDIV__) < 257UL)) + +#define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\ + ((__PCLKDIV__) < 257UL)) + +#define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\ + (((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL)) + +#define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\ + (((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL)) + +#define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_COMPOUT_LOCKL) ||\ + ((__PLLLOCK__) == ANA_COMPOUT_LOCKH)) +/* Exported Functions ------------------------------------------------------- */ +/* CLK Exported Functions Group1: + Initialization and functions ---------------*/ +void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); + +/* CLK Exported Functions Group2: + Peripheral Control -------------------------*/ +void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState); +void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState); +/* CLK Exported Functions Group3: + Get clock/configuration information --------*/ +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLKFreq(void); +void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); +uint8_t CLK_GetXTALHStatus(void); +uint8_t CLK_GetXTALLStatus(void); +uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CLK_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_comp.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_comp.h new file mode 100644 index 0000000000..f99230f91d --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_comp.h @@ -0,0 +1,97 @@ +/** + ****************************************************************************** + * @file lib_comp.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief COMP library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_COMP_H +#define __LIB_COMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* Macros --------------------------------------------------------------------*/ + +/***** COMP_DEBConfig *****/ +//COMPx +#define COMP_1 (0x00U) +#define COMP_2 (0x02U) +#define IS_COMP(__COMP__) (((__COMP__) == COMP_1) || ((__COMP__) == COMP_2)) +//Debounce +#define COMP_DEB_0 ANA_CTRL_CMP1DEB_0 +#define COMP_DEB_1 ANA_CTRL_CMP1DEB_1 +#define COMP_DEB_2 ANA_CTRL_CMP1DEB_2 +#define COMP_DEB_3 ANA_CTRL_CMP1DEB_3 +#define IS_COMP_DEB(__DEB__) (((__DEB__) == COMP_DEB_0) ||\ + ((__DEB__) == COMP_DEB_1) ||\ + ((__DEB__) == COMP_DEB_2) ||\ + ((__DEB__) == COMP_DEB_3)) + +/***** Mode (COMP_ModeConfig) *****/ +#define COMP_MODE_OFF ANA_CTRL_COMP1_SEL_0 +#define COMP_MODE_RISING ANA_CTRL_COMP1_SEL_1 +#define COMP_MODE_FALLING ANA_CTRL_COMP1_SEL_2 +#define COMP_MODE_BOTH ANA_CTRL_COMP1_SEL_3 +#define IS_COMP_MODE(__MODE__) (((__MODE__) == COMP_MODE_OFF) ||\ + ((__MODE__) == COMP_MODE_RISING) ||\ + ((__MODE__) == COMP_MODE_FALLING) ||\ + ((__MODE__) == COMP_MODE_BOTH)) + +/***** SourceSelect (COMP_ConfigSignalSource) *****/ +#define COMP_SIGNALSRC_P_TO_REF ANA_REG2_CMP1_SEL_0 +#define COMP_SIGNALSRC_N_TO_REF ANA_REG2_CMP1_SEL_1 +#define COMP_SIGNALSRC_P_TO_N ANA_REG2_CMP1_SEL_2 +#define IS_COMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_REF) ||\ + ((__SIGNALSRC__) == COMP_SIGNALSRC_N_TO_REF) ||\ + ((__SIGNALSRC__) == COMP_SIGNALSRC_P_TO_N)) + +/***** REFSelect (COMP_ConfigREF) *****/ +#define COMP_REF_VREF (0) +#define COMP_REF_BGPREF ANA_REG2_REFSEL_CMP1 +#define IS_COMP_REF(__REF__) (((__REF__) == COMP_REF_VREF) ||\ + ((__REF__) == COMP_REF_BGPREF)) + +/***** BiasSel (COMP_BiasConfig) *****/ +#define COMP_BIAS_20nA ANA_REG5_IT_CMP1_0 +#define COMP_BIAS_100nA ANA_REG5_IT_CMP1_1 +#define COMP_BIAS_500nA ANA_REG5_IT_CMP1_2 +#define IS_COMP_BIAS(__BIAS__) (((__BIAS__) == COMP_BIAS_20nA) ||\ + ((__BIAS__) == COMP_BIAS_100nA)||\ + ((__BIAS__) == COMP_BIAS_500nA)) + +/* Exported Functions ------------------------------------------------------- */ + +void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce); +void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode); +void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect); +void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect); +void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel); + +void COMP_INTConfig(uint32_t COMPx, uint32_t NewState); +uint8_t COMP_GetINTStatus(uint32_t COMPx); +void COMP_ClearINTStatus(uint32_t COMPx); + +void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState); +void COMP_Cmd(uint32_t COMPx, uint32_t NewState); + +uint32_t COMP_GetCNTValue(uint32_t COMPx); +void COMP_ClearCNTValue(uint32_t COMPx); +uint8_t COMP1_GetOutputLevel(void); +uint8_t COMP2_GetOutputLevel(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_COMP_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_crypt.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_crypt.h new file mode 100644 index 0000000000..071f098ccf --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_crypt.h @@ -0,0 +1,85 @@ +/** + ****************************************************************************** + * @file lib_crypt.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief CRYPT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_CRYPT_H +#define __LIB_CRYPT_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//Length +#define CRYPT_LENGTH_32 CRYPT_CTRL_LENGTH_32 +#define CRYPT_LENGTH_64 CRYPT_CTRL_LENGTH_64 +#define CRYPT_LENGTH_96 CRYPT_CTRL_LENGTH_96 +#define CRYPT_LENGTH_128 CRYPT_CTRL_LENGTH_128 +#define CRYPT_LENGTH_160 CRYPT_CTRL_LENGTH_160 +#define CRYPT_LENGTH_192 CRYPT_CTRL_LENGTH_192 +#define CRYPT_LENGTH_224 CRYPT_CTRL_LENGTH_224 +#define CRYPT_LENGTH_256 CRYPT_CTRL_LENGTH_256 +#define CRYPT_LENGTH_288 CRYPT_CTRL_LENGTH_288 +#define CRYPT_LENGTH_320 CRYPT_CTRL_LENGTH_320 +#define CRYPT_LENGTH_352 CRYPT_CTRL_LENGTH_352 +#define CRYPT_LENGTH_384 CRYPT_CTRL_LENGTH_384 +#define CRYPT_LENGTH_416 CRYPT_CTRL_LENGTH_416 +#define CRYPT_LENGTH_448 CRYPT_CTRL_LENGTH_448 +#define CRYPT_LENGTH_480 CRYPT_CTRL_LENGTH_480 +#define CRYPT_LENGTH_512 CRYPT_CTRL_LENGTH_512 +//Nostop +#define CRYPT_STOPCPU (0) +#define CRYPT_NOSTOPCPU CRYPT_CTRL_NOSTOP + +/* Private macros ------------------------------------------------------------*/ +#define IS_CRYPT_ADDR(__ADDR__) (((__ADDR__) < 0x8000) &&\ + (((__ADDR__) & 0x3U) == 0U)) + +#define IS_CRYPT_LENGTH(__LENGTH__) (((__LENGTH__) == CRYPT_LENGTH_32) ||\ + ((__LENGTH__) == CRYPT_LENGTH_64) ||\ + ((__LENGTH__) == CRYPT_LENGTH_32) ||\ + ((__LENGTH__) == CRYPT_LENGTH_96) ||\ + ((__LENGTH__) == CRYPT_LENGTH_128) ||\ + ((__LENGTH__) == CRYPT_LENGTH_160) ||\ + ((__LENGTH__) == CRYPT_LENGTH_192) ||\ + ((__LENGTH__) == CRYPT_LENGTH_224) ||\ + ((__LENGTH__) == CRYPT_LENGTH_256) ||\ + ((__LENGTH__) == CRYPT_LENGTH_288) ||\ + ((__LENGTH__) == CRYPT_LENGTH_320) ||\ + ((__LENGTH__) == CRYPT_LENGTH_352) ||\ + ((__LENGTH__) == CRYPT_LENGTH_384) ||\ + ((__LENGTH__) == CRYPT_LENGTH_416) ||\ + ((__LENGTH__) == CRYPT_LENGTH_448) ||\ + ((__LENGTH__) == CRYPT_LENGTH_480) ||\ + ((__LENGTH__) == CRYPT_LENGTH_512)) + +#define IS_CRYPT_NOSTOP(__NOSTOP__) (((__NOSTOP__) == CRYPT_STOPCPU) || ((__NOSTOP__) == CRYPT_NOSTOPCPU)) + +/* Exported Functions ------------------------------------------------------- */ +void CRYPT_AddressAConfig(uint16_t AddrA); +void CRYPT_AddressBConfig(uint16_t AddrB); +void CRYPT_AddressOConfig(uint16_t AddrO); +uint8_t CRYPT_GetCarryBorrowBit(void); +void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop); +void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop); +void CRYPT_StartSub(uint32_t Length, uint32_t Nostop); +void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop); +void CRYPT_WaitForLastOperation(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_CRYPT_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_dma.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_dma.h new file mode 100644 index 0000000000..1ecfbf0126 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_dma.h @@ -0,0 +1,253 @@ +/** + ****************************************************************************** + * @file lib_dma.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief DMA library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_DMA_H +#define __LIB_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//Channel +#define DMA_CHANNEL_0 0 +#define DMA_CHANNEL_1 1 +#define DMA_CHANNEL_2 2 +#define DMA_CHANNEL_3 3 + +typedef struct +{ + uint32_t DestAddr; /* destination address */ + uint32_t SrcAddr; /* source address */ + uint8_t FrameLen; /* Frame length */ + uint8_t PackLen; /* Package length */ + uint32_t ContMode; /* Continuous mode */ + uint32_t TransMode; /* Transfer mode */ + uint32_t ReqSrc; /* DMA request source */ + uint32_t DestAddrMode; /* Destination address mode */ + uint32_t SrcAddrMode; /* Source address mode */ + uint32_t TransSize; /* Transfer size mode */ +} DMA_InitType; +//ContMode +#define DMA_CONTMODE_ENABLE DMA_CTL_CONT +#define DMA_CONTMODE_DISABLE 0 +//TransMode +#define DMA_TRANSMODE_SINGLE 0 +#define DMA_TRANSMODE_PACK DMA_CTL_TMODE +//ReqSrc +#define DMA_REQSRC_SOFT DMA_CTL_DMASEL_SOFT +#define DMA_REQSRC_UART0TX DMA_CTL_DMASEL_UART0TX +#define DMA_REQSRC_UART0RX DMA_CTL_DMASEL_UART0RX +#define DMA_REQSRC_UART1TX DMA_CTL_DMASEL_UART1TX +#define DMA_REQSRC_UART1RX DMA_CTL_DMASEL_UART1RX +#define DMA_REQSRC_UART2TX DMA_CTL_DMASEL_UART2TX +#define DMA_REQSRC_UART2RX DMA_CTL_DMASEL_UART2RX +#define DMA_REQSRC_UART3TX DMA_CTL_DMASEL_UART3TX +#define DMA_REQSRC_UART3RX DMA_CTL_DMASEL_UART3RX +#define DMA_REQSRC_UART4TX DMA_CTL_DMASEL_UART4TX +#define DMA_REQSRC_UART4RX DMA_CTL_DMASEL_UART4RX +#define DMA_REQSRC_UART5TX DMA_CTL_DMASEL_UART5TX +#define DMA_REQSRC_UART5RX DMA_CTL_DMASEL_UART5RX +#define DMA_REQSRC_ISO78160TX DMA_CTL_DMASEL_ISO78160TX +#define DMA_REQSRC_ISO78160RX DMA_CTL_DMASEL_ISO78160RX +#define DMA_REQSRC_ISO78161TX DMA_CTL_DMASEL_ISO78161TX +#define DMA_REQSRC_ISO78161RX DMA_CTL_DMASEL_ISO78161RX +#define DMA_REQSRC_TIMER0 DMA_CTL_DMASEL_TIMER0 +#define DMA_REQSRC_TIMER1 DMA_CTL_DMASEL_TIMER1 +#define DMA_REQSRC_TIMER2 DMA_CTL_DMASEL_TIMER2 +#define DMA_REQSRC_TIMER3 DMA_CTL_DMASEL_TIMER3 +#define DMA_REQSRC_SPI1TX DMA_CTL_DMASEL_SPI1TX +#define DMA_REQSRC_SPI1RX DMA_CTL_DMASEL_SPI1RX +#define DMA_REQSRC_U32K0 DMA_CTL_DMASEL_U32K0 +#define DMA_REQSRC_U32K1 DMA_CTL_DMASEL_U32K1 +#define DMA_REQSRC_CMP1 DMA_CTL_DMASEL_CMP1 +#define DMA_REQSRC_CMP2 DMA_CTL_DMASEL_CMP2 +#define DMA_REQSRC_SPI2TX DMA_CTL_DMASEL_SPI2TX +#define DMA_REQSRC_SPI2RX DMA_CTL_DMASEL_SPI2RX +//DestAddrMode +#define DMA_DESTADDRMODE_FIX DMA_CxCTL_DMODE_FIX +#define DMA_DESTADDRMODE_PEND DMA_CxCTL_DMODE_PEND +#define DMA_DESTADDRMODE_FEND DMA_CxCTL_DMODE_FEND +//SrcAddrMode +#define DMA_SRCADDRMODE_FIX DMA_CxCTL_SMODE_FIX +#define DMA_SRCADDRMODE_PEND DMA_CxCTL_SMODE_PEND +#define DMA_SRCADDRMODE_FEND DMA_CxCTL_SMODE_FEND +//TransSize +#define DMA_TRANSSIZE_BYTE DMA_CxCTL_SIZE_BYTE +#define DMA_TRANSSIZE_HWORD DMA_CxCTL_SIZE_HWORD +#define DMA_TRANSSIZE_WORD DMA_CxCTL_SIZE_WORD + +typedef struct +{ + uint32_t Mode; /* AES mode */ + uint32_t Direction; /* Direction */ + uint32_t *KeyStr; /* AES key */ +} DMA_AESInitType; +//AES MODE +#define DMA_AESMODE_128 DMA_AESCTL_MODE_AES128 +#define DMA_AESMODE_192 DMA_AESCTL_MODE_AES192 +#define DMA_AESMODE_256 DMA_AESCTL_MODE_AES256 +//AES Direction +#define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC +#define DMA_AESDIRECTION_DECODE 0 + +//INT +#define DMA_INT_C3DA DMA_IE_C3DAIE +#define DMA_INT_C2DA DMA_IE_C2DAIE +#define DMA_INT_C1DA DMA_IE_C1DAIE +#define DMA_INT_C0DA DMA_IE_C0DAIE +#define DMA_INT_C3FE DMA_IE_C3FEIE +#define DMA_INT_C2FE DMA_IE_C2FEIE +#define DMA_INT_C1FE DMA_IE_C1FEIE +#define DMA_INT_C0FE DMA_IE_C0FEIE +#define DMA_INT_C3PE DMA_IE_C3PEIE +#define DMA_INT_C2PE DMA_IE_C2PEIE +#define DMA_INT_C1PE DMA_IE_C1PEIE +#define DMA_INT_C0PE DMA_IE_C0PEIE +#define DMA_INT_Msk (0xFFFUL) + +//INTSTS +#define DMA_INTSTS_C3DA DMA_STS_C3DA +#define DMA_INTSTS_C2DA DMA_STS_C2DA +#define DMA_INTSTS_C1DA DMA_STS_C1DA +#define DMA_INTSTS_C0DA DMA_STS_C0DA +#define DMA_INTSTS_C3FE DMA_STS_C3FE +#define DMA_INTSTS_C2FE DMA_STS_C2FE +#define DMA_INTSTS_C1FE DMA_STS_C1FE +#define DMA_INTSTS_C0FE DMA_STS_C0FE +#define DMA_INTSTS_C3PE DMA_STS_C3PE +#define DMA_INTSTS_C2PE DMA_STS_C2PE +#define DMA_INTSTS_C1PE DMA_STS_C1PE +#define DMA_INTSTS_C0PE DMA_STS_C0PE +#define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY +#define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY +#define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY +#define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY +#define DMA_INTSTS_Msk (0xFFF0UL) + +/* Private macros ------------------------------------------------------------*/ +#define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\ + ((__CH__) == DMA_CHANNEL_1) ||\ + ((__CH__) == DMA_CHANNEL_2) ||\ + ((__CH__) == DMA_CHANNEL_3)) + +#define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U) + +#define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U) + +#define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\ + ((__CONTMOD__) == DMA_CONTMODE_DISABLE)) + +#define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\ + ((__TRANSMOD__) == DMA_TRANSMODE_PACK)) + +#define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\ + ((__REQSRC__) == DMA_REQSRC_UART0TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART0RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART1TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART1RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART2TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART2RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART3TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART3RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART4TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART4RX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART5TX) ||\ + ((__REQSRC__) == DMA_REQSRC_UART5RX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\ + ((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER0) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER1) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER2) ||\ + ((__REQSRC__) == DMA_REQSRC_TIMER3) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\ + ((__REQSRC__) == DMA_REQSRC_U32K0) ||\ + ((__REQSRC__) == DMA_REQSRC_U32K1) ||\ + ((__REQSRC__) == DMA_REQSRC_CMP1) ||\ + ((__REQSRC__) == DMA_REQSRC_CMP2) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\ + ((__REQSRC__) == DMA_REQSRC_SPI2RX)) + +#define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\ + ((__DAM__) == DMA_DESTADDRMODE_PEND) ||\ + ((__DAM__) == DMA_DESTADDRMODE_FEND)) + +#define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\ + ((__SAM__) == DMA_SRCADDRMODE_PEND) ||\ + ((__SAM__) == DMA_SRCADDRMODE_FEND)) + +#define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\ + ((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\ + ((__TSIZE__) == DMA_TRANSSIZE_WORD)) + +#define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\ + ((__AESMOD__) == DMA_AESMODE_192) ||\ + ((__AESMOD__) == DMA_AESMODE_256)) + +#define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\ + ((__AESDIR__) == DMA_AESDIRECTION_DECODE)) + +#define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\ + (((__INT__) & ~DMA_INT_Msk) == 0U)) + +#define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\ + ((__INTFLAGR__) == DMA_INTSTS_C0BUSY)) + +#define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +/* DMA Exported Functions Group1: + (De)Initialization ------------------------*/ +void DMA_DeInit(uint32_t Channel); +void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel); +void DMA_AESDeInit(void); +void DMA_AESInit(DMA_AESInitType *InitStruct); +/* DMA Exported Functions Group2: + Interrupt (flag) --------------------------*/ +void DMA_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t DMA_GetINTStatus(uint32_t INTMask); +void DMA_ClearINTStatus(uint32_t INTMask); +/* DMA Exported Functions Group3: + MISC Configuration ------------------------*/ +void DMA_Cmd(uint32_t Channel, uint32_t NewState); +void DMA_AESCmd(uint32_t NewState); +void DMA_StopTransmit(uint32_t Channel, uint32_t NewState); +uint8_t DMA_GetFrameLenTransferred(uint32_t Channel); +uint8_t DMA_GetPackLenTransferred(uint32_t Channel); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_DMA_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_flash.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_flash.h new file mode 100644 index 0000000000..dc1304b4b3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_flash.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file lib_flash.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief FLASH library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_FLASH_H +#define __LIB_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//CSMode +#define FLASH_CSMODE_DISABLE FLASH_CTRL_CSMODE_DISABLE +#define FLASH_CSMODE_ALWAYSON FLASH_CTRL_CSMODE_ALWAYSON +#define FLASH_CSMODE_TIM2OF FLASH_CTRL_CSMODE_TIM2OV +#define FLASH_CSMODE_RTC FLASH_CTRL_CSMODE_RTC +#define IS_FLASH_CSMODE(__CSMODE__) (((__CSMODE__) == FLASH_CSMODE_DISABLE) ||\ + ((__CSMODE__) == FLASH_CSMODE_ALWAYSON) ||\ + ((__CSMODE__) == FLASH_CSMODE_TIM2OF) ||\ + ((__CSMODE__) == FLASH_CSMODE_RTC)) + +//INT +#define FLASH_INT_CS FLASH_CTRL_CSINTEN +#define IS_FLASH_INT(__INT__) ((__INT__) == FLASH_INT_CS) + +//WriteStatus +#define FLASH_WSTA_BUSY 0 +#define FLASH_WRITE_FINISH 1 +#define FLASH_WSTA_FINISH FLASH_WRITE_FINISH + +#define IS_FLASH_ADDRESS(__ADDRESS__) ((__ADDRESS__) < 0x40000UL) + +#define IS_FLASH_ADRRW(__ADDRW__) (((__ADDRW__) < 0x40000UL) &&\ + (((__ADDRW__) & 0x3U) == 0U)) + +#define IS_FLASH_ADRRHW(__ADDRHW__) (((__ADDRHW__) < 0x40000UL) &&\ + (((__ADDRHW__) & 0x1U) == 0U)) + +#define IS_FLASH_CHECKSUMADDR(__ADDRESS1__,__ADDRESS2__) (((__ADDRESS1__) < 0x40000) && ((__ADDRESS2__) < 0x40000) && ((__ADDRESS1__) < (__ADDRESS2__))) + +/* Exported Functions ------------------------------------------------------- */ + +void FLASH_Init(uint32_t CSMode); +void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState); +void FLASH_CycleInit(void); +void FLASH_SectorErase(uint32_t SectorAddr); +void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length); +void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length); +void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length); +uint32_t FLASH_GetWriteStatus(void); +void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd); +void FLASH_SetCheckSumCompValue(uint32_t Checksum); +uint32_t FLASH_GetCheckSum(void); +uint8_t FLASH_GetINTStatus(uint32_t IntMask); +void FLASH_ClearINTStatus(uint32_t IntMask); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_FLASH_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_gpio.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_gpio.h new file mode 100644 index 0000000000..985a788d0b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_gpio.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file lib_gpio.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief GPIO library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_GPIO_H +#define __LIB_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t GPIO_Pin; + uint32_t GPIO_Mode; +} GPIO_InitType; + +/** + * @brief Bit_State_enumeration + */ +typedef enum { + Bit_RESET = 0, + Bit_SET +} BitState; + +//GPIO_Pin +#define GPIO_Pin_0 ((uint16_t)0x0001) +#define GPIO_Pin_1 ((uint16_t)0x0002) +#define GPIO_Pin_2 ((uint16_t)0x0004) +#define GPIO_Pin_3 ((uint16_t)0x0008) +#define GPIO_Pin_4 ((uint16_t)0x0010) +#define GPIO_Pin_5 ((uint16_t)0x0020) +#define GPIO_Pin_6 ((uint16_t)0x0040) +#define GPIO_Pin_7 ((uint16_t)0x0080) +#define GPIO_Pin_8 ((uint16_t)0x0100) +#define GPIO_Pin_9 ((uint16_t)0x0200) +#define GPIO_Pin_10 ((uint16_t)0x0400) +#define GPIO_Pin_11 ((uint16_t)0x0800) +#define GPIO_Pin_12 ((uint16_t)0x1000) +#define GPIO_Pin_13 ((uint16_t)0x2000) +#define GPIO_Pin_14 ((uint16_t)0x4000) +#define GPIO_Pin_15 ((uint16_t)0x8000) +#define GPIO_Pin_All ((uint16_t)0xFFFF) +//GPIO_Mode +#define GPIO_Mode_INPUT (0xCU) +#define GPIO_Mode_OUTPUT_CMOS (0x2U) +#define GPIO_Mode_OUTPUT_OD (0x3U) +#define GPIO_Mode_INOUT_OD (0xBU) +#define GPIO_Mode_INOUT_CMOS (0xAU) +#define GPIO_Mode_FORBIDDEN (0x4U) + +//GPIO AF +#define GPIOB_AF_PLLHDIV IOB_SEL_SEL1 +#define GPIOB_AF_OSC IOB_SEL_SEL6 +#define GPIOB_AF_PLLLOUT IOB_SEL_SEL2 +#define GPIOE_AF_CMP1O IOE_SEL_SEL7 + +//PMUIO AF +#define PMUIO7_AF_PLLDIV PMU_IOASEL_SEL7 +#define PMUIO_AF_CMP2O PMU_IOASEL_SEL6 +#define PMUIO3_AF_PLLDIV PMU_IOASEL_SEL3 +#define PMUIO_AF_Msk (PMUIO7_AF_PLLDIV | PMUIO_AF_CMP2O | PMUIO3_AF_PLLDIV) + +//GPIO pin remap +#define GPIO_REMAP_I2C IO_MISC_I2CIOC + +//PLLDIV +#define GPIO_PLLDIV_1 IO_MISC_PLLHDIV_1 +#define GPIO_PLLDIV_2 IO_MISC_PLLHDIV_2 +#define GPIO_PLLDIV_4 IO_MISC_PLLHDIV_4 +#define GPIO_PLLDIV_8 IO_MISC_PLLHDIV_8 +#define GPIO_PLLDIV_16 IO_MISC_PLLHDIV_16 + +/* Private macros ------------------------------------------------------------*/ +#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_Pin_All) != 0UL) &&\ + (((__PIN__) & ~GPIO_Pin_All) == 0UL)) + +#define IS_GPIO_PINR(__PINR__) (((__PINR__) == GPIO_Pin_0) ||\ + ((__PINR__) == GPIO_Pin_1) ||\ + ((__PINR__) == GPIO_Pin_2) ||\ + ((__PINR__) == GPIO_Pin_3) ||\ + ((__PINR__) == GPIO_Pin_4) ||\ + ((__PINR__) == GPIO_Pin_5) ||\ + ((__PINR__) == GPIO_Pin_6) ||\ + ((__PINR__) == GPIO_Pin_7) ||\ + ((__PINR__) == GPIO_Pin_8) ||\ + ((__PINR__) == GPIO_Pin_9) ||\ + ((__PINR__) == GPIO_Pin_10) ||\ + ((__PINR__) == GPIO_Pin_11) ||\ + ((__PINR__) == GPIO_Pin_12) ||\ + ((__PINR__) == GPIO_Pin_13) ||\ + ((__PINR__) == GPIO_Pin_14) ||\ + ((__PINR__) == GPIO_Pin_15)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_INPUT) ||\ + ((__MODE__) == GPIO_Mode_OUTPUT_CMOS) ||\ + ((__MODE__) == GPIO_Mode_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_Mode_INOUT_OD) ||\ + ((__MODE__) == GPIO_Mode_INOUT_CMOS) ||\ + ((__MODE__) == GPIO_Mode_FORBIDDEN)) + +#define IS_GPIO_BITVAL(__BITVAL__) (((__BITVAL__) == 1U) || ((__BITVAL__) == 0U)) + +#define IS_GPIO_GPIOAF(__GPIOAF__) (((__GPIOAF__) == GPIOB_AF_PLLHDIV) ||\ + ((__GPIOAF__) == GPIOB_AF_OSC) ||\ + ((__GPIOAF__) == GPIOE_AF_CMP1O) ||\ + ((__GPIOAF__) == GPIOB_AF_PLLLOUT)) + +#define IS_GPIO_PMUIOAF(__PMUIOAF__) ((((__PMUIOAF__) & PMUIO_AF_Msk) != 0U) &&\ + (((__PMUIOAF__) & ~PMUIO_AF_Msk) == 0U)) + +#define IS_GPIO_REMAP(__REMAP__) ((__REMAP__) == GPIO_REMAP_I2C) + +#define IS_GPIO_PLLDIV(__PLLDIV__) (((__PLLDIV__) == GPIO_PLLDIV_1) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_2) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_4) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_8) ||\ + ((__PLLDIV__) == GPIO_PLLDIV_16)) + +/* Exported Functions ------------------------------------------------------- */ +/* GPIO Exported Functions Group1: + Initialization and functions --------------*/ +void GPIOBToF_Init(GPIO_TypeDef *GPIOx, GPIO_InitType *InitStruct); +void GPIOA_Init(GPIOA_TypeDef *GPIOx, GPIO_InitType *InitStruct); +/* GPIO Exported Functions Group2: + Read input data ---------------------------*/ +uint8_t GPIOBToF_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint8_t GPIOA_ReadInputDataBit(GPIOA_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIOBToF_ReadInputData(GPIO_TypeDef* GPIOx); +uint16_t GPIOA_ReadInputData(GPIOA_TypeDef* GPIOx); +/* GPIO Exported Functions Group3: + Read output data --------------------------*/ +uint8_t GPIOBToF_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint8_t GPIOA_ReadOutputDataBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIOBToF_ReadOutputData(GPIO_TypeDef* GPIOx); +uint16_t GPIOA_ReadOutputData(GPIOA_TypeDef* GPIOx); +/* GPIO Exported Functions Group4: + Write output data -------------------------*/ +void GPIOBToF_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOA_SetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOBToF_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOA_ResetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIOBToF_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val); +void GPIOA_WriteBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val); +void GPIOBToF_Write(GPIO_TypeDef* GPIOx, uint16_t val); +void GPIOA_Write(GPIOA_TypeDef* GPIOx, uint16_t val); +/* GPIO Exported Functions Group5: + IO AF configure ---------------------------*/ +void GPIOBToF_AFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_AFx, uint8_t NewState); +void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState); +/* GPIO Exported Functions Group6: + IO Remap configure ------------------------*/ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState); +/* GPIO Exported Functions Group7: + Others ------------------------------------*/ +void GPIO_PLLDIV_Config(uint32_t Divider); +void GPIOA_NoDeg_Cmd( uint16_t GPIO_Pin, uint8_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_GPIO_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_i2c.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_i2c.h new file mode 100644 index 0000000000..4976a68e91 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_i2c.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file lib_i2c.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief IIC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_I2C_H +#define __LIB_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t SlaveAddr; + uint32_t GeneralCallAck; + uint32_t AssertAcknowledge; + uint32_t ClockSource; +} I2C_InitType; +//GeneralCallAck +#define I2C_GENERALCALLACK_ENABLE I2C_ADDR_GC +#define I2C_GENERALCALLACK_DISABLE 0 +//AssertAcknowledge +#define I2C_ASSERTACKNOWLEDGE_ENABLE I2C_CTRL_AA +#define I2C_ASSERTACKNOWLEDGE_DISABLE 0 +//ClockSource +#define I2C_CLOCKSOURCE_APBD256 I2C_CTRL_CR_0 +#define I2C_CLOCKSOURCE_APBD224 I2C_CTRL_CR_1 +#define I2C_CLOCKSOURCE_APBD192 I2C_CTRL_CR_2 +#define I2C_CLOCKSOURCE_APBD160 I2C_CTRL_CR_3 +#define I2C_CLOCKSOURCE_APBD960 I2C_CTRL_CR_4 +#define I2C_CLOCKSOURCE_APBD120 I2C_CTRL_CR_5 +#define I2C_CLOCKSOURCE_APBD60 I2C_CTRL_CR_6 +#define I2C_CLOCKSOURCE_TIM3OFD8 I2C_CTRL_CR_7 + +typedef struct +{ + uint16_t SlaveAddr; + uint8_t SubAddrType; + uint32_t PageRange; + uint32_t SubAddress; + uint8_t *pBuffer; + uint32_t Length; +} I2C_WRType; +//SubAddrType +#define I2C_SUBADDR_1BYTE 1 +#define I2C_SUBADDR_2BYTE 2 +#define I2C_SUBADDR_OTHER 3 + +//remap +#define I2C_REMAP_ENABLE 1 +#define I2C_REMAP_DISABLE 0 + +/* Private macros ------------------------------------------------------------*/ + +#define IS_I2C_GC(__GC__) (((__GC__) == I2C_GENERALCALLACK_ENABLE) ||\ + ((__GC__) == I2C_GENERALCALLACK_DISABLE)) + +#define IS_I2C_AA(__AA__) (((__AA__) == I2C_ASSERTACKNOWLEDGE_ENABLE) ||\ + ((__AA__) == I2C_ASSERTACKNOWLEDGE_DISABLE)) + +#define IS_I2C_CLKSRC(__CLKSRC__) (((__CLKSRC__) == I2C_CLOCKSOURCE_APBD256) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD224) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD192) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD160) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD960) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD120) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_APBD60) ||\ + ((__CLKSRC__) == I2C_CLOCKSOURCE_TIM3OFD8)) + +#define I2C_SUBADDR_TYPE(__TYPE__) (((__TYPE__) == I2C_SUBADDR_1BYTE) ||\ + ((__TYPE__) == I2C_SUBADDR_2BYTE) ||\ + ((__TYPE__) == I2C_SUBADDR_OTHER)) + +/* Exported Functions ------------------------------------------------------- */ +/* I2C Exported Functions Group1: + (De)Initialization ------------------------*/ +void I2C_DeInit(uint32_t remap); +void I2C_StructInit(I2C_InitType *InitStruct); +void I2C_Init(I2C_InitType *InitStruct); +/* I2C Exported Functions Group2: + Interrupt ---------------------------------*/ +void I2C_INTConfig(uint32_t NewState); +uint8_t I2C_GetINTStatus(void); +void I2C_ClearINTStatus(void); +/* I2C Exported Functions Group3: + Transfer datas ----------------------------*/ +uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct); +uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct); +/* I2C Exported Functions Group4: + MISC Configuration ------------------------*/ +void I2C_Cmd(uint32_t NewState); + +/* I2C Exported Functions Group5: + Others ------------------------------------*/ +void I2C_AssertAcknowledgeConfig(uint32_t NewState); +uint8_t I2C_ReceiveData(void); +void I2C_SendData(uint8_t Dat); +void I2C_GenerateSTART(uint32_t NewState); +void I2C_GenerateSTOP(uint32_t NewState); +uint8_t I2C_GetStatusCode(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_I2C_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_iso7816.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_iso7816.h new file mode 100644 index 0000000000..fb77f3084a --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_iso7816.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file lib_iso7816.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ISO7816 library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_ISO7816_H +#define __LIB_ISO7816_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t FirstBit; + uint32_t ACKLen; + uint32_t Parity; + uint32_t Baudrate; +} ISO7816_InitType; + +//FirstBit +#define ISO7816_FIRSTBIT_LSB ISO7816_INFO_LSB +#define ISO7816_FIRSTBIT_MSB 0 +#define IS_ISO7816_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == ISO7816_FIRSTBIT_LSB) ||\ + ((__FIRSTBIT__) == ISO7816_FIRSTBIT_MSB)) +//ACKLen +#define ISO7816_ACKLEN_1 0 +#define ISO7816_ACKLEN_2 ISO7816_CFG_ACKLEN +#define IS_ISO7816_ACKLEN(__ACKLEN__) (((__ACKLEN__) == ISO7816_ACKLEN_1) ||\ + ((__ACKLEN__) == ISO7816_ACKLEN_2)) +//Parity +#define ISO7816_PARITY_EVEN 0 +#define ISO7816_PARITY_ODD ISO7816_CFG_CHKP +#define IS_ISO7816_PARITY(__PARITY__) (((__PARITY__) == ISO7816_PARITY_EVEN) || ((__PARITY__) == ISO7816_PARITY_ODD)) + +#define IS_ISO7816_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) > 299UL) +#define IS_ISO7816_PRESCALER(__PRESCALER__) (((__PRESCALER__) <= 0x80) && ((__PRESCALER__) > 0U)) + +//interrupt +#define ISO7816_INT_RXOV ISO7816_CFG_OVIE +#define ISO7816_INT_TX ISO7816_CFG_SDIE +#define ISO7816_INT_RX ISO7816_CFG_RCIE +#define ISO7816_INT_Msk (ISO7816_INT_RXOV \ + |ISO7816_INT_TX \ + |ISO7816_INT_RX) +#define IS_ISO7816_INT(__INT__) ((((__INT__) & ISO7816_INT_Msk) != 0U) &&\ + (((__INT__) & ~ISO7816_INT_Msk) == 0U)) + +//INTStatus +#define ISO7816_INTSTS_RXOV ISO7816_INFO_OVIF +#define ISO7816_INTSTS_TX ISO7816_INFO_SDIF +#define ISO7816_INTSTS_RX ISO7816_INFO_RCIF +#define ISO7816_INTSTS_Msk (ISO7816_INTSTS_RXOV \ + |ISO7816_INTSTS_TX \ + |ISO7816_INTSTS_RX) +#define IS_ISO7816_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == ISO7816_INTSTS_RXOV) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_TX) ||\ + ((__INTFLAG__) == ISO7816_INTSTS_RX)) + +#define IS_ISO7816_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&ISO7816_INTSTS_Msk) != 0U) &&\ + (((__INTFLAG__)&(~ISO7816_INTSTS_Msk)) == 0U)) +//status +#define ISO7816_FLAG_SDERR ISO7816_INFO_SDERR +#define ISO7816_FLAG_RCERR ISO7816_INFO_RCERR +#define ISO7816_FLAG_Msk (ISO7816_FLAG_SDERR|ISO7816_FLAG_RCERR) +#define IS_ISO7816_FLAGR(__FLAG__) (((__FLAG__) == ISO7816_FLAG_SDERR) || ((__FLAG__) == ISO7816_FLAG_RCERR)) +#define IS_ISO7816_FLAGC(__FLAG__) ((((__FLAG__) & ISO7816_FLAG_Msk) != 0U) &&\ + (((__FLAG__) & (~ISO7816_FLAG_Msk)) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +void ISO7816_DeInit(ISO7816_TypeDef *ISO7816x); +void ISO7816_StructInit(ISO7816_InitType *InitStruct); +void ISO7816_Init(ISO7816_TypeDef *ISO7816x, ISO7816_InitType *Init_Struct); +void ISO7816_Cmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState); +void ISO7816_BaudrateConfig(ISO7816_TypeDef *ISO7816x, uint32_t BaudRate); +void ISO7816_CLKDIVConfig(ISO7816_TypeDef *ISO7816x, uint32_t Prescaler); +void ISO7816_CLKOutputCmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState); +void ISO7816_SendData(ISO7816_TypeDef *ISO7816x, uint8_t ch); +uint8_t ISO7816_ReceiveData(ISO7816_TypeDef *ISO7816x); +void ISO7816_INTConfig(ISO7816_TypeDef *ISO7816x, uint32_t INTMask, uint8_t NewState); +uint8_t ISO7816_GetINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask); +void ISO7816_ClearINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask); +uint8_t ISO7816_GetFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask); +void ISO7816_ClearFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask); +uint8_t ISO7816_GetLastTransmitACK(ISO7816_TypeDef *ISO7816x); +uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_TypeDef *ISO7816x); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_ISO7816_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_lcd.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_lcd.h new file mode 100644 index 0000000000..785330619f --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_lcd.h @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * @file lib_lcd.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief LCD library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_LCD_H +#define __LIB_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* LCD SEGx IO typedef */ +typedef struct +{ + __IO uint32_t *GPIO; + uint16_t Pin; +}LCD_SEGIO; + +/* LCD COMx IO typedef */ +typedef struct +{ + __IO uint32_t *GPIO; + uint16_t Pin; +}LCD_COMIO; + +typedef struct +{ + uint32_t Type; + uint32_t Drv; + uint32_t FRQ; + uint32_t SWPR; + uint32_t FBMODE; + uint32_t BKFILL; +} LCD_InitType; +//Type +#define LCD_TYPE_4COM LCD_CTRL_TYPE_4COM +#define LCD_TYPE_6COM LCD_CTRL_TYPE_6COM +#define LCD_TYPE_8COM LCD_CTRL_TYPE_8COM +//DrivingRes +#define LCD_DRV_300 LCD_CTRL_DRV_300KOHM +#define LCD_DRV_600 LCD_CTRL_DRV_600KOHM +#define LCD_DRV_150 LCD_CTRL_DRV_150KOHM +#define LCD_DRV_200 LCD_CTRL_DRV_200KOHM +//ScanFRQ +#define LCD_FRQ_64H LCD_CTRL_FRQ_64HZ +#define LCD_FRQ_128H LCD_CTRL_FRQ_128HZ +#define LCD_FRQ_256H LCD_CTRL_FRQ_256HZ +#define LCD_FRQ_512H LCD_CTRL_FRQ_512HZ +//SwitchMode +#define LCD_FBMODE_BUFA LCD_CTRL2_FBMODE_BUFA +#define LCD_FBMODE_BUFAB LCD_CTRL2_FBMODE_BUFAANDBUFB +#define LCD_FBMODE_BUFABLANK LCD_CTRL2_FBMODE_BUFAANDBLANK +//BlankFill +#define LCD_BKFILL_1 LCD_CTRL2_BKFILL +#define LCD_BKFILL_0 0 + +//ComMode +#define LCD_COMMOD_4COM 1 +#define LCD_COMMOD_6COM 3 +#define LCD_COMMOD_8COM 7 + +//BiasSelection +#define LCD_BMODE_DIV3 0 +#define LCD_BMODE_DIV4 ANA_REG6_LCD_BMODE + +//VLCDSelection +#define LCD_VLCD_0 0 +#define LCD_VLCD_INC60MV 1 +#define LCD_VLCD_INC120MV 2 +#define LCD_VLCD_INC180MV 3 +#define LCD_VLCD_INC240MV 4 +#define LCD_VLCD_INC300MV 5 +#define LCD_VLCD_DEC60MV 6 +#define LCD_VLCD_DEC120MV 7 +#define LCD_VLCD_DEC180MV 8 +#define LCD_VLCD_DEC240MV 9 +#define LCD_VLCD_DEC300MV 10 +#define LCD_VLCD_DEC360MV 11 +#define LCD_VLCD_DEC420MV 12 +#define LCD_VLCD_DEC480MV 13 +#define LCD_VLCD_DEC540MV 14 +#define LCD_VLCD_DEC600MV 15 + +/* Private macros ------------------------------------------------------------*/ +#define IS_LCD_TYPE(__TYPE__) (((__TYPE__) == LCD_TYPE_4COM) ||\ + ((__TYPE__) == LCD_TYPE_6COM) ||\ + ((__TYPE__) == LCD_TYPE_8COM)) + +#define IS_LCD_DRV(__DRV__) (((__DRV__) == LCD_DRV_300) ||\ + ((__DRV__) == LCD_DRV_600) ||\ + ((__DRV__) == LCD_DRV_150) ||\ + ((__DRV__) == LCD_DRV_200)) + +#define IS_LCD_FRQ(__FRQ__) (((__FRQ__) == LCD_FRQ_64H) ||\ + ((__FRQ__) == LCD_FRQ_128H) ||\ + ((__FRQ__) == LCD_FRQ_256H) ||\ + ((__FRQ__) == LCD_FRQ_512H)) + +#define IS_LCD_SWPR(__SWPR__) ((__SWPR__) <= 0xFFUL) + +#define IS_LCD_FBMODE(__FBMODE__) (((__FBMODE__) == LCD_FBMODE_BUFA) ||\ + ((__FBMODE__) == LCD_FBMODE_BUFAB) ||\ + ((__FBMODE__) == LCD_FBMODE_BUFABLANK)) + +#define IS_LCD_BKFILL(__BKFILL__) (((__BKFILL__) == LCD_BKFILL_1) || ((__BKFILL__) == LCD_BKFILL_0)) + +#define IS_LCD_BMODE(__BMODE__) (((__BMODE__) == LCD_BMODE_DIV3) ||\ + ((__BMODE__) == LCD_BMODE_DIV4)) + +#define IS_LCD_COMMOD(__COMMOD__) (((__COMMOD__) == LCD_COMMOD_4COM) ||\ + ((__COMMOD__) == LCD_COMMOD_6COM) ||\ + ((__COMMOD__) == LCD_COMMOD_8COM)) + +#define IS_LCD_VLCD(__VLCD__) (((__VLCD__) == LCD_VLCD_0) ||\ + ((__VLCD__) == LCD_VLCD_INC60MV) ||\ + ((__VLCD__) == LCD_VLCD_INC120MV) ||\ + ((__VLCD__) == LCD_VLCD_INC180MV) ||\ + ((__VLCD__) == LCD_VLCD_INC240MV) ||\ + ((__VLCD__) == LCD_VLCD_INC300MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC60MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC120MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC180MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC240MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC300MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC360MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC420MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC480MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC540MV) ||\ + ((__VLCD__) == LCD_VLCD_DEC600MV)) + +/* Exported Functions ------------------------------------------------------- */ +/* LCD Exported Functions Group1: + (De)Initialization -------------------------*/ +void LCD_DeInit(void); +void LCD_StructInit(LCD_InitType *LCD_InitStruct); +void LCD_Init(LCD_InitType *InitStruct); +/* LCD Exported Functions Group1: + MISC Configuration -------------------------*/ +void LCD_Cmd(uint32_t NewState); +void LCD_IOConfig(uint32_t ComMode, uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2, uint32_t NewState); +void LCD_SetSEG(uint32_t SegCtrl0, uint32_t SegCtrl1, uint16_t SegCtrl2); +void LCD_BiasModeConfig(uint32_t BiasSelection); +uint32_t LCD_VoltageConfig(uint32_t VLCDSelection); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_LCD_H */ + +/*********************************** END OF FILE ******************************/ + diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_misc.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_misc.h new file mode 100644 index 0000000000..50585d58a1 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_misc.h @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file lib_misc.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief MISC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_MISC_H +#define __LIB_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//FlagMask +#define MISC_FLAG_LOCKUP MISC_SRAMINT_LOCKUP +#define MISC_FLAG_PIAC MISC_SRAMINT_PIAC +#define MISC_FLAG_HIAC MISC_SRAMINT_HIAC +#define MISC_FLAG_PERR MISC_SRAMINT_PERR +#define MISC_FLAG_Msk (MISC_FLAG_LOCKUP | MISC_FLAG_PIAC | MISC_FLAG_HIAC | MISC_FLAG_PERR) + +//MISC interrupt +#define MISC_INT_LOCK MISC_SRAMINIT_LOCKIE +#define MISC_INT_PIAC MISC_SRAMINIT_PIACIE +#define MISC_INT_HIAC MISC_SRAMINIT_HIACIE +#define MISC_INT_PERR MISC_SRAMINIT_PERRIE +#define MISC_INT_Msk (MISC_INT_LOCK | MISC_INT_PIAC | MISC_INT_HIAC | MISC_INT_PERR) + +//IR +#define MISC_IREN_TX0 MISC_IREN_UART0 +#define MISC_IREN_TX1 MISC_IREN_UART1 +#define MISC_IREN_TX2 MISC_IREN_UART2 +#define MISC_IREN_TX3 MISC_IREN_UART3 +#define MISC_IREN_TX4 MISC_IREN_UART4 +#define MISC_IREN_TX5 MISC_IREN_UART5 +#define MISC_IREN_Msk (0x3FUL) + +/* Private macros ------------------------------------------------------------*/ +#define IS_MISC_FLAGR(__FLAGR__) (((__FLAGR__) == MISC_FLAG_LOCKUP) ||\ + ((__FLAGR__) == MISC_FLAG_PIAC) ||\ + ((__FLAGR__) == MISC_FLAG_HIAC) ||\ + ((__FLAGR__) == MISC_FLAG_PERR)) + +#define IS_MISC_FLAGC(__FLAGC__) ((((__FLAGC__) & MISC_FLAG_Msk) != 0U) &&\ + (((__FLAGC__) & ~MISC_FLAG_Msk) == 0U)) + +#define IS_MISC_INT(__INT__) ((((__INT__) & MISC_INT_Msk) != 0U) &&\ + (((__INT__) &~MISC_INT_Msk) == 0U)) + +#define IS_MISC_IREN(__IREN__) ((((__IREN__) & MISC_IREN_Msk) != 0U) &&\ + (((__IREN__) & ~MISC_IREN_Msk) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +uint8_t MISC_GetFlag(uint32_t FlagMask); +void MISC_ClearFlag(uint32_t FlagMask); +void MISC_INTConfig(uint32_t INTMask, uint32_t NewState); +void MISC_SRAMParityCmd(uint32_t NewState); +uint32_t MISC_GetSRAMPEAddr(void); +uint32_t MISC_GetAPBErrAddr(void); +uint32_t MISC_GetAHBErrAddr(void); +void MISC_IRCmd(uint32_t IRx, uint32_t NewState); +void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow); +void MISC_HardFaultCmd(uint32_t NewState); +void MISC_LockResetCmd(uint32_t NewState); +void MISC_IRQLATConfig(uint8_t Latency); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_MISC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pmu.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pmu.h new file mode 100644 index 0000000000..a8b7524773 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pmu.h @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file lib_pmu.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PMU library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_PMU_H +#define __LIB_PMU_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/** + * Deep-sleep low-power configuration +*/ +typedef struct +{ + uint32_t COMP1Power; /* Comparator 1 power control */ + uint32_t COMP2Power; /* Comparator 2 power control */ + uint32_t TADCPower; /* Tiny ADC power control */ + uint32_t BGPPower; /* BGP power control */ + uint32_t AVCCPower; /* AVCC power control */ + uint32_t LCDPower; /* LCD controller power control */ + uint32_t VDCINDetector; /* VDCIN detector control */ + uint32_t VDDDetector; /* VDD detector control */ + uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */ + uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */ +} PMU_LowPWRTypeDef; + + +/* COMP1Power */ +#define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN) +#define PMU_COMP1PWR_OFF (0) +#define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\ + ((__COMP1PWR__) == PMU_COMP1PWR_OFF)) +/* COMP2Power */ +#define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN) +#define PMU_COMP2PWR_OFF (0) +#define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\ + ((__COMP2PWR__) == PMU_COMP2PWR_OFF)) +/* TADCPower */ +#define PMU_TADCPWR_ON (ANA_REGF_PDNADT) +#define PMU_TADCPWR_OFF (0) +#define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\ + ((__TADCPWR__) == PMU_TADCPWR_OFF)) +/* BGPPower */ +#define PMU_BGPPWR_ON (0) +#define PMU_BGPPWR_OFF (ANA_REG3_BGPPD) +#define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\ + ((__BGPPWR__) == PMU_BGPPWR_OFF)) +/* AVCCPower */ +#define PMU_AVCCPWR_ON (0) +#define PMU_AVCCPWR_OFF (ANA_REG8_PD_AVCCLDO) +#define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\ + ((__AVCCPWR__) == PMU_AVCCPWR_OFF)) +/* LCDPower */ +#define PMU_LCDPWER_ON (LCD_CTRL_EN) +#define PMU_LCDPWER_OFF (0) +#define IS_PMU_LCDPWER(__LCDPWER__) (((__LCDPWER__) == PMU_LCDPWER_ON) ||\ + ((__LCDPWER__) == PMU_LCDPWER_OFF)) +/* VDCINDetector */ +#define PMU_VDCINDET_ENABLE (0) +#define PMU_VDCINDET_DISABLE (ANA_REGA_PD_VDCINDET) +#define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\ + ((__VDCINDET__) == PMU_VDCINDET_DISABLE)) + +/* VDDDetector */ +#define PMU_VDDDET_ENABLE (0) +#define PMU_VDDDET_DISABLE (ANA_REG9_PDDET) +#define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\ + ((__VDDDET__) == PMU_VDDDET_DISABLE)) + +/* APBPeriphralDisable */ +#define PMU_APB_ALL (MISC2_PCLKEN_DMA \ + |MISC2_PCLKEN_I2C \ + |MISC2_PCLKEN_SPI1 \ + |MISC2_PCLKEN_UART0 \ + |MISC2_PCLKEN_UART1 \ + |MISC2_PCLKEN_UART2 \ + |MISC2_PCLKEN_UART3 \ + |MISC2_PCLKEN_UART4 \ + |MISC2_PCLKEN_UART5 \ + |MISC2_PCLKEN_ISO78160\ + |MISC2_PCLKEN_ISO78161\ + |MISC2_PCLKEN_TIMER \ + |MISC2_PCLKEN_MISC \ + |MISC2_PCLKEN_U32K0 \ + |MISC2_PCLKEN_U32K1 \ + |MISC2_PCLKEN_SPI2) +#define PMU_APB_DMA MISC2_PCLKEN_DMA +#define PMU_APB_I2C MISC2_PCLKEN_I2C +#define PMU_APB_SPI1 MISC2_PCLKEN_SPI1 +#define PMU_APB_UART0 MISC2_PCLKEN_UART0 +#define PMU_APB_UART1 MISC2_PCLKEN_UART1 +#define PMU_APB_UART2 MISC2_PCLKEN_UART2 +#define PMU_APB_UART3 MISC2_PCLKEN_UART3 +#define PMU_APB_UART4 MISC2_PCLKEN_UART4 +#define PMU_APB_UART5 MISC2_PCLKEN_UART5 +#define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160 +#define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161 +#define PMU_APB_TIMER MISC2_PCLKEN_TIMER +#define PMU_APB_MISC MISC2_PCLKEN_MISC +#define PMU_APB_U32K0 MISC2_PCLKEN_U32K0 +#define PMU_APB_U32K1 MISC2_PCLKEN_U32K1 +#define PMU_APB_SPI2 MISC2_PCLKEN_SPI2 +/* AHBPeriphralDisable */ +#define PMU_AHB_ALL (MISC2_HCLKEN_DMA \ + |MISC2_HCLKEN_GPIO \ + |MISC2_HCLKEN_LCD \ + |MISC2_HCLKEN_CRYPT) +#define PMU_AHB_DMA MISC2_HCLKEN_DMA +#define PMU_AHB_GPIO MISC2_HCLKEN_GPIO +#define PMU_AHB_LCD MISC2_HCLKEN_LCD +#define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT + +//PMU interrupt +#define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN +#define PMU_INT_32K PMU_CONTROL_INT_32K_EN +#define PMU_INT_6M PMU_CONTROL_INT_6M_EN +#define PMU_INT_Msk (PMU_INT_IOAEN \ + |PMU_INT_32K \ + |PMU_INT_6M) +#define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0U) &&\ + (((__INT__)&(~PMU_INT_Msk)) == 0U)) + +//INTStatus +#define PMU_INTSTS_32K PMU_STS_INT_32K +#define PMU_INTSTS_6M PMU_STS_INT_6M +#define PMU_INTSTS_EXTRST PMU_STS_EXTRST +#define PMU_INTSTS_PORST PMU_STS_PORST +#define PMU_INTSTS_DPORST PMU_STS_DPORST +#define PMU_INTSTS_Msk (PMU_INTSTS_32K \ + |PMU_INTSTS_6M \ + |PMU_INTSTS_EXTRST \ + |PMU_INTSTS_PORST \ + |PMU_INTSTS_DPORST) +#define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\ + ((__INTFLAG__) == PMU_INTSTS_6M) ||\ + ((__INTFLAG__) == PMU_INTSTS_EXTRST) ||\ + ((__INTFLAG__) == PMU_INTSTS_PORST) ||\ + ((__INTFLAG__) == PMU_INTSTS_DPORST)) + +#define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0U) &&\ + (((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0U)) + + + +//Status +#define PMU_STS_32K PMU_STS_EXIST_32K +#define PMU_STS_6M PMU_STS_EXIST_6M +#define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M)) + +//Wakeup_Event +#define IOA_DISABLE (0) +#define IOA_RISING (1) +#define IOA_FALLING (2) +#define IOA_HIGH (3) +#define IOA_LOW (4) +#define IOA_EDGEBOTH (5) +#define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\ + ((__WAKEUP__) == IOA_RISING) ||\ + ((__WAKEUP__) == IOA_FALLING) ||\ + ((__WAKEUP__) == IOA_HIGH) ||\ + ((__WAKEUP__) == IOA_LOW) ||\ + ((__WAKEUP__) == IOA_EDGEBOTH)) + +/***** Wakeup_Event (PMU_SleepWKUSRC_Config_RTC) *****/ +#define PMU_RTCEVT_ACDONE RTC_INTSTS_INTSTS7 +#define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6 +#define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5 +#define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4 +#define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3 +#define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2 +#define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1 +#define PMU_RTCEVT_Msk (PMU_RTCEVT_ACDONE \ + |PMU_RTCEVT_WKUCNT \ + |PMU_RTCEVT_MIDNIGHT \ + |PMU_RTCEVT_WKUHOUR \ + |PMU_RTCEVT_WKUMIN \ + |PMU_RTCEVT_WKUSEC \ + |PMU_RTCEVT_TIMEILLE) +#define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0U) &&\ + (((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0U)) + + +/***** BATDisc (PMU_BATDischargeConfig) *****/ +#define PMU_BATRTC_DISC ANA_REG6_BATRTCDISC +#define IS_PMU_BATRTCDISC(__BATRTCDISC__) ((__BATRTCDISC__) == PMU_BATRTC_DISC) + +/***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/ +#define PMU_PWTH_4_5 ANA_REG8_VDDPVDSEL_0 +#define PMU_PWTH_4_2 ANA_REG8_VDDPVDSEL_1 +#define PMU_PWTH_3_9 ANA_REG8_VDDPVDSEL_2 +#define PMU_PWTH_3_6 ANA_REG8_VDDPVDSEL_3 +#define PMU_PWTH_3_2 ANA_REG8_VDDPVDSEL_4 +#define PMU_PWTH_2_9 ANA_REG8_VDDPVDSEL_5 +#define PMU_PWTH_2_6 ANA_REG8_VDDPVDSEL_6 +#define PMU_PWTH_2_3 ANA_REG8_VDDPVDSEL_7 + +#define IS_PMU_PWTH(__PWTH__) (((__PWTH__) == PMU_PWTH_4_5) ||\ + ((__PWTH__) == PMU_PWTH_4_2) ||\ + ((__PWTH__) == PMU_PWTH_3_9) ||\ + ((__PWTH__) == PMU_PWTH_3_6) ||\ + ((__PWTH__) == PMU_PWTH_3_2) ||\ + ((__PWTH__) == PMU_PWTH_2_9) ||\ + ((__PWTH__) == PMU_PWTH_2_6) ||\ + ((__PWTH__) == PMU_PWTH_2_3)) + +/***** RTCLDOSel (PMU_RTCLDOConfig) *****/ +#define PMU_RTCLDO_1_5 (0) +#define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL + +/***** StatusMask (PMU_GetPowerStatus) *****/ +#define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV +#define PMU_PWRSTS_VDCINDROP ANA_COMPOUT_VDCINDROP +#define PMU_PWRSTS_VDDALARM ANA_COMPOUT_VDDALARM + +/***** Debounce (PMU_PWRDropDEBConfig) *****/ +#define PMU_PWRDROP_DEB_0 ANA_CTRL_PWRDROPDEB_0 +#define PMU_PWRDROP_DEB_1 ANA_CTRL_PWRDROPDEB_1 +#define PMU_PWRDROP_DEB_2 ANA_CTRL_PWRDROPDEB_2 +#define PMU_PWRDROP_DEB_3 ANA_CTRL_PWRDROPDEB_3 +#define IS_PMU_PWRDROP_DEB(__DEB__) (((__DEB__) == PMU_PWRDROP_DEB_0) ||\ + ((__DEB__) == PMU_PWRDROP_DEB_1) ||\ + ((__DEB__) == PMU_PWRDROP_DEB_2) ||\ + ((__DEB__) == PMU_PWRDROP_DEB_3)) + +/***** RSTSource (PMU_GetRSTSource) *****/ +#define PMU_RSTSRC_EXTRST PMU_STS_EXTRST +#define PMU_RSTSRC_PORST PMU_STS_PORST +#define PMU_RSTSRC_DPORST PMU_STS_DPORST +//#define PMU_RSTSRC_WDTRST PMU_WDTSTS_WDTSTS +#define IS_PMU_RSTSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_PORST) ||\ + ((__RSTSRC__) == PMU_RSTSRC_DPORST) ) + +/***** PMU_PDNDSleepConfig *****/ +//VDCIN_PDNS +#define PMU_VDCINPDNS_0 (0) +#define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS) +#define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\ + ((__VDCINPDNS__) == PMU_VDCINPDNS_1)) +//VDD_PDNS +#define PMU_VDDPDNS_0 (0) +#define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2) +#define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\ + ((__VDDPDNS__) == PMU_VDDPDNS_1)) + +/* Exported Functions ------------------------------------------------------- */ + +uint32_t PMU_EnterDSleepMode(void); +void PMU_EnterIdleMode(void); +uint32_t PMU_EnterSleepMode(void); + +void PMU_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t PMU_GetINTStatus(uint32_t INTMask); +void PMU_ClearINTStatus(uint32_t INTMask); + +uint8_t PMU_GetStatus(uint32_t Mask); +uint16_t PMU_GetIOAAllINTStatus(void); +uint16_t PMU_GetIOAINTStatus(uint16_t INTMask); +void PMU_ClearIOAINTStatus(uint16_t INTMask); + +void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event); + +uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); +uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); +#ifndef __GNUC__ +void PMU_EnterIdle_LowPower(void); +#endif +void PMU_SleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority); +void PMU_SleepWKUSRC_Config_RTC(uint32_t Wakeup_Event, uint32_t Priority); +void PMU_DeepSleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event); +void PMU_DeepSleepWKUSRC_Config_RTC(uint32_t Wakeup_Event); +void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS); + +/***** BGP functions *****/ +void PMU_BGP_Cmd(uint32_t NewState); + +/***** VDD functions *****/ +void PMU_VDDAlarmTHConfig(uint32_t PowerThreshold); +uint8_t PMU_GetVDDALARMStatus(void); +void PMU_VDDDetectorCmd(uint32_t NewState); + +/***** AVCC functions *****/ +void PMU_AVCC_Cmd(uint32_t NewState); +void PMU_AVCCOutput_Cmd(uint32_t NewState); +void PMU_AVCCLVDetector_Cmd(uint32_t NewState); +uint8_t PMU_GetAVCCLVStatus(void); + +/***** VDCIN functions *****/ +void PMU_VDCINDetector_Cmd(uint32_t NewState); +uint8_t PMU_GetVDCINDropStatus(void); + +/***** BAT functions *****/ +void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState); + +/***** Other functions *****/ +uint8_t PMU_GetModeStatus(void); +uint8_t PMU_GetPowerStatus(uint32_t StatusMask); +void PMU_PWRDropDEBConfig(uint32_t Debounce); +uint8_t PMU_GetRSTSource(uint32_t RSTSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_PMU_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pwm.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pwm.h new file mode 100644 index 0000000000..ce78befcd1 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_pwm.h @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file lib_pwm.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PWM library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_PWM_H +#define __LIB_PWM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t ClockDivision; + uint32_t Mode; + uint32_t ClockSource; +} PWM_BaseInitType; +//ClockDivision +#define PWM_CLKDIV_2 PWM_CTL_ID_DIV2 +#define PWM_CLKDIV_4 PWM_CTL_ID_DIV4 +#define PWM_CLKDIV_8 PWM_CTL_ID_DIV8 +#define PWM_CLKDIV_16 PWM_CTL_ID_DIV16 +//Mode +#define PWM_MODE_STOP PWM_CTL_MC_STOP +#define PWM_MODE_UPCOUNT PWM_CTL_MC_UP +#define PWM_MODE_CONTINUOUS PWM_CTL_MC_CONTINUE +#define PWM_MODE_UPDOWN PWM_CTL_MC_UPDOWN +//ClockSource +#define PWM_CLKSRC_APB PWM_CTL_TESL_APBDIV1 +#define PWM_CLKSRC_APBD128 PWM_CTL_TESL_APBDIV128 + +typedef struct +{ + uint32_t Period; + uint32_t OutMode; +} PWM_OCInitType; +//OUTMOD +#define PWM_OUTMOD_CONST PWM_CCTL_OUTMOD_CONST +#define PWM_OUTMOD_SET PWM_CCTL_OUTMOD_SET +#define PWM_OUTMOD_TOGGLE_RESET PWM_CCTL_OUTMOD_TOGGLE_RESET +#define PWM_OUTMOD_SET_RESET PWM_CCTL_OUTMOD_SET_RESET +#define PWM_OUTMOD_TOGGLE PWM_CCTL_OUTMOD_TOGGLE +#define PWM_OUTMOD_RESET PWM_CCTL_OUTMOD_RESET +#define PWM_OUTMOD_TOGGLE_SET PWM_CCTL_OUTMOD_TOGGLE_SET +#define PWM_OUTMOD_RESET_SET PWM_CCTL_OUTMOD_RESET_SET + +//PWM CHANNEL +#define PWM_CHANNEL_0 0 +#define PWM_CHANNEL_1 1 +#define PWM_CHANNEL_2 2 + +#define PWM_OSEL0_T0O0 (0<<0) +#define PWM_OSEL0_T0O1 (1<<0) +#define PWM_OSEL0_T0O2 (2<<0) +#define PWM_OSEL0_T1O0 (4<<0) +#define PWM_OSEL0_T1O1 (5<<0) +#define PWM_OSEL0_T1O2 (6<<0) +#define PWM_OSEL0_T2O0 (8<<0) +#define PWM_OSEL0_T2O1 (9<<0) +#define PWM_OSEL0_T2O2 (10<<0) +#define PWM_OSEL0_T3O0 (12<<0) +#define PWM_OSEL0_T3O1 (13<<0) +#define PWM_OSEL0_T3O2 (14<<0) +//outline +#define PWM_OLINE_0 1 +#define PWM_OLINE_1 2 +#define PWM_OLINE_2 4 +#define PWM_OLINE_3 8 +#define PWM_OLINE_Msk 0xF +//PWM output selection +#define PWM0_OUT0 PWM_OSEL0_T0O0 +#define PWM0_OUT1 PWM_OSEL0_T0O1 +#define PWM0_OUT2 PWM_OSEL0_T0O2 +#define PWM1_OUT0 PWM_OSEL0_T1O0 +#define PWM1_OUT1 PWM_OSEL0_T1O1 +#define PWM1_OUT2 PWM_OSEL0_T1O2 +#define PWM2_OUT0 PWM_OSEL0_T2O0 +#define PWM2_OUT1 PWM_OSEL0_T2O1 +#define PWM2_OUT2 PWM_OSEL0_T2O2 +#define PWM3_OUT0 PWM_OSEL0_T3O0 +#define PWM3_OUT1 PWM_OSEL0_T3O1 +#define PWM3_OUT2 PWM_OSEL0_T3O2 + +//Level +#define PWM_LEVEL_HIGH PWM_CCTL_OUT +#define PWM_LEVEL_LOW 0 + +/* Private macros ------------------------------------------------------------*/ +#define IS_PWM_CLKDIV(__CLKDIV__) (((__CLKDIV__) == PWM_CLKDIV_2) ||\ + ((__CLKDIV__) == PWM_CLKDIV_4) ||\ + ((__CLKDIV__) == PWM_CLKDIV_8) ||\ + ((__CLKDIV__) == PWM_CLKDIV_16)) + +#define IS_PWM_CNTMODE(__CNTMODE__) (((__CNTMODE__) == PWM_MODE_STOP) ||\ + ((__CNTMODE__) == PWM_MODE_UPCOUNT) ||\ + ((__CNTMODE__) == PWM_MODE_CONTINUOUS) ||\ + ((__CNTMODE__) == PWM_MODE_UPDOWN)) + +#define IS_PWM_CLKSRC(__CLKSRC__) (((__CLKSRC__) == PWM_CLKSRC_APB) ||\ + ((__CLKSRC__) == PWM_CLKSRC_APBD128)) + +#define IS_PWM_OUTMODE(__OUTMODE__) (((__OUTMODE__) == PWM_OUTMOD_CONST) ||\ + ((__OUTMODE__) == PWM_OUTMOD_SET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_SET_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE) ||\ + ((__OUTMODE__) == PWM_OUTMOD_RESET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_TOGGLE_SET) ||\ + ((__OUTMODE__) == PWM_OUTMOD_RESET_SET)) + +#define IS_PWM_CCR(__CCR__) ((__CCR__) < 0x10000U) + +#define IS_PWM_CHANNEL(__CHANNEL__) (((__CHANNEL__) == PWM_CHANNEL_0) ||\ + ((__CHANNEL__) == PWM_CHANNEL_1) ||\ + ((__CHANNEL__) == PWM_CHANNEL_2)) + +#define IS_PWM_OUTLINE(__OUTLINE__) ((((__OUTLINE__) & PWM_OLINE_Msk) != 0U) &&\ + (((__OUTLINE__) & ~PWM_OLINE_Msk) == 0U)) + +#define IS_PWM_OUTSEL(__OUTSEL__) (((__OUTSEL__) == PWM0_OUT0) ||\ + ((__OUTSEL__) == PWM0_OUT1) ||\ + ((__OUTSEL__) == PWM0_OUT2) ||\ + ((__OUTSEL__) == PWM1_OUT0) ||\ + ((__OUTSEL__) == PWM1_OUT1) ||\ + ((__OUTSEL__) == PWM1_OUT2) ||\ + ((__OUTSEL__) == PWM2_OUT0) ||\ + ((__OUTSEL__) == PWM2_OUT1) ||\ + ((__OUTSEL__) == PWM2_OUT2) ||\ + ((__OUTSEL__) == PWM3_OUT0) ||\ + ((__OUTSEL__) == PWM3_OUT1) ||\ + ((__OUTSEL__) == PWM3_OUT2)) + +#define IS_PWM_OUTLVL(__OUTLVL__) (((__OUTLVL__) == PWM_LEVEL_HIGH) ||\ + ((__OUTLVL__) == PWM_LEVEL_LOW)) + +/* Exported Functions ------------------------------------------------------- */ +/* PWM Exported Functions Group1: + Initialization ----------------------------*/ +void PWM_BaseInit(PWM_TypeDef *PWMx, PWM_BaseInitType *InitStruct); +void PWM_BaseStructInit(PWM_BaseInitType *InitStruct); +void PWM_OC0Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType); +void PWM_OC1Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType); +void PWM_OC2Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType); +void PWM_OCStructInit(PWM_OCInitType *OCInitType); +/* PWM Exported Functions Group2: + Interrupt ---------------------------------*/ +void PWM_BaseINTConfig(PWM_TypeDef *PWMx, uint32_t NewState); +uint8_t PWM_GetBaseINTStatus(PWM_TypeDef *PWMx); +void PWM_ClearBaseINTStatus(PWM_TypeDef *PWMx); +void PWM_ChannelINTConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState); +uint8_t PWM_GetChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel); +void PWM_ClearChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel); +/* PWM Exported Functions Group3: + MISC --------------------------------------*/ +void PWM_ClearCounter(PWM_TypeDef *PWMx); +void PWM_CCRConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint16_t Period); +//Compare output +void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine); +void PWM_OutputCmd(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState); +void PWM_SetOutLevel(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t Level); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_PWM_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_rtc.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_rtc.h new file mode 100644 index 0000000000..fff229bb2c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_rtc.h @@ -0,0 +1,198 @@ +/** + ****************************************************************************** + * @file lib_rtc.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief RTC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_RTC_H +#define __LIB_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +/* RTC Time struct */ +typedef struct +{ + uint32_t Year; + uint32_t Month; + uint32_t Date; + uint32_t WeekDay; + uint32_t Hours; + uint32_t Minutes; + uint32_t Seconds; +} RTC_TimeTypeDef; + +//INT +#define RTC_INT_CEILLE RTC_INTEN_INTEN8 +#define RTC_INT_ACDONE RTC_INTEN_INTEN7 +#define RTC_INT_WKUCNT RTC_INTEN_INTEN6 +#define RTC_INT_MIDNIGHT RTC_INTEN_INTEN5 +#define RTC_INT_WKUHOUR RTC_INTEN_INTEN4 +#define RTC_INT_WKUMIN RTC_INTEN_INTEN3 +#define RTC_INT_WKUSEC RTC_INTEN_INTEN2 +#define RTC_INT_TIMEILLE RTC_INTEN_INTEN1 +#define RTC_INT_Msk (0x1FEUL) + +//INTSTS +#define RTC_INTSTS_CEILLE RTC_INTSTS_INTSTS8 +#define RTC_INTSTS_ACDONE RTC_INTSTS_INTSTS7 +#define RTC_INTSTS_WKUCNT RTC_INTSTS_INTSTS6 +#define RTC_INTSTS_MIDNIGHT RTC_INTSTS_INTSTS5 +#define RTC_INTSTS_WKUHOUR RTC_INTSTS_INTSTS4 +#define RTC_INTSTS_WKUMIN RTC_INTSTS_INTSTS3 +#define RTC_INTSTS_WKUSEC RTC_INTSTS_INTSTS2 +#define RTC_INTSTS_TIMEILLE RTC_INTSTS_INTSTS1 +#define RTC_INTSTS_Msk (0x1FEUL) + +/* RTC AutoCal struct */ +typedef struct +{ + uint32_t Period; + uint32_t ATDelay; + uint32_t ATClockSource; + uint32_t ADCSource; +} RTC_AutCalType; +//ATDelay +#define RTC_ATDELAY_15MS RTC_ACCTRL_ACDEL_0 +#define RTC_ATDELAY_31MS RTC_ACCTRL_ACDEL_1 +#define RTC_ATDELAY_62MS RTC_ACCTRL_ACDEL_2 +#define RTC_ATDELAY_125MS RTC_ACCTRL_ACDEL_3 +//ATClockSource +#define RTC_ATCS_DISABLE RTC_ACCTRL_ACCLK_0 +#define RTC_ATCS_SEC RTC_ACCTRL_ACCLK_1 +#define RTC_ATCS_MIN RTC_ACCTRL_ACCLK_2 +#define RTC_ATCS_HOUR RTC_ACCTRL_ACCLK_3 +//ADCSource +#define RTC_ADCS_DATA (0) +#define RTC_ADCS_PORT RTC_ACCTRL_ADCSEL + +//CNTCLK +#define RTC_WKUCNT_RTCCLK RTC_WKUCNT_CNTSEL_0 +#define RTC_WKUCNT_2048 RTC_WKUCNT_CNTSEL_1 +#define RTC_WKUCNT_512 RTC_WKUCNT_CNTSEL_2 +#define RTC_WKUCNT_128 RTC_WKUCNT_CNTSEL_3 + +//Prescaler +#define RTC_CLKDIV_1 RTC_PSCA_PSCA_0 +#define RTC_CLKDIV_4 RTC_PSCA_PSCA_1 + +/* Private macros ------------------------------------------------------------*/ +#define IS_RTC_REGOP_STARTADDR(__STARTADDR__) (((__STARTADDR__) & 0x3U) == 0U) +/* Year 0 ~ 99 */ +#define IS_RTC_TIME_YEAR(__YEAR__) ((__YEAR__) < 0x9AU) +/* Month 1 ~ 12 */ +#define IS_RTC_TIME_MONTH(__MONTH__) (((__MONTH__) > 0x0U) && ((__MONTH__) < 0x13U)) +/* Date 1 ~ 31 */ +#define IS_RTC_TIME_DATE(__DATE__) (((__DATE__) > 0x0U) && ((__DATE__) < 0x32)) +/* Weekday 0 ~ 6 */ +#define IS_RTC_TIME_WEEKDAY(__WEEKDAY__) ((__WEEKDAY__) < 0x7U) +/* Hours 0 ~ 23 */ +#define IS_RTC_TIME_HOURS(__HOURS__) ((__HOURS__) < 0x24) +/* Minutes 0 ~ 59 */ +#define IS_RTC_TIME_MINS(__MINS__) ((__MINS__) < 0x5A) +/* Seconds 0 ~ 59 */ +#define IS_RTC_TIME_SECS(__SECS__) ((__SECS__) < 0x5A) + +#define IS_RTC_INT(__INT__) ((((__INT__) & RTC_INT_Msk) != 0U) &&\ + (((__INT__) & ~RTC_INT_Msk) == 0U)) + +#define IS_RTC_INTFLAGR(__INTFLAGR_) (((__INTFLAGR_) == RTC_INTSTS_CEILLE) ||\ + ((__INTFLAGR_) == RTC_INTSTS_ACDONE) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUCNT) ||\ + ((__INTFLAGR_) == RTC_INTSTS_MIDNIGHT) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUHOUR) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUMIN) ||\ + ((__INTFLAGR_) == RTC_INTSTS_WKUSEC) ||\ + ((__INTFLAGR_) == RTC_INTSTS_TIMEILLE)) + +#define IS_RTC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & RTC_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~RTC_INTSTS_Msk) == 0U)) + +#define IS_RTC_AUTOCAL_RELOAD(__RELOAD__) (((__RELOAD__) == RTC_AUTORELOAD_DISABLE) ||\ + ((__RELOAD__) == RTC_AUTORELOAD_ENABLE)) + +#define IS_RTC_AUTOCAL_ATDLY(__ATDLY__) (((__ATDLY__) == RTC_ATDELAY_15MS) ||\ + ((__ATDLY__) == RTC_ATDELAY_31MS) ||\ + ((__ATDLY__) == RTC_ATDELAY_62MS) ||\ + ((__ATDLY__) == RTC_ATDELAY_125MS)) + +#define IS_RTC_AUTOCAL_ATCS(__ATCS__) (((__ATCS__) == RTC_ATCS_DISABLE) ||\ + ((__ATCS__) == RTC_ATCS_SEC) ||\ + ((__ATCS__) == RTC_ATCS_MIN) ||\ + ((__ATCS__) == RTC_ATCS_HOUR)) + +#define IS_RTC_AUTOCAL_ADCSRC(__ADCSRC__) (((__ADCSRC__) == RTC_ADCS_DATA) ||\ + ((__ADCSRC__) == RTC_ADCS_PORT)) + +#define IS_RTC_AUTOCAL_PERIOD(__PERIOD__) ((__PERIOD__) < 64U) + +#define IS_RTC_WKUSEC_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUMIN_PERIOD(__PERIOD__) (((__PERIOD__) < 0x41U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUHOUR_PERIOD(__PERIOD__) (((__PERIOD__) < 0x21U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUCNT_PERIOD(__PERIOD__) (((__PERIOD__) < 0x1000001U) && ((__PERIOD__) > 0U)) + +#define IS_RTC_WKUCNT_CNTSEL(__CNTSEL__) (((__CNTSEL__) == RTC_WKUCNT_RTCCLK) ||\ + ((__CNTSEL__) == RTC_WKUCNT_2048) ||\ + ((__CNTSEL__) == RTC_WKUCNT_512) ||\ + ((__CNTSEL__) == RTC_WKUCNT_128)) + +#define IS_RTC_CLKDIV(__CLKDIV__) (((__CLKDIV__) == RTC_CLKDIV_1) ||\ + ((__CLKDIV__) == RTC_CLKDIV_4)) + +/* Exported Functions ------------------------------------------------------- */ +/* RTC Exported Functions Group1: + Time functions -----------------------------*/ +void RTC_SetTime(RTC_TimeTypeDef *sTime); +void RTC_GetTime(RTC_TimeTypeDef *gTime); +/* RTC Exported Functions Group2: + Registers operation functions --------------*/ +void RTC_WriteProtection(uint32_t NewState); +void RTC_WaitForSynchro(void); +void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len); +void RTC_ReadRegisters(uint32_t StartAddr, uint32_t *rBuffer, uint8_t Len); +/* RTC Exported Functions Group3: + Interrupt functions ------------------------*/ +void RTC_INTConfig(uint32_t INTMask, uint32_t NewState); +uint8_t RTC_GetINTStatus(uint32_t FlagMask); +void RTC_ClearINTStatus(uint32_t FlagMask); +/* RTC Exported Functions Group4: + AutoCal functions --------------------------*/ +void RTC_AutoCalStructInit(RTC_AutCalType *RTCAC_InitStruct); +void RTC_AutoCalInit(RTC_AutCalType *InitStruct); +void RTC_TrigSourceConfig(uint32_t TrigSource, uint32_t Period); +uint32_t RTC_AutoCalCmd(uint32_t NewState); +void RTC_StartAutoCalManual(void); +void RTC_WaitForAutoCalManual(void); +uint8_t RTC_GetACBusyFlag(void); +/* RTC Exported Functions Group5: + Wake-up functions --------------------------*/ +void RTC_WKUSecondsConfig(uint8_t nPeriod); +void RTC_WKUMinutesConfig(uint8_t nPeriod); +void RTC_WKUHoursConfig(uint8_t nPeriod); +void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK); +uint32_t RTC_GetWKUCounterValue(void); +/* RTC Exported Functions Group6: + MISC functions -----------------------------*/ +void RTC_PrescalerConfig(uint32_t Prescaler); +void RTC_PLLDIVConfig(uint32_t nfrequency); +void RTC_PLLDIVOutputCmd(uint8_t NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_RTC_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_spi.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_spi.h new file mode 100644 index 0000000000..89c3568c6c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_spi.h @@ -0,0 +1,180 @@ +/** + ****************************************************************************** + * @file lib_spi.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief SPI library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_SPI_H +#define __LIB_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Mode; + uint32_t SPH; + uint32_t SPO; + uint32_t ClockDivision; + uint32_t CSNSoft; + uint32_t SWAP; +} SPI_InitType; +//Mode +#define SPI_MODE_MASTER 0 +#define SPI_MODE_SLAVE SPI_CTRL_MOD +//SPH +#define SPI_SPH_0 0 +#define SPI_SPH_1 SPI_CTRL_SCKPHA +//SPO +#define SPI_SPO_0 0 +#define SPI_SPO_1 SPI_CTRL_SCKPOL +//ClockDivision +#define SPI_CLKDIV_2 (0) +#define SPI_CLKDIV_4 (SPI_CTRL_SCKSEL_0) +#define SPI_CLKDIV_8 (SPI_CTRL_SCKSEL_1) +#define SPI_CLKDIV_16 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_1) +#define SPI_CLKDIV_32 (SPI_CTRL_SCKSEL_2) +#define SPI_CLKDIV_64 (SPI_CTRL_SCKSEL_0 | SPI_CTRL_SCKSEL_2) +#define SPI_CLKDIV_128 (SPI_CTRL_SCKSEL_1 | SPI_CTRL_SCKSEL_2) +//CSNSoft +#define SPI_CSNSOFT_ENABLE SPI_CTRL_CSGPIO +#define SPI_CSNSOFT_DISABLE 0 +//SWAP +#define SPI_SWAP_ENABLE SPI_CTRL_SWAP +#define SPI_SWAP_DISABLE 0 + +//INT +#define SPI_INT_TX (0x80000000|SPI_TXSTS_TXIEN) +#define SPI_INT_RX (0x40000000|SPI_RXSTS_RXIEN) + +//status +#define SPI_STS_TXIF (0x80000000|SPI_TXSTS_TXIF) +#define SPI_STS_TXEMPTY (0x80000000|SPI_TXSTS_TXEMPTY) +#define SPI_STS_TXFUR (0x80000000|SPI_TXSTS_TXFUR) +#define SPI_STS_RXIF (0x40000000|SPI_RXSTS_RXIF) +#define SPI_STS_RXFULL (0x40000000|SPI_RXSTS_RXFULL) +#define SPI_STS_RXFOV (0x40000000|SPI_RXSTS_RXFOV) +#define SPI_STS_BSY (0x20000000|SPI_MISC_BSY) +#define SPI_STS_RFF (0x20000000|SPI_MISC_RFF) +#define SPI_STS_RNE (0x20000000|SPI_MISC_RNE) +#define SPI_STS_TNF (0x20000000|SPI_MISC_TNF) +#define SPI_STS_TFE (0x20000000|SPI_MISC_TFE) + +//TXFLEV +#define SPI_TXFLEV_0 (0) +#define SPI_TXFLEV_1 (SPI_TXSTS_TXFLEV_0) +#define SPI_TXFLEV_2 (SPI_TXSTS_TXFLEV_1) +#define SPI_TXFLEV_3 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1) +#define SPI_TXFLEV_4 (SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_5 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_6 (SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2) +#define SPI_TXFLEV_7 (SPI_TXSTS_TXFLEV_0 | SPI_TXSTS_TXFLEV_1 | SPI_TXSTS_TXFLEV_2) + +//RXFLEV +#define SPI_RXFLEV_0 (0) +#define SPI_RXFLEV_1 (SPI_RXSTS_RXFLEV_0) +#define SPI_RXFLEV_2 (SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_3 (SPI_RXSTS_RXFLEV_0 | SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_4 (SPI_RXSTS_RXFLEV_2) +#define SPI_RXFLEV_5 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_0) +#define SPI_RXFLEV_6 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1) +#define SPI_RXFLEV_7 (SPI_RXSTS_RXFLEV_2 | SPI_RXSTS_RXFLEV_1 | SPI_RXSTS_RXFLEV_0) + + +/* Private macros ------------------------------------------------------------*/ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_MASTER) || ((__MODE__) == SPI_MODE_SLAVE)) + +#define IS_SPI_SPH(__SPH__) (((__SPH__) == SPI_SPH_0) || ((__SPH__) == SPI_SPH_1)) + +#define IS_SPI_SPO(__SPO__) (((__SPO__) == SPI_SPO_0) || ((__SPO__) == SPI_SPO_1)) + +#define IS_SPI_CLKDIV(__CLKDIV__) (((__CLKDIV__) == SPI_CLKDIV_2) ||\ + ((__CLKDIV__) == SPI_CLKDIV_4) ||\ + ((__CLKDIV__) == SPI_CLKDIV_8) ||\ + ((__CLKDIV__) == SPI_CLKDIV_16) ||\ + ((__CLKDIV__) == SPI_CLKDIV_32) ||\ + ((__CLKDIV__) == SPI_CLKDIV_64) ||\ + ((__CLKDIV__) == SPI_CLKDIV_128)) + +#define IS_SPI_CSN(__CSN__) (((__CSN__) == SPI_CSNSOFT_ENABLE) || ((__CSN__) == SPI_CSNSOFT_DISABLE)) + +#define IS_SPI_SWAP(__SWAP__) (((__SWAP__) == SPI_SWAP_ENABLE) || ((__SWAP__) == SPI_SWAP_DISABLE)) + +#define IS_SPI_INT(__INT__) ((((__INT__) & (SPI_INT_TX | SPI_INT_RX)) != 0U) &&\ + (((__INT__) & ~(SPI_INT_TX | SPI_INT_RX)) == 0U)) + +#define IS_SPI_STSR(__STSR__) (((__STSR__) == SPI_STS_TXIF) ||\ + ((__STSR__) == SPI_STS_TXEMPTY) ||\ + ((__STSR__) == SPI_STS_TXFUR) ||\ + ((__STSR__) == SPI_STS_RXFULL) ||\ + ((__STSR__) == SPI_STS_RXFOV) ||\ + ((__STSR__) == SPI_STS_BSY) ||\ + ((__STSR__) == SPI_STS_RFF) ||\ + ((__STSR__) == SPI_STS_RNE) ||\ + ((__STSR__) == SPI_STS_TNF) ||\ + ((__STSR__) == SPI_STS_TFE) ||\ + ((__STSR__) == SPI_STS_RXIF)) + +#define IS_SPI_STSC(__STSC__) ((((__STSC__) & (SPI_STS_TXIF | SPI_STS_RXIF)) != 0U) &&\ + (((__STSC__) & ~(SPI_STS_TXIF | SPI_STS_RXIF)) == 0U)) + +#define IS_SPI_TXFLEV(__TXFLEV__) (((__TXFLEV__) == SPI_TXFLEV_0) ||\ + ((__TXFLEV__) == SPI_TXFLEV_1) ||\ + ((__TXFLEV__) == SPI_TXFLEV_2) ||\ + ((__TXFLEV__) == SPI_TXFLEV_3) ||\ + ((__TXFLEV__) == SPI_TXFLEV_4) ||\ + ((__TXFLEV__) == SPI_TXFLEV_5) ||\ + ((__TXFLEV__) == SPI_TXFLEV_6) ||\ + ((__TXFLEV__) == SPI_TXFLEV_7)) + +#define IS_SPI_RXFLEV(__RXFLEV__) (((__RXFLEV__) == SPI_RXFLEV_0) ||\ + ((__RXFLEV__) == SPI_RXFLEV_1) ||\ + ((__RXFLEV__) == SPI_RXFLEV_2) ||\ + ((__RXFLEV__) == SPI_RXFLEV_3) ||\ + ((__RXFLEV__) == SPI_RXFLEV_4) ||\ + ((__RXFLEV__) == SPI_RXFLEV_5) ||\ + ((__RXFLEV__) == SPI_RXFLEV_6) ||\ + ((__RXFLEV__) == SPI_RXFLEV_7)) + +/* Exported Functions ------------------------------------------------------- */ +/* SPI Exported Functions Group1: + (De)Initialization -------------------------*/ +void SPI_DeviceInit(SPI_TypeDef *SPIx); +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitType *InitStruct); +void SPI_StructInit(SPI_InitType *InitStruct); +/* SPI Exported Functions Group2: + Interrupt (flag) ---------------------------*/ +void SPI_INTConfig(SPI_TypeDef *SPIx, uint32_t INTMask, uint32_t NewState); +uint8_t SPI_GetStatus(SPI_TypeDef *SPIx, uint32_t Status); +void SPI_ClearStatus(SPI_TypeDef *SPIx, uint32_t Status); +/* SPI Exported Functions Group3: + Transfer datas -----------------------------*/ +void SPI_SendData(SPI_TypeDef *SPIx, uint8_t ch); +uint8_t SPI_ReceiveData(SPI_TypeDef *SPIx); +/* SPI Exported Functions Group4: + MISC Configuration -------------------------*/ +void SPI_Cmd(SPI_TypeDef *SPIx, uint32_t NewState); +void SPI_TransmitFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel); +void SPI_ReceiveFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel); +uint8_t SPI_GetTransmitFIFOLevel(SPI_TypeDef *SPIx); +uint8_t SPI_GetReceiveFIFOLevel(SPI_TypeDef *SPIx); +void SPI_SmartModeCmd(SPI_TypeDef *SPIx, uint32_t NewState); +void SPI_OverWriteModeCmd(SPI_TypeDef *SPIx, uint32_t NewState); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_SPI_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h new file mode 100644 index 0000000000..f377ae1746 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_tmr.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file lib_tmr.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Timer library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_TMR_H +#define __LIB_TMR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Period; + uint32_t ClockSource; + uint32_t EXTGT; +} TMR_InitType; +//ClockSource +#define TMR_CLKSRC_INTERNAL 0 +#define TMR_CLKSRC_EXTERNAL TMR_CTRL_EXTCLK +//ClockGate +#define TMR_EXTGT_DISABLE 0 +#define TMR_EXTGT_ENABLE TMR_CTRL_EXTEN + +/* Private macros ------------------------------------------------------------*/ +#define IS_TMR_CLKSRC(__CLKSRC__) (((__CLKSRC__) == TMR_CLKSRC_INTERNAL) || ((__CLKSRC__) == TMR_CLKSRC_EXTERNAL)) + +#define IS_TMR_EXTGT(__EXTGT__) (((__EXTGT__) == TMR_EXTGT_DISABLE) || ((__EXTGT__) == TMR_EXTGT_ENABLE)) + + +/* Exported Functions ------------------------------------------------------- */ +/* Timer Exported Functions Group1: + (De)Initialization ----------------------*/ +void TMR_DeInit(TMR_TypeDef *TMRx); +void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct); +void TMR_StructInit(TMR_InitType *InitStruct); +/* Timer Exported Functions Group2: + Interrupt (flag) -------------------------*/ +void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState); +uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx); +void TMR_ClearINTStatus(TMR_TypeDef *TMRx); +/* Timer Exported Functions Group3: + MISC Configuration -----------------------*/ +void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState); +uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_TMR_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_u32k.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_u32k.h new file mode 100644 index 0000000000..c396da28ed --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_u32k.h @@ -0,0 +1,142 @@ +/** + ****************************************************************************** + * @file lib_u32k.h + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief UART 32K library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_U32K_H +#define __LIB_U32K_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +typedef struct +{ + uint32_t Debsel; + uint32_t Parity; + uint32_t WordLen; + uint32_t FirstBit; + uint32_t AutoCal; + uint32_t Baudrate; + uint32_t LineSel; +} U32K_InitType; +//Debsel +#define U32K_DEBSEL_0 U32K_CTRL0_DEBSEL_0 +#define U32K_DEBSEL_1 U32K_CTRL0_DEBSEL_1 +#define U32K_DEBSEL_2 U32K_CTRL0_DEBSEL_2 +#define U32K_DEBSEL_3 U32K_CTRL0_DEBSEL_3 +//Parity +#define U32K_PARITY_EVEN U32K_CTRL0_PMODE_EVEN +#define U32K_PARITY_ODD U32K_CTRL0_PMODE_ODD +#define U32K_PARITY_0 U32K_CTRL0_PMODE_0 +#define U32K_PARITY_1 U32K_CTRL0_PMODE_1 +#define U32K_PARITY_NONE 0 +//WordLen +#define U32K_WORDLEN_8B 0 +#define U32K_WORDLEN_9B U32K_CTRL0_MODE +//FirstBit +#define U32K_FIRSTBIT_LSB 0 +#define U32K_FIRSTBIT_MSB U32K_CTRL0_MSB +//AutoCal +#define U32K_AUTOCAL_ON 0 +#define U32K_AUTOCAL_OFF U32K_CTRL0_ACOFF +//Line +#define U32K_LINE_RX0 U32K_CTRL1_RXSEL_RX0 +#define U32K_LINE_RX1 U32K_CTRL1_RXSEL_RX1 +#define U32K_LINE_RX2 U32K_CTRL1_RXSEL_RX2 +#define U32K_LINE_RX3 U32K_CTRL1_RXSEL_RX3 + +//INT +#define U32K_INT_RXOV U32K_CTRL1_RXOVIE +#define U32K_INT_RXPE U32K_CTRL1_RXPEIE +#define U32K_INT_RX U32K_CTRL1_RXIE +#define U32K_INT_Msk (U32K_INT_RXOV \ + |U32K_INT_RXPE \ + |U32K_INT_RX) + +//INT Status +#define U32K_INTSTS_RXOV U32K_STS_RXOV +#define U32K_INTSTS_RXPE U32K_STS_RXPE +#define U32K_INTSTS_RX U32K_STS_RXIF +#define U32K_INTSTS_Msk (U32K_INTSTS_RXOV \ + |U32K_INTSTS_RXPE \ + |U32K_INTSTS_RX) + +//WKUMode +#define U32K_WKUMOD_RX 0 // Wake-up when receive data +#define U32K_WKUMOD_PC U32K_CTRL0_WKUMODE // Wake-up when receive data and parity/stop bit correct + +/* Private macros ------------------------------------------------------------*/ +#define IS_U32K_DEBSEL(__DEBSEL__) (((__DEBSEL__) == U32K_DEBSEL_0) ||\ + ((__DEBSEL__) == U32K_DEBSEL_1) ||\ + ((__DEBSEL__) == U32K_DEBSEL_2) ||\ + ((__DEBSEL__) == U32K_DEBSEL_3)) + +#define IS_U32K_PARITY(__PARITY__) (((__PARITY__) == U32K_PARITY_EVEN) ||\ + ((__PARITY__) == U32K_PARITY_ODD) ||\ + ((__PARITY__) == U32K_PARITY_0) ||\ + ((__PARITY__) == U32K_PARITY_1) ||\ + ((__PARITY__) == U32K_PARITY_NONE)) + +#define IS_U32K_WORDLEN(__WORDLEN__) (((__WORDLEN__) == U32K_WORDLEN_8B) || ((__WORDLEN__) == U32K_WORDLEN_9B)) + +#define IS_U32K_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == U32K_FIRSTBIT_LSB) || ((__FIRSTBIT__) == U32K_FIRSTBIT_MSB)) + +#define IS_U32K_AUTOCAL(__AUTOCAL__) (((__AUTOCAL__) == U32K_AUTOCAL_ON) || ((__AUTOCAL__) == U32K_AUTOCAL_OFF)) + +#define IS_U32K_LINE(__LINE__) (((__LINE__) == U32K_LINE_RX0) ||\ + ((__LINE__) == U32K_LINE_RX1) ||\ + ((__LINE__) == U32K_LINE_RX2) ||\ + ((__LINE__) == U32K_LINE_RX3)) + +#define IS_U32K_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9601UL) + +#define IS_U32K_INT(__INT__) ((((__INT__) & U32K_INT_Msk) != 0U) &&\ + (((__INT__) & ~U32K_INT_Msk) == 0U)) + +#define IS_U32K_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == U32K_INTSTS_RXOV) ||\ + ((__INTFLAGR__) == U32K_INTSTS_RXPE) ||\ + ((__INTFLAGR__) == U32K_INTSTS_RX)) + +#define IS_U32K_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & U32K_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~U32K_INTSTS_Msk) == 0U)) + +#define IS_U32K_WKUMODE(__WKUMODE__) (((__WKUMODE__) == U32K_WKUMOD_RX) || ((__WKUMODE__) == U32K_WKUMOD_PC)) + +/* Exported Functions ------------------------------------------------------- */ +/* U32K Exported Functions Group1: + (De)Initialization -----------------------*/ +void U32K_DeInit(U32K_TypeDef *U32Kx); +void U32K_Init(U32K_TypeDef *U32Kx, U32K_InitType *InitStruct); +void U32K_StructInit(U32K_InitType *InitStruct); +/* U32K Exported Functions Group2: + Interrupt (flag) configure ---------------*/ +void U32K_INTConfig(U32K_TypeDef *U32Kx, uint32_t INTMask, uint8_t NewState); +uint8_t U32K_GetINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask); +void U32K_ClearINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask); +/* U32K Exported Functions Group3: + Receive datas -----------------------------*/ +uint8_t U32K_ReceiveData(U32K_TypeDef *U32Kx); +/* U32K Exported Functions Group4: + MISC Configuration -------- ---------------*/ +void U32K_BaudrateConfig(U32K_TypeDef *U32Kx, uint32_t BaudRate); +void U32K_Cmd(U32K_TypeDef *U32Kx, uint32_t NewState); +void U32K_LineConfig(U32K_TypeDef *U32Kx, uint32_t Line); +void U32K_WKUModeConfig(U32K_TypeDef *U32Kx, uint32_t WKUMode); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_U32K_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_uart.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_uart.h new file mode 100644 index 0000000000..3839c2e67f --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_uart.h @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file lib_uart.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief UART library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_UART_H +#define __LIB_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +//UART Init struct +typedef struct +{ + uint32_t Mode; + uint32_t Parity; + uint32_t WordLen; + uint32_t FirstBit; + uint32_t Baudrate; +} UART_InitType; +//Mode +#define UART_MODE_RX UART_CTRL_RXEN +#define UART_MODE_TX UART_CTRL_TXEN +#define UART_MODE_OFF 0 +#define UART_MODE_Msk (UART_CTRL_RXEN | UART_CTRL_TXEN) +//Parity +#define UART_PARITY_EVEN UART_CTRL2_PMODE_EVEN +#define UART_PARITY_ODD UART_CTRL2_PMODE_ODD +#define UART_PARITY_0 UART_CTRL2_PMODE_0 +#define UART_PARITY_1 UART_CTRL2_PMODE_1 +#define UART_PARITY_NONE 0 +//WordLen +#define UART_WORDLEN_8B 0 +#define UART_WORDLEN_9B UART_CTRL2_MODE +//FirstBit +#define UART_FIRSTBIT_LSB 0 +#define UART_FIRSTBIT_MSB UART_CTRL2_MSB + +//UART Configration Information struct +typedef struct +{ + uint32_t Mode_Transmit :1; //1: TX Enable; 0: TX Disable + uint32_t Mode_Receive :1; //1: RX Enable; 0: RX Disable + uint32_t Baudrate; //The value of current budrate + uint8_t Parity; //0: parity bit=0; 1: parity bit=1; 2: Even parity; 3:Odd parity + uint8_t WordLen; //8: data bits=8; 9: data bits=9 + uint8_t FirstBit; //0: LSB transmit first; 1: MSB transmit first +} UART_ConfigINFOType; + +//status +#define UART_FLAG_RXPARITY UART_STATE_RXPSTS +#define UART_FLAG_TXDONE UART_STATE_TXDONE +#define UART_FLAG_RXPE UART_STATE_RXPE +#define UART_FLAG_RXOV UART_STATE_RXOV +#define UART_FLAG_TXOV UART_STATE_TXOV +#define UART_FLAG_RXFULL UART_STATE_RXFULL +#define UART_FLAG_RCMsk (UART_FLAG_TXDONE \ + |UART_FLAG_RXPE \ + |UART_FLAG_RXOV \ + |UART_STATE_RXFULL\ + |UART_FLAG_TXOV) + +//interrupt +#define UART_INT_TXDONE UART_CTRL_TXDONEIE +#define UART_INT_RXPE UART_CTRL_RXPEIE +#define UART_INT_RXOV UART_CTRL_RXOVIE +#define UART_INT_TXOV UART_CTRL_TXOVIE +#define UART_INT_RX UART_CTRL_RXIE +#define UART_INT_Msk (UART_INT_TXDONE \ + |UART_INT_RXPE \ + |UART_INT_RXOV \ + |UART_INT_TXOV \ + |UART_INT_RX) + +//INTStatus +#define UART_INTSTS_TXDONE UART_INTSTS_TXDONEIF +#define UART_INTSTS_RXPE UART_INTSTS_RXPEIF +#define UART_INTSTS_RXOV UART_INTSTS_RXOVIF +#define UART_INTSTS_TXOV UART_INTSTS_TXOVIF +#define UART_INTSTS_RX UART_INTSTS_RXIF +#define UART_INTSTS_Msk (UART_INTSTS_TXDONE \ + |UART_INTSTS_RXPE \ + |UART_INTSTS_RXOV \ + |UART_INTSTS_TXOV \ + |UART_INTSTS_RX) + +/* Private macros ------------------------------------------------------------*/ +#define IS_UART_MODE(__MODE__) (((((__MODE__) & UART_MODE_Msk) != 0U) && (((__MODE__) & ~UART_MODE_Msk) == 0U)) ||\ + ((__MODE__) == UART_MODE_OFF)) + +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_EVEN) ||\ + ((__PARITY__) == UART_PARITY_ODD) ||\ + ((__PARITY__) == UART_PARITY_0) ||\ + ((__PARITY__) == UART_PARITY_1) ||\ + ((__PARITY__) == UART_PARITY_NONE)) + +#define IS_UART_WORDLEN(__WORDLEN__) (((__WORDLEN__) == UART_WORDLEN_8B) ||\ + ((__WORDLEN__) == UART_WORDLEN_9B)) + +#define IS_UART_FIRSTBIT(__FIRSTBIT__) (((__FIRSTBIT__) == UART_FIRSTBIT_LSB) ||\ + ((__FIRSTBIT__) == UART_FIRSTBIT_MSB)) + +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 0x100000UL) + +#define IS_UART_FLAGR(__FLAGR__) (((__FLAGR__) == UART_FLAG_RXPARITY) ||\ + ((__FLAGR__) == UART_FLAG_TXDONE) ||\ + ((__FLAGR__) == UART_FLAG_RXPE) ||\ + ((__FLAGR__) == UART_FLAG_RXOV) ||\ + ((__FLAGR__) == UART_FLAG_TXOV) ||\ + ((__FLAGR__) == UART_FLAG_RXFULL)) + +#define IS_UART_FLAGC(__FLAGC__) ((((__FLAGC__) & UART_FLAG_RCMsk) != 0U) &&\ + (((__FLAGC__) & ~UART_FLAG_RCMsk) == 0U)) + +#define IS_UART_INT(__INT__) ((((__INT__) & UART_INT_Msk) != 0U) &&\ + (((__INT__) & ~UART_INT_Msk) == 0U)) + +#define IS_UART_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == UART_INTSTS_TXDONE) ||\ + ((__INTFLAGR__) == UART_INTSTS_RXPE) ||\ + ((__INTFLAGR__) == UART_INTSTS_RXOV) ||\ + ((__INTFLAGR__) == UART_INTSTS_TXOV) ||\ + ((__INTFLAGR__) == UART_INTSTS_RX)) + +#define IS_UART_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & UART_INTSTS_Msk) != 0U) &&\ + (((__INTFLAGC__) & ~UART_INTSTS_Msk) == 0U)) + +/* Exported Functions ------------------------------------------------------- */ +/* UART Exported Functions Group1: + Initialization and functions --------------*/ +void UART_DeInit(UART_TypeDef *UARTx); +void UART_Init(UART_TypeDef *UARTx, UART_InitType *InitStruct); +void UART_StructInit(UART_InitType *InitStruct); +/* UART Exported Functions Group2: + (Interrupt) Flag --------------------------*/ +uint8_t UART_GetFlag(UART_TypeDef *UARTx, uint32_t FlagMask); +void UART_ClearFlag(UART_TypeDef *UARTx, uint32_t FlagMask); +void UART_INTConfig(UART_TypeDef *UARTx, uint32_t INTMask, uint8_t NewState); +uint8_t UART_GetINTStatus(UART_TypeDef *UARTx, uint32_t INTMask); +void UART_ClearINTStatus(UART_TypeDef *UARTx, uint32_t INTMask); +/* UART Exported Functions Group3: + Transfer datas ----------------------------*/ +void UART_SendData(UART_TypeDef *UARTx, uint8_t ch); +uint8_t UART_ReceiveData(UART_TypeDef *UARTx); +/* UART Exported Functions Group4: + MISC Configuration ------------------------*/ +void UART_BaudrateConfig(UART_TypeDef *UARTx, uint32_t BaudRate); +void UART_Cmd(UART_TypeDef *UARTx, uint32_t Mode, uint32_t NewState); +void UART_GetConfigINFO(UART_TypeDef *UARTx, UART_ConfigINFOType *ConfigInfo); + + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_UART_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_version.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_version.h new file mode 100644 index 0000000000..0bc51b303d --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_version.h @@ -0,0 +1,36 @@ +/** +******************************************************************************* +* @file lib_version.h +* @author Application Team +* @version V4.5.0 +* @date 2019-05-14 +* @brief Version library. +*******************************************************************************/ + +#ifndef __LIB_VERSION_H +#define __LIB_VERSION_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor)) + +/* Exported Functions ------------------------------------------------------- */ + +/** + * @brief Read receive data register. + * @param None + * @retval Version value + */ +uint16_t Target_GetDriveVersion(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_VERSION_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_wdt.h b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_wdt.h new file mode 100644 index 0000000000..ab02db6473 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Include/lib_wdt.h @@ -0,0 +1,46 @@ +/** + ****************************************************************************** + * @file lib_wdt.h + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief WDT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#ifndef __LIB_WDT_H +#define __LIB_WDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "target.h" + +#define WDT_2_SECS PMU_WDTEN_WDTSEL_0 +#define WDT_1_SECS PMU_WDTEN_WDTSEL_1 +#define WDT_0_5_SECS PMU_WDTEN_WDTSEL_2 +#define WDT_0_25_SECS PMU_WDTEN_WDTSEL_3 + +/* Private macros ------------------------------------------------------------*/ +#define IS_WDT_PERIOD(__PERIOD__) (((__PERIOD__) == WDT_2_SECS) ||\ + ((__PERIOD__) == WDT_1_SECS) ||\ + ((__PERIOD__) == WDT_0_5_SECS) ||\ + ((__PERIOD__) == WDT_0_25_SECS)) + +/* Exported Functions ------------------------------------------------------- */ +void WDT_Enable(void); +void WDT_Disable(void); +void WDT_Clear(void); +void WDT_SetPeriod(uint32_t period); +uint16_t WDT_GetCounterValue(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LIB_WDT_H */ + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc.c new file mode 100644 index 0000000000..c37213d70c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc.c @@ -0,0 +1,977 @@ +/** + ****************************************************************************** + * @file lib_adc.c + * @author Application Team + * @version V4.6.0 + * @date 2019-06-18 + * @brief ADC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_adc.h" + +extern __IO uint32_t ana_reg3_tmp; +#define ANA_REG1_RSTValue (0U) +#define ANA_ADCCTRL_RSTValue (0U) + +/** + * @brief Initializes ADC peripheral registers to their default reset values. + * @note 1. Disable ADC + 2. Disable ADC overall bias current trim + 3. Disable resistor/cap division. + 4. Disable ADC auto/manual done interrupt + 5. ANA_ADCCTRL(register) write default value. + * @param None + * @retval None + */ +void ADC_DeInit(void) +{ + /* Power down ADC */ + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + /* Disable resistor/cap division. */ + ANA->REG1 = ANA_REG1_RSTValue; + /* Disable interrupt, Clear interrupt flag */ + ANA->INTEN &= ~(ANA_INTEN_INTEN0 | ANA_INTEN_INTEN1); + ANA->INTSTS = (ANA_INTSTS_INTSTS0 | ANA_INTSTS_INTSTS1); + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = ANA_ADCCTRL_RSTValue; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct: pointer to an ADCInitType structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADCInitType* ADC_InitStruct) +{ + /*--------------- Reset ADC init structure parameters values ---------------*/ + /* Initialize the ClockSource member */ + ADC_InitStruct->ClockSource = ADC_CLKSRC_RCH; + /* Initialize the Channel member */ + ADC_InitStruct->Channel = ADC_CHANNEL0; + /* Initialize the ClockDivider member */ + ADC_InitStruct->ClockDivider = ADC_CLKDIV_1; + /* Initialize the ConvMode member */ + ADC_InitStruct->ConvMode = ADC_CONVMODE_SINGLECHANNEL; + /* Initialize the TrigMode member */ + ADC_InitStruct->TrigMode = ADC_TRIGMODE_MANUAL; +} + +/** + * @brief ADC initialization. + * @param ADC_InitStruct: + TrigMode: + ADC_TRIGMODE_AUTO + ADC_TRIGMODE_MANUAL + ConvMode: + ADC_CONVMODE_SINGLECHANNEL + ADC_CONVMODE_MULTICHANNEL + ClockSource: + ADC_CLKSRC_RCH + ADC_CLKSRC_PLLL + ClockDivider: + ADC_CLKDIV_1 + ADC_CLKDIV_2 + ADC_CLKDIV_3 + ADC_CLKDIV_4 + ADC_CLKDIV_5 + ADC_CLKDIV_6 + ADC_CLKDIV_7 + ADC_CLKDIV_8 + ADC_CLKDIV_9 + ADC_CLKDIV_10 + ADC_CLKDIV_11 + ADC_CLKDIV_12 + ADC_CLKDIV_13 + ADC_CLKDIV_14 + ADC_CLKDIV_15 + ADC_CLKDIV_16 + Channel:(be valid when ConvMode is ADC_CONVMODE_SINGLECHANNEL) + ADC_CHANNEL0 + ADC_CHANNEL1 + ADC_CHANNEL2 + ADC_CHANNEL3 + ADC_CHANNEL4 + ADC_CHANNEL5 + ADC_CHANNEL6 + ADC_CHANNEL7 + ADC_CHANNEL8 + ADC_CHANNEL9 + ADC_CHANNEL10 + ADC_CHANNEL11 + + * @retval None + */ +void ADC_Init(ADCInitType* ADC_InitStruct) +{ + uint32_t tmp = 0; + + /* Check parameters */ + assert_parameters(IS_ADC_TRIGMODE(ADC_InitStruct->TrigMode)); + assert_parameters(IS_ADC_CONVMODE(ADC_InitStruct->ConvMode)); + assert_parameters(IS_ADC_CLKDIV(ADC_InitStruct->ClockDivider)); + assert_parameters(IS_ADC_CLKSRC(ADC_InitStruct->ClockSource)); + + tmp = ANA->ADCCTRL; + tmp &= ~(ANA_ADCCTRL_AMODE \ + |ANA_ADCCTRL_MMODE \ + |ANA_ADCCTRL_CLKSEL \ + |ANA_ADCCTRL_CLKDIV \ + |ANA_ADCCTRL_AEN \ + |ANA_ADCCTRL_MCH \ + |ANA_ADCCTRL_ACH); + tmp |= (ADC_InitStruct->ClockDivider | ADC_InitStruct->ClockSource); + + if(ADC_InitStruct->TrigMode == ADC_TRIGMODE_AUTO) //Auto mode + { + if(ADC_InitStruct->ConvMode == ADC_CONVMODE_SINGLECHANNEL) //signal channel + { + assert_parameters(IS_ADC_CHANNEL(ADC_InitStruct->Channel)); + tmp &= (~ANA_ADCCTRL_ACH); + tmp |= (ADC_InitStruct->Channel << ANA_ADCCTRL_ACH_Pos); + } + else //multi channels + { + tmp |= ANA_ADCCTRL_AMODE; + } + } + else // Manual mode + { + if(ADC_InitStruct->ConvMode == ADC_CONVMODE_SINGLECHANNEL) //signal channel + { + assert_parameters(IS_ADC_CHANNEL(ADC_InitStruct->Channel)); + tmp &= (~ANA_ADCCTRL_MCH); + tmp |= (ADC_InitStruct->Channel << ANA_ADCCTRL_MCH_Pos); + } + else //multi channels + { + tmp |= ANA_ADCCTRL_MMODE; + } + } + + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief Calculate ADC voltage value(uint:V) via ADC original data. + * @param [in]Mode: + * ADC_3V_EXTERNAL_NODIV + * ADC_3V_EXTERNAL_RESDIV + * ADC_3V_EXTERNAL_CAPDIV + * ADC_3V_VDD_RESDIV + * ADC_3V_VDD_CAPDIV + * ADC_3V_BATRTC_RESDIV + * ADC_3V_BATRTC_CAPDIV + * ADC_5V_EXTERNAL_NODIV + * ADC_5V_EXTERNAL_RESDIV + * ADC_5V_EXTERNAL_CAPDIV + * ADC_5V_VDD_RESDIV + * ADC_5V_VDD_CAPDIV + * ADC_5V_BATRTC_RESDIV + * ADC_5V_BATRTC_CAPDIV + * @param [in]adc_data: The ADC original data + * @param [out]Voltage: The pointer of voltage value calculated by this function + * @retval 1 NVR checksum error. + 0 Function successed. + */ +uint32_t ADC_CalculateVoltage(uint32_t Mode, int16_t adc_data, float *Voltage) +{ + NVR_ADCVOLPARA parameter; + NVR_BATMEARES BAT_OffsetInfo; + + /* Check parameters */ + assert_parameters(IS_ADCVOL_MODE(Mode)); + + if (NVR_GetADCVoltageParameter(Mode, ¶meter)) + { + if ((Mode&0xFUL) > 2UL) /* VDD or BATRTC channel */ + { + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return 1; + } + else + { + if (((Mode&0xFUL) == 3UL) || ((Mode&0xFUL) == 5UL)) /* VDD/BATRTC, Resistive */ + { + *Voltage = (float)(0.00015392*(float)adc_data + 0.06667986) + BAT_OffsetInfo.BATRESResult; + } + else /* VDD/BATRTC, Capacitive */ + { + *Voltage = (float)(0.00014107*(float)adc_data - 0.00699515) + BAT_OffsetInfo.BATCAPResult; + } + } + } + else /* External channel */ + { + if (Mode & 0x100UL) /* Power supply: 5V */ + { + if ((Mode&0xFUL) == 0UL) /* No divider */ + { + *Voltage = (float)(0.00003678*(float)adc_data + 0.00235783); + } + else if ((Mode&0xFUL) == 1UL) /* Resistive */ + { + *Voltage = (float)(0.00016129*(float)adc_data + 0.00673599); + } + else /* Capacitive */ + { + *Voltage = (float)(0.00014076*(float)adc_data - 0.00753319); + } + } + else /* Power supply: 3.3V */ + { + if ((Mode&0xFUL) == 0UL) /* No divider */ + { + *Voltage = (float)(0.00003680*(float)adc_data + 0.00205011); + } + else if ((Mode&0xFUL) == 1UL) /* Resistive */ + { + *Voltage = (float)(0.00016425*(float)adc_data + 0.03739179); + } + else /* Capacitive */ + { + *Voltage = (float)(0.00014051*(float)adc_data - 0.00023322); + } + } + } + } + else + { + *Voltage = (float)(parameter.aParameter*(float)adc_data + parameter.bParameter); + } + + return 0; +} + +/** + * @brief Get VDD Voltage(takes 244us). + * @note This function costs about 170us when SystemClock is 26M. + * ADC data refresh time is 117us. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(VDD channel 1) + * - ADC clock: 3.2M + * - Skip samples: Skip 2 samples + * - Down sampling rate: 1/64 + * @param [in]Division + ADC_BAT_CAPDIV (Cap division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage The value of VDD Voltage + [out]CalResults.BATRTCVoltage is ignored + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetVDDVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + NVR_BATMEARES BAT_OffsetInfo; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = 0x06C00101; + + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + data = ANA->ADCDATA1; + + /* Calculate the voltage of VDD */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->VDDVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->VDDVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get VDD Voltage(takes 3.3ms). + * @note This function costs about 3.3ms when SystemClock is 26M. + * ADC data refresh time is about 3.2ms. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(VDD channel 1) + * - ADC clock: 1.6M + * - Skip samples: Skip first 4 samples + * - Down sampling rate: 1/512 + * @param [in]Division + ADC_BAT_CAPDIV (Cap division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage The value of VDD Voltage + [out]CalResults.BATRTCVoltage is ignored + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetVDDVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + NVR_BATMEARES BAT_OffsetInfo; + ADCInitType ADC_InitStruct; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL; + ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL; + ADC_InitStruct.Channel = ADC_CHANNEL1; + ADC_InitStruct.ClockDivider = ADC_CLKDIV_4; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_Init(&ADC_InitStruct); + + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + + data = ANA->ADCDATA1; + + /* Calculate the voltage of VDD */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->VDDVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->VDDVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get BATRTC Voltage(takes 244us). + * @note This function takes about 244us when SystemClock is 26M. + * ADC data refresh time is 117us. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(BATRTC channel 2) + * - ADC clock: 3.2M + * - Skip samples: Skip 2 samples + * - Down sampling rate: 1/64 + * @param [in]Division + ADC_BAT_CAPDIV (Cap division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage is ignored + [out]CalResults.BATRTCVoltage The value of BATRTC Voltage + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset or BGP-gain information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetBATRTCVoltage_Fast(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + + NVR_BATMEARES BAT_OffsetInfo; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = 0x06C00102; + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + data = ANA->ADCDATA2; + + /* Calculate the voltage of BAT1 */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->BATRTCVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->BATRTCVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get BATRTC Voltage(takes 3.3ms). + * @note This function takes about 3.3ms when SystemClock is 26M. + * ADC data refresh time is about 3.2ms. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(BATRTC channel 2) + * - ADC clock: 1.6M + * - Skip samples: Skip first 4 samples + * - Down sampling rate: 1/512 + * @param [in]Division + ADC_BAT_CAPDIV (Capacitance division 1/4) + ADC_BAT_RESDIV (Resistance division 1/4) + [out]CalResults.VDDVoltage is ignored + [out]CalResults.BATRTCVoltage The value of BATRTC Voltage + [out]CalResults.Temperature is ignored + * @retval 1 NVR BAT-offset information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetBATRTCVoltage_Normal(uint32_t Division, ADC_CalResType *CalResults) +{ + float Vbatcap; + float Vbatres; + NVR_BATMEARES BAT_OffsetInfo; + ADCInitType ADC_InitStruct; + int16_t data; + + assert_parameters(IS_ADC_BATDIV(Division)); + + /* Get NVR BAT offset information */ + if (NVR_GetBATOffset(&BAT_OffsetInfo)) + { + return (1); + } + else + { + Vbatcap = BAT_OffsetInfo.BATCAPResult; + Vbatres = BAT_OffsetInfo.BATRESResult; + } + + /* ADC initialization */ + ADC_DeInit(); + ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL; + ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL; + ADC_InitStruct.Channel = ADC_CHANNEL2; + ADC_InitStruct.ClockDivider = ADC_CLKDIV_4; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_Init(&ADC_InitStruct); + + /* Enable division */ + ANA->REG1 |= Division; + /* Enable ADC */ + ana_reg3_tmp |= ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Start a manual ADC conversion */ + ADC_StartManual(); + /* Waiting last operation done */ + ADC_WaitForManual(); + + data = ANA->ADCDATA2; + + /* Calculate the voltage of BAT1 */ + if (Division & ADC_BAT_CAPDIV) + { + CalResults->BATRTCVoltage = (0.00014107*(float)data - 0.00699515) + Vbatcap; + } + else + { + CalResults->BATRTCVoltage = (0.00015392*(float)data + 0.06667986) + Vbatres; + } + + /* ADC resource release */ + ADC_DeInit(); + + return (0); +} + +/** + * @brief Get Temperature(takes 6.5ms). + * @note This function costs about 6.5ms when SystemClock is 26M. + * ADC data refresh time is about 3.2ms. + * @note This function will release ADC resource(write ADC registers with their + * default reset values). + * @note ADC configurarion: + * - Trigger mode: manual mode + * - Conversion mode: single channel mode(Temperature channel 10) + * - ADC clock: 1.6M + * - Skip samples: Skip first 4 samples + * - Down sampling rate: 1/512 + * @param [out]CalResults.VDDVoltage is ignored + [out]CalResults.BATRTCVoltage is ignored + [out]CalResults.Temperature The value of Temperature + * @retval 1 Temperature delta information checksum error. + 0 Function successed. + */ +uint32_t ADC_GetTemperature(ADC_CalResType *CalResults) +{ + int32_t P2; + int16_t P1, P0; + int16_t adc_data; + uint32_t retval; + NVR_RTCINFO RTC_DataStruct; + ADCInitType ADC_InitStruct; + + /* Get RTC Px parameters */ + retval = NVR_GetInfo_LoadRTCData(&RTC_DataStruct); + if (retval & 0x1U) + { + return (1); + } + else + { + P0 = RTC_DataStruct.RTCTempP0; + P1 = RTC_DataStruct.RTCTempP1; + P2 = RTC_DataStruct.RTCTempP2; + } + + /* ADC initialization */ + ADC_DeInit(); + ADC_InitStruct.TrigMode = ADC_TRIGMODE_MANUAL; + ADC_InitStruct.ConvMode = ADC_CONVMODE_SINGLECHANNEL; + ADC_InitStruct.Channel = ADC_CHANNEL10; + ADC_InitStruct.ClockDivider = ADC_CLKDIV_4; + ADC_InitStruct.ClockSource = ADC_CLKSRC_RCH; + ADC_Init(&ADC_InitStruct); + + /* Configure 1/512 down-sampling rate */ + ADC_CICDownSamRateConfig(ADC_SDRSEL_DIV512); + /* Enable ADC */ + ADC_Cmd(ENABLE); + + /*---------- Get ADC data1 ----------*/ + /* Starts a manual ADC conversion */ + ADC_StartManual(); + /* Waiting Manual ADC conversion done */ + ADC_WaitForManual(); + adc_data = (int16_t)ADC_GetADCConversionValue(ADC_CHANNEL10); + + /* ADC resource release */ + ADC_DeInit(); + + /* Calculate temperature */ + CalResults->Temperature = (float)((((P0 * ((adc_data*adc_data)>>16)) + P1*adc_data + P2) >> 8) / 256.0); + + return (0); +} + +/** + * @brief ADC power control. + * @note When DISABLE is selected, the automatic triggering of the ADC must be turned off by calling + * ADC_TrigSourceConfig(ADC_TRIGSOURCE_OFF) before using this function. + * @param NewState + ENABLE + DISABLE + * @retval 0: Function succeeded + * 1: Function failded, the automatic triggering be enabled when DISABLE selected + */ +uint32_t ADC_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + if (ANA->ADCCTRL & ANA_ADCCTRL_AEN) + { + return 1; + } + else + { + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + } + } + else + { + ana_reg3_tmp |= ANA_REG3_ADCPDN; + } + + ANA->REG3 = ana_reg3_tmp; + + return 0; +} + +/** + * @brief Manual ADC trigger + * @param None + * @retval None + */ +void ADC_StartManual(void) +{ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL |= ANA_ADCCTRL_MTRIG; +} + +/** + * @brief Wait for the last Manual ADC conversion done. + * @param None + * @retval None + */ +void ADC_WaitForManual(void) +{ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG) + { + } +} + +/** + * @brief ADC auto mode trigger source configure. + * @param TrigSource: + ADC_TRIGSOURCE_OFF + ADC_TRIGSOURCE_TIM0 + ADC_TRIGSOURCE_TIM1 + ADC_TRIGSOURCE_TIM2 + ADC_TRIGSOURCE_TIM3 + * @retval None + */ +void ADC_TrigSourceConfig(uint32_t TrigSource) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_TRIGSOURCE(TrigSource)); + + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_AEN; + tmp |= TrigSource; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief Resistance division enable control. + * @param NewState + ENABLE (x1/4) + DISABLE (x1) + * @retval None + */ +void ADC_RESDivisionCmd(uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = ANA->REG1; + if (NewState == ENABLE) + { + tmp &= ~ANA_REG1_GDE4; + tmp |=ANA_REG1_RESDIV; + } + else + { + tmp &= ~ANA_REG1_RESDIV; + } + ANA->REG1 = tmp; +} + +/** + * @brief Capacitance division enable control. + * @param NewState + ENABLE (x1/4) + DISABLE (x1) + * @retval None + */ +void ADC_CAPDivisionCmd(uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = ANA->REG1; + if (NewState == ENABLE) + { + tmp &= ~ANA_REG1_RESDIV; + tmp |=ANA_REG1_GDE4; + } + else + { + tmp &= ~ANA_REG1_GDE4; + } + ANA->REG1 = tmp; +} + +/** + * @brief CIC filter always on control. + * @param NewState + ENABLE (CIC filter always on) + DISABLE (CIC filter will be disabled when no ADC sample process is ongoing.) + * @retval None + */ +void ADC_CICAlwaysOnCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + + if (NewState == ENABLE) + ANA->ADCCTRL |= ANA_ADCCTRL_CICAON; + else + ANA->ADCCTRL &= ~ANA_ADCCTRL_CICAON; +} + +/** + * @brief CIC filter input inversion control. + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_CICINVCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + + if (NewState == ENABLE) + ANA->ADCCTRL |= ANA_ADCCTRL_CICINV; + else + ANA->ADCCTRL &= ~ANA_ADCCTRL_CICINV; +} + +/** + * @brief CIC output scale-down configure. + * @param ScaleDown: + ADC_SCA_NONE + ADC_SCA_DIV2 + * @retval None + */ +void ADC_CICScaleDownConfig(uint32_t ScaleDown) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_SCA(ScaleDown)); + + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_CICSCA; + tmp |= ScaleDown; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief CIC output skip control. + * @param Skip: + ADC_SKIP_4 + ADC_SKIP_5 + ADC_SKIP_6 + ADC_SKIP_7 + ADC_SKIP_0 + ADC_SKIP_1 + ADC_SKIP_2 + ADC_SKIP_3 + * @retval None + */ +void ADC_CICSkipConfig(uint32_t Skip) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_SKIP(Skip)); + + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_CICSKIP; + tmp |= Skip; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief CIC down sampling rate control. + * @param DSRSelection: + ADC_SDRSEL_DIV512 + ADC_SDRSEL_DIV256 + ADC_SDRSEL_DIV128 + ADC_SDRSEL_DIV64 + * @retval None + */ +void ADC_CICDownSamRateConfig(uint32_t DSRSelection) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADC_SDR(DSRSelection)); + tmp = ANA->ADCCTRL; + tmp &= ~ANA_ADCCTRL_DSRSEL; + tmp |= DSRSelection; + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL = tmp; +} + +/** + * @brief Get ADC vonversion value. + * @param Channel: + ADC_CHANNEL0 + ADC_CHANNEL1 + ADC_CHANNEL2 + ADC_CHANNEL3 + ADC_CHANNEL4 + ADC_CHANNEL5 + ADC_CHANNEL6 + ADC_CHANNEL7 + ADC_CHANNEL8 + ADC_CHANNEL9 + ADC_CHANNEL10 + ADC_CHANNEL11 + * @retval ADC conversion value. + */ +int16_t ADC_GetADCConversionValue(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_ADC_CHANNEL(Channel)); + + addr = &ANA->ADCDATA0 + Channel; + + return *addr; +} + +/** + * @brief ADC interrupt control. + * @param INTMask: + ADC_INT_AUTODONE + ADC_INT_MANUALDONE + NewState + ENABLE + DISABLE + * @retval None + */ +void ADC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + assert_parameters(IS_ADC_INT(INTMask)); + + if (NewState == ENABLE) + ANA->INTEN |= INTMask; + else + ANA->INTEN &= ~INTMask; +} + +/** + * @brief Get auto done flag + * @param None + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t ADC_GetAutoDoneFlag(void) +{ + if(ANA->INTSTS & ANA_INTSTS_INTSTS1) + return 1; + else + return 0; +} + +/** + * @brief Get manual done flag + * @param None + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t ADC_GetManualDoneFlag(void) +{ + if(ANA->INTSTS & ANA_INTSTS_INTSTS0) + return 1; + else + return 0; +} + +/** + * @brief Clear auto done flag + * @param None + * @retval None + */ +void ADC_ClearAutoDoneFlag(void) +{ + ANA->INTSTS = ANA_INTSTS_INTSTS1; +} + +/** + * @brief Clear manual done flag + * @param None + * @retval None + */ +void ADC_ClearManualDoneFlag(void) +{ + ANA->INTSTS = ANA_INTSTS_INTSTS0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c new file mode 100644 index 0000000000..6a50c20075 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_adc_tiny.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file lib_adc_tiny.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ADC_TINY library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_adc_tiny.h" + +#define ANA_REGF_RSTValue (0U) + +/** + * @brief Initializes the Tiny ADC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void TADC_DeInit(void) +{ + ANA->REGF = ANA_REGF_RSTValue; + ANA->INTSTS = ANA_INTSTS_INTSTS13; + ANA->MISC_A &= ~ANA_MISC_TADCTH; +} + +/** + * @brief Fills each TADC_InitStruct member with its default value. + * @param TADC_InitStruct: pointer to an TADCInitType structure which will be initialized. + * @retval None + */ +void TADC_StructInit(TADCInitType* TADC_InitStruct) +{ + /*--------------- Reset TADC init structure parameters values ---------------*/ + /* Initialize the SignalSel member */ + TADC_InitStruct->SignalSel = ADCTINY_SIGNALSEL_IOE6; + /* Initialize the ADTREF1 member */ + TADC_InitStruct->ADTREF1 = ADCTINY_REF1_0_9; + /* Initialize the ADTREF2 member */ + TADC_InitStruct->ADTREF2 = ADCTINY_REF2_1_8; + /* Initialize the ADTREF3 member */ + TADC_InitStruct->ADTREF3 = ADCTINY_REF3_2_7; +} + +/** + * @brief Tiny ADC initialization. + * @param TADC_InitStruct + SelADT: + ADCTINY_SIGNALSEL_IOE6 + ADCTINY_SIGNALSEL_IOE7 + ADTREF1: + ADCTINY_REF1_0_9 + ADCTINY_REF1_0_7 + ADTREF2: + ADCTINY_REF2_1_8 + ADCTINY_REF2_1_6 + ADTREF3: + ADCTINY_REF3_2_7 + ADCTINY_REF3_2_5 + * @retval None + */ +void TADC_Init(TADCInitType* TADC_InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADCTINY_SELADT(TADC_InitStruct->SignalSel)); + assert_parameters(IS_ADCTINY_ADTREF1(TADC_InitStruct->ADTREF1)); + assert_parameters(IS_ADCTINY_ADTREF2(TADC_InitStruct->ADTREF2)); + assert_parameters(IS_ADCTINY_ADTREF3(TADC_InitStruct->ADTREF3)); + + tmp = ANA->REGF; + tmp &= ~(ANA_REGF_SELADT \ + |ANA_REGF_ADTREF1SEL\ + |ANA_REGF_ADTREF2SEL\ + |ANA_REGF_ADTREF3SEL); + tmp |= (TADC_InitStruct->SignalSel \ + |TADC_InitStruct->ADTREF1\ + |TADC_InitStruct->ADTREF2\ + |TADC_InitStruct->ADTREF3); + ANA->REGF = tmp; +} + +/** + * @brief TADC enable control. + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void TADC_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == ENABLE) + ANA->REGF |= ANA_REGF_PDNADT; + else + ANA->REGF &= ~ANA_REGF_PDNADT; +} + +/** + * @brief Get TADC output. + * @param None + * @retval Output of Tiny ADC(0 ~ 3). + */ +uint8_t TADC_GetOutput(void) +{ + return ((ANA->COMPOUT & ANA_COMPOUT_TADCO) >> ANA_COMPOUT_TADCO_Pos); +} + +/** + * @brief Configure Tiny ADC interrupt threshold. + * @param THSel: + ADCTINY_THSEL_0 + ADCTINY_THSEL_1 + ADCTINY_THSEL_2 + ADCTINY_THSEL_3 + * @retval None. + */ +void TADC_IntTHConfig(uint32_t THSel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ADCTINY_THSEL(THSel)); + + tmp = ANA->MISC_A; + tmp &= ~ANA_MISC_TADCTH; + tmp |= THSel; + ANA->MISC_A = tmp; +} + +/** + * @brief TADC interrupt enable control. + * @param NewState + ENABLE + DISABLE + * @retval None + */ +void TADC_INTConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == ENABLE) + ANA->INTEN |= ANA_INTEN_INTEN13; + else + ANA->INTEN &= ~ANA_INTEN_INTEN13; +} + +/** + * @brief Get Tiny ADC interrupt status. + * @param None + * @retval Interrupt status. + */ +uint8_t TADC_GetINTStatus(void) +{ + if (ANA->INTSTS & ANA_INTSTS_INTSTS13) + return 1; + else + return 0; +} + +/** + * @brief Clear Tiny ADC interrupt status. + * @param None + * @retval None + */ +void TADC_ClearINTStatus(void) +{ + ANA->INTSTS = ANA_INTSTS_INTSTS13; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_ana.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_ana.c new file mode 100644 index 0000000000..614e7f9621 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_ana.c @@ -0,0 +1,136 @@ +/** + ****************************************************************************** + * @file lib_ana.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Analog library. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lib_ana.h" + + +/** + * @brief Get analog status. + * @param StatusMask: + ANA_STATUS_AVCCLV + ANA_STATUS_VDCINDROP + ANA_STATUS_VDDALARM + ANA_STATUS_COMP2 + ANA_STATUS_COMP1 + ANA_STATUS_LOCKL + ANA_STATUS_LOCKH + * @retval Analog status + */ +uint8_t ANA_GetStatus(uint32_t StatusMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_STATUS(StatusMask)); + + if (ANA->COMPOUT & StatusMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Get interrupt status. + * @param IntMask: + ANA_INT_TADC_OVER + ANA_INT_REGERR + ANA_INT_SME + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_COMP2 + ANA_INT_COMP1 + ANA_INT_ADCA + ANA_INT_ADCM + * @retval interrupt status. + */ +uint8_t ANA_GetINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_INTSTSR(IntMask)); + + if (ANA->INTSTS&IntMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param IntMask: + ANA_INT_TADC_OVER + ANA_INT_REGERR + ANA_INT_SME + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_COMP2 + ANA_INT_COMP1 + ANA_INT_ADCA + ANA_INT_ADCM + * @retval None + */ +void ANA_ClearINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_ANA_INTSTSC(IntMask)); + + ANA->INTSTS = IntMask; +} + +/** + * @brief ANA interrupt configure. + * @param IntMask: + ANA_INT_REGERR + ANA_INT_SME + ANA_INT_AVCCLV + ANA_INT_VDCINDROP + ANA_INT_VDDALARM + ANA_INT_COMP2 + ANA_INT_COMP1 + ANA_INT_ADCA + ANA_INT_ADCM + NewState: + ENABLE + DISABLE + * @retval None + */ +void ANA_INTConfig(uint32_t IntMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ANA_INT(IntMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = ANA->INTEN; + if (NewState == ENABLE) + { + tmp |= IntMask; + } + else + { + tmp &= ~IntMask; + } + ANA->INTEN = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_clk.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_clk.c new file mode 100644 index 0000000000..cf42a2899b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_clk.c @@ -0,0 +1,635 @@ +/** + ****************************************************************************** + * @file lib_clk.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Clock library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_clk.h" + +__IO uint32_t ana_reg3_tmp; +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the CLK_ClkInitStruct. + * + * @note This function performs the following: + * 1. If want to switch AHB clock source, enable BGP, enable 6.5M RC, + * AHB clock source switch to RCH first. + * 2. configure clock (except AHB clock source configuration). - optional + * 3. configure AHB clock source. - optional + * 4. HCLK/PCLK divider configuration. - optional + * + * @note CLK_InitTypeDef *CLK_ClkInitStruct + * [in]CLK_ClkInitStruct->ClockType, can use the ¡®|¡¯ operator, the selection of parameters is as follows + * CLK_TYPE_ALL + * CLK_TYPE_AHBSRC + * CLK_TYPE_PLLL + * CLK_TYPE_PLLH + * CLK_TYPE_XTALH + * CLK_TYPE_RTCCLK + * CLK_TYPE_HCLK + * CLK_TYPE_PCLK + * + * CLK_TYPE_ALL All clocks' configurations is valid + * CLK_TYPE_AHBSRC CLK_ClkInitStruct->AHBSource(AHB Clock source configuration) is valid + * [in]CLK_ClkInitStruct->AHBSource: + * CLK_AHBSEL_6_5MRC + * CLK_AHBSEL_6_5MXTAL + * CLK_AHBSEL_HSPLL + * CLK_AHBSEL_RTCCLK + * CLK_AHBSEL_LSPLL + * CLK_TYPE_PLLL CLK_ClkInitStruct->PLLL(PLLL configuration) is valid + * [in]CLK_ClkInitStruct->PLLL.State: + * CLK_PLLL_ON (PLLL.Source/Frequency configuration is valid) + * CLK_PLLL_OFF (PLLL.Source/Frequency configuration is not valid) + * [in]CLK_ClkInitStruct->PLLL.Source: + * CLK_PLLLSRC_RCL + * CLK_PLLLSRC_XTALL + * [in]CLK_ClkInitStruct->PLLL.Frequency: + * CLK_PLLL_26_2144MHz + * CLK_PLLL_13_1072MHz + * CLK_PLLL_6_5536MHz + * CLK_PLLL_3_2768MHz + * CLK_PLLL_1_6384MHz + * CLK_PLLL_0_8192MHz + * CLK_PLLL_0_4096MHz + * CLK_PLLL_0_2048MHz + * CLK_TYPE_PLLH CLK_ClkInitStruct->PLLH(PLLH configuration) is valid + * [in]CLK_ClkInitStruct->PLLH.State: + * CLK_PLLH_ON (PLLH.Source/Frequency configuration is valid) + * CLK_PLLH_OFF (PLLH.Source/Frequency configuration is not valid) + * [in]CLK_ClkInitStruct->PLLH.Source: + * CLK_PLLHSRC_RCH + * CLK_PLLHSRC_XTALH + * [in]CLK_ClkInitStruct->PLLH.Frequency: + * CLK_PLLH_13_1072MHz + * CLK_PLLH_16_384MHz + * CLK_PLLH_19_6608MHz + * CLK_PLLH_22_9376MHz + * CLK_PLLH_26_2144MHz + * CLK_PLLH_29_4912MHz + * CLK_PLLH_32_768MHz + * CLK_PLLH_36_0448MHz + * CLK_PLLH_39_3216MHz + * CLK_PLLH_42_5984MHz + * CLK_PLLH_45_8752MHz + * CLK_PLLH_49_152MHz + * CLK_TYPE_XTALH CLK_ClkInitStruct->XTALH(XTALH configuration) is valid + * [in]CLK_ClkInitStruct->XTALH.State: + * CLK_XTALH_ON + * CLK_XTALH_OFF + * CLK_TYPE_RTCCLK CLK_ClkInitStruct->RTCCLK(RTCCLK configuration) is valid + * [in]CLK_ClkInitStruct->RTCCLK.Source: + * CLK_RTCCLKSRC_XTALL + * CLK_RTCCLKSRC_RCL + * [in]CLK_ClkInitStruct->RTCCLK.Divider: + * CLK_RTCCLKDIV_1 + * CLK_RTCCLKDIV_4 + * CLK_TYPE_HCLK CLK_ClkInitStruct->HCLK(AHB Clock(divider) configuration) is valid + * [in]CLK_ClkInitStruct->HCLK.Divider: + * 1 ~ 256 + * CLK_TYPE_PCLK CLK_ClkInitStruct->PCLK(APB Clock(divider) configuration) is valid + * [in]CLK_ClkInitStruct->PCLK.Divider: + * 1 ~ 256 + * + * @param CLK_ClkInitStruct pointer to an CLK_InitTypeDef structure that + * contains the configuration information for the clocks. + * + * @retval None + */ +void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct) +{ + uint32_t tmp; + + assert_parameters(IS_CLK_TYPE(CLK_ClkInitStruct->ClockType)); + + if (CLK_ClkInitStruct->ClockType & CLK_TYPE_AHBSRC) + { + /* Enable BGP */ + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + /* Enable 6.5M RC */ + ana_reg3_tmp &= ~ANA_REG3_RCHPD; + ANA->REG3 = ana_reg3_tmp; + /* AHB clock source switch to RCH */ + MISC2->CLKSEL = 0; + } + + ANA->REGA &= ~BIT6; + ANA->REG2 &= ~BIT7; + + /*---------- XTALH configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_XTALH) + { + assert_parameters(IS_CLK_XTALHSTA(CLK_ClkInitStruct->XTALH.State)); + + /* XTALH state configure */ + ana_reg3_tmp &= ~ANA_REG3_XOHPDN; + ana_reg3_tmp |= CLK_ClkInitStruct->XTALH.State; + ANA->REG3 = ana_reg3_tmp; + } + + /*-------------------- PLLL configuration --------------------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLL) + { + assert_parameters(IS_CLK_PLLLSRC(CLK_ClkInitStruct->PLLL.Source)); + assert_parameters(IS_CLK_PLLLSTA(CLK_ClkInitStruct->PLLL.State)); + assert_parameters(IS_CLK_PLLLFRQ(CLK_ClkInitStruct->PLLL.Frequency)); + + /* XTALL power up */ + tmp = ANA->REG2; + tmp &= ~BIT7; + ANA->REG2 = tmp; + + /* PLLL state configure */ + if (CLK_ClkInitStruct->PLLL.State == CLK_PLLL_ON) + { + /* power up PLLL */ + ana_reg3_tmp |= ANA_REG3_PLLLPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Configure PLLL frequency */ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PLLLSEL; + tmp |= CLK_ClkInitStruct->PLLL.Frequency; + ANA->REG9 = tmp; + + /* Configure PLLL input clock selection */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_PLLL_SEL; + tmp |= CLK_ClkInitStruct->PLLL.Source; + PMU->CONTROL = tmp; + } + else + { + /* power down PLLL */ + ana_reg3_tmp &= ~ANA_REG3_PLLLPDN; + ANA->REG3 = ana_reg3_tmp; + } + } + + /*-------------------- PLLH configuration --------------------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLH) + { + assert_parameters(IS_CLK_PLLHSRC(CLK_ClkInitStruct->PLLH.Source)); + assert_parameters(IS_CLK_PLLHSTA(CLK_ClkInitStruct->PLLH.State)); + assert_parameters(IS_CLK_PLLHFRQ(CLK_ClkInitStruct->PLLH.Frequency)); + + /* PLLH state configure */ + if (CLK_ClkInitStruct->PLLH.State == CLK_PLLH_ON) + { + /* Power up PLLH */ + ana_reg3_tmp |= ANA_REG3_PLLHPDN; + ANA->REG3 = ana_reg3_tmp; + + /* Configure PLLH frequency */ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PLLHSEL; + tmp |= CLK_ClkInitStruct->PLLH.Frequency; + ANA->REG9 = tmp; + + /* Clock input source, XTALH, XOH power on*/ + if (CLK_ClkInitStruct->PLLH.Source == CLK_PLLHSRC_XTALH) + { + ana_reg3_tmp |= ANA_REG3_XOHPDN; + ANA->REG3 = ana_reg3_tmp; + } + + /* Configure PLLH input clock selection */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_PLLH_SEL; + tmp |= CLK_ClkInitStruct->PLLH.Source; + PMU->CONTROL = tmp; + } + else + { + /* Power down PLLH */ + ana_reg3_tmp &= ~ANA_REG3_PLLHPDN; + ANA->REG3 = ana_reg3_tmp; + } + } + + /*---------- RTCCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_RTCCLK) + { + assert_parameters(IS_CLK_RTCSRC(CLK_ClkInitStruct->RTCCLK.Source)); + assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider)); + + /* RTCCLK source(optional) */ + tmp = PMU->CONTROL; + tmp &= ~PMU_CONTROL_RTCLK_SEL; + tmp |= CLK_ClkInitStruct->RTCCLK.Source; + PMU->CONTROL = tmp; + + /*----- RTCCLK Divider -----*/ + RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider); + } + + /*---------- AHB clock source configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_AHBSRC) + { + assert_parameters(IS_CLK_AHBSRC(CLK_ClkInitStruct->AHBSource)); + + /* clock source: 6.5M RC */ + if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MRC) + { + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: 6_5MXTAL */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MXTAL) + { + /* Power up 6.5M xtal */ + ana_reg3_tmp |= ANA_REG3_XOHPDN; + ANA->REG3 = ana_reg3_tmp; + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: PLLH */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_HSPLL) + { + /* Power up PLLH */ + ana_reg3_tmp |= ANA_REG3_PLLHPDN; + ANA->REG3 = ana_reg3_tmp; + /* while loop until PLLL is lock */ + while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKH)) + { + } + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + + /* clock source: PLLL */ + else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_LSPLL) + { + /* Power up PLLL */ + ana_reg3_tmp |= ANA_REG3_PLLLPDN; + ANA->REG3 = ana_reg3_tmp; + /* while loop until PLLL is lock */ + while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKL)) + { + } + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + /* clock source: RTCCLK */ + else + { + /* clock source configuration */ + MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource; + } + } + + /*---------- HCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_HCLK) + { + assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider)); + + MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1; + } + + /*---------- PCLK configuration ----------*/ + if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PCLK) + { + assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider)); + + MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1; + } +} + +/** + * @brief AHB Periphral clock control. + * @param Periphral: can use the ¡®|¡¯ operator + CLK_AHBPERIPHRAL_DMA + CLK_AHBPERIPHRAL_GPIO + CLK_AHBPERIPHRAL_LCD + CLK_AHBPERIPHRAL_CRYPT + NewState: + ENABLE + DISABLE + * @retval None. + */ +void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CLK_AHBPERIPHRAL(Periphral)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC2->HCLKEN |= Periphral; + } + else + { + MISC2->HCLKEN &= ~Periphral; + } +} + +/** + * @brief APB Periphral clock control. + * @param Periphral: can use the ¡®|¡¯ operator + CLK_APBPERIPHRAL_DMA + CLK_APBPERIPHRAL_I2C + CLK_APBPERIPHRAL_SPI1 + CLK_APBPERIPHRAL_SPI2 + CLK_APBPERIPHRAL_UART0 + CLK_APBPERIPHRAL_UART1 + CLK_APBPERIPHRAL_UART2 + CLK_APBPERIPHRAL_UART3 + CLK_APBPERIPHRAL_UART4 + CLK_APBPERIPHRAL_UART5 + CLK_APBPERIPHRAL_ISO78160 + CLK_APBPERIPHRAL_ISO78161 + CLK_APBPERIPHRAL_TIMER + CLK_APBPERIPHRAL_MISC + CLK_APBPERIPHRAL_MISC2 + CLK_APBPERIPHRAL_PMU + CLK_APBPERIPHRAL_RTC + CLK_APBPERIPHRAL_ANA + CLK_APBPERIPHRAL_U32K0 + CLK_APBPERIPHRAL_U32K1 + NewState: + ENABLE + DISABLE + * @retval None. + */ +void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_CLK_APBPERIPHRAL(Periphral)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC2->PCLKEN |= Periphral; + } + else + { + MISC2->PCLKEN &= ~Periphral; + } +} + +/** + * @brief Returns the HCLK frequency + * @param None + * @retval HCLK frequency + */ +uint32_t CLK_GetHCLKFreq(void) +{ + uint32_t ahb_clksrc; + uint32_t ahb_div; + uint32_t pllh_frq; + uint32_t plll_frq; + uint32_t rtcclk_div; + uint32_t hclk; + + /* Get current AHB clock source */ + ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL; + /* Get AHB clock divider */ + ahb_div = (MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1; + + switch (ahb_clksrc) + { + /* AHB Clock source : 6.5M RC */ + case MISC2_CLKSEL_CLKSEL_RCOH: + hclk = 6553600 / ahb_div; + break; + + /* AHB Clock source : 6.5M XTAL */ + case MISC2_CLKSEL_CLKSEL_XOH: + hclk = 6553600 / ahb_div; + break; + + /* AHB Clock source : PLLH */ + case MISC2_CLKSEL_CLKSEL_PLLH: + /* Get PLLH Frequency */ + pllh_frq = ANA->REG9 & ANA_REG9_PLLHSEL; + switch (pllh_frq) + { + case ANA_REG9_PLLHSEL_X2: + hclk = 13107200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X2_5: + hclk = 16384000 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X3: + hclk = 19660800 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X3_5: + hclk = 22937600 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X4: + hclk = 26214400 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X4_5: + hclk = 29491200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X5: + hclk = 32768000 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X5_5: + hclk = 36044800 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X6: + hclk = 39321600 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X6_5: + hclk = 42598400 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X7: + hclk = 45875200 / ahb_div; + break; + + case ANA_REG9_PLLHSEL_X7_5: + hclk = 49152000 / ahb_div; + break; + + default: + hclk = 0; + break; + } + break; + + /* AHB Clock source : RTCCLK */ + case MISC2_CLKSEL_CLKSEL_RTCCLK: + /* Get current RTC clock divider */ + rtcclk_div = RTC->PSCA & RTC_PSCA_PSCA; + if (rtcclk_div == RTC_PSCA_PSCA_0) + { + hclk = 32768 / ahb_div; + } + else if (rtcclk_div == RTC_PSCA_PSCA_1) + { + hclk = 8192 / ahb_div; + } + else + { + hclk = 0; + } + break; + + /* AHB Clock source : PLLL */ + case MISC2_CLKSEL_CLKSEL_PLLL: + /* Get PLLL Frequency */ + plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL; + switch (plll_frq) + { + case ANA_REG9_PLLLSEL_26M: + hclk = 26214400 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_13M: + hclk = 13107200 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_6_5M: + hclk = 6553600 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_3_2M: + hclk = 3276800 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_1_6M: + hclk = 1638400 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_800K: + hclk = 819200 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_400K: + hclk = 409600 / ahb_div; + break; + + case ANA_REG9_PLLLSEL_200K: + hclk = 204800 / ahb_div; + break; + + default: + hclk = 0; + break; + } + break; + + default: + hclk = 0; + break; + } + + return (hclk); +} + +/** + * @brief Returns the PCLK frequency + * @param None + * @retval PCLK frequency + */ +uint32_t CLK_GetPCLKFreq(void) +{ + return ((CLK_GetHCLKFreq()) / ((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1)); +} + +/** + * @brief Get the CLK_ClkInitStruct according to the internal + * Clock configuration registers. + * + * @param CLK_ClkInitStruct pointer to an CLK_ClkInitStruct structure that + * contains the current clock configuration. + * + * @retval None + */ +void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + CLK_ClkInitStruct->ClockType = CLK_TYPE_ALL; + + /* Get AHB clock source ----------------------------------------------------*/ + CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL); + /* Get PLLL clock configration ---------------------------------------------*/ + CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL); + CLK_ClkInitStruct->PLLL.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLLSEL); + CLK_ClkInitStruct->PLLL.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLLPDN); + /* Get PLLH clock configuration --------------------------------------------*/ + CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL); + CLK_ClkInitStruct->PLLH.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLHSEL); + CLK_ClkInitStruct->PLLH.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLHPDN); + /* Get XTALH configuration -------------------------------------------------*/ + CLK_ClkInitStruct->XTALH.State = (uint32_t)(ANA->REG3 & ANA_REG3_XOHPDN); + /* Get HCLK(Divider) configuration -----------------------------------------*/ + CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1); + /* Get PCLK((Divider) configuration ----------------------------------------*/ + CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1); +} + +/** + * @brief Get current external 6.5M crystal status. + * + * @param None + * + * @retval 6.5M crystal status + * 0: 6.5536M crystal is absent. + * 1: 6.5536M crystal is present. + */ +uint8_t CLK_GetXTALHStatus(void) +{ + if (PMU->STS & PMU_STS_EXIST_6M) + return (1); + else + return (0); +} + +/** + * @brief Get current external 32K crystal status. + * + * @param None + * + * @retval 32K crystal status + * 0: 32K crystal is absent + * 1: 32K crystal is present. + */ +uint8_t CLK_GetXTALLStatus(void) +{ + if (PMU->STS & PMU_STS_EXIST_32K) + return (1); + else + return (0); +} + +/** + * @brief Get PLL lock status. + * @param PLLStatus: + * CLK_STATUS_LOCKL + * CLK_STATUS_LOCKH + * @retval PLL lock status + * 0 PLL is not locked. + * 1 PLL is locked. + */ +uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus) +{ + /* Check parameters */ + assert_parameters(IS_CLK_PLLLOCK(PLLStatus)); + + if (ANA->COMPOUT & PLLStatus) + return 1; + else + return 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_comp.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_comp.c new file mode 100644 index 0000000000..c0f899cfc3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_comp.c @@ -0,0 +1,337 @@ +/** + ****************************************************************************** + * @file lib_comp.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief COMP library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_comp.h" + +extern __IO uint32_t ana_reg3_tmp; +/** + * @brief Comparator debounce configure. + * @param COMPx: + COMP_1 + COMP_2 + Debounce: + COMP_DEB_0 + COMP_DEB_1 + COMP_DEB_2 + COMP_DEB_3 + * @retval None + */ +void COMP_DEBConfig(uint32_t COMPx, uint32_t Debounce) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_DEB(Debounce)); + + tmp = ANA->CTRL; + tmp &= ~(ANA_CTRL_CMP1DEB << COMPx); + tmp |= Debounce << COMPx; + ANA->CTRL = tmp; +} + +/** + * @brief Comparator mode configure. + * @param COMPx: + COMP_1 + COMP_2 + Mode: + COMP_MODE_OFF + COMP_MODE_RISING + COMP_MODE_FALLING + COMP_MODE_BOTH + * @retval None + */ +void COMP_ModeConfig(uint32_t COMPx, uint32_t Mode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_MODE(Mode)); + + tmp = ANA->CTRL; + tmp &= ~(ANA_CTRL_COMP1_SEL << COMPx); + tmp |= Mode << COMPx; + ANA->CTRL = tmp; +} + +/** + * @brief Configure signal source. + * @param COMPx: + * COMP_1 + * COMP_2 + * SourceSelect: + * COMP_SIGNALSRC_P_TO_REF + * COMP_SIGNALSRC_N_TO_REF + * COMP_SIGNALSRC_P_TO_N + * @retval None + */ +void COMP_SignalSourceConfig(uint32_t COMPx, uint32_t SourceSelect) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_SIGNALSRC(SourceSelect)); + + tmp = ANA->REG2; + tmp &= ~(ANA_REG2_CMP1_SEL << COMPx); + tmp |= SourceSelect << COMPx; + + ANA->REG2 = tmp; +} + +/** + * @brief Comparator configure REF selection. + * @param COMPx: + * COMP_1 + * COMP_2 + * REFSelect: + * COMP_REF_VREF + * COMP_REF_BGPREF + * @retval None + */ +void COMP_REFConfig(uint32_t COMPx, uint32_t REFSelect) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_REF(REFSelect)); + + tmp = ANA->REG2; + tmp &= ~(ANA_REG2_REFSEL_CMP1 << (COMPx / 2)); + tmp |= REFSelect << (COMPx / 2); + + ANA->REG2 = tmp; +} + +/** + * @brief Comparator configure Bias current selection. + * @param COMPx: + * COMP_1 + * COMP_2 + * BiasSel: + * COMP_BIAS_20nA + * COMP_BIAS_100nA + * COMP_BIAS_500nA + * @retval None + */ +void COMP_BiasConfig(uint32_t COMPx, uint32_t BiasSel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_COMP_BIAS(BiasSel)); + + tmp = ANA->REG5; + tmp &= ~(ANA_REG5_IT_CMP1 << COMPx); + tmp |= BiasSel << COMPx; + + ANA->REG5 = tmp; +} + +/** + * @brief Get comparator count value. + * @param COMPx: + COMP_1 + COMP_2 + * @retval Comparator count value. + */ +uint32_t COMP_GetCNTValue(uint32_t COMPx) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + addr = &ANA->CMPCNT1 + (COMPx / 2); + + return (*addr); +} + +/** + * @brief Clear comparator counter value. + * @param COMPx: + COMP_1 + COMP_2 + * @retval None + */ +void COMP_ClearCNTValue(uint32_t COMPx) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + addr = &ANA->CMPCNT1 + (COMPx / 2); + *addr = 0; +} + +/** + * @brief comparator output enable control. + * @param COMPx: + COMP_1 + COMP_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void COMP_Output_Cmd(uint32_t COMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + if (COMPx == COMP_1) + GPIOAF->SELE |= IOE_SEL_SEL7; + else + PMU->IOASEL |= PMU_IOASEL_SEL6; + } + else + { + if (COMPx == COMP_1) + GPIOAF->SELE &= ~IOE_SEL_SEL7; + else + PMU->IOASEL &= ~PMU_IOASEL_SEL6; + } +} + +/** + * @brief Comparator enable control. + * @param COMPx: + COMP_1 + COMP_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void COMP_Cmd(uint32_t COMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (COMPx == COMP_1) + { + if (NewState == ENABLE) + ana_reg3_tmp |= ANA_REG3_CMP1PDN; + else + ana_reg3_tmp &= ~ANA_REG3_CMP1PDN; + } + else + { + if (NewState == ENABLE) + ana_reg3_tmp |= ANA_REG3_CMP2PDN; + else + ana_reg3_tmp &= ~ANA_REG3_CMP2PDN; + } + ANA->REG3 = ana_reg3_tmp; +} + +/** + * @brief Get comparator 1 output level + * @param None + * @retval None + */ +uint8_t COMP1_GetOutputLevel(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_COMP1) + return 1; + else + return 0; +} + +/** + * @brief Get comparator 2 output level + * @param None + * @retval None + */ +uint8_t COMP2_GetOutputLevel(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_COMP2) + return 1; + else + return 0; +} + +/** + * @brief Comparator interrupt enable control. + * @param COMPx: + * COMP_1 + * COMP_2 + * NewState: + * ENABLE + * DISABLE + * @retval None + */ +void COMP_INTConfig(uint32_t COMPx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + if (NewState == ENABLE) + { + ANA->INTEN |= ANA_INTEN_INTEN2 << (COMPx/2); + } + else + { + ANA->INTEN &= ~(ANA_INTEN_INTEN2 << (COMPx/2)); + } +} + +/** + * @brief Get comparator interrupt flag status. + * @param COMPx: + * COMP_1 + * COMP_2 + * @retval flag status + * 0: status not set + * 1: status set + */ +uint8_t COMP_GetINTStatus(uint32_t COMPx) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + if (ANA->INTSTS & (ANA_INTSTS_INTSTS2 << (COMPx/2))) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear comparator interrupt flag. + * @param COMPx: + * COMP_1 + * COMP_2 + * @retval None + */ +void COMP_ClearINTStatus(uint32_t COMPx) +{ + /* Check parameters */ + assert_parameters(IS_COMP(COMPx)); + + ANA->INTSTS = ANA_INTSTS_INTSTS2 << (COMPx/2); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_crypt.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_crypt.c new file mode 100644 index 0000000000..1e0dbb30d6 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_crypt.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file lib_crypt.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief CRYPT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_crypt.h" + +/** + * @brief Configure PTRA register, data in this address will be read out to do + * the CRYPT calculation + * @param AddrA: the SRAM address(Bit 14:0) + * @retval None + */ +void CRYPT_AddressAConfig(uint16_t AddrA) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrA)); + + CRYPT->PTRA = AddrA & CRYPT_PTRA_PTRA; +} + +/** + * @brief Configure PTRB register, data in this address will be read out to do + * the CRYPT calculation + * @param AddrB: the SRAM address(Bit 14:0) + * @retval None + */ +void CRYPT_AddressBConfig(uint16_t AddrB) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrB)); + + CRYPT->PTRB = AddrB & CRYPT_PTRB_PTRB; +} + +/** + * @brief Configure PTRO register, The CRYPT engine will write calculation + * result into this address + * @param AddrO: the SRAM address(Bit 14:0) + * @retval None + */ +void CRYPT_AddressOConfig(uint16_t AddrO) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_ADDR(AddrO)); + + CRYPT->PTRO = AddrO & CRYPT_PTRO_PTRO; +} + +/** + * @brief Get carry/borrow bit of add/sub operation. + * @param None + * @retval carry/borrow bit value + */ +uint8_t CRYPT_GetCarryBorrowBit(void) +{ + if (CRYPT->CARRY & CRYPT_CARRY_CARRY) + return (1); + else + return (0); +} + +/** + * @brief Start addition operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartAdd(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_ADD \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Start multiplication operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartMultiply(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_MULTIPLY \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Start subtraction operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartSub(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_SUB \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Start rigth shift 1-bit operation. + * @param Length: + * CRYPT_LENGTH_32 + * CRYPT_LENGTH_64 + * CRYPT_LENGTH_96 + * CRYPT_LENGTH_128 + * CRYPT_LENGTH_160 + * CRYPT_LENGTH_192 + * CRYPT_LENGTH_224 + * CRYPT_LENGTH_256 + * CRYPT_LENGTH_288 + * CRYPT_LENGTH_320 + * CRYPT_LENGTH_352 + * CRYPT_LENGTH_384 + * CRYPT_LENGTH_416 + * CRYPT_LENGTH_448 + * CRYPT_LENGTH_480 + * CRYPT_LENGTH_512 + * Nostop: + * CRYPT_STOPCPU + * CRYPT_NOSTOPCPU + * @retval None + */ +void CRYPT_StartRShift1(uint32_t Length, uint32_t Nostop) +{ + /* Check parameters */ + assert_parameters(IS_CRYPT_LENGTH(Length)); + assert_parameters(IS_CRYPT_NOSTOP(Nostop)); + + CRYPT->CTRL = (Nostop \ + |Length \ + |CRYPT_CTRL_MODE_RSHIFT1 \ + |CRYPT_CTRL_ACT); +} + +/** + * @brief Waiting for last operation to complete. + * @param None + * @retval None + */ +void CRYPT_WaitForLastOperation(void) +{ + while (CRYPT->CTRL & CRYPT_CTRL_ACT) + { + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_dma.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_dma.c new file mode 100644 index 0000000000..113c08d424 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_dma.c @@ -0,0 +1,442 @@ +/** + ****************************************************************************** + * @file lib_dma.c + * @author Application Team + * @version V4.4.0 + * @date 22018-09-27 + * @brief DMA library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_dma.h" + +//registers default reset values +#define DMA_CxCTL_RSTValue (0UL) +#define DMA_CxSRC_RSTValue (0UL) +#define DMA_CxDST_RSTValue (0UL) +#define DMA_AESCTL_RSTValue (0UL) +#define DMA_AESKEY_RSTValue (0UL) + +/** + * @brief Initializes the DMA Cx peripheral registers to their default reset values. + * @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3 + * @retval None + */ +void DMA_DeInit(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + /* channel x disable, clear stop */ + addr = &DMA->C0CTL + Channel*4; + *addr &= ~(DMA_CxCTL_EN | DMA_CTL_STOP); + + /* interrupt disable */ + DMA->IE &= ~((1<<(Channel))\ + |(1<<(Channel+4))\ + |(1<<(Channel+8))); + + /* interrupt state clear */ + DMA->STS = (1<<(Channel+4))\ + |(1<<(Channel+8))\ + |(1<<(Channel+12)); + + /* DMA_CxCTL */ + addr = &DMA->C0CTL + Channel*4; + *addr = DMA_CxCTL_RSTValue; + + /* DMA_CxSRC */ + addr = &DMA->C0SRC + Channel*4; + *addr = DMA_CxSRC_RSTValue; + + /* DMA_CxDST */ + addr = &DMA->C0DST + Channel*4; + *addr = DMA_CxDST_RSTValue; +} + +/** + * @brief DMA channel x initialization. + * @param InitStruct: DMA configuration. + DestAddr : destination address + SrcAddr : source address + FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1) + PackLen : Package length (Ranges 0~255, actual length PackLen+1) + ContMode: + DMA_CONTMODE_ENABLE + DMA_CONTMODE_DISABLE + TransMode: + DMA_TRANSMODE_SINGLE + DMA_TRANSMODE_PACK + ReqSrc: + DMA_REQSRC_SOFT + DMA_REQSRC_UART0TX + DMA_REQSRC_UART0RX + DMA_REQSRC_UART1TX + DMA_REQSRC_UART1RX + DMA_REQSRC_UART2TX + DMA_REQSRC_UART2RX + DMA_REQSRC_UART3TX + DMA_REQSRC_UART3RX + DMA_REQSRC_UART4TX + DMA_REQSRC_UART4RX + DMA_REQSRC_UART5TX + DMA_REQSRC_UART5RX + DMA_REQSRC_ISO78160TX + DMA_REQSRC_ISO78160RX + DMA_REQSRC_ISO78161TX + DMA_REQSRC_ISO78161RX + DMA_REQSRC_TIMER0 + DMA_REQSRC_TIMER1 + DMA_REQSRC_TIMER2 + DMA_REQSRC_TIMER3 + DMA_REQSRC_SPI1TX + DMA_REQSRC_SPI1RX + DMA_REQSRC_U32K0 + DMA_REQSRC_U32K1 + DMA_REQSRC_CMP1 + DMA_REQSRC_CMP2 + DMA_REQSRC_SPI2TX + DMA_REQSRC_SPI2RX + DestAddrMode: + DMA_DESTADDRMODE_FIX + DMA_DESTADDRMODE_PEND + DMA_DESTADDRMODE_FEND + SrcAddrMode: + DMA_SRCADDRMODE_FIX + DMA_SRCADDRMODE_PEND + DMA_SRCADDRMODE_FEND + TransSize: + DMA_TRANSSIZE_BYTE + DMA_TRANSSIZE_HWORD + DMA_TRANSSIZE_WORD + Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval None + */ +void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel) +{ + uint32_t tmp; + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode)); + assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode)); + assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc)); + assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode)); + assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode)); + assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize)); + + if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD) + { + assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr)); + assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr)); + } + if (InitStruct->TransSize == DMA_TRANSSIZE_WORD) + { + assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr)); + assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr)); + } + + addr = &DMA->C0DST + Channel*4; + *addr = InitStruct->DestAddr; + + addr = &DMA->C0SRC + Channel*4; + *addr = InitStruct->SrcAddr; + + addr = &DMA->C0CTL + Channel*4; + + tmp = *addr; + tmp &= ~(DMA_CTL_FLEN\ + |DMA_CTL_PLEN\ + |DMA_CTL_CONT\ + |DMA_CTL_TMODE\ + |DMA_CTL_DMASEL\ + |DMA_CxCTL_DMODE\ + |DMA_CxCTL_SMODE\ + |DMA_CxCTL_SIZE); + tmp |= ((InitStruct->FrameLen<PackLen<ContMode)\ + |(InitStruct->TransMode)\ + |(InitStruct->ReqSrc)\ + |(InitStruct->DestAddrMode)\ + |(InitStruct->SrcAddrMode)\ + |(InitStruct->TransSize)); + *addr = tmp; +} + +/** + * @brief Initializes the DMA AES channel3 registers to their default reset values. + * @param None + * @retval None + */ +void DMA_AESDeInit(void) +{ + DMA->AESCTL = DMA_AESCTL_RSTValue; + DMA->AESKEY0 = DMA_AESKEY_RSTValue; + DMA->AESKEY1 = DMA_AESKEY_RSTValue; + DMA->AESKEY2 = DMA_AESKEY_RSTValue; + DMA->AESKEY3 = DMA_AESKEY_RSTValue; + DMA->AESKEY4 = DMA_AESKEY_RSTValue; + DMA->AESKEY5 = DMA_AESKEY_RSTValue; + DMA->AESKEY6 = DMA_AESKEY_RSTValue; + DMA->AESKEY7 = DMA_AESKEY_RSTValue; +} + +/** + * @brief AES initialization. + * @param InitStruct: AES configuration. + Mode: + DMA_AESMODE_128 + DMA_AESMODE_192 + DMA_AESMODE_256 + Direction: + DMA_AESDIRECTION_ENCODE + DMA_AESDIRECTION_DECODE + KeyStr: the pointer to DMA_AESKEYx register + * @retval None + */ +void DMA_AESInit(DMA_AESInitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_DMA_AESMOD(InitStruct->Mode)); + assert_parameters(IS_DMA_AESDIR(InitStruct->Direction)); + + tmp = DMA->AESCTL; + tmp &= ~(DMA_AESCTL_MODE\ + |DMA_AESCTL_ENC); + tmp |= (InitStruct->Mode\ + |InitStruct->Direction); + DMA->AESCTL = tmp; + DMA->AESKEY0 = InitStruct->KeyStr[0]; + DMA->AESKEY1 = InitStruct->KeyStr[1]; + DMA->AESKEY2 = InitStruct->KeyStr[2]; + DMA->AESKEY3 = InitStruct->KeyStr[3]; + + if ((InitStruct->Mode == DMA_AESMODE_192) ||\ + (InitStruct->Mode == DMA_AESMODE_256)) + { + DMA->AESKEY4 = InitStruct->KeyStr[4]; + DMA->AESKEY5 = InitStruct->KeyStr[5]; + } + if (InitStruct->Mode == DMA_AESMODE_256) + { + DMA->AESKEY6 = InitStruct->KeyStr[6]; + DMA->AESKEY7 = InitStruct->KeyStr[7]; + } +} + +/** + * @brief Interrupt configure. + * @param INTMask: can use the ¡®|¡¯ operator + DMA_INT_C3DA + DMA_INT_C2DA + DMA_INT_C1DA + DMA_INT_C0DA + DMA_INT_C3FE + DMA_INT_C2FE + DMA_INT_C1FE + DMA_INT_C0FE + DMA_INT_C3PE + DMA_INT_C2PE + DMA_INT_C1PE + DMA_INT_C0PE + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + DMA->IE |= INTMask; + else + DMA->IE &= ~INTMask; +} + +/** + * @brief Get interrupt status. + * @param INTMask: + DMA_INTSTS_C3DA + DMA_INTSTS_C2DA + DMA_INTSTS_C1DA + DMA_INTSTS_C0DA + DMA_INTSTS_C3FE + DMA_INTSTS_C2FE + DMA_INTSTS_C1FE + DMA_INTSTS_C0FE + DMA_INTSTS_C3PE + DMA_INTSTS_C2PE + DMA_INTSTS_C1PE + DMA_INTSTS_C0PE + DMA_INTSTS_C3BUSY + DMA_INTSTS_C2BUSY + DMA_INTSTS_C1BUSY + DMA_INTSTS_C0BUSY + * @retval interrupt status. + */ +uint8_t DMA_GetINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INTFLAGR(INTMask)); + + if (DMA->STS&INTMask) + return 1; + else + return 0; +} + +/** + * @brief Clear interrupt status. + * @param INTMask: can use the ¡®|¡¯ operator + DMA_INTSTS_C3DA + DMA_INTSTS_C2DA + DMA_INTSTS_C1DA + DMA_INTSTS_C0DA + DMA_INTSTS_C3FE + DMA_INTSTS_C2FE + DMA_INTSTS_C1FE + DMA_INTSTS_C0FE + DMA_INTSTS_C3PE + DMA_INTSTS_C2PE + DMA_INTSTS_C1PE + DMA_INTSTS_C0PE + * @retval None + */ +void DMA_ClearINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_DMA_INTFLAGC(INTMask)); + + DMA->STS = INTMask; +} + +/** + * @brief DMA channel enable. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_Cmd(uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &DMA->C0CTL + Channel*4; + + if (NewState == ENABLE) + *addr |= DMA_CxCTL_EN; + else + *addr &= ~DMA_CxCTL_EN; +} + +/** + * @brief Enable AES encrypt/decrypt function of DMA channel3. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_AESCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + DMA->C3CTL |= DMA_CTL_AESEN; + else + DMA->C3CTL &= ~DMA_CTL_AESEN; +} + +/** + * @brief DMA stop transmit. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void DMA_StopTransmit(uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &DMA->C0CTL + Channel*4; + + if (NewState == ENABLE) + *addr |= DMA_CTL_STOP; + else + *addr &= ~DMA_CTL_STOP; +} + +/** + * @brief Get current frame transferred length. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval Current frame transferred length. + */ +uint8_t DMA_GetFrameLenTransferred(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + addr = &DMA->C0LEN + Channel*4; + return ((*addr&0xFF00)>>8); +} + +/** + * @brief Get current package transferred length. + * @param Channel: + DMA_CHANNEL_0 + DMA_CHANNEL_1 + DMA_CHANNEL_2 + DMA_CHANNEL_3 + * @retval Current package transferred length. + */ +uint8_t DMA_GetPackLenTransferred(uint32_t Channel) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_DMA_CHANNEL(Channel)); + + addr = &DMA->C0LEN + Channel*4; + return (*addr&0xFF); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_flash.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_flash.c new file mode 100644 index 0000000000..261a98eea6 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_flash.c @@ -0,0 +1,297 @@ +/** + ****************************************************************************** + * @file lib_flash.c + * @author Application Team + * @version V4.3.0 + * @date 2018-09-27 + * @brief FLASH library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_flash.h" +#include "lib_clk.h" + +/* FLASH Keys */ +#define FLASH_PASS_KEY 0x55AAAA55 +#define FLASH_SERASE_KEY 0xAA5555AA +#define FLASH_CERASE_KEY 0xAA5555AA +#define FLASH_DSTB_KEY 0xAA5555AA + +#define FLASH_MODE_MASK 0x1F3 + +/** + * @brief FLASH mode initialization. + * @param CSMode: + FLASH_CSMODE_DISABLE + FLASH_CSMODE_ALWAYSON + FLASH_CSMODE_TIM2OF + FLASH_CSMODE_RTC + * @retval None + */ +void FLASH_Init(uint32_t CSMode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FLASH_CSMODE(CSMode)); + + tmp = FLASH->CTRL; + tmp &= ~FLASH_MODE_MASK; + tmp |= CSMode; + FLASH->CTRL = tmp; +} + +/** + * @brief Configure FLASH interrupt. + * @param IntMask: + FLASH_INT_CS + NewState: + ENABLE + DISABLE + * @retval None + */ +void FLASH_INTConfig(uint32_t IntMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = FLASH->CTRL; + tmp &= ~IntMask; + if (NewState == ENABLE) + { + tmp |= IntMask; + } + FLASH->CTRL = tmp; +} + +/** + * @brief Init FLASH 1USCYCLE. + * @param None + * @retval None + */ +void FLASH_CycleInit(void) +{ + uint32_t hclk; + + hclk = CLK_GetHCLKFreq(); + + if (hclk > 1000000) + MISC2->FLASHWC = (hclk/1000000)<<8; + else + MISC2->FLASHWC = 0; +} + +/** + * @brief Erase FLASH sector. + * @param SectorAddr: sector address. + * @retval None + */ +void FLASH_SectorErase(uint32_t SectorAddr) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_ADDRESS(SectorAddr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = SectorAddr; + FLASH->SERASE = FLASH_SERASE_KEY; + while (FLASH->SERASE != 0); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief FLASH word program. + * @param Addr: program start address + WordBuffer: word's buffer pointer to write + Length: The length of WordBuffer + * @retval None + */ +void FLASH_ProgramWord(uint32_t Addr, uint32_t *WordBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADRRW(Addr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = Addr; + for (i=0; iPGDATA = *(WordBuffer++); + } + while (FLASH->STS != 1); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief FLASH half-word progarm. + * @param Addr: program start address + HWordBuffer: half-word's buffer pointer to write + Length: The length of HWordBuffer + * @retval None + */ +void FLASH_ProgramHWord(uint32_t Addr, uint16_t *HWordBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADRRHW(Addr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = Addr; + for (i=0; iPGDATA)) = *(HWordBuffer++); + else + *((__IO uint16_t*)(&FLASH->PGDATA ) + 1) = *(HWordBuffer++); + } + while (FLASH->STS != 1); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief FLASH byte progarm. + * @param Addr: program start address + ByteBuffer: byte's buffer pointer to write + Length: The length of ByteBuffer + * @retval None + */ +void FLASH_ProgramByte(uint32_t Addr, uint8_t *ByteBuffer, uint32_t Length) +{ + uint32_t i; + + /* Check parameters */ + assert_parameters(IS_FLASH_ADDRESS(Addr)); + + /* Unlock flash */ + FLASH->PASS = FLASH_PASS_KEY; + + FLASH->PGADDR = Addr; + for (i=0; iPGDATA)) = *(ByteBuffer++); + else if (((Addr + i)&0x3) == 1) + *((__IO uint8_t*)(&FLASH->PGDATA) + 1) = *(ByteBuffer++); + else if (((Addr + i)&0x3) == 2) + *((__IO uint8_t*)(&FLASH->PGDATA) + 2) = *(ByteBuffer++); + else + *((__IO uint8_t*)(&FLASH->PGDATA) + 3) = *(ByteBuffer++); + } + while (FLASH->STS != 1); + + /* Lock flash */ + FLASH->PASS = 0; +} + +/** + * @brief Get Write status. + * @param None. + * @retval FLASH_WSTA_BUSY + FLASH_WSTA_FINISH + */ +uint32_t FLASH_GetWriteStatus(void) +{ + if (FLASH->STS == 1) + { + return FLASH_WSTA_FINISH; + } + else + { + return FLASH_WSTA_BUSY; + } +} + +/** + * @brief Set checksum range. + * @param AddrStart: checksum start address + AddrEnd: checksum end address + * @retval None + */ +void FLASH_SetCheckSumRange(uint32_t AddrStart, uint32_t AddrEnd) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_CHECKSUMADDR(AddrStart,AddrEnd)); + + FLASH->CSSADDR = AddrStart; + FLASH->CSEADDR = AddrEnd; +} + +/** + * @brief Set checksum compare value. + * @param Checksum: checksum compare value + * @retval None + */ +void FLASH_SetCheckSumCompValue(uint32_t Checksum) +{ + FLASH->CSCVALUE = Checksum; +} + +/** + * @brief Get FLASH checksum value. + * @param None + * @retval Checksum + */ +uint32_t FLASH_GetCheckSum(void) +{ + return FLASH->CSVALUE; +} + + +/** + * @brief Get FLASH interrupt status. + * @param IntMask: + FLASH_INT_CS + * @retval 1: interrupt status set + 0: interrupt status reset + */ +uint8_t FLASH_GetINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + + if (FLASH->INT&FLASH_INT_CSERR) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear FLASH interrupt status. + * @param IntMask: + FLASH_INT_CS + * @retval None + */ +void FLASH_ClearINTStatus(uint32_t IntMask) +{ + /* Check parameters */ + assert_parameters(IS_FLASH_INT(IntMask)); + + if (IntMask == FLASH_INT_CS) + { + FLASH->INT = FLASH_INT_CSERR; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_gpio.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_gpio.c new file mode 100644 index 0000000000..d711a4c592 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_gpio.c @@ -0,0 +1,563 @@ +/** + ****************************************************************************** + * @file lib_gpio.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief GPIO library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_gpio.h" + + +/** + * @brief GPIO initialization. + * @param GPIOx: GPIOB~GPIOF + InitStruct:GPIO configuration. + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + GPIO_Mode: + GPIO_Mode_INPUT + GPIO_Mode_OUTPUT_CMOS + GPIO_Mode_OUTPUT_OD + GPIO_Mode_INOUT_OD + GPIO_Mode_INOUT_CMOS + GPIO_Mode_FORBIDDEN + * @retval None + */ +void GPIOBToF_Init(GPIO_TypeDef *GPIOx, GPIO_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin)); + assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode)); + + if (GPIOF == GPIOx) + InitStruct->GPIO_Pin &= ~(GPIO_Pin_2); + + /* Configure ATT */ + if (InitStruct->GPIO_Mode & 0x2U) + { + tmp_reg1 = GPIOx->ATT; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x1U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->ATT = tmp_reg1; + } + + /* Configure output/input mode */ + tmp_reg1 = GPIOx->OEN; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + tmp_reg2 = GPIOx->IE; + tmp_reg2 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x8U) + { + tmp_reg2 |= InitStruct->GPIO_Pin; + } + if (InitStruct->GPIO_Mode & 0x4U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->OEN = tmp_reg1; + GPIOx->IE = tmp_reg2; +} + +/** + * @brief GPIOA initialization. + * @param GPIOx: GPIOA + InitStruct:GPIO configuration. + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + GPIO_Mode: + GPIO_Mode_INPUT + GPIO_Mode_OUTPUT_CMOS + GPIO_Mode_OUTPUT_OD + GPIO_Mode_INOUT_OD + GPIO_Mode_FORBIDDEN + * @retval None + */ +void GPIOA_Init(GPIOA_TypeDef *GPIOx, GPIO_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(InitStruct->GPIO_Pin)); + assert_parameters(IS_GPIO_MODE(InitStruct->GPIO_Mode)); + + /* Configure ATT */ + if (InitStruct->GPIO_Mode & 0x2U) + { + tmp_reg1 = GPIOx->ATT; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x1U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->ATT = tmp_reg1; + } + + /* Configure output/input mode */ + tmp_reg1 = GPIOx->OEN; + tmp_reg1 &= ~InitStruct->GPIO_Pin; + tmp_reg2 = GPIOx->IE; + tmp_reg2 &= ~InitStruct->GPIO_Pin; + if (InitStruct->GPIO_Mode & 0x8U) + { + tmp_reg2 |= InitStruct->GPIO_Pin; + } + if (InitStruct->GPIO_Mode & 0x4U) + { + tmp_reg1 |= InitStruct->GPIO_Pin; + } + GPIOx->OEN = tmp_reg1; + GPIOx->IE = tmp_reg2; +} + +/** + * @brief Read input data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15. + * @retval input pin value. + */ +uint8_t GPIOBToF_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->STS; + + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read input data register bit. + * @param GPIOx: GPIOA + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15. + * @retval input pin value. + */ +uint8_t GPIOA_ReadInputDataBit(GPIOA_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->STS; + + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read input data register. + * @param GPIOx: GPIOB~GPIOF + * @retval input port value. + */ +uint16_t GPIOBToF_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->STS; +} + +/** + * @brief Read input data register. + * @param GPIOx: GPIOA + * @retval input port value. + */ +uint16_t GPIOA_ReadInputData(GPIOA_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->STS; +} + +/** + * @brief Read output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15 + * @retval output pin value. + */ +uint8_t GPIOBToF_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->DAT; + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin:GPIO_Pin_0~GPIO_Pin_15 + * @retval output pin value. + */ +uint8_t GPIOA_ReadOutputDataBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PINR(GPIO_Pin)); + + tmp = GPIOx->DAT; + tmp &= GPIO_Pin; + if (tmp) + return 1; + else + return 0; +} + +/** + * @brief Read output data register. + * @param GPIOx: GPIOB~GPIOF + * @retval Output port value. + */ +uint16_t GPIOBToF_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->DAT; +} + +/** + * @brief Read output data register. + * @param GPIOx: GPIOA + * @retval Output port value. + */ +uint16_t GPIOA_ReadOutputData(GPIOA_TypeDef* GPIOx) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + return GPIOx->DAT; +} + +/** + * @brief Set output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0 ~ GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOBToF_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT |= GPIO_Pin; +} + +/** + * @brief Set output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOA_SetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT |= GPIO_Pin; +} + +/** + * @brief Reset output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOBToF_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT &= ~GPIO_Pin; +} + +/** + * @brief Reset output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + * @retval None. + */ +void GPIOA_ResetBits(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->DAT &= ~GPIO_Pin; +} + +/** + * @brief Write output data register bit. + * @param GPIOx: GPIOB~GPIOF + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + val:value write to register bit. + * @retval None. + */ +void GPIOBToF_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + assert_parameters(IS_GPIO_BITVAL(val)); + + if (val == 1) + { + GPIOx->DAT |= GPIO_Pin; + } + else + { + GPIOx->DAT &= ~GPIO_Pin; + } +} + +/** + * @brief Write output data register bit. + * @param GPIOx: GPIOA + GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + val:value write to register bit. + * @retval None. + */ +void GPIOA_WriteBit(GPIOA_TypeDef* GPIOx, uint16_t GPIO_Pin, uint8_t val) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + assert_parameters(IS_GPIO_BITVAL(val)); + + if (val == 1) + { + GPIOx->DAT |= GPIO_Pin; + } + else + { + GPIOx->DAT &= ~GPIO_Pin; + } +} + +/** + * @brief Write output data register. + * @param GPIOx: GPIOB~GPIOF + val:value write to register. + * @retval None. + */ +void GPIOBToF_Write(GPIO_TypeDef* GPIOx, uint16_t val) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_ALL_INSTANCE(GPIOx)); + + GPIOx->DAT = val; +} + +/** + * @brief Write output data register. + * @param GPIOx: GPIOA + val:value write to register. + * @retval None. + */ +void GPIOA_Write(GPIOA_TypeDef* GPIOx, uint16_t val) +{ + /* Check parameters */ + assert_parameters(IS_PMUIO_ALL_INSTANCE(GPIOx)); + + GPIOx->DAT = val; +} + +/** + * @brief GPIO AF configure. + * @param GPIOx:GPIOB GPIOE + GPIO_AFx: + GPIOB_AF_PLLHDIV + GPIOB_AF_OSC + GPIOB_AF_PLLLOUT + GPIOE_AF_CMP1O + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOBToF_AFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_AFx, uint8_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIOAF_ALL_INSTANCE(GPIOx)); + assert_parameters(IS_GPIO_GPIOAF(GPIO_AFx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (GPIOx == GPIOB) + { + tmp = GPIOAF->SELB; + if (NewState != DISABLE) + { + tmp |= GPIO_AFx; + } + else + { + tmp &= ~GPIO_AFx; + } + GPIOAF->SELB = tmp; + } + if (GPIOx == GPIOE) + { + tmp = GPIOAF->SELE; + if (NewState != DISABLE) + { + tmp |= GPIO_AFx; + } + else + { + tmp &= ~GPIO_AFx; + } + GPIOAF->SELE = tmp; + } +} + +/** + * @brief GPIO AF configure. + * @param PMUIO_AFx: + PMUIO7_AF_PLLDIV + PMUIO_AF_CMP2O + PMUIO3_AF_PLLDIV + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOA_AFConfig(uint32_t PMUIO_AFx, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PMUIOAF(PMUIO_AFx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + GPIOA->SEL |= PMUIO_AFx; + } + else + { + GPIOA->SEL &= ~PMUIO_AFx; + } +} + +/** + * @brief GPIO pin remap. + * @param GPIO_Remap: + GPIO_REMAP_I2C + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, uint8_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_REMAP(GPIO_Remap)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = GPIOAF->_MISC; + tmp &= ~GPIO_Remap; + if (NewState == ENABLE) + tmp |= GPIO_Remap; + GPIOAF->_MISC = tmp; +} + +/** + * @brief GPIO PLLDIV configure. + * @param Divider: + GPIO_PLLDIV_1 + GPIO_PLLDIV_2 + GPIO_PLLDIV_4 + GPIO_PLLDIV_8 + GPIO_PLLDIV_16 + * @retval None. + */ +void GPIO_PLLDIV_Config(uint32_t Divider) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_PLLDIV(Divider)); + + tmp = GPIOAF->_MISC; + tmp &= ~IO_MISC_PLLHDIV; + tmp |= Divider; + GPIOAF->_MISC = tmp; +} + +/** + * @brief GPIOA de-glitch circuit control. + * @param GPIO_Pin: can use the ¡®|¡¯ operator + GPIO_Pin_0~GPIO_Pin_15 or GPIO_Pin_All + NewState: + ENABLE + DISABLE + * @retval None. + */ +void GPIOA_NoDeg_Cmd( uint16_t GPIO_Pin, uint8_t NewState) +{ + uint16_t tmp; + + /* Check parameters */ + assert_parameters(IS_GPIO_PIN(GPIO_Pin)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = GPIOA->IOANODEG; + /*IOA wake-up signal will not go through de-glitch circuit.*/ + if (NewState != DISABLE) + { + tmp |= GPIO_Pin; + } + /*IOA wake-up signal will go through de-glitch circuit.*/ + else + { + tmp &= ~GPIO_Pin; + } + GPIOA->IOANODEG = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c new file mode 100644 index 0000000000..1bf70cb182 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_i2c.c @@ -0,0 +1,689 @@ +/** + ****************************************************************************** + * @file lib_i2c.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief IIC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_i2c.h" + +//registers default reset values +#define I2C_ADDR_RSTValue 0 +#define I2C_CTRL_RSTValue 0 +#define I2C_CTRL2_RSTValue 0 + +/* Private Functions -------------------------------------------------------- */ +static uint16_t I2C_CheckState(uint8_t State); +static void I2C_SendStart(void); +static void I2C_SendRestart(void); +static void I2C_SendByte(uint8_t dat); +static void I2C_SendStop(void); +static uint8_t I2C_ReceiveByte(void); +static void I2C_ClearBus(uint32_t remap); +static void I2C_WaitForCrossPage(uint8_t sla); + +/** + * @brief Check required state. + * @param State: + Required state. + * @retval 0: state OK + !0: state Error, [15:8]Required status code, [7:0] real status code. + */ +static uint16_t I2C_CheckState(uint8_t State) +{ + uint16_t ret; + if (I2C_GetStatusCode() != State) + { + ret = (State<<8)|(I2C_GetStatusCode()); + return ret; + } + else + { + return 0; + } +} + +/** + * @brief Send start signal. + * @param None + * @retval None + */ +static void I2C_SendStart(void) +{ + I2C_GenerateSTART(ENABLE); + while (I2C_GetINTStatus() == 0); + I2C_GenerateSTART(DISABLE); +} + +/** + * @brief Send restart signal. + * @param None + * @retval None + */ +static void I2C_SendRestart(void) +{ + I2C_GenerateSTART(ENABLE); + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); + I2C_GenerateSTART(DISABLE); +} + +/** + * @brief Send stop signal. + * @param None + * @retval None + */ +static void I2C_SendStop(void) +{ + I2C_GenerateSTOP(ENABLE); + I2C_ClearINTStatus(); + I2C_GenerateSTOP(DISABLE); +} + +/** + * @brief Send data. + * @param dat:data to send. + * @retval None + */ +static void I2C_SendByte(uint8_t dat) +{ + I2C_SendData(dat); + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); +} + +/** + * @brief Receive byte. + * @param None + * @retval Byte received + */ +static uint8_t I2C_ReceiveByte(void) +{ + I2C_ClearINTStatus(); + while (I2C_GetINTStatus() == 0); + return I2C_ReceiveData(); +} + +/** + * @brief Wait for cross page operation done. + * @param None + * @retval None + */ +static void I2C_WaitForCrossPage(uint8_t sla) +{ + do + { + I2C_SendRestart(); + I2C_SendByte(sla); //device address + }while (I2C_GetStatusCode() !=0x18); + I2C_SendStop(); //stop +} + +static void I2C_ClearBus(uint32_t remap) +{ + __IO uint8_t i, j; + + if (remap) // I2C remap enable, SCL IOC4 + { + GPIOC->DAT &= ~BIT4; + GPIOC->ATT |= BIT4; + GPIOC->OEN &= ~BIT4; + for (i=0; i<9; i++) + { + GPIOC->DAT |= BIT4; + for (j=0; j<100; j++) + __NOP(); + GPIOC->DAT &= ~BIT4; + for (j=0; j<100; j++) + __NOP(); + } + GPIOC->DAT |= BIT4; + GPIOC->OEN |= BIT4; + GPIOC->IE &= ~BIT4; + } + else // I2C remap disable, SCL IOB13 + { + GPIOB->DAT &= ~BIT13; + GPIOB->ATT |= BIT13; + GPIOB->OEN &= ~BIT13; + for (i=0; i<9; i++) + { + GPIOB->DAT |= BIT13; + for (j=0; j<100; j++) + __NOP(); + GPIOB->DAT &= ~BIT13; + for (j=0; j<100; j++) + __NOP(); + } + GPIOB->DAT |= BIT13; + GPIOB->OEN |= BIT13; + GPIOB->IE &= ~BIT13; + } +} + +/* Exported Functions ------------------------------------------------------- */ + +/** + * @brief Initializes the I2C peripheral registers to their default reset values. + * @param remap: I2C_REMAP_ENABLE or I2C_REMAP_DISABLE + * @retval None + */ +void I2C_DeInit(uint32_t remap) +{ + I2C->CTRL &= ~I2C_CTRL_EN; + + I2C->ADDR = I2C_ADDR_RSTValue; + I2C->CTRL = I2C_CTRL_RSTValue; + I2C->CTRL2 = I2C_CTRL2_RSTValue; + + I2C_ClearBus(remap); +} + +/** + * @brief Fills each InitStruct member with its default value. + * @param InitStruct: pointer to an I2C_InitType structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitType *InitStruct) +{ + /*--------------- Reset I2C init structure parameters values ---------------*/ + /* Initialize the AssertAcknowledge member */ + InitStruct->AssertAcknowledge = I2C_ASSERTACKNOWLEDGE_DISABLE; + /* Initialize the ClockSource member */ + InitStruct->ClockSource = I2C_CLOCKSOURCE_APBD256; + /* Initialize the GeneralCallAck member */ + InitStruct->GeneralCallAck = I2C_GENERALCALLACK_DISABLE; + /* Initialize the SlaveAddr member */ + InitStruct->SlaveAddr = 0; +} + +/** + * @brief I2C initialization. + * @param InitStruct: I2C configuration. + SlaveAddr: Own I2C slave address (7 bit) + GeneralCallAck: + I2C_GENERALCALLACK_ENABLE + I2C_GENERALCALLACK_DISABLE + AssertAcknowledge: + I2C_ASSERTACKNOWLEDGE_ENABLE + I2C_ASSERTACKNOWLEDGE_DISABLE + ClockSource: + I2C_CLOCKSOURCE_APBD256 + I2C_CLOCKSOURCE_APBD224 + I2C_CLOCKSOURCE_APBD192 + I2C_CLOCKSOURCE_APBD160 + I2C_CLOCKSOURCE_APBD960 + I2C_CLOCKSOURCE_APBD120 + I2C_CLOCKSOURCE_APBD60 + I2C_CLOCKSOURCE_TIM3OFD8 + * @retval None. + */ +void I2C_Init(I2C_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_I2C_GC(InitStruct->GeneralCallAck)); + assert_parameters(IS_I2C_AA(InitStruct->AssertAcknowledge)); + assert_parameters(IS_I2C_CLKSRC(InitStruct->ClockSource)); + + I2C->ADDR = InitStruct->SlaveAddr\ + |InitStruct->GeneralCallAck; + tmp = I2C->CTRL; + tmp &= ~(I2C_CTRL_CR\ + |I2C_CTRL_AA); + tmp |= (InitStruct->ClockSource\ + |InitStruct->AssertAcknowledge); + I2C->CTRL = tmp; +} + +/** + * @brief Interrupt configure. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_INTConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL2 |= I2C_CTRL2_INTEN; + else + I2C->CTRL2 &= ~I2C_CTRL2_INTEN; +} + +/** + * @brief Get interrupt status. + * @param None + * @retval Interrupt status. + */ +uint8_t I2C_GetINTStatus(void) +{ + if (I2C->CTRL&I2C_CTRL_SI) + return 1; + else + return 0; +} + +/** + * @brief Clear interrupt status. + * @param None + * @retval None. + */ +void I2C_ClearINTStatus(void) +{ + I2C->CTRL &= ~I2C_CTRL_SI; +} + +/** + * @brief Read a packge of data from slave device. + * @param InitStruct: I2C_WRType + SlaveAddr : Slave device address + SubAddress : start of slave device sub-address + PageRange : maximum range of page to Read operation + pBuffer : Read data pointer + Length : sum of Read datas + SubAddrType: + I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte) + I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes) + I2C_SUBADDR_OTHER (Slave device sub-address type: othres) + * @retval 0: true + £¡0£ºstatus code + bit15~8 status code(true) + bit7~0 status code(false) + */ +uint16_t I2C_MasterReadBytes(I2C_WRType *InitStruct) +{ + uint32_t i; + uint16_t ret_val; + + /* Check parameters */ + assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType)); + + I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA + /*-------------------------------- START -----------------------------------*/ + I2C_SendStart(); + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + + /*------------------------------ Send SLA+W --------------------------------*/ + /* Slave device sub-address type: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: 2 bytes */ + if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: othres */ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + /*------------------------------- Restart ----------------------------------*/ + I2C_SendRestart(); //restart + ret_val = I2C_CheckState(0x10); + if (ret_val) return ret_val; + + /*----------------------------- Send SLA+R ---------------------------------*/ + /* Slave device sub-address type: othres */ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>7)&0xE)); + else // 16 + x + I2C_SendByte(InitStruct->SlaveAddr|0x01|((InitStruct->SubAddress>>15)&0xE)); + } + else + I2C_SendByte(InitStruct->SlaveAddr|0x01); + + ret_val = I2C_CheckState(0x40); + if (ret_val) return ret_val; + + /*----------------------------- Read datas ---------------------------------*/ + for (i=0; i<(InitStruct->Length-1); i++) + { + *InitStruct->pBuffer = I2C_ReceiveByte(); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x50); + if (ret_val) return ret_val; + } + /*-------------------- Read the last data, disable AA ----------------------*/ + I2C_AssertAcknowledgeConfig(DISABLE); + *InitStruct->pBuffer = I2C_ReceiveByte(); + ret_val = I2C_CheckState(0x58); + if (ret_val) return ret_val; + /*--------------------------------- Stop -----------------------------------*/ + I2C_SendStop(); //stop + return 0; +} + +/** + * @brief Write a packge of data to slave device. + * @param InitStruct: I2C_WRType + SlaveAddr : Slave device address + SubAddress : start of slave device sub-address + PageRange : maximum range of page to write operation + pBuffer : write data pointer + Length : sum of write datas + SubAddrType: + I2C_SUBADDR_1BYTE (Slave device sub-address type: 1 byte) + I2C_SUBADDR_2BYTE (Slave device sub-address type: 2 bytes) + I2C_SUBADDR_OTHER (Slave device sub-address type: othres) + * @retval 0: true + £¡0£ºstatus code + bit15~8 status code(true) + bit7~0 status code(false) + */ +uint16_t I2C_MasterWriteBytes(I2C_WRType *InitStruct) +{ + uint16_t ret_val; + uint32_t i; + + /* Check parameters */ + assert_parameters(I2C_SUBADDR_TYPE(InitStruct->SubAddrType)); + + I2C_AssertAcknowledgeConfig(ENABLE); //Enable AA + /*-------------------------------- START -----------------------------------*/ + I2C_SendStart(); + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + + /*------------------------------ Send SLA+W --------------------------------*/ + /* Slave device sub-address type: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: 2 bytes */ + else if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); //device address + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); //first word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); //second word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Slave device sub-address type: othres */ + else + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|((InitStruct->SubAddress>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte(InitStruct->SubAddress&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + /*----------------------------- Write datas --------------------------------*/ + for (i=0; i<(InitStruct->Length); i++) + { + /* Reach the page boundary */ + if ((i > 0) && ((InitStruct->SubAddress+i)%InitStruct->PageRange == 0)) + { + I2C_SendStop(); + I2C_WaitForCrossPage(InitStruct->SlaveAddr); + I2C_SendStart(); //start + ret_val = I2C_CheckState(0x08); + if (ret_val) return ret_val; + /* WriteAddr: 1 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_1BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* WriteAddr: 2 byte */ + if (InitStruct->SubAddrType == I2C_SUBADDR_2BYTE) + { + I2C_SendByte(InitStruct->SlaveAddr); //device address + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); //first word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); //second word address + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* WriteAddr: (16 or 8)+x*/ + if (InitStruct->SubAddrType == I2C_SUBADDR_OTHER) + { + if (InitStruct->PageRange < 256) // 8 + x + { + I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>7)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + else // 16 + x + { + I2C_SendByte(InitStruct->SlaveAddr|(((InitStruct->SubAddress+i)>>15)&0xE)); + ret_val = I2C_CheckState(0x18); + if (ret_val) return ret_val; + + I2C_SendByte(((InitStruct->SubAddress+i)>>8)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + + I2C_SendByte((InitStruct->SubAddress+i)&0xFF); + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + I2C_SendByte(*InitStruct->pBuffer); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + /* Not reaching the page boundary */ + else + { + I2C_SendByte(*InitStruct->pBuffer); + InitStruct->pBuffer++; + ret_val = I2C_CheckState(0x28); + if (ret_val) return ret_val; + } + } + + I2C_SendStop(); + I2C_WaitForCrossPage(InitStruct->SlaveAddr); + return 0; +} + +/** + * @brief I2C enable. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_EN; + else + I2C->CTRL &= ~I2C_CTRL_EN; +} + +/* I2C Exported Functions Group5: + Others ------------------------------------*/ + +/** + * @brief Assert acknowledge configure. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_AssertAcknowledgeConfig(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_AA; + else + I2C->CTRL &= ~I2C_CTRL_AA; +} + +/** + * @brief Receive a byte data. + * @param None. + * @retval Data received. + */ +uint8_t I2C_ReceiveData(void) +{ + return I2C->DATA; +} + +/** + * @brief Sends a byte data. + * @param Dat:data to transmit. + * @retval None + */ +void I2C_SendData(uint8_t Dat) +{ + I2C->DATA = Dat; +} + +/** + * @brief Generate start signal. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_GenerateSTART(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_STA; + else + I2C->CTRL &= ~I2C_CTRL_STA; +} + +/** + * @brief Generate stop signal. + * @param NewState: + ENABLE + DISABLE + * @retval None. + */ +void I2C_GenerateSTOP(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + I2C->CTRL |= I2C_CTRL_STO; + else + I2C->CTRL &= ~I2C_CTRL_STO; +} + +/** + * @brief Get status code. + * @param None + * @retval status code. + */ +uint8_t I2C_GetStatusCode(void) +{ + return (I2C->STS&I2C_STS_STS); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_iso7816.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_iso7816.c new file mode 100644 index 0000000000..73a7992de9 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_iso7816.c @@ -0,0 +1,396 @@ +/** + ****************************************************************************** + * @file lib_iso7816.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief ISO7816 library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_iso7816.h" +#include "lib_clk.h" + +//registers default reset values +#define ISO7816_BAUDDIVL_RSTValue 0 +#define ISO7816_BAUDDIVH_RSTValue 0 +#define ISO7816_CFG_RSTValue 0 +#define ISO7816_CLK_RSTValue 0 + +#define ISO7816_INFO_RC_MASK (0xECUL) //R/C +#define ISO7816_INFO_RW_MASK (0x13UL) //R/W + +/** + * @brief ISO7816 initialization. + * @param ISO7816x: ISO78160~ISO78161 + Init_Struct:iso7816 configuration. + FirstBit: + ISO7816_FIRSTBIT_LSB + ISO7816_FIRSTBIT_MSB + ACKLen: + ISO7816_ACKLEN_1 + ISO7816_ACKLEN_2 + Parity: + ISO7816_PARITY_EVEN + ISO7816_PARITY_ODD + Baudrate: Baud rate value + * @retval None + */ +void ISO7816_Init(ISO7816_TypeDef *ISO7816x, ISO7816_InitType *Init_Struct) +{ + uint32_t tmp; + uint16_t div; + uint32_t pclk; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FIRSTBIT(Init_Struct->FirstBit)); + assert_parameters(IS_ISO7816_ACKLEN(Init_Struct->ACKLen)); + assert_parameters(IS_ISO7816_PARITY(Init_Struct->Parity)); + assert_parameters(IS_ISO7816_BAUDRATE(Init_Struct->Baudrate)); + + tmp = ISO7816x->INFO; + tmp &= ~(ISO7816_INFO_LSB|ISO7816_INFO_RC_MASK); + tmp |= Init_Struct->FirstBit; + ISO7816x->INFO = tmp; + + tmp = ISO7816x->CFG; + tmp &= ~(ISO7816_CFG_ACKLEN\ + |BIT3\ + |BIT2\ + |ISO7816_CFG_CHKP); + tmp |= (Init_Struct->ACKLen\ + |Init_Struct->Parity); + ISO7816x->CFG = tmp; + + pclk = CLK_GetPCLKFreq(); + div = 0x10000 - (pclk/Init_Struct->Baudrate); + ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH; + ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL; +} + +/** + * @brief Fills each InitStruct member with its default value. + * @param InitStruct: pointer to an ISO7816_InitType structure which will be initialized. + * @retval None + */ +void ISO7816_StructInit(ISO7816_InitType *InitStruct) +{ + /*--------------- Reset ISO7816 init structure parameters values ---------------*/ + /* Initialize the ACKLen member */ + InitStruct->ACKLen = ISO7816_ACKLEN_1; + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = ISO7816_FIRSTBIT_MSB; + /* Initialize the Parity member */ + InitStruct->Parity = ISO7816_PARITY_EVEN; +} + +/** + * @brief Initializes the ISO7816 peripheral registers to their default reset + values. + * @param ISO7816x: ISO78160~ISO78161 + * @retval None + */ +void ISO7816_DeInit(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + ISO7816x->CFG &= ~ISO7816_CFG_EN; + + /* clear interrupt flag */ + ISO7816x->INFO = ISO7816_INFO_RC_MASK; + ISO7816x->BAUDDIVH = ISO7816_BAUDDIVH_RSTValue; + ISO7816x->BAUDDIVL = ISO7816_BAUDDIVL_RSTValue; + ISO7816x->CFG = ISO7816_CFG_RSTValue; + ISO7816x->CLK = ISO7816_CLK_RSTValue; +} + +/** + * @brief ISO7816 enable control. + * @param ISO7816x: ISO78160~ISO78161 + NewState: + ENABLE + DISABLE + * @retval None. + */ +void ISO7816_Cmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + ISO7816x->CFG |= ISO7816_CFG_EN; + } + else + { + ISO7816x->CFG &= ~ISO7816_CFG_EN; + } +} + +/** + * @brief ISO7816 Baudrate control. + * @param ISO7816x: ISO78160~ISO78161 + BaudRate: + * @retval None + */ +void ISO7816_BaudrateConfig(ISO7816_TypeDef *ISO7816x, uint32_t BaudRate) +{ + uint32_t pclk; + uint16_t div; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_BAUDRATE(BaudRate)); + + pclk = CLK_GetPCLKFreq(); + div = 0x10000 - (pclk/BaudRate); + ISO7816x->BAUDDIVH = (div>>8) & ISO7816_BAUDDIVH; + ISO7816x->BAUDDIVL = div & ISO7816_BAUDDIVL; +} + +/** + * @brief ISO7816 clock divider configure. + * @param ISO7816x: ISO78160~ISO78161 + Prescaler:1~128 + * @retval None + */ +void ISO7816_CLKDIVConfig(ISO7816_TypeDef *ISO7816x, uint32_t Prescaler) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_PRESCALER(Prescaler)); + + tmp = ISO7816x->CLK; + tmp &= ~ISO7816_CLK_CLKDIV; + tmp |= ((Prescaler - 1) & ISO7816_CLK_CLKDIV); + ISO7816x->CLK = tmp; +} + +/** + * @brief ISO7816 clock output enable control. + * @param ISO7816x: ISO78160~ISO78161 + NewState: + ENABLE + DISABLE + * @retval None + */ +void ISO7816_CLKOutputCmd(ISO7816_TypeDef *ISO7816x, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + ISO7816x->CLK |= ISO7816_CLK_CLKEN; + } + else + { + ISO7816x->CLK &= ~ISO7816_CLK_CLKEN; + } +} + +/** + * @brief Read data. + * @param ISO7816: ISO78160~ISO78161 + * @retval The received data. + */ +uint8_t ISO7816_ReceiveData(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + return ISO7816x->DATA; +} + +/** + * @brief Write data. + * @param ISO7816x: ISO78160~ISO78161 + * @retval None + */ +void ISO7816_SendData(ISO7816_TypeDef *ISO7816x, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + ISO7816x->DATA = ch; +} + +/** + * @brief Interrupt configure. + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + This parameter can be any combination of the following values + ISO7816_INT_RXOV + ISO7816_INT_RX + ISO7816_INT_TX + NewState: + ENABLE + DISABLE + * @retval None + */ +void ISO7816_INTConfig(ISO7816_TypeDef *ISO7816x, uint32_t INTMask, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + ISO7816x->CFG |= INTMask; + } + else + { + ISO7816x->CFG &= ~INTMask; + } +} + +/** + * @brief Get interrupt state + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + ISO7816_INTSTS_RXOV + ISO7816_INTSTS_RX + ISO7816_INTSTS_TX + * @retval 1: state set + 0: state reset + */ +uint8_t ISO7816_GetINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INTFLAGR(INTMask)); + + if (ISO7816x->INFO & INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt state. + * @param ISO7816x: ISO78160~ISO78161 + INTMask: + This parameter can be any combination of the following values + ISO7816_INTSTS_RXOV + ISO7816_INTSTS_RX + ISO7816_INTSTS_TX + * @retval None + */ +void ISO7816_ClearINTStatus(ISO7816_TypeDef *ISO7816x, uint32_t INTMask) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_INTFLAGC(INTMask)); + + tmp = ISO7816x->INFO; + tmp &= ~ISO7816_INFO_RC_MASK; + tmp |= INTMask; + ISO7816x->INFO = tmp; +} + +/** + * @brief Get peripheral flag. + * @param ISO7816x: ISO78160~ISO78161 + FlagMask: + ISO7816_FLAG_SDERR + ISO7816_FLAG_RCERR + * @retval 1: state set + 0: state reset + */ +uint8_t ISO7816_GetFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FLAGR(FlagMask)); + + if (ISO7816x->INFO&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear peripheral flag. + * @param ISO7816x: ISO78160~ISO78161 + FlagMask: + This parameter can be any combination of the following values + ISO7816_FLAG_SDERR + ISO7816_FLAG_RCERR + * @retval None + */ +void ISO7816_ClearFlag(ISO7816_TypeDef *ISO7816x, uint32_t FlagMask) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + assert_parameters(IS_ISO7816_FLAGC(FlagMask)); + + tmp = ISO7816x->INFO; + tmp &= ~ISO7816_INFO_RC_MASK; + tmp |= FlagMask; + ISO7816x->INFO = tmp; +} + +/** + * @brief Get last transmit ACK. + * @param ISO7816: ISO78160~ISO78161 + * @retval ACK value + */ +uint8_t ISO7816_GetLastTransmitACK(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + if (ISO7816x->INFO&ISO7816_INFO_RCACK) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Get last receive check sum bit. + * @param ISO7816: ISO78160~ISO78161 + * @retval CHKSUM bit value + */ +uint8_t ISO7816_GetLastReceiveCHKSUM(ISO7816_TypeDef *ISO7816x) +{ + /* Check parameters */ + assert_parameters(IS_ISO7816_ALL_INSTANCE(ISO7816x)); + + if (ISO7816x->INFO&ISO7816_INFO_CHKSUM) + { + return 1; + } + else + { + return 0; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_lcd.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_lcd.c new file mode 100644 index 0000000000..50a2015401 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_lcd.c @@ -0,0 +1,601 @@ +/** + ****************************************************************************** + * @file lib_lcd.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief LCD library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_lcd.h" +#include "lib_LoadNVR.h" + +//registers default reset values +#define LCD_CTRL_RSTValue 0 +#define LCD_CTRL2_RSTValue 0 +#define LCD_SEGCTRL0_RSTValue 0 +#define LCD_SEGCTRL1_RSTValue 0 +#define LCD_SEGCTRL2_RSTValue 0 + +/* COMx IO */ +const LCD_SEGIO lcd_comio[] = +{ + {&GPIOD->OEN, GPIO_Pin_0}, + {&GPIOD->OEN, GPIO_Pin_1}, + {&GPIOD->OEN, GPIO_Pin_2}, + {&GPIOD->OEN, GPIO_Pin_3}, + {&GPIOD->OEN, GPIO_Pin_4}, + {&GPIOD->OEN, GPIO_Pin_5}, + {&GPIOD->OEN, GPIO_Pin_6}, + {&GPIOD->OEN, GPIO_Pin_7}, +}; + +/* SEGx IO */ +const LCD_SEGIO lcd_segio[] = +{ /**************************/ + /* SEG | GPIO | Pin */ + {&GPIOD->OEN, GPIO_Pin_4}, /* 0 D 4 */ + {&GPIOD->OEN, GPIO_Pin_5}, /* 1 D 5 */ + {&GPIOD->OEN, GPIO_Pin_6}, /* 2 D 6 */ + {&GPIOD->OEN, GPIO_Pin_7}, /* 3 D 7 */ + {&GPIOD->OEN, GPIO_Pin_8}, /* 4 D 8 */ + {&GPIOD->OEN, GPIO_Pin_9}, /* 5 D 9 */ + {&GPIOD->OEN, GPIO_Pin_10}, /* 6 D 10 */ + {&GPIOD->OEN, GPIO_Pin_11}, /* 7 D 11 */ + {&GPIOD->OEN, GPIO_Pin_12}, /* 8 D 12 */ + {&GPIOD->OEN, GPIO_Pin_13}, /* 9 D 13 */ + {&GPIOD->OEN, GPIO_Pin_14}, /* 10 D 14 */ + {&GPIOD->OEN, GPIO_Pin_15}, /* 11 D 15 */ + {&GPIOB->OEN, GPIO_Pin_4}, /* 12 B 4 */ + {&GPIOA->OEN, GPIO_Pin_14}, /* 13 A 14 */ + {&GPIOB->OEN, GPIO_Pin_5}, /* 14 B 5 */ + {&GPIOA->OEN, GPIO_Pin_15}, /* 15 A 15 */ + {&GPIOC->OEN, GPIO_Pin_0}, /* 16 C 0 */ + {&GPIOC->OEN, GPIO_Pin_1}, /* 17 C 1 */ + {&GPIOC->OEN, GPIO_Pin_2}, /* 18 C 2 */ + {&GPIOC->OEN, GPIO_Pin_3}, /* 19 C 3 */ + {&GPIOC->OEN, GPIO_Pin_4}, /* 20 C 4 */ + {&GPIOC->OEN, GPIO_Pin_5}, /* 21 C 5 */ + {&GPIOC->OEN, GPIO_Pin_6}, /* 22 C 6 */ + {&GPIOC->OEN, GPIO_Pin_7}, /* 23 C 7 */ + {&GPIOC->OEN, GPIO_Pin_8}, /* 24 C 8 */ + {&GPIOC->OEN, GPIO_Pin_9}, /* 25 C 9 */ + {&GPIOC->OEN, GPIO_Pin_10}, /* 26 C 10 */ + {&GPIOC->OEN, GPIO_Pin_11}, /* 27 C 11 */ + {&GPIOC->OEN, GPIO_Pin_12}, /* 28 C 12 */ + {&GPIOC->OEN, GPIO_Pin_13}, /* 29 C 13 */ + {&GPIOC->OEN, GPIO_Pin_14}, /* 30 C 14 */ + {&GPIOC->OEN, GPIO_Pin_15}, /* 31 C 15 */ + {&GPIOE->OEN, GPIO_Pin_10}, /* 32 E 10 */ + {&GPIOE->OEN, GPIO_Pin_11}, /* 33 E 11 */ + {&GPIOE->OEN, GPIO_Pin_12}, /* 34 E 12 */ + {&GPIOB->OEN, GPIO_Pin_8}, /* 35 B 8 */ + {&GPIOB->OEN, GPIO_Pin_9}, /* 36 B 9 */ + {&GPIOB->OEN, GPIO_Pin_10}, /* 37 B 10 */ + {&GPIOB->OEN, GPIO_Pin_11}, /* 38 B 11 */ + {&GPIOB->OEN, GPIO_Pin_12}, /* 39 B 12 */ + {&GPIOB->OEN, GPIO_Pin_13}, /* 40 B 13 */ + {&GPIOB->OEN, GPIO_Pin_14}, /* 41 B 14 */ + {&GPIOB->OEN, GPIO_Pin_15}, /* 42 B 15 */ + {&GPIOB->OEN, GPIO_Pin_0}, /* 43 B 0 */ + {&GPIOB->OEN, GPIO_Pin_6}, /* 44 B 6 */ + {&GPIOB->OEN, GPIO_Pin_1}, /* 45 B 1 */ + {&GPIOB->OEN, GPIO_Pin_7}, /* 46 B 7 */ + {&GPIOA->OEN, GPIO_Pin_11}, /* 47 A 11 */ + {&GPIOA->OEN, GPIO_Pin_10}, /* 48 A 10 */ + {&GPIOA->OEN, GPIO_Pin_9}, /* 49 A 9 */ + {&GPIOA->OEN, GPIO_Pin_8}, /* 50 A 8 */ + {&GPIOA->OEN, GPIO_Pin_3}, /* 51 A 3 */ + {&GPIOA->OEN, GPIO_Pin_2}, /* 52 A 2 */ + {&GPIOA->OEN, GPIO_Pin_1}, /* 53 A 1 */ + {&GPIOA->OEN, GPIO_Pin_0}, /* 54 A 0 */ + {&GPIOE->OEN, GPIO_Pin_13}, /* 55 E 13 */ + {&GPIOE->OEN, GPIO_Pin_14}, /* 56 E 14 */ + {&GPIOE->OEN, GPIO_Pin_15}, /* 57 E 15 */ + {&GPIOE->OEN, GPIO_Pin_9}, /* 58 E 9 */ + {&GPIOE->OEN, GPIO_Pin_8}, /* 59 E 8 */ + {&GPIOE->OEN, GPIO_Pin_7}, /* 60 E 7 */ + {&GPIOE->OEN, GPIO_Pin_6}, /* 61 E 6 */ + {&GPIOE->OEN, GPIO_Pin_5}, /* 62 E 5 */ + {&GPIOE->OEN, GPIO_Pin_4}, /* 63 E 4 */ + {&GPIOE->OEN, 0}, /* 64 NC NC */ + {&GPIOE->OEN, 0}, /* 65 NC NC */ + {&GPIOA->OEN, GPIO_Pin_4}, /* 66 A 4 */ + {&GPIOA->OEN, GPIO_Pin_5}, /* 67 A 5 */ + {&GPIOA->OEN, GPIO_Pin_6}, /* 68 A 6 */ + {&GPIOA->OEN, GPIO_Pin_7}, /* 69 A 7 */ + {&GPIOB->OEN, GPIO_Pin_2}, /* 70 B 2 */ + {&GPIOA->OEN, GPIO_Pin_12}, /* 71 A 12 */ + {&GPIOB->OEN, GPIO_Pin_3}, /* 72 B 3 */ + {&GPIOA->OEN, GPIO_Pin_13}, /* 73 A 13 */ + {&GPIOE->OEN, GPIO_Pin_0}, /* 74 E 0 */ + {&GPIOE->OEN, GPIO_Pin_1}, /* 75 E 1 */ + {&GPIOE->OEN, GPIO_Pin_2}, /* 76 E 2 */ + {&GPIOE->OEN, GPIO_Pin_3}, /* 77 E 3 */ + {&GPIOE->OEN, 0}, /* 78 NC NC */ + {&GPIOE->OEN, 0} /* 79 NC NC */ +}; + +/** + * @brief LCD initialization. + * @param InitStruct: LCD configuration. + Type: + LCD_TYPE_4COM + LCD_TYPE_6COM + LCD_TYPE_8COM + Drv: + LCD_DRV_300 + LCD_DRV_600 + LCD_DRV_150 + LCD_DRV_200 + FRQ: + LCD_FRQ_64H + LCD_FRQ_128H + LCD_FRQ_256H + LCD_FRQ_512H + SWPR: Frame buffer switch period(0.5 sec * (SWPR + 1)). + FBMODE: + LCD_FBMODE_BUFA + LCD_FBMODE_BUFAB + LCD_FBMODE_BUFABLANK + BKFILL: + LCD_BKFILL_1 + LCD_BKFILL_0 + * @retval None + */ +void LCD_Init(LCD_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_LCD_TYPE(InitStruct->Type)); + assert_parameters(IS_LCD_DRV(InitStruct->Drv)); + assert_parameters(IS_LCD_FRQ(InitStruct->FRQ)); + assert_parameters(IS_LCD_SWPR(InitStruct->SWPR)); + assert_parameters(IS_LCD_FBMODE(InitStruct->FBMODE)); + assert_parameters(IS_LCD_BKFILL(InitStruct->BKFILL)); + + tmp_reg1 = LCD->CTRL; + tmp_reg2 = LCD->CTRL2; + tmp_reg1 &= ~(LCD_CTRL_TYPE\ + |LCD_CTRL_DRV\ + |LCD_CTRL_FRQ); + tmp_reg1 |= (InitStruct->Type\ + |InitStruct->Drv\ + |InitStruct->FRQ); + tmp_reg2 &= ~(LCD_CTRL2_SWPR\ + |LCD_CTRL2_FBMODE\ + |LCD_CTRL2_BKFILL); + tmp_reg2 |= ((InitStruct->SWPR << 8)\ + |InitStruct->FBMODE\ + |InitStruct->BKFILL); + LCD->CTRL = tmp_reg1; + LCD->CTRL2 = tmp_reg2; +} + +/** + * @brief Fills each LCD_InitStruct member with its default value. + * @param LCD_InitStruct: pointer to an LCD_InitType structure which will be initialized. + * @retval None + */ +void LCD_StructInit(LCD_InitType *LCD_InitStruct) +{ + /*--------------- Reset LCD init structure parameters values ---------------*/ + /* Initialize the BKFILL member */ + LCD_InitStruct->BKFILL = LCD_BKFILL_0; + /* Initialize the Drv member */ + LCD_InitStruct->Drv = LCD_DRV_300; + /* Initialize the FBMODE member */ + LCD_InitStruct->FBMODE = LCD_FBMODE_BUFA; + /* Initialize the FRQ member */ + LCD_InitStruct->FRQ = LCD_FRQ_64H; + /* Initialize the SWPR member */ + LCD_InitStruct->SWPR = 0; + /* Initialize the Type member */ + LCD_InitStruct->Type = LCD_TYPE_4COM; +} + +/** + * @brief Initializes the LCD registers to their default reset values. + * @param None + * @retval None + */ +void LCD_DeInit(void) +{ + LCD->CTRL &= ~LCD_CTRL_EN; + + LCD->CTRL = LCD_CTRL_RSTValue; + LCD->CTRL2 = LCD_CTRL2_RSTValue; + LCD->SEGCTRL0 = LCD_SEGCTRL0_RSTValue; + LCD->SEGCTRL1 = LCD_SEGCTRL1_RSTValue; + LCD->SEGCTRL2 = LCD_SEGCTRL2_RSTValue; +} + +/** + * @brief LCD controller enable. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void LCD_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + LCD->CTRL |= LCD_CTRL_EN; + } + else + { + LCD->CTRL &= ~LCD_CTRL_EN; + } +} + +/** + * @brief Configure LCD COMs'/SEGs' IOs. + * @param ComMode: + LCD_COMMOD_4COM : Control the COM0~3 IO configuration + LCD_COMMOD_6COM : Control the COM0~5 IO configuration + LCD_COMMOD_8COM : Control the COM0~7 IO configuration + * @param SEGVal0 SEGVal1 SEGVal2 : Each bit control the SEGs' IO configuration + * @param NewState: + ENABLE : The corresponded IOs be set to forbidden mode(disable output/disable input), enable SEGs' output and LCD function. + DISABLE : LCD be disabled and the corresponded IOs be set to output(low) mode. + * @retval None + */ +void LCD_IOConfig(uint32_t ComMode, uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2, uint32_t NewState) +{ + uint32_t position, segcurrent; + + /* Check parameters */ + assert_parameters(IS_LCD_COMMOD(ComMode)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + /* Disable LCD */ + LCD->CTRL &= ~LCD_CTRL_EN; + + /* COMs' IO configuration : ouput low */ + *(lcd_comio[0].GPIO+2) &= ~lcd_comio[0].Pin; + *lcd_comio[0].GPIO &= ~lcd_comio[0].Pin; + *(lcd_comio[1].GPIO+2) &= ~lcd_comio[1].Pin; + *lcd_comio[1].GPIO &= ~lcd_comio[1].Pin; + *(lcd_comio[2].GPIO+2) &= ~lcd_comio[2].Pin; + *lcd_comio[2].GPIO &= ~lcd_comio[2].Pin; + *(lcd_comio[3].GPIO+2) &= ~lcd_comio[3].Pin; + *lcd_comio[3].GPIO &= ~lcd_comio[3].Pin; + if (ComMode & 2UL) + { + *(lcd_comio[4].GPIO+2) &= ~lcd_comio[4].Pin; + *lcd_comio[4].GPIO &= ~lcd_comio[4].Pin; + *(lcd_comio[5].GPIO+2) &= ~lcd_comio[5].Pin; + *lcd_comio[5].GPIO &= ~lcd_comio[5].Pin; + } + if (ComMode & 4UL) + { + *(lcd_comio[6].GPIO+2) &= ~lcd_comio[6].Pin; + *lcd_comio[6].GPIO &= ~lcd_comio[6].Pin; + *(lcd_comio[7].GPIO+2) &= ~lcd_comio[7].Pin; + *lcd_comio[7].GPIO &= ~lcd_comio[7].Pin; + } + + /* SEG0~31 IO Configuration : ouput low */ + position = 0; + while ((SEGVal0 >> position) != 0UL) + { + segcurrent = SEGVal0 & (1U << position); + if (segcurrent) + { + *(lcd_segio[position].GPIO + 2) &= ~lcd_segio[position].Pin; + *lcd_segio[position].GPIO &= ~lcd_segio[position].Pin; + } + position++; + } + /* SEG32~63 IO Configuration : ouput low */ + position = 0; + while ((SEGVal1 >> position) != 0UL) + { + segcurrent = SEGVal1 & (1U << position); + if (segcurrent) + { + *(lcd_segio[position + 32].GPIO + 2) &= ~lcd_segio[position + 32].Pin; + *lcd_segio[position + 32].GPIO &= ~lcd_segio[position + 32].Pin; + } + position++; + } + /* SEG64~79 IO Configuration : ouput low */ + position = 0; + while ((SEGVal2 >> position) != 0UL) + { + segcurrent = SEGVal2 & (1U << position); + if (segcurrent) + { + *(lcd_segio[position + 64].GPIO + 2) &= ~lcd_segio[position + 64].Pin; + *lcd_segio[position + 64].GPIO &= ~lcd_segio[position + 64].Pin; + } + position++; + } + } + else + { + /* COMs' IO configuration : forbidden */ + *lcd_comio[0].GPIO |= lcd_comio[0].Pin; + *(lcd_comio[0].GPIO+1) &= ~lcd_comio[0].Pin; + *lcd_comio[1].GPIO |= lcd_comio[1].Pin; + *(lcd_comio[1].GPIO+1) &= ~lcd_comio[1].Pin; + *lcd_comio[2].GPIO |= lcd_comio[2].Pin; + *(lcd_comio[2].GPIO+1) &= ~lcd_comio[2].Pin; + *lcd_comio[3].GPIO |= lcd_comio[3].Pin; + *(lcd_comio[3].GPIO+1) &= ~lcd_comio[3].Pin; + if (ComMode & 2UL) + { + *lcd_comio[4].GPIO |= lcd_comio[4].Pin; + *(lcd_comio[4].GPIO+1) &= ~lcd_comio[4].Pin; + *lcd_comio[5].GPIO |= lcd_comio[5].Pin; + *(lcd_comio[5].GPIO+1) &= ~lcd_comio[5].Pin; + } + if (ComMode & 4UL) + { + *lcd_comio[6].GPIO |= lcd_comio[6].Pin; + *(lcd_comio[6].GPIO+1) &= ~lcd_comio[6].Pin; + *lcd_comio[7].GPIO |= lcd_comio[7].Pin; + *(lcd_comio[7].GPIO+1) &= ~lcd_comio[7].Pin; + } + + /* SEG0~31 IO Configuration */ + position = 0; + while ((SEGVal0 >> position) != 0UL) + { + segcurrent = SEGVal0 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position].GPIO |= lcd_segio[position].Pin; + /* Disable input */ + *(lcd_segio[position].GPIO + 1) &= ~lcd_segio[position].Pin; + } + position++; + } + /* SEG32~63 IO Configuration */ + position = 0; + while ((SEGVal1 >> position) != 0UL) + { + segcurrent = SEGVal1 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 32].GPIO |= lcd_segio[position + 32].Pin; + /* Disable input */ + *(lcd_segio[position + 32].GPIO + 1) &= ~lcd_segio[position + 32].Pin; + } + position++; + } + /* SEG64~79 IO Configuration */ + position = 0; + while ((SEGVal2 >> position) != 0UL) + { + segcurrent = SEGVal2 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 64].GPIO |= lcd_segio[position + 64].Pin; + /* Disable input */ + *(lcd_segio[position + 64].GPIO + 1) &= ~lcd_segio[position + 64].Pin; + } + position++; + } + + /* Enable SEGs' function of IOs */ + LCD->SEGCTRL0 = SEGVal0; + LCD->SEGCTRL1 = SEGVal1; + LCD->SEGCTRL2 = SEGVal2 & 0xFFFE; + + /* Enable LCD */ + LCD->CTRL |= LCD_CTRL_EN; + } +} + +/** + * @brief LCD SEGx enable. + * @param SEGVal0 SEGVal1 SEGVal2 + * @retval None + */ +void LCD_SetSEG(uint32_t SEGVal0, uint32_t SEGVal1, uint16_t SEGVal2) +{ + uint32_t position; + uint32_t segcurrent; + + /* SEG0~31 IO Configuration */ + position = 0; + while ((SEGVal0 >> position) != 0UL) + { + segcurrent = SEGVal0 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position].GPIO |= lcd_segio[position].Pin; + /* Disable input */ + *(lcd_segio[position].GPIO + 1) &= ~lcd_segio[position].Pin; + } + position++; + } + /* SEG32~63 IO Configuration */ + position = 0; + while ((SEGVal1 >> position) != 0UL) + { + segcurrent = SEGVal1 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 32].GPIO |= lcd_segio[position + 32].Pin; + /* Disable input */ + *(lcd_segio[position + 32].GPIO + 1) &= ~lcd_segio[position + 32].Pin; + } + position++; + } + /* SEG64~79 IO Configuration */ + position = 0; + while ((SEGVal2 >> position) != 0UL) + { + segcurrent = SEGVal2 & (1U << position); + if (segcurrent) + { + /* Disable output */ + *lcd_segio[position + 64].GPIO |= lcd_segio[position + 64].Pin; + /* Disable input */ + *(lcd_segio[position + 64].GPIO + 1) &= ~lcd_segio[position + 64].Pin; + } + position++; + } + + LCD->SEGCTRL0 = SEGVal0; + LCD->SEGCTRL1 = SEGVal1; + LCD->SEGCTRL2 = SEGVal2 & 0xFFFE; +} + +/** + * @brief LCD BIAS mode configure. + * @param BiasSelection: + LCD_BMODE_DIV3 + LCD_BMODE_DIV4 + * @retval None + */ +void LCD_BiasModeConfig(uint32_t BiasSelection) +{ + uint32_t tmp; + + assert_parameters(IS_LCD_BMODE(BiasSelection)); + + tmp = ANA->REG6; + tmp &= ~ANA_REG6_LCD_BMODE; + tmp |= BiasSelection; + ANA->REG6 = tmp; +} + +/** + * @brief LCD driving voltage configure. + * @note The LCD driving voltage's configuration in NVR will be load to register + * (ANA_REG6[4:1]) in startup_target.s file. + * ex: + * The VLCD information in NVR[0x40D94] 10<<1(-300mV) + * 1. When LCD_VLCD_DEC60MV is selected + * 11<<1(-360mV) will be configured to ANA_REG6[4:1], return 0 + * 2. When LCD_VLCD_DEC360MV is selected(out of range) + * 15<<1(-600mV) will be configured to ANA_REG6[4:1], return 2 + * @param VLCDSelection: + LCD_VLCD_0 + LCD_VLCD_INC60MV + LCD_VLCD_INC120MV + LCD_VLCD_INC180MV + LCD_VLCD_INC240MV + LCD_VLCD_INC300MV + LCD_VLCD_DEC60MV + LCD_VLCD_DEC120MV + LCD_VLCD_DEC180MV + LCD_VLCD_DEC240MV + LCD_VLCD_DEC300MV + LCD_VLCD_DEC360MV + LCD_VLCD_DEC420MV + LCD_VLCD_DEC480MV + LCD_VLCD_DEC540MV + LCD_VLCD_DEC600MV + * @retval 0 Function successed. + 1 NVR LCD information checksum error. + 2 LCD driving voltage's configuration out of range. + */ +uint32_t LCD_VoltageConfig(uint32_t VLCDSelection) +{ + uint32_t lcd_vol; + uint32_t lcd_vol_tmp; + uint32_t tmp; + NVR_LCDINFO LCD_InfoStruct; + + assert_parameters(IS_LCD_VLCD(VLCDSelection)); + + /* Get NVR LCD information */ + if (NVR_GetLCDInfo(&LCD_InfoStruct)) + return (1); + else + lcd_vol_tmp = LCD_InfoStruct.MEALCDVol; + + tmp = ANA->REG6; + tmp &= ~ANA_REG6_VLCD; + lcd_vol = lcd_vol_tmp<0x5U) + { + tmp |= LCD_VLCD_INC300MV << ANA_REG6_VLCD_Pos; + ANA->REG6 = tmp; + return (2); + } + else + { + tmp |= (lcd_vol + (VLCDSelection << ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + } + /*Adjust voltage is negtive*/ + else if ( (lcd_vol_tmp > 0x5U) && (VLCDSelection > 0x5U) ) + { + /*Adjust voltage is out of range(-600mv)*/ + if ((lcd_vol_tmp + VLCDSelection - 5)>0xFU) + { + tmp |= LCD_VLCD_DEC600MV << ANA_REG6_VLCD_Pos; + ANA->REG6 = tmp; + return (2); + } + else + { + tmp |= (lcd_vol + ((VLCDSelection -0x5)<< ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + } + else if ( (lcd_vol_tmp > 0x5U) && (VLCDSelection <= 0x5U) ) + { + /*Adjust voltage is postive or 0*/ + if ((lcd_vol_tmp - 5) <= VLCDSelection) + { + tmp |= (((VLCDSelection + 0x5) << ANA_REG6_VLCD_Pos) - lcd_vol); + ANA->REG6 = tmp; + return (0); + } + /*Adjust voltage is negtive*/ + else + { + tmp |= (lcd_vol - ((VLCDSelection) << ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + } + else + { + /*Adjust voltage is postive or 0*/ + if ((VLCDSelection - 5) <= lcd_vol_tmp) + { + tmp |= (lcd_vol - ((VLCDSelection - 0x5) << ANA_REG6_VLCD_Pos)); + ANA->REG6 = tmp; + return (0); + } + /*Adjust voltage is negtive*/ + else + { + tmp |= ((VLCDSelection << ANA_REG6_VLCD_Pos) - lcd_vol); + ANA->REG6 = tmp; + return (0); + } + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_misc.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_misc.c new file mode 100644 index 0000000000..fba3361c88 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_misc.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file lib_misc.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief MISC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_misc.h" + +/** + * @brief Get flag status. + * @param FlagMask: + MISC_FLAG_LOCKUP + MISC_FLAG_PIAC + MISC_FLAG_HIAC + MISC_FLAG_PERR + * @retval Flag status. + */ +uint8_t MISC_GetFlag(uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_MISC_FLAGR(FlagMask)); + + if (MISC->SRAMINT&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear flag status. + * @param FlagMask: can use the ¡®|¡¯ operator + MISC_FLAG_LOCKUP + MISC_FLAG_PIAC + MISC_FLAG_HIAC + MISC_FLAG_PERR + * @retval None + */ +void MISC_ClearFlag(uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_MISC_FLAGC(FlagMask)); + + MISC->SRAMINT = FlagMask; +} + +/** + * @brief Interrupt configure. + * @param INTMask: can use the ¡®|¡¯ operator + MISC_INT_LOCK + MISC_INT_PIAC + MISC_INT_HIAC + MISC_INT_PERR + NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_MISC_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = MISC->SRAMINIT; + if (NewState == ENABLE) + { + tmp |= INTMask; + } + else + { + tmp &= ~INTMask; + } + MISC->SRAMINIT = tmp; +} + +/** + * @brief sram parity contrl. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_SRAMParityCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC->SRAMINIT |= MISC_SRAMINIT_PEN; + } + else + { + MISC->SRAMINIT &= ~MISC_SRAMINIT_PEN; + } +} + +/** + * @brief Get sram parity error address. + * @param None + * @retval parity error address. + */ +uint32_t MISC_GetSRAMPEAddr(void) +{ + uint32_t tmp; + + tmp = MISC->PARERR; + tmp = tmp*4 + 0x20000000; + return tmp; +} + +/** + * @brief Get APB error address. + * @param None + * @retval APB error address. + */ +uint32_t MISC_GetAPBErrAddr(void) +{ + uint32_t tmp; + + tmp = MISC->PIADDR; + tmp = tmp + 0x40010000; + return tmp; +} + +/** + * @brief Get AHB error address. + * @param None + * @retval AHB error address. + */ +uint32_t MISC_GetAHBErrAddr(void) +{ + uint32_t tmp; + + tmp = MISC->HIADDR; + tmp = tmp + 0x40000000; + return tmp; +} + +/** + * @brief IR control. + * @param IRx: + MISC_IREN_TX0 + MISC_IREN_TX1 + MISC_IREN_TX2 + MISC_IREN_TX3 + MISC_IREN_TX4 + MISC_IREN_TX5 + NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_IRCmd(uint32_t IRx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + assert_parameters(IS_MISC_IREN(IRx)); + + tmp = MISC->IREN; + if (NewState == ENABLE) + { + tmp |= IRx; + } + else + { + tmp &= ~IRx; + } + MISC->IREN = tmp; +} + +/** + * @brief IR duty configure. + * @param DutyHigh + The high pulse width will be (DUTYH + 1)*APBCLK period. + DutyLow + The low pulse width will be (DUTYL + 1)*APBCLK period. + * @retval None + */ +void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow) +{ + MISC->DUTYH = DutyHigh; + MISC->DUTYL = DutyLow; +} + +/** + * @brief Hardfault generation configure. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_HardFaultCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC->IRQLAT &= ~MISC_IRQLAT_NOHARDFAULT; + } + else + { + MISC->IRQLAT |= MISC_IRQLAT_NOHARDFAULT; + } +} + +/** + * @brief Control if the lockup will issue a system reset. + * @param NewState: + ENABLE + DISABLE + * @retval None + */ +void MISC_LockResetCmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + MISC->IRQLAT |= MISC_IRQLAT_LOCKRESET; + } + else + { + MISC->IRQLAT &= ~MISC_IRQLAT_LOCKRESET; + } +} + +/** + * @brief IRQLAT configure. + * @param Latency:0~255 + * @retval None + */ +void MISC_IRQLATConfig(uint8_t Latency) +{ + uint32_t tmp; + + tmp = MISC->IRQLAT; + tmp &= ~MISC_IRQLAT_IRQLAT; + tmp |= Latency; + MISC->IRQLAT = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pmu.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pmu.c new file mode 100644 index 0000000000..f86b4e325f --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pmu.c @@ -0,0 +1,1158 @@ +/** + ****************************************************************************** + * @file lib_pmu.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PMU library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_pmu.h" +#include "lib_gpio.h" +#include "lib_CodeRAM.h" +#include "lib_clk.h" +#include "lib_cortex.h" + +#define DSLEEPPASS_KEY 0xAA5555AA +#define DSLEEPEN_KEY 0x55AAAA55 + +extern __IO uint32_t ana_reg3_tmp; + +/** + * @brief Enter Deep sleep mode. + * @param None + * @retval 1: Current mode is debug mode, function failed. + * 2: Enter deep-sleep mode failed. + */ +uint32_t PMU_EnterDSleepMode(void) +{ + uint32_t hclk; + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Enter deep sleep when WKU event is cleared */ + while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU) + { + } + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + + PMU->DSLEEPPASS = DSLEEPPASS_KEY; + PMU->DSLEEPEN = DSLEEPEN_KEY; + + return 2; +} + +/** + * @brief Enter idel mode. + * @note Any interrupt generate to CPU will break idle mode. + * @param None + * @retval None + */ +void PMU_EnterIdleMode(void) +{ + /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + __WFI(); +} + +/** + * @brief Enter sleep mode. + * @param None + * @retval 1: Current mode is debug mode, function failed. + * 0: Quit deep-sleep mode ucceeded. + */ +uint32_t PMU_EnterSleepMode(void) +{ + uint32_t hclk; + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + __WFI(); + + return 0; +} + +/** + * @brief PMU interrupt configuration. + * @param INTMask:(between PMU_INT_IOAEN,PMU_INT_32K and PMU_INT_6M, can use the | operator) + PMU_INT_IOAEN + PMU_INT_32K + PMU_INT_6M + NewState: + ENABLE + DISABLE + * @retval None + */ +void PMU_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + PMU->CONTROL |= INTMask; + } + else + { + PMU->CONTROL &= ~INTMask; + } +} + +/** + * @brief Get interrupt status. + * @param INTMask: + PMU_INTSTS_32K + PMU_INTSTS_6M + PMU_INTSTS_EXTRST + PMU_INTSTS_PORST + PMU_INTSTS_DPORST + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INTFLAGR(INTMask)); + + if (PMU->STS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param INTMask:specifies the flag to clear. + This parameter can be any combination of the following values + PMU_INTSTS_32K + PMU_INTSTS_6M + PMU_INTSTS_EXTRST + PMU_INTSTS_PORST + PMU_INTSTS_DPORST + * @retval None + */ +void PMU_ClearINTStatus(uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_INTFLAGC(INTMask)); + + PMU->STS = INTMask; +} + +/** + * @brief Get status. + * @param Mask: + PMU_STS_32K + PMU_STS_6M + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetStatus(uint32_t Mask) +{ + /* Check parameters */ + assert_parameters(IS_PMU_FLAG(Mask)); + + if (PMU->STS&Mask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Get all IOA interrupt status. + * @param None + * @retval IOA's interrupt status + */ +uint16_t PMU_GetIOAAllINTStatus(void) +{ + return (PMU->IOAINTSTS); +} + +/** + * @brief Get IOA interrupt status. + * @param INTMask: + GPIO_Pin_0 ~ GPIO_Pin_15 + * @retval 1:status set + 0:status reset + */ +uint16_t PMU_GetIOAINTStatus(uint16_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(INTMask)); + + if (PMU->IOAINTSTS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear IOA interrupt status. + * @param INTMask: + This parameter can be any combination of the following values + GPIO_Pin_0 ~ GPIO_Pin_15 + * @retval None + */ +void PMU_ClearIOAINTStatus(uint16_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PIN(INTMask)); + + PMU->IOAINTSTS = INTMask; +} + +/** + * @brief Wake-up sources pin configuration. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + * @retval None + */ +void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event) +{ + uint32_t tmp; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + while ((IOAx >> position) != 0U) + { + /* Get current io position */ + iocurrent = IOAx & (0x01U << position); + + if (iocurrent) + { + /* Current IO Input configure*/ + GPIOA->OEN |= iocurrent; + GPIOA->IE |= iocurrent; + + tmp = PMU->IOAWKUEN; + tmp &= ~(3U << (2 * position)); + switch (Wakeup_Event) + { + /* Disable wake-up function */ + default: + case IOA_DISABLE: + break; + + /* wake-up function: Rising */ + case IOA_RISING: + GPIOA->DAT &= ~iocurrent; + tmp |= 1 << (2 * position); + break; + + /* wake-up function: falling */ + case IOA_FALLING: + GPIOA->DAT |= iocurrent; + tmp |= 1 << (2 * position); + break; + + /* wake-up function: high level */ + case IOA_HIGH: + GPIOA->DAT &= ~iocurrent; + tmp |= 2 << (2 * position); + break; + + /* wake-up function: low level */ + case IOA_LOW: + GPIOA->DAT |= iocurrent; + tmp |= 2 << (2 * position); + break; + + /* wake-up function: boht edge */ + case IOA_EDGEBOTH: + tmp |= 3 << (2 * position); + break; + } + PMU->IOAWKUEN = tmp; + } + position++; + } +} + +/** + * @brief Control low-power configuration, enter deep-sleep mode. + * + * @param InitStruct : pointer to PMU_LowPWRTypeDef + COMP1Power: + PMU_COMP1PWR_ON + PMU_COMP1PWR_OFF + COMP2Power: + PMU_COMP2PWR_ON + PMU_COMP2PWR_OFF + TADCPower: + PMU_TADCPWR_ON + PMU_TADCPWR_OFF + BGPPower: + PMU_BGPPWR_ON + PMU_BGPPWR_OFF + AVCCPower: + PMU_AVCCPWR_ON + PMU_AVCCPWR_OFF + LCDPower: + PMU_LCDPWER_ON + PMU_LCDPWER_OFF + VDCINDetector: + PMU_VDCINDET_ENABLE + PMU_VDCINDET_DISABLE + VDDDetector: + PMU_VDDDET_ENABLE + PMU_VDDDET_DISABLE + APBPeriphralDisable: + PMU_APB_ALL + PMU_APB_DMA + PMU_APB_I2C + PMU_APB_SPI1 + PMU_APB_SPI2 + PMU_APB_UART0 + PMU_APB_UART1 + PMU_APB_UART2 + PMU_APB_UART3 + PMU_APB_UART4 + PMU_APB_UART5 + PMU_APB_ISO78160 + PMU_APB_ISO78161 + PMU_APB_TIMER + PMU_APB_MISC + PMU_APB_U32K0 + PMU_APB_U32K1 + AHBPeriphralDisable: + PMU_AHB_ALL + PMU_AHB_DMA + PMU_AHB_GPIO + PMU_AHB_LCD + PMU_AHB_CRYPT + + * @note This function performs the following: + Comparator 1 power control ON or OFF(optional) + Comparator 2 power control ON or OFF(optional) + Tiny ADC power control ON or OFF(optional) + Bandgap power control ON or OFF(optional) + AVCC power control ON or OFF(optional) + LCD controller power control ON or OFF(optional) + VDCIN detector control Disable or Enable(optional) + VDD detector control Disable or Enable(optional) + Disable AHB/APB periphral clock Modules(optional) + Disable AVCC output + Power down ADC, Power down Temp sensor + Disable resistance/capacitance division for ADC input signal + + * @retval 1: Current MODE is debug mode, enter deep-sleep mode failed. + 2: VDCIN is not drop before enter deep-sleep mode or Failure to enter deep sleep mode. + */ +uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct) +{ + uint32_t tmp; + uint32_t hclk; + + /* Check parameters */ + assert_parameters(IS_PMU_COMP1PWR(InitStruct->COMP1Power)); + assert_parameters(IS_PMU_COMP2PWR(InitStruct->COMP2Power)); + assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower)); + assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower)); + assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower)); + assert_parameters(IS_PMU_LCDPWER(InitStruct->LCDPower)); + assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector)); + assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector)); + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Disable AVCC output */ + ANA->REGF &= ~ANA_REGF_AVCCO_EN; + /* Power down ADC */ + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + /* Power down Temp sensor */ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL &= ~(ANA_ADCCTRL_MCH | ANA_ADCCTRL_ACH); + /* Disable resistor/cap division for ADC input signal */ + ANA->REG1 &= ~(ANA_REG1_RESDIV | ANA_REG1_GDE4); + + /******** Comparator 1 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP1PDN; + ana_reg3_tmp |= InitStruct->COMP1Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Comparator 2 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP2PDN; + ana_reg3_tmp |= InitStruct->COMP2Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Tiny ADC power control ********/ + tmp = ANA->REGF; + tmp &= ~ANA_REGF_PDNADT; + tmp |= InitStruct->TADCPower; + ANA->REGF = tmp; + + /******** BGP power control ********/ + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + ana_reg3_tmp |= InitStruct->BGPPower; + ANA->REG3 = ana_reg3_tmp; + + /******** AVCC power control ********/ + tmp = ANA->REG8; + tmp &= ~ANA_REG8_PD_AVCCLDO; + tmp |= InitStruct->AVCCPower; + ANA->REG8 = tmp; + + /******** LCD controller power control ********/ + tmp = LCD->CTRL; + tmp &= ~LCD_CTRL_EN; + tmp |= InitStruct->LCDPower; + LCD->CTRL = tmp; + /* LCD power off, disable all SEG */ + if (InitStruct->LCDPower == PMU_LCDPWER_OFF) + { + LCD->SEGCTRL0 = 0; + LCD->SEGCTRL1 = 0; + LCD->SEGCTRL2 = 0; + } + + /******** VDCIN detector control ********/ + tmp = ANA->REGA; + tmp &= ~ANA_REGA_PD_VDCINDET; + tmp |= InitStruct->VDCINDetector; + ANA->REGA = tmp; + + /******** VDD detector control *********/ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PDDET; + tmp |= InitStruct->VDDDetector; + ANA->REG9 = tmp; + + /******** AHB Periphral clock disable selection ********/ + tmp = MISC2->HCLKEN; + tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL); + MISC2->HCLKEN = tmp; + + /******** APB Periphral clock disable selection ********/ + tmp = MISC2->PCLKEN; + tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL); + MISC2->PCLKEN = tmp; + + if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE) + { + if (!(ANA->COMPOUT & ANA_COMPOUT_VDCINDROP)) + { + return 2; + } + } + // make sure WKU is 0 before entering deep-sleep mode + while (PMU->DSLEEPEN & PMU_DSLEEPEN_WKU); + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + /* Enter deep-sleep mode */ + PMU->DSLEEPPASS = DSLEEPPASS_KEY; + PMU->DSLEEPEN = DSLEEPEN_KEY; + + return 2; +} + +/** + * @brief Control low-power configuration, enter sleep mode. + * + * @param InitStruct : pointer to PMU_LowPWRTypeDef + COMP1Power: + PMU_COMP1PWR_ON + PMU_COMP1PWR_OFF + COMP2Power: + PMU_COMP2PWR_ON + PMU_COMP2PWR_OFF + TADCPower: + PMU_TADCPWR_ON + PMU_TADCPWR_OFF + BGPPower: + PMU_BGPPWR_ON + PMU_BGPPWR_OFF + AVCCPower: + PMU_AVCCPWR_ON + PMU_AVCCPWR_OFF + LCDPower: + PMU_LCDPWER_ON + PMU_LCDPWER_OFF + VDCINDetector: + PMU_VDCINDET_ENABLE + PMU_VDCINDET_DISABLE + VDDDetector: + PMU_VDDDET_ENABLE + PMU_VDDDET_DISABLE + APBPeriphralDisable: + PMU_APB_ALL + PMU_APB_DMA + PMU_APB_I2C + PMU_APB_SPI1 + PMU_APB_SPI2 + PMU_APB_UART0 + PMU_APB_UART1 + PMU_APB_UART2 + PMU_APB_UART3 + PMU_APB_UART4 + PMU_APB_UART5 + PMU_APB_ISO78160 + PMU_APB_ISO78161 + PMU_APB_TIMER + PMU_APB_MISC + PMU_APB_U32K0 + PMU_APB_U32K1 + AHBPeriphralDisable: + PMU_AHB_ALL + PMU_AHB_DMA + PMU_AHB_GPIO + PMU_AHB_LCD + PMU_AHB_CRYPT + + * @note This function performs the following: + Comparator 1 power control ON or OFF(optional) + Comparator 2 power control ON or OFF(optional) + Tiny ADC power control ON or OFF(optional) + Bandgap power control ON or OFF(optional) + AVCC power control ON or OFF(optional) + LCD controller power control ON or OFF(optional) + VDCIN detector control Disable or Enable(optional) + VDD detector control Disable or Enable(optional) + Disable AHB/APB periphral clock Modules(optional) + Disable AVCC output + Power down ADC, Power down Temp sensor + Disable resistance/capacitance division for ADC input signal + + * @retval 2: VDCIN is not drop before enter sleep mode(failed). + 1: Current mode is debug mode, enter sleep mode failed. + 0: Quit from sleep mode success. +*/ +uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct) +{ + uint32_t tmp; + uint32_t hclk; + + /* Check parameters */ + assert_parameters(IS_PMU_COMP1PWR(InitStruct->COMP1Power)); + assert_parameters(IS_PMU_COMP2PWR(InitStruct->COMP2Power)); + assert_parameters(IS_PMU_TADCPWR(InitStruct->TADCPower)); + assert_parameters(IS_PMU_BGPPWR(InitStruct->BGPPower)); + assert_parameters(IS_PMU_AVCCPWR(InitStruct->AVCCPower)); + assert_parameters(IS_PMU_LCDPWER(InitStruct->LCDPower)); + assert_parameters(IS_PMU_VDCINDET(InitStruct->VDCINDetector)); + assert_parameters(IS_PMU_VDDDET(InitStruct->VDDDetector)); + + /* Current MODE is 0, debug mode, return error */ + if (!(PMU->STS & PMU_STS_MODE)) + return 1; + + /* Disable AVCC output */ + ANA->REGF &= ~ANA_REGF_AVCCO_EN; + /* Power down ADC */ + ana_reg3_tmp &= ~ANA_REG3_ADCPDN; + ANA->REG3 = ana_reg3_tmp; + /* Power down Temp sensor */ + while (ANA->ADCCTRL & ANA_ADCCTRL_MTRIG); + ANA->ADCCTRL &= ~(ANA_ADCCTRL_MCH | ANA_ADCCTRL_ACH); + /* Disable resistor/cap division for ADC input signal */ + ANA->REG1 &= ~(ANA_REG1_RESDIV | ANA_REG1_GDE4); + + /******** Comparator 1 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP1PDN; + ana_reg3_tmp |= InitStruct->COMP1Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Comparator 2 power control ********/ + ana_reg3_tmp &= ~ANA_REG3_CMP2PDN; + ana_reg3_tmp |= InitStruct->COMP2Power; + ANA->REG3 = ana_reg3_tmp; + + /******** Tiny ADC power control ********/ + tmp = ANA->REGF; + tmp &= ~ANA_REGF_PDNADT; + tmp |= InitStruct->TADCPower; + ANA->REGF = tmp; + + /******** BGP power control ********/ + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + ana_reg3_tmp |= InitStruct->BGPPower; + ANA->REG3 = ana_reg3_tmp; + + /******** AVCC power control ********/ + tmp = ANA->REG8; + tmp &= ~ANA_REG8_PD_AVCCLDO; + tmp |= InitStruct->AVCCPower; + ANA->REG8 = tmp; + + /******** LCD controller power control ********/ + tmp = LCD->CTRL; + tmp &= ~LCD_CTRL_EN; + tmp |= InitStruct->LCDPower; + LCD->CTRL = tmp; + /* LCD power off, disable all SEG */ + if (InitStruct->LCDPower == PMU_LCDPWER_OFF) + { + LCD->SEGCTRL0 = 0; + LCD->SEGCTRL1 = 0; + LCD->SEGCTRL2 = 0; + } + + /******** VDCIN detector control ********/ + tmp = ANA->REGA; + tmp &= ~ANA_REGA_PD_VDCINDET; + tmp |= InitStruct->VDCINDetector; + ANA->REGA = tmp; + + /******** VDD detector control *********/ + tmp = ANA->REG9; + tmp &= ~ANA_REG9_PDDET; + tmp |= InitStruct->VDDDetector; + ANA->REG9 = tmp; + + /******** AHB Periphral clock disable selection ********/ + tmp = MISC2->HCLKEN; + tmp &= ~((InitStruct->AHBPeriphralDisable) & PMU_AHB_ALL); + MISC2->HCLKEN = tmp; + + /******** APB Periphral clock disable selection ********/ + tmp = MISC2->PCLKEN; + tmp &= ~((InitStruct->APBPeriphralDisable) & PMU_APB_ALL); + MISC2->PCLKEN = tmp; + + if ((InitStruct->VDCINDetector) != PMU_VDCINDET_DISABLE) + { + if (!(ANA->COMPOUT & ANA_COMPOUT_VDCINDROP)) + { + return 2; + } + } + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + ANA->REG7 &= ~BIT5; + ANA->REGA |= BIT3 | BIT1; + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + + return 0; +} + + +/** + * @brief Flash deep standby, enter idle mode. + * @param None + * @retval None + */ +#ifndef __GNUC__ +void PMU_EnterIdle_LowPower(void) +{ + uint32_t hclk; + + /* Flash 1USCYCLE configure */ + hclk = CLK_GetHCLKFreq(); + if(hclk > 1000000) + { + MISC2->FLASHWC = (hclk/1000000)<<8; + } + else + { + MISC2->FLASHWC = 0<<8; + } + + PMU_EnterIdle_FlashDSTB(); +} +#endif + +/** + * @brief IOA wake-up source configure about Sleep mode. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + Priority: The preemption priority for the IRQn channel. + This parameter can be a value between 0 and 3. + * @retval + */ +void PMU_SleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + /* Disable PMU interrupt in NVIC */ + NVIC_DisableIRQ(PMU_IRQn); + /* Wake-up pins configuration */ + PMU_WakeUpPinConfig(IOAx, Wakeup_Event); + /* Clear interrupt flag */ + PMU->IOAINTSTS = IOAx; + /* Enable PMU interrupt */ + PMU->CONTROL |= PMU_CONTROL_INT_IOA_EN; + CORTEX_SetPriority_ClearPending_EnableIRQ(PMU_IRQn, Priority); +} + +/** + * @brief RTC wake-up source configure about Sleep mode. + * @param Wakeup_Event: + This parameter can be any combination of the following values + PMU_RTCEVT_ACDONE + PMU_RTCEVT_WKUCNT + PMU_RTCEVT_MIDNIGHT + PMU_RTCEVT_WKUHOUR + PMU_RTCEVT_WKUMIN + PMU_RTCEVT_WKUSEC + PMU_RTCEVT_TIMEILLE + Priority: The preemption priority for the IRQn channel. + This parameter can be a value between 0 and 3. + * @retval + */ +void PMU_SleepWKUSRC_Config_RTC(uint32_t Wakeup_Event, uint32_t Priority) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RTCEVT(Wakeup_Event)); + + /* Disable RTC interrupt in NVIC */ + NVIC_DisableIRQ(RTC_IRQn); + /* Clear interrupt flag */ + RTC->INTSTS = Wakeup_Event; + /* Enable RTC interrupt */ + RTC->INTEN |= Wakeup_Event & (~0x01UL); + CORTEX_SetPriority_ClearPending_EnableIRQ(RTC_IRQn, Priority); +} +/** + * @brief IOA wake-up source configure about Deep-Sleep mode. + * @param IOAx: GPIO_Pin_0 ~ GPIO_Pin_15 + Wakeup_Event: + IOA_DISABLE + IOA_RISING + IOA_FALLING + IOA_HIGH + IOA_LOW + IOA_EDGEBOTH + * @retval + */ +void PMU_DeepSleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event) +{ + /* Check parameters */ + assert_parameters(IS_GPIO_PINR(IOAx)); + assert_parameters(IS_PMU_WAKEUP(Wakeup_Event)); + + /* Wake-up pins configuration */ + PMU_WakeUpPinConfig(IOAx, Wakeup_Event); + /* Clear interrupt flag */ + PMU->IOAINTSTS = IOAx; +} + +/** + * @brief RTC wake-up source configure about Deep-Sleep mode. + * @param Wakeup_Event: + This parameter can be any combination of the following values + PMU_RTCEVT_ACDONE + PMU_RTCEVT_WKUCNT + PMU_RTCEVT_MIDNIGHT + PMU_RTCEVT_WKUHOUR + PMU_RTCEVT_WKUMIN + PMU_RTCEVT_WKUSEC + PMU_RTCEVT_TIMEILLE + * @retval + */ +void PMU_DeepSleepWKUSRC_Config_RTC(uint32_t Wakeup_Event) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RTCEVT(Wakeup_Event)); + + /* Clear interrupt flag */ + RTC->INTSTS = Wakeup_Event; + /* Enable RTC interrupt */ + RTC->INTEN |= Wakeup_Event & (~0x01UL); +} + +/** + * @brief Set the deep sleep behavior when VDD/VDCIN is not drop. + * @param VDCIN_PDNS: + PMU_VDCINPDNS_0 , can't enter deep-sleep mode when VDCIN is not drop + can wake-up mcu from deep-sleep, when VDCIN is not drop. + PMU_VDCINPDNS_1 , The condition for entering deep sleep mode is independent of VDCIN. + VDD_PDNS: + PMU_VDDPDNS_0 , can't enter deep-sleep mode when VDD is not drop(>Threshold) + can wake-up mcu from deep-sleep, when VDD is not drop. + PMU_VDDPDNS_1 , The condition for entering deep sleep mode is independent of VDD. + * @retval None + */ +void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_VDCINPDNS(VDCIN_PDNS)); + assert_parameters(IS_PMU_VDDPDNS(VDD_PDNS)); + + tmp = ANA->CTRL; + tmp &= ~(ANA_CTRL_PDNS | ANA_CTRL_PDNS2); + tmp |= (VDCIN_PDNS | VDD_PDNS); + + ANA->CTRL = tmp; +} + +/** + * @brief BGP power control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_BGP_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ana_reg3_tmp &= ~ANA_REG3_BGPPD; + else + ana_reg3_tmp |= ANA_REG3_BGPPD; + ANA->REG3 = ana_reg3_tmp; +} + +/** + * @brief Configure VDD alarm threshold voltage. + * @param PowerThreshold: + * PMU_PWTH_4_5 + * PMU_PWTH_4_2 + * PMU_PWTH_3_9 + * PMU_PWTH_3_6 + * PMU_PWTH_3_2 + * PMU_PWTH_2_9 + * PMU_PWTH_2_6 + * PMU_PWTH_2_3 + * @retval None + */ +void PMU_VDDAlarmTHConfig(uint32_t PowerThreshold) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_PWTH(PowerThreshold)); + + tmp = ANA->REG8; + tmp &= ~ANA_REG8_VDDPVDSEL; + tmp |= PowerThreshold; + + ANA->REG8 = tmp; +} + +/** + * @brief Get POWALARM status. + * @param None + * @retval POWALARM status + * 0: Voltage of VDD is higher than threshold. + * 1: Voltage of VDD is lower than threshold. + */ +uint8_t PMU_GetVDDALARMStatus(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_VDDALARM) + return 1; + else + return 0; +} + +/** + * @brief VDD detector enable control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_VDDDetectorCmd(uint32_t NewState) +{ + /* Check parameter */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG9 &= ~ANA_REG9_PDDET; + else + ANA->REG9 |= ANA_REG9_PDDET; +} + +/** + * @brief Gets current MODE pin status. + * @param None + * @retval MODE pin status + * 0: Debug mode. + * 1: Normal mode. + */ +uint8_t PMU_GetModeStatus(void) +{ + if(PMU->STS & PMU_STS_MODE) + return 1; + else + return 0; +} + +/** + * @brief Control AVCC enable. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_AVCC_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG8 &= ~ANA_REG8_PD_AVCCLDO; + else + ANA->REG8 |= ANA_REG8_PD_AVCCLDO; +} + +/** + * @brief Control VDD33_O pin power. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_AVCCOutput_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + ANA->REGF &= ~ANA_REGF_AVCCO_EN; + else + ANA->REGF |= ANA_REGF_AVCCO_EN; +} + +/** + * @brief AVCC Low Voltage detector power control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_AVCCLVDetector_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG5 &= ~ANA_REG5_PD_AVCCDET; + else + ANA->REG5 |= ANA_REG5_PD_AVCCDET; +} + +/** + * @brief Get AVCC low power status. + * @param None + * @retval low power status of AVCC + * 0: status not set, AVCC is higher than 2.5V. + * 1: status set, AVCC is lower than 2.5V. + */ +uint8_t PMU_GetAVCCLVStatus(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_AVCCLV) + return 1; + else + return 0; +} + +/** + * @brief Control VDCIN decector enable. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_VDCINDetector_Cmd(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REGA &= ~ANA_REGA_PD_VDCINDET; + else + ANA->REGA |= ANA_REGA_PD_VDCINDET; +} + +/** + * @brief Get VDCIN drop status. + * @param None + * @retval drop status of VDCIN + * 0: status not set, VDCIN is not drop. + * 1: status set, VDCIN is drop. + */ +uint8_t PMU_GetVDCINDropStatus(void) +{ + if (ANA->COMPOUT & ANA_COMPOUT_VDCINDROP) + return 1; + else + return 0; +} + +/** + * @brief Discharge the BAT battery. + * @param BATDisc: + * PMU_BATRTC_DISC + * NewState: + * ENABLE + * DISABLE + * @retval None + */ +void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_PMU_BATRTCDISC(BATDisc)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + ANA->REG6 |= BATDisc; + else + ANA->REG6 &= ~BATDisc; +} + +/** + * @brief Power drop de-bounce control. + * @param Debounce: + * PMU_PWRDROP_DEB_0 + * PMU_PWRDROP_DEB_1 + * PMU_PWRDROP_DEB_2 + * PMU_PWRDROP_DEB_3 + * @retval None + */ +void PMU_PWRDropDEBConfig(uint32_t Debounce) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PMU_PWRDROP_DEB(Debounce)); + + tmp = ANA->CTRL; + tmp &= ~ANA_CTRL_PWRDROPDEB; + tmp |= Debounce; + + ANA->CTRL = tmp; +} + +/** + * @brief Get last reset source. + * @param RSTSource: + PMU_RSTSRC_EXTRST + PMU_RSTSRC_PORST + PMU_RSTSRC_DPORST + * @retval 1:status set + 0:status reset + */ +uint8_t PMU_GetRSTSource(uint32_t RSTSource) +{ + /* Check parameters */ + assert_parameters(IS_PMU_RSTSRC(RSTSource)); + + if (PMU->STS & RSTSource) + { + PMU->STS = RSTSource; //Clear flag + return (1); + } + else + { + return (0); + } +} + +/** + * @brief Get power status. + * @param StatusMask: + PMU_PWRSTS_AVCCLV + PMU_PWRSTS_VDCINDROP + PMU_PWRSTS_VDDALARM + * @retval power status + * 1 status set + * 0 status not set + */ +uint8_t PMU_GetPowerStatus(uint32_t StatusMask) +{ + if (ANA->COMPOUT & StatusMask) + return 1; + else + return 0; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pwm.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pwm.c new file mode 100644 index 0000000000..6b99c2be1c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_pwm.c @@ -0,0 +1,466 @@ +/** + ****************************************************************************** + * @file lib_pwm.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief PWM library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_pwm.h" + +/** + * @brief PWM timebase initialization. + * @param PWMx: PWM0~PWM3 + InitStruct:PWM BASE configuration. + ClockDivision: + PWM_CLKDIV_2 + PWM_CLKDIV_4 + PWM_CLKDIV_8 + PWM_CLKDIV_16 + Mode: + PWM_MODE_STOP + PWM_MODE_UPCOUNT + PWM_MODE_CONTINUOUS + PWM_MODE_UPDOWN + ClockSource: + PWM_CLKSRC_APB + PWM_CLKSRC_APBD128 + * @retval None + */ +void PWM_BaseInit(PWM_TypeDef *PWMx, PWM_BaseInitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CLKDIV(InitStruct->ClockDivision)); + assert_parameters(IS_PWM_CNTMODE(InitStruct->Mode)); + assert_parameters(IS_PWM_CLKSRC(InitStruct->ClockSource)); + + tmp = PWMx->CTL; + tmp &= ~(PWM_CTL_ID\ + |PWM_CTL_MC\ + |PWM_CTL_TESL); + tmp |= (InitStruct->ClockDivision\ + |InitStruct->Mode\ + |InitStruct->ClockSource); + PWMx->CTL = tmp; +} + +/** + * @brief Fills each PWM_BaseInitType member with its default value. + * @param InitStruct: pointer to an PWM_BaseInitType structure which will be initialized. + * @retval None + */ +void PWM_BaseStructInit(PWM_BaseInitType *InitStruct) +{ + /*------------ Reset PWM base init structure parameters values ------------*/ + /* Initialize the ClockDivision member */ + InitStruct->ClockDivision = PWM_CLKDIV_2; + /* Initialize the ClockSource member */ + InitStruct->ClockSource = PWM_CLKSRC_APBD128; + /* Initialize the Mode member */ + InitStruct->Mode = PWM_MODE_STOP; +} + +/** + * @brief Fills each PWM_OCInitType member with its default value. + * @param OCInitType: pointer to an PWM_OCInitType structure which will be initialized. + * @retval None + */ +void PWM_OCStructInit(PWM_OCInitType *OCInitType) +{ + /*------- Reset PWM output channel init structure parameters values --------*/ + /* Initialize the OutMode member */ + OCInitType->OutMode = PWM_OUTMOD_CONST; + /* Initialize the Period member */ + OCInitType->Period = 0; +} + +/** + * @brief PWM output compare channel 0. + * @param PWMx: PWM0~PWM3 + OCInitType:PWM output compare configuration. + OutMode: + PWM_OUTMOD_CONST + PWM_OUTMOD_SET + PWM_OUTMOD_TOGGLE_RESET + PWM_OUTMOD_SET_RESET + PWM_OUTMOD_TOGGLE + PWM_OUTMOD_RESET + PWM_OUTMOD_TOGGLE_SET + PWM_OUTMOD_RESET_SET + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_OC0Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode)); + assert_parameters(IS_PWM_CCR(OCInitType->Period)); + + tmp = PWMx->CCTL0; + tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG); + tmp |= OCInitType->OutMode; + PWMx->CCTL0 = tmp; + PWMx->CCR0 = OCInitType->Period; +} + +/** + * @brief PWM output compare channel 1. + * @param PWMx: PWM0~PWM3 + OCInitType:PWM output compare configuration. + OutMode: + PWM_OUTMOD_CONST + PWM_OUTMOD_SET + PWM_OUTMOD_TOGGLE_RESET + PWM_OUTMOD_SET_RESET + PWM_OUTMOD_TOGGLE + PWM_OUTMOD_RESET + PWM_OUTMOD_TOGGLE_SET + PWM_OUTMOD_RESET_SET + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_OC1Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode)); + assert_parameters(IS_PWM_CCR(OCInitType->Period)); + + tmp = PWMx->CCTL1; + tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG); + tmp |= OCInitType->OutMode; + PWMx->CCTL1 = tmp; + PWMx->CCR1 = OCInitType->Period; +} + +/** + * @brief PWM output compare channel 2. + * @param PWMx: PWM0~PWM3 + OCInitType:PWM output compare configuration. + OutMode: + PWM_OUTMOD_CONST + PWM_OUTMOD_SET + PWM_OUTMOD_TOGGLE_RESET + PWM_OUTMOD_SET_RESET + PWM_OUTMOD_TOGGLE + PWM_OUTMOD_RESET + PWM_OUTMOD_TOGGLE_SET + PWM_OUTMOD_RESET_SET + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_OC2Init(PWM_TypeDef *PWMx, PWM_OCInitType *OCInitType) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_OUTMODE(OCInitType->OutMode)); + assert_parameters(IS_PWM_CCR(OCInitType->Period)); + + tmp = PWMx->CCTL2; + tmp &= ~(PWM_CCTL_OUTMOD | PWM_CCTL_CCIGG); + tmp |= OCInitType->OutMode; + PWMx->CCTL2 = tmp; + PWMx->CCR2 = OCInitType->Period; +} + +/** + * @brief PWM base interrupt configure. + * @param PWMx: PWM0~PWM3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_BaseINTConfig(PWM_TypeDef *PWMx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = PWMx->CTL; + tmp &= ~(PWM_CTL_IE | PWM_CTL_IFG); + if (NewState == ENABLE) + { + tmp |= PWM_CTL_IE; + } + PWMx->CTL = tmp; +} + +/** + * @brief Get PWM base interrupt status. + * @param PWMx: PWM0~PWM3 + * @retval interrupt status. + */ +uint8_t PWM_GetBaseINTStatus(PWM_TypeDef *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + if (PWMx->CTL&PWM_CTL_IFG) + return 1; + else + return 0; +} + +/** + * @brief Clear PWM base interrupt status. + * @param PWMx: PWM0~PWM3 + * @retval None. + */ +void PWM_ClearBaseINTStatus(PWM_TypeDef *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + PWMx->CTL |= PWM_CTL_IFG; +} + +/** + * @brief channel interrupt configure. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_ChannelINTConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + tmp &= ~(PWM_CCTL_CCIE | PWM_CCTL_CCIGG); + if (NewState == ENABLE) + { + tmp |= PWM_CCTL_CCIE; + } + *addr = tmp; +} + +/** + * @brief Get channel interrupt status. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + * @retval interrupt status + */ +uint8_t PWM_GetChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + if (tmp & PWM_CCTL_CCIGG) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear channel interrupt status. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + * @retval None + */ +void PWM_ClearChannelINTStatus(PWM_TypeDef *PWMx, uint32_t Channel) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + addr = &PWMx->CCTL0 + Channel; + + tmp = *addr; + tmp &= ~PWM_CCTL_CCIGG; + tmp |= PWM_CCTL_CCIGG; + *addr = tmp; +} + +/** + * @brief PWM clear counter. + * @param PWMx: PWM0~PWM3 + * @retval None + */ +void PWM_ClearCounter(PWM_TypeDef *PWMx) +{ + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + + PWMx->CTL |= PWM_CTL_CLR; +} + +/** + * @brief Configure PWMx channelx's CCR value. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + Period: 0 ~ 0xFFFF + * @retval None + */ +void PWM_CCRConfig(PWM_TypeDef *PWMx, uint32_t Channel, uint16_t Period) +{ + __IO uint32_t *addr; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + + addr = &PWMx->CCR0 + Channel; + *addr = Period; +} + +/** + * @brief pwm output line selection. + * @param OutSelection: + PWM0_OUT0 + PWM0_OUT1 + PWM0_OUT2 + PWM1_OUT0 + PWM1_OUT1 + PWM1_OUT2 + PWM2_OUT0 + PWM2_OUT1 + PWM2_OUT2 + PWM3_OUT0 + PWM3_OUT1 + PWM3_OUT2 + OLine: can use the ¡®|¡¯ operator + PWM_OLINE_0 + PWM_OLINE_1 + PWM_OLINE_2 + PWM_OLINE_3 + * @note PWM Single channel's output waveform can be output on multiple output lines. + * Multiple-line configuration can be performed by using the ¡®|¡¯ operator. + * ex: PWM_OLineConfig(PWM0_OUT0, PWM_OLINE_0 | PWM_OLINE_2) + * PWM0 channel0 output by PWM0&PWM2's lien. + * @retval None + */ +void PWM_OLineConfig(uint32_t OutSelection, uint32_t OLine) +{ + uint32_t tmp; + uint32_t position = 0; + + /* Check parameters */ + assert_parameters(IS_PWM_OUTLINE(OLine)); + assert_parameters(IS_PWM_OUTSEL(OutSelection)); + + tmp = PWMMUX->OSEL; + while ((OLine >> position) != 0UL) + { + if ((OLine >> position) & 1UL) + { + tmp &= ~(PWM_O_SEL_O_SEL0 << (position * 4)); + tmp |= (OutSelection << (position * 4)); + } + position++; + } + PWMMUX->OSEL = tmp; +} + +/** + * @brief PWM output enable. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void PWM_OutputCmd(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t NewState) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + tmp &= ~PWM_CCTL_CCIGG; + if (NewState == ENABLE) + tmp |= PWM_CCTL_OUTEN; + else + tmp &= ~PWM_CCTL_OUTEN; + *addr = tmp; +} + +/** + * @brief Set channel output level. + * @param PWMx: PWM0~PWM3 + Channel: + PWM_CHANNEL_0 + PWM_CHANNEL_1 + PWM_CHANNEL_2 + Level: + PWM_LEVEL_HIGH + PWM_LEVEL_LOW + * @retval None + */ +void PWM_SetOutLevel(PWM_TypeDef *PWMx, uint32_t Channel, uint32_t Level) +{ + __IO uint32_t *addr; + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_PWM_ALL_INSTANCE(PWMx)); + assert_parameters(IS_PWM_CHANNEL(Channel)); + assert_parameters(IS_PWM_OUTLVL(Level)); + + addr = &PWMx->CCTL0 + Channel; + tmp = *addr; + tmp &= ~(PWM_CCTL_OUT | PWM_CCTL_CCIGG); + tmp |= Level; + *addr = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_rtc.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_rtc.c new file mode 100644 index 0000000000..855817dfee --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_rtc.c @@ -0,0 +1,667 @@ +/** + ****************************************************************************** + * @file lib_rtc.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief RTC library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_rtc.h" + +#define RTCPWD_KEY 0x5AA55AA5 +#define RTCCE_SETKEY 0xA55AA55B +#define RTCCE_CLRKEY 0xA55AA55A + +/** + * @brief RTC registers write protection control. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_WriteProtection(uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + /* Enable RTC Write-Protection */ + if (NewState != DISABLE) + { + RTC->PWD = RTCPWD_KEY; + RTC->CE = RTCCE_CLRKEY; + } + /* Disable RTC Write-Protection */ + else + { + RTC->PWD = RTCPWD_KEY; + RTC->CE = RTCCE_SETKEY; + } +} + +/** + * @brief Wait until the RTC registers (be W/R protected) are synchronized + * with RTC APB clock. + * + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtection(DISABLE) before calling this function. + * Write-Operation process as follows: + * 1. RTC_WriteProtection(DISABLE); + * 2. RTC Registers write operation(only first write-operation be + * valid on the same register). + * 3. RTC_WriteProtection(ENABLE); + * 4. RTC_WaitForSynchro(); Wait until the RTC registers be + * synchronized by calling this function. + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + while (RTC->CE & RTC_CE_BSY) + { + } +} + +/** + * @brief Write RTC registers(continuous/be write-protected). + * @param[in] StartAddr the start address of registers be written + * @param[in] wBuffer pointer to write + * @param[in] Len number of registers be written + * @retval None + */ +void RTC_WriteRegisters(uint32_t StartAddr, const uint32_t *wBuffer, uint8_t Len) +{ + uint8_t cnt; + + /* Parameter check */ + assert_parameters(IS_RTC_REGOP_STARTADDR(StartAddr)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + for (cnt=0; cntLOAD */ + tmp = RTC->LOAD; + tmp += 1; + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Read registers */ + for (cnt=0; cntYear)); + assert_parameters(IS_RTC_TIME_MONTH(sTime->Month)); + assert_parameters(IS_RTC_TIME_DATE(sTime->Date)); + assert_parameters(IS_RTC_TIME_WEEKDAY(sTime->WeekDay)); + assert_parameters(IS_RTC_TIME_HOURS(sTime->Hours)); + assert_parameters(IS_RTC_TIME_MINS(sTime->Minutes)); + assert_parameters(IS_RTC_TIME_SECS(sTime->Seconds)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write RTC time registers */ + RTC->SEC = sTime->Seconds; + RTC->MIN = sTime->Minutes; + RTC->HOUR = sTime->Hours; + RTC->DAY = sTime->Date; + RTC->WEEK = sTime->WeekDay; + RTC->MON = sTime->Month; + RTC->YEAR = sTime->Year; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Get RTC current time. + * @param gTime: Pointer to Time structure + * @retval None +*/ +void RTC_GetTime(RTC_TimeTypeDef *gTime) +{ + __IO uint32_t dummy_data = 0; + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Dummy read-operation to RTC->LOAD register */ + dummy_data = RTC->LOAD; + dummy_data += 1; + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Read RTC time registers */ + gTime->Seconds = RTC->SEC; + gTime->Minutes = RTC->MIN; + gTime->Hours = RTC->HOUR; + gTime->Date = RTC->DAY; + gTime->WeekDay = RTC->WEEK; + gTime->Month = RTC->MON; + gTime->Year = RTC->YEAR; +} + +/** + * @brief Interrupt configure. + * @param INTMask: can use the ¡®|¡¯ operator + RTC_INT_CEILLE + RTC_INT_ACDONE + RTC_INT_WKUCNT + RTC_INT_MIDNIGHT + RTC_INT_WKUHOUR + RTC_INT_WKUMIN + RTC_INT_WKUSEC + RTC_INT_TIMEILLE + NewState: + ENABLE + DISABLE + * @retval None + */ +void RTC_INTConfig(uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = RTC->INTEN; + tmp &= ~(0x1UL); + + if (NewState == ENABLE) + tmp |= INTMask; + else + tmp &= ~INTMask; + + RTC->INTEN = tmp; +} + +/** + * @brief Get interrupt status. + * @param INTMask: + RTC_INTSTS_CEILLE + RTC_INTSTS_ACDONE + RTC_INTSTS_WKUCNT + RTC_INTSTS_MIDNIGHT + RTC_INTSTS_WKUHOUR + RTC_INTSTS_WKUMIN + RTC_INTSTS_WKUSEC + RTC_INTSTS_TIMEILLE + * @retval 1: status set + 0: status reset. + */ +uint8_t RTC_GetINTStatus(uint32_t FlagMask) +{ + /* Parameter check */ + assert_parameters(IS_RTC_INTFLAGR(FlagMask)); + + if (RTC->INTSTS&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param INTMask: can use the ¡®|¡¯ operator + RTC_INTSTS_CEILLE + RTC_INTSTS_ACDONE + RTC_INTSTS_WKUCNT + RTC_INTSTS_MIDNIGHT + RTC_INTSTS_WKUHOUR + RTC_INTSTS_WKUMIN + RTC_INTSTS_WKUSEC + RTC_INTSTS_TIMEILLE + * @retval None + */ +void RTC_ClearINTStatus(uint32_t FlagMask) +{ + /* Parameter check */ + assert_parameters(IS_RTC_INTFLAGC(FlagMask)); + + RTC->INTSTS = FlagMask; +} + +/** + * @brief Fills each RTCAC_InitStruct member with its default value. + * @param RTCAC_InitStruct: pointer to an RTC_AutCalType structure which will be initialized. + * @retval None + */ +void RTC_AutoCalStructInit(RTC_AutCalType *RTCAC_InitStruct) +{ + /*------------ Reset RTC AutCal init structure parameters values -----------*/ + /* Initialize the ADCSource member */ + RTCAC_InitStruct->ADCSource = RTC_ADCS_DATA; + /* Initialize the ATClockSource member */ + RTCAC_InitStruct->ATClockSource = RTC_ATCS_DISABLE; + /* Initialize the ATDelay member */ + RTCAC_InitStruct->ATDelay = RTC_ATDELAY_15MS; + /* Initialize the Period member */ + RTCAC_InitStruct->Period = 0; +} + +/** + * @brief Auto calibration initialization. + * @param InitStruct: pointer to AutoCal_InitType Auto calibration configuration. + * ATDelay: + * RTC_ATDELAY_15MS + * RTC_ATDELAY_31MS + * RTC_ATDELAY_62MS + * RTC_ATDELAY_125MS + * ATClockSource: + * RTC_ATCS_DISABLE + * RTC_ATCS_SEC + * RTC_ATCS_MIN + * RTC_ATCS_HOUR + * ADCSource: + * RTC_ADCS_DATA + * RTC_ADCS_PORT + * Period: 0 ~ 63 + * @note Auto trigger period is (Period+1)*1, unit is set by ATClockSource. + * Auto trigger function is not valid when ATClockSource is RTC_ATCS_DISABLE. + * @retval None + */ +void RTC_AutoCalInit(RTC_AutCalType *InitStruct) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_AUTOCAL_ATDLY(InitStruct->ATDelay)); + assert_parameters(IS_RTC_AUTOCAL_ATCS(InitStruct->ATClockSource)); + assert_parameters(IS_RTC_AUTOCAL_ADCSRC(InitStruct->ADCSource)); + assert_parameters(IS_RTC_AUTOCAL_PERIOD(InitStruct->Period)); + + tmp = RTC->ACCTRL; + tmp &= ~(RTC_ACCTRL_ACPER\ + |RTC_ACCTRL_ACDEL\ + |RTC_ACCTRL_ACCLK\ + |RTC_ACCTRL_ADCSEL); + tmp |= (InitStruct->ADCSource\ + |InitStruct->ATClockSource\ + |InitStruct->ATDelay\ + |((InitStruct->Period << RTC_ACCTRL_ACPER_Pos) & RTC_ACCTRL_ACPER)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + RTC->ACCTRL = tmp; + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief RTC automatic calibration auto-trigger source configure. + * @param TrigSource: + * RTC_ATCS_DISABLE + * RTC_ATCS_SEC + * RTC_ATCS_MIN + * RTC_ATCS_HOUR + * Period: 0 ~ 63 + * @retval None + */ +void RTC_TrigSourceConfig(uint32_t TrigSource, uint32_t Period) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_AUTOCAL_ATCS(TrigSource)); + assert_parameters(IS_RTC_AUTOCAL_PERIOD(Period)); + + tmp = RTC->ACCTRL; + tmp &= ~(RTC_ACCTRL_ACPER | RTC_ACCTRL_ACCLK); + tmp |= (TrigSource | (Period << RTC_ACCTRL_ACPER_Pos)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + RTC->ACCTRL = tmp; + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief ADC Auto-calibration enable control. + * @note When DISABLE is selected, the automatic triggering of the RTC-auto-calibration must be turned off by calling + * RTC_TrigSourceConfig(RTC_ATCS_DISABLE, 0) before using this function. + * @param NewState: + * ENABLE + * DISABLE + * @retval 0: Function succeeded + * 1: Function failded, the automatic triggering be enabled when DISABLE selected + */ +uint32_t RTC_AutoCalCmd(uint32_t NewState) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = RTC->ACCTRL; + if (NewState == DISABLE) + { + if (tmp & RTC_ACCTRL_ACCLK) + return 1; + else + tmp &= ~RTC_ACCTRL_ACEN; + } + else + { + tmp |= RTC_ACCTRL_ACEN; + } + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + RTC->ACCTRL = tmp; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + return 0; +} + +/** + * @brief Start RTC Auto-calibration manually. + * @param None + * @retval None + */ +void RTC_StartAutoCalManual(void) +{ + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* manual trigger Auto-calibration */ + RTC->ACCTRL |= RTC_ACCTRL_MANU; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Wait until Auto-calibration manual is done. + * @param None + * @retval None + */ +void RTC_WaitForAutoCalManual(void) +{ + while (RTC->ACCTRL&RTC_ACCTRL_MANU) + { + } +} + +/** + * @brief Get auto-calibration busy flag. + * @param None + * @retval 1 flag set + * 0 flag reset. + */ +uint8_t RTC_GetACBusyFlag(void) +{ + if (RTC->INTSTS & RTC_INTSTS_ACBSY) return (1); + else return (0); +} + + +/* + * @brief Multi-second wake up configure. + * @param nPeriod£ºN seconds interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 sec error if the new WKUSEC number(parameter) is not equal + * to current WKUSEC number. If the new WKUSEC is equal to current WKUSEC, + * the first interrupt time may have 0~(WKUSEC +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUSecondsConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUSEC_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUSEC = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/* + * @brief Multi-minute wake up configure. + * @param nPeriod£ºN minute interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 min error if the new WKUMIN number(parameter) is not equal + * to current WKUMIN number. If the new WKUMIN is equal to current WKUMIN, + * the first interrupt time may have 0~(WKUMIN +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUMinutesConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUMIN_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUMIN = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/* + * @brief Multi-hour wake up configure. + * @param nPeriod£ºN hour interval. + * @note For the first interrupt generated by calling this function, it may + * have < 1 hour error if the new WKUHOUR number(parameter) is not equal + * to current WKUHOUR number. If the new WKUHOUR is equal to current WKUHOUR, + * the first interrupt time may have 0~(WKUHOUR +1) variation. + * To avoid this problem, set an alternative parameter (like 1) by calling + * this function, then set the correct parameter to it. + * @retval None + */ +void RTC_WKUHoursConfig(uint8_t nPeriod) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUHOUR_PERIOD(nPeriod)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUHOUR = nPeriod - 1; + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief RTC counter wake up configure. + * @param nClock: 1 ~ 0x1000000 + CNTCLK: + RTC_WKUCNT_RTCCLK + RTC_WKUCNT_2048 + RTC_WKUCNT_512 + RTC_WKUCNT_128 + * @retval None + */ +void RTC_WKUCounterConfig(uint32_t nClock,uint32_t CNTCLK) +{ + /* Parameter check */ + assert_parameters(IS_RTC_WKUCNT_PERIOD(nClock)); + assert_parameters(IS_RTC_WKUCNT_CNTSEL(CNTCLK)); + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + + /* Write registers */ + RTC->WKUCNT = (CNTCLK & RTC_WKUCNT_CNTSEL) | (nClock -1 ); + + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief Gets RTC wake-up counter value. + * @retval RTC wake-up counter value + */ +uint32_t RTC_GetWKUCounterValue(void) +{ + return RTC->WKUCNTR; +} + +/** + * @brief RTC clock prescaler configure. + * @param[in] Prescaler: + * RTC_CLKDIV_1 + * RTC_CLKDIV_4 + * @retval None + */ +void RTC_PrescalerConfig(uint32_t Prescaler) +{ + uint32_t tmp; + + /* Parameter check */ + assert_parameters(IS_RTC_CLKDIV(Prescaler)); + + tmp = RTC->PSCA; + tmp &= ~RTC_PSCA_PSCA; + tmp |= Prescaler; + + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); + /* Disable RTC Registers write-protection */ + RTC_WriteProtection(DISABLE); + RTC->PSCA = tmp; + /* Enable RTC Registers write-protection */ + RTC_WriteProtection(ENABLE); + /* Wait until the RTC registers be synchronized */ + RTC_WaitForSynchro(); +} + +/** + * @brief RTC PLLDIV frequency configure. + * @param nfrequency(HZ): the frequency of RTC PLLDIV output configuration. + * @note Ensure clocks be configured by calling function CLK_ClockConfig(), + * get correct PCLK frequency by calling function CLK_GetPCLKFreq(). + * @retval None + */ +void RTC_PLLDIVConfig(uint32_t nfrequency) +{ + RTC->DIV = CLK_GetPCLKFreq()/2/nfrequency - 1; +} + +/** + * @brief RTC PLLDIV output enable. + * @param NewState: + * ENABLE + * DISABLE + * @retval None + */ +void RTC_PLLDIVOutputCmd(uint8_t NewState) +{ + /* Parameter check */ + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) RTC->CTL |= RTC_CTL_RTCPLLOE; + else RTC->CTL &= ~RTC_CTL_RTCPLLOE; +} + + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_spi.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_spi.c new file mode 100644 index 0000000000..b134d359cd --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_spi.c @@ -0,0 +1,430 @@ +/** + ****************************************************************************** + * @file lib_spi.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief SPI library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_spi.h" + +#define SPI_MISC_RSTValue (0UL) + +/** + * @brief Reset SPI controller. + * @param SPIx:SPI1~SPI2 + * @retval None + */ +void SPI_DeviceInit(SPI_TypeDef *SPIx) +{ + __IO uint32_t dummy_data = 0UL; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Disable SPI */ + SPIx->CTRL = 0; + /* SPI soft reset */ + SPIx->CTRL |= SPI_CTRL_SPIRST; + SPIx->CTRL &= ~SPI_CTRL_SPIRST; + /* Clear flag */ + dummy_data = SPIx->RXDAT; + dummy_data += 1; + SPIx->TXSTS = SPI_TXSTS_TXIF; + SPIx->RXSTS = SPI_RXSTS_RXIF; + /* write default values */ + SPIx->MISC_ = SPI_MISC_RSTValue; +} + +/** + * @brief Fills each SPI_InitType member with its default value. + * @param InitStruct: pointer to an SPI_InitType structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitType *InitStruct) +{ + /*--------------- Reset SPI init structure parameters values ---------------*/ + /* Initialize the ClockDivision member */ + InitStruct->ClockDivision = SPI_CLKDIV_2; + /* Initialize the CSNSoft member */ + InitStruct->CSNSoft = SPI_CSNSOFT_DISABLE; + /* Initialize the Mode member */ + InitStruct->Mode = SPI_MODE_MASTER; + /* Initialize the SPH member */ + InitStruct->SPH = SPI_SPH_0; + /* Initialize the SPO member */ + InitStruct->SPO = SPI_SPO_0; + /* Initialize the SWAP member */ + InitStruct->SWAP = SPI_SWAP_DISABLE; +} + +/** + * @brief SPI initialization. + * @param SPIx:SPI1~SPI2 + InitStruct: SPI configuration. + Mode: + SPI_MODE_MASTER + SPI_MODE_SLAVE + SPH: + SPI_SPH_0 + SPI_SPH_1 + SPO: + SPI_SPO_0 + SPI_SPO_1 + ClockDivision: + SPI_CLKDIV_2 + SPI_CLKDIV_4 + SPI_CLKDIV_8 + SPI_CLKDIV_16 + SPI_CLKDIV_32 + SPI_CLKDIV_64 + SPI_CLKDIV_128 + CSNSoft: + SPI_CSNSOFT_ENABLE + SPI_CSNSOFT_DISABLE + SWAP: + SPI_SWAP_ENABLE + SPI_SWAP_DISABLE + * @retval None + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_MODE(InitStruct->Mode)); + assert_parameters(IS_SPI_SPH(InitStruct->SPH)); + assert_parameters(IS_SPI_SPO(InitStruct->SPO)); + assert_parameters(IS_SPI_CLKDIV(InitStruct->ClockDivision)); + assert_parameters(IS_SPI_CSN(InitStruct->CSNSoft)); + assert_parameters(IS_SPI_SWAP(InitStruct->SWAP)); + + tmp = SPIx->CTRL; + tmp &= ~(SPI_CTRL_MOD\ + |SPI_CTRL_SCKPHA\ + |SPI_CTRL_SCKPOL\ + |SPI_CTRL_CSGPIO\ + |SPI_CTRL_SWAP\ + |SPI_CTRL_SCKSEL); + tmp |= (InitStruct->Mode\ + |InitStruct->SPH\ + |InitStruct->SPO\ + |InitStruct->CSNSoft\ + |InitStruct->SWAP\ + |InitStruct->ClockDivision); + SPIx->CTRL = tmp; +} + +/** + * @brief Enables or disables SPI. + * @param SPIx:SPI1~SPI2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_Cmd(SPI_TypeDef *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + SPIx->CTRL |= SPI_CTRL_SPIEN; + else + SPIx->CTRL &= ~SPI_CTRL_SPIEN; +} + +/** + * @brief SPI interrupt config. + * @param SPIx:SPI1~SPI2 + INTMask: can use the ¡®|¡¯ operator + SPI_INT_TX + SPI_INT_RX + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_INTConfig(SPI_TypeDef *SPIx, uint32_t INTMask, uint32_t NewState) +{ + uint32_t tmp, tmp_INTMask; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp_INTMask = INTMask; + if (tmp_INTMask & 0x80000000) + { + INTMask &= 0xFFFF; + tmp = SPIx->TXSTS; + tmp &= ~SPI_TXSTS_TXIF; + if (NewState == ENABLE) + { + tmp |= INTMask; + SPIx->TXSTS = tmp; + } + else + { + tmp &= ~INTMask; + SPIx->TXSTS = tmp; + } + } + if (tmp_INTMask & 0x40000000) + { + INTMask &= 0xFFFF; + tmp = SPIx->RXSTS; + tmp &= ~SPI_RXSTS_RXIF; + if (NewState == ENABLE) + { + tmp |= INTMask; + SPIx->RXSTS = tmp; + } + else + { + tmp &= ~INTMask; + SPIx->RXSTS = tmp; + } + } +} + +/** + * @brief Get status flag. + * @param SPIx:SPI1~SPI2 + Status: + SPI_STS_TXIF + SPI_STS_TXEMPTY + SPI_STS_TXFUR + SPI_STS_RXIF + SPI_STS_RXFULL + SPI_STS_RXFOV + SPI_STS_BSY + SPI_STS_RFF + SPI_STS_RNE + SPI_STS_TNF + SPI_STS_TFE + * @retval Flag status. + */ +uint8_t SPI_GetStatus(SPI_TypeDef *SPIx, uint32_t Status) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_STSR(Status)); + + if ((Status&0xE0000000) == 0x80000000) + { + if (Status&SPIx->TXSTS) + return 1; + else + return 0; + } + else if ((Status&0xE0000000) == 0x40000000) + { + if (Status&SPIx->RXSTS) + return 1; + else + return 0; + } + else + { + if (Status&SPIx->MISC_) + return 1; + else + return 0; + } +} + +/** + * @brief Clear status flag. + * @param SPIx:SPI1~SPI2 + Status: can use the ¡®|¡¯ operator + SPI_STS_TXIF + SPI_STS_RXIF + * @retval None + */ +void SPI_ClearStatus(SPI_TypeDef *SPIx, uint32_t Status) +{ + uint32_t tmp_status; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_STSC(Status)); + + tmp_status = Status; + if (tmp_status & 0x80000000) + { + Status &= 0xFFFF; + SPIx->TXSTS |= Status; + } + if (tmp_status & 0x40000000) + { + Status &= 0xFFFF; + SPIx->RXSTS |= Status; + } +} + +/** + * @brief Load send data register. + * @param SPIx:SPI1~SPI2 + ch: data write to send data register + * @retval None + */ +void SPI_SendData(SPI_TypeDef *SPIx, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + SPIx->TXDAT = ch; +} + +/** + * @brief Read receive data register. + * @param SPIx:SPI1~SPI2 + * @retval receive data value + */ +uint8_t SPI_ReceiveData(SPI_TypeDef *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->RXDAT); +} + +/** + * @brief Transmit fifo level configure. + * @param SPIx:SPI1~SPI2 + FIFOLevel: + SPI_TXFLEV_0 + SPI_TXFLEV_1 + SPI_TXFLEV_2 + SPI_TXFLEV_3 + SPI_TXFLEV_4 + SPI_TXFLEV_5 + SPI_TXFLEV_6 + SPI_TXFLEV_7 + * @retval None + */ +void SPI_TransmitFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_TXFLEV(FIFOLevel)); + + tmp = SPIx->TXSTS; + tmp &= ~(SPI_TXSTS_TXFLEV | SPI_TXSTS_TXIF); + tmp |= FIFOLevel; + SPIx->TXSTS = tmp; +} + +/** + * @brief Receive fifo level configure. + * @param SPIx:SPI1~SPI2 + FIFOLevel: + SPI_RXFLEV_0 + SPI_RXFLEV_1 + SPI_RXFLEV_2 + SPI_RXFLEV_3 + SPI_RXFLEV_4 + SPI_RXFLEV_5 + SPI_RXFLEV_6 + SPI_RXFLEV_7 + * @retval None + */ +void SPI_ReceiveFIFOLevelConfig(SPI_TypeDef *SPIx, uint32_t FIFOLevel) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_SPI_RXFLEV(FIFOLevel)); + + tmp = SPIx->RXSTS; + tmp &= ~(SPI_RXSTS_RXFLEV | SPI_RXSTS_RXIF); + tmp |= FIFOLevel; + SPIx->RXSTS = tmp; +} + +/** + * @brief Get transmit fifo level. + * @param SPIx:SPI1~SPI2 + * @retval Transmit fifo level. + */ +uint8_t SPI_GetTransmitFIFOLevel(SPI_TypeDef *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->TXSTS & SPI_TXSTS_TXFFLAG); +} + +/** + * @brief Get receive fifo level. + * @param SPIx:SPI1~SPI2 + * @retval Receive fifo level. + */ +uint8_t SPI_GetReceiveFIFOLevel(SPI_TypeDef *SPIx) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + + return (SPIx->RXSTS & SPI_RXSTS_RXFFLAG); +} + +/** + * @brief FIFO smart mode. + * @param SPIx:SPI1~SPI2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_SmartModeCmd(SPI_TypeDef *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + SPIx->MISC_ |= SPI_MISC_SMART; + } + else + { + SPIx->MISC_ &= ~SPI_MISC_SMART; + } +} + +/** + * @brief FIFO over write mode. + * @param SPIx:SPI1~SPI2 + NewState: + ENABLE + DISABLE + * @retval None + */ +void SPI_OverWriteModeCmd(SPI_TypeDef *SPIx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_SPI_ALL_INSTANCE(SPIx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + SPIx->MISC_ |= SPI_MISC_OVER; + } + else + { + SPIx->MISC_ &= ~SPI_MISC_OVER; + } +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_tmr.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_tmr.c new file mode 100644 index 0000000000..b022bb511c --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_tmr.c @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file lib_tmr.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief Timer library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_tmr.h" + +#define TMR_CTRL_RSTValue (0UL) +#define TMR_VALUE_RSTValue (0UL) +#define TMR_RELOAD_RSTValue (0UL) + +/** + * @brief Initializes the TMRx peripheral registers to their default reset values. + * @param TMRx: + TMR0 ~ TMR3 + * @retval None + */ +void TMR_DeInit(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + /* Disable timer */ + TMRx->CTRL &= ~TMR_CTRL_EN; + /* clear interrupt status */ + TMRx->INT = TMR_INT_INT; + /* write default reset values */ + TMRx->CTRL = TMR_CTRL_RSTValue; + TMRx->RELOAD = TMR_RELOAD_RSTValue; + TMRx->VALUE = TMR_VALUE_RSTValue; +} + +/** + * @brief TMR initialization. + * @param TMRx: + TMR0 ~ TMR3 + InitStruct: Timer configuration. + ClockSource: + TMR_CLKSRC_INTERNAL + TMR_CLKSRC_EXTERNAL + EXTGT: + TMR_EXTGT_DISABLE + TMR_EXTGT_ENABLE + Period: the auto-reload value + * @retval None + */ +void TMR_Init(TMR_TypeDef *TMRx, TMR_InitType *InitStruct) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_TMR_CLKSRC(InitStruct->ClockSource)); + assert_parameters(IS_TMR_EXTGT(InitStruct->EXTGT)); + + tmp = TMRx->CTRL; + tmp &= ~(TMR_CTRL_EXTCLK|TMR_CTRL_EXTEN); + tmp |= (InitStruct->ClockSource|InitStruct->EXTGT); + TMRx->CTRL = tmp; + TMRx->VALUE = InitStruct->Period; + TMRx->RELOAD = InitStruct->Period; +} + +/** + * @brief Fills each TMR_InitType member with its default value. + * @param InitStruct: pointer to an TMR_InitType structure which will be initialized. + * @retval None + */ +void TMR_StructInit(TMR_InitType *InitStruct) +{ + /*--------------- Reset TMR init structure parameters values ---------------*/ + /* Initialize the ClockSource member */ + InitStruct->ClockSource = TMR_CLKSRC_INTERNAL; + /* Initialize the EXTGT member */ + InitStruct->EXTGT = TMR_EXTGT_DISABLE; + /* Initialize the Period member */ + InitStruct->Period = 0; +} + +/** + * @brief Interrupt configuration. + * @param TMRx: + TMR0~TMR3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void TMR_INTConfig(TMR_TypeDef *TMRx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + TMRx->CTRL |= TMR_CTRL_INTEN; + } + else + { + TMRx->CTRL &= ~TMR_CTRL_INTEN; + } +} + +/** + * @brief Get timer interrupt status. + * @param TMRx: + TMR0~TMR3 + * @retval Interrupt status. + */ +uint8_t TMR_GetINTStatus(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + if (TMRx->INT&TMR_INT_INT) + return 1; + else + return 0; +} + +/** + * @brief Clear timer interrupt status bit. + * @param TMRx: + TMR0~TMR3 + * @retval None. + */ +void TMR_ClearINTStatus(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + TMRx->INT = TMR_INT_INT; +} + +/** + * @brief TMRER enable. + * @param TMRx: + TMR0~TMR3 + NewState: + ENABLE + DISABLE + * @retval None + */ +void TMR_Cmd(TMR_TypeDef *TMRx, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + TMRx->CTRL |= TMR_CTRL_EN; + else + TMRx->CTRL &= ~TMR_CTRL_EN; +} + +/** + * @brief Get TMRx current value. + * @param TMRx: + TMR0~TMR3 + * @retval timer value. + */ +uint32_t TMR_GetCurrentValue(TMR_TypeDef *TMRx) +{ + /* Check parameters */ + assert_parameters(IS_TMR_ALL_INSTANCE(TMRx)); + + return (TMRx->VALUE); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_u32k.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_u32k.c new file mode 100644 index 0000000000..4d321ec9f3 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_u32k.c @@ -0,0 +1,317 @@ +/** + ****************************************************************************** + * @file lib_u32k.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief UART 32K library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_u32k.h" + +#define U32K_STS_Msk (0x7UL) +#define U32K_CTRL0_RSTValue (0UL) +#define U32K_CTRL1_RSTValue (0UL) +#define U32K_PHASE_RSTValue (0x4B00UL) + +/** + * @brief Initializes the U32Kx peripheral registers to their default reset + values. + * @param U32Kx: U32K0~U32K1 + * @retval None + */ +void U32K_DeInit(U32K_TypeDef *U32Kx) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + + /* Disable U32K */ + U32Kx->CTRL0 &= ~U32K_CTRL0_EN; + /* clear interrupt status */ + U32Kx->STS = U32K_STS_Msk; + /* write default reset values */ + U32Kx->CTRL0 = U32K_CTRL0_RSTValue; + U32Kx->CTRL1 = U32K_CTRL1_RSTValue; + U32Kx->PHASE = U32K_PHASE_RSTValue; +} + +/** + * @brief U32K initialization. + * @param U32Kx: + U32K0~U32K1 + InitStruct: U32K configuration + Debsel: + U32K_DEBSEL_0 + U32K_DEBSEL_1 + U32K_DEBSEL_2 + U32K_DEBSEL_3 + Parity: + U32K_PARITY_EVEN + U32K_PARITY_ODD + U32K_PARITY_0 + U32K_PARITY_1 + U32K_PARITY_NONE + WordLen: + U32K_WORDLEN_8B + U32K_WORDLEN_9B + FirstBit: + U32K_FIRSTBIT_LSB + U32K_FIRSTBIT_MSB + AutoCal: + U32K_AUTOCAL_ON + U32K_AUTOCAL_OFF + LineSel: + U32K_LINE_RX0 + U32K_LINE_RX1 + U32K_LINE_RX2 + U32K_LINE_RX3 + Baudrate: Baudrate value + * @retval None + */ +void U32K_Init(U32K_TypeDef *U32Kx, U32K_InitType *InitStruct) +{ + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_DEBSEL(InitStruct->Debsel)); + assert_parameters(IS_U32K_PARITY(InitStruct->Parity)); + assert_parameters(IS_U32K_WORDLEN(InitStruct->WordLen)); + assert_parameters(IS_U32K_FIRSTBIT(InitStruct->FirstBit)); + assert_parameters(IS_U32K_AUTOCAL(InitStruct->AutoCal)); + assert_parameters(IS_U32K_LINE(InitStruct->LineSel)); + assert_parameters(IS_U32K_BAUDRATE(InitStruct->Baudrate)); + + tmp_reg1 = U32Kx->CTRL0; + tmp_reg1 &= ~(U32K_CTRL0_DEBSEL\ + |U32K_CTRL0_PMODE\ + |U32K_CTRL0_MODE\ + |U32K_CTRL0_MSB\ + |U32K_CTRL0_ACOFF); + tmp_reg1 |= (InitStruct->Debsel\ + |InitStruct->Parity\ + |InitStruct->WordLen\ + |InitStruct->FirstBit\ + |InitStruct->AutoCal); + U32Kx->CTRL0 = tmp_reg1; + if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz + U32Kx->PHASE = 65536*InitStruct->Baudrate/32768; + else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz + U32Kx->PHASE = 65536*InitStruct->Baudrate/8192; + else + assert_parameters(0); + + tmp_reg2 = U32Kx->CTRL1; + tmp_reg2 &= ~(U32K_CTRL1_RXSEL); + tmp_reg2 |= (InitStruct->LineSel); + U32Kx->CTRL1 = tmp_reg2; +} + +/** + * @brief Fills each U32K_InitType member with its default value. + * @param InitStruct: pointer to an U32K_InitType structure which will be initialized. + * @retval None + */ +void U32K_StructInit(U32K_InitType *InitStruct) +{ + /*-------------- Reset U32K init structure parameters values ---------------*/ + /* Initialize the AutoCal member */ + InitStruct->AutoCal = U32K_AUTOCAL_ON; + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the Debsel member */ + InitStruct->Debsel = U32K_DEBSEL_0; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = U32K_FIRSTBIT_LSB; + /* Initialize the LineSel member */ + InitStruct->LineSel = U32K_LINE_RX0; + /* Initialize the Parity member */ + InitStruct->Parity = U32K_PARITY_NONE; + /* Initialize the Parity member */ + InitStruct->WordLen = U32K_WORDLEN_8B; +} + +/** + * @brief U32K interrupt configuration. + * @param U32Kx: + U32K0~U32K1 + INTMask: can use the ¡®|¡¯ operator + U32K_INT_RXOV + U32K_INT_RXPE + U32K_INT_RX + NewState: + ENABLE + DISABLE + * @retval None + */ +void U32K_INTConfig(U32K_TypeDef *U32Kx, uint32_t INTMask, uint8_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = U32Kx->CTRL1; + tmp &= ~INTMask; + if (NewState == ENABLE) + { + tmp |= INTMask; + } + U32Kx->CTRL1 = tmp; +} + +/** + * @brief Get interrupt flag status. + * @param U32Kx: + U32K0~U32K1 + INTMask: + U32K_INTSTS_RXOV + U32K_INTSTS_RXPE + U32K_INTSTS_RX + * @retval Flag status + */ +uint8_t U32K_GetINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INTFLAGR(INTMask)); + + if (U32Kx->STS&INTMask) + return 1; + else + return 0; +} + +/** + * @brief Clear flag status. + * @param U32Kx: + U32K0~U32K1 + INTMask: can use the ¡®|¡¯ operator + U32K_INTSTS_RXOV + U32K_INTSTS_RXPE + U32K_INTSTS_RX + * @retval None + */ +void U32K_ClearINTStatus(U32K_TypeDef *U32Kx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_INTFLAGC(INTMask)); + + U32Kx->STS = INTMask; +} + +/** + * @brief Read receive data register. + * @param U32Kx: + U32K0~U32K1 + * @retval Receive data value + */ +uint8_t U32K_ReceiveData(U32K_TypeDef *U32Kx) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + + return (U32Kx->DATA); +} + +/** + * @brief U32K Baudrate control. + * @param U32Kx: U32K0~U32K1 + BaudRate: Baudrate value + * @retval None + */ +void U32K_BaudrateConfig(U32K_TypeDef *U32Kx, uint32_t BaudRate) +{ + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_BAUDRATE(BaudRate)); + + if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_0) //RTCCLK 32768Hz + U32Kx->PHASE = 65536*BaudRate/32768; + else if ((RTC->PSCA & RTC_PSCA_PSCA) == RTC_PSCA_PSCA_1) //RTCCLK 8192Hz + U32Kx->PHASE = 65536*BaudRate/8192; + else + assert_parameters(0); +} + +/** + * @brief U32K controlller enable. + * @param U32Kx: + U32K0~U32K1 + NewState: + ENABLE + DISABLE + * @retval None + */ +void U32K_Cmd(U32K_TypeDef *U32Kx, uint32_t NewState) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + tmp = U32Kx->CTRL0; + tmp &= ~(U32K_CTRL0_EN); + if (NewState == ENABLE) + { + tmp |= U32K_CTRL0_EN; + } + U32Kx->CTRL0 = tmp; +} + +/** + * @brief U32K receive line selection. + * @param U32Kx: + U32K0~U32K1 + Line: + U32K_LINE_RX0 + U32K_LINE_RX1 + U32K_LINE_RX2 + U32K_LINE_RX3 + * @retval None + */ +void U32K_LineConfig(U32K_TypeDef *U32Kx, uint32_t Line) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_LINE(Line)); + + tmp = U32Kx->CTRL1; + tmp &= ~U32K_CTRL1_RXSEL; + tmp |= Line; + U32Kx->CTRL1 = tmp; +} + +/** + * @brief Wake-up mode configure. + * @param U32Kx: + U32K0~U32K1 + WKUMode: + U32K_WKUMOD_RX + U32K_WKUMOD_PC + * @retval None + */ +void U32K_WKUModeConfig(U32K_TypeDef *U32Kx, uint32_t WKUMode) +{ + uint32_t tmp; + + /* Check parameters */ + assert_parameters(IS_U32K_ALL_INSTANCE(U32Kx)); + assert_parameters(IS_U32K_WKUMODE(WKUMode)); + + tmp = U32Kx->CTRL0; + tmp &= ~U32K_CTRL0_WKUMODE; + tmp |= WKUMode; + U32Kx->CTRL0 = tmp; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_uart.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_uart.c new file mode 100644 index 0000000000..7aeecea45b --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_uart.c @@ -0,0 +1,391 @@ +/** + ****************************************************************************** + * @file lib_uart.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief UART library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_uart.h" +#include "lib_clk.h" + +#define UART_STATE_RCMsk (0x3CUL) +#define UART_INTSTS_RCMsk (0x3FUL) +#define UART_BAUDDIV_RSTValue (0UL) +#define UART_CTRL_RSTValue (0UL) +#define UART_CTRL2_RSTValue (0UL) + +/** + * @brief Iinitializes the UARTx peripheral registers to their default reset + values. + * @param UARTx: UART0~UART5 + * @retval None + */ +void UART_DeInit(UART_TypeDef *UARTx) +{ + __IO uint32_t dummy_data = 0UL; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + /* read data, clear RXFULL flag */ + dummy_data = UARTx->DATA; + dummy_data += 1; + + UARTx->INTSTS = UART_INTSTS_RCMsk; + UARTx->STATE = UART_STATE_RCMsk; + UARTx->BAUDDIV = UART_BAUDDIV_RSTValue; + UARTx->CTRL2 = UART_CTRL2_RSTValue; + UARTx->CTRL = UART_CTRL_RSTValue; +} + +/** + * @brief UART initialization. + * @param UARTx: UART0~UART5 + InitStruct:UART configuration. + Mode: (between UART_MODE_RX and UART_MODE_TX, can use the ¡®|¡¯ operator) + UART_MODE_RX + UART_MODE_TX + UART_MODE_OFF + Parity: + UART_PARITY_EVEN + UART_PARITY_ODD + UART_PARITY_0 + UART_PARITY_1 + UART_PARITY_NONE + WordLen: + UART_WORDLEN_8B + UART_WORDLEN_9B + FirstBit: + UART_FIRSTBIT_LSB + UART_FIRSTBIT_MSB + Baudrate: Baudrate value + * @retval None + */ +void UART_Init(UART_TypeDef *UARTx, UART_InitType *InitStruct) +{ + uint32_t pclk; + uint32_t div; + uint32_t tmp_reg1, tmp_reg2; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_MODE(InitStruct->Mode)); + assert_parameters(IS_UART_PARITY(InitStruct->Parity)); + assert_parameters(IS_UART_WORDLEN(InitStruct->WordLen)); + assert_parameters(IS_UART_FIRSTBIT(InitStruct->FirstBit)); + assert_parameters(IS_UART_BAUDRATE(InitStruct->Baudrate)); + + tmp_reg1 = UARTx->CTRL; + tmp_reg1 &= ~(UART_CTRL_RXEN\ + |UART_CTRL_TXEN); + tmp_reg1 |= (InitStruct->Mode); + + tmp_reg2 = UARTx->CTRL2; + tmp_reg2 &= ~(UART_CTRL2_MSB \ + |UART_CTRL2_MODE \ + |UART_CTRL2_PMODE); + tmp_reg2 |= (InitStruct->Parity\ + |InitStruct->WordLen\ + |InitStruct->FirstBit); + UARTx->CTRL2 = tmp_reg2; + + pclk = CLK_GetPCLKFreq(); + div = pclk/InitStruct->Baudrate; + + if ((pclk%InitStruct->Baudrate) > (InitStruct->Baudrate/2)) + { + div++; + } + + UARTx->BAUDDIV = div; + UARTx->CTRL = tmp_reg1; +} + +/** + * @brief Fills each UART_InitType member with its default value. + * @param InitStruct: pointer to an UART_InitType structure which will be initialized. + * @retval None + */ +void UART_StructInit(UART_InitType *InitStruct) +{ + /*-------------- Reset UART init structure parameters values ---------------*/ + /* Initialize the Baudrate member */ + InitStruct->Baudrate = 9600; + /* Initialize the FirstBit member */ + InitStruct->FirstBit = UART_FIRSTBIT_LSB; + /* Initialize the Mode member */ + InitStruct->Mode = UART_MODE_OFF; + /* Initialize the Parity member */ + InitStruct->Parity = UART_PARITY_NONE; + /* Initialize the WordLen member */ + InitStruct->WordLen = UART_WORDLEN_8B; +} + +/** + * @brief Get peripheral flag. + * @param UARTx: UART0~UART5 + FlagMask: flag to get. + --UART_FLAG_RXPARITY + --UART_FLAG_TXDONE + --UART_FLAG_RXPE + --UART_FLAG_RXOV + --UART_FLAG_TXOV + --UART_FLAG_RXFULL + * @retval 1:flag set + 0:flag reset + */ +uint8_t UART_GetFlag(UART_TypeDef *UARTx, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_FLAGR(FlagMask)); + + if (UARTx->STATE&FlagMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear peripheral flag. + * @param UARTx: UART0~UART5 + FlagMask: status to clear, can use the ¡®|¡¯ operator. + --UART_FLAG_TXDONE + --UART_FLAG_RXPE + --UART_FLAG_RXOV + --UART_FLAG_TXOV + * @retval None + */ +void UART_ClearFlag(UART_TypeDef *UARTx, uint32_t FlagMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_FLAGC(FlagMask)); + + UARTx->STATE = FlagMask; +} + +/** + * @brief Enable or disable the specified UART interrupts. + * @param UARTx: UART0~UART5 + INTMask: can use the ¡®|¡¯ operator. + --UART_INT_TXDONE + --UART_INT_RXPE + --UART_INT_RXOV + --UART_INT_TXOV + --UART_INT_RX + NewState:New status of interrupt mask. + * @retval None + */ +void UART_INTConfig(UART_TypeDef *UARTx, uint32_t INTMask, uint8_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INT(INTMask)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->CTRL |= INTMask; + } + else + { + UARTx->CTRL &= ~INTMask; + } +} + +/** + * @brief Get interrupt status. + * @param UARTx: UART0~UART5 + INTMask: status to get. + --UART_INTSTS_TXDONE + --UART_INTSTS_RXPE + --UART_INTSTS_RXOV + --UART_INTSTS_TXOV + --UART_INTSTS_RX + * @retval 1:status set + 0:status reset + */ +uint8_t UART_GetINTStatus(UART_TypeDef *UARTx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INTFLAGR(INTMask)); + + if (UARTx->INTSTS&INTMask) + { + return 1; + } + else + { + return 0; + } +} + +/** + * @brief Clear interrupt status. + * @param UARTx: UART0~UART5 + INTMask: status to clear, can use the ¡®|¡¯ operator. + --UART_INTSTS_TXDONE + --UART_INTSTS_RXPE + --UART_INTSTS_RXOV + --UART_INTSTS_TXOV + --UART_INTSTS_RX + * @retval None + */ +void UART_ClearINTStatus(UART_TypeDef *UARTx, uint32_t INTMask) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_INTFLAGC(INTMask)); + + UARTx->INTSTS = INTMask; +} + +/** + * @brief Load send data register. + * @param UARTx: UART0~USART5 + DAT: data to send. + * @retval None + */ +void UART_SendData(UART_TypeDef *UARTx, uint8_t ch) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + UARTx->DATA = ch; +} + +/** + * @brief Read receive data register. + * @param UARTx: UART0~UART5 + * @retval The received data. + */ +uint8_t UART_ReceiveData(UART_TypeDef *UARTx) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + return UARTx->DATA; +} + +/** + * @brief UART Baudrate control. + * @param UARTx: UART0~UART5 + BaudRate: Baudrate value + * @retval None + */ +void UART_BaudrateConfig(UART_TypeDef *UARTx, uint32_t BaudRate) +{ + uint32_t pclk; + uint32_t div; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_BAUDRATE(BaudRate)); + + pclk = CLK_GetPCLKFreq(); + div = pclk/BaudRate; + if ((pclk%BaudRate) > (BaudRate/2)) + { + div++; + } + + UARTx->BAUDDIV = div; +} + +/** + * @brief UART Transmit/Receive enable control. + * @param UARTx: UART0~UART5 + Mode: + UART_MODE_RX + UART_MODE_TX + NewState: + ENABLE + DISABLE + * @retval None + */ +void UART_Cmd(UART_TypeDef *UARTx, uint32_t Mode, uint32_t NewState) +{ + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + assert_parameters(IS_UART_MODE(Mode)); + assert_parameters(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + UARTx->CTRL |= Mode; + } + else + { + UARTx->CTRL &= ~Mode; + } +} + +/** + * @brief Get UART configure information. + * @param UARTx: UART0~UART5 + * ConfigInfo: The pointer of UART configuration. + * @retval None + */ +void UART_GetConfigINFO(UART_TypeDef *UARTx, UART_ConfigINFOType *ConfigInfo) +{ + uint32_t tmp1, tmp2, tmp3; + uint32_t pclk; + + /* Check parameters */ + assert_parameters(IS_UART_ALL_INSTANCE(UARTx)); + + tmp1 = UARTx->CTRL; + tmp2 = UARTx->BAUDDIV; + pclk = CLK_GetPCLKFreq(); + tmp3 = UARTx->CTRL2; + + /* Mode_Transmit */ + if (tmp1 & UART_CTRL_TXEN) + ConfigInfo->Mode_Transmit = 1; + else + ConfigInfo->Mode_Transmit = 0; + + /* Mode_Receive */ + if (tmp1 & UART_CTRL_RXEN) + ConfigInfo->Mode_Receive = 1; + else + ConfigInfo->Mode_Receive = 0; + + /* Baudrate */ + ConfigInfo->Baudrate = pclk / tmp2; + + /* LSB/MSB */ + if (tmp3 & UART_CTRL2_MSB) + ConfigInfo->FirstBit = 1; + else + ConfigInfo->FirstBit = 0; + + /* WordLen */ + if (tmp3 & UART_CTRL2_MODE) + ConfigInfo->WordLen = 9; + else + ConfigInfo->WordLen = 8; + + /* Parity */ + if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_0) + ConfigInfo->Parity = 0; + else if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_1) + ConfigInfo->Parity = 1; + else if ((tmp3 & UART_CTRL2_PMODE) == UART_CTRL2_PMODE_EVEN) + ConfigInfo->Parity = 2; + else + ConfigInfo->Parity = 3; +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_version.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_version.c new file mode 100644 index 0000000000..5f24015193 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_version.c @@ -0,0 +1,25 @@ +/** +******************************************************************************* + * @file lib_version.c + * @author Application Team + * @version V4.5.0 + * @date 2019-05-14 + * @brief Version library. +*******************************************************************************/ +#include "lib_version.h" + +#define Target_DriveVersion DRIVER_VERSION(4, 7) + +/** + * @brief Get Target driver's current version. + * @param None + * @retval Version value + * Bit[15:8] : Major version + * Bit[7:0] : Minor version + */ +uint16_t Target_GetDriveVersion(void) +{ + return (Target_DriveVersion); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_wdt.c b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_wdt.c new file mode 100644 index 0000000000..94d58e9034 --- /dev/null +++ b/bsp/Vango_V85xx/Libraries/VangoV85xx_standard_peripheral/Source/lib_wdt.c @@ -0,0 +1,88 @@ +/** + ****************************************************************************** + * @file lib_wdt.c + * @author Application Team + * @version V4.4.0 + * @date 2018-09-27 + * @brief WDT library. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ +#include "lib_wdt.h" + +#define WDTPASS_KEY 0xAA5555AA +#define WDTCLR_KEY 0x55AAAA55 + +/** + * @brief Enable WDT timer. + * @param None + * @retval None + */ +void WDT_Enable(void) +{ + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN |= PMU_WDTEN_WDTEN; + + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN |= PMU_WDTEN_WDTEN; +} + +/** + * @brief Disable WDT timer. + * @param None + * @retval None + */ +void WDT_Disable(void) +{ + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN &= ~PMU_WDTEN_WDTEN; + + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN &= ~PMU_WDTEN_WDTEN; +} + +/** + * @brief Clear WDT counter. + * @param None + * @retval None + */ +void WDT_Clear(void) +{ + PMU->WDTCLR = WDTCLR_KEY; +} + +/** + * @brief Set WDT counting period. + * @param counting period: + WDT_2_SECS + WDT_1_SECS + WDT_0_5_SECS + WDT_0_25_SECS + * @retval None + */ +void WDT_SetPeriod(uint32_t period) +{ + uint32_t tmp; + + assert_parameters(IS_WDT_PERIOD(period)); + + tmp = PMU->WDTEN; + tmp &= ~PMU_WDTEN_WDTSEL; + tmp |= period; + PMU->WDTPASS = WDTPASS_KEY; + PMU->WDTEN = tmp; +} + +/** + * @brief Get WDT counter value. + * @param None + * @retval current counter value. + */ +uint16_t WDT_GetCounterValue(void) +{ + return (PMU->WDTCLR & PMU_WDTCLR_WDTCNT); +} + +/*********************************** END OF FILE ******************************/ diff --git a/bsp/Vango_V85xx/README.md b/bsp/Vango_V85xx/README.md new file mode 100644 index 0000000000..6790ed6af4 --- /dev/null +++ b/bsp/Vango_V85xx/README.md @@ -0,0 +1,77 @@ +# VANGOV85XX-EVAL + +## 简介 + +VANGOV85XX-EVAL是-æ­å·žä¸‡é«˜ç§‘技推出的一款基于V85XX的评估æ¿ï¼Œæ¿è½½èµ„æºä¸»è¦å¦‚下： + +| 硬件 | æè¿° | +| --------- | ------------- | +| èŠ¯ç‰‡åž‹å· | V8530 | +| CPU | ARM Cortex M0 | +| 主频 | 26M | +| 片内SRAM | 32K | +| 片内FLASH | 256K | + +## æ•°æ®æ‰‹å†Œ + +[产å“页é¢](http://www.vangotech.com/product.php?areas=0&bigs=1&smalls=4&id=14) +[datasheet](http://www.vangotech.com/uploadpic/162798006058.pdf) + +## 编译说明 + +VANGOV85XX-EVALæ¿çº§åŒ…支æŒMDK4﹑MDK5﹑IARå¼€å‘环境和GCC编译器，以下是具体版本信æ¯ï¼š + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------------------------- | +| GCC |gcc version 6.2.1 20161205 (release) | + +## 烧写åŠæ‰§è¡Œ + +供电方å¼ï¼šå¼€å‘æ¿ä½¿ç”¨ USB TypeA 接å£æˆ–者 DC-005 连接器æä¾› 5V 电æºã€‚ + +下载程åºï¼šä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿éœ€è¦ä¸€å¥— JLink 或者使用 SD612 工具。 + +串å£è¿žæŽ¥ï¼šä½¿ç”¨ä¸²å£çº¿è¿žæŽ¥åˆ°COM1(UART0)，或者使用USB转TTL模å—连接PA9(MCU TX)å’ŒPA10(MCU RX)。 + +### è¿è¡Œç»“æžœ + +如果编译 & 烧写无误，当å¤ä½è®¾å¤‡åŽï¼Œä¼šåœ¨ä¸²å£ä¸Šçœ‹åˆ°RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Jan 4 2021 + 2006 - 2021 Copyright by rt-thread team +msh /> +``` +## 驱动支æŒæƒ…况åŠè®¡åˆ’ + +| 驱动 | 支æŒæƒ…况 | 备注 | +| --------- | -------- | :------------------------: | +| UART | æ”¯æŒ | UART0~4 | +| GPIO | æ”¯æŒ | GPIOB~F | +| ADC | æœªæ”¯æŒ | ADC0~7 | +| HWTIMER | æœªæ”¯æŒ | TIMER0~3 | +| RTC | æœªæ”¯æŒ | RTC | +| WDT | æœªæ”¯æŒ | Free watchdog timer | +| IIC | æœªæ”¯æŒ | I2C0 | +| SPI | æœªæ”¯æŒ | SPI0~1 | +| LCD | æœªæ”¯æŒ | | +| SDRAM | æœªæ”¯æŒ | | +| SPI FLASH | æœªæ”¯æŒ | | + +### IO在æ¿çº§æ”¯æŒåŒ…中的映射情况 + +| IOå· | æ¿çº§åŒ…中的定义 | +| ---- | -------------- | +| PC0 | LED1 | +| PC2 | LED2 | +| PE0 | LED3 | +| PE1 | LED4 | +| PA0 | KEY1 | +| PC13 | KEY2 | +| PB14 | KEY3 | + +## è”ç³»äººä¿¡æ¯ + +维护人：[idk500](https://github.com/idk500) diff --git a/bsp/Vango_V85xx/SConscript b/bsp/Vango_V85xx/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/Vango_V85xx/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/Vango_V85xx/SConstruct b/bsp/Vango_V85xx/SConstruct new file mode 100644 index 0000000000..8925090c6c --- /dev/null +++ b/bsp/Vango_V85xx/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread-VangoV85xx.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/Vango_V85xx/Target_FLASH.icf b/bsp/Vango_V85xx/Target_FLASH.icf new file mode 100644 index 0000000000..f10a7cb75e --- /dev/null +++ b/bsp/Vango_V85xx/Target_FLASH.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __Reset_Handler_text_start__ = 0x000000C0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/Vango_V85xx/Target_FLASH.ld b/bsp/Vango_V85xx/Target_FLASH.ld new file mode 100644 index 0000000000..5e38d5bd02 --- /dev/null +++ b/bsp/Vango_V85xx/Target_FLASH.ld @@ -0,0 +1,173 @@ +/* +***************************************************************************** +** + +** File : Target_FLASH.ld +** +** Abstract : Linker script for Target Device with +** 256KByte FLASH, 32KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Date : 2019-01-07 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : AT(0) + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .chipinit_section : AT(0xC0) + { + . = ALIGN(4); + *(.chipinit_section) /* .text sections (code) */ + *(.chipinit_section*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/bsp/Vango_V85xx/Target_FLASH.sct b/bsp/Vango_V85xx/Target_FLASH.sct new file mode 100644 index 0000000000..4e38d9b280 --- /dev/null +++ b/bsp/Vango_V85xx/Target_FLASH.sct @@ -0,0 +1,17 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00010000 { ; load region size_region + ER_IROM1 0x00000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00002000 { ; RW data + lib_CodeRAM.o (+RO +ZI +RW) + .ANY (+RW +ZI) + } +} + diff --git a/bsp/Vango_V85xx/Vango.V85XX.4.0.2.pack b/bsp/Vango_V85xx/Vango.V85XX.4.0.2.pack new file mode 100644 index 0000000000..186df8a3f6 Binary files /dev/null and b/bsp/Vango_V85xx/Vango.V85XX.4.0.2.pack differ diff --git a/bsp/Vango_V85xx/applications/SConscript b/bsp/Vango_V85xx/applications/SConscript new file mode 100644 index 0000000000..ca2395451a --- /dev/null +++ b/bsp/Vango_V85xx/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/Vango_V85xx/applications/main.c b/bsp/Vango_V85xx/applications/main.c new file mode 100644 index 0000000000..c0926c341c --- /dev/null +++ b/bsp/Vango_V85xx/applications/main.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + */ + +#include +#include +#include +#include +#include +#include "board.h" + +#define LED1 GET_PIN(C, 0) + +int main(void) +{ + rt_pin_mode(LED1, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED1, PIN_LOW); + rt_thread_mdelay(500); + } + + return 0; +} + +#ifndef ASSERT_NDEBUG +/** + * @brief Reports the name of the source file and the source line number + * where the assert_errhandler error has occurred. + * @param file: pointer to the source file name + * @param line: assert_errhandler error line source number + * @retval None + */ +void assert_errhandler(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif diff --git a/bsp/Vango_V85xx/drivers/SConscript b/bsp/Vango_V85xx/drivers/SConscript new file mode 100644 index 0000000000..c6cf664e49 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/SConscript @@ -0,0 +1,38 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'drivers') + +# add the general drivers. +src = Split(""" +board.c +""") + +CPPPATH = [cwd] + +# add uart drivers. +if GetDepend('RT_USING_SERIAL'): + src += ['drv_usart.c'] + +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +if GetDepend('RT_USING_ADC'): + src += ['drv_adc.c'] + +if GetDepend('RT_USING_HWTIMER'): + src += ['drv_hwtimer.c'] + +if GetDepend('RT_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('RT_USING_WDT'): + src += ['drv_iwdt.c'] + +if GetDepend('RT_USING_SPI'): + src += ['drv_spi.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/Vango_V85xx/drivers/board.c b/bsp/Vango_V85xx/drivers/board.c new file mode 100644 index 0000000000..ca016a00df --- /dev/null +++ b/bsp/Vango_V85xx/drivers/board.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + * 2021-09-07 idk500 suit for Vango V85xx + * 2021-09-08 ZhuXW add delay function + */ + +#include +#include +#include + +#include +#include +#include + +/* + * System Clock Configuration + */ +void SystemClock_Config(void) +{ +// SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); + CLK_InitTypeDef CLK_Struct; + + CLK_Struct.ClockType = CLK_TYPE_AHBSRC \ + |CLK_TYPE_PLLL \ + |CLK_TYPE_HCLK \ + |CLK_TYPE_PCLK; + CLK_Struct.AHBSource = CLK_AHBSEL_LSPLL; + + CLK_Struct.PLLL.Frequency = CLK_PLLL_26_2144MHz; + CLK_Struct.PLLL.Source = CLK_PLLLSRC_XTALL; + CLK_Struct.PLLL.State = CLK_PLLL_ON; + CLK_Struct.HCLK.Divider = 1; + CLK_Struct.PCLK.Divider = 2; + CLK_ClockConfig(&CLK_Struct); +} + +/* + * This is the timer interrupt service routine. + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial V85xx board. + */ +void rt_hw_board_init() +{ + SystemClock_Config(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef BSP_USING_SDRAM + rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); +#else + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} +/*@}*/ diff --git a/bsp/Vango_V85xx/drivers/board.h b/bsp/Vango_V85xx/drivers/board.h new file mode 100644 index 0000000000..e8e312d110 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + * 2021-09-07 FuC Suit for Vango V85xx + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#include "drv_gpio.h" +#include "drv_spi.h" + +/* Internal SRAM memory size[Kbytes] <8-64>, Default: 32*/ +#define V85XX_SRAM_SIZE 32 +#define V85XX_SRAM_END (0x20000000 + V85XX_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END V85XX_SRAM_END + +/* #define DEBUG */ +#ifdef DEBUG +#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + +#endif diff --git a/bsp/Vango_V85xx/drivers/drv_comm.h b/bsp/Vango_V85xx/drivers/drv_comm.h new file mode 100644 index 0000000000..5aef53cce2 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_comm.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-28 iysheng first version + */ + +#ifndef __DRV_COMM_H__ +#define __DRV_COMM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_HWTIMER_H__ */ + diff --git a/bsp/Vango_V85xx/drivers/drv_gpio.c b/bsp/Vango_V85xx/drivers/drv_gpio.c new file mode 100644 index 0000000000..8c9f7bf6d3 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_gpio.c @@ -0,0 +1,447 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-27 iysheng first version + * 2021-01-01 iysheng support exti interrupt + * 2021-09-07 FuC Suit for Vango V85xx + * 2021-09-09 ZhuXW Add GPIO interrupt + */ + +#include +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#if defined(GPIOF) +#define __V85XX_PORT_MAX 6u +#elif defined(GPIOE) +#define __V85XX_PORT_MAX 5u +#elif defined(GPIOD) +#define __V85XX_PORT_MAX 4u +#elif defined(GPIOC) +#define __V85XX_PORT_MAX 3u +#elif defined(GPIOB) +#define __V85XX_PORT_MAX 2u +#elif defined(GPIOA) +#define __V85XX_PORT_MAX 1u +#else +#define __V85XX_PORT_MAX 0u +#error Unsupported V85XX GPIO peripheral. +#endif + +#define PIN_V85XXPORT_MAX __V85XX_PORT_MAX +#define PIN_V85XXPORT_A 0u + +static const struct pin_irq_map pin_irq_map[] = +{ +#if defined(SOC_SERIES_V85XX) + {GPIO_Pin_0, PMU_IRQn}, + {GPIO_Pin_1, PMU_IRQn}, + {GPIO_Pin_2, PMU_IRQn}, + {GPIO_Pin_3, PMU_IRQn}, + {GPIO_Pin_4, PMU_IRQn}, + {GPIO_Pin_5, PMU_IRQn}, + {GPIO_Pin_6, PMU_IRQn}, + {GPIO_Pin_7, PMU_IRQn}, + {GPIO_Pin_8, PMU_IRQn}, + {GPIO_Pin_9, PMU_IRQn}, + {GPIO_Pin_10, PMU_IRQn}, + {GPIO_Pin_11, PMU_IRQn}, + {GPIO_Pin_12, PMU_IRQn}, + {GPIO_Pin_13, PMU_IRQn}, + {GPIO_Pin_14, PMU_IRQn}, + {GPIO_Pin_15, PMU_IRQn}, +#else +#error "Unsupported soc series" +#endif +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static rt_base_t v85xx_pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 4) || (name_len >= 6)) + { + return -RT_EINVAL; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + return -RT_EINVAL; + } + + if ((name[1] >= 'A') && (name[1] <= 'F')) + { + hw_port_num = (int)(name[1] - 'A'); + } + else + { + return -RT_EINVAL; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; +} + +static void v85xx_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + + if (PIN_PORT(pin) == PIN_V85XXPORT_A) + { + gpio_pin = PIN_V85XXPIN(pin); + + GPIOA_WriteBit(GPIOA, gpio_pin, (BitState)value); + } + else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX) + { + gpio_port = PIN_V85XXPORT(pin); + gpio_pin = PIN_V85XXPIN(pin); + + GPIOBToF_WriteBit(gpio_port, gpio_pin, (BitState)value); + } +} + +static int v85xx_pin_read(rt_device_t dev, rt_base_t pin) +{ + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (PIN_PORT(pin) == PIN_V85XXPORT_A) + { + gpio_pin = PIN_V85XXPIN(pin); + value = GPIOA_ReadInputDataBit(GPIOA, gpio_pin); + } + else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX) + { + gpio_port = PIN_V85XXPORT(pin); + gpio_pin = PIN_V85XXPIN(pin); + value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin); + } + + return value; +} + +static void v85xx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + GPIO_InitType GPIO_InitStruct = {0}; + + if (PIN_PORT(pin) >= PIN_V85XXPORT_MAX) + { + return; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin); + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT; + + switch (mode) + { + case PIN_MODE_OUTPUT: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUTPUT_CMOS; + break; + case PIN_MODE_INPUT: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT; + break; + case PIN_MODE_INPUT_PULLUP: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_CMOS; + break; + case PIN_MODE_INPUT_PULLDOWN: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_OD; + break; + case PIN_MODE_OUTPUT_OD: + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INOUT_OD; + break; + default: + break; + } + + if (PIN_PORT(pin) == PIN_V85XXPORT_A) + { + GPIOA_Init(GPIOA, &GPIO_InitStruct); + } + else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX) + { + GPIOBToF_Init(PIN_V85XXPORT(pin), &GPIO_InitStruct); + } +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + + +static rt_err_t v85xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) > PIN_V85XXPORT_A) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_V85XXPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +static rt_err_t v85xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) > PIN_V85XXPORT_A) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_V85XXPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +static rt_err_t v85xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitType GPIO_InitStruct = {0}; + + if (PIN_PORT(pin) > PIN_V85XXPORT_A) + { + return -RT_ENOSYS; + } + + GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin); + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(PIN_V85XXPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT; + GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin); + GPIOA_Init(GPIOA, &GPIO_InitStruct); + + irqmap = &pin_irq_map[irqindex]; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_RISING); + break; + case PIN_IRQ_MODE_FALLING: + PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_FALLING); + break; + case PIN_IRQ_MODE_RISING_FALLING: + PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_EDGEBOTH); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_HIGH); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_LOW); + break; + default: + break; + } + PMU_INTConfig(PMU_INT_IOAEN, ENABLE); + + NVIC_SetPriority(irqmap->irqno, 0); + NVIC_EnableIRQ(irqmap->irqno); + pin_irq_enable_mask |= irqmap->pinbit; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + + level = rt_hw_interrupt_disable(); + + PMU_INTConfig(PMU_INT_IOAEN, DISABLE); + + NVIC_DisableIRQ(irqmap->irqno); + + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + return RT_EOK; +} + + + +const static struct rt_pin_ops _v85xx_pin_ops = +{ + v85xx_pin_mode, + v85xx_pin_write, + v85xx_pin_read, + v85xx_pin_attach_irq, + v85xx_pin_detach_irq, + v85xx_pin_irq_enable, + v85xx_pin_get, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + + +void v85xx_pin_exti_irqhandler() +{ + rt_base_t intsts=0; + int i=0; + + intsts = PMU_GetIOAAllINTStatus(); + for(i=0; i<16; i++) + { + if((1< +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __V85XX_PORT(port) GPIO##port##_BASE + +#define GET_PIN(PORTx,PIN) (__V85XX_PORT(PORTx)==GPIOA_BASE) ? (rt_base_t)(0 + PIN):(rt_base_t)((16 * ( ((rt_base_t)__V85XX_PORT(PORTx) - (rt_base_t)GPIOB_BASE)/(0x0400UL) +1)) + PIN) + +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_V85XXPORT(pin) ((GPIO_TypeDef *)(GPIOB_BASE + (0x400u * PIN_PORT(pin)))) +#define PIN_V85XXPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/Vango_V85xx/drivers/drv_spi.c b/bsp/Vango_V85xx/drivers/drv_spi.c new file mode 100644 index 0000000000..ce0e5bd87d --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_spi.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-06-05 tanek first implementation. + * 2018-04-19 misonyo Porting for v85xxf30x + * 2019-03-31 xuzhuoyi Porting for v85xxe230 + * 2021-09-21 zhuxw Porting for v85xx + */ + +#include "drv_spi.h" +#include "board.h" +#include + +#if defined(RT_USING_SPI) && defined(RT_USING_PIN) +#include + +#if !defined(RT_USING_SPI1) && !defined(RT_USING_SPI2) +#error "Please define at least one SPIx" +#endif + +/* private rt-thread spi ops function */ +static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); +static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); + +static struct rt_spi_ops v85xx_spi_ops = +{ + configure, + xfer +}; + +static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) +{ + SPI_InitType spi_init_struct; + + rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + if(configuration->data_width > 8) + { + return RT_EIO; + } + + { + rt_uint32_t spi_apb_clock; + rt_uint32_t max_hz; + + max_hz = configuration->max_hz; + + spi_apb_clock = CLK_GetPCLKFreq(); + + if(max_hz >= spi_apb_clock/2) + { + spi_init_struct.ClockDivision = SPI_CLKDIV_2; + } + else if (max_hz >= spi_apb_clock/4) + { + spi_init_struct.ClockDivision = SPI_CLKDIV_4; + } + else if (max_hz >= spi_apb_clock/8) + { + spi_init_struct.ClockDivision = SPI_CLKDIV_8; + } + else if (max_hz >= spi_apb_clock/16) + { + spi_init_struct.ClockDivision = SPI_CLKDIV_16; + } + else if (max_hz >= spi_apb_clock/32) + { + spi_init_struct.ClockDivision = SPI_CLKDIV_32; + } + else if (max_hz >= spi_apb_clock/64) + { + spi_init_struct.ClockDivision = SPI_CLKDIV_64; + } + else + { + /* min prescaler 128 */ + spi_init_struct.ClockDivision = SPI_CLKDIV_128; + } + } /* baudrate */ + + switch(configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + spi_init_struct.SPH = SPI_SPH_0; + spi_init_struct.SPO = SPI_SPO_0; + break; + case RT_SPI_MODE_1: + spi_init_struct.SPH = SPI_SPH_1; + spi_init_struct.SPO = SPI_SPO_0; + break; + case RT_SPI_MODE_2: + spi_init_struct.SPH = SPI_SPH_0; + spi_init_struct.SPO = SPI_SPO_1; + break; + case RT_SPI_MODE_3: + spi_init_struct.SPH = SPI_SPH_1; + spi_init_struct.SPO = SPI_SPO_1; + break; + } + + if(!(configuration->mode & RT_SPI_MSB)) + { + return RT_EIO; + } + + spi_init_struct.Mode = SPI_MODE_MASTER; + spi_init_struct.CSNSoft = SPI_CSNSOFT_ENABLE; + + SPI_Init((SPI_TypeDef*)spi_periph, &spi_init_struct); + + SPI_Cmd((SPI_TypeDef*)spi_periph, ENABLE); + + return RT_EOK; +}; + +static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) +{ + rt_base_t v85xx_cs_pin = (rt_base_t)device->parent.user_data; + rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; + struct rt_spi_configuration * config = &device->config; + + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + + /* take CS */ + if(message->cs_take) + { + rt_pin_write(v85xx_cs_pin, PIN_LOW); + DEBUG_PRINTF("spi take cs\n"); + } + + { + if(config->data_width <= 8) + { + const rt_uint8_t * send_ptr = message->send_buf; + rt_uint8_t * recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + DEBUG_PRINTF("spi poll transfer start: %d\n", size); + + while(size--) + { + rt_uint8_t data = 0xFF; + + if(send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + //Wait until the transmit buffer is empty + while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_TXEMPTY)); + // Send the byte + SPI_SendData((SPI_TypeDef*)spi_periph, data); + + //Wait until a data is received + while(RESET == SPI_GetStatus((SPI_TypeDef*)spi_periph, SPI_STS_RNE)); + // Get the received data + data = SPI_ReceiveData((SPI_TypeDef*)spi_periph); + + if(recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + DEBUG_PRINTF("spi poll transfer finsh\n"); + } + } + + /* release CS */ + if(message->cs_release) + { + rt_pin_write(v85xx_cs_pin, PIN_HIGH); + DEBUG_PRINTF("spi release cs\n"); + } + + return message->length; +}; + +int v85xx_hw_spi_init(void) +{ + int result = 0; +#ifdef RT_USING_SPI1 + static struct rt_spi_bus spi_bus0; + spi_bus0.parent.user_data = (void *)SPI1; + + result = rt_spi_bus_register(&spi_bus0, "spi1", &v85xx_spi_ops); + +#endif + +#ifdef RT_USING_SPI2 + static struct rt_spi_bus spi_bus1; + spi_bus1.parent.user_data = (void *)SPI2; + + result = rt_spi_bus_register(&spi_bus1, "spi2", &v85xx_spi_ops); + +#endif + return result; +} +INIT_BOARD_EXPORT(v85xx_hw_spi_init); +#endif diff --git a/bsp/Vango_V85xx/drivers/drv_spi.h b/bsp/Vango_V85xx/drivers/drv_spi.h new file mode 100644 index 0000000000..438fcb8878 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_spi.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-01 aozima first implementation. + * 2021-09-21 zhuxw add vango v85xx spi drivers + * + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + + +#endif // __DRV_SPI_H__ diff --git a/bsp/Vango_V85xx/drivers/drv_usart.c b/bsp/Vango_V85xx/drivers/drv_usart.c new file mode 100644 index 0000000000..52801b77a3 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_usart.c @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + * 2021-09-07 FuC Suit for Vango V85XX + * 2021·09-12 ZhuXW fix UART5 + */ + +#include +#include +#include + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \ + !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) + #error "Please define at least one UARTx" + +#endif + +#include + +static void uart_isr(struct rt_serial_device *serial); + +#if defined(BSP_USING_UART0) +struct rt_serial_device serial0; + +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial0); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +struct rt_serial_device serial1; + +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +struct rt_serial_device serial2; + +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +struct rt_serial_device serial3; + +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial3); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +struct rt_serial_device serial4; + +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial4); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +struct rt_serial_device serial5; + +void UART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial5); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +static const struct V85xx_uart uarts[] = +{ +#ifdef BSP_USING_UART0 + { + UART0, /* uart peripheral index */ + UART0_IRQn, /* uart iqrn */ + &serial0, + "uart0", + }, +#endif + +#ifdef BSP_USING_UART1 + { + UART1, /* uart peripheral index */ + UART1_IRQn, /* uart iqrn */ + &serial1, + "uart1", + }, +#endif + +#ifdef BSP_USING_UART2 + { + UART2, /* uart peripheral index */ + UART2_IRQn, /* uart iqrn */ + &serial2, + "uart2", + }, +#endif + +#ifdef BSP_USING_UART3 + { + UART3, /* uart peripheral index */ + UART3_IRQn, /* uart iqrn */ + &serial3, + "uart3", + }, +#endif + +#ifdef BSP_USING_UART4 + { + UART4, /* uart peripheral index */ + UART4_IRQn, /* uart iqrn */ + &serial4, + "uart4", + }, +#endif + +#ifdef BSP_USING_UART5 + { + UART5, /* uart peripheral index */ + UART5_IRQn, /* uart iqrn */ + &serial5, + "uart5", + }, +#endif +}; + +static rt_err_t V85xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct V85xx_uart *uart; + UART_TypeDef *UARTx; + UART_InitType UART_InitParaStruct = {0}; + + UART_StructInit(&UART_InitParaStruct); + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = (struct V85xx_uart *)serial->parent.user_data; + + UARTx = (UART_TypeDef *)uart->uart_periph; + UART_InitParaStruct.Baudrate = cfg->baud_rate; + + switch (cfg->data_bits) + { + case DATA_BITS_9: + UART_InitParaStruct.WordLen = UART_WORDLEN_9B; + break; + + default: + UART_InitParaStruct.WordLen = UART_WORDLEN_8B; + break; + } + + switch (cfg->parity) + { + case PARITY_ODD: + UART_InitParaStruct.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + UART_InitParaStruct.Parity = UART_PARITY_EVEN; + break; + default: + UART_InitParaStruct.Parity = UART_PARITY_NONE; + break; + } + + UART_InitParaStruct.Mode = UART_MODE_RX | UART_MODE_TX; + UART_Init(UARTx, &UART_InitParaStruct); + UART_Cmd(UARTx, UART_InitParaStruct.Mode, ENABLE); + + return RT_EOK; +} + +static rt_err_t V85xx_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct V85xx_uart *uart; + UART_TypeDef *UARTx; + + RT_ASSERT(serial != RT_NULL); + uart = (struct V85xx_uart *)serial->parent.user_data; + UARTx = (UART_TypeDef *)uart->uart_periph; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irqn); + /* disable interrupt */ + UART_INTConfig(UARTx, UART_INT_RX, DISABLE); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irqn); + /* enable interrupt */ + UART_INTConfig(UARTx, UART_INT_RX, ENABLE); + break; + } + + return RT_EOK; +} + +static int V85xx_putc(struct rt_serial_device *serial, char ch) +{ + struct V85xx_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct V85xx_uart *)serial->parent.user_data; + + UART_SendData((UART_TypeDef *)uart->uart_periph, ch); + while ((UART_GetFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_TXDONE) == RESET)); + UART_ClearFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_TXDONE); + return 1; +} + +static int V85xx_getc(struct rt_serial_device *serial) +{ + int ch; + struct V85xx_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct V85xx_uart *)serial->parent.user_data; + + ch = -1; + if (UART_GetFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_RXFULL) != RESET) + ch = UART_ReceiveData((UART_TypeDef *)uart->uart_periph); + return ch; +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) +{ + struct V85xx_uart *uart = (struct V85xx_uart *) serial->parent.user_data; + + RT_ASSERT(uart != RT_NULL); + + if ((UART_GetINTStatus((UART_TypeDef *)uart->uart_periph, UART_INTSTS_RX) != RESET) && + (UART_GetFlag((UART_TypeDef *)uart->uart_periph, UART_FLAG_RXFULL) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + /* Clear RXNE interrupt flag */ + UART_ClearINTStatus((UART_TypeDef *)uart->uart_periph, UART_INTSTS_RX); + } +} + +static const struct rt_uart_ops V85xx_uart_ops = +{ + V85xx_configure, + V85xx_control, + V85xx_putc, + V85xx_getc, +}; + +int V85xx_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + int i; + + + for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) + { + uarts[i].serial->ops = &V85xx_uart_ops; + uarts[i].serial->config = config; + + /* register UART device */ + rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void *)&uarts[i]); + } + + return 0; +} +INIT_BOARD_EXPORT(V85xx_hw_usart_init); +#endif diff --git a/bsp/Vango_V85xx/drivers/drv_usart.h b/bsp/Vango_V85xx/drivers/drv_usart.h new file mode 100644 index 0000000000..45dca3bfe1 --- /dev/null +++ b/bsp/Vango_V85xx/drivers/drv_usart.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-04 iysheng first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include + +/* V85XX uart driver */ +struct V85xx_uart { + UART_TypeDef * uart_periph; + IRQn_Type irqn; + + struct rt_serial_device *serial; + char *device_name; +}; + +#endif diff --git a/bsp/Vango_V85xx/project.uvoptx b/bsp/Vango_V85xx/project.uvoptx new file mode 100644 index 0000000000..6a1c508a66 --- /dev/null +++ b/bsp/Vango_V85xx/project.uvoptx @@ -0,0 +1,1324 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c + lib_dma.c + 0 + 0 + + + 9 + 88 + 1 + 0 + 0 + 0 + Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c + lib_uart.c + 0 + 0 + + + 9 + 89 + 1 + 0 + 0 + 0 + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c + lib_adc_tiny.c + 0 + 0 + + + 9 + 90 + 1 + 0 + 0 + 0 + Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c + lib_tmr.c + 0 + 0 + + + + diff --git a/bsp/Vango_V85xx/project.uvprojx b/bsp/Vango_V85xx/project.uvprojx new file mode 100644 index 0000000000..336e55e0eb --- /dev/null +++ b/bsp/Vango_V85xx/project.uvprojx @@ -0,0 +1,955 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + V85XX + Generic + Vango.V85XX.4.0.2 + IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM)) + 0 + $$Device:V85XX$Device\Include\V85XX.h + + + + + + + + + + $$Device:V85XX$SVD\V85XX.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + V85xx, USE_STDPERIPH_DRIVER, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, USE_TARGET_DRIVER, RT_USING_ARM_LIBC + + applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel;Libraries\CMSIS\Vango\V85xx\Include;Libraries\CMSIS;Libraries\VangoV85xx_standard_peripheral\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + board.c + 1 + drivers\board.c + + + drv_spi.c + 1 + drivers\drv_spi.c + + + + + Filesystem + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + finsh + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + Kernel + + + timer.c + 1 + ..\..\src\timer.c + + + irq.c + 1 + ..\..\src\irq.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + idle.c + 1 + ..\..\src\idle.c + + + clock.c + 1 + ..\..\src\clock.c + + + object.c + 1 + ..\..\src\object.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + device.c + 1 + ..\..\src\device.c + + + components.c + 1 + ..\..\src\components.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + thread.c + 1 + ..\..\src\thread.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + unistd.c + 1 + ..\..\components\libc\compilers\common\unistd.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + delay.c + 1 + ..\..\components\libc\compilers\common\delay.c + + + + + Vango_Lib + + + lib_adc.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc.c + + + lib_pmu.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_pmu.c + + + startup_target.S + 2 + Libraries\CMSIS\Vango\V85xx\Source\Keil5\startup_target.S + + + lib_LoadNVR.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\lib_LoadNVR.c + + + lib_ana.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_ana.c + + + lib_i2c.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_i2c.c + + + lib_version.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_version.c + + + lib_gpio.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_gpio.c + + + lib_u32k.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_u32k.c + + + lib_misc.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_misc.c + + + lib_wdt.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_wdt.c + + + lib_flash.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_flash.c + + + lib_spi.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_spi.c + + + lib_CodeRAM.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\lib_CodeRAM.c + + + lib_iso7816.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_iso7816.c + + + lib_pwm.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_pwm.c + + + lib_comp.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_comp.c + + + lib_rtc.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_rtc.c + + + system_target.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\system_target.c + + + lib_cortex.c + 1 + Libraries\CMSIS\Vango\V85xx\Source\lib_cortex.c + + + lib_clk.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_clk.c + + + lib_crypt.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_crypt.c + + + lib_lcd.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_lcd.c + + + lib_dma.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c + + + lib_uart.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c + + + lib_adc_tiny.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c + + + lib_tmr.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c + + + + + + + + + + + + + + diff --git a/bsp/Vango_V85xx/rtconfig.h b/bsp/Vango_V85xx/rtconfig.h new file mode 100644 index 0000000000..899ca6661a --- /dev/null +++ b/bsp/Vango_V85xx/rtconfig.h @@ -0,0 +1,185 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_SPI + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_SERIES_V85XX +#define SOC_V85XX + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART2 +#define RT_USING_SPI1 +#define RT_USING_SPI2 + +#endif diff --git a/bsp/Vango_V85xx/rtconfig.py b/bsp/Vango_V85xx/rtconfig.py new file mode 100644 index 0000000000..8302af0cf5 --- /dev/null +++ b/bsp/Vango_V85xx/rtconfig.py @@ -0,0 +1,126 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # tool-chains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-v85xx.map,-cref,-u,Reset_Handler -T Target_FLASH.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-v85xx.map --scatter Target_FLASH.sct' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + EXEC_PATH += '/ARM/ARMCC/bin' + print(EXEC_PATH) + + CFLAGS += ' --c99' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D VANGOV85XXDEV' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config Target_FLASH.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH += '/arm/bin/' + POST_ACTION = '' + diff --git a/bsp/Vango_V85xx/template.uvprojx b/bsp/Vango_V85xx/template.uvprojx new file mode 100644 index 0000000000..b26c9a0261 --- /dev/null +++ b/bsp/Vango_V85xx/template.uvprojx @@ -0,0 +1,393 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 0 + + + V85XX + Generic + Vango.V85XX.4.0.2 + IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM)) + 0 + $$Device:V85XX$Device\Include\V85XX.h + + + + + + + + + + $$Device:V85XX$SVD\V85XX.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/apm32/apm32f103xe-minibroard/.config b/bsp/apm32/apm32f103xe-minibroard/.config new file mode 100644 index 0000000000..495e6cd0d4 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/.config @@ -0,0 +1,375 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40001 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M3=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F1=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F103ZE=y + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_EEPROM is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SDIO is not set + +# +# Board extended module Drivers +# diff --git a/bsp/apm32/apm32f103xe-minibroard/.gitignore b/bsp/apm32/apm32f103xe-minibroard/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/apm32/apm32f103xe-minibroard/Kconfig b/bsp/apm32/apm32f103xe-minibroard/Kconfig new file mode 100644 index 0000000000..7a400db91f --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/apm32/apm32f103xe-minibroard/README.md b/bsp/apm32/apm32f103xe-minibroard/README.md new file mode 100644 index 0000000000..63f3df1030 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/README.md @@ -0,0 +1,84 @@ +# APM32F103ZE MINI BOARD BSP 说明 + +## 简介 + +本文档为 APM32F103ZE MINI å¼€å‘æ¿ï¼ˆMINI BOARD）的 BSP (æ¿çº§æ”¯æŒåŒ…) 说明。 + +主è¦å†…容如下： + +- å¼€å‘æ¿èµ„æºä»‹ç» +- BSP 快速上手 + +通过阅读快速上手章节开å‘者å¯ä»¥å¿«é€Ÿåœ°ä¸Šæ‰‹è¯¥ BSP，将 RT-Thread è¿è¡Œåœ¨å¼€å‘æ¿ä¸Šã€‚ + +## å¼€å‘æ¿ä»‹ç» + +APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接å£ï¼Œå¼•å‡ºäº†å…¨éƒ¨çš„IO。开å‘æ¿å¤–观如下图所示： + +![board](figures/APM32F103ZE.png) + + + +该开å‘æ¿å¸¸ç”¨ **æ¿è½½èµ„æº** 如下： + +- MCU：APM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM +- 外部 RAM：无 +- 外部 FLASH：无 +- 常用外设 + - LED：2个，（黄色，PE5/PE6） + - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13） +- 常用接å£ï¼šRS232转串å£ã€ã€USB SLAVE +- 调试接å£ï¼šæ ‡å‡† JTAG/SWD + + + +## å¤–è®¾æ”¯æŒ + +本 BSP ç›®å‰å¯¹å¤–设的支æŒæƒ…况如下： + +| **æ¿è½½å¤–设** | **支æŒæƒ…况** | **备注** | +| :----------- | :----------: | :------------------------------------ | +| RS232è½¬ä¸²å£ | æ”¯æŒ | 使用 UART1/ UART2(通过跳线选择) | +| **片上外设** | **支æŒæƒ…况** | **备注** | +| GPIO | æ”¯æŒ | PA0, PA1... PG15 ---> PIN: 0, 1...143 | +| UART | æ”¯æŒ | UART1/2 | + +## 使用说明 + +本章节是为刚接触 RT-Thread 的新手准备的使用说明，éµå¾ªç®€å•çš„步骤å³å¯å°† RT-Thread æ“作系统è¿è¡Œåœ¨è¯¥å¼€å‘æ¿ä¸Šï¼Œçœ‹åˆ°å®žéªŒæ•ˆæžœ 。 + + +### 快速上手 + +本 BSP 为开å‘者æä¾›MDK5 工程。下é¢ä»¥ MDK5 å¼€å‘环境为例，介ç»å¦‚何将系统è¿è¡Œèµ·æ¥ã€‚ + +#### 硬件连接 + +使用数æ®çº¿è¿žæŽ¥å¼€å‘æ¿åˆ° PC，打开电æºå¼€å…³ã€‚ + +#### 编译下载 + +åŒå‡» project.uvprojx 文件，打开 MDK5 工程，编译并下载程åºåˆ°å¼€å‘æ¿ã€‚ + +> 工程默认é…置使用 J-Link 仿真器下载程åºï¼Œåœ¨é€šè¿‡ J-Link 连接开å‘æ¿çš„基础上，点击下载按钮å³å¯ä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿ + +#### è¿è¡Œç»“æžœ + +下载程åºæˆåŠŸä¹‹åŽï¼Œç³»ç»Ÿä¼šè‡ªåŠ¨è¿è¡Œï¼ŒLED é—ªçƒ + +连接开å‘æ¿å¯¹åº”串å£åˆ° PC , 在终端工具里打开相应的串å£ï¼ˆ115200-8-1-N），å¤ä½è®¾å¤‡åŽï¼Œå¯ä»¥çœ‹åˆ° RT-Thread 的输出信æ¯: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Aug 20 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +## 注æ„事项 + +- å¯åœ¨æžæµ·å®˜æ–¹ç½‘站进行所需资料下载，如pack安装包和MINIå¼€å‘æ¿åŽŸç†å›¾ç­‰ï¼ˆwww.geehy.com）; + +## è”ç³»äººä¿¡æ¯ + +-[abbbcc ](https://gitee.com/abbbcc) \ No newline at end of file diff --git a/bsp/apm32/apm32f103xe-minibroard/SConscript b/bsp/apm32/apm32f103xe-minibroard/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/apm32/apm32f103xe-minibroard/SConstruct b/bsp/apm32/apm32f103xe-minibroard/SConstruct new file mode 100644 index 0000000000..c253622173 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +apm32_library = 'APM32F10x_Library' +rtconfig.BSP_LIBRARY_TYPE = apm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/apm32/apm32f103xe-minibroard/applications/SConscript b/bsp/apm32/apm32f103xe-minibroard/applications/SConscript new file mode 100644 index 0000000000..ca2395451a --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/apm32/apm32f103xe-minibroard/applications/main.c b/bsp/apm32/apm32f103xe-minibroard/applications/main.c new file mode 100644 index 0000000000..a592ea4f88 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include +#include +#include + +/* defined the LED2 pin: PE6 */ +#define LED2_PIN GET_PIN(E, 6) + +int main(void) +{ + /* set LED2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/apm32/apm32f103xe-minibroard/board/Kconfig b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig new file mode 100644 index 0000000000..3a7d4e1312 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig @@ -0,0 +1,32 @@ +menu "Hardware Drivers Config" + +config SOC_APM32F103ZE + bool + select SOC_SERIES_APM32F1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + endif + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +endmenu diff --git a/bsp/apm32/apm32f103xe-minibroard/board/SConscript b/bsp/apm32/apm32f103xe-minibroard/board/SConscript new file mode 100644 index 0000000000..f453b68f6a --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/SConscript @@ -0,0 +1,24 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s'] + +# You can select chips from the list above +CPPDEFINES = ['APM32F103xE'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.c b/bsp/apm32/apm32f103xe-minibroard/board/board.c new file mode 100644 index 0000000000..bec2c01cde --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include "board.h" + +void apm32_usart_init(void) +{ + GPIO_Config_T GPIO_ConfigStruct; + +#ifdef BSP_USING_UART1 + RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_USART1)); + + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; + GPIO_ConfigStruct.pin = GPIO_PIN_9; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; + GPIO_ConfigStruct.pin = GPIO_PIN_10; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif + +#ifdef BSP_USING_UART2 + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2); + + GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP; + GPIO_ConfigStruct.pin = GPIO_PIN_2; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); + + GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU; + GPIO_ConfigStruct.pin = GPIO_PIN_3; + GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz; + GPIO_Config(GPIOA, &GPIO_ConfigStruct); +#endif +} diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.h b/bsp/apm32/apm32f103xe-minibroard/board/board.h new file mode 100644 index 0000000000..da63a21995 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +#include "apm32f10x_gpio.h" +#include "apm32f10x_rcm.h" +#include "apm32f10x_misc.h" +#include "apm32f10x_rcm.h" +#include "apm32f10x_eint.h" +#include "apm32f10x_usart.h" + +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define APM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define APM32_FLASH_SIZE (512 * 1024) +#define APM32_FLASH_END_ADDRESS ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <6-128>, Default: 128 */ +#define APM32_SRAM_SIZE 128 +#define APM32_SRAM_END (0x20000000 + APM32_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END APM32_SRAM_END + +void SystemClock_Config(void); + +void apm32_usart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct new file mode 100644 index 0000000000..5f21bc4aa3 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct @@ -0,0 +1,17 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + + diff --git a/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png b/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png new file mode 100644 index 0000000000..de26f5f422 Binary files /dev/null and b/bsp/apm32/apm32f103xe-minibroard/figures/APM32F103ZE.png differ diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx new file mode 100644 index 0000000000..c10a97669c --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx @@ -0,0 +1,638 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + APM32F103ZE + Geehy + Geehy.APM32F1xx_DFP.1.0.7 + https://www.geehy.com/uploads/tool/ + IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)) + 0 + $$Device:APM32F103ZE$Device\Include\apm32f10x.h + + + + + + + + + + $$Device:APM32F103ZE$SVD\APM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_STDPERIPH_DRIVER, APM32F103xE, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m3\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + Drivers + + + startup_apm32f10x_hd.s + 2 + ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\ARM\startup_apm32f10x_hd.s + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + ..\libraries\Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\Drivers\drv_usart.c + + + drv_common.c + 1 + ..\libraries\Drivers\drv_common.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + idle.c + 1 + ..\..\..\src\idle.c + + + object.c + 1 + ..\..\..\src\object.c + + + components.c + 1 + ..\..\..\src\components.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + clock.c + 1 + ..\..\..\src\clock.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + device.c + 1 + ..\..\..\src\device.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + Libraries + + + system_apm32f10x.c + 1 + ..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c + + + apm32f10x_rcm.c + 1 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c + + + apm32f10x_misc.c + 1 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c + + + apm32f10x_usart.c + 1 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c + + + apm32f10x_eint.c + 1 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c + + + apm32f10x_gpio.c + 1 + ..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_gpio.c + + + + + + + + + + + + + + diff --git a/bsp/apm32/apm32f103xe-minibroard/rtconfig.h b/bsp/apm32/apm32f103xe-minibroard/rtconfig.h new file mode 100644 index 0000000000..8919e38851 --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/rtconfig.h @@ -0,0 +1,177 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40001 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M3 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_FAMILY_APM32 +#define SOC_SERIES_APM32F1 + +/* Hardware Drivers Config */ + +#define SOC_APM32F103ZE + +/* Onboard Peripheral Drivers */ + + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/apm32/apm32f103xe-minibroard/rtconfig.py b/bsp/apm32/apm32f103xe-minibroard/rtconfig.py new file mode 100644 index 0000000000..888e1566ba --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M3 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/apm32/apm32f103xe-minibroard/template.uvprojx b/bsp/apm32/apm32f103xe-minibroard/template.uvprojx new file mode 100644 index 0000000000..dee46dc63c --- /dev/null +++ b/bsp/apm32/apm32f103xe-minibroard/template.uvprojx @@ -0,0 +1,396 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + APM32F103ZE + Geehy + Geehy.APM32F1xx_DFP.1.0.7 + https://www.geehy.com/uploads/tool/ + IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)) + 0 + $$Device:APM32F103ZE$Device\Include\apm32f10x.h + + + + + + + + + + $$Device:APM32F103ZE$SVD\APM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h new file mode 100644 index 0000000000..8117944933 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h @@ -0,0 +1,332 @@ +/*! + * @file apm32f10x_adc.h + * + * @brief This file contains all the functions prototypes for the ADC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_ADC_H +#define __APM32F10X_ADC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup ADC_Enumerations Enumerations + @{ +*/ + +/** + * @brief ADC configuration Mode + */ +typedef enum +{ + ADC_MODE_INDEPENDENT = ((uint32_t)0x00000000), //!< Independent mode + ADC_MODE_REG_INJEC_SIMULT = ((uint32_t)0x00010000), //!< Combined regular simultaneous and injected simultaneous mode + ADC_MODE_REG_SIMULT_ALTER_TRIG = ((uint32_t)0x00020000), //!< Combined regular simultaneous and alternate trigger mode + ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), //!< Combined injected simultaneous and fast interleaved mode + ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), //!< Combined injected simultaneous and slow interleaved mode + ADC_MODE_INJEC_SIMULT = ((uint32_t)0x00050000), //!< Injected simultaneous mode + ADC_MODE_REG_SIMULT = ((uint32_t)0x00060000), //!< Regular simultaneous mode + ADC_MODE_FAST_INTERL = ((uint32_t)0x00070000), //!< Fast interleaved mode + ADC_MODE_SLOW_INTERL = ((uint32_t)0x00080000), //!< Slow interleaved mode + ADC_MODE_ALTER_TRIG = ((uint32_t)0x00090000) //!< Alternate trigger mode +} ADC_MODE_T; + +/** + * @brief ADC external trigger sources for regular channels conversion enumeration + */ +typedef enum +{ + ADC_EXT_TRIG_CONV_TMR1_CC1 = ((uint32_t)0x00000000), + ADC_EXT_TRIG_CONV_TMR1_CC2 = ((uint32_t)0x00020000), + ADC_EXT_TRIG_CONV_TMR2_CC2 = ((uint32_t)0x00060000), + ADC_EXT_TRIG_CONV_TMR3_TRGO = ((uint32_t)0x00080000), + ADC_EXT_TRIG_CONV_TMR4_CC4 = ((uint32_t)0x000A0000), + ADC_EXT_TRIG_CONV_EINT9_T8_TRGO = ((uint32_t)0x000C0000), + ADC_EXT_TRIG_CONV_TMR1_CC3 = ((uint32_t)0x00040000), + ADC_EXT_TRIG_CONV_None = ((uint32_t)0x000E0000), + + ADC_EXT_TRIG_CONV_TMR3_CC1 = ((uint32_t)0x00000000), + ADC_EXT_TRIG_CONV_TMR2_CC3 = ((uint32_t)0x00030000), + ADC_EXT_TRIG_CONV_TMR8_CC1 = ((uint32_t)0x00060000), + ADC_EXT_TRIG_CONV_TMR8_TRGO = ((uint32_t)0x00080000), + ADC_EXT_TRIG_CONV_TMR5_CC1 = ((uint32_t)0x000A0000), + ADC_EXT_TRIG_CONV_TMR5_CC3 = ((uint32_t)0x000C0000) +} ADC_EXT_TRIG_CONV_T; + +/** + * @brief ADC Data Align + */ +typedef enum +{ + ADC_DATA_ALIGN_RIGHT = 0x00000000, + ADC_DATA_ALIGN_LEFT = 0x00000800 +} ADC_DATA_ALIGN_T; + +/** + * @brief ADC Channels + */ +typedef enum +{ + ADC_CHANNEL_0 = ((uint8_t)0x00), + ADC_CHANNEL_1 = ((uint8_t)0x01), + ADC_CHANNEL_2 = ((uint8_t)0x02), + ADC_CHANNEL_3 = ((uint8_t)0x03), + ADC_CHANNEL_4 = ((uint8_t)0x04), + ADC_CHANNEL_5 = ((uint8_t)0x05), + ADC_CHANNEL_6 = ((uint8_t)0x06), + ADC_CHANNEL_7 = ((uint8_t)0x07), + ADC_CHANNEL_8 = ((uint8_t)0x08), + ADC_CHANNEL_9 = ((uint8_t)0x09), + ADC_CHANNEL_10 = ((uint8_t)0x0A), + ADC_CHANNEL_11 = ((uint8_t)0x0B), + ADC_CHANNEL_12 = ((uint8_t)0x0C), + ADC_CHANNEL_13 = ((uint8_t)0x0D), + ADC_CHANNEL_14 = ((uint8_t)0x0E), + ADC_CHANNEL_15 = ((uint8_t)0x0F), + ADC_CHANNEL_16 = ((uint8_t)0x10), + ADC_CHANNEL_TEMP_SENSOR = ((uint8_t)0x10), + ADC_CHANNEL_17 = ((uint8_t)0x11), + ADC_CHANNEL_V_REFINT = ((uint8_t)0x11) +} ADC_CHANNEL_T; + +/** + * @brief ADC Sampling Time + */ +typedef enum +{ + ADC_SAMPLE_TIME_1_5 = ((uint8_t)0x00), + ADC_SAMPLE_TIME_7_5 = ((uint8_t)0x01), + ADC_SAMPLE_TIME_13_5 = ((uint8_t)0x02), + ADC_SAMPLE_TIME_28_5 = ((uint8_t)0x03), + ADC_SAMPLE_TIME_41_5 = ((uint8_t)0x04), + ADC_SAMPLE_TIME_55_5 = ((uint8_t)0x05), + ADC_SAMPLE_TIME_71_5 = ((uint8_t)0x06), + ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07) +} ADC_SAMPLE_TIME_T; + +/** + * @brief ADC external trigger sources for injected channels conversion + */ +typedef enum +{ + /** for ADC1 and ADC2 */ + ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO = ((uint8_t)0x02), + ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1 = ((uint8_t)0x03), + ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4 = ((uint8_t)0x04), + ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO = ((uint8_t)0x05), + ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4 = ((uint8_t)0x06), + + /** for ADC1, ADC2 and ADC3 */ + ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO = ((uint8_t)0x00), + ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4 = ((uint8_t)0x01), + ADC_EXT_TRIG_INJEC_CONV_NONE = ((uint8_t)0x07), + + /** for ADC3 only */ + ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3 = ((uint8_t)0x02), + ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2 = ((uint8_t)0x03), + ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4 = ((uint8_t)0x04), + ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO = ((uint8_t)0x05), + ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4 = ((uint8_t)0x06) +} ADC_EXT_TRIG_INJEC_CONV_T; + +/** + * @brief ADC Injected channels + */ +typedef enum +{ + ADC_INJEC_CHANNEL_1 = ((uint8_t)0x14), + ADC_INJEC_CHANNEL_2 = ((uint8_t)0x18), + ADC_INJEC_CHANNEL_3 = ((uint8_t)0x1C), + ADC_INJEC_CHANNEL_4 = ((uint8_t)0x20) +} ADC_INJEC_CHANNEL_T; + +/** + * @brief ADC Analog Watchdog Selection + */ +typedef enum +{ + ADC_ANALOG_WATCHDOG_SINGLE_REG = ((uint32_t)0x00800200), + ADC_ANALOG_WATCHDOG_SINGLE_INJEC = ((uint32_t)0x00400200), + ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC = ((uint32_t)0x00C00200), + ADC_ANALOG_WATCHDOG_ALL_REG = ((uint32_t)0x00800000), + ADC_ANALOG_WATCHDOG_ALL_INJEC = ((uint32_t)0x00400000), + ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC = ((uint32_t)0x00C00000), + ADC_ANALOG_WATCHDOG_NONE = ((uint32_t)0x00000000) +} ADC_ANALOG_WATCHDOG_T; + +/** + * @brief ADC Interrupt definition + */ +typedef enum +{ + ADC_INT_AWD = ((uint16_t)0x0140), //!< Analog Watchdog interrupt + ADC_INT_EOC = ((uint16_t)0x0220), //!< End Of Conversion interrupt + ADC_INT_INJEOC = ((uint16_t)0x0480) //!< Injected Channel End Of Conversion interrupt +} ADC_INT_T; + +/** + * @brief ADC Flag + */ +typedef enum +{ + ADC_FLAG_AWD = ((uint8_t)0x01), //!< Analog Watchdog event occur flag + ADC_FLAG_EOC = ((uint8_t)0x02), //!< End Of Conversion flag + ADC_FLAG_INJEOC = ((uint8_t)0x04), //!< Injected Channel End Of Conversion flag + ADC_FLAG_INJCS = ((uint8_t)0x08), //!< Injected Channel Conversion Start flag + ADC_FLAG_REGCS = ((uint8_t)0x10) //!< Regular Channel Conversion Start flag +} ADC_FLAG_T; + +/**@} end of group ADC_Enumerations*/ + + +/** @addtogroup ADC_Macros Macros + @{ +*/ + +/** ADC_IJD Offset */ +#define INJDATA_OFFSET ((uint8_t)0x28) + +/** ADC_RDG register address */ +#define RDG_ADDRESS ((uint32_t)0x4001244C) + +/** INJSEQ register config */ +#define INJSEQ_SET_INJSEQC ((uint32_t)0x0000001F) +#define INJSEQ_SET_INJSEQLEN ((uint32_t)0x00300000) + +/** SMPTIM register SET */ +#define SMPCYCCFG_SET_SMPTIM1 ((uint32_t)0x00000007) +#define SMPCYCCFG_SET_SMPTIM2 ((uint32_t)0x00000007) + +/** REGSEQ register SET */ +#define REGSEQC_SET_REGSEQ3 ((uint32_t)0x0000001F) +#define REGSEQC_SET_REGSEQ2 ((uint32_t)0x0000001F) +#define REGSEQC_SET_REGSEQ1 ((uint32_t)0x0000001F) + +/**@} end of group ADC_Macros*/ + + +/** @addtogroup ADC_Structure Data Structure + @{ +*/ + +/** + * @brief ADC Config structure definition + */ +typedef struct +{ + ADC_MODE_T mode; + uint8_t scanConvMode; //!< This parameter can be ENABLE or DISABLE. + uint8_t continuosConvMode; //!< This parameter can be ENABLE or DISABLE. + ADC_EXT_TRIG_CONV_T externalTrigConv; + ADC_DATA_ALIGN_T dataAlign; + uint8_t nbrOfChannel; //!< This parameter must range from 1 to 16. +} ADC_Config_T; + +/**@} end of group ADC_Structure*/ + + +/** @addtogroup ADC_Fuctions Fuctions + @{ +*/ + +/** ADC reset and common configuration */ +void ADC_Reset(ADC_T* adc); +void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig); +void ADC_ConfigStructInit(ADC_Config_T* adcConfig); +void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime); +void ADC_Enable(ADC_T* adc); +void ADC_Disable(ADC_T* adc); + +/** ADC for DMA */ +void ADC_EnableDMA(ADC_T* adc); +void ADC_DisableDMA(ADC_T* adc); + +/** ADC Calibration */ +void ADC_ResetCalibration(ADC_T* adc); +uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc); +void ADC_StartCalibration(ADC_T* adc); +uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc); + +/** ADC software start conversion */ +void ADC_EnableSoftwareStartConv(ADC_T* adc); +void ADC_DisableSoftwareStartConv(ADC_T* adc); +uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc); + +/** ADC Discontinuous mode */ +void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number); +void ADC_EnableDiscMode(ADC_T* adc); +void ADC_DisableDiscMode(ADC_T* adc); + +/** ADC External trigger conversion */ +void ADC_EnableExternalTrigConv(ADC_T* adc); +void ADC_DisableExternalTrigConv(ADC_T* adc); + +/** ADC Conversion result */ +uint16_t ADC_ReadConversionValue(ADC_T* adc); +uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc); + +/** ADC Automatic injected group */ +void ADC_EnableInjectedConv(ADC_T* adc); +void ADC_DisableInjectedConv(ADC_T* adc); +void ADC_EnableInjectedDiscMode(ADC_T* adc); +void ADC_DisableInjectedDiscMode(ADC_T* adc); + +/** ADC External trigger for injected channels conversion */ +void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv); +void ADC_EnableExternalTrigInjectedConv(ADC_T* adc); +void ADC_DisableExternalTrigInjectedConv(ADC_T* adc); + +/** ADC Start of the injected channels conversion */ +void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc); +void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc); +uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc); + +/** ADC injected channel */ +void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length); +void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet); +uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel); + +/** ADC analog watchdog */ +void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog); +void ADC_DisableAnalogWatchdog(ADC_T* adc); +void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold); +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel); + +/** ADC temperature sensor */ +void ADC_EnableTempSensorVrefint(ADC_T* adc); +void ADC_DisableTempSensorVrefint(ADC_T* adc); + +/** Interrupt and flag */ +void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt); +void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt); +uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag); +void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag); +uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt); +void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt); + +/**@} end of group ADC_Fuctions*/ +/**@} end of group ADC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /** __APM32F10X_ADC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h new file mode 100644 index 0000000000..84b12b4fea --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h @@ -0,0 +1,135 @@ +/*! + * @file apm32f10x_bakr.h + * + * @brief This file contains all the functions prototypes for the BAKPR firmware library. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_BAKPR_H +#define __APM32F10X_BAKPR_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup BAKPR_Driver BAKPR Driver + @{ +*/ + +/** @addtogroup BAKPR_Enumerations Enumerations + @{ +*/ + +/** + * @brief BAKPR TAMPER Pin Active Level + */ +typedef enum +{ + BAKPR_TAMPER_PIN_LEVEL_HIGH, + BAKPR_TAMPER_PIN_LEVEL_LOW +} BAKPR_TAMPER_PIN_LEVEL_T; + +/** + * @brief BAKPR RTC output source + */ +typedef enum +{ + BAKPR_RTC_OUTPUT_SOURCE_NONE, + BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK, + BAKPR_RTC_OUTPUT_SOURCE_ALARM, + BAKPR_RTC_OUTPUT_SOURCE_SECOND +} BAKPR_RTC_OUTPUT_SOURCE_T; + +/** + * @brief BAKPR DATA register Addr + */ +typedef enum +{ + BAKPR_DATA1 = ((uint16_t)0x0004), + BAKPR_DATA2 = ((uint16_t)0x0008), + BAKPR_DATA3 = ((uint16_t)0x000C), + BAKPR_DATA4 = ((uint16_t)0x0010), + BAKPR_DATA5 = ((uint16_t)0x0014), + BAKPR_DATA6 = ((uint16_t)0x0018), + BAKPR_DATA7 = ((uint16_t)0x001C), + BAKPR_DATA8 = ((uint16_t)0x0020), + BAKPR_DATA9 = ((uint16_t)0x0024), + BAKPR_DATA10 = ((uint16_t)0x0028), + BAKPR_DATA11 = ((uint16_t)0x0040), + BAKPR_DATA12 = ((uint16_t)0x0044), + BAKPR_DATA13 = ((uint16_t)0x0048), + BAKPR_DATA14 = ((uint16_t)0x004C), + BAKPR_DATA15 = ((uint16_t)0x0050), + BAKPR_DATA16 = ((uint16_t)0x0054), + BAKPR_DATA17 = ((uint16_t)0x0058), + BAKPR_DATA18 = ((uint16_t)0x005C), + BAKPR_DATA19 = ((uint16_t)0x0060), + BAKPR_DATA20 = ((uint16_t)0x0064), + BAKPR_DATA21 = ((uint16_t)0x0068), + BAKPR_DATA22 = ((uint16_t)0x006C), + BAKPR_DATA23 = ((uint16_t)0x0070), + BAKPR_DATA24 = ((uint16_t)0x0074), + BAKPR_DATA25 = ((uint16_t)0x0078), + BAKPR_DATA26 = ((uint16_t)0x007C), + BAKPR_DATA27 = ((uint16_t)0x0080), + BAKPR_DATA28 = ((uint16_t)0x0084), + BAKPR_DATA29 = ((uint16_t)0x0088), + BAKPR_DATA30 = ((uint16_t)0x008C), + BAKPR_DATA31 = ((uint16_t)0x0090), + BAKPR_DATA32 = ((uint16_t)0x0094), + BAKPR_DATA33 = ((uint16_t)0x0098), + BAKPR_DATA34 = ((uint16_t)0x009C), + BAKPR_DATA35 = ((uint16_t)0x00A0), + BAKPR_DATA36 = ((uint16_t)0x00A4), + BAKPR_DATA37 = ((uint16_t)0x00A8), + BAKPR_DATA38 = ((uint16_t)0x00AC), + BAKPR_DATA39 = ((uint16_t)0x00B0), + BAKPR_DATA40 = ((uint16_t)0x00B4), + BAKPR_DATA41 = ((uint16_t)0x00B8), + BAKPR_DATA42 = ((uint16_t)0x00BC) +} BAKPR_DATA_T; + +/**@} end of group BAKPR_Enumerations*/ + + +/** @addtogroup BAKPR_Fuctions Fuctions + @{ +*/ + +/** BAKPR reset and configuration */ +void BAKPR_Reset(void); +void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value); +void BAKPR_EnableTamperPin(void); +void BAKPR_DisableTamperPin(void); +void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure); +void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue); +void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data); +uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData); + +/** Interrupts and flags */ +void BAKPR_EnableInterrupt(void); +void BAKPR_DisableInterrupt(void); +uint8_t BAKPR_ReadStatusFlag(void); +void BAKPR_ClearStatusFlag(void); +uint8_t BAKPR_ReadIntFlag(void); +void BAKPR_ClearIntFlag(void); + +/**@} end of group BAKPR_Fuctions*/ +/**@} end of group BAKPR_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_BAKPR_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h new file mode 100644 index 0000000000..766d1918e4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h @@ -0,0 +1,337 @@ +/*! + * @file apm32f10x_can.h + * + * @brief This file contains all the functions prototypes for the CAN firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_CAN_H +#define __APM32F10X_CAN_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_Enumerations Enumerations + @{ +*/ + +/** + * @brief CAN mode + */ +typedef enum +{ + CAN_MODE_NORMAL = ((uint8_t)00), //!< normal mode + CAN_MODE_LOOPBACK = ((uint8_t)01), //!< loopback mode + CAN_MODE_SILENT = ((uint8_t)02), //!< silent mode + CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03), //!< loopback combined with silent mode +} CAN_MODE_T; + +/** + * @brief CAN synchronisation jump width + */ +typedef enum +{ + CAN_SJW_1 = ((uint8_t)00), //!< 1 time quantum + CAN_SJW_2 = ((uint8_t)01), //!< 2 time quantum + CAN_SJW_3 = ((uint8_t)02), //!< 3 time quantum + CAN_SJW_4 = ((uint8_t)03) //!< 4 time quantum +} CAN_SJW_T; + +/** + * @brief CAN time quantum in bit segment 1 + */ +typedef enum +{ + CAN_TIME_SEGMENT1_1 = ((uint8_t)0x00), //!< 1 time quanta + CAN_TIME_SEGMENT1_2 = ((uint8_t)0x01), //!< 2 time quanta + CAN_TIME_SEGMENT1_3 = ((uint8_t)0x02), //!< 3 time quanta + CAN_TIME_SEGMENT1_4 = ((uint8_t)0x03), //!< 4 time quanta + CAN_TIME_SEGMENT1_5 = ((uint8_t)0x04), //!< 5 time quanta + CAN_TIME_SEGMENT1_6 = ((uint8_t)0x05), //!< 6 time quanta + CAN_TIME_SEGMENT1_7 = ((uint8_t)0x06), //!< 7 time quanta + CAN_TIME_SEGMENT1_8 = ((uint8_t)0x07), //!< 8 time quanta + CAN_TIME_SEGMENT1_9 = ((uint8_t)0x08), //!< 9 time quanta + CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09), //!< 10 time quanta + CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A), //!< 11 time quanta + CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B), //!< 12 time quanta + CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C), //!< 13 time quanta + CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D), //!< 14 time quanta + CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E), //!< 15 time quanta + CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F) //!< 16 time quanta +} CAN_TIME_SEGMENT1_T; + +/** + * @brief CAN time quantum in bit segment 2 + */ +typedef enum +{ + CAN_TIME_SEGMENT2_1 = (uint8_t)0x00, //!< 1 time quanta + CAN_TIME_SEGMENT2_2 = (uint8_t)0x01, //!< 2 time quanta + CAN_TIME_SEGMENT2_3 = (uint8_t)0x02, //!< 3 time quanta + CAN_TIME_SEGMENT2_4 = (uint8_t)0x03, //!< 4 time quanta + CAN_TIME_SEGMENT2_5 = (uint8_t)0x04, //!< 5 time quanta + CAN_TIME_SEGMENT2_6 = (uint8_t)0x05, //!< 6 time quanta + CAN_TIME_SEGMENT2_7 = (uint8_t)0x06, //!< 7 time quanta + CAN_TIME_SEGMENT2_8 = (uint8_t)0x07, //!< 8 time quanta +} CAN_TIME_SEGMENT2_T; + +/** + * @brief CAN filter FIFO + */ +typedef enum +{ + CAN_FILTER_FIFO_0 = ((uint8_t)0x00), //!< filter FIFO 0 + CAN_FILTER_FIFO_1 = ((uint8_t)0x01), //!< filter FIFO 1 +} CAN_FILTER_FIFO_T; + +/** + * @brief CAN filter mode + */ +typedef enum +{ + CAN_FILTER_MODE_IDMASK = ((uint8_t)00), //!< identifier/mask mode + CAN_FILTER_MODE_IDLIST = ((uint8_t)01) //!< identifier list mode +} CAN_FILTER_MODE_T; + +/** + * @brief CAN filter scale + */ +typedef enum +{ + CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters + CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), //!< One 32-bit filter +} CAN_FILTER_SCALE_T; + +/** + * @brief CAN identifier type + */ +typedef enum +{ + CAN_TYPEID_STD = ((uint32_t)0x00000000), //!< Standard Id + CAN_TYPEID_EXT = ((uint32_t)0x00000004) //!< Extended Id +} CAN_TYPEID_T; + +/** + * @brief CAN_remote_transmission_request + */ +typedef enum +{ + CAN_RTXR_DATA = ((uint32_t)0x00000000), //!< Data frame + CAN_RTXR_REMOTE = ((uint32_t)0x00000002) //!< Remote frame +} CAN_RTXR_T; + +/** + * @brief Mailboxes definition + */ +typedef enum +{ + CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0 + CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1 + CAN_TX_MAILBIX_2 = ((uint8_t)0x02), //!< Tx mailbox2 +} CAN_TX_MAILBIX_T; + +/** + * @brief CAN receive FIFO number constants + */ +typedef enum +{ + CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0 + CAN_RX_FIFO_1 = ((uint8_t)0x01), //!< receive FIFO 1 +} CAN_RX_FIFO_T; + +/** + * @brief CAN Operating Mode + */ +typedef enum +{ + CAN_OPERATING_MODE_INIT = ((uint8_t)00), //!< Initialization mode + CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), //!< Normal mode + CAN_OPERATING_MODE_SLEEP = ((uint8_t)02), //!< sleep mode +} CAN_OPERATING_MODE_T; + +/** + * @brief CAN Interrupts + */ +typedef enum +{ + CAN_INT_TXME = ((uint32_t)0x00000001), //!< Transmit mailbox empty Interrupt + CAN_INT_F0MP = ((uint32_t)0x00000002), //!< FIFO 0 message pending Interrupt + CAN_INT_F0FULL = ((uint32_t)0x00000004), //!< FIFO 0 full Interrupt + CAN_INT_F0OVR = ((uint32_t)0x00000008), //!< FIFO 0 overrun Interrupt + CAN_INT_F1MP = ((uint32_t)0x00000010), //!< FIFO 1 message pending Interrupt + CAN_INT_F1FULL = ((uint32_t)0x00000020), //!< FIFO 1 full Interrupt + CAN_INT_F1OVR = ((uint32_t)0x00000040), //!< FIFO 1 overrun Interrupt + CAN_INT_ERRW = ((uint32_t)0x00000100), //!< Error warning Interrupt + CAN_INT_ERRP = ((uint32_t)0x00000200), //!< Error passive Interrupt + CAN_INT_BOF = ((uint32_t)0x00000400), //!< Bus-off Interrupt + CAN_INT_LEC = ((uint32_t)0x00000800), //!< Last error record code Interrupt + CAN_INT_ERR = ((uint32_t)0x00008000), //!< Error Interrupt + CAN_INT_WUP = ((uint32_t)0x00010000), //!< Wake-up Interrupt + CAN_INT_SLEEP = ((uint32_t)0x00020000) //!< Sleep acknowledge Interrupt +} CAN_INT_T; + +/** + * @brief CAN Flags + */ +typedef enum +{ + /** Error flag*/ + CAN_FLAG_ERRW = ((uint32_t)0x10F00001), //!< Error Warning Flag + CAN_FLAG_ERRP = ((uint32_t)0x10F00002), //!< Error Passive Flag + CAN_FLAG_BOF = ((uint32_t)0x10F00004), //!< Bus-Off Flag + CAN_FLAG_LERRC = ((uint32_t)0x30F00070), //!< Last error record code Flag + /** Operating Mode Flags */ + CAN_FLAG_WUPI = ((uint32_t)0x31000008), //!< Wake up Flag + CAN_FLAG_SLEEP = ((uint32_t)0x31000012), //!< Sleep acknowledge Flag + /** Receive Flags */ + CAN_FLAG_F0MP = ((uint32_t)0x12000003), //!< FIFO 0 Message Pending Flag + CAN_FLAG_F0FULL = ((uint32_t)0x32000008), //!< FIFO 0 Full Flag + CAN_FLAG_F0OVR = ((uint32_t)0x32000010), //!< FIFO 0 Overrun Flag + CAN_FLAG_F1MP = ((uint32_t)0x14000003), //!< FIFO 1 Message Pending Flag + CAN_FLAG_F1FULL = ((uint32_t)0x34000008), //!< FIFO 1 Full Flag + CAN_FLAG_F1OVR = ((uint32_t)0x34000010), //!< FIFO 1 Overrun Flag + /** Transmit Flags */ + CAN_FLAG_REQC0 = ((uint32_t)0x38000001), //!< Request MailBox0 Flag + CAN_FLAG_REQC1 = ((uint32_t)0x38000100), //!< Request MailBox1 Flag + CAN_FLAG_REQC2 = ((uint32_t)0x38010000) //!< Request MailBox2 Flag +} CAN_FLAG_T; + +/**@} end of group CAN_Enumerations*/ + + +/** + * @brief CAN Config structure definition + */ + +/** + * @brief CAN config structure definition + */ +typedef struct +{ + uint8_t timeTrigComMode; //!< Enable or disable the time triggered communication mode. + uint8_t autoBusOffManage; //!< Enable or disable the automatic bus-off management. + uint8_t autoWakeUpMode; //!< Enable or disable the automatic wake-up mode. + uint8_t nonAutoRetran; //!< Enable or disable the non-automatic retransmission mode. + uint8_t rxFIFOLockMode; //!< Enable or disable the Receive FIFO Locked mode. + uint8_t txFIFOPriority; //!< Enable or disable the transmit FIFO priority. + CAN_MODE_T mode; //!< Specifies the CAN operating mode. + CAN_SJW_T syncJumpWidth; /** Specifies the maximum number of time quanta the CAN hardware + * is allowed to lengthen or shorten a bit to perform resynchronization. + */ + CAN_TIME_SEGMENT1_T timeSegment1; //!< Specifies the number of time quanta in Bit Segment 1. + CAN_TIME_SEGMENT2_T timeSegment2; //!< Specifies the number of time quanta in Bit Segment 2. + uint16_t prescaler; //!< Specifies the length of a time quantum. It can be 1 to 1024. +} CAN_Config_T; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF. + uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. + CAN_TYPEID_T typeID; + CAN_RTXR_T remoteTxReq; + uint8_t dataLengthCode;//!< Specifies the data length code. It can be 0 to 8. + uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. +} CAN_TX_MESSAGE_T; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t stdID; //!< Specifies the standard identifier. It can be 0 to 0x7FF. + uint32_t extID; //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. + uint32_t typeID; + uint32_t remoteTxReq; + uint8_t dataLengthCode; //!< Specifies the data length code. It can be 0 to 8. + uint8_t data[8]; //!< Specifies the data to be transmitted. It can be 0 to 0xFF. + uint8_t filterMatchIndex;//!< Specifies the filter match index. It can be 0 to 0xFF. +} CAN_RX_MESSAGE_T; + +/** + * @brief CAN filter config structure definition + */ +typedef struct +{ + uint8_t filterNumber; //!< Specifies the filter number. It can be 0 to 13. + uint16_t filterIdHigh; //!< Specifies the filter identification number.It can be 0 to 0xFFFF. + uint16_t filterIdLow; //!< Specifies the filter identification number.It can be 0 to 0xFFFF. + uint16_t filterMaskIdHigh; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF. + uint16_t filterMaskIdLow; //!< Specifies the filter mask identification. It can be 0 to 0xFFFF. + uint16_t filterActivation; //!< Specifies the filter Activation. It can be ENABLE or DISABLE. + CAN_FILTER_FIFO_T filterFIFO; + CAN_FILTER_MODE_T filterMode; + CAN_FILTER_SCALE_T filterScale; +} CAN_FILTER_CONFIG_T; + +/**@} end of group CAN_Structure*/ + + +/** @addtogroup CAN_Fuctions Fuctions + @{ +*/ + +/** CAN reset and configuration */ +void CAN_Reset(CAN_T* can); +uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig); +void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig); +void CAN_ConfigStructInit(CAN_Config_T* canConfig); +void CAN_EnableDBGFreeze(CAN_T* can); +void CAN_DisableDBGFreeze(CAN_T* can); +void CAN_EnableTTCComMode(CAN_T* can); +void CAN_DisableTTCComMode(CAN_T* can); + +/** CAN frames transmit */ +uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage); +uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); +void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox); + +/** CAN frames receive */ +void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage); +void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber); +uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber); + +/** CAN operation modes */ +uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode); +uint8_t CAN_SleepMode(CAN_T* can); +uint8_t CAN_WakeUpMode(CAN_T* can); + +/** CAN bus error management */ +uint8_t CAN_ReadLastErrorCode(CAN_T* can); +uint8_t CAN_ReadRxErrorCounter(CAN_T* can); +uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can); + +/** CAN interrupt and flag */ +void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt); +void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt); +uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag); +void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag); +uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag); +void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag); + +/**@} end of group CAN_Fuctions*/ +/**@} end of group CAN_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_CAN_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h new file mode 100644 index 0000000000..c3a0098aee --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h @@ -0,0 +1,52 @@ +/*! + * @file apm32f10x_crc.h + * + * @brief This file contains all the functions prototypes for the CRC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_CRC_H +#define __APM32F10X_CRC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_Fuctions Fuctions + @{ +*/ + +/** Reset DATA */ +void CRC_ResetDATA(void); + +/** Operation functions */ +uint32_t CRC_CalculateCRC(uint32_t data); +uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen); +uint32_t CRC_ReadCRC(void); +void CRC_WriteIDRegister(uint8_t inData); +uint8_t CRC_ReadIDRegister(void); + +/**@} end of group CRC_Fuctions*/ +/**@} end of group CRC_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_CRC_H */ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h new file mode 100644 index 0000000000..1fce07ebc1 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h @@ -0,0 +1,181 @@ +/*! + * @file apm32f10x_dac.h + * + * @brief This file contains all the functions prototypes for the DAC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_DAC_H +#define __APM32F10X_DAC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_Enumerations Enumerations + @{ +*/ + +/** + * @brief DAC Channel selection + */ +typedef enum +{ + DAC_CHANNEL_1 = 0x00000000, + DAC_CHANNEL_2 = 0x00000010 +}DAC_CHANNEL_T; + +/** + * @brief DAC trigger selection + */ +typedef enum +{ + DAC_TRIGGER_NONE = 0x00000000, + DAC_TRIGGER_TMR6_TRGO = 0x00000004, + DAC_TRIGGER_TMR8_TRGO = 0x0000000C, + DAC_TRIGGER_TMR7_TRGO = 0x00000014, + DAC_TRIGGER_TMR5_TRGO = 0x0000001C, + DAC_TRIGGER_TMR2_TRGO = 0x00000024, + DAC_TRIGGER_TMR4_TRGO = 0x0000002C, + DAC_TRIGGER_EINT9 = 0x00000034, + DAC_TRIGGER_SOFT = 0x0000003C +}DAC_TRIGGER_T; + +/** + * @brief DAC wave generation + */ +typedef enum +{ + DAC_WAVE_GENERATION_NONE = 0x00000000, + DAC_WAVE_GENERATION_NOISE = 0x00000040, + DAC_WAVE_GENERATION_TRIANGLE = 0x00000080 +}DAC_WAVE_GENERATION_T; + +/** + * @brief DAC channelx mask/amplitude selector + */ +typedef enum +{ + DAC_LFSR_MASK_BIT11_1 = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_2 = 0x00001000, //!< Mask bit[11:2] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_3 = 0x00002000, //!< Mask bit[11:3] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_4 = 0x00003000, //!< Mask bit[11:4] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_5 = 0x00004000, //!< Mask bit[11:5] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_6 = 0x00005000, //!< Mask bit[11:6] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_7 = 0x00006000, //!< Mask bit[11:7] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_8 = 0x00007000, //!< Mask bit[11:8] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_9 = 0x00008000, //!< Mask bit[11:9] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11_10 = 0x00009000, //!< Mask bit[11:10] of LFSR for noise wave generation + DAC_LFSR_MASK_BIT11 = 0x0000A000, //!< Mask bit11 of LFSR for noise wave generation + DAC_LFSR_MASK_NONE = 0x0000B000, //!< Mask none bit of LFSR for noise wave generation + + DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000, //!< Triangle amplitude equal to 1 + DAC_TRIANGLE_AMPLITUDE_3 = 0x00001000, //!< Triangle amplitude equal to 3 + DAC_TRIANGLE_AMPLITUDE_7 = 0x00002000, //!< Triangle amplitude equal to 7 + DAC_TRIANGLE_AMPLITUDE_15 = 0x00003000, //!< Triangle amplitude equal to 15 + DAC_TRIANGLE_AMPLITUDE_31 = 0x00004000, //!< Triangle amplitude equal to 31 + DAC_TRIANGLE_AMPLITUDE_63 = 0x00005000, //!< Triangle amplitude equal to 63 + DAC_TRIANGLE_AMPLITUDE_127 = 0x00006000, //!< Triangle amplitude equal to 127 + DAC_TRIANGLE_AMPLITUDE_255 = 0x00007000, //!< Triangle amplitude equal to 255 + DAC_TRIANGLE_AMPLITUDE_511 = 0x00008000, //!< Triangle amplitude equal to 511 + DAC_TRIANGLE_AMPLITUDE_1023 = 0x00009000, //!< Triangle amplitude equal to 1023 + DAC_TRIANGLE_AMPLITUDE_2047 = 0x0000A000, //!< Triangle amplitude equal to 2047 + DAC_TRIANGLE_AMPLITUDE_4095 = 0x0000B000 //!< Triangle amplitude equal to 4095 +}DAC_MASK_AMPLITUDE_SEL_T; + +/** + * @brief DAC output buffer + */ +typedef enum +{ + DAC_OUTPUT_BUFFER_ENBALE = 0x00000000, + DAC_OUTPUT_BUFFER_DISABLE = 0x00000002 +}DAC_OUTPUT_BUFFER_T; + +/** + * @brief DAC data align + */ +typedef enum +{ + DAC_ALIGN_12BIT_R = 0x00000000, + DAC_ALIGN_12BIT_L = 0x00000004, + DAC_ALIGN_8BIT_R = 0x00000008 +}DAC_ALIGN_T; + +/**@} end of group DAC_Enumerations*/ + + +/** @addtogroup DAC_Structure Data Structure + @{ +*/ + +/** + * @brief DAC Config structure definition + */ +typedef struct +{ + DAC_TRIGGER_T trigger; + DAC_OUTPUT_BUFFER_T outputBuffer; + DAC_WAVE_GENERATION_T waveGeneration; + DAC_MASK_AMPLITUDE_SEL_T maskAmplitudeSelect; +}DAC_ConfigStruct_T; + +/**@} end of group DAC_Structure*/ + + +/** @addtogroup DAC_Fuctions Fuctions + @{ +*/ + +/** DAC Reset and Configuration */ +void DAC_Reset(void); +void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct); +void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct); +void DAC_Enable(DAC_CHANNEL_T channel); +void DAC_Disable(DAC_CHANNEL_T channel); + +/** DAC channel for DAM */ +void DAC_DMA_Enable(DAC_CHANNEL_T channel); +void DAC_DMA_Disable(DAC_CHANNEL_T channel); + +/** DAC channel software trigger */ +void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel); +void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel); +void DAC_EnableDualSoftwareTrigger(void); +void DAC_DisableDualSoftwareTrigger(void); + +/** DAC channel wave generation */ +void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); +void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave); + +/** DAC set channel data */ +void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data); +void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data); +void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1); + +/** DAC read data output value */ +uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel); + +/**@} end of group DAC_Fuctions*/ +/**@} end of group DAC_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DAC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h new file mode 100644 index 0000000000..193f86ffba --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h @@ -0,0 +1,83 @@ +/*! + * @file apm32f10x_dbgmcu.h + * + * @brief This file contains all the functions prototypes for the DBUGMCU firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_DBGMCU_H +#define __APM32F10X_DBGMCU_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DBGMCU_Driver DBGMCU Driver + @{ +*/ + +/** @addtogroup DBGMCU_Enumerations Enumerations + @{ +*/ + +enum +{ + DBGMCU_SLEEP = ((uint32_t)0x00000001), + DBGMCU_STOP = ((uint32_t)0x00000002), + DBGMCU_STANDBY = ((uint32_t)0x00000004), + DBGMCU_IWDT_STOP = ((uint32_t)0x00000100), + DBGMCU_WWDT_STOP = ((uint32_t)0x00000200), + DBGMCU_TMR1_STOP = ((uint32_t)0x00000400), + DBGMCU_TMR2_STOP = ((uint32_t)0x00000800), + DBGMCU_TMR3_STOP = ((uint32_t)0x00001000), + DBGMCU_TMR4_STOP = ((uint32_t)0x00002000), + DBGMCU_CAN1_STOP = ((uint32_t)0x00004000), + DBGMCU_I2C1_SMBUS_TIMEOUT = ((uint32_t)0x00008000), + DBGMCU_I2C2_SMBUS_TIMEOUT = ((uint32_t)0x00010000), + DBGMCU_TMR8_STOP = ((uint32_t)0x00020000), + DBGMCU_TMR5_STOP = ((uint32_t)0x00040000), + DBGMCU_TMR6_STOP = ((uint32_t)0x00080000), + DBGMCU_TMR7_STOP = ((uint32_t)0x00100000), + DBGMCU_CAN2_STOP = ((uint32_t)0x00200000), + DBGMCU_TMR15_STOP = ((uint32_t)0x00400000), + DBGMCU_TMR16_STOP = ((uint32_t)0x00800000), + DBGMCU_TMR17_STOP = ((uint32_t)0x01000000), + DBGMCU_TMR12_STOP = ((uint32_t)0x02000000), + DBGMCU_TMR13_STOP = ((uint32_t)0x04000000), + DBGMCU_TMR14_STOP = ((uint32_t)0x08000000), + DBGMCU_TMR9_STOP = ((uint32_t)0x10000000), + DBGMCU_TMR10_STOP = ((uint32_t)0x20000000), + DBGMCU_TMR11_STOP = ((uint32_t)0x40000000), +}; + +/**@} end of group DBGMCU_Enumerations*/ + + +/** @addtogroup DBGMCU_Fuctions Fuctions + @{ +*/ + +uint32_t DBGMCU_ReadDEVID(void); +uint32_t DBGMCU_ReadREVID(void); +void DBGMCU_Enable(uint32_t periph); +void DBGMCU_Disable(uint32_t periph); + +/**@} end of group DBGMCU_Fuctions*/ +/**@} end of group DBGMCU_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DBGMCU_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h new file mode 100644 index 0000000000..eb574afb73 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h @@ -0,0 +1,290 @@ +/*! + * @file apm32f10x_dma.h + * + * @brief This file contains all the functions prototypes for the DMA firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_DMA_H +#define __APM32F10X_DMA_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMA_Driver DMA Driver + @{ +*/ + +/** @addtogroup DMA_Enumerations Enumerations + @{ +*/ + +/** + * @brief DMA Transmission direction + */ +typedef enum +{ + DMA_DIR_PERIPHERAL_SRC, + DMA_DIR_PERIPHERAL_DST +} DMA_DIR_T; + +/** + * @brief DMA Peripheral address increment + */ +typedef enum +{ + DMA_PERIPHERAL_INC_DISABLE, + DMA_PERIPHERAL_INC_ENABLE +} DMA_PERIPHERAL_INC_T; + +/** + * @brief DMA Memory address increment + */ +typedef enum +{ + DMA_MEMORY_INC_DISABLE, + DMA_MEMORY_INC_ENABLE +} DMA_MEMORY_INC_T; + +/** + * @brief DMA Peripheral Data Size + */ +typedef enum +{ + DMA_PERIPHERAL_DATA_SIZE_BYTE, + DMA_PERIPHERAL_DATA_SIZE_HALFWORD, + DMA_PERIPHERAL_DATA_SIZE_WOED +} DMA_PERIPHERAL_DATA_SIZE_T; + +/** + * @brief DMA Memory Data Size + */ +typedef enum +{ + DMA_MEMORY_DATA_SIZE_BYTE, + DMA_MEMORY_DATA_SIZE_HALFWORD, + DMA_MEMORY_DATA_SIZE_WOED +} DMA_MEMORY_DATA_SIZE_T; + +/** + * @brief DMA Mode + */ +typedef enum +{ + DMA_MODE_NORMAL, + DMA_MODE_CIRCULAR +} DMA_LOOP_MODE_T; + +/** + * @brief DMA priority level + */ +typedef enum +{ + DMA_PRIORITY_LOW, + DMA_PRIORITY_MEDIUM, + DMA_PRIORITY_HIGH, + DMA_PRIORITY_VERYHIGH +} DMA_PRIORITY_T; + +/** + * @brief DMA Memory to Memory + */ +typedef enum +{ + DMA_M2MEN_DISABLE, + DMA_M2MEN_ENABLE +} DMA_M2MEN_T; + +/** + * @brief DMA interrupt + */ +typedef enum +{ + DMA_INT_TC = 0x00000002, + DMA_INT_HT = 0x00000004, + DMA_INT_TERR = 0x00000008 +} DMA_INT_T; + +/** + * @brief DMA Flag + */ +typedef enum +{ + DMA1_FLAG_GINT1 = 0x00000001, + DMA1_FLAG_TC1 = 0x00000002, + DMA1_FLAG_HT1 = 0x00000004, + DMA1_FLAG_TERR1 = 0x00000008, + DMA1_FLAG_GINT2 = 0x00000010, + DMA1_FLAG_TC2 = 0x00000020, + DMA1_FLAG_HT2 = 0x00000040, + DMA1_FLAG_TERR2 = 0x00000080, + DMA1_FLAG_GINT3 = 0x00000100, + DMA1_FLAG_TC3 = 0x00000200, + DMA1_FLAG_HT3 = 0x00000400, + DMA1_FLAG_TERR3 = 0x00000800, + DMA1_FLAG_GINT4 = 0x00001000, + DMA1_FLAG_TC4 = 0x00002000, + DMA1_FLAG_HT4 = 0x00004000, + DMA1_FLAG_TERR4 = 0x00008000, + DMA1_FLAG_GINT5 = 0x00010000, + DMA1_FLAG_TC5 = 0x00020000, + DMA1_FLAG_HT5 = 0x00040000, + DMA1_FLAG_TERR5 = 0x00080000, + DMA1_FLAG_GINT6 = 0x00100000, + DMA1_FLAG_TC6 = 0x00200000, + DMA1_FLAG_HT6 = 0x00400000, + DMA1_FLAG_TERR6 = 0x00800000, + DMA1_FLAG_GINT7 = 0x01000000, + DMA1_FLAG_TC7 = 0x02000000, + DMA1_FLAG_HT7 = 0x04000000, + DMA1_FLAG_TERR7 = 0x08000000, + + DMA2_FLAG_GINT1 = 0x10000001, + DMA2_FLAG_TC1 = 0x10000002, + DMA2_FLAG_HT1 = 0x10000004, + DMA2_FLAG_TERR1 = 0x10000008, + DMA2_FLAG_GINT2 = 0x10000010, + DMA2_FLAG_TC2 = 0x10000020, + DMA2_FLAG_HT2 = 0x10000040, + DMA2_FLAG_TERR2 = 0x10000080, + DMA2_FLAG_GINT3 = 0x10000100, + DMA2_FLAG_TC3 = 0x10000200, + DMA2_FLAG_HT3 = 0x10000400, + DMA2_FLAG_TERR3 = 0x10000800, + DMA2_FLAG_GINT4 = 0x10001000, + DMA2_FLAG_TC4 = 0x10002000, + DMA2_FLAG_HT4 = 0x10004000, + DMA2_FLAG_TERR4 = 0x10008000, + DMA2_FLAG_GINT5 = 0x10010000, + DMA2_FLAG_TC5 = 0x10020000, + DMA2_FLAG_HT5 = 0x10040000, + DMA2_FLAG_TERR5 = 0x10080000 +} DMA_FLAG_T; + +/** + * @brief DMA Flag + */ +typedef enum +{ + DMA1_INT_FLAG_GINT1 = 0x00000001, + DMA1_INT_FLAG_TC1 = 0x00000002, + DMA1_INT_FLAG_HT1 = 0x00000004, + DMA1_INT_FLAG_TERR1 = 0x00000008, + DMA1_INT_FLAG_GINT2 = 0x00000010, + DMA1_INT_FLAG_TC2 = 0x00000020, + DMA1_INT_FLAG_HT2 = 0x00000040, + DMA1_INT_FLAG_TERR2 = 0x00000080, + DMA1_INT_FLAG_GINT3 = 0x00000100, + DMA1_INT_FLAG_TC3 = 0x00000200, + DMA1_INT_FLAG_HT3 = 0x00000400, + DMA1_INT_FLAG_TERR3 = 0x00000800, + DMA1_INT_FLAG_GINT4 = 0x00001000, + DMA1_INT_FLAG_TC4 = 0x00002000, + DMA1_INT_FLAG_HT4 = 0x00004000, + DMA1_INT_FLAG_TERR4 = 0x00008000, + DMA1_INT_FLAG_GINT5 = 0x00010000, + DMA1_INT_FLAG_TC5 = 0x00020000, + DMA1_INT_FLAG_HT5 = 0x00040000, + DMA1_INT_FLAG_TERR5 = 0x00080000, + DMA1_INT_FLAG_GINT6 = 0x00100000, + DMA1_INT_FLAG_TC6 = 0x00200000, + DMA1_INT_FLAG_HT6 = 0x00400000, + DMA1_INT_FLAG_TERR6 = 0x00800000, + DMA1_INT_FLAG_GINT7 = 0x01000000, + DMA1_INT_FLAG_TC7 = 0x02000000, + DMA1_INT_FLAG_HT7 = 0x04000000, + DMA1_INT_FLAG_TERR7 = 0x08000000, + + DMA2_INT_FLAG_GINT1 = 0x10000001, + DMA2_INT_FLAG_TC1 = 0x10000002, + DMA2_INT_FLAG_HT1 = 0x10000004, + DMA2_INT_FLAG_TERR1 = 0x10000008, + DMA2_INT_FLAG_GINT2 = 0x10000010, + DMA2_INT_FLAG_TC2 = 0x10000020, + DMA2_INT_FLAG_HT2 = 0x10000040, + DMA2_INT_FLAG_TERR2 = 0x10000080, + DMA2_INT_FLAG_GINT3 = 0x10000100, + DMA2_INT_FLAG_TC3 = 0x10000200, + DMA2_INT_FLAG_HT3 = 0x10000400, + DMA2_INT_FLAG_TERR3 = 0x10000800, + DMA2_INT_FLAG_GINT4 = 0x10001000, + DMA2_INT_FLAG_TC4 = 0x10002000, + DMA2_INT_FLAG_HT4 = 0x10004000, + DMA2_INT_FLAG_TERR4 = 0x10008000, + DMA2_INT_FLAG_GINT5 = 0x10010000, + DMA2_INT_FLAG_TC5 = 0x10020000, + DMA2_INT_FLAG_HT5 = 0x10040000, + DMA2_INT_FLAG_TERR5 = 0x10080000 +} DMA_INT_FLAG_T; + +/**@} end of group DMA_Enumerations*/ + + +/** @addtogroup DMA_Structure Data Structure + @{ +*/ + +/** + * @brief DMA Config struct definition + */ +typedef struct +{ + uint32_t peripheralBaseAddr; + uint32_t memoryBaseAddr; + DMA_DIR_T dir; + uint32_t bufferSize; + DMA_PERIPHERAL_INC_T peripheralInc; + DMA_MEMORY_INC_T memoryInc; + DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize; + DMA_MEMORY_DATA_SIZE_T memoryDataSize; + DMA_LOOP_MODE_T loopMode; + DMA_PRIORITY_T priority; + DMA_M2MEN_T M2M; +} DMA_Config_T; + +/**@} end of group DMA_Structure*/ + + +/** @addtogroup DMA_Fuctions Fuctions + @{ +*/ + +/** Reset and configuration */ +void DMA_Reset(DMA_Channel_T *channel); +void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig); +void DMA_ConfigStructInit( DMA_Config_T* dmaConfig); +void DMA_Enable(DMA_Channel_T *channel); +void DMA_Disable(DMA_Channel_T *channel); + +/** Data number */ +void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber); +uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel); + +/** Interrupt and flag */ +void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt); +void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt); +uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag); +void DMA_ClearStatusFlag(uint32_t flag); +uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag); +void DMA_ClearIntFlag(uint32_t flag); + +/**@} end of group DMA_Fuctions*/ +/**@} end of group DMA_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DMA_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h new file mode 100644 index 0000000000..809e2663d7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h @@ -0,0 +1,351 @@ +/*! + * @file apm32f10x_dmc.h + * + * @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#ifndef __APM32F10X_DMC_H +#define __APM32F10X_DMC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMC_Driver DMC Driver + @{ +*/ + +/** @addtogroup DMC_Enumerations Enumerations + @{ +*/ + + +/** + * @brief Bank Address Width + */ +typedef enum +{ + DMC_BANK_WIDTH_1, + DMC_BANK_WIDTH_2 +}DMC_BANK_WIDTH_T; + +/** + * @brief Row Address Width + */ +typedef enum +{ + DMC_ROW_WIDTH_11 = 0x0A, + DMC_ROW_WIDTH_12, + DMC_ROW_WIDTH_13, + DMC_ROW_WIDTH_14, + DMC_ROW_WIDTH_15, + DMC_ROW_WIDTH_16 +}DMC_ROW_WIDTH_T; + +/** + * @brief Column Address Width + */ +typedef enum +{ + DMC_COL_WIDTH_8 = 0x07, + DMC_COL_WIDTH_9, + DMC_COL_WIDTH_10, + DMC_COL_WIDTH_11, + DMC_COL_WIDTH_12, + DMC_COL_WIDTH_13, + DMC_COL_WIDTH_14, + DMC_COL_WIDTH_15 +}DMC_COL_WIDTH_T; + +/** + * @brief CAS Latency Select + */ +typedef enum +{ + DMC_CAS_LATENCY_1, + DMC_CAS_LATENCY_2, + DMC_CAS_LATENCY_3, + DMC_CAS_LATENCY_4 +}DMC_CAS_LATENCY_T; + +/** + * @brief RAS Minimun Time Select + */ +typedef enum +{ + DMC_RAS_MINIMUM_1, + DMC_RAS_MINIMUM_2, + DMC_RAS_MINIMUM_3, + DMC_RAS_MINIMUM_4, + DMC_RAS_MINIMUM_5, + DMC_RAS_MINIMUM_6, + DMC_RAS_MINIMUM_7, + DMC_RAS_MINIMUM_8, + DMC_RAS_MINIMUM_9, + DMC_RAS_MINIMUM_10, + DMC_RAS_MINIMUM_11, + DMC_RAS_MINIMUM_12, + DMC_RAS_MINIMUM_13, + DMC_RAS_MINIMUM_14, + DMC_RAS_MINIMUM_15, + DMC_RAS_MINIMUM_16 +}DMC_RAS_MINIMUM_T; + +/** + * @brief RAS To CAS Delay Time Select + */ +typedef enum +{ + DMC_DELAY_TIME_1, + DMC_DELAY_TIME_2, + DMC_DELAY_TIME_3, + DMC_DELAY_TIME_4, + DMC_DELAY_TIME_5, + DMC_DELAY_TIME_6, + DMC_DELAY_TIME_7, + DMC_DELAY_TIME_8 +}DMC_DELAY_TIME_T; + +/** + * @brief Precharge Period Select + */ +typedef enum +{ + DMC_PRECHARGE_1, + DMC_PRECHARGE_2, + DMC_PRECHARGE_3, + DMC_PRECHARGE_4, + DMC_PRECHARGE_5, + DMC_PRECHARGE_6, + DMC_PRECHARGE_7, + DMC_PRECHARGE_8 +}DMC_PRECHARGE_T; + +/** + * @brief Last Data Next Precharge For Write Time Select + */ +typedef enum +{ + DMC_NEXT_PRECHARGE_1, + DMC_NEXT_PRECHARGE_2, + DMC_NEXT_PRECHARGE_3, + DMC_NEXT_PRECHARGE_4 +}DMC_NEXT_PRECHARGE_T; + +/** + * @brief Auto-Refresh Period Select + */ +typedef enum +{ + DMC_AUTO_REFRESH_1, + DMC_AUTO_REFRESH_2, + DMC_AUTO_REFRESH_3, + DMC_AUTO_REFRESH_4, + DMC_AUTO_REFRESH_5, + DMC_AUTO_REFRESH_6, + DMC_AUTO_REFRESH_7, + DMC_AUTO_REFRESH_8, + DMC_AUTO_REFRESH_9, + DMC_AUTO_REFRESH_10, + DMC_AUTO_REFRESH_11, + DMC_AUTO_REFRESH_12, + DMC_AUTO_REFRESH_13, + DMC_AUTO_REFRESH_14, + DMC_AUTO_REFRESH_15, + DMC_AUTO_REFRESH_16, +}DMC_AUTO_REFRESH_T; + +/** + * @brief Active-to-active Command Period Select + */ +typedef enum +{ + DMC_ATA_CMD_1, + DMC_ATA_CMD_2, + DMC_ATA_CMD_3, + DMC_ATA_CMD_4, + DMC_ATA_CMD_5, + DMC_ATA_CMD_6, + DMC_ATA_CMD_7, + DMC_ATA_CMD_8, + DMC_ATA_CMD_9, + DMC_ATA_CMD_10, + DMC_ATA_CMD_11, + DMC_ATA_CMD_12, + DMC_ATA_CMD_13, + DMC_ATA_CMD_14, + DMC_ATA_CMD_15, + DMC_ATA_CMD_16, +}DMC_ATA_CMD_T; + +/** + * @brief Clock PHASE + */ +typedef enum +{ + DMC_CLK_PHASE_NORMAL, + DMC_CLK_PHASE_REVERSE +}DMC_CLK_PHASE_T; + +/** + * @brief DMC Memory Size + */ +typedef enum +{ + DMC_MEMORY_SIZE_0, + DMC_MEMORY_SIZE_64KB, + DMC_MEMORY_SIZE_128KB, + DMC_MEMORY_SIZE_256KB, + DMC_MEMORY_SIZE_512KB, + DMC_MEMORY_SIZE_1MB, + DMC_MEMORY_SIZE_2MB, + DMC_MEMORY_SIZE_4MB, + DMC_MEMORY_SIZE_8MB, + DMC_MEMORY_SIZE_16MB, + DMC_MEMORY_SIZE_32MB, + DMC_MEMORY_SIZE_64MB, + DMC_MEMORY_SIZE_128MB, + DMC_MEMORY_SIZE_256MB, +}DMC_MEMORY_SIZE_T; + +/** + * @brief Open Banks Of Number + */ +typedef enum +{ + DMC_BANK_NUMBER_1, + DMC_BANK_NUMBER_2, + DMC_BANK_NUMBER_3, + DMC_BANK_NUMBER_4, + DMC_BANK_NUMBER_5, + DMC_BANK_NUMBER_6, + DMC_BANK_NUMBER_7, + DMC_BANK_NUMBER_8, + DMC_BANK_NUMBER_9, + DMC_BANK_NUMBER_10, + DMC_BANK_NUMBER_11, + DMC_BANK_NUMBER_12, + DMC_BANK_NUMBER_13, + DMC_BANK_NUMBER_14, + DMC_BANK_NUMBER_15, + DMC_BANK_NUMBER_16, +}DMC_BANK_NUMBER_T; + +/** + * @brief Full refresh type + */ +typedef enum +{ + DMC_REFRESH_ROW_ONE, //!< Refresh one row + DMC_REFRESH_ROW_ALL, //!< Refresh all row +}DMC_REFRESH_T; + +/** + * @brief Precharge type + */ +typedef enum +{ + DMC_PRECHARGE_IM, //!< Immediate precharge + DMC_PRECHARGE_DELAY, //!< Delayed precharge +}DMC_PRECHARE_T; + + +/**@} end of group DMC_Enumerations*/ + + +/** @addtogroup DMC_Structure Data Structure + @{ +*/ + +/** + * @brief Timing config definition + */ +typedef struct +{ + uint32_t latencyCAS : 2; //!< DMC_CAS_LATENCY_T + uint32_t tRAS : 4; //!< DMC_RAS_MINIMUM_T + uint32_t tRCD : 3; //!< DMC_DELAY_TIME_T + uint32_t tRP : 3; //!< DMC_PRECHARGE_T + uint32_t tWR : 2; //!< DMC_NEXT_PRECHARGE_T + uint32_t tARP : 4; //!< DMC_AUTO_REFRESH_T + uint32_t tCMD : 4; //!< DMC_ATA_CMD_T + uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF + uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF +}DMC_TimingConfig_T; + +/** + * @brief Config struct definition + */ +typedef struct +{ + DMC_MEMORY_SIZE_T memorySize; //!< Memory size(byte) + DMC_BANK_WIDTH_T bankWidth; //!< Number of bank bits + DMC_ROW_WIDTH_T rowWidth; //!< Number of row address bits + DMC_COL_WIDTH_T colWidth; //!< Number of col address bits + DMC_CLK_PHASE_T clkPhase; //!< Clock phase + DMC_TimingConfig_T timing; //!< Timing +}DMC_Config_T; + +/**@} end of group DMC_Structure*/ + + +/** @addtogroup DMC_Fuctions Fuctions + @{ +*/ + + /** Enable / Disable */ +void DMC_Enable(void); +void DMC_Disable(void); +void DMC_EnableInit(void); + +/** Global config */ +void DMC_Config(DMC_Config_T *dmcConfig); +void DMC_ConfigStructInit(DMC_Config_T *dmcConfig); + +/** Address */ +void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth); +void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth); + +/** Timing */ +void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig); +void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig); +void DMC_ConfigStableTimePowerup(uint16_t stableTime); +void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num); +void DMC_ConfigRefreshPeriod(uint16_t period); + +/** Refresh mode */ +void DMC_EixtSlefRefreshMode(void); +void DMC_EnterSlefRefreshMode(void); + +/** Config */ +void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num); +void DMC_EnableUpdateMode(void); +void DMC_EnterPowerdownMode(void); +void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh); +void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh); +void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge); +void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize); +void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase); + +/** read flag */ +uint8_t DMC_ReadSelfRefreshStatus(void); + +/**@} end of group DMC_Fuctions*/ +/**@} end of group DMC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_DMC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h new file mode 100644 index 0000000000..23bedc9b02 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h @@ -0,0 +1,119 @@ +/*! + * @file apm32f10x_eint.h + * + * @brief This file contains all the functions prototypes for the EINT firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_EINT_H +#define __APM32F10X_EINT_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EINT_Driver EINT Driver + @{ +*/ + +/** @addtogroup EINT_Enumerations Enumerations + @{ +*/ + +/** + * @brief EINT mode enumeration + */ +typedef enum +{ + EINT_MODE_INTERRUPT = 0x00, + EINT_MODE_EVENT = 0x04 +} EINT_MODE_T; + +/** + * @brief EINT Trigger enumeration + */ +typedef enum +{ + EINT_TRIGGER_RISING = 0x08, + EINT_TRIGGER_FALLING = 0x0C, + EINT_TRIGGER_RISING_FALLING = 0x10 +} EINT_TRIGGER_T; + +typedef enum +{ + EINT_LINE_0 = 0x00001, //!< External interrupt line 0 + EINT_LINE_1 = 0x00002, //!< External interrupt line 1 + EINT_LINE_2 = 0x00004, //!< External interrupt line 2 + EINT_LINE_3 = 0x00008, //!< External interrupt line 3 + EINT_LINE_4 = 0x00010, //!< External interrupt line 4 + EINT_LINE_5 = 0x00020, //!< External interrupt line 5 + EINT_LINE_6 = 0x00040, //!< External interrupt line 6 + EINT_LINE_7 = 0x00080, //!< External interrupt line 7 + EINT_LINE_8 = 0x00100, //!< External interrupt line 8 + EINT_LINE_9 = 0x00200, //!< External interrupt line 9 + EINT_LINE_10 = 0x00400, //!< External interrupt line 10 + EINT_LINE_11 = 0x00800, //!< External interrupt line 11 + EINT_LINE_12 = 0x01000, //!< External interrupt line 12 + EINT_LINE_13 = 0x02000, //!< External interrupt line 13 + EINT_LINE_14 = 0x04000, //!< External interrupt line 14 + EINT_LINE_15 = 0x08000, //!< External interrupt line 15 + EINT_LINE_16 = 0x10000, //!< External interrupt line 16 Connected to the PVD Output + EINT_LINE_17 = 0x20000, //!< External interrupt line 17 Connected to the RTC Alarm event + EINT_LINE_18 = 0x40000, //!< External interrupt line 18 Connected to the USB Device +} EINT_LINE_T; + +/**@} end of group EINT_Enumerations*/ + + +/** @addtogroup EINT_Structure Data Structure + @{ +*/ + +/** + * @brief EINT Config structure definition + */ +typedef struct +{ + uint32_t line; + EINT_MODE_T mode; + EINT_TRIGGER_T trigger; + uint8_t lineCmd; +} EINT_Config_T; + +/**@} end of group EINT_Structure*/ + + +/** @addtogroup EINT_Fuctions Fuctions + @{ +*/ + +/** Reset and configuration */ +void EINT_Reset(void); +void EINT_Config( EINT_Config_T* eintConfig); + +/** Interrupt and flag */ +void EINT_SelectSWInterrupt(uint32_t line); +uint8_t EINT_ReadStatusFlag(EINT_LINE_T line); +void EINT_ClearStatusFlag(uint32_t line); +uint8_t EINT_ReadIntFlag(EINT_LINE_T line); +void EINT_ClearIntFlag(uint32_t line); + +/**@} end of group EINT_Fuctions*/ +/**@} end of group EINT_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __APM32F10X_cplusplus +} +#endif + +#endif /* __EINT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h new file mode 100644 index 0000000000..5b5c82e727 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h @@ -0,0 +1,355 @@ +/*! + * @file apm32f10x_emmc.h + * + * @brief This file contains all the functions prototypes for the EMMC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_EMMC_H +#define __APM32F10X_EMMC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EMMC_Driver EMMC Driver + @{ +*/ + +/** @addtogroup EMMC_Enumerations Enumerations + @{ +*/ + +/** + * @brief EMMC NORSRAM_Bank + */ +typedef enum +{ + EMMC_BANK1_NORSRAM_1 = 0x00000000, + EMMC_BANK1_NORSRAM_2 = 0x00000002, + EMMC_BANK1_NORSRAM_3 = 0x00000004, + EMMC_BANK1_NORSRAM_4 = 0x00000006 +} EMMC_BANK1_NORSRAM_T; + +/** + * @brief EMMC NAND and PC Card Bank + */ +typedef enum +{ + EMMC_BANK2_NAND = 0x00000010, + EMMC_BANK3_NAND = 0x00000100, + EMMC_BANK4_PCCARD = 0x00001000 +} EMMC_BANK_NAND_T; + +/** + * @brief EMMC_Data_Address_Bus_Multiplexing + */ +typedef enum +{ + EMMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000, + EMMC_DATA_ADDRESS_MUX_ENABLE = 0x00000002 +} EMMC_DATA_ADDRESS_MUX_T; + +/** + * @brief EMMC_Memory_Type + */ +typedef enum +{ + EMMC_MEMORY_TYPE_SRAM = 0x00000000, + EMMC_MEMORY_TYPE_PARAM = 0x00000004, + EMMC_MEMORY_TYPE_NOR = 0x00000008 +} EMMC_MEMORY_TYPE_T; + +/** + * @brief EMMC_Data_Width + */ +typedef enum +{ + EMMC_MEMORY_DATA_WIDTH_8BIT = 0x00000000, + EMMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010 +} EMMC_MEMORY_DATA_WIDTH_T; + +/** + * @brief EMMC_Burst_Access_Mode + */ +typedef enum +{ + EMMC_BURST_ACCESS_MODE_DISABLE = 0x00000000, + EMMC_BURST_ACCESS_MODE_ENABLE = 0x00000100 +} EMMC_BURST_ACCESS_MODE_T; + +/** + * @brief EMMC_AsynchronousWait + */ +typedef enum +{ + EMMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000, + EMMC_ASYNCHRONOUS_WAIT_ENABLE = 0x00008000 +} EMMC_ASYNCHRONOUS_WAIT_T; + +/** + * @brief EMMC_Wait_Signal_Polarity + */ +typedef enum +{ + EMMC_WAIT_SIGNAL_POLARITY_LOW = 0x00000000, + EMMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200 +} EMMC_WAIT_SIGNAL_POLARITY_T; + +/** + * @brief EMMC_Wrap_Mode + */ +typedef enum +{ + EMMC_WRAP_MODE_DISABLE = 0x00000000, + EMMC_WRAP_MODE_ENABLE = 0x00000400 +} EMMC_WRAP_MODE_T; + +/** + * @brief EMMC_Wait_Timing + */ +typedef enum +{ + EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000, + EMMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800 +} EMMC_WAIT_SIGNAL_ACTIVE_T; + +/** + * @brief EMMC_Write_Operation + */ +typedef enum +{ + EMMC_WRITE_OPERATION_DISABLE = 0x00000000, + EMMC_WRITE_OPERATION_ENABLE = 0x00001000 +} EMMC_WRITE_OPERATION_T; + +/** + * @brief EMMC_Wait_Signal + */ +typedef enum +{ + EMMC_WAITE_SIGNAL_DISABLE = 0x00000000, + EMMC_WAITE_SIGNAL_ENABLE = 0x00002000 +} EMMC_WAITE_SIGNAL_T; + +/** + * @brief EMMC_Extended_Mode + */ +typedef enum +{ + EMMC_EXTENDEN_MODE_DISABLE = 0x00000000, + EMMC_EXTENDEN_MODE_ENABLE = 0x00004000 +} EMMC_EXTENDEN_MODE_T; + +/** + * @brief EMMC_Write_Burst + */ +typedef enum +{ + EMMC_WRITE_BURST_DISABLE = 0x00000000, + EMMC_WRITE_BURST_ENABLE = 0x00080000 +} EMMC_WRITE_BURST_T; + +/** + * @brief EMMC_WAIT_FEATURE + */ +typedef enum +{ + EMMC_WAIT_FEATURE_DISABLE = 0x00000000, + EMMC_WAIT_FEATURE_ENABLE = 0x00000002 +} EMMC_WAIT_FEATURE_T; + +/** + * @brief EMMC_ECC + */ +typedef enum +{ + EMMC_ECC_DISABLE = 0x00000000, + EMMC_ECC_ENABLE = 0x00000040 +} EMMC_ECC_T; + +/** + * @brief EMMC_ECC_Page_Size + */ +typedef enum +{ + EMMC_ECC_PAGE_SIZE_BYTE_256 = 0x00000000, + EMMC_ECC_PAGE_SIZE_BYTE_512 = 0x00020000, + EMMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000, + EMMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000, + EMMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000, + EMMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000 +} EMMC_ECC_PAGE_SIZE_BYTE_T; + +/** + * @brief EMMC_Access_Mode + */ +typedef enum +{ + EMMC_ACCESS_MODE_A = 0x00000000, + EMMC_ACCESS_MODE_B = 0x10000000, + EMMC_ACCESS_MODE_C = 0x20000000, + EMMC_ACCESS_MODE_D = 0x30000000 +} EMMC_ACCESS_MODE_T; + +/** + * @brief EMMC_Interrupt_sources + */ +typedef enum +{ + EMMC_INT_EDGE_RISING = 0x00000008, + EMMC_INT_LEVEL_HIGH = 0x00000010, + EMMC_INT_EDGE_FALLING = 0x00000020 +} EMMC_INT_T; + +/** + * @brief EMMC_Flags + */ +typedef enum +{ + EMMC_FLAG_EDGE_RISING = 0x00000001, + EMMC_FLAG_LEVEL_HIGH = 0x00000002, + EMMC_FLAG_EDGE_FALLING = 0x00000004, + EMMC_FLAG_FIFO_EMPTY = 0x00000040 +} EMMC_FLAG_T; + +/**@} end of group EMMC_Enumerations*/ + + +/** @addtogroup EMMC_Structure Data Structure + @{ +*/ + +/** + * @brief Timing parameters for NOR/SRAM Banks + */ +typedef struct +{ + uint32_t addressSetupTime; + uint32_t addressHodeTime; + uint32_t dataSetupTime; + uint32_t busTurnaroundTime; + uint32_t clockDivision; + uint32_t dataLatency; + EMMC_ACCESS_MODE_T accessMode; +} EMMC_NORSRAMTimingConfig_T; + +/** + * @brief EMMC NOR/SRAM Config structure + */ +typedef struct +{ + EMMC_BANK1_NORSRAM_T bank; + EMMC_DATA_ADDRESS_MUX_T dataAddressMux; + EMMC_MEMORY_TYPE_T memoryType; + EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth; + EMMC_BURST_ACCESS_MODE_T burstAcceesMode; + EMMC_ASYNCHRONOUS_WAIT_T asynchronousWait; + EMMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity; + EMMC_WRAP_MODE_T wrapMode; + EMMC_WAIT_SIGNAL_ACTIVE_T waitSignalActive; + EMMC_WRITE_OPERATION_T writeOperation; + EMMC_WAITE_SIGNAL_T waiteSignal; + EMMC_EXTENDEN_MODE_T extendedMode; + EMMC_WRITE_BURST_T writeBurst; + EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct; + EMMC_NORSRAMTimingConfig_T* writeTimingStruct; +} EMMC_NORSRAMConfig_T; + +/** + * @brief Timing parameters for NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t setupTime; + uint32_t waitSetupTime; + uint32_t holdSetupTime; + uint32_t HiZSetupTime; +} EMMC_NAND_PCCARDTimingConfig_T; + +/** + * @brief EMMC NAND Config structure + */ +typedef struct +{ + EMMC_BANK_NAND_T bank; + EMMC_WAIT_FEATURE_T waitFeature; + EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth; + EMMC_ECC_T ECC; + EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize; + uint32_t TCLRSetupTime; + uint32_t TARSetupTime; + EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; +} EMMC_NANDConfig_T; + +/** + * @brief EMMC PCCARD Config structure + */ +typedef struct +{ + EMMC_WAIT_FEATURE_T waitFeature; + uint32_t TCLRSetupTime; + uint32_t TARSetupTime; + EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct; + EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct; +} EMMC_PCCARDConfig_T; + +/**@} end of group EMMC_Structure*/ + +/** @addtogroup EMMC_Fuctions Fuctions + @{ +*/ + +/** EMMC reset */ +void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank); +void EMMC_ResetNAND(EMMC_BANK_NAND_T bank); +void EMMC_ResetPCCard(void); + +/** EMMC Configuration */ +void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig); +void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig); +void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig); +void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig); +void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig); +void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig); + +/** EMMC bank control */ +void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank); +void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank); +void EMMC_EnableNAND(EMMC_BANK_NAND_T bank); +void EMMC_DisableNAND(EMMC_BANK_NAND_T bank); +void EMMC_EnablePCCARD(void); +void EMMC_DisablePCCARD(void); +void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank); +void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank); +uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank); + +/** Interrupt and flag */ +void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt); +void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt); +uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag); +void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag); +uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag); +void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag); + +/**@} end of group EMMC_Fuctions*/ +/**@} end of group EMMC_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_EMMC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h new file mode 100644 index 0000000000..5915185f6f --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h @@ -0,0 +1,251 @@ +/*! + * @file apm32f10x_fmc.h + * + * @brief This file contains all the functions prototypes for the FMC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_FMC_H +#define __APM32F10X_FMC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_Enumerations Enumerations + @{ +*/ + +/** + * @brief Flash Latency + */ +typedef enum +{ + FMC_LATENCY_0, + FMC_LATENCY_1, + FMC_LATENCY_2 +} FMC_LATENCY_T; + +/** + * @brief FMC Status + */ +typedef enum +{ + FMC_STATUS_BUSY = 1, //!< flash busy + FMC_STATUS_ERROR_PG, //!< flash programming error + FMC_STATUS_ERROR_WRP, //!< flash write protection error + FMC_STATUS_COMPLETE, //!< flash operation complete + FMC_STATUS_TIMEOUT //!< flash time out +} FMC_STATUS_T; + +/** + * @brief Option Bytes IWatchdog + */ +typedef enum +{ + OB_IWDT_HARD = 0x0000, + OB_IWDT_SOTF = 0x0001 +} OB_IWDT_T; + +/** + * @brief Option Bytes nRST STOP + */ +typedef enum +{ + OB_STOP_RST = 0x0000, + OB_STOP_NORST = 0x0002 +} OB_STOP_T; + +/** + * @brief Option Bytes nRST STDBY + */ +typedef enum +{ + OB_STDBY_RST = 0x0000, + OB_STDBY_NORST = 0x0004 +} OB_STDBY_T; + +/** + * @brief FMC Interrupts + */ +typedef enum +{ + FMC_INT_ERR, + FMC_INT_OC +} FMC_INT_T; + +/** + * @brief FMC flag + */ +typedef enum +{ + FMC_FLAG_BUSY = 0x00000001, //!< FMC Busy flag + FMC_FLAG_OC = 0x00000020, //!< FMC End of Operation flag + FMC_FLAG_PE = 0x00000004, //!< FMC Program error flag + FMC_FLAG_WPE = 0x00000010, //!< FMC Write protected error flag + FMC_FLAG_OBE = 0x10000001, //!< FMC Option Byte error flag +} FMC_FLAG_T; + +/**@} end of group FMC_Enumerations*/ + +/** @addtogroup FMC_Macros Macros + @{ +*/ + +/** Macros description */ + +/** Values for APM32 Low and Medium density devices */ +#define FLASH_WRP_PAGE_0_3 ((uint32_t)BIT0) //!< Write protection of page 0 to 3 +#define FLASH_WRP_PAGE_4_7 ((uint32_t)BIT1) //!< Write protection of page 4 to 7 +#define FLASH_WRP_PAGE_8_11 ((uint32_t)BIT2) //!< Write protection of page 8 to 11 +#define FLASH_WRP_PAGE_12_15 ((uint32_t)BIT3) //!< Write protection of page 12 to 15 +#define FLASH_WRP_PAGE_16_19 ((uint32_t)BIT4) //!< Write protection of page 16 to 19 +#define FLASH_WRP_PAGE_20_23 ((uint32_t)BIT5) //!< Write protection of page 20 to 23 +#define FLASH_WRP_PAGE_24_27 ((uint32_t)BIT6) //!< Write protection of page 24 to 27 +#define FLASH_WRP_PAGE_28_31 ((uint32_t)BIT7) //!< Write protection of page 28 to 31 + +/** Values for APM32 Medium-density devices */ +#define FLASH_WRP_PAGE_32_35 ((uint32_t)BIT8) //!< Write protection of page 32 to 35 +#define FLASH_WRP_PAGE_36_39 ((uint32_t)BIT9) //!< Write protection of page 36 to 39 +#define FLASH_WRP_PAGE_40_43 ((uint32_t)BIT10) //!< Write protection of page 40 to 43 +#define FLASH_WRP_PAGE_44_47 ((uint32_t)BIT11) //!< Write protection of page 44 to 47 +#define FLASH_WRP_PAGE_48_51 ((uint32_t)BIT12) //!< Write protection of page 48 to 51 +#define FLASH_WRP_PAGE_52_55 ((uint32_t)BIT13) //!< Write protection of page 52 to 55 +#define FLASH_WRP_PAGE_56_59 ((uint32_t)BIT14) //!< Write protection of page 56 to 59 +#define FLASH_WRP_PAGE_60_63 ((uint32_t)BIT15) //!< Write protection of page 60 to 63 +#define FLASH_WRP_PAGE_64_67 ((uint32_t)BIT16) //!< Write protection of page 64 to 67 +#define FLASH_WRP_PAGE_68_71 ((uint32_t)BIT17) //!< Write protection of page 68 to 71 +#define FLASH_WRP_PAGE_72_75 ((uint32_t)BIT18) //!< Write protection of page 72 to 75 +#define FLASH_WRP_PAGE_76_79 ((uint32_t)BIT19) //!< Write protection of page 76 to 79 +#define FLASH_WRP_PAGE_80_83 ((uint32_t)BIT20) //!< Write protection of page 80 to 83 +#define FLASH_WRP_PAGE_84_87 ((uint32_t)BIT21) //!< Write protection of page 84 to 87 +#define FLASH_WRP_PAGE_88_91 ((uint32_t)BIT22) //!< Write protection of page 88 to 91 +#define FLASH_WRP_PAGE_92_95 ((uint32_t)BIT23) //!< Write protection of page 92 to 95 +#define FLASH_WRP_PAGE_96_99 ((uint32_t)BIT24) //!< Write protection of page 96 to 99 +#define FLASH_WRP_PAGE_100_103 ((uint32_t)BIT25) //!< Write protection of page 100 to 103 +#define FLASH_WRP_PAGE_104_107 ((uint32_t)BIT26) //!< Write protection of page 104 to 107 +#define FLASH_WRP_PAGE_108_111 ((uint32_t)BIT27) //!< Write protection of page 108 to 111 +#define FLASH_WRP_PAGE_112_115 ((uint32_t)BIT28) //!< Write protection of page 112 to 115 +#define FLASH_WRP_PAGE_116_119 ((uint32_t)BIT29) //!< Write protection of page 116 to 119 +#define FLASH_WRP_PAGE_120_123 ((uint32_t)BIT30) //!< Write protection of page 120 to 123 +#define FLASH_WRP_PAGE_124_127 ((uint32_t)BIT31) //!< Write protection of page 124 to 127 + +/** Values only for APM32 High-density devices */ +#define FLASH_WRP_PAGE_0_1 ((uint32_t)BIT0) //!< Write protection of page 0 to 1 +#define FLASH_WRP_PAGE_2_3 ((uint32_t)BIT1) //!< Write protection of page 2 to 3 +#define FLASH_WRP_PAGE_4_5 ((uint32_t)BIT2) //!< Write protection of page 4 to 5 +#define FLASH_WRP_PAGE_6_7 ((uint32_t)BIT3) //!< Write protection of page 6 to 7 +#define FLASH_WRP_PAGE_8_9 ((uint32_t)BIT4) //!< Write protection of page 8 to 9 +#define FLASH_WRP_PAGE_10_11 ((uint32_t)BIT5) //!< Write protection of page 10 to 11 +#define FLASH_WRP_PAGE_12_13 ((uint32_t)BIT6) //!< Write protection of page 12 to 13 +#define FLASH_WRP_PAGE_14_15 ((uint32_t)BIT7) //!< Write protection of page 14 to 15 +#define FLASH_WRP_PAGE_16_17 ((uint32_t)BIT8) //!< Write protection of page 16 to 17 +#define FLASH_WRP_PAGE_18_19 ((uint32_t)BIT9) //!< Write protection of page 18 to 19 +#define FLASH_WRP_PAGE_20_21 ((uint32_t)BIT10) //!< Write protection of page 20 to 21 +#define FLASH_WRP_PAGE_22_23 ((uint32_t)BIT11) //!< Write protection of page 22 to 23 +#define FLASH_WRP_PAGE_24_25 ((uint32_t)BIT12) //!< Write protection of page 24 to 25 +#define FLASH_WRP_PAGE_26_27 ((uint32_t)BIT13) //!< Write protection of page 26 to 27 +#define FLASH_WRP_PAGE_28_29 ((uint32_t)BIT14) //!< Write protection of page 28 to 29 +#define FLASH_WRP_PAGE_30_31 ((uint32_t)BIT15) //!< Write protection of page 30 to 31 +#define FLASH_WRP_PAGE_32_33 ((uint32_t)BIT16) //!< Write protection of page 32 to 33 +#define FLASH_WRP_PAGE_34_35 ((uint32_t)BIT17) //!< Write protection of page 34 to 35 +#define FLASH_WRP_PAGE_36_37 ((uint32_t)BIT18) //!< Write protection of page 36 to 37 +#define FLASH_WRP_PAGE_38_39 ((uint32_t)BIT19) //!< Write protection of page 38 to 39 +#define FLASH_WRP_PAGE_40_41 ((uint32_t)BIT20) //!< Write protection of page 40 to 41 +#define FLASH_WRP_PAGE_42_43 ((uint32_t)BIT21) //!< Write protection of page 42 to 43 +#define FLASH_WRP_PAGE_44_45 ((uint32_t)BIT22) //!< Write protection of page 44 to 45 +#define FLASH_WRP_PAGE_46_47 ((uint32_t)BIT23) //!< Write protection of page 46 to 47 +#define FLASH_WRP_PAGE_48_49 ((uint32_t)BIT24) //!< Write protection of page 48 to 49 +#define FLASH_WRP_PAGE_50_51 ((uint32_t)BIT25) //!< Write protection of page 50 to 51 +#define FLASH_WRP_PAGE_52_53 ((uint32_t)BIT26) //!< Write protection of page 52 to 53 +#define FLASH_WRP_PAGE_54_55 ((uint32_t)BIT27) //!< Write protection of page 54 to 55 +#define FLASH_WRP_PAGE_56_57 ((uint32_t)BIT28) //!< Write protection of page 56 to 57 +#define FLASH_WRP_PAGE_58_59 ((uint32_t)BIT29) //!< Write protection of page 58 to 59 +#define FLASH_WRP_PAGE_60_61 ((uint32_t)BIT30) //!< Write protection of page 60 to 61 +#define FLASH_WRP_PAGE_62_127 ((uint32_t)BIT31) //!< Write protection of page 62 to 127 +#define FMC_WRP_PAGE_ALL ((uint32_t)0xFFFFFFFF) //!< Write protection of page all */ + +/**@} end of group FMC_Macros*/ + +/** @addtogroup FMC_Structure Data Structure + @{ +*/ + +/** + * @brief User Option byte config struct definition + */ +typedef struct +{ + OB_IWDT_T iwdtSet; + OB_STOP_T stopSet; + OB_STDBY_T stdbySet; +} FMC_UserConfig_T; + +/**@} end of group FMC_Structure*/ + +/** @addtogroup FMC_Fuctions Fuctions + @{ +*/ + +/** Initialization and Configuration */ +void FMC_ConfigLatency(FMC_LATENCY_T latency); +void FMC_EnableHalfCycleAccess(void); +void FMC_DisableHalfCycleAccess(void); +void FMC_EnablePrefetchBuffer(void); +void FMC_DisablePrefetchBuffer(void); + +/** Lock management */ +void FMC_Unlock(void); +void FMC_Lock(void); + +/** Erase management */ +FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr); +FMC_STATUS_T FMC_EraseAllPage(void); +FMC_STATUS_T FMC_EraseOptionBytes(void); + +/** Read Write management */ +FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data); +FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data); +FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data); +FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page); +FMC_STATUS_T FMC_EnableReadOutProtection(void); +FMC_STATUS_T FMC_DisableReadOutProtection(void); +FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig); +uint32_t FMC_ReadUserOptionByte(void); +uint32_t FMC_ReadOptionByteWriteProtection(void); +uint8_t FMC_GetReadProtectionStatus(void); +uint8_t FMC_ReadPrefetchBufferStatus(void); + +/** Interrupts and flags */ +void FMC_EnableInterrupt(FMC_INT_T interrupt); +void FMC_DisableInterrupt(FMC_INT_T interrupt); +uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag); +void FMC_ClearStatusFlag(FMC_FLAG_T flag); + +/** Status management */ +FMC_STATUS_T FMC_ReadStatus(void); +FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut); + +/**@} end of group FMC_Fuctions*/ +/**@} end of group FMC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_FMC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h new file mode 100644 index 0000000000..e78ac91b01 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h @@ -0,0 +1,247 @@ +/*! + * @file apm32f10x_gpio.h + * + * @brief This file contains all the functions prototypes for the GPIO firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_GPIO_H +#define __APM32F10X_GPIO_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_Enumerations Enumerations + @{ +*/ + +/** + * @brief GPIO Output Maximum frequency selection + */ +typedef enum +{ + GPIO_SPEED_10MHz = 1, + GPIO_SPEED_2MHz, + GPIO_SPEED_50MHz +}GPIO_SPEED_T; + +/** + * @brief Configuration Mode enumeration + */ +typedef enum +{ + GPIO_MODE_ANALOG = 0x0, //!< Analog mode + GPIO_MODE_IN_FLOATING = 0x04, //!< Floating input + GPIO_MODE_IN_PD = 0x28, //!< Input with pull-down + GPIO_MODE_IN_PU = 0x48, //!< Input with pull-up + GPIO_MODE_OUT_PP = 0x80, //!< General purpose output push-pull + GPIO_MODE_OUT_OD = 0x84, //!< General purpose output Open-drain + GPIO_MODE_AF_PP = 0x88, //!< Alternate function output Push-pull + GPIO_MODE_AF_OD = 0x8C, //!< Alternate function output Open-drain +}GPIO_MODE_T; + +/** + * @brief Definition of the GPIO pins + */ +typedef enum +{ + GPIO_PIN_0 = ((uint16_t)BIT0), + GPIO_PIN_1 = ((uint16_t)BIT1), + GPIO_PIN_2 = ((uint16_t)BIT2), + GPIO_PIN_3 = ((uint16_t)BIT3), + GPIO_PIN_4 = ((uint16_t)BIT4), + GPIO_PIN_5 = ((uint16_t)BIT5), + GPIO_PIN_6 = ((uint16_t)BIT6), + GPIO_PIN_7 = ((uint16_t)BIT7), + GPIO_PIN_8 = ((uint16_t)BIT8), + GPIO_PIN_9 = ((uint16_t)BIT9), + GPIO_PIN_10 = ((uint16_t)BIT10), + GPIO_PIN_11 = ((uint16_t)BIT11), + GPIO_PIN_12 = ((uint16_t)BIT12), + GPIO_PIN_13 = ((uint16_t)BIT13), + GPIO_PIN_14 = ((uint16_t)BIT14), + GPIO_PIN_15 = ((uint16_t)BIT15), + GPIO_PIN_ALL = ((uint32_t)0XFFFF), +} GPIO_PIN_T; + +/** + * @brief GPIO remap type define + */ +typedef enum +{ + GPIO_NO_REMAP_SPI1 = 0x00000010, + GPIO_REMAP_SPI1 = 0x00000011, + + GPIO_NO_REMAP_I2C1 = 0x00000110, + GPIO_REMAP_I2C1 = 0x00000111, + + GPIO_NO_REMAP_USART1 = 0x00000210, + GPIO_REMAP_USART1 = 0x00000211, + + GPIO_NO_REMAP_USART2 = 0x00000310, + GPIO_REMAP_USART2 = 0x00000311, + + GPIO_NO_REMAP_USART3 = 0x00000430, + GPIO_PARTIAL_REMAP_USART3 = 0x00000431, + GPIO_FULL_REMAP_USART3 = 0x00000433, + + GPIO_NO_REMAP_TMR1 = 0x00000630, + GPIO_PARTIAL_REMAP_TMR1 = 0x00000631, + GPIO_FULL_REMAP_TMR1 = 0x00000633, + + GPIO_NO_REMAP_TMR2 = 0x00000830, + GPIO_PARTIAL_REMAP1_TMR2 = 0x00000831, + GPIO_PARTIAL_REMAP2_TMR2 = 0x00000832, + GPIO_FULL_REMAP_TMR2 = 0x00000833, + + GPIO_NO_REMAP_TMR3 = 0x00000A30, + GPIO_PARTIAL_REMAP_TMR3 = 0x00000A32, + GPIO_FULL_REMAP_TMR3 = 0x00000A33, + + GPIO_NO_REMAP_TMR4 = 0x00000C10, + GPIO_REMAP_TMR4 = 0x00000C11, + + GPIO_NO_REMAP_CAN1 = 0x00000D30, + GPIO_REMAP1_CAN1 = 0x00000D32, + GPIO_REMAP2_CAN1 = 0x00000D33, + + GPIO_NO_REMAP_PD01 = 0x00000F10, + GPIO_REMAP_PD01 = 0x00000F11, + + GPIO_NO_REMAP_TMR5CH4_LSI = 0x00001010, + GPIO_REMAP_TMR5CH4_LSI = 0x00001011, + + GPIO_NO_REMAP_ADC1_ETRGINJ = 0x00001110, + GPIO_REMAP_ADC1_ETRGINJ = 0x00001111, + + GPIO_NO_REMAP_ADC1_ETRGREG = 0x00001210, + GPIO_REMAP_ADC1_ETRGREG = 0x00001211, + + GPIO_NO_REMAP_ADC2_ETRGINJ = 0x00001310, + GPIO_REMAP_ADC2_ETRGINJ = 0x00001311, + + GPIO_NO_REMAP_ADC2_ETRGREG = 0x00001410, + GPIO_REMAP_ADC2_ETRGREG = 0x00001411, + + GPIO_NO_REMAP_CAN2 = 0x00001610, + GPIO_REMAP_CAN2 = 0x00001611, + + GPIO_NO_REMAP_SWJ = 0x00001870, + GPIO_REMAP_SWJ_NOJTRST = 0x00001871, + GPIO_REMAP_SWJ_JTAGDISABLE = 0x00001872, + GPIO_REMAP_SWJ_DISABLE = 0x00001874, + + GPIO_NO_REMAP_EMMC_NADV = 0x00010A10, + GPIO_REMAP_EMMC_NADV = 0x00010A11, +}GPIO_REMAP_T; + +/** + * @brief gpio port source define + */ +typedef enum +{ + GPIO_PORT_SOURCE_A, + GPIO_PORT_SOURCE_B, + GPIO_PORT_SOURCE_C, + GPIO_PORT_SOURCE_D, + GPIO_PORT_SOURCE_E, + GPIO_PORT_SOURCE_F, + GPIO_PORT_SOURCE_G, +}GPIO_PORT_SOURCE_T; + +/** + * @brief gpio pin source define + */ +typedef enum +{ + GPIO_PIN_SOURCE_0, + GPIO_PIN_SOURCE_1, + GPIO_PIN_SOURCE_2, + GPIO_PIN_SOURCE_3, + GPIO_PIN_SOURCE_4, + GPIO_PIN_SOURCE_5, + GPIO_PIN_SOURCE_6, + GPIO_PIN_SOURCE_7, + GPIO_PIN_SOURCE_8, + GPIO_PIN_SOURCE_9, + GPIO_PIN_SOURCE_10, + GPIO_PIN_SOURCE_11, + GPIO_PIN_SOURCE_12, + GPIO_PIN_SOURCE_13, + GPIO_PIN_SOURCE_14, + GPIO_PIN_SOURCE_15, +}GPIO_PIN_SOURCE_T; + +/**@} end of group GPIO_Enumerations*/ + + +/** @addtogroup GPIO_Structure Data Structure + @{ +*/ + +/** + * @brief GPIO Config structure definition + */ +typedef struct +{ + uint16_t pin; + GPIO_SPEED_T speed; + GPIO_MODE_T mode; +}GPIO_Config_T; + +/**@} end of group GPIO_Structure*/ + +/** @addtogroup GPIO_Fuctions Fuctions + @{ +*/ + +/** Reset and common Configuration */ +void GPIO_Reset(GPIO_T* port); +void GPIO_AFIOReset(void); +void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig); +void GPIO_StructInit(GPIO_Config_T* gpioConfig); + +/** Read */ +uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin); +uint16_t GPIO_ReadInputPort(GPIO_T* port); +uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin); +uint16_t GPIO_ReadOutputPort(GPIO_T* port); + +/** Write */ +void GPIO_SetBits(GPIO_T* port, uint16_t pin); +void GPIO_ResetBits(GPIO_T* port, uint16_t pin); +void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue); +void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal); + +/** GPIO Configuration */ +void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin); +void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); +void GPIO_EnableEventOutput(void); +void GPIO_DisableEventOutput(void); +void GPIO_ConfigPinRemap(GPIO_REMAP_T remap); +void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource); + +/**@} end of group GPIO_Fuctions*/ +/**@} end of group GPIO_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_GPIO_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h new file mode 100644 index 0000000000..49c6537e11 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h @@ -0,0 +1,334 @@ +/*! + * @file apm32f10x_i2c.h + * + * @brief This file contains all the functions prototypes for the I2C firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_I2C_H +#define __APM32F10X_I2C_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_Enumerations Enumerations + @{ +*/ + +/** + * @brief I2C Mode + */ +typedef enum +{ + I2C_MODE_I2C = 0x0000, + I2C_MODE_SMBUUSDEVICE = 0x0002, + I2C_MODE_SMBUSHOST = 0x000A +} I2C_MODE_T; + +/** + * @brief I2C duty cycle in fast mode + */ +typedef enum +{ + I2C_DUTYCYCLE_16_9 = 0x4000, + I2C_DUTYCYCLE_2 = 0xBFFF +} I2C_DUTYCYCLE_T; + +/** + * @brief I2C acknowledgement + */ +typedef enum +{ + I2C_ACK_DISABLE, + I2C_ACK_ENABLE +} I2C_ACK_T; + +/** + * @brief I2C acknowledged address + */ +typedef enum +{ + I2C_ACK_ADDRESS_7BIT = 0x4000, + I2C_ACK_ADDRESS_10BIT = 0xC000 +} I2C_ACK_ADDRESS_T; + +/** + * @brief I2C interrupts definition + */ +typedef enum +{ + I2C_INT_BUF = 0x0400, + I2C_INT_EVT = 0x0200, + I2C_INT_ERR = 0x0100 +} I2C_INT_T; + +/** + * @brief I2C transfer direction + */ + +typedef enum +{ + I2C_DIRECTION_TX, + I2C_DIRECTION_RX +} I2C_DIRECTION_T; + +/** + * @brief I2C Register + */ +typedef enum +{ + I2C_REGISTER_CTRL1, + I2C_REGISTER_CTRL2, + I2C_REGISTER_SADDR1, + I2C_REGISTER_SADDR2, + I2C_REGISTER_DATA, + I2C_REGISTER_STS1, + I2C_REGISTER_STS2, + I2C_REGISTER_CLKCTRL, + I2C_REGISTER_RISETMAX, + I2C_REGISTER_SWITCH +} I2C_REGISTER_T; + +/** + * @brief I2C NCAK position + */ +typedef enum +{ + I2C_NACK_POSITION_NEXT, + I2C_NACK_POSITION_CURRENT +} I2C_NACK_POSITION_T; + +/** + * @brief I2C SMBus alert pin level + */ +typedef enum +{ + I2C_SMBUSALER_LOW, + I2C_SMBUSALER_HIGH +} I2C_SMBUSALER_T; + +/** + * @brief I2C PEC position + */ +typedef enum +{ + I2C_PEC_POSITION_NEXT, + I2C_PEC_POSITION_CURRENT +} I2C_PEC_POSITION_T; + +/** + * @brief I2C Events + */ +typedef enum +{ + /** I2C Master Events */ + /** Event 5: Communication start event */ + I2C_EVENT_MASTER_MODE_SELECT = 0x00030001, //!< BUSBSYFLG, MSFLG and STARTFLG flag + + /** + * Event 6: 7-bit Address Acknowledge + * in case of master receiver + */ + I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = 0x00070082, //!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */ + I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = 0x00030002, //!< BUSBSYFLG, MSFLG and ADDRFLG flags */ + /** + * Event 9: Master has sent the first byte + * in 10-bit address mode + */ + I2C_EVENT_MASTER_MODE_ADDRESS10 = 0x00030008, //!< BUSBSYFLG, MSFLG and ADDR10FLG flags */ + + /** Master RECEIVER mode */ + /** Event 7 */ + I2C_EVENT_MASTER_BYTE_RECEIVED = 0x00030040, //!< BUSBSYFLG, MSFLG and RXBNEFLG flags */ + + /** Master TRANSMITTER mode */ + /** Event 8 */ + I2C_EVENT_MASTER_BYTE_TRANSMITTING = 0x00070080, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */ + /** Event 8_2 */ + I2C_EVENT_MASTER_BYTE_TRANSMITTED = 0x00070084, //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */ + + + /** EV1 (all the events below are variants of EV1) */ + /** 1, Case of One Single Address managed by the slave */ + I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = 0x00020002, //!< BUSBSYFLG and ADDRFLG flags */ + I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = 0x00060082, //!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */ + + /** 2, Case of Dual address managed by the slave */ + I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = 0x00820000, //!< DUALF and BUSBSYFLG flags */ + I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = 0x00860080, //!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */ + + /** 3, Case of General Call enabled for the slave */ + I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = 0x00120000, //!< GENCALL and BUSBSYFLG flags */ + + + /** Slave RECEIVER mode */ + /** EV2 */ + I2C_EVENT_SLAVE_BYTE_RECEIVED = 0x00020040, //!< BUSBSYFLG and RXBNEFLG flags */ + /** EV4 */ + I2C_EVENT_SLAVE_STOP_DETECTED = 0x00000010, //!< STOPFLG flag */ + + /** Slave TRANSMITTER mode */ + /** EV3 */ + I2C_EVENT_SLAVE_BYTE_TRANSMITTED = 0x00060084, //!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */ + I2C_EVENT_SLAVE_BYTE_TRANSMITTING = 0x00060080, //!< TRFLG, BUSBSYFLG and TXBEFLG flags */ + /** EV3_2 */ + I2C_EVENT_SLAVE_ACK_FAILURE = 0x00000400, //!< AEFLG flag */ +} I2C_EVENT_T; + +/** + * @brief I2C flags + */ +typedef enum +{ + /** STS2 register flags */ + I2C_FLAG_DUALADDR, + I2C_FLAG_SMMHADDR, + I2C_FLAG_SMBDADDR, + I2C_FLAG_GENCALL, + I2C_FLAG_TR, + I2C_FLAG_BUSBSY, + I2C_FLAG_MS, + + /** STS1 register flags */ + I2C_FLAG_SMBALT, + I2C_FLAG_TTE, + I2C_FLAG_PECE, + I2C_FLAG_OVRUR, + I2C_FLAG_AE, + I2C_FLAG_AL, + I2C_FLAG_BERR, + I2C_FLAG_TXBE, + I2C_FLAG_RXBNE, + I2C_FLAG_STOP, + I2C_FLAG_ADDR10, + I2C_FLAG_BTC, + I2C_FLAG_ADDR, + I2C_FLAG_START, +} I2C_FLAG_T; + +/** + * @brief I2C interrupt + */ +typedef enum +{ + I2C_INT_FLAG_SMBALT = 0x01008000, + I2C_INT_FLAG_TTE = 0x01004000, + I2C_INT_FLAG_PECE = 0x01001000, + I2C_INT_FLAG_OVRUR = 0x01000800, + I2C_INT_FLAG_AE = 0x01000400, + I2C_INT_FLAG_AL = 0x01000200, + I2C_INT_FLAG_BERR = 0x01000100, + I2C_INT_FLAG_TXBE = 0x06000080, + I2C_INT_FLAG_RXBNE = 0x06000040, + I2C_INT_FLAG_STOP = 0x02000010, + I2C_INT_FLAG_ADDR10 = 0x02000008, + I2C_INT_FLAG_BTC = 0x02000004, + I2C_INT_FLAG_ADDR = 0x02000002, + I2C_INT_FLAG_START = 0x02000001, +} I2C_INT_FLAG_T; + +/**@} end of group I2C_Enumerations*/ + +/** @addtogroup I2C_Structure Data Structure + @{ +*/ + +/** + * @brief I2C Config structure definition + */ +typedef struct +{ + uint32_t clockSpeed; + I2C_MODE_T mode; + I2C_DUTYCYCLE_T dutyCycle; + uint16_t ownAddress1; + I2C_ACK_T ack; + I2C_ACK_ADDRESS_T ackAddress; +} I2C_Config_T; + +/**@} end of group I2C_Structure*/ + + +/** @addtogroup I2C_Fuctions Fuctions + @{ +*/ + +/** I2C reset and configuration */ +void I2C_Reset(I2C_T* i2c); +void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig); +void I2C_ConfigStructInit(I2C_Config_T* i2cConfig); +void I2C_Enable(I2C_T* i2c); +void I2C_Disable(I2C_T* i2c); +void I2C_EnableGenerateStart(I2C_T* i2c); +void I2C_DisableGenerateStart(I2C_T* i2c); +void I2C_EnableGenerateStop(I2C_T* i2c); +void I2C_DisableGenerateStop(I2C_T* i2c); +void I2C_EnableAcknowledge(I2C_T* i2c); +void I2C_DisableAcknowledge(I2C_T* i2c); +void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address); +void I2C_EnableDualAddress(I2C_T* i2c); +void I2C_DisableDualAddress(I2C_T* i2c); +void I2C_EnableGeneralCall(I2C_T* i2c); +void I2C_DisableGeneralCall(I2C_T* i2c); + +/** Transmit Configuration */ +void I2C_TxData(I2C_T* i2c, uint8_t data); +uint8_t I2C_RxData(I2C_T* i2c); +void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction); +uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister); +void I2C_EnableSoftwareReset(I2C_T* i2c); +void I2C_DisableSoftwareReset(I2C_T* i2c); +void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition); +void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState); +void I2C_EnablePECTransmit(I2C_T* i2c); +void I2C_DisablePECTransmit(I2C_T* i2c); +void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition); +void I2C_EnablePEC(I2C_T* i2c); +void I2C_DisablePEC(I2C_T* i2c); +uint8_t I2C_ReadPEC(I2C_T* i2c); +void I2C_EnableARP(I2C_T* i2c); +void I2C_DisableARP(I2C_T* i2c); +void I2C_EnableStretchClock(I2C_T* i2c); +void I2C_DisableStretchClock(I2C_T* i2c); +void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle); + +/** DMA */ +void I2C_EnableDMA(I2C_T* i2c); +void I2C_DisableDMA(I2C_T* i2c); +void I2C_EnableDMALastTransfer(I2C_T* i2c); +void I2C_DisableDMALastTransfer(I2C_T* i2c); + +/** Interrupts and flags */ +void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt); +void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt); +uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent); +uint32_t I2C_ReadLastEvent(I2C_T* i2c); +uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); +void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag); +uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); +void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag); + +/**@} end of group I2C_Fuctions*/ +/**@} end of group I2C_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_I2C_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h new file mode 100644 index 0000000000..45c2c34c4d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h @@ -0,0 +1,108 @@ +/*! + * @file apm32f10x_iwdt.h + * + * @brief This file contains all the functions prototypes for the IWDT firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_IWDT_H +#define __APM32F10X_IWDT_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup IWDT_Driver IWDT Driver + @{ +*/ + +/** @addtogroup IWDT_Enumerations Enumerations + @{ +*/ + +/** + * @brief IWDT KEYWORD define + */ +typedef enum +{ + IWDT_KEYWORD_RELOAD = 0xAAAA, + IWDT_KEYWORD_ENABLE = 0xCCCC +}IWDT_KEYWORD_T; + +/** + * @brief IWDT Write Access define + */ +typedef enum +{ + IWDT_WRITEACCESS_ENABLE = 0x5555, + IWDT_WRITEACCESS_DISABLE = 0x0000 +}IWDT_WRITEACCESS_T; + +/** + * @brief IWDT Divider + */ +typedef enum +{ + IWDT_DIVIDER_4 = 0x00, + IWDT_DIVIDER_8 = 0x01, + IWDT_DIVIDER_16 = 0x02, + IWDT_DIVIDER_32 = 0x03, + IWDT_DIVIDER_64 = 0x04, + IWDT_DIVIDER_128 = 0x05, + IWDT_DIVIDER_256 = 0x06 +}IWDT_DIVIDER_T; + +/** + * @brief IWDT Flag + */ +typedef enum +{ + IWDT_FLAG_PSCU = BIT0, + IWDT_FLAG_CNTU = BIT1 +}IWDT_FLAG_T; + +/**@} end of group IWDT_Enumerations*/ + + +/** @addtogroup IWDT_Fuctions Fuctions + @{ +*/ + +/** Enable IWDT */ +void IWDT_Enable(void); + +/** Refresh IWDT */ +void IWDT_Refresh(void); + +/** Counter reload */ +void IWDT_ConfigReload(uint16_t reload); + +/** Divider */ +void IWDT_ConfigDivider(uint8_t div); + +/** Write Access */ +void IWDT_EnableWriteAccess(void); +void IWDT_DisableWriteAccess(void); + +/** flag */ +uint8_t IWDT_ReadStatusFlag(uint16_t flag); + +/**@} end of group IWDT_Fuctions*/ +/**@} end of group IWDT_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_IWDT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h new file mode 100644 index 0000000000..fbc8171da0 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h @@ -0,0 +1,100 @@ +/*! + * @file apm32f10x_misc.h + * + * @brief This file provides all the miscellaneous firmware functions. + * Include NVIC,SystemTick and Power management. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_MISC_H +#define __APM32F10X_MISC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup MISC_Driver MISC Driver + @{ +*/ + +/** @addtogroup MISC_Enumerations Enumerations + @{ +*/ + +/** + * @brief NVIC Vect table + */ +typedef enum +{ + NVIC_VECT_TAB_RAM = 0x20000000, + NVIC_VECT_TAB_FLASH = 0x08000000, +}NVIC_VECT_TAB_T; + +/** + * @brief system low power mode + */ +typedef enum +{ + NVIC_LOWPOWER_SEVONPEND = 0x10, + NVIC_LOWPOWER_SLEEPDEEP = 0x04, + NVIC_LOWPOWER_SLEEPONEXIT = 0x02 +}NVIC_LOWPOWER_T; + +/** + * @brief nvic priority group + */ +typedef enum +{ + NVIC_PRIORITY_GROUP_0 = 0x700, //!< 0 bits for pre-emption priority,4 bits for subpriority + NVIC_PRIORITY_GROUP_1 = 0x600, //!< 1 bits for pre-emption priority,3 bits for subpriority + NVIC_PRIORITY_GROUP_2 = 0x500, //!< 2 bits for pre-emption priority,2 bits for subpriority + NVIC_PRIORITY_GROUP_3 = 0x400, //!< 3 bits for pre-emption priority,1 bits for subpriority + NVIC_PRIORITY_GROUP_4 = 0x300 //!< 4 bits for pre-emption priority,0 bits for subpriority +}NVIC_PRIORITY_GROUP_T; + +/** + * @brief SysTick Clock source + */ +typedef enum +{ + SYSTICK_CLK_SOURCE_HCLK_DIV8 = 0x00, + SYSTICK_CLK_SOURCE_HCLK = 0x01 +}SYSTICK_CLK_SOURCE_T; + +/**@} end of group MISC_Enumerations*/ + + +/** @addtogroup MISC_Fuctions Fuctions + @{ +*/ + +/** NVIC */ +void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup); +void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority); +void NVIC_DisableIRQRequest(IRQn_Type irq); + +/** Vector Table */ +void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset); + +/** Power */ +void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode); +void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode); + +/** Systick */ +void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_MISC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h new file mode 100644 index 0000000000..873686a220 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h @@ -0,0 +1,97 @@ +/*! + * @file apm32f10x_pmu.h + * + * @brief This file contains all the functions prototypes for the PMU firmware library. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_PMU_H +#define __APM32F10X_PMU_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup PMU_Driver PMU Driver + @{ +*/ + +/** @addtogroup PMU_Enumerations Enumerations + @{ +*/ + +typedef enum +{ + PMU_PVD_LEVEL_2V2 = 0x00, //!< PVD detection level set to 2.2V + PMU_PVD_LEVEL_2V3 = 0x01, //!< PVD detection level set to 2.3V + PMU_PVD_LEVEL_2V4 = 0x02, //!< PVD detection level set to 2.4V + PMU_PVD_LEVEL_2V5 = 0x03, //!< PVD detection level set to 2.5V + PMU_PVD_LEVEL_2V6 = 0x04, //!< PVD detection level set to 2.6V + PMU_PVD_LEVEL_2V7 = 0x05, //!< PVD detection level set to 2.7V + PMU_PVD_LEVEL_2V8 = 0x06, //!< PVD detection level set to 2.8V + PMU_PVD_LEVEL_2V9 = 0x07, //!< PVD detection level set to 2.9V +} PMU_PVD_LEVEL_T; + +typedef enum +{ + PMU_REGULATOR_ON = 0x00, + PMU_REGULATOR_LOWPOWER = 0x01 +} PMU_REGULATOR_T; + +typedef enum +{ + PMU_STOP_ENTRY_WFI = 0x01, + PMU_STOP_ENTRY_WFE = 0x02 +} PMU_STOP_ENTRY_T; + +typedef enum +{ + PMU_FLAG_WUE, + PMU_FLAG_SB, + PMU_FLAG_PVDO +} PMU_FLAG_T; + +/**@} end of group PMU_Enumerations*/ + + +/** @addtogroup PMU_Fuctions Fuctions + @{ +*/ + +/** PMU Reset */ +void PMU_Reset(void); + +/** Configuration and Operation modes */ +void PMU_EnableBackupAccess(void); +void PMU_DisableBackupAccess(void); +void PMU_EnablePVD(void); +void PMU_DisablePVD(void); +void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level); +void PMU_EnableWakeUpPin(void); +void PMU_DisableWakeUpPin(void); +void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry); +void PMU_EnterSTANDBYMode(void); + +/** flags */ +uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag); +void PMU_ClearStatusFlag(PMU_FLAG_T flag); + +/**@} end of group PMU_Fuctions*/ +/**@} end of group PMU_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_PMU_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h new file mode 100644 index 0000000000..8a373eb326 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h @@ -0,0 +1,337 @@ +/*! + * @file apm32f10x_qspi.h + * + * @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_QSPI_H +#define __APM32F10X_QSPI_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_Enumerations Enumerations + @{ +*/ + +/** + * @brief Frame format + */ +typedef enum +{ + QSPI_FRF_STANDARD, //!< Standard mode + QSPI_FRF_DUAL, //!< Dual SPI + QSPI_FRF_QUAD //!< QUAD SPI +}QSPI_FRF_T; + +/** + * @brief Transmission mode + */ +typedef enum +{ + QSPI_TRANS_MODE_TX_RX, //!< TX and RX mode + QSPI_TRANS_MODE_TX, //!< TX mode only + QSPI_TRANS_MODE_RX, //!< RX mode only + QSPI_TRANS_MODE_EEPROM_READ, //!< EEPROM read mode +}QSPI_TRANS_MODE_T; + +/** + * @brief Clock polarity + */ +typedef enum +{ + QSPI_CLKPOL_LOW, + QSPI_CLKPOL_HIGH, +}QSPI_CLKPOL_T; + +/** + * @brief Clock phase + */ +typedef enum +{ + QSPI_CLKPHA_1EDGE, + QSPI_CLKPHA_2EDGE +}QSPI_CLKPHA_T; + +/** + * @brief Data format size + */ +typedef enum +{ + QSPI_DFS_4BIT = 3, + QSPI_DFS_5BIT, + QSPI_DFS_6BIT, + QSPI_DFS_7BIT, + QSPI_DFS_8BIT, + QSPI_DFS_9BIT, + QSPI_DFS_10BIT, + QSPI_DFS_11BIT, + QSPI_DFS_12BIT, + QSPI_DFS_13BIT, + QSPI_DFS_14BIT, + QSPI_DFS_15BIT, + QSPI_DFS_16BIT, + QSPI_DFS_17BIT, + QSPI_DFS_18BIT, + QSPI_DFS_19BIT, + QSPI_DFS_20BIT, + QSPI_DFS_21BIT, + QSPI_DFS_22BIT, + QSPI_DFS_23BIT, + QSPI_DFS_24BIT, + QSPI_DFS_25BIT, + QSPI_DFS_26BIT, + QSPI_DFS_27BIT, + QSPI_DFS_28BIT, + QSPI_DFS_29BIT, + QSPI_DFS_30BIT, + QSPI_DFS_31BIT, + QSPI_DFS_32BIT, +}QSPI_DFS_T; + +/** + * @brief QSPI flag + */ +typedef enum +{ + QSPI_FLAG_BUSY = BIT0, //!< Busy flag + QSPI_FLAG_TFNF = BIT1, //!< TX FIFO not full flag + QSPI_FLAG_TFE = BIT2, //!< TX FIFO empty flag + QSPI_FLAG_RFNE = BIT3, //!< RX FIFO not empty flag + QSPI_FLAG_RFF = BIT4, //!< RX FIFO full flag + QSPI_FLAG_DCE = BIT6 //!< Data collision error +}QSPI_FLAG_T; + +/** + * @brief QSPI interrupt source + */ +typedef enum +{ + QSPI_INT_TFE = BIT0, //!< TX FIFO empty interrupt + QSPI_INT_TFO = BIT1, //!< TX FIFO overflow interrupt + QSPI_INT_RFU = BIT2, //!< RX FIFO underflow interrupt + QSPI_INT_RFO = BIT3, //!< RX FIFO overflow interrupt + QSPI_INT_RFF = BIT4, //!< RX FIFO full interrupt + QSPI_INT_MST = BIT5, //!< Master interrupt +}QSPI_INT_T; + +/** + * @brief QSPI interrupt flag + */ +typedef enum +{ + QSPI_INT_FLAG_TFE = BIT0, //!< TX FIFO empty interrupt flag + QSPI_INT_FLAG_TFO = BIT1, //!< TX FIFO overflow interrupt flag + QSPI_INT_FLAG_RFU = BIT2, //!< RX FIFO underflow interrupt flag + QSPI_INT_FLAG_RFO = BIT3, //!< RX FIFO overflow interrupt flag + QSPI_INT_FLAG_RFF = BIT4, //!< RX FIFO full interrupt flag + QSPI_INT_FLAG_MST = BIT5, //!< Master interrupt flag +}QSPI_INT_FLAG_T; + +/** + * @brief Reception sample edge + */ +typedef enum +{ + QSPI_RSE_RISING, + QSPI_RSE_FALLING +}QSPI_RSE_T; + +/** + * @brief Instruction length + */ +typedef enum +{ + QSPI_INST_LEN_0, + QSPI_INST_LEN_4BIT, + QSPI_INST_LEN_8BIT, + QSPI_INST_LEN_16BIT, +}QSPI_INST_LEN_T; + +/** + * @brief QSPI address length + */ +typedef enum +{ + QSPI_ADDR_LEN_0, + QSPI_ADDR_LEN_4BIT, + QSPI_ADDR_LEN_8BIT, + QSPI_ADDR_LEN_12BIT, + QSPI_ADDR_LEN_16BIT, + QSPI_ADDR_LEN_20BIT, + QSPI_ADDR_LEN_24BIT, + QSPI_ADDR_LEN_28BIT, + QSPI_ADDR_LEN_32BIT, + QSPI_ADDR_LEN_36BIT, + QSPI_ADDR_LEN_40BIT, + QSPI_ADDR_LEN_44BIT, + QSPI_ADDR_LEN_48BIT, + QSPI_ADDR_LEN_52BIT, + QSPI_ADDR_LEN_56BIT, + QSPI_ADDR_LEN_60BIT, +}QSPI_ADDR_LEN_T; + +/** + * @brief Instruction and address transmission mode + */ +typedef enum +{ + QSPI_INST_ADDR_TYPE_STANDARD, + QSPI_INST_TYPE_STANDARD, + QSPI_INST_ADDR_TYPE_FRF, +}QSPI_INST_ADDR_TYPE_T; + +/** + * @brief Slave Select Toggle + */ +typedef enum +{ + QSPI_SST_DISABLE, + QSPI_SST_ENABLE, +}QSPI_SST_T; + +/**@} end of group QSPI_Enumerations*/ + +/** @addtogroup QSPI_Macros Macros + @{ +*/ + +/** CTRL1 register reset value */ +#define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007) +/** CTRL2 register reset value */ +#define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00) +/** SSIEN register reset value */ +#define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00) +/** SLAEN register reset value */ +#define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00) +/** BR register reset value */ +#define QSPI_BR_RESET_VALUE ((uint32_t)0x00) +/** TFTL register reset value */ +#define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00) +/** RFTL register reset value */ +#define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00) +/** TFL register reset value */ +#define QSPI_TFL_RESET_VALUE ((uint32_t)0x00) +/** RFL register reset value */ +#define QSPI_RFL_RESET_VALUE ((uint32_t)0x00) +/** STS register reset value */ +#define QSPI_STS_RESET_VALUE ((uint32_t)0x06) +/** INTEN register reset value */ +#define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F) +/** RSD register reset value */ +#define QSPI_RSD_RESET_VALUE ((uint32_t)0x00) +/** CTRL3 register reset value */ +#define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200) +/** IOSW register reset value */ +#define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00) + +/**@} end of group QSPI_Macros*/ + + +/** @addtogroup QSPI_Structure Data Structure + @{ +*/ +typedef struct +{ + QSPI_SST_T selectSlaveToggle; //!< Slave Select Toggle + QSPI_FRF_T frameFormat; //!< Frame format + uint16_t clockDiv; //!< Clock divider + QSPI_CLKPOL_T clockPolarity; //!< Clock polarity + QSPI_CLKPHA_T clockPhase; //!< Clock phase + QSPI_DFS_T dataFrameSize; //!< Data frame size +}QSPI_Config_T; + +/**@} end of group QSPI_Structure*/ + + +/** @addtogroup QSPI_Fuctions Fuctions + @{ +*/ + +/** Reset */ +void QSPI_Reset(void); + +/** Configuration */ +void QSPI_Config(QSPI_Config_T *qspiConfig); +void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig); + +/** Data frame size, frame number, frame format */ +void QSPI_ConfigFrameNum(uint16_t num); +void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs); +void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat); + +/** Disable or Enable */ +void QSPI_Enable(void); +void QSPI_Disable(void); + +/** TX and RX FIFO */ +uint8_t QSPI_ReadTxFifoDataNum(void); +uint8_t QSPI_ReadRxFifoDataNum(void); +void QSPI_ConfigRxFifoThreshold(uint8_t threshold); +void QSPI_ConfigTxFifoThreshold(uint8_t threshold); +void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold); + +/** RX Sample */ +void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse); +void QSPI_ConfigRxSampleDelay(uint8_t delay); + +/** Clock stretch */ +void QSPI_EnableClockStretch(void); +void QSPI_DisableClockStretch(void); + +/** Instruction, address, Wait cycle */ +void QSPI_ConfigInstLen(QSPI_INST_LEN_T len); +void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len); +void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type); +void QSPI_ConfigWaitCycle(uint8_t cycle); + +/** IO */ +void QSPI_OpenIO(void); +void QSPI_CloseIO(void); + +/** Transmission mode */ +void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode); + +/** Rx and Tx data */ +uint32_t QSPI_RxData(void); +void QSPI_TxData(uint32_t data); + +/** Slave */ +void QSPI_EnableSlave(void); +void QSPI_DisableSlave(void); + +/** Interrupt */ +void QSPI_EnableInterrupt(uint32_t interrupt); +void QSPI_DisableInterrupt(uint32_t interrupt); + +/** Flag */ +uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag); +void QSPI_ClearStatusFlag(void); +uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag); +void QSPI_ClearIntFlag(uint32_t flag); + +/**@} end of group QSPI_Fuctions*/ +/**@} end of group QSPI_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_QSPI_H_ */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h new file mode 100644 index 0000000000..0d4ba102fa --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h @@ -0,0 +1,365 @@ +/*! + * @file apm32f10x_rcm.h + * + * @brief This file contains all the functions prototypes for the RCM firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_RCM_H +#define __APM32F10X_RCM_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RCM_Driver RCM Driver + @{ +*/ + +/** @addtogroup RCM_Enumerations Enumerations + @{ +*/ + +/** + * @brief HSE state + */ +typedef enum +{ + RCM_HSE_CLOSE, //!< CLOSE HSE + RCM_HSE_OPEN, //!< OPEN HSE + RCM_HSE_BYPASS, //!< HSE BYPASS +} RCM_HSE_T; + +/** + * @brief PLL multiplication factor + */ +typedef enum +{ + RCM_PLLMF_2, + RCM_PLLMF_3, + RCM_PLLMF_4, + RCM_PLLMF_5, + RCM_PLLMF_6, + RCM_PLLMF_7, + RCM_PLLMF_8, + RCM_PLLMF_9, + RCM_PLLMF_10, + RCM_PLLMF_11, + RCM_PLLMF_12, + RCM_PLLMF_13, + RCM_PLLMF_14, + RCM_PLLMF_15, + RCM_PLLMF_16, +} RCM_PLLMF_T; + +/** + * @brief System clock select + */ +typedef enum +{ + RCM_SYSCLK_SEL_HSI, + RCM_SYSCLK_SEL_HSE, + RCM_SYSCLK_SEL_PLL +} RCM_SYSCLK_SEL_T; + +/** + * @brief AHB divider Number + */ +typedef enum +{ + RCM_AHB_DIV_1 = 7, + RCM_AHB_DIV_2, + RCM_AHB_DIV_4, + RCM_AHB_DIV_8, + RCM_AHB_DIV_16, + RCM_AHB_DIV_64, + RCM_AHB_DIV_128, + RCM_AHB_DIV_256, + RCM_AHB_DIV_512, +} RCM_AHB_DIV_T; + +/** + * @brief APB divider Number + */ +typedef enum +{ + RCM_APB_DIV_1 = 3, + RCM_APB_DIV_2, + RCM_APB_DIV_4, + RCM_APB_DIV_8, + RCM_APB_DIV_16 +} RCM_APB_DIV_T; + +/** + * @brief USB divider Number + */ +typedef enum +{ + RCM_USB_DIV_1_5, + RCM_USB_DIV_1, + RCM_USB_DIV_2, + RCM_USB_DIV_2_5 //!< (Only for High-density devices for APM32F103xx) +} RCM_USB_DIV_T; + +/** + * @brief FPU divider Number + */ +typedef enum +{ + RCM_FPU_DIV_1, + RCM_FPU_DIV_2, +} RCM_FPU_DIV_T; + +/** + * @brief ADC divider Number + */ +typedef enum +{ + RCM_PCLK2_DIV_2, + RCM_PCLK2_DIV_4, + RCM_PCLK2_DIV_6, + RCM_PCLK2_DIV_8, +} RCM_PCLK2_DIV_T; + +/** + * @brief LSE State + */ +typedef enum +{ + RCM_LSE_CLOSE, + RCM_LSE_OPEN, + RCM_LSE_BYPASS +} RCM_LSE_T; + +/** + * @brief RTC clock select + */ +typedef enum +{ + RCM_RTCCLK_LSE = 1, + RCM_RTCCLK_LSI, + RCM_RTCCLK_HSE_DIV_128 +} RCM_RTCCLK_T; + +/** + * @brief Clock output control + */ +typedef enum +{ + RCM_MCOCLK_NO_CLOCK = 3, + RCM_MCOCLK_SYSCLK, + RCM_MCOCLK_HSI, + RCM_MCOCLK_HSE, + RCM_MCOCLK_PLLCLK_DIV_2, +} RCM_MCOCLK_T; + +/** + * @brief PLL entry clock select + */ +typedef enum +{ + RCM_PLLSEL_HSI_DIV_2 = 0, + RCM_PLLSEL_HSE = 1, + RCM_PLLSEL_HSE_DIV2 = 3, +} RCM_PLLSEL_T; + +/** + * @brief RCM Interrupt Source + */ +typedef enum +{ + RCM_INT_LSIRDY = BIT0, //!< LSI ready interrupt + RCM_INT_LSERDY = BIT1, //!< LSE ready interrupt + RCM_INT_HSIRDY = BIT2, //!< HSI ready interrupt + RCM_INT_HSERDY = BIT3, //!< HSE ready interrupt + RCM_INT_PLLRDY = BIT4, //!< PLL ready interrupt + RCM_INT_CSS = BIT7 //!< Clock security system interrupt +} RCM_INT_T; + +/** + * @brief AHB peripheral + */ +typedef enum +{ + RCM_AHB_PERIPH_DMA1 = BIT0, + RCM_AHB_PERIPH_DMA2 = BIT1, + RCM_AHB_PERIPH_SRAM = BIT2, + RCM_AHB_PERIPH_FPU = BIT3, + RCM_AHB_PERIPH_FMC = BIT4, + RCM_AHB_PERIPH_QSPI = BIT5, + RCM_AHB_PERIPH_CRC = BIT6, + RCM_AHB_PERIPH_EMMC = BIT8, + RCM_AHB_PERIPH_SDIO = BIT10, +} RCM_AHB_PERIPH_T; + +/** + * @brief AHB2 peripheral + */ +typedef enum +{ + RCM_APB2_PERIPH_AFIO = BIT0, + RCM_APB2_PERIPH_GPIOA = BIT2, + RCM_APB2_PERIPH_GPIOB = BIT3, + RCM_APB2_PERIPH_GPIOC = BIT4, + RCM_APB2_PERIPH_GPIOD = BIT5, + RCM_APB2_PERIPH_GPIOE = BIT6, + RCM_APB2_PERIPH_GPIOF = BIT7, + RCM_APB2_PERIPH_GPIOG = BIT8, + RCM_APB2_PERIPH_ADC1 = BIT9, + RCM_APB2_PERIPH_ADC2 = BIT10, + RCM_APB2_PERIPH_TMR1 = BIT11, + RCM_APB2_PERIPH_SPI1 = BIT12, + RCM_APB2_PERIPH_TMR8 = BIT13, + RCM_APB2_PERIPH_USART1 = BIT14, + RCM_APB2_PERIPH_ADC3 = BIT15, +} RCM_APB2_PERIPH_T; + +/** + * @brief AHB1 peripheral + */ +typedef enum +{ + RCM_APB1_PERIPH_TMR2 = BIT0, + RCM_APB1_PERIPH_TMR3 = BIT1, + RCM_APB1_PERIPH_TMR4 = BIT2, + RCM_APB1_PERIPH_TMR5 = BIT3, + RCM_APB1_PERIPH_TMR6 = BIT4, + RCM_APB1_PERIPH_TMR7 = BIT5, + RCM_APB1_PERIPH_WWDT = BIT11, + RCM_APB1_PERIPH_SPI2 = BIT14, + RCM_APB1_PERIPH_SPI3 = BIT15, + RCM_APB1_PERIPH_USART2 = BIT17, + RCM_APB1_PERIPH_USART3 = BIT18, + RCM_APB1_PERIPH_UART4 = BIT19, + RCM_APB1_PERIPH_UART5 = BIT20, + RCM_APB1_PERIPH_I2C1 = BIT21, + RCM_APB1_PERIPH_I2C2 = BIT22, + RCM_APB1_PERIPH_USB = BIT23, + RCM_APB1_PERIPH_CAN1 = BIT25, + RCM_APB1_PERIPH_CAN2 = BIT26, + RCM_APB1_PERIPH_BAKR = BIT27, + RCM_APB1_PERIPH_PMU = BIT28, + RCM_APB1_PERIPH_DAC = BIT29, +} RCM_APB1_PERIPH_T; + +/** + * @brief RCM FLAG define + */ +typedef enum +{ + RCM_FLAG_HSIRDY = 0x001, //!< HSI Ready Flag + RCM_FLAG_HSERDY = 0x011, //!< HSE Ready Flag + RCM_FLAG_PLLRDY = 0x019, //!< PLL Ready Flag + RCM_FLAG_LSERDY = 0x101, //!< LSE Ready Flag + RCM_FLAG_LSIRDY = 0x201, //!< LSI Ready Flag + RCM_FLAG_PINRST = 0x21A, //!< PIN reset flag + RCM_FLAG_PORRST = 0x21B, //!< POR/PDR reset flag + RCM_FLAG_SWRST = 0x21C, //!< Software reset flag + RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag + RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag + RCM_FLAG_LPRRST = 0x21F, //!< Low-power reset flag +} RCM_FLAG_T; + +/**@} end of group RCM_Enumerations*/ + + +/** @addtogroup RCM_Fuctions Fuctions + @{ +*/ + +/** Function description */ + +/** RCM Reset */ +void RCM_Reset(void); + +/** HSE clock */ +void RCM_ConfigHSE(RCM_HSE_T state); +uint8_t RCM_WaitHSEReady(void); + +/** HSI clock */ +void RCM_SetHSITrim(uint8_t HSITrim); +void RCM_EnableHSI(void); +void RCM_DisableHSI(void); + +/** LSE and LSI clock */ +void RCM_ConfigLSE(RCM_LSE_T state); +void RCM_EnableLSI(void); +void RCM_DisableLSI(void); + +/** PLL clock */ +void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf); +void RCM_EnablePLL(void); +void RCM_DisablePLL(void); + +/** Clock Security System */ +void RCM_EnableCSS(void); +void RCM_DisableCSS(void); + +void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock); +void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect); +RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void); + +/** Config clock prescaler of AHB, APB1, APB2, USB and ADC */ +void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv); +void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div); +void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div); +void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv); +void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv); +void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv); + +/** RTC clock */ +void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect); +void RCM_EnableRTCCLK(void); +void RCM_DisableRTCCLK(void); + +/** Reads the clock frequency */ +uint32_t RCM_ReadSYSCLKFreq(void); +uint32_t RCM_ReadHCLKFreq(void); +void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2); +uint32_t RCM_ReadADCCLKFreq(void); + +/** Enable or disable Periph Clock */ +void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph); +void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph); +void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph); +void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph); +void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph); +void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph); + +/** Enable or disable Periph Reset */ +void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph); +void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph); +void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph); +void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph); + +/** Backup domain reset */ +void RCM_EnableBackupReset(void); +void RCM_DisableBackupReset(void); + +/** Interrupts and flags */ +void RCM_EnableInterrupt(uint32_t interrupt); +void RCM_DisableInterrupt(uint32_t interrupt); +uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag); +void RCM_ClearStatusFlag(void); +uint8_t RCM_ReadIntFlag(RCM_INT_T flag); +void RCM_ClearIntFlag(uint32_t flag); + +/**@} end of group RCM_Fuctions*/ +/**@} end of group RCM_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_RCM_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h new file mode 100644 index 0000000000..5e243794f6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h @@ -0,0 +1,85 @@ +/*! + * @file apm32f10x_rtc.h + * + * @brief This file contains all the functions prototypes for the RTC firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_RTC_H +#define __APM32F10X_RTC_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_Enumerations Enumerations + @{ +*/ + +typedef enum +{ + RTC_FLAG_OC = 0x0020, //!< RTC Operation Complete flag + RTC_FLAG_RSYNC = 0x0008, //!< Registers Synchronized flag + RTC_FLAG_OVR = 0x0004, //!< Overflow flag + RTC_FLAG_ALR = 0x0002, //!< Alarm flag + RTC_FLAG_SEC = 0x0001 //!< Second flag +} RTC_FLAG_T; + +typedef enum +{ + RTC_INT_OVR = 0x0004, //!< Overflow interrupt + RTC_INT_ALR = 0x0002, //!< Alarm interrupt + RTC_INT_SEC = 0x0001 //!< Second interrupt +} RTC_INT_T; + +/**@} end of group RTC_Enumerations*/ + + +/** @addtogroup RTC_Fuctions Fuctions + @{ +*/ + +/** Operation modes */ +void RTC_EnableConfigMode(void); +void RTC_DisableConfigMode(void); + +/** Configuration */ +uint32_t RTC_ReadCounter(void); +void RTC_ConfigCounter(uint32_t value); +void RTC_ConfigPrescaler(uint32_t value); +void RTC_ConfigAlarm(uint32_t value); +uint32_t RTC_ReadDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchor(void); + +/** Interrupts and flags */ +void RTC_EnableInterrupt(uint16_t interrupt); +void RTC_DisableInterrupt(uint16_t interrupt); +uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag); +void RTC_ClearStatusFlag(uint16_t flag); +uint8_t RTC_ReadIntFlag(RTC_INT_T flag); +void RTC_ClearIntFlag(uint16_t flag); + +/**@} end of group RTC_Fuctions*/ +/**@} end of group RTC_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_RTC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h new file mode 100644 index 0000000000..fe6e1a6138 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h @@ -0,0 +1,311 @@ +/*! + * @file apm32f10x_sci2c.h + * + * @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_SCI2C_H +#define __APM32F10X_SCI2C_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SCI2C_Driver SCI2C Driver + @{ +*/ + +/** @addtogroup SCI2C_Enumerations Enumerations + @{ +*/ + +/** + * @brief SCI2C speed enumeration + */ +typedef enum +{ + SCI2C_SPEED_STANDARD = 1, + SCI2C_SPEED_FAST, + SCI2C_SPEED_HIGH +}SCI2C_SPEED_T; + +/** + * @brief Address mode + */ +typedef enum +{ + SCI2C_ADDR_MODE_7BIT, + SCI2C_ADDR_MODE_10BIT +}SCI2C_ADDR_MODE_T; + +/** + * @brief SCI2C mode enumeration + */ +typedef enum +{ + SCI2C_MODE_MASTER, + SCI2C_MODE_SLAVE +}SCI2C_MODE_T; + +/** + * @brief Restart enable or disable + */ +typedef enum +{ + SCI2C_RESTART_DISABLE, + SCI2C_RESTART_ENABLE +}SCI2C_RESTART_T; + +/** + * @brief Enable or disable generate stop condition + */ +typedef enum +{ + SCI2C_STOP_DISABLE, + SCI2C_STOP_ENABLE +}SCI2C_STOP_T; +/** + * @brief Data direction + */ +typedef enum +{ + SCI2C_DATA_DIR_WRITE, + SCI2C_DATA_DIR_READ, +}SCI2C_DATA_DIR_T; + +/** + * @brief SCI2C interrupt + */ +typedef enum +{ + SCI2C_INT_RFU = BIT0, //!< Rx FIFO underflow interrupt + SCI2C_INT_RFO = BIT1, //!< Rx FIFO onverflow interrupt + SCI2C_INT_RFF = BIT2, //!< Rx FIFO full interrupt + SCI2C_INT_TFO = BIT3, //!< Tx FIFO onverflow interrupt + SCI2C_INT_TFE = BIT4, //!< Tx FIFO empty interrupt + SCI2C_INT_RR = BIT5, //!< Read request interrupt + SCI2C_INT_TA = BIT6, //!< Tx abort interrupt + SCI2C_INT_RD = BIT7, //!< Read done interrupt + SCI2C_INT_ACT = BIT8, //!< Activity interrupt + SCI2C_INT_STPD = BIT9, //!< Stop detect interrupt + SCI2C_INT_STAD = BIT10, //!< Start detect interrupt + SCI2C_INT_GC = BIT11, //!< Gernal call interrupt + SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt + SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt + SCI2C_INT_ALL = BIT15 //!< All interrupt +}SCI2C_INT_T; + +/** + * @brief Flag enumeration + */ +typedef enum +{ + SCI2C_FLAG_ACT = BIT0, //!< Activity flag + SCI2C_FLAG_TFNF = BIT1, //!< Tx FIFO not full flag + SCI2C_FLAG_TFE = BIT2, //!< Tx FIFO empty flag + SCI2C_FLAG_RFNE = BIT3, //!< Rx FIFO not empty flag + SCI2C_FLAG_RFF = BIT4, //!< Rx FIFO full flag + SCI2C_FLAG_MA = BIT5, //!< Master activity flag + SCI2C_FLAG_SA = BIT6, //!< Slave activity flag + SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag + SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag + SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag +}SCI2C_FLAG_T; + +/** + * @brief Tx abort source + */ +typedef enum +{ + SCI2C_TAS_AD7NA = BIT0, //!< 7 bit address mode NACK + SCI2C_TAS_AD10FBNA = BIT1, //!< 10 bit address mode first byte NACK + SCI2C_TAS_AD10SBNA = BIT2, //!< 10 bit address mode second byte NACK + SCI2C_TAS_TDNA = BIT3, //!< Tx data NACK + SCI2C_TAS_GCNA = BIT4, //!< Gernal call NACK + SCI2C_TAS_GCR = BIT5, //!< Gernal call read + SCI2C_TAS_HSAD = BIT6, //!< High speed ack detected + SCI2C_TAS_SNR = BIT7, //!< Start byte no restart + SCI2C_TAS_RNR10B = BIT8, //!< Read 10bit address mode when restart disable + SCI2C_TAS_MSTDIS = BIT9, //!< Master disable + SCI2C_TAS_ARBLOST = BIT10, //!< Arbitration lost + SCI2C_TAS_LFTF = BIT11, //!< Slave flush tx FIFO + SCI2C_TAS_SAL = BIT12, //!< Slave arbitration lost + SCI2C_TAS_SRI = BIT13, //!< Slave read done + SCI2C_TAS_USRARB = BIT14, //!< User abort + SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter +}SCI2C_TAS_T; + +/** + * @brief DMA Enable + */ +typedef enum +{ + SCI2C_DMA_RX = BIT0, + SCI2C_DMA_TX = BIT1, +}SCI2C_DMA_T; + +/**@} end of group SCI2C_Enumerations*/ + + +/** @addtogroup SCI2C_Macros Macros + @{ +*/ + +/** Macros description */ + +#define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E) +#define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055) +#define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55) +#define SCI2C_HSMC_RESET_VALUE ((uint32_t)0x07) +#define SCI2C_DATA_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_SSCHC_RESET_VALUE ((uint32_t)0x190) +#define SCI2C_SSCLC_RESET_VALUE ((uint32_t)0x1D6) +#define SCI2C_FSCHC_RESET_VALUE ((uint32_t)0x3C) +#define SCI2C_FSCLC_RESET_VALUE ((uint32_t)0x82) +#define SCI2C_HSCHC_RESET_VALUE ((uint32_t)0x06) +#define SCI2C_HSCLC_RESET_VALUE ((uint32_t)0x10) +#define SCI2C_INTEN_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_RFT_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_TFT_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_CTRL2_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_TFL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_RFL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_SDAHOLD_RESET_VALUE ((uint32_t)0x01) +#define SCI2C_SDNO_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_DMACTRL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_DTDL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_DRDL_RESET_VALUE ((uint32_t)0x00) +#define SCI2C_SDADLY_RESET_VALUE ((uint32_t)0x64) +#define SCI2C_GCA_RESET_VALUE ((uint32_t)0x01) +#define SCI2C_LSSSL_RESET_VALUE ((uint32_t)0x05) +#define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01) + +#define SCI2C_FIFO_DEPTH (0X08) +/**@} end of group SCI2C_Macros*/ + + +/** @addtogroup SCI2C_Structure Data Structure + @{ +*/ + +/** + * @brief Struct description + */ +typedef struct +{ + uint16_t slaveAddr; //!< Slave address. + SCI2C_MODE_T mode; //!< Specifies mode, master mode or slave mode + SCI2C_SPEED_T speed; //!< Specifies speed. Standard speed, fast speed or high speed. + uint16_t clkLowPeriod; //!< SCL high period + uint16_t clkHighPeriod; //!< SCL low period + uint8_t rxFifoThreshold; //!< Rx FIFO threshold + uint8_t txFifoThreshold; //!< Tx FIFO threshold + SCI2C_RESTART_T restart; //!< Enable or disable restart + SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode. +}SCI2C_Config_T; + +/**@} end of group SCI2C_Structure*/ + + +/** @addtogroup SCI2C_Fuctions Fuctions + @{ +*/ + +/** Reset */ +void SCI2C_Reset(SCI2C_T *i2c); + +/** Configuration */ +void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig); +void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig); + +/** Stop detect */ +void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c); +void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c); +void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c); +void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c); + +/** Restart */ +void SCI2C_EnableRestart(SCI2C_T *i2c); +void SCI2C_DisableRestart(SCI2C_T *i2c); + +/** Speed */ +void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed); + +/** Address */ +void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); +void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); + +/** Master mode and slave mode */ +void SCI2C_EnableMasterMode(SCI2C_T *i2c); +void SCI2C_DisableMasterMode(SCI2C_T *i2c); +void SCI2C_EnableSlaveMode(SCI2C_T *i2c); +void SCI2C_DisableSlaveMode(SCI2C_T *i2c); +void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code); + +/** Data */ +void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir); +void SCI2C_TxData(SCI2C_T *i2c, uint8_t data); +uint8_t SCI2C_RxData(SCI2C_T *i2c); +void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data); + +/** Rx and Tx FIFO */ +uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c); +uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c); +void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); +void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); + +/** I2C Enable, disable, abort, block */ +void SCI2C_Enable(SCI2C_T *i2c); +void SCI2C_Disable(SCI2C_T *i2c); +void SCI2C_Abort(SCI2C_T *i2c); +void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable); + +/** SCL and SDA */ +void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod); +void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold); +void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay); + +/** ACK and NACK */ +void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable); +void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable); + +/** Abort */ +uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c); + +/** DMA */ +void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); +void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); +void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt); +void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt); + +/** Spike suppression limit */ +void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit); + +/** Ingerrupt and flag */ +uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag); +void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); +uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); +uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); +void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt); +void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt); + +/**@} end of group SCI2C_Fuctions*/ +/**@} end of group SCI2C_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_SCI2C_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h new file mode 100644 index 0000000000..cc29cc3c8f --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h @@ -0,0 +1,418 @@ +/*! + * @file apm32f10x_sdio.h + * + * @brief This file contains all the functions prototypes for the SDIO firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_SDIO_H +#define __APM32F10X_SDIO_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SDIO_Driver SDIO Driver + @{ +*/ + +/** @addtogroup SDIO_Enumerations Enumerations + @{ +*/ + +/** + * @brief SDIO clock edge + */ +typedef enum +{ + SDIO_CLOCK_EDGE_RISING = 0x00000000, + SDIO_CLOCK_EDGE_FALLING = 0x00002000 +}SDIO_CLOCK_EDGE_T; + +/** + * @brief SDIO clock bypass + */ +typedef enum +{ + SDIO_CLOCK_BYPASS_DISABLE = 0x00000000, + SDIO_CLOCK_BYPASS_ENABLE = 0x00000400 +}SDIO_CLOCK_BYPASS_T; + +/** + * @brief SDIO clock power save + */ +typedef enum +{ + SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000, + SDIO_CLOCK_POWER_SAVE_ENABLE = 0x00000200 +}SDIO_CLOCK_POWER_SAVE_T; + +/** + * @brief SDIO bus wide + */ +typedef enum +{ + SDIO_BUSWIDE_1B = 0x00000000, + SDIO_BUSWIDE_4B = 0x00000800, + SDIO_BUSWIDE_8B = 0x00001000 +}SDIO_BUSWIDE_T; + +/** + * @brief SDIO hardware flow control + */ +typedef enum +{ + SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000, + SDIO_HARDWARE_FLOW_CONTROL_ENABLE = 0x00004000 +}SDIO_HARDWARE_FLOW_CONTROL_T; + +/** + * @brief SDIO power state + */ +typedef enum +{ + SDIO_POWER_STATE_OFF = 0x00000000, + SDIO_POWER_STATE_ON = 0x00000003 +}SDIO_POWER_STATE_T; + +/** + * @brief SDIO interrupt sources + */ +typedef enum +{ + SDIO_INT_COMRESP = 0x00000001, + SDIO_INT_DBDR = 0x00000002, + SDIO_INT_CMDRESTO = 0x00000004, + SDIO_INT_DATATO = 0x00000008, + SDIO_INT_TXUDRER = 0x00000010, + SDIO_INT_RXOVRER = 0x00000020, + SDIO_INT_CMDRES = 0x00000040, + SDIO_INT_CMDSENT = 0x00000080, + SDIO_INT_DATAEND = 0x00000100, + SDIO_INT_SBE = 0x00000200, + SDIO_INT_DBCP = 0x00000400, + SDIO_INT_CMDACT = 0x00000800, + SDIO_INT_TXACT = 0x00001000, + SDIO_INT_RXACT = 0x00002000, + SDIO_INT_TXFHF = 0x00004000, + SDIO_INT_RXFHF = 0x00008000, + SDIO_INT_TXFF = 0x00010000, + SDIO_INT_RXFF = 0x00020000, + SDIO_INT_TXFE = 0x00040000, + SDIO_INT_RXFE = 0x00080000, + SDIO_INT_TXDA = 0x00100000, + SDIO_INT_RXDA = 0x00200000, + SDIO_INT_SDIOINT = 0x00400000, + SDIO_INT_ATAEND = 0x00800000 +}SDIO_INT_T; + +/** + * @brief SDIO response + */ +typedef enum +{ + SDIO_RESPONSE_NO = 0x00000000, + SDIO_RESPONSE_SHORT = 0x00000040, + SDIO_RESPONSE_LONG = 0x000000C0 +}SDIO_RESPONSE_T; + +/** + * @brief SDIO wait interrupt state + */ +typedef enum +{ + SDIO_WAIT_NO = 0x00000000, + SDIO_WAIT_INT = 0x00000100, + SDIO_WAIT_PEND = 0x00000200 +}SDIO_WAIT_T; + +/** + * @brief SDIO CPSM state + */ +typedef enum +{ + SDIO_CPSM_DISABLE = 0x00000000, + SDIO_CPSM_ENABLE = 0x00000400 +}SDIO_CPSM_T; + +/** + * @brief SDIO response registers + */ +typedef enum +{ + SDIO_RES1 = 0x00000000, + SDIO_RES2 = 0x00000004, + SDIO_RES3 = 0x00000008, + SDIO_RES4 = 0x0000000C +}SDIO_RES_T; + +/** + * @brief SDIO data block size + */ +typedef enum +{ + SDIO_DATA_BLOCKSIZE_1B = 0x00000000, + SDIO_DATA_BLOCKSIZE_2B = 0x00000010, + SDIO_DATA_BLOCKSIZE_4B = 0x00000020, + SDIO_DATA_BLOCKSIZE_8B = 0x00000030, + SDIO_DATA_BLOCKSIZE_16B = 0x00000040, + SDIO_DATA_BLOCKSIZE_32B = 0x00000050, + SDIO_DATA_BLOCKSIZE_64B = 0x00000060, + SDIO_DATA_BLOCKSIZE_128B = 0x00000070, + SDIO_DATA_BLOCKSIZE_256B = 0x00000080, + SDIO_DATA_BLOCKSIZE_512B = 0x00000090, + SDIO_DATA_BLOCKSIZE_1024B = 0x000000A0, + SDIO_DATA_BLOCKSIZE_2048B = 0x000000B0, + SDIO_DATA_BLOCKSIZE_496B = 0x000000C0, + SDIO_DATA_BLOCKSIZE_8192B = 0x000000D0, + SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0 +}SDIO_DATA_BLOCKSIZE_T; + +/** + * @brief SDIO transfer direction + */ +typedef enum +{ + SDIO_TRANSFER_DIR_TOCARD = 0x00000000, + SDIO_TRANSFER_DIR_TOSDIO = 0x00000002 +}SDIO_TRANSFER_DIR_T; + +/** + * @brief SDIO transfer type + */ +typedef enum +{ + SDIO_TRANSFER_MODE_BLOCK = 0x00000000, + SDIO_TRANSFER_MODE_STREAM = 0x00000004 +}SDIO_TRANSFER_MODE_T; + +/** + * @brief SDIO DPSM state + */ +typedef enum +{ + SDIO_DPSM_DISABLE = 0x00000000, + SDIO_DPSM_ENABLE = 0x00000001 +}SDIO_DPSM_T; + +/** + * @brief SDIO flag + */ +typedef enum +{ + SDIO_FLAG_COMRESP = 0x00000001, + SDIO_FLAG_DBDR = 0x00000002, + SDIO_FLAG_CMDRESTO = 0x00000004, + SDIO_FLAG_DATATO = 0x00000008, + SDIO_FLAG_TXUDRER = 0x00000010, + SDIO_FLAG_RXOVRER = 0x00000020, + SDIO_FLAG_CMDRES = 0x00000040, + SDIO_FLAG_CMDSENT = 0x00000080, + SDIO_FLAG_DATAEND = 0x00000100, + SDIO_FLAG_SBE = 0x00000200, + SDIO_FLAG_DBCP = 0x00000400, + SDIO_FLAG_CMDACT = 0x00000800, + SDIO_FLAG_TXACT = 0x00001000, + SDIO_FLAG_RXACT = 0x00002000, + SDIO_FLAG_TXFHF = 0x00004000, + SDIO_FLAG_RXFHF = 0x00008000, + SDIO_FLAG_TXFF = 0x00010000, + SDIO_FLAG_RXFF = 0x00020000, + SDIO_FLAG_TXFE = 0x00040000, + SDIO_FLAG_RXFE = 0x00080000, + SDIO_FLAG_TXDA = 0x00100000, + SDIO_FLAG_RXDA = 0x00200000, + SDIO_FLAG_SDIOINT = 0x00400000, + SDIO_FLAG_ATAEND = 0x00800000 +}SDIO_FLAG_T; + +/** + * @brief SDIO read wait mode + */ +typedef enum +{ + SDIO_READ_WAIT_MODE_CLK = 0x00000001, + SDIO_READ_WAIT_MODE_DATA2 = 0x00000000 +}SDIO_READ_WAIT_MODE_T; + +/**@} end of group SDIO_Enumerations*/ + + +/** @addtogroup SDIO_Macros Macros + @{ +*/ + +/** ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCTRL Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSC bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSC_BitNumber 0x0B +#define CMD_SDIOSC_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4)) + +/* Alias word address of CMDCPEN bit */ +#define CMDCPEN_BitNumber 0x0C +#define CMD_CMDCPEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4)) + +/* Alias word address of INTEN bit */ +#define INTEN_BitNumber 0x0D +#define CMD_INTEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTR bit */ +#define RWSTR_BitNumber 0x08 +#define DCTRL_RWSTR_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RDWAIT bit */ +#define RDWAIT_BitNumber 0x0A +#define DCTRL_RDWAIT_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4)) + +/* Alias word address of SDIOF bit */ +#define SDIOF_BitNumber 0x0B +#define DCTRL_SDIOF_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4)) + +/**@} end of group SDIO_Macros*/ + +/** @addtogroup SDIO_Structure Data Structure + @{ +*/ + +/** + * @brief SDIO Config structure definition + */ +typedef struct +{ + SDIO_CLOCK_EDGE_T clockEdge; + SDIO_CLOCK_BYPASS_T clockBypass; + SDIO_CLOCK_POWER_SAVE_T clockPowerSave; + SDIO_BUSWIDE_T busWide; + SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl; + uint8_t clockDiv; +}SDIO_Config_T; + +/** + * @brief SDIO CMD Config structure definition + */ +typedef struct +{ + uint32_t argument; + uint32_t cmdIndex; + SDIO_RESPONSE_T response; + SDIO_WAIT_T wait; + SDIO_CPSM_T CPSM; +}SDIO_CMDConfig_T; + +/** + * @brief SDIO Data Config structure definition + */ +typedef struct +{ + uint32_t dataTimeOut; + uint32_t dataLength; + SDIO_DATA_BLOCKSIZE_T dataBlockSize; + SDIO_TRANSFER_DIR_T transferDir; + SDIO_TRANSFER_MODE_T transferMode; + SDIO_DPSM_T DPSM; +}SDIO_DataConfig_T; + +/**@} end of group SDIO_Structure*/ + + +/** @addtogroup SDIO_Fuctions Fuctions + @{ +*/ + +/** SDIO reset and configuration */ +void SDIO_Reset(void); +void SDIO_Config(SDIO_Config_T* sdioConfig); +void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig); +void SDIO_EnableClock(void); +void SDIO_DisableClock(void); +void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState); +uint32_t SDIO_ReadPowerState(void); + +/** DMA */ +void SDIO_EnableDMA(void); +void SDIO_DisableDMA(void); + +/** Command */ +void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig); +void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdconfig); +uint8_t SDIO_ReadCommandResponse(void); +uint32_t SDIO_ReadResponse(SDIO_RES_T res); + +/** SDIO data configuration */ +void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig); +void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig); +uint32_t SDIO_ReadDataCounter(void); +void SDIO_WriteData(uint32_t data); +uint32_t SDIO_ReadData(void); +uint32_t SDIO_ReadFIFOCount(void); + +/** SDIO mode */ +void SDIO_EnableStartReadWait(void); +void SDIO_DisableStartReadWait(void); +void SDIO_EnableStopReadWait(void); +void SDIO_DisableStopReadWait(void); +void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode); +void SDIO_EnableSDIO(void); +void SDIO_DisableSDIO(void); +void SDIO_EnableTxSDIOSuspend(void); +void SDIO_DisableTxSDIOSuspend(void); +void SDIO_EnableCommandCompletion(void); +void SDIO_DisableCommandCompletion(void); +void SDIO_EnableCEATAInterrupt(void); +void SDIO_DisableCEATAInterrupt(void); +void SDIO_EnableTxCEATA(void); +void SDIO_DisableTxCEATA(void); + +/** Interrupt and flags */ +void SDIO_EnableInterrupt(uint32_t interrupt); +void SDIO_DisableInterrupt(uint32_t interrupt); +uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag); +void SDIO_ClearStatusFlag(uint32_t flag); +uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag); +void SDIO_ClearIntFlag(uint32_t flag); + +/**@} end of group SDIO_Fuctions*/ +/**@} end of group SDIO_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_SDIO_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h new file mode 100644 index 0000000000..40e4afe7c0 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h @@ -0,0 +1,319 @@ +/*! + * @file apm32f10x_spi.h + * + * @brief This file contains all the functions prototypes for the SPI firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_SPI_H +#define __APM32F10X_SPI_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_Enumerations Enumerations + @{ +*/ + +/** + * @brief SPI data direction mode + */ +typedef enum +{ + SPI_DIRECTION_2LINES_FULLDUPLEX = 0x0000, + SPI_DIRECTION_2LINES_RXONLY = 0x0400, + SPI_DIRECTION_1LINE_RX = 0x8000, + SPI_DIRECTION_1LINE_TX = 0xC000 +}SPI_DIRECTION_T; + +/** + * @brief SPI mode + */ +typedef enum +{ + SPI_MODE_MASTER = 0x0104, + SPI_MODE_SLAVE = 0x0000 +}SPI_MODE_T; + +/** + * @brief SPI Data length + */ +typedef enum +{ + SPI_DATA_LENGTH_16B = 0x0800, + SPI_DATA_LENGTH_8B = 0x0000 +}SPI_DATA_LENGTH_T; + +/** + * @brief SPI Clock Polarity + */ +typedef enum +{ + SPI_CLKPOL_LOW = 0x0000, + SPI_CLKPOL_HIGH = 0x0002 +}SPI_CLKPOL_T; + +/** + * @brief SPI Clock Phase + */ +typedef enum +{ + SPI_CLKPHA_1EDGE = 0x0000, + SPI_CLKPHA_2EDGE = 0x0001 +}SPI_CLKPHA_T; + +/** + * @brief SPI Slave Select management + */ +typedef enum +{ + SPI_NSS_SOFT = 0x0200, + SPI_NSS_HARD = 0x0000 +}SPI_NSS_T; + +/** + * @brief SPI BaudRate Prescaler + */ +typedef enum +{ + SPI_BAUDRATE_DIV_2 = 0x0000, + SPI_BAUDRATE_DIV_4 = 0x0008, + SPI_BAUDRATE_DIV_8 = 0x0010, + SPI_BAUDRATE_DIV_16 = 0x0018, + SPI_BAUDRATE_DIV_32 = 0x0020, + SPI_BAUDRATE_DIV_64 = 0x0028, + SPI_BAUDRATE_DIV_128 = 0x0030, + SPI_BAUDRATE_DIV_256 = 0x0038, +}SPI_BAUDRATE_DIV_T; + +/** + * @brief SPI MSB LSB transmission + */ +typedef enum +{ + SPI_FIRSTBIT_MSB = 0x0000, + SPI_FIRSTBIT_LSB = 0x0080 +}SPI_FIRSTBIT_T; + +/** + * @brief I2S Mode + */ +typedef enum +{ + I2S_MODE_SLAVE_TX = 0x0000, + I2S_MODE_SLAVE_RX = 0x0100, + I2S_MODE_MASTER_TX = 0x0200, + I2S_MODE_MASTER_RX = 0x0300 +}I2S_MODE_T; + +/** + * @brief I2S Standard + */ +typedef enum +{ + I2S_STANDARD_PHILLIPS = 0x0000, + I2S_STANDARD_MSB = 0x0010, + I2S_STANDARD_LSB = 0x0020, + I2S_STANDARD_PCMSHORT = 0x0030, + I2S_STANDARD_PCMLONG = 0x00B0 +}I2S_STANDARD_T; + +/** + * @brief I2S data length + */ +typedef enum +{ + I2S_DATA_LENGHT_16B = 0x0000, + I2S_DATA_LENGHT_16BEX = 0x0001, + I2S_DATA_LENGHT_24B = 0x0003, + I2S_DATA_LENGHT_32B = 0x0005, +} I2S_DATA_LENGTH_T; + +/** + * @brief I2S_MCLK_Output + */ +typedef enum +{ + I2S_MCLK_OUTPUT_DISABLE = 0x0000, + I2S_MCLK_OUTPUT_ENABLE = 0x0200, +}I2S_MCLK_OUTPUT_T; + +/** + * @brief I2S Audio divider + */ +typedef enum +{ + I2S_AUDIO_DIV_192K = 192000, + I2S_AUDIO_DIV_96K = 96000, + I2S_AUDIO_DIV_48K = 48000, + I2S_AUDIO_DIV_44K = 44100, + I2S_AUDIO_DIV_32K = 32000, + I2S_AUDIO_DIV_22K = 22050, + I2S_AUDIO_DIV_16K = 16000, + I2S_AUDIO_DIV_11K = 11025, + I2S_AUDIO_DIV_8K = 8000, + I2S_AUDIO_DIV_DEFAULT = 2 +}I2S_AUDIO_DIV_T; + +/** + * @brief I2S Clock Polarity + */ +typedef enum +{ + I2S_CLKPOL_LOW = 0x0000, + I2S_CLKPOL_HIGH = 0x0008 +}I2S_CLKPOL_T; + +/** + * @brief SPI Direction select + */ +typedef enum +{ + SPI_DIRECTION_RX = 0xBFFF, + SPI_DIRECTION_TX = 0x4000 +}SPI_DIRECTION_SELECT_T; + +/** + * @brief SPI interrupts definition + */ +typedef enum +{ + SPI_I2S_INT_TXBE = 0x8002, + SPI_I2S_INT_RXBNE = 0x4001, + SPI_I2S_INT_ERR = 0x2000, + SPI_I2S_INT_OVR = 0x2040, + SPI_INT_CRCE = 0x2010, + SPI_INT_ME = 0x2020, + I2S_INT_UDR = 0x2008 +}SPI_I2S_INT_T; + +/** + * @brief SPI flags definition + */ +typedef enum +{ + SPI_FLAG_RXBNE = 0x0001, + SPI_FLAG_TXBE = 0x0002, + I2S_FLAG_SCHDIR = 0x0004, + I2S_FLAG_UDR = 0x0008, + SPI_FLAG_CRCE = 0x0010, + SPI_FLAG_ME = 0x0020, + SPI_FLAG_OVR = 0x0040, + SPI_FLAG_BSY = 0x0080 +}SPI_FLAG_T; + +/** + * @brief SPI I2S DMA requests + */ +typedef enum +{ + SPI_I2S_DMA_REQ_TX = 0x0002, + SPI_I2S_DMA_REQ_RX = 0x0001 +}SPI_I2S_DMA_REQ_T; + +/**@} end of group SPI_Enumerations*/ + + +/** @addtogroup SPI_Structure Data Structure + @{ +*/ + +/** + * @brief SPI Config structure definition + */ +typedef struct +{ + SPI_MODE_T mode; + SPI_DATA_LENGTH_T length; + SPI_CLKPHA_T phase; + SPI_CLKPOL_T polarity; + SPI_NSS_T nss; + SPI_FIRSTBIT_T firstBit; + SPI_DIRECTION_T direction; + SPI_BAUDRATE_DIV_T baudrateDiv; + uint16_t crcPolynomial; +}SPI_Config_T; + +/** + * @brief I2S Config structure definition + */ +typedef struct +{ + I2S_MODE_T mode; + I2S_STANDARD_T standard; + I2S_DATA_LENGTH_T length; + I2S_MCLK_OUTPUT_T MCLKOutput; + I2S_AUDIO_DIV_T audioDiv; + I2S_CLKPOL_T polarity; +}I2S_Config_T; + +/**@} end of group SPI_Structure*/ + +/** @addtogroup SPI_Fuctions Fuctions + @{ +*/ + +/** Reset and Configuration */ +void SPI_I2S_Reset(SPI_T* spi); +void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig); +void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig); +void SPI_ConfigStructInit(SPI_Config_T* spiConfig); +void I2S_ConfigStructInit(I2S_Config_T* i2sConfig); +void SPI_Enable(SPI_T* spi); +void SPI_Disable(SPI_T* spi); +void I2S_Enable(SPI_T* spi); +void I2S_Disable(SPI_T* spi); + +void SPI_I2S_TxData(SPI_T* spi, uint16_t data); +uint16_t SPI_I2S_RxData(SPI_T* spi); +void SPI_SetSoftwareNSS(SPI_T* spi); +void SPI_ResetSoftwareNSS(SPI_T* spi); +void SPI_EnableSSOutput(SPI_T* spi); +void SPI_DisableSSOutput(SPI_T* spi); +void SPI_ConfigDataSize(SPI_T* spi, uint16_t dataSize); + +/** DMA */ +void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); +void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq); + +/** CRC */ +void SPI_TxCRC(SPI_T* spi); +void SPI_EnableCRC(SPI_T* spi); +void SPI_DisableCRC(SPI_T* spi); +uint16_t SPI_ReadTxCRC(SPI_T* spi); +uint16_t SPI_ReadRxCRC(SPI_T* spi); +uint16_t SPI_ReadCRCPolynomial(SPI_T* spi); +void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction); + +/** Interrupts and flag */ +void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); +void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt); +uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag); +void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag); +uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); +void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag); + +/**@} end of group SPI_Fuctions*/ +/**@} end of group SPI_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_SPI_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h new file mode 100644 index 0000000000..50313d7e08 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h @@ -0,0 +1,659 @@ +/*! + * @file apm32f10x_tmr.h + * + * @brief This file contains all the functions prototypes for the TMR firmware library. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#ifndef __APM32F10X_TMR_H +#define __APM32F10X_TMR_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup TMR_Driver TMR Driver + @{ +*/ + +/** @addtogroup TMR_Enumerations Enumerations + @{ +*/ + +/** + * @brief TMR Counter Mode + */ +typedef enum +{ + TMR_COUNTER_MODE_UP = 0x0000, + TMR_COUNTER_MODE_DOWN = 0x0010, + TMR_COUNTER_MODE_CENTERALIGNED1 = 0x0020, + TMR_COUNTER_MODE_CENTERALIGNED2 = 0x0040, + TMR_COUNTER_MODE_CENTERALIGNED3 = 0x0060 +} TMR_COUNTER_MODE_T; + +/** + * @brief TMR Clock division + */ +typedef enum +{ + TMR_CLOCK_DIV_1, + TMR_CLOCK_DIV_2, + TMR_CLOCK_DIV_4 +} TMR_CLOCK_DIV_T; + +/** + * @brief TMR Output Compare and PWM modes + */ +typedef enum +{ + TMR_OC_MODE_TMRING = 0x00, + TMR_OC_MODE_ACTIVE = 0x01, + TMR_OC_MODE_INACTIVE = 0x02, + TMR_OC_MODE_TOGGEL = 0x03, + TMR_OC_MODE_LOWLEVEL = 0x04, + TMR_OC_MODE_HIGHLEVEL = 0x05, + TMR_OC_MODE_PWM1 = 0x06, + TMR_OC_MODE_PWM2 = 0x07, +} TMR_OC_MODE_T; + +/** + * @brief TMR Output Compare state + */ +typedef enum +{ + TMR_OC_STATE_DISABLE, + TMR_OC_STATE_ENABLE +} TMR_OC_STATE_T; + +/** + * @brief TMR Output Compare N state + */ +typedef enum +{ + TMR_OC_NSTATE_DISABLE, + TMR_OC_NSTATE_ENABLE +} TMR_OC_NSTATE_T; + +/** + * @brief TMR Output Compare Polarity + */ +typedef enum +{ + TMR_OC_POLARITY_HIGH, + TMR_OC_POLARITY_LOW +} TMR_OC_POLARITY_T; + +/** + * @brief TMR Output Compare N Polarity + */ +typedef enum +{ + TMR_OC_NPOLARITY_HIGH, + TMR_OC_NPOLARITY_LOW +} TMR_OC_NPOLARITY_T; + +/** + * @brief TMR Output Compare Idle State + */ +typedef enum +{ + TMR_OC_IDLE_STATE_RESET, + TMR_OC_IDLE_STATE_SET +} TMR_OC_IDLE_STATE_T; + +/** + * @brief TMR Output Compare N Idle State + */ +typedef enum +{ + TMR_OC_NIDLE_STATE_RESET, + TMR_OC_NIDLE_STATE_SET +} TMR_OC_NIDLE_STATE_T; + +/** + * @brief TMR Input Capture Init structure definition + */ +typedef enum +{ + TMR_CHANNEL_1 = 0x0000, + TMR_CHANNEL_2 = 0x0004, + TMR_CHANNEL_3 = 0x0008, + TMR_CHANNEL_4 = 0x000C +} TMR_CHANNEL_T; + +/** + * @brief TMR Input Capture Polarity + */ +typedef enum +{ + TMR_IC_POLARITY_RISING = 0x00, + TMR_IC_POLARITY_FALLING = 0x02, + TMR_IC_POLARITY_BOTHEDGE = 0x0A +} TMR_IC_POLARITY_T; + +/** + * @brief TMR Input Capture Selection + */ +typedef enum +{ + TMR_IC_SELECTION_DIRECT_TI = 0x01, + TMR_IC_SELECTION_INDIRECT_TI = 0x02, + TMR_IC_SELECTION_TRC = 0x03 +} TMR_IC_SELECTION_T; + +/** + * @brief TMR Input Capture Prescaler + */ +typedef enum +{ + TMR_IC_PSC_1, + TMR_IC_PSC_2, + TMR_IC_PSC_4, + TMR_IC_PSC_8 +} TMR_IC_PSC_T; + +/** + * @brief TMR Specifies the Off-State selection used in Run mode + */ +typedef enum +{ + TMR_RMOS_STATE_DISABLE, + TMR_RMOS_STATE_ENABLE +} TMR_RMOS_STATE_T; + +/** + * @brief TMR Closed state configuration in idle mode + */ +typedef enum +{ + TMR_IMOS_STATE_DISABLE, + TMR_IMOS_STATE_ENABLE +} TMR_IMOS_STATE_T; + +/** + * @brief TMR Protect mode configuration values + */ +typedef enum +{ + TMR_LOCK_LEVEL_OFF, + TMR_LOCK_LEVEL_1, + TMR_LOCK_LEVEL_2, + TMR_LOCK_LEVEL_3 +} TMR_LOCK_LEVEL_T; + +/** + * @brief TMR BRK state + */ +typedef enum +{ + TMR_BRK_STATE_DISABLE, + TMR_BRK_STATE_ENABLE +} TMR_BRK_STATE_T; + +/** + * @brief TMR Specifies the Break Input pin polarity. + */ +typedef enum +{ + TMR_BRK_POLARITY_LOW, + TMR_BRK_POLARITY_HIGH +} TMR_BRK_POLARITY_T; + +/** + * @brief TMR Specifies the Break Input pin polarity. + */ +typedef enum +{ + TMR_AUTOMATIC_OUTPUT_DISABLE, + TMR_AUTOMATIC_OUTPUT_ENABLE +} TMR_AUTOMATIC_OUTPUT_T; + +/** + * @brief TMR_interrupt_sources + */ +typedef enum +{ + TMR_INT_UPDATE = 0x0001, + TMR_INT_CC1 = 0x0002, + TMR_INT_CC2 = 0x0004, + TMR_INT_CC3 = 0x0008, + TMR_INT_CC4 = 0x0010, + TMR_INT_COM = 0x0020, + TMR_INT_TRG = 0x0040, + TMR_INT_BRK = 0x0080 +} TMR_INT_T; + +/** + * @brief TMR event sources + */ +typedef enum +{ + TMR_EVENT_UPDATE = 0x001, + TMR_EVENT_CC1 = 0x002, + TMR_EVENT_CC2 = 0x004, + TMR_EVENT_CC3 = 0x008, + TMR_EVENT_CC4 = 0x010, + TMR_EVENT_COM = 0x020, + TMR_EVENT_TRG = 0x040, + TMR_EVENT_BRK = 0x080 +} TMR_EVENT_T; + +/** + * @brief TMR DMA Base Address + */ +typedef enum +{ + TMR_DMA_BASE_CTRL1 = 0x0000, + TMR_DMA_BASE_CTRL2 = 0x0001, + TMR_DMA_BASE_SMCTRL = 0x0002, + TMR_DMA_BASE_DIEN = 0x0003, + TMR_DMA_BASE_STS = 0x0004, + TMR_DMA_BASE_CEG = 0x0005, + TMR_DMA_BASE_CCM1 = 0x0006, + TMR_DMA_BASE_CCM2 = 0x0007, + TMR_DMA_BASE_CCEN = 0x0008, + TMR_DMA_BASE_CNT = 0x0009, + TMR_DMA_BASE_PSC = 0x000A, + TMR_DMA_BASE_AUTORLD = 0x000B, + TMR_DMA_BASE_REPCNT = 0x000C, + TMR_DMA_BASE_CC1 = 0x000D, + TMR_DMA_BASE_CC2 = 0x000E, + TMR_DMA_BASE_CC3 = 0x000F, + TMR_DMA_BASE_CC4 = 0x0010, + TMR_DMA_BASE_BDT = 0x0011, + TMR_DMA_BASE_DCTRL = 0x0012 +} TMR_DMA_BASE_T; + +/** + * @brief TMR DMA Burst Length + */ +typedef enum +{ + TMR_DMA_BURSTLENGTH_1TRANSFER = 0x0000, + TMR_DMA_BURSTLENGTH_2TRANSFERS = 0x0100, + TMR_DMA_BURSTLENGTH_3TRANSFERS = 0x0200, + TMR_DMA_BURSTLENGTH_4TRANSFERS = 0x0300, + TMR_DMA_BURSTLENGTH_5TRANSFERS = 0x0400, + TMR_DMA_BURSTLENGTH_6TRANSFERS = 0x0500, + TMR_DMA_BURSTLENGTH_7TRANSFERS = 0x0600, + TMR_DMA_BURSTLENGTH_8TRANSFERS = 0x0700, + TMR_DMA_BURSTLENGTH_9TRANSFERS = 0x0800, + TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900, + TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00, + TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00, + TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00, + TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00, + TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00, + TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00, + TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000, + TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100, +} TMR_DMA_BURSTLENGTH_T; + +/** + * @brief TMR DMA Soueces + */ +typedef enum +{ + TMR_DMA_SOURCE_UPDATE = 0x0100, + TMR_DMA_SOURCE_CC1 = 0x0200, + TMR_DMA_SOURCE_CC2 = 0x0400, + TMR_DMA_SOURCE_CC3 = 0x0800, + TMR_DMA_SOURCE_CC4 = 0x1000, + TMR_DMA_SOURCE_COM = 0x2000, + TMR_DMA_SOURCE_TRG = 0x4000 +} TMR_DMA_SOURCE_T; + +/** + * @brief TMR Internal Trigger Selection + */ +typedef enum +{ + TMR_TRIGGER_SOURCE_ITR0 = 0x00, + TMR_TRIGGER_SOURCE_ITR1 = 0x01, + TMR_TRIGGER_SOURCE_ITR2 = 0x02, + TMR_TRIGGER_SOURCE_ITR3 = 0x03, + TMR_TRIGGER_SOURCE_TI1F_ED = 0x04, + TMR_TRIGGER_SOURCE_TI1FP1 = 0x05, + TMR_TRIGGER_SOURCE_TI2FP2 = 0x06, + TMR_TRIGGER_SOURCE_ETRF = 0x07 +} TMR_TRIGGER_SOURCE_T; + +/** + * @brief TMR The external Trigger Prescaler. + */ +typedef enum +{ + TMR_EXTTRG_PSC_OFF = 0x00, + TMR_EXTTRG_PSC_DIV2 = 0x01, + TMR_EXTTRG_PSC_DIV4 = 0x02, + TMR_EXTTRG_PSC_DIV8 = 0x03 +} TMR_EXTTRG_PSC_T; + +/** + * @brief TMR External Trigger Polarity + */ +typedef enum +{ + TMR_EXTTGR_POL_NONINVERTED, + TMR_EXTTRG_POL_INVERTED +} TMR_EXTTRG_POL_T; + +/** + * @brief TMR Prescaler Reload Mode + */ +typedef enum +{ + TMR_PRESCALER_RELOAD_UPDATA, + TMR_PRESCALER_RELOAD_IMMEDIATE +} TMR_PRESCALER_RELOAD_T; + +/** + * @brief TMR Encoder Mode + */ +typedef enum +{ + TMR_ENCODER_MODE_TI1 = 0x01, + TMR_ENCODER_MODE_TI2 = 0x02, + TMR_ENCODER_MODE_TI12 = 0x03 +} TMR_ENCODER_MODE_T; + +/** + * @brief TMR Forced Action + */ +typedef enum +{ + TMR_FORCED_ACTION_INACTIVE = 0x04, + TMR_FORCED_ACTION_ACTIVE = 0x05 +} TMR_FORCED_ACTION_T; + +/** + * @brief TMR Output Compare Preload State + */ +typedef enum +{ + TMR_OC_PRELOAD_DISABLE, + TMR_OC_PRELOAD_ENABLE +} TMR_OC_PRELOAD_T; + +/** + * @brief TMR Output Compare Preload State + */ +typedef enum +{ + TMR_OC_FAST_DISABLE, + TMR_OC_FAST_ENABLE +} TMR_OC_FAST_T; + +/** + * @brief TMR Output Compare Preload State + */ +typedef enum +{ + TMR_OC_CLEAR_DISABLE, + TMR_OC_CLEAR_ENABLE +} TMR_OC_CLEAR_T; + +/** + * @brief TMR UpdateSource + */ +typedef enum +{ + TMR_UPDATE_SOURCE_GLOBAL, + TMR_UPDATE_SOURCE_REGULAR, +} TMR_UPDATE_SOURCE_T; + +/** + * @brief TMR Single Pulse Mode + */ +typedef enum +{ + TMR_SPM_REPETITIVE, + TMR_SPM_SINGLE, +} TMR_SPM_T; + +/** + * @brief TMR Trigger Output Source + */ +typedef enum +{ + TMR_TRGO_SOURCE_RESET, + TMR_TRGO_SOURCE_ENABLE, + TMR_TRGO_SOURCE_UPDATE, + TMR_TRGO_SOURCE_OC1, + TMR_TRGO_SOURCE_OC1REF, + TMR_TRGO_SOURCE_OC2REF, + TMR_TRGO_SOURCE_OC3REF, + TMR_TRGO_SOURCE_OC4REF +} TMR_TRGO_SOURCE_T; + +/** + * @brief TMR Slave Mode + */ +typedef enum +{ + TMR_SLAVE_MODE_RESET = 0x04, + TMR_SLAVE_MODE_GATED = 0x05, + TMR_SLAVE_MODE_TRIGGER = 0x06, + TMR_SLAVE_MODE_EXTERNALL = 0x07 +} TMR_SLAVE_MODE_T; + +/** + * @brief TMR Flag + */ +typedef enum +{ + TMR_FLAG_UPDATE = 0x0001, + TMR_FLAG_CC1 = 0x0002, + TMR_FLAG_CC2 = 0x0004, + TMR_FLAG_CC3 = 0x0008, + TMR_FLAG_CC4 = 0x0010, + TMR_FLAG_COM = 0x0020, + TMR_FLAG_TRG = 0x0040, + TMR_FLAG_BRK = 0x0080, + TMR_FLAG_CC1RC = 0x0200, + TMR_FLAG_CC2RC = 0x0400, + TMR_FLAG_CC3RC = 0x0800, + TMR_FLAG_CC4RC = 0x1000 +} TMR_FLAG_T; + +/**@} end of group TMR_Enumerations*/ + +/** @addtogroup TMR_Structure Data Structure + @{ +*/ + +/** + * @brief TMR Config struct definition + */ +typedef struct +{ + TMR_COUNTER_MODE_T countMode; + TMR_CLOCK_DIV_T clockDivision; + uint16_t period; //!< This must between 0x0000 and 0xFFFF + uint16_t division; //!< This must between 0x0000 and 0xFFFF + uint8_t repetitionCounter; //!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. +} TMR_BaseConfig_T; ; + +/** + * @brief TMR Config struct definition + */ +typedef struct +{ + TMR_OC_MODE_T mode; + TMR_OC_STATE_T outputState; + TMR_OC_NSTATE_T outputNState; + TMR_OC_POLARITY_T polarity; + TMR_OC_NPOLARITY_T nPolarity; + TMR_OC_IDLE_STATE_T idleState; + TMR_OC_NIDLE_STATE_T nIdleState; + uint16_t pulse; //!< This must between 0x0000 and 0xFFFF +} TMR_OCConfig_T; + +/** + * @brief TMR BDT structure definition + */ +typedef struct +{ + TMR_RMOS_STATE_T RMOS; + TMR_IMOS_STATE_T IMOS; + TMR_LOCK_LEVEL_T lockLevel; + uint16_t deadTime; + TMR_BRK_STATE_T BRKState; + TMR_BRK_POLARITY_T BRKPolarity; + TMR_AUTOMATIC_OUTPUT_T automaticOutput; +} TMR_BDTConfig_T; + +/** + * @brief TMR Input Capture Config struct definition + */ +typedef struct +{ + TMR_CHANNEL_T channel; + TMR_IC_POLARITY_T polarity; + TMR_IC_SELECTION_T selection; + TMR_IC_PSC_T prescaler; + uint16_t filter; //!< This must between 0x00 and 0x0F +} TMR_ICConfig_T; + +/**@} end of group TMR_Structure*/ + +/** @addtogroup TMR_Fuctions Fuctions + @{ +*/ + +/** Reset and Configuration */ +void TMR_Reset(TMR_T* tmr); +void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig); +void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OC1Config); +void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OC2Config); +void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OC3Config); +void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OC4Config); +void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig); +void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig); +void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig); +void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig); +void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig); +void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig); +void TMR_Enable(TMR_T* tmr); +void TMR_Disable(TMR_T* tmr); + +/* PWM Configuration */ +void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig); +void TMR_EnablePWMOutputs(TMR_T* tmr); +void TMR_DisablePWMOutputs(TMR_T* tmr); + +/** DMA */ +void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength); +void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource); +void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource); + +/** Configuration */ +void TMR_ConfigInternalClock(TMR_T* tmr); +void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource); +void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); +void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter); +void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter); +void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter); +void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode); +void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode); +void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce); +void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, + TMR_IC_POLARITY_T IC2Polarity); +void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction); +void TMR_EnableAUTOReload(TMR_T* tmr); +void TMR_DisableAUTOReload(TMR_T* tmr); +void TMR_EnableSelectCOM(TMR_T* tmr); +void TMR_DisableSelectCOM(TMR_T* tmr); +void TMR_EnableCCDMA(TMR_T* tmr); +void TMR_DisableCCDMA(TMR_T* tmr); +void TMR_EnableCCPreload(TMR_T* tmr); +void TMR_DisableCCPreload(TMR_T* tmr); +void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); +void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); +void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); +void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); +void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); +void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel); +void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode); +void TMR_EnableNoUpdate(TMR_T* tmr); +void TMR_DisableNoUpdate(TMR_T* tmr); +void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource); +void TMR_EnableHallSensor(TMR_T* tmr); +void TMR_DisableHallSensor(TMR_T* tmr); +void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode); +void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource); +void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode); +void TMR_EnableMasterSlaveMode(TMR_T* tmr); +void TMR_DisableMasterSlaveMode(TMR_T* tmr); +void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter); +void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload); +void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1); +void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2); +void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3); +void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4); +void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler); +void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision); +uint16_t TMR_ReadCaputer1(TMR_T* tmr); +uint16_t TMR_ReadCaputer2(TMR_T* tmr); +uint16_t TMR_ReadCaputer3(TMR_T* tmr); +uint16_t TMR_ReadCaputer4(TMR_T* tmr); +uint16_t TMR_ReadCounter(TMR_T* tmr); +uint16_t TMR_ReadPrescaler(TMR_T* tmr); + +/** Interrupts and Event */ +void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt); +void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt); +void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources); + +/** flags */ +uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag); +void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag); +uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag); +void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag); + +/**@} end of group TMR_Fuctions*/ +/**@} end of group TMR_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_TMR_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h new file mode 100644 index 0000000000..fb7880c1ee --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h @@ -0,0 +1,296 @@ +/*! + * @file apm32f10x_usart.h + * + * @brief This file contains all the functions prototypes for the USART firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_USART_H +#define __APM32F10X_USART_H + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup USART_Driver USART Driver + @{ +*/ + +/** @addtogroup USART_Enumerations Enumerations + @{ +*/ + +/** + * @brief USART Word Length define + */ +typedef enum +{ + USART_WORD_LEN_8B = 0, + USART_WORD_LEN_9B = BIT12 +} USART_WORD_LEN_T; + +/** + * @brief USART Stop bits define + */ +typedef enum +{ + USART_STOP_BIT_1 = 0, + USART_STOP_BIT_0_5 = BIT12, + USART_STOP_BIT_2 = BIT13, + USART_STOP_BIT_1_5 = BIT12 | BIT13 +} USART_STOP_BIT_T; + +/** + * @brief USART Parity define + */ +typedef enum +{ + USART_PARITY_NONE = 0, + USART_PARITY_EVEN = BIT10, + USART_PARITY_ODD = BIT10 | BIT9 +} USART_PARITY_T; + +/** + * @brief USART mode define + */ +typedef enum +{ + USART_MODE_RX = BIT2, + USART_MODE_TX = BIT3, + USART_MODE_TX_RX = BIT2 | BIT3 +} USART_MODE_T; + +/** + * @brief USART hardware flow control define + */ +typedef enum +{ + USART_HARDWARE_FLOW_NONE = 0, + USART_HARDWARE_FLOW_RTS = BIT8, + USART_HARDWARE_FLOW_CTS = BIT9, + USART_HARDWARE_FLOW_RTS_CTS = BIT8 | BIT9 +} USART_HARDWARE_FLOW_T; + +/** + * @brief USART Clock enable + */ +typedef enum +{ + USART_CLKEN_DISABLE, + USART_CLKEN_ENABLE +} USART_CLKEN_T; + +/** + * @brief USART Clock polarity define + */ +typedef enum +{ + USART_CLKPOL_LOW, + USART_CLKPOL_HIGH +} USART_CLKPOL_T; + +/** + * @brief USART Clock phase define + */ +typedef enum +{ + USART_CLKPHA_1EDGE, + USART_CLKPHA_2EDGE +} USART_CLKPHA_T; + +/** + * @brief USART Last bit clock pulse enable + */ +typedef enum +{ + USART_LBCP_DISABLE, + USART_LBCP_ENABLE, +} USART_LBCP_T; + +/** + * @brief USART Interrupt Source + */ +typedef enum +{ + USART_INT_PE = 0x0010100, + USART_INT_TXBE = 0x7010080, + USART_INT_TXC = 0x6010040, + USART_INT_RXBNE = 0x5010020, + USART_INT_IDLE = 0x4010010, + USART_INT_LBD = 0x8020040, + USART_INT_CTS = 0x9040400, + USART_INT_ERR = 0x0040001, + USART_INT_OVRE = 0x3040001, + USART_INT_NE = 0x2040001, + USART_INT_FE = 0x1040001 +} USART_INT_T; + +/** + * @brief USART DMA enable + */ +typedef enum +{ + USART_DMA_TX = BIT7, + USART_DMA_RX = BIT6, + USART_DMA_TX_RX = BIT6 | BIT7 +} USART_DMA_T; + +/** + * @brief USART Wakeup method + */ +typedef enum +{ + USART_WAKEUP_IDLE_LINE, + USART_WAKEUP_ADDRESS_MARK +} USART_WAKEUP_T; + +/** + * @brief USART LIN break detection length + */ +typedef enum +{ + USART_LBDL_10B, + USART_LBDL_11B +} USART_LBDL_T; + +/** + * @brief USART IrDA low-power + */ +typedef enum +{ + USART_IRDALP_NORMAL, + USART_IRDALP_LOWPOWER +} USART_IRDALP_T; + +/** + * @brief USART flag define + */ +typedef enum +{ + USART_FLAG_CTS = 0x0200, + USART_FLAG_LBD = 0x0100, + USART_FLAG_TXBE = 0x0080, + USART_FLAG_TXC = 0x0040, + USART_FLAG_RXBNE = 0x0020, + USART_FLAG_IDLE = 0x0010, + USART_FLAG_OVRE = 0x0008, + USART_FLAG_NE = 0x0004, + USART_FLAG_FE = 0x0002, + USART_FLAG_PE = 0x0001 +} USART_FLAG_T; + +/**@} end of group USART_Enumerations*/ + +/** @addtogroup USART_Structure Data Structure + @{ +*/ + +/** + * @brief USART Config struct definition + */ +typedef struct +{ + uint32_t baudRate; //!< Specifies the baud rate + USART_WORD_LEN_T wordLength; //!< Specifies the word length + USART_STOP_BIT_T stopBits; //!< Specifies the stop bits + USART_PARITY_T parity; //!< Specifies the parity + USART_MODE_T mode; //!< Specifies the mode + USART_HARDWARE_FLOW_T hardwareFlow; //!< Specifies the hardware flow control +} USART_Config_T; + +/** + * @brief USART synchronous communication clock config struct definition + */ +typedef struct +{ + USART_CLKEN_T clock; //!< Enable or Disable Clock + USART_CLKPOL_T polarity; //!< Specifies the clock polarity + USART_CLKPHA_T phase; //!< Specifies the clock phase + USART_LBCP_T lastBit; //!< Enable or Disable last bit clock +} USART_ClockConfig_T; + +/**@} end of group USART_Structure*/ + +/** @addtogroup USART_Fuctions Fuctions + @{ +*/ + +/** USART Reset and Configuration */ +void USART_Reset(USART_T* usart); +void USART_Config(USART_T* uart, USART_Config_T* usartConfig); +void USART_ConfigStructInit(USART_Config_T* usartConfig); +void USART_Address(USART_T* usart, uint8_t address); +void USART_Enable(USART_T* usart); +void USART_Disable(USART_T* usart); + +/** Clock communication */ +void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig); +void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig); + +/** DMA mode */ +void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq); +void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq); + +/** Mute mode */ +void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup); +void USART_EnableMuteMode(USART_T* usart); +void USART_DisableMuteMode(USART_T* usart); + +/** LIN mode */ +void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length); +void USART_EnableLIN(USART_T* usart); +void USART_DisableLIN(USART_T* usart); + +/** Transmit and receive */ +void USART_EnableTx(USART_T* usart); +void USART_DisableTx(USART_T* usart); +void USART_EnableRx(USART_T* usart); +void USART_DisableRx(USART_T* usart); +void USART_TxData(USART_T* usart, uint16_t data); +uint16_t USART_RxData(USART_T* usart); +void USART_TxBreak(USART_T* usart); + +/** Smartcard mode */ +void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime); +void USART_ConfigPrescaler(USART_T* usart, uint8_t div); +void USART_EnableSmartCard(USART_T* usart); +void USART_DisableSmartCard(USART_T* usart); +void USART_EnableSmartCardNACK(USART_T* usart); +void USART_DisableSmartCardNACK(USART_T* usart); + +/** Half-duplex mode */ +void USART_EnableHalfDuplex(USART_T* usart); +void USART_DisableHalfDuplex(USART_T* usart); + +/** IrDA mode */ +void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode); +void USART_EnableIrDA(USART_T* usart); +void USART_DisableIrDA(USART_T* usart); + +/** Interrupt and flag */ +void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt); +void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt); +uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag); +void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag); +uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag); +void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag); + +/**@} end of group USART_Fuctions*/ +/**@} end of group USART_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_USART_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h new file mode 100644 index 0000000000..570c0e30a1 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usb.h @@ -0,0 +1,582 @@ +/*! + * @file apm32f10x_usb.h + * + * @brief This file contains all the prototypes,enumeration and macros for USBD peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#ifndef __APM32F10X_USBD_H_ +#define __APM32F10X_USBD_H_ + +#include "apm32f10x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_Enumerations Enumerations + @{ +*/ + +/** + * @brief USBD Endpoint register bit definition + */ +typedef enum +{ + USBD_EP_BIT_ADDR = (uint32_t)(BIT0 | BIT1 | BIT2 | BIT3), + USBD_EP_BIT_TXSTS = (uint32_t)(BIT4 | BIT5), + USBD_EP_BIT_TXDTOG = (uint32_t)(BIT6), + USBD_EP_BIT_CTFT = (uint32_t)(BIT7), + USBD_EP_BIT_KIND = (uint32_t)(BIT8), + USBD_EP_BIT_TYPE = (uint32_t)(BIT9 | BIT10), + USBD_EP_BIT_SETUP = (uint32_t)(BIT11), + USBD_EP_BIT_RXSTS = (uint32_t)(BIT12 | BIT13), + USBD_EP_BIT_RXDTOG = (uint32_t)(BIT14), + USBD_EP_BIT_CTFR = (uint32_t)(BIT15) +}USBD_EP_BIT_T; + +/** + * @brief Endpoint id + */ +typedef enum +{ + USBD_EP_0, + USBD_EP_1, + USBD_EP_2, + USBD_EP_3, + USBD_EP_4, + USBD_EP_5, + USBD_EP_6, + USBD_EP_7, +}USBD_EP_T; + +/** + * @brief Endpoint status + */ +typedef enum +{ + USBD_EP_STATUS_DISABLE = ((uint32_t)0), + USBD_EP_STATUS_STALL = ((uint32_t)1), + USBD_EP_STATUS_NAK = ((uint32_t)2), + USBD_EP_STATUS_VALID = ((uint32_t)3), +}USBD_EP_STATUS_T; + +/** + * @brief USBD Endpoint type + */ +typedef enum +{ + USBD_EP_TYPE_BULK, + USBD_EP_TYPE_CONTROL, + USBD_EP_TYPE_ISO, + USBD_EP_TYPE_INTERRUPT +}USBD_EP_TYPE_T; + +/**@} end of group USBD_Enumerations*/ + + +/** @addtogroup USBD_Macros Macros + @{ +*/ + +/** USBD packet memory area base address */ +#define USBD_PMA_ADDR (0x40006000L) + +/** Endpoint register mask value default */ +#define USBD_EP_MASK_DEFAULT (USBD_EP_BIT_CTFR | USBD_EP_BIT_SETUP | USBD_EP_BIT_TYPE | USBD_EP_BIT_KIND | USBD_EP_BIT_CTFT |USBD_EP_BIT_ADDR) + +/** + * @brief USBD interrupt source + */ +#define USBD_INT_ESOF 0X100 +#define USBD_INT_SOF 0X200 +#define USBD_INT_RST 0X400 +#define USBD_INT_SUS 0x800 +#define USBD_INT_WKUP 0X1000 +#define USBD_INT_ERR 0X2000 +#define USBD_INT_PMAOU 0X4000 +#define USBD_INT_CTR 0X8000 +#define USBD_INT_ALL 0XFF00 + +/**@} end of group USBD_Macros*/ + + +/** @addtogroup USBD_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Set CTRL register + * + * @param val: Register value + * + * @retval None + * + */ +#define USBD_SetRegCTRL(val) (USBD->CTRL = val) + +/*! + * @brief Set INTSTS register + * + * @param val: Register value + * + * @retval None + */ +#define USBD_SetRegINTSTS(val) (USBD->INTSTS = val) + +/*! + * @brief Set force reset + * + * @param None + * + * @retval None + */ +#define USBD_SetForceReset() (USBD->CTRL_B.FORRST = BIT_SET) + +/*! + * @brief Reset force reset + * + * @param None + * + * @retval None + */ +#define USBD_ResetForceReset() (USBD->CTRL_B.FORRST = BIT_RESET) + +/*! + * @brief Set power down + * + * @param None + * + * @retval None + */ +#define USBD_SetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_SET) + +/*! + * @brief Reset power down + * + * @param None + * + * @retval None + */ +#define USBD_ResetPowerDown() (USBD->CTRL_B.PWRDOWN = BIT_RESET) + +/*! + * @brief Set low power mode + * + * @param None + * + * @retval None + */ +#define USBD_SetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_SET) + +/*! + * @brief Ret low power mode + * + * @param None + * + * @retval None + */ +#define USBD_ResetLowerPowerMode() (USBD->CTRL_B.LPWREN = BIT_RESET) + +/*! + * @brief Set force suspend + * + * @param None + * + * @retval None + */ +#define USBD_SetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_SET) + +/*! + * @brief Reset force suspend + * + * @param None + * + * @retval None + */ +#define USBD_ResetForceSuspend() (USBD->CTRL_B.FORSUS = BIT_RESET) + +/*! + * @brief Read force suspend status + * + * @param None + * + * @retval None + */ +#define USBD_ReadForceSuspend() (USBD->CTRL_B.FORSUS) + +/*! + * @brief Set resume + * + * @param None + * + * @retval None + */ +#define USBD_SetResume() (USBD->CTRL_B.WUPREQ = BIT_SET) + +/*! + * @brief Reset resume + * + * @param None + * + * @retval None + */ +#define USBD_ResetResume() (USBD->CTRL_B.WUPREQ = BIT_RESET) + +/*! + * @brief Enable interrupt + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_EnableInterrupt(int) (USBD->CTRL |= int) + +/*! + * @brief Disable interrupt + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_DisableInterrupt(int) (USBD->CTRL &= (uint32_t)~int) + +/*! + * @brief Read the specified interrupt flag status + * + * @param int: Interrupt source + * + * @retval Flag status.0 or not 0 + */ +#define USBD_ReadIntFlag(int) (USBD->INTSTS & int) + +/*! + * @brief Clear the specified interrupt flag status + * + * @param int: Interrupt source + * + * @retval None + */ +#define USBD_ClearIntFlag(int) (USBD->INTSTS &= (uint32_t)~int) + +/*! + * @brief Read DOT field value in INTSTS rigister + * + * @param None + * + * @retval DOT field value + */ +#define USBD_ReadDir() (USBD->INTSTS_B.DOT) + +/*! + * @brief Read EPID field value in INTSTS rigister + * + * @param None + * + * @retval EPIDfield value + */ +#define USBD_ReadEP() ((USBD_EP_T)(USBD->INTSTS_B.EPID)) + +/*! + * @brief Read EP type + * + * @param ep: EP number + * + * @retval EP type + */ +#define USBD_ReadEPType(ep) (USBD->EP[ep].EP_B.TYPE) + +/*! + * @brief Read EP Tx status + * + * @param ep: EP number + * + * @retval EP Tx status + */ +#define USBD_ReadEPTxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.TXSTS)) + +/*! + * @brief Read EP Rx status + * + * @param ep: EP number + * + * @retval EP Rx status + */ +#define USBD_ReadEPRxStatus(ep) ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.RXSTS)) + +/*! + * @brief Read EP Tx address pointer + * + * @param ep: EP number + * + * @retval EP Tx address pointer + */ +#define USBD_ReadEPTxAddrPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR) + + +/*! + * @brief Read EP Tx count pointer + * + * @param ep: EP number + * + * @retval EP Tx count pointer + */ +#define USBD_ReadEPTxCntPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx address pointer + * + * @param ep: EP number + * + * @retval EP Rx address pointer + */ +#define USBD_ReadEPRxAddrPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Read EP Rx count pointer + * + * @param ep: EP number + * + * @retval EP Rx count pointer + */ +#define USBD_ReadEPRxCntPointer(ep) (uint32_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR) + +/*! + * @brief Set EP Tx addr + * + * @param ep: EP number + * + * @param addr: Tx addr + * + * @retval None + */ +#define USBD_SetEPTxAddr(ep, addr) (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Set EP Rx addr + * + * @param ep: EP number + * + * @param addr: Rx addr + * + * @retval None + */ +#define USBD_SetEPRxAddr(ep, addr) (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1) + +/*! + * @brief Read EP Tx addr + * + * @param ep: EP number + * + * @retval EP Tx addr + */ +#define USBD_ReadEPTxAddr(ep) ((uint16_t)*USBD_ReadEPTxAddrPointer(ep)) + +/*! + * @brief Read EP Rx addr + * + * @param ep: EP number + * + * @retval EP Rx addr + */ +#define USBD_ReadEPRxAddr(ep) ((uint16_t)*USBD_ReadEPRxAddrPointer(ep)) + +/*! + * @brief Set EP Rx Count + * + * @param ep: EP number + * + * @param cnt: Tx count + * + * @retval None + */ +#define USBD_SetEPTxCnt(ep, cnt) (*USBD_ReadEPTxCntPointer(ep) = cnt) + +/*! + * @brief Read EP Tx count + * + * @param ep: EP number + * + * @retval EP Tx count + */ +#define USBD_ReadEPTxCnt(ep) ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read EP Rx count + * + * @param ep: EP number + * + * @retval EP Rx count + */ +#define USBD_ReadEPRxCnt(ep) ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff) + +/*! + * @brief Read SETUP field value in EP register + * + * @param ep: EP number + * + * @retval SETUP field value + */ +#define USBD_ReadEPSetup(ep) (USBD->EP[ep].EP_B.SETUP) + +/*! + * @brief Set buffer table value + * + * @param tab: Buffer table value + * + * @retval None + */ +#define USBD_SetBufferTable(tab) (USBD->BUFFTB_B.BUFFTB = tab) + +/*! + * @brief Set device address + * + * @param addr: Device address + * + * @retval None + */ +#define USBD_SetDeviceAddr(addr) (USBD->ADDR_B.ADDR = addr) + +/*! + * @brief Read CTFR field value in EP register + * + * @param ep: Endpoint number + * + * @retval CTFR field value + */ +#define USBD_ReadEPRxFlag(ep) (USBD->EP[ep].EP_B.CTFR) + +/*! + * @brief Read CTFT field value in EP register + * + * @param ep: Endpoint number + * + * @retval CTFT field value + */ +#define USBD_ReadEPTxFlag(ep) (USBD->EP[ep].EP_B.CTFT) + +/*! + * @brief Enable USBD peripheral + * + * @param None + * + * @retval None + */ +#define USBD_Enable() (USBD->ADDR_B.USBDEN = BIT_SET) + +/*! + * @brief Disable USBD peripheral + * + * @param None + * + * @retval None + */ +#define USBD_Disable() (USBD->ADDR_B.USBDEN = BIT_RESET) + +/*! + * @brief Enable USBD2 peripheral + * + * @param None + * + * @retval None + */ +#define USBD2_Enable() (USBD->SWITCH = BIT_SET) + +/*! + * @brief Disable USBD2 peripheral + * + * @param None + * + * @retval None + */ +#define USBD2_Disable() (USBD->SWITCH = BIT_RESET) + +/*! + * @brief Read RXDPSTS field value in FRANUM register + * + * @param None + * + * @retval RXDPSTS field value + */ +#define USBD_ReadRDPS() (USBD->FRANUM_B.RXDPSTS) + +/*! + * @brief Read RXDMSTS field value in FRANUM register + * + * @param None + * + * @retval RXDMSTS field value + */ +#define USBD_ReadRDMS() (USBD->FRANUM_B.RXDMSTS) + +/*! + * @brief Read LOCK field value in FRANUM register + * + * @param None + * + * @retval LOCK field value + */ +#define USBD_ReadLOCK() (USBD->FRANUM_B.LOCK) + +/*! + * @brief Read LSOFNUM field value in FRANUM register + * + * @param None + * + * @retval LSOFNUM field value + */ +#define USBD_ReadLSOF() (USBD->FRANUM_B.LSOFNUM) + +/*! + * @brief Read FRANUM field value in FRANUM register + * + * @param None + * + * @retval FRANUM field value + */ +#define USBD_ReadFRANUM() (USBD->FRANUM_B.FRANUM) + +void USBD_SetEPType(USBD_EP_T ep, USBD_EP_TYPE_T type); + +void USBD_SetEPKind(USBD_EP_T ep); +void USBD_ResetEPKind(USBD_EP_T ep); + +void USBD_ResetEPRxFlag(USBD_EP_T ep); +void USBD_ResetEPTxFlag(USBD_EP_T ep); + +void USBD_ToggleTx(USBD_EP_T ep); +void USBD_ToggleRx(USBD_EP_T ep); +void USBD_ResetTxToggle(USBD_EP_T ep); +void USBD_ResetRxToggle(USBD_EP_T ep); + +void USBD_SetEpAddr(USBD_EP_T ep, uint8_t addr); + +void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status); +void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status); +void USBD_SetEPRxTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus); + +void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt); + +void USBD_WriteDataToEP(USBD_EP_T ep, uint8_t *wBuf, uint32_t wLen); +void USBD_ReadDataFromEP(USBD_EP_T ep, uint8_t *rBuf, uint32_t rLen); + +/**@} end of group USBD_Fuctions*/ +/**@} end of group USBD_Driver*/ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_USBD_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h new file mode 100644 index 0000000000..cb958d3dcb --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h @@ -0,0 +1,78 @@ +/*! + * @file apm32f10x_wwdt.h + * + * @brief This file contains all the functions prototypes for the WWDT firmware library + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10X_WWDT_H +#define __APM32F10X_WWDT_H + +#include "apm32f10x.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_Enumerations Enumerations + @{ +*/ + +/** + * @brief WWDT Timebase(Prescaler) define + */ +typedef enum +{ + WWDT_TIME_BASE_1 = 0x00000000, + WWDT_TIME_BASE_2 = 0x00000080, + WWDT_TIME_BASE_4 = 0x00000100, + WWDT_TIME_BASE_8 = 0x00000180 +}WWDT_TIME_BASE_T; + +/**@} end of group WWDT_Enumerations*/ + +/** @addtogroup WWDT_Fuctions Fuctions + @{ +*/ + +/** WWDT reset */ +void WWDT_Reset(void); + +/** Config WWDT Timebase */ +void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase); + +/** Config Window Data */ +void WWDT_ConfigWindowData(uint8_t windowData); + +/** Config Couter */ +void WWDT_ConfigCounter(uint8_t counter); + +/** Enable WWDT and Early Wakeup interrupt */ +void WWDT_EnableEWI(void); +void WWDT_Enable(uint8_t count); + +/** Read Flag and Clear Flag */ +uint8_t WWDT_ReadFlag(void); +void WWDT_ClearFlag(void); + +/**@} end of group WWDT_Fuctions*/ +/**@} end of group WWDT_Driver */ +/**@} end of group Peripherals_Library*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10X_WWDT_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c new file mode 100644 index 0000000000..c061ca94d4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c @@ -0,0 +1,1058 @@ +/*! + * @file apm32f10x_adc.c + * + * @brief This file provides all the ADC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_adc.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup ADC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset ADC peripheral registers to their default reset values. + * + * @param adc: Select ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Reset(ADC_T* adc) +{ + if(adc == ADC1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1); + } + else if(adc == ADC2) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2); + } + else if (adc == ADC3) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC3); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC3); + } +} + +/*! + * @brief Config the ADC peripheral according to the specified parameters in the adcConfig. + * + * @param adc: Select ADC peripheral. + * + * @param adcConfig: pointer to a ADC_Config_T structure. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig) +{ + uint32_t reg; + + reg = adc->CTRL1; + reg &= 0xFFF0FEFF; + reg |= (uint32_t)((adcConfig->mode) | ((uint32_t)adcConfig->scanConvMode << 8)); + adc->CTRL1 = reg; + + reg = adc->CTRL2; + reg &= 0xFFF1F7FD; + reg |= (uint32_t)(adcConfig->dataAlign | adcConfig->externalTrigConv | + ((uint32_t)adcConfig->continuosConvMode << 1)); + adc->CTRL2 = reg; + + reg = adc->REGSEQ1; + reg &= 0xFF0FFFFF; + reg |= (uint32_t)((adcConfig->nbrOfChannel - (uint8_t)1) << 20); + adc->REGSEQ1 = reg; +} + +/*! + * @brief Fills each ADC_Config_T member with its default value. + * + * @param adcConfig: pointer to a ADC_Config_T structure which will be initialized. + * + * @retval None + */ +void ADC_ConfigStructInit(ADC_Config_T* adcConfig) +{ + adcConfig->mode = ADC_MODE_INDEPENDENT; + adcConfig->scanConvMode = DISABLE; + adcConfig->continuosConvMode = DISABLE; + adcConfig->externalTrigConv = ADC_EXT_TRIG_CONV_TMR1_CC1; + adcConfig->dataAlign = ADC_DATA_ALIGN_RIGHT; + adcConfig->nbrOfChannel = 1; +} + +/*! + * @brief Enables the specified ADC peripheral. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Enable(ADC_T* adc) +{ + adc->CTRL2_B.ADCEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC peripheral. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_Disable(ADC_T* adc) +{ + adc->CTRL2_B.ADCEN = BIT_RESET; +} + +/*! + * @brief Disable the specified ADC DMA request. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableDMA(ADC_T* adc) +{ + adc->CTRL2_B.DMAEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC DMA request. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableDMA(ADC_T* adc) +{ + adc->CTRL2_B.DMAEN = BIT_RESET; +} + +/*! + * @brief Reset the specified ADC calibration registers. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ResetCalibration(ADC_T* adc) +{ + adc->CTRL2_B.CALRST = BIT_SET; +} + +/*! + * @brief Reads the specified ADC calibration reset status. + * + * @param adc: Select the ADC peripheral. + * + * @retval The status of ADC calibration reset. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Starts the specified ADC calibration. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_StartCalibration(ADC_T* adc) +{ + adc->CTRL2_B.CAL = BIT_SET; +} + +/*! + * @brief Reads the specified ADC calibration start flag. + * + * @param adc: Select the ADC peripheral. + * + * @retval The status of ADC calibration start. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Enables the specified ADC software start conversion. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableSoftwareStartConv(ADC_T* adc) +{ + adc->CTRL2 |= 0x00500000; +} + +/*! + * @brief Disable the specified ADC software start conversion. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableSoftwareStartConv(ADC_T* adc) +{ + adc->CTRL2 &= 0xFFAFFFFF; +} + +/*! + * @brief Reads the specified ADC Software start conversion Status. + * + * @param adc: Select the ADC peripheral. + * + * @retval The status of ADC Software start conversion registers. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Configures the specified ADC regular discontinuous mode. + * + * @param adc: Select the ADC peripheral. + * + * @param number: The number of the discontinuous mode regular channels. + * This parameter can be between 1 and 8. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number) +{ + adc->CTRL1_B.DISCNUMCFG |= number - 1; +} + +/*! + * @brief Enable the specified ADC regular discontinuous mode. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.REGDISCEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC regular discontinuous mode. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.REGDISCEN = BIT_RESET; +} + +/*! + * @brief Configures the specified ADC regular channel. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC channel. + * This parameter can be one of the following values: + * @arg ADC_CHANNEL_0: ADC channel 0 + * @arg ADC_CHANNEL_1: ADC channel 1 + * @arg ADC_CHANNEL_2: ADC channel 2 + * @arg ADC_CHANNEL_3: ADC channel 3 + * @arg ADC_CHANNEL_4: ADC channel 4 + * @arg ADC_CHANNEL_5: ADC channel 5 + * @arg ADC_CHANNEL_6: ADC channel 6 + * @arg ADC_CHANNEL_7: ADC channel 7 + * @arg ADC_CHANNEL_8: ADC channel 8 + * @arg ADC_CHANNEL_9: ADC channel 9 + * @arg ADC_CHANNEL_10: ADC channel 10 + * @arg ADC_CHANNEL_11: ADC channel 11 + * @arg ADC_CHANNEL_12: ADC channel 12 + * @arg ADC_CHANNEL_13: ADC channel 13 + * @arg ADC_CHANNEL_14: ADC channel 14 + * @arg ADC_CHANNEL_15: ADC channel 15 + * @arg ADC_CHANNEL_16: ADC channel 16 which is connected to TempSensor + * @arg ADC_CHANNEL_17: ADC channel 17 which is connected to Vrefint + * + * @param rank: The rank in the regular group sequencer + * This parameter must be between 1 to 16. + * + * @param sampleTime: the specified ADC channel SampleTime + * The parameter can be one of following values: + * @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles + * @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles + * @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles + * @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles + * @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles + * @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles + * @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles + * @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime) +{ + uint32_t temp1 = 0; + uint32_t temp2 = 0; + if(channel > ADC_CHANNEL_9) + { + temp1 = adc->SMPTIM1; + temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10)); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3 * (channel - 10)); + temp1 |= temp2; + adc->SMPTIM1 = temp1; + } + else + { + temp1 = adc->SMPTIM2; + temp2 = SMPCYCCFG_SET_SMPTIM2 << (3 * channel); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3 * channel); + temp1 |= temp2; + adc->SMPTIM2 = temp1; + } + + if(rank < 7) + { + temp1 = adc->REGSEQ3; + temp2 = REGSEQC_SET_REGSEQ3 << (5 * (rank - 1)); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (rank - 1)); + temp1 |= temp2; + adc->REGSEQ3 = temp1; + } + else if(rank < 13) + { + temp1 = adc->REGSEQ2; + temp2 = REGSEQC_SET_REGSEQ2 << (5 * (rank - 7)); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (rank - 7)); + temp1 |= temp2; + adc->REGSEQ2 = temp1; + } + else + { + temp1 = adc->REGSEQ1; + temp2 = REGSEQC_SET_REGSEQ1 << (5 * (rank - 13)); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (rank - 13)); + temp1 |= temp2; + adc->REGSEQ1 = temp1; + } +} + +/*! + * @brief Enable the specified ADC regular channel external trigger. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableExternalTrigConv(ADC_T* adc) +{ + adc->CTRL2_B.REGEXTTRGEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC regular channel external trigger. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableExternalTrigConv(ADC_T* adc) +{ + adc->CTRL2_B.REGEXTTRGEN = BIT_RESET; +} + +/*! + * @brief Reads the specified ADC conversion result data. + * + * @param adc: Select the ADC peripheral. + * + * @retval The Data conversion value. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint16_t ADC_ReadConversionValue(ADC_T* adc) +{ + return (uint16_t) adc->REGDATA; +} + +/*! + * @brief Reads the specified ADC conversion result data in dual mode. + * + * @param adc: Select the ADC peripheral. + * + * @retval The Data conversion value. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc) +{ + return (*(__IOM uint32_t *) RDG_ADDRESS); +} + +/*! + * @brief Enable the specified ADC automatic injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableInjectedConv(ADC_T* adc) +{ + adc->CTRL1_B.INJGACEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC automatic injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableInjectedConv(ADC_T* adc) +{ + adc->CTRL1_B.INJGACEN = BIT_RESET; +} + +/*! + * @brief Enable the specified ADC discontinuous mode for injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableInjectedDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.INJDISCEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC discontinuous mode for injected group. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableInjectedDiscMode(ADC_T* adc) +{ + adc->CTRL1_B.INJDISCEN = BIT_RESET; +} + +/*! + * @brief Configures the specified ADC external trigger for injected channels conversion + * + * @param adc: Select the ADC peripheral + * + * @param extTrigInjecConv: Select the ADC trigger to start injected conversion + * This parameter can be one of the following values: + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO : Select Timer1 TRGO event (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4 : Select Timer1 capture compare4 (for ADC1, ADC2 and ADC3) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO : Select Timer2 TRGO event (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1 : Select Timer2 capture compare1 (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4 : Select Timer3 capture compare4 (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO : Select Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4: External interrupt line 15 or Timer8 capture compare4 event + * (for ADC1 and ADC2) + * + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3 : Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2 : Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4 : Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4 : Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_EXT_TRIG_INJEC_CONV_NONE : Injected conversion started by software instead of external trigger + * (for ADC1, ADC2 and ADC3) + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv) +{ + adc->CTRL2_B.INJGEXTTRGSEL = RESET; + adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv; +} + +/*! + * @brief Ensable the specified ADC injected channels conversion through + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableExternalTrigInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC injected channels conversion through + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableExternalTrigInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; +} + +/*! + * @brief Enable the specified ADC start of the injected + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_SET; + adc->CTRL2_B.INJSWSC = BIT_SET; +} + +/*! + * @brief Disable the specified ADC start of the injected + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc) +{ + adc->CTRL2_B.INJEXTTRGEN = BIT_RESET; + adc->CTRL2_B.INJSWSC = BIT_RESET; +} + +/*! + * @brief Reads the specified ADC Software start injected conversion Status + * + * @param adc: Select the ADC peripheral + * + * @retval The status of ADC Software start injected conversion + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc) +{ + uint8_t ret; + ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET; + return ret; +} + +/*! + * @brief Configures the specified ADC injected channel. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_CHANNEL_0: ADC channel 0 + * @arg ADC_CHANNEL_1: ADC channel 1 + * @arg ADC_CHANNEL_2: ADC channel 2 + * @arg ADC_CHANNEL_3: ADC channel 3 + * @arg ADC_CHANNEL_4: ADC channel 4 + * @arg ADC_CHANNEL_5: ADC channel 5 + * @arg ADC_CHANNEL_6: ADC channel 6 + * @arg ADC_CHANNEL_7: ADC channel 7 + * @arg ADC_CHANNEL_8: ADC channel 8 + * @arg ADC_CHANNEL_9: ADC channel 9 + * @arg ADC_CHANNEL_10: ADC channel 10 + * @arg ADC_CHANNEL_11: ADC channel 11 + * @arg ADC_CHANNEL_12: ADC channel 12 + * @arg ADC_CHANNEL_13: ADC channel 13 + * @arg ADC_CHANNEL_14: ADC channel 14 + * @arg ADC_CHANNEL_15: ADC channel 15 + * @arg ADC_CHANNEL_16: ADC channel 16 which is connected to TempSensor + * @arg ADC_CHANNEL_17: ADC channel 17 which is connected to Vrefint + * + * @param rank: The rank in the injected group sequencer. + * This parameter must be between 1 to 4. + * + * @param sampleTime: the specified ADC channel SampleTime + * The parameter can be one of following values: + * @arg ADC_SAMPLE_TIME_1_5: ADC 1.5 clock cycles + * @arg ADC_SAMPLE_TIME_7_5: ADC 7.5 clock cycles + * @arg ADC_SAMPLE_TIME_13_5: ADC 13.5 clock cycles + * @arg ADC_SAMPLE_TIME_28_5: ADC 28.5 clock cycles + * @arg ADC_SAMPLE_TIME_41_5: ADC 41.5 clock cycles + * @arg ADC_SAMPLE_TIME_55_5: ADC 55.5 clock cycles + * @arg ADC_SAMPLE_TIME_71_5: ADC 71.5 clock cycles + * @arg ADC_SAMPLE_TIME_239_5: ADC 239.5 clock cycles + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime) +{ + uint32_t temp1 = 0; + uint32_t temp2 = 0; + uint32_t temp3 = 0; + if (channel > ADC_CHANNEL_9) + { + temp1 = adc->SMPTIM1; + temp2 = SMPCYCCFG_SET_SMPTIM1 << (3*(channel - 10)); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3*(channel - 10)); + temp1 |= temp2; + adc->SMPTIM1 = temp1; + } + else + { + temp1 = adc->SMPTIM2; + temp2 = SMPCYCCFG_SET_SMPTIM2 << (3 * channel); + temp1 &= ~temp2; + temp2 = (uint32_t)sampleTime << (3 * channel); + temp1 |= temp2; + adc->SMPTIM2 = temp1; + } + temp1 = adc->INJSEQ; + temp3 = (temp1 & INJSEQ_SET_INJSEQLEN)>> 20; + temp2 = INJSEQ_SET_INJSEQC << (5 * (uint8_t)((rank + 3) - (temp3 + 1))); + temp1 &= ~temp2; + temp2 = (uint32_t)channel << (5 * (uint8_t)((rank + 3) - (temp3 + 1))); + temp1 |= temp2; + adc->INJSEQ = temp1; +} + +/*! + * @brief Configures the specified ADC injected channel. + * + * @param adc: Select the ADC peripheral. + * + * @param length: The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length) +{ + adc->INJSEQ_B.INJSEQLEN = RESET; + adc->INJSEQ_B.INJSEQLEN |= length - 1; +} + +/*! + * @brief Configures the specified ADC injected channel conversion value offset. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJEC_CHANNEL_1: select Injected Channel 1 + * @arg ADC_INJEC_CHANNEL_2: select Injected Channel 2 + * @arg ADC_INJEC_CHANNEL_3: select Injected Channel 3 + * @arg ADC_INJEC_CHANNEL_4: select Injected Channel 4 + * + * @param offSet: The specified ADC injected channel offset. + * This parameter must be a 12bit value. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet) +{ + __IOM uint32_t tmp = 0; + + tmp = (uint32_t)adc; + tmp += channel; + + *(__IOM uint32_t *) tmp = (uint32_t)offSet; +} + +/*! + * @brief Reads the ADC injected channel conversion value. + * + * @param adc: Select the ADC peripheral. + * + * @param channel: Select the ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_INJEC_CHANNEL_1: select Injected Channel 1 + * @arg ADC_INJEC_CHANNEL_2: select Injected Channel 2 + * @arg ADC_INJEC_CHANNEL_3: select Injected Channel 3 + * @arg ADC_INJEC_CHANNEL_4: select Injected Channel 4 + * + * @retval The Data of conversion value. + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel) +{ + __IOM uint32_t temp = 0; + + temp = (uint32_t)adc; + temp += channel + INJDATA_OFFSET; + + return (uint16_t) (*(__IOM uint32_t*) temp); +} + +/*! + * @brief Enable the specified ADC analog watchdog. + * + * @param adc: Select the ADC peripheral. + * + * @param analogWatchdog: The ADC analog watchdog configuration + * This parameter can be one of the following values: + * @arg ADC_ANALOG_WATCHDOG_SINGLE_REG : Analog watchdog on a single regular channel + * @arg ADC_ANALOG_WATCHDOG_SINGLE_INJEC : Analog watchdog on a single injected channel + * @arg ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC : Analog watchdog on a single regular or injected channel + * @arg ADC_ANALOG_WATCHDOG_ALL_REG : Analog watchdog on all regular channel + * @arg ADC_ANALOG_WATCHDOG_ALL_INJEC : Analog watchdog on all injected channel + * @arg ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC : Analog watchdog on all regular and injected channels + * @arg ADC_ANALOG_WATCHDOG_NONE : No channel guarded by the analog watchdog + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog) +{ + adc->CTRL1 &= 0xFF3FFDFF; + adc->CTRL1 |= analogWatchdog; +} + +/*! + * @brief Disable the specified ADC analog watchdog. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableAnalogWatchdog(ADC_T* adc) +{ + adc->CTRL1 &= 0xFF3FFDFF; +} + +/*! + * @brief Configures the specified ADC high and low thresholds of the analog watchdog. + * + * @param adc: Select the ADC peripheral. + * + * @param highThreshold: The ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * + * @param lowThreshold: The ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold) +{ + adc->AWDHT = highThreshold; + adc->AWDLT = lowThreshold; +} + +/*! + * @brief Configures the specified ADC analog watchdog guarded single channel + * + * @param adc: Select the ADC peripheral + * + * @param channel: Select the ADC channel + * This parameter can be one of the following values: + * @arg ADC_Channel_0: Select ADC Channel 0 + * @arg ADC_Channel_1: Select ADC Channel 1 + * @arg ADC_Channel_2: Select ADC Channel 2 + * @arg ADC_Channel_3: Select ADC Channel 3 + * @arg ADC_Channel_4: Select ADC Channel 4 + * @arg ADC_Channel_5: Select ADC Channel 5 + * @arg ADC_Channel_6: Select ADC Channel 6 + * @arg ADC_Channel_7: Select ADC Channel 7 + * @arg ADC_Channel_8: Select ADC Channel 8 + * @arg ADC_Channel_9: Select ADC Channel 9 + * @arg ADC_Channel_10: Select ADC Channel 10 + * @arg ADC_Channel_11: Select ADC Channel 11 + * @arg ADC_Channel_12: Select ADC Channel 12 + * @arg ADC_Channel_13: Select ADC Channel 13 + * @arg ADC_Channel_14: Select ADC Channel 14 + * @arg ADC_Channel_15: Select ADC Channel 15 + * @arg ADC_Channel_16: Select ADC Channel 16 which is connected to TempSensor + * @arg ADC_Channel_17: Select ADC Channel 17 which is connected to Vrefint + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel) +{ + adc->CTRL1_B.AWDCHSEL = BIT_RESET; + adc->CTRL1 |= channel; +} + +/*! + * @brief Enable the specified ADC temperature sensor and Vrefint channel. + * + * @param adc: Select the ADC peripheral. + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableTempSensorVrefint(ADC_T* adc) +{ + adc->CTRL2_B.TSVREFEN = BIT_SET; +} + +/*! + * @brief Disable the specified ADC temperature sensor and Vrefint channel. + * + * @param adc: Select the ADC peripheral + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableTempSensorVrefint(ADC_T* adc) +{ + adc->CTRL2_B.TSVREFEN = BIT_RESET; +} + +/*! + * @brief Enable the specified ADC interrupt. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt sources + * This parameter can be any combination of the following values: + * @arg ADC_INT_AWD : Enable Analog watchdog interrupt + * @arg ADC_INT_EOC : Enable End of conversion interrupt + * @arg ADC_INT_INJEOC : Enable End of injected conversion interrupt + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt) +{ + uint8_t mask; + + mask = (uint8_t)interrupt; + adc->CTRL1 |= (uint8_t)mask; +} + +/*! + * @brief Disable the specified ADC interrupt. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt sources + * This parameter can be any combination of the following values: + * @arg ADC_INT_AWD : Disable Analog watchdog interrupt + * @arg ADC_INT_EOC : Disable End of conversion interrupt + * @arg ADC_INT_INJEOC : Disable End of injected conversion interrupt + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt) +{ + uint8_t mask; + + mask = (uint8_t)interrupt; + adc->CTRL1 &= (~(uint32_t)mask); +} + +/*! + * @brief Reads the specified ADC flag + * + * @param adc: Select the ADC peripheral + * + * @param flag: Select the flag to check + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD : Analog watchdog flag + * @arg ADC_FLAG_EOC : End of conversion flag + * @arg ADC_FLAG_INJEOC: End of injected group conversion flag + * @arg ADC_FLAG_INJCS : Injected group conversion Start flag + * @arg ADC_FLAG_REGCS : Regular group conversion Start flag + * + * @retval The status of ADC flag + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag) +{ + uint8_t status = RESET; + + if ((adc->STS & flag) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the specified ADC flag + * + * @param adc: Select the ADC peripheral + * + * @param flag: Select the flag to clear + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD : Analog watchdog flag + * @arg ADC_FLAG_EOC : End of conversion flag + * @arg ADC_FLAG_INJEOC: End of injected group conversion flag + * @arg ADC_FLAG_INJCS : Injected group conversion Start flag + * @arg ADC_FLAG_REGCS : Regular group conversion Start flag + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag) +{ + adc->STS = ~(uint32_t)flag; +} + +/*! + * @brief Reads the specified ADC Interrupt flag. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt source. + * This parameter can be one of the following values: + * @arg ADC_INT_AWD : Enable Analog watchdog interrupt + * @arg ADC_INT_EOC : Enable End of conversion interrupt + * @arg ADC_INT_INJEOC : Enable End of injected conversion interrupt + * + * @retval The status of ADC interrupt + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt) +{ + uint8_t bitStatus = RESET; + uint32_t itmask = 0; + uint32_t enableStatus = 0; + + itmask = interrupt >> 8; + enableStatus = (adc->CTRL1 & (uint8_t)interrupt); + + if (((adc->STS & itmask) != (uint32_t)RESET) && enableStatus) + { + bitStatus = SET; + } + else + { + bitStatus = RESET; + } + return bitStatus; +} + +/*! + * @brief Clears the specified ADC Interrupt pending bits. + * + * @param adc: Select the ADC peripheral. + * + * @param interrupt: Select the ADC interrupt source. + * This parameter can be any combination of the following values: + * @arg ADC_INT_AWD : Enable Analog watchdog interrupt + * @arg ADC_INT_EOC : Enable End of conversion interrupt + * @arg ADC_INT_INJEOC : Enable End of injected conversion interrupt + * + * @retval None + * + * @note adc can be ADC1, ADC2 or ADC3. + */ +void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt) +{ + uint8_t mask = 0; + + mask = (uint8_t)(interrupt >> 8); + adc->STS = ~(uint32_t)mask; +} + +/**@} end of group ADC_Fuctions*/ +/**@} end of group ADC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c new file mode 100644 index 0000000000..a7bfad2fdb --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c @@ -0,0 +1,234 @@ +/*! + * @file apm32f10x_bakpr.c + * + * @brief This file provides all the BAKPR firmware functions. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_bakpr.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup BAKPR_Driver ADC Driver + @{ +*/ + +/** @addtogroup BAKPR_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the BAKPR peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void BAKPR_Reset(void) +{ + RCM_EnableBackupReset(); + RCM_DisableBackupReset(); +} + +/*! + * @brief Deinitializes the BAKPR peripheral registers to their default reset values. + * + * @param value: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BAKPR_TAMPER_PIN_LEVEL_HIGH: Tamper pin active on high level + * @arg BAKPR_TAMPER_PIN_LEVEL_LOW: Tamper pin active on low level + * + * @retval None + */ +void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value) +{ + BAKPR->CTRL_B.TPALCFG = value; +} + +/*! + * @brief Enables the Tamper Pin activation. + * + * @param None + * + * @retval None + */ +void BAKPR_EnableTamperPin(void) +{ + BAKPR->CTRL_B.TPFCFG = ENABLE ; +} + +/*! + * @brief Disables the Tamper Pin activation. + * + * @param None + * + * @retval None + */ +void BAKPR_DisableTamperPin(void) +{ + BAKPR->CTRL_B.TPFCFG = DISABLE ; +} + +/*! + * @brief Enables the Tamper Pin Interrupt. + * + * @param None + * + * @retval None + */ +void BAKPR_EnableInterrupt(void) +{ + BAKPR->CSTS_B.TPIEN = ENABLE ; +} + +/*! + * @brief Disables the Tamper Pin Interrupt. + * + * @param None + * + * @retval None + */ +void BAKPR_DisableInterrupt(void) +{ + BAKPR->CSTS_B.TPIEN = DISABLE ; +} + +/*! + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param soure: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BAKPR_RTC_OUTPUT_SOURCE_NONE : no RTC output on the Tamper pin. + * @arg BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK: output the RTC clock with frequency divided by 64 on the Tamper pin. + * @arg BAKPR_RTC_OUTPUT_SOURCE_ALARM : output the RTC Alarm pulse signal on the Tamper pin. + * @arg BAKPR_RTC_OUTPUT_SOURCE_SECOND : output the RTC Second pulse signal on the Tamper pin. + * + * @retval None + */ +void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure) +{ + if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE) + { + BAKPR->CLKCAL = RESET; + } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK) + { + BAKPR->CLKCAL_B.CALCOEN = BIT_SET; + } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM) + { + BAKPR->CLKCAL_B.ASPOEN = BIT_SET; + } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND) + { + BAKPR->CLKCAL_B.ASPOSEL = BIT_SET; + } +} + +/*! + * @brief Sets RTC Clock Calibration value. + * + * @param calibrationValue: Specifies the calibration value. + * This parameter must be a number between 0 and 0x7F. + * + * @retval None + */ +void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue) +{ + BAKPR->CLKCAL_B.CALVALUE = calibrationValue; +} + +/*! + * @brief Set user data to the specified Data Backup Register. + * + * @param bakrData : specifies the Data Backup Register. + * This parameter can be BAKPR_DATAx where x is between 1 and 42. + * + * @param data : data to set + * This parameter can be a 16bit value. + * + * @retval None + */ +void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data) +{ + __IOM uint32_t tmp = 0; + + tmp = (uint32_t)BAKPR_BASE; + tmp += bakrData; + + *(__IOM uint32_t *) tmp = data; +} + +/*! + * @brief Reads user data from the specified Data Backup Register. + * + * @param bakrData : specifies the Data Backup Register. + * This parameter can be BAKPR_DATAx where x is between 1 and 42. + * + * @retval The content of the specified Data Backup Register + */ +uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData) +{ + __IOM uint32_t tmp = 0; + + tmp = (uint32_t)BAKPR_BASE; + tmp += bakrData; + + return (*(__IOM uint32_t *) tmp); +} + +/*! + * @brief Read whether the Tamper Pin Event flag is set or not. + * + * @param None + * + * @retval Tamper Pin Event flag state + */ +uint8_t BAKPR_ReadStatusFlag(void) +{ + return BAKPR->CSTS_B.TEFLG; +} + +/*! + * @brief Clears Tamper Pin Event pending flag. + * + * @param None + * + * @retval None + */ +void BAKPR_ClearStatusFlag(void) +{ + BAKPR->CSTS_B.TECLR = BIT_SET; +} + +/*! + * @brief Get whether the Tamper Pin Interrupt has occurred or not. + * + * @param None + * + * @retval Tamper Pin Interrupt State + */ +uint8_t BAKPR_ReadIntFlag(void) +{ + return BAKPR->CSTS_B.TIFLG; +} + +/*! + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @param None + * + * @retval None + */ +void BAKPR_ClearIntFlag(void) +{ + BAKPR->CSTS_B.TICLR = BIT_SET; +} + +/**@} end of group BAKPR_Fuctions*/ +/**@} end of group BAKPR_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c new file mode 100644 index 0000000000..7efff90f9d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c @@ -0,0 +1,1110 @@ +/*! + * @file apm32f10x_can.c + * + * @brief This file provides all the CAN firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_can.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset CAN registers + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_Reset(CAN_T* can) +{ + if (can == CAN1) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CAN1); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CAN1); + } + else if (can == CAN2) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CAN2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CAN2); + } +} + +/*! + * @brief Initialization parameter configuration + * + * @param can: Select the CAN peripheral which can be CAN1 or CAN2. + * + * @param canConfig: Point to a CAN_Config_T structure. + * + * @retval ERROR or SUCCEESS + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig) +{ + uint8_t initStatus = ERROR; + uint32_t wait_ack = 0x00000000; + + /** Exit from sleep mode */ + can->MCTRL_B.SLEEPREQ = BIT_RESET; + /** Request initialisation */ + can->MCTRL_B.INITREQ = BIT_SET; + + /** Wait the acknowledge */ + while(((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF)) + { + wait_ack++; + } + /** Check acknowledge */ + if(((can->MSTS_B.INITFLG) != BIT_SET)) + { + initStatus = ERROR; + } + else + { + if(canConfig->timeTrigComMode == ENABLE) + { + can->MCTRL_B.TTCM = BIT_SET; + } + else + { + can->MCTRL_B.TTCM = BIT_RESET; + } + + if(canConfig->autoBusOffManage == ENABLE) + { + can->MCTRL_B.ALBOFFM = BIT_SET; + } + else + { + can->MCTRL_B.ALBOFFM = BIT_RESET; + } + + if(canConfig->autoWakeUpMode == ENABLE) + { + can->MCTRL_B.AWUPCFG = BIT_SET; + } + else + { + can->MCTRL_B.AWUPCFG = BIT_RESET; + } + + if(canConfig->nonAutoRetran == ENABLE) + { + can->MCTRL_B.ARTXMD = BIT_SET; + } + else + { + can->MCTRL_B.ARTXMD = BIT_RESET; + } + + if(canConfig->rxFIFOLockMode == ENABLE) + { + can->MCTRL_B.RXFLOCK = BIT_SET; + } + else + { + can->MCTRL_B.RXFLOCK = BIT_RESET; + } + + if(canConfig->txFIFOPriority == ENABLE) + { + can->MCTRL_B.TXFPCFG = BIT_SET; + } + else + { + can->MCTRL_B.TXFPCFG = BIT_RESET; + } + + /** Set the bit timing register */ + can->BITTIM &= (uint32_t)0x3fffffff; + can->BITTIM |= (uint32_t)canConfig->mode << 30; + can->BITTIM_B.RSYNJW = canConfig->syncJumpWidth; + can->BITTIM_B.TIMSEG1 = canConfig->timeSegment1; + can->BITTIM_B.TIMSEG2 = canConfig->timeSegment2; + can->BITTIM_B.BRPSC = canConfig->prescaler - 1; + + /** Request leave initialisation */ + can->MCTRL_B.INITREQ = BIT_RESET; + + wait_ack = 0; + /** Wait the acknowledge */ + while(((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF)) + { + wait_ack++; + } + /** Check acknowledge */ + if(((can->MSTS_B.INITFLG) != BIT_RESET)) + { + initStatus = ERROR; + } + else + { + initStatus = SUCCESS; + } + } + return initStatus; +} + +/*! + * @brief Congig the CAN peripheral according to the specified parameters in the filterConfig. + * + * @param can: Select the CAN peripheral which can be CAN1 or CAN2. + * + * @param filterConfig :Point to a CAN_FILTER_CONFIG_T structure. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig) +{ + can->FCTRL_B.FINITEN = BIT_SET; + + can->FACT &= ~(1 << filterConfig->filterNumber); + + /** Filter Scale */ + if(filterConfig->filterScale == CAN_FILTER_SCALE_16BIT) + { + /** 16-bit scale for the filter */ + can->FSCFG &= ~(1 << filterConfig->filterNumber); + + can->sFilterRegister[filterConfig->filterNumber].FBANK1 = + ((0x0000FFFF & filterConfig->filterMaskIdLow) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + can->sFilterRegister[filterConfig->filterNumber].FBANK2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdHigh); + } + + if(filterConfig->filterScale == CAN_FILTER_SCALE_32BIT) + { + can->FSCFG |= (1 << filterConfig->filterNumber); + + can->sFilterRegister[filterConfig->filterNumber].FBANK1 = + ((0x0000FFFF & filterConfig->filterIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterIdLow); + + can->sFilterRegister[filterConfig->filterNumber].FBANK2 = + ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) | + (0x0000FFFF & filterConfig->filterMaskIdLow); + } + + /** Filter Mode */ + if(filterConfig->filterMode == CAN_FILTER_MODE_IDMASK) + { + can->FMCFG &= ~(1 << filterConfig->filterNumber); + } + else + { + can->FMCFG |= (1 << filterConfig->filterNumber); + } + + /** Filter FIFO assignment */ + if(filterConfig->filterFIFO == CAN_FILTER_FIFO_0) + { + can->FFASS &= ~(1 << filterConfig->filterNumber); + } + if(filterConfig->filterFIFO == CAN_FILTER_FIFO_1) + { + can->FFASS |= (1 << filterConfig->filterNumber); + } + + /** Filter activation */ + if(filterConfig->filterActivation == ENABLE) + { + can->FACT |= (1 << filterConfig->filterNumber); + } + can->FCTRL_B.FINITEN = BIT_RESET; +} + +/*! + * @brief Initialize a CAN_Config_T structure with the initial value. + * + * @param canConfig :Point to a CAN_Config_T structure. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ConfigStructInit(CAN_Config_T* canConfig) +{ + canConfig->timeTrigComMode = DISABLE; + canConfig->autoBusOffManage = DISABLE; + canConfig->autoWakeUpMode = DISABLE; + canConfig->nonAutoRetran = DISABLE; + canConfig->rxFIFOLockMode = DISABLE; + canConfig->txFIFOPriority = DISABLE; + canConfig->mode = CAN_MODE_NORMAL; + canConfig->syncJumpWidth = CAN_SJW_1; + canConfig->timeSegment1 = CAN_TIME_SEGMENT1_4; + canConfig->timeSegment2 = CAN_TIME_SEGMENT2_3; + canConfig->prescaler = 1; +} + +/*! + * @brief Enables the DBG Freeze for CAN. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_EnableDBGFreeze(CAN_T* can) +{ + can->MCTRL_B.DBGFRZE = ENABLE; +} + +/*! + * @brief Disable the DBG Freeze for CAN. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_DisableDBGFreeze(CAN_T* can) +{ + can->MCTRL_B.DBGFRZE = DISABLE; +} + +/*! + * @brief Enables the CAN Time TriggerOperation communication mode. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_EnableTTCComMode(CAN_T* can) +{ + can->MCTRL_B.TTCM = ENABLE; + + can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_SET; + can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_SET; + can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_SET; +} + +/*! + * @brief Disable the CAN Time TriggerOperation communication mode. + * + * @param can: Select the CAN peripheral. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_DisableTTCComMode(CAN_T* can) +{ + can->MCTRL_B.TTCM = DISABLE; + + can->sTxMailBox[0].TXDLEN_B.TXTS = BIT_RESET; + can->sTxMailBox[1].TXDLEN_B.TXTS = BIT_RESET; + can->sTxMailBox[2].TXDLEN_B.TXTS = BIT_RESET; +} + +/*! + * @brief Initiates the transmission of a message. + * + * @param can: Select the CAN peripheral. + * + * @param TxMessage: pointer to a CAN_TX_MESSAGE_T structure. + * + * @retval The number of the mailbox which is used for transmission or 3 if No mailbox is empty. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage) +{ + uint8_t transmit_milbox = 0; + + /** Select one empty transmit mailbox */ + if((can->TXSTS & 0x04000000) == 0x04000000) + { + transmit_milbox = 0; + } + else if((can->TXSTS & 0x08000000) == 0x08000000) + { + transmit_milbox = 1; + } + else if((can->TXSTS & 0x10000000) == 0x10000000) + { + transmit_milbox = 2; + } else + { + return 3; //!< No mailbox is empty + } + + /** Set up the Id */ + can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001; + if(TxMessage->typeID == CAN_TYPEID_STD) + { + can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->stdID << 21) | (TxMessage->remoteTxReq); + } else + { + can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq); + } + + /** Set up the TXDLEN */ + TxMessage->dataLengthCode &= 0x0F; + can->sTxMailBox[transmit_milbox].TXDLEN &= (uint32_t)0xFFFFFFF0; + can->sTxMailBox[transmit_milbox].TXDLEN |= TxMessage->dataLengthCode; + + /** Set up the data field */ + can->sTxMailBox[transmit_milbox].TXMDL = ((uint32_t)TxMessage->data[3] << 24) | ((uint32_t)TxMessage->data[2] << 16) + | ((uint32_t)TxMessage->data[1] << 8) | ((uint32_t)TxMessage->data[0]); + can->sTxMailBox[transmit_milbox].TXMDH = ((uint32_t)TxMessage->data[7] << 24) | ((uint32_t)TxMessage->data[6] << 16) + | ((uint32_t)TxMessage->data[5] << 8) | ((uint32_t)TxMessage->data[4]); + /** Request transmission */ + can->sTxMailBox[transmit_milbox].TXMID |= 0x00000001; + + return transmit_milbox; +} + +/*! + * @brief Checks the transmission of a message. + * + * @param can: Select the CAN peripheral. + * + * @param transmitMailbox: the number of the mailbox + * + * @retval state: 0: Status of transmission is Failed + * 1: Status of transmission is Ok + * 2: transmit pending + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) +{ + uint32_t state = 0; + + switch (TxMailbox) + { + case (CAN_TX_MAILBIX_0): + state = can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000); + break; + case (CAN_TX_MAILBIX_1): + state = can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000); + break; + case (CAN_TX_MAILBIX_2): + state = can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000); + break; + default: + state = 0; + break; + } + switch (state) + { + /** transmit pending */ + case (0x0): state = 2; + break; + /* transmit failed */ + case (0x00000001 | 0x04000000): state = 0; + break; + case (0x00000100 | 0x08000000): state = 0; + break; + case (0x00010000 | 0x10000000): state = 0; + break; + /* transmit succeeded */ + case (0x00000001 | 0x00000002 | 0x04000000):state = 1; + break; + case (0x00000100 | 0x00000200 | 0x08000000):state = 1; + break; + case (0x00010000 | 0x00020000 | 0x10000000):state = 1; + break; + default: state = 0; + break; + } + return (uint8_t) state; +} + +/*! + * @brief Cancels a transmit request. + * + * @param can: Select the CAN peripheral. + * + * @param mailBox: the number of the mailbox + * This parameter can be one of the following values: + * @arg CAN_TX_MAILBIX_0 : Tx mailbox 0 + * @arg CAN_TX_MAILBIX_1 : Tx mailbox 1 + * @arg CAN_TX_MAILBIX_2 : Tx mailbox 2 + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox) +{ + switch (TxMailbox) + { + case CAN_TX_MAILBIX_0: + can->TXSTS_B.ABREQFLG0 = BIT_SET; + break; + case CAN_TX_MAILBIX_1: + can->TXSTS_B.ABREQFLG1 = BIT_SET; + break; + case CAN_TX_MAILBIX_2: + can->TXSTS_B.ABREQFLG2 = BIT_SET; + break; + default: + break; + } +} + +/*! + * @brief Receives a message and save to a CAN_RX_MESSAGE_T structure. + * + * @param can: Select the CAN peripheral. + * + * @param FIFONumber: Receive FIFO number. + * This parameter can be one of the following values: + * @arg CAN_RX_FIFO_0 : Receive FIFO 0 + * @arg CAN_RX_FIFO_1 : Receive FIFO 1 + * + * @param RxMessage: pointer to a structure to receive the message. + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage) +{ + /* Get the Id */ + RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID)); + if(RxMessage->typeID == CAN_TYPEID_STD) + { + RxMessage->stdID = (can->sRxMailBox[FIFONumber].RXMID >> 21) & 0x000007FF; + } + else + { + RxMessage->extID = (can->sRxMailBox[FIFONumber].RXMID >> 3) & 0x1FFFFFFF; + } + + RxMessage->remoteTxReq = can->sRxMailBox[FIFONumber].RXMID_B.RFTXREQ; + RxMessage->dataLengthCode = can->sRxMailBox[FIFONumber].RXDLEN_B.DLCODE; + RxMessage->filterMatchIndex = can->sRxMailBox[FIFONumber].RXDLEN_B.FMIDX; + /** Get the data field */ + RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1; + RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2; + RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE3; + RxMessage->data[3] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE4; + RxMessage->data[4] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE5; + RxMessage->data[5] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6; + RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7; + RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE8; + + if(FIFONumber == CAN_RX_FIFO_0) + { + can->RXF0_B.RFOM0 = BIT_SET; + } + else + { + can->RXF1_B.RFOM1 = BIT_SET; + } +} + +/*! + * @brief Releases the specified FIFO. + * + * @param can: Select the CAN peripheral. + * + * @param FIFONumber: Receive FIFO number + * This parameter can be one of the following values: + * @arg CAN_RX_FIFO_0 : Receive FIFO 0 + * @arg CAN_RX_FIFO_1 : Receive FIFO 1 + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber) +{ + if(FIFONumber == CAN_RX_FIFO_0) + { + can->RXF0_B.RFOM0 = BIT_SET; + } + else + { + can->RXF1_B.RFOM1 = BIT_SET; + } +} + +/*! + * @brief Returns the number of pending messages. + * + * @param can: Select the CAN peripheral. + * + * @param FIFONumber: Receive FIFO number + * This parameter can be one of the following values: + * @arg CAN_RX_FIFO_0 : Receive FIFO 0 + * @arg CAN_RX_FIFO_1 : Receive FIFO 1 + * + * @retval The number of pending message. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber) +{ + if(FIFONumber == CAN_RX_FIFO_0) + { + return can->RXF0 & 0x03; + } + else + { + return can->RXF1 & 0x03; + } +} + +/*! + * @brief Select the CAN Operation mode + * + * @param can: Select the CAN peripheral. + * + * @param operatingMode: CAN Operating Mode + * This parameter can be one of the following values: + * @arg CAN_OPERATING_MODE_INIT : Initialization mode + * @arg CAN_OPERATING_MODE_NORMAL: Normal mode + * @arg CAN_OPERATING_MODE_SLEEP : sleep mode + * + * @retval modeState:status of the requested mode + * 0:CAN failed entering the specific mode + * 1:CAN Succeed entering the specific mode + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode) +{ + uint8_t states = 0; + uint32_t time_out = 0x0000FFFF; + + if(operatingMode == CAN_OPERATING_MODE_INIT) + { + can->MCTRL_B.SLEEPREQ = BIT_RESET; + can->MCTRL_B.INITREQ = BIT_SET; + + while((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + { + time_out --; + } + if((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET)) + { + states = 1; + } + } + else if(operatingMode == CAN_OPERATING_MODE_NORMAL) + { + can->MCTRL_B.SLEEPREQ = BIT_RESET; + can->MCTRL_B.INITREQ = BIT_RESET; + + time_out = 0x0000FFFF; + + while((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + { + time_out --; + } + if((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET)) + { + states = 1; + } + } + else if(operatingMode == CAN_OPERATING_MODE_SLEEP) + { + can->MCTRL_B.SLEEPREQ = BIT_SET; + can->MCTRL_B.INITREQ = BIT_RESET; + + time_out = 0x0000FFFF; + + while((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0)) + { + time_out --; + } + if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) + { + states = 1; + } + } + return states ; +} + +/*! + * @brief Into the low power mode. + * + * @param can: Select the CAN peripheral. + * + * @retval status: Status of entering sleep mode. + * 0: Enter sleep fail + * 1: Enter sleep success + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_SleepMode(CAN_T* can) +{ + can->MCTRL_B.SLEEPREQ = BIT_SET; + can->MCTRL_B.INITREQ = BIT_RESET; + + if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET)) + { + return 1; + } + return 0; +} + +/*! + * @brief Wakes the CAN up. + * + * @param can: Select the CAN peripheral. + * + * @retval status: Status of waking the CAN up + * 0: WakeUp CAN fail, + * 1: WakeUp CAN success + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_WakeUpMode(CAN_T* can) +{ + uint32_t time_out = 0x0000FFFF; + + can->MCTRL_B.SLEEPREQ = BIT_RESET; + while((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0)) + { + time_out --; + } + if(can->MSTS_B.SLEEPFLG == BIT_RESET) + { + return 1; + } + return 0; +} + +/*! + * @brief Read the can's last error code (LERRC) + * + * @param can: Select the CAN peripheral. + * + * @retval The Last Error Code. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadLastErrorCode(CAN_T* can) +{ + return can->ERRSTS_B.LERRC; +} + +/*! + * @brief Read the can Receive Error Counter(RXERRCNT) + * + * @param can: Select the CAN peripheral. + * + * @retval CAN Receive Error Counter. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadRxErrorCounter(CAN_T* can) +{ + return can->ERRSTS_B.RXERRCNT; +} + +/*! + * @brief Read the LSB of the 9-bit can Transmit Error Counter(TXERRCNT). + * + * @param can: Select the CAN peripheral. + * + * @retval Least Significant Byte Of The 9-Bit Transmit Error Counter. + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can) +{ + return can->ERRSTS_B.TXERRCNT; +} + +/*! + * @brief Enables the specified can interrupts. + * + * @param can: Select the CAN peripheral. + * + * @param interrupts: specifies the CAN interrupt sources + * This parameter can be any combination of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts) +{ + can->INTEN |= interrupts; +} + +/*! + * @brief Disable the specified can interrupts. + * + * @param can: Select the CAN peripheral. + * + * @param interrupts: specifies the CAN interrupt sources + * This parameter can be any combination of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts) +{ + can->INTEN &= ~interrupts; +} + +/*! + * @brief Read whether the specified CAN flag is set or not. + * + * @param can: Select the CAN peripheral. + * + * @param flag: specifies the CAN flag. + * This parameter can be one of the following values: + * @arg CAN_FLAG_ERRW : Error Warning Flag + * @arg CAN_FLAG_ERRP : Error Passive Flag + * @arg CAN_FLAG_BOF : Bus-Off Flag + * @arg CAN_FLAG_LERRC : Last error record code Flag + * @arg CAN_FLAG_WUPI : Wake up Flag + * @arg CAN_FLAG_SLEEP : Sleep acknowledge Flag + * @arg CAN_FLAG_F0MP : FIFO 0 Message Pending Flag + * @arg CAN_FLAG_F0FULL : FIFO 0 Full Flag + * @arg CAN_FLAG_F0OVR : FIFO 0 Overrun Flag + * @arg CAN_FLAG_F1MP : FIFO 1 Message Pending Flag + * @arg CAN_FLAG_F1FULL : FIFO 1 Full Flag + * @arg CAN_FLAG_F1OVR : FIFO 1 Overrun Flag + * @arg CAN_FLAG_REQC0 : Request MailBox0 Flag + * @arg CAN_FLAG_REQC1 : Request MailBox1 Flag + * @arg CAN_FLAG_REQC2 : Request MailBox2 Flag + * + * @retval flag staus: RESET or SET + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag) +{ + uint8_t status = 0; + + if((flag & 0x00F00000) != RESET ) + { + if((can->ERRSTS & (flag & 0x000FFFFF)) != RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + else if((flag & 0x01000000) != RESET ) + { + if((can->MSTS & (flag & 0x000FFFFF)) != RESET ) + { + status = SET; + } + else + { + status = RESET ; + } + } + else if((flag & 0x08000000) != RESET ) + { + if((can->TXSTS & (flag & 0x000FFFFF)) != RESET ) + { + status = SET; + } + else + { + status = RESET; + } + } + else if((flag & 0x02000000) != RESET ) + { + if((can->RXF0 & (flag & 0x000FFFFF)) != RESET ) + { + status = SET; + } + else + { + status = RESET; + } + } + else + { + if((can->RXF1 & (flag & 0x000FFFFF)) != RESET) + { + status = SET; + } + else + { + status = RESET; + } + } + return status; +} + +/*! + * @brief Clears the CAN's pending flags. + * + * @param can: Select the CAN peripheral. + * + * @param flag: specifies the CAN flag. + * This parameter can be one of the following values: + * @arg CAN_FLAG_LERRC : Last error record code Flag + * @arg CAN_FLAG_WUPI : Wake up Flag + * @arg CAN_FLAG_SLEEP : Sleep acknowledge Flag + * @arg CAN_FLAG_F0FULL: FIFO 0 Full Flag + * @arg CAN_FLAG_F0OVR : FIFO 0 Overrun Flag + * @arg CAN_FLAG_F1FULL: FIFO 1 Full Flag + * @arg CAN_FLAG_F1OVR : FIFO 1 Overrun Flag + * @arg CAN_FLAG_REQC0 : Request MailBox0 Flag + * @arg CAN_FLAG_REQC1 : Request MailBox1 Flag + * @arg CAN_FLAG_REQC2 : Request MailBox2 Flag + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag) +{ + uint32_t flagtmp = 0; + + /** ERRSTS register */ + if(flag == 0x30F00070) + { + can->ERRSTS = RESET; + } + else + { + flagtmp = flag & 0x000FFFFF; + if((flag & 0x02000000) != RESET) + { + can->RXF0 = flagtmp; + } + else if((flag & 0x04000000) != RESET) + { + can->RXF1 = flagtmp; + } + else if((flag & 0x08000000) != RESET) + { + can->TXSTS = flagtmp; + } + else + { + can->MSTS = flagtmp; + } + } +} + +/*! + * @brief Read whether the specified can interrupt has occurred or not. + * + * @param can: Select the CAN peripheral. + * + * @param flag: specifies the CAN interrupt sources + * This parameter can be one of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0MP : FIFO 0 message pending Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1MP : FIFO 1 message pending Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval status : SET or RESET + * + * @note CAN2 applies only to APM32F103xC device. + */ +uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag) +{ + uint8_t status = 0; + + if((can->INTEN & flag) != RESET) + { + switch (flag) + { + case CAN_INT_TXME: + status = can->TXSTS_B.REQCFLG0 | can->TXSTS_B.REQCFLG1 | can->TXSTS_B.REQCFLG2; + break; + case CAN_INT_F0MP: + status = can->RXF0_B.FMNUM0; + break; + case CAN_INT_F0FULL: + status = can->RXF0_B.FFULLFLG0; + break; + case CAN_INT_F0OVR: + status = can->RXF0_B.FOVRFLG0; + break; + case CAN_INT_F1MP: + status = can->RXF1_B.FMNUM1; + break; + case CAN_INT_F1FULL: + status = can->RXF1_B.FFULLFLG1; + break; + case CAN_INT_F1OVR: + status = can->RXF1_B.FOVRFLG1; + break; + case CAN_INT_WUP: + status = can->MSTS_B.WUPIFLG; + break; + case CAN_INT_SLEEP: + status = can->MSTS_B.SLEEPIFLG; + break; + case CAN_INT_ERRW: + status = can->ERRSTS_B.ERRWFLG; + break; + case CAN_INT_ERRP: + status = can->ERRSTS_B.ERRPFLG; + break; + case CAN_INT_BOF: + status = can->ERRSTS_B.BOFLG; + break; + case CAN_INT_LEC: + status = can->ERRSTS_B.LERRC; + break; + case CAN_INT_ERR: + status = can->MSTS_B.ERRIFLG; + break; + default: + status = RESET; + break; + } + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the can's interrupt flag. + * + * @param can: Select the CAN peripheral. + * + * @param flag: Interrupt pending bit to clear + * This parameter can be one of the following values: + * @arg CAN_INT_TXME : Transmit mailbox empty Interrupt + * @arg CAN_INT_F0FULL : FIFO 0 full Interrupt + * @arg CAN_INT_F0OVR : FIFO 0 overrun Interrupt + * @arg CAN_INT_F1FULL : FIFO 1 full Interrupt + * @arg CAN_INT_F1OVR : FIFO 1 overrun Interrupt + * @arg CAN_INT_ERRW : Error warning Interrupt + * @arg CAN_INT_ERRP : Error passive Interrupt + * @arg CAN_INT_BOF : Bus-off Interrupt + * @arg CAN_INT_LEC : Last error record code Interrupt + * @arg CAN_INT_ERR : Error Interrupt + * @arg CAN_INT_WUP : Wake-up Interrupt + * @arg CAN_INT_SLEEP : Sleep acknowledge Interrupt + * + * @retval None + * + * @note CAN2 applies only to APM32F103xC device. + */ +void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag) +{ + switch (flag) + { + case CAN_INT_TXME: + can->TXSTS_B.REQCFLG0 = BIT_SET; + can->TXSTS_B.REQCFLG1 = BIT_SET; + can->TXSTS_B.REQCFLG2 = BIT_SET; + break; + case CAN_INT_F0FULL: + can->RXF0_B.FFULLFLG0 = BIT_SET; + break; + case CAN_INT_F0OVR: + can->RXF0_B.FOVRFLG0 = BIT_SET; + break; + case CAN_INT_F1FULL: + can->RXF1_B.FFULLFLG1 = BIT_SET; + break; + case CAN_INT_F1OVR: + can->RXF1_B.FOVRFLG1 = BIT_SET; + break; + case CAN_INT_WUP: + can->MSTS_B.WUPIFLG = BIT_SET; + break; + case CAN_INT_SLEEP: + can->MSTS_B.SLEEPIFLG = BIT_SET; + break; + case CAN_INT_ERRW: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_ERRP: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_BOF: + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_LEC: + can->ERRSTS_B.LERRC = BIT_RESET; + can->MSTS_B.ERRIFLG = BIT_SET; + break; + case CAN_INT_ERR: + can->ERRSTS_B.LERRC = BIT_RESET; + can->MSTS_B.ERRIFLG = BIT_SET; + break; + default: + break; + } +} + +/**@} end of group CAN_Fuctions*/ +/**@} end of group CAN_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c new file mode 100644 index 0000000000..fd0d7b28a6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c @@ -0,0 +1,112 @@ +/*! + * @file apm32f10x_crc.c + * + * @brief This file provides all the CRC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_crc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset CRC data register. + * + * @param None + * + * @retval None + * + * @note + */ +void CRC_ResetDATA(void) +{ + CRC->CTRL_B.RST = BIT_SET; +} + +/*! + * @brief Calculate CRC of a 32bit data word. + * + * @param data: a data word to compute its CRC. + * This parameter can be a 32bit value: + * + * @retval A 32-bit CRC value + */ +uint32_t CRC_CalculateCRC(uint32_t data) +{ + CRC->DATA = data; + + return (CRC->DATA); +} + +/*! + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param buf: Pointer to the buffer containing the data to be computed. + * + * @param bufLen: The length of buffer which is computed. + * + * @retval A 32-bit CRC value + */ +uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen) +{ + while(bufLen--) + { + CRC->DATA = *buf++; + } + + return (CRC->DATA); +} + +/*! + * @brief Returns the current CRC value. + * + * @param None + * + * @retval A 32-bit CRC value + */ +uint32_t CRC_ReadCRC(void) +{ + return (CRC->DATA); +} + +/*! + * @brief Saves a 8bit data in the Independent Data register(INDATA). + * + * @param inData: a 8-bit value to be stored in the ID register + * + * @retval None + */ +void CRC_WriteIDRegister(uint8_t inData) +{ + CRC->INDATA = inData; +} + +/*! + * @brief Reads a 8-bit data saved in the Independent Data register(INDATA). + * + * @param None + * + * @retval a 8-bit value from the INDATA register + */ +uint8_t CRC_ReadIDRegister(void) +{ + return (CRC->INDATA); +} + +/**@} end of group CRC_Fuctions*/ +/**@} end of group CRC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c new file mode 100644 index 0000000000..e66cd77463 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c @@ -0,0 +1,393 @@ +/*! + * @file apm32f10x_dac.c + * + * @brief This file provides all the DAC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_dac.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset dac peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void DAC_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_DAC); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_DAC); +} + +/*! + * @brief Config the DAC peripheral according to the specified parameters in the configStruct + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @param configStruct: pointer to a DAC_ConfigStruct_T structure + * + * @retval None + */ +void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + tmp1 = DAC->CTRL; + + tmp1 &= ~(((uint32_t)0x00000FFE) << channel); + + tmp2 = (configStruct->trigger | configStruct->waveGeneration | configStruct->maskAmplitudeSelect | configStruct->outputBuffer); + tmp1 |= tmp2 << channel; + + DAC->CTRL = tmp1; +} + +/*! + * @brief Fills each DAC_ConfigStruct_T member with its default value + * + * @param configStruct: pointer to a DAC_ConfigStruct_T structure which will be initialized + * + * @retval None + */ +void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct) +{ + /* Initialize the DAC_Trigger member */ + configStruct->trigger = DAC_TRIGGER_NONE; + /* Initialize the DAC_WaveGeneration member */ + configStruct->waveGeneration = DAC_WAVE_GENERATION_NONE; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + configStruct->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1; + /* Initialize the DAC_OutputBuffer member */ + configStruct->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE; +} + +/*! + * @brief Enables the specified DAC peripheral + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_Enable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.ENCH1 = BIT_SET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.ENCH2 = BIT_SET; + } +} + +/*! + * @brief Disables the specified DAC peripheral + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_Disable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.ENCH1 = BIT_RESET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.ENCH2 = BIT_RESET; + } +} + + +/*! + * @brief Enables the specified DAC channel DMA request + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_DMA_Enable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAENCH1 = BIT_SET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.DMAENCH2 = BIT_SET; + } +} + +/*! + * @brief Disables the specified DAC channel DMA request + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_DMA_Disable(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->CTRL_B.DMAENCH1 = BIT_RESET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->CTRL_B.DMAENCH2 = BIT_RESET; + } +} + +/*! + * @brief Enables the selected DAC channel software trigger + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->SWTRG_B.SWTRG1 = BIT_SET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->SWTRG_B.SWTRG2 = BIT_SET; + } +} + +/*! + * @brief Disable the selected DAC channel software trigger + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval None + */ +void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel) +{ + if (channel == DAC_CHANNEL_1) + { + DAC->SWTRG_B.SWTRG1 = BIT_RESET; + } + else if (channel == DAC_CHANNEL_2) + { + DAC->SWTRG_B.SWTRG2 = BIT_RESET; + } +} +/*! + * @brief Enables simultaneously the two DAC channels software + * + * @param None + * + * @retval None + */ +void DAC_EnableDualSoftwareTrigger(void) +{ + DAC->SWTRG_B.SWTRG1 = BIT_SET; + DAC->SWTRG_B.SWTRG2 = BIT_SET; +} + +/*! + * @brief Disables simultaneously the two DAC channels software + * + * @param None + * + * @retval None + */ +void DAC_DisableDualSoftwareTrigger(void) +{ + DAC->SWTRG_B.SWTRG1 = BIT_RESET; + DAC->SWTRG_B.SWTRG2 = BIT_RESET; +} + +/*! + * @brief Enables the selected DAC channel wave generation + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @param wave: Select the wave + * This parameter can be one of the following values: + * @arg DAC_WAVE_GENERATION_NONE : no wave generation + * @arg DAC_WAVE_GENERATION_NOISE : Noise wave generation + * @arg DAC_WAVE_GENERATION_TRIANGLE : Triangle wave generation + * + * @retval None + */ +void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave) +{ + DAC->CTRL &= 0xFF3FFF3F; + DAC->CTRL |= wave << channel; +} + +/*! + * @brief Disables the selected DAC channel wave generation + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @param wave: Select the wave + * This parameter can be one of the following values: + * @arg DAC_WAVE_GENERATION_NONE : no wave generation + * @arg DAC_WAVE_GENERATION_NOISE : Noise wave generation + * @arg DAC_WAVE_GENERATION_TRIANGLE : Triangle wave generation + * + * @retval None + */ +void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave) +{ + DAC->CTRL &= ~(wave << channel); +} + +/*! + * @brief Set the specified data holding register value for DAC channel 1 + * + * @param align: DAC channel 1 data alignment + * This parameter can be one of the following values: + * @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data + * @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data + * @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data + * + * @param data: The data to be loaded in the selected data register. + * + * @retval None + */ +void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += 0x00000008 + align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = data; +} + +/*! + * @brief Set the specified data holding register value for DAC channel 2 + * + * @param align: DAC channel 2 data alignment + * This parameter can be one of the following values: + * @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data + * @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data + * @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data + * + * @param data: The data to be loaded in the selected data register. + * + * @retval None + */ +void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += 0x00000014 + align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = data; +} + +/*! + * @brief Set the specified data holding register value for dual DAC channel + * + * @param align: Dual DAC channel data alignment + * This parameter can be one of the following values: + * @arg DAC_ALIGN_12BIT_R : 12-bit right-aligned data + * @arg DAC_ALIGN_12BIT_L : 12-bit left-aligned data + * @arg DAC_ALIGN_8BIT_R : 8-bit right-aligned data + * + * @param data2: Data for channel2 to be loaded in the selected data register. + * + * @param data1: Data for channel1 to be loaded in the selected data register + * + * @retval None + */ +void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1) +{ + uint32_t data = 0, tmp = 0; + + /* Calculate and set dual DAC data holding register value */ + if (align == DAC_ALIGN_8BIT_R) + { + data = ((uint32_t)data2 << 8) | data1; + } + else + { + data = ((uint32_t)data2 << 16) | data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += 0x00000020 + align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/*! + * @brief Reads the specified DAC channel data output value. + * + * @param channel: Select the DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC channel 1 + * @arg DAC_CHANNEL_2 : DAC channel 2 + * + * @retval The data output value of the specified DAC channel. + */ +uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t) DAC_BASE ; + tmp += 0x0000002C + ((uint32_t)channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/**@} end of group DAC_Fuctions*/ +/**@} end of group DAC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c new file mode 100644 index 0000000000..985f9f215d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c @@ -0,0 +1,132 @@ +/*! + * @file apm32f10x_dbgmcu.c + * + * @brief This file provides all the DEBUG firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_dbgmcu.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DBGMCU_Driver DBGMCU Driver + @{ +*/ + +/** @addtogroup DBGMCU_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Returns the device identifier. + * + * @param None + * + * @retval Device identifier + */ +uint32_t DBGMCU_ReadDEVID(void) +{ + return(DBGMCU->IDCODE_B.EQR); +} + +/*! + * @brief Returns the device revision identifier. + * + * @param None + * + * @retval Device revision identifier + */ +uint32_t DBGMCU_ReadREVID(void) +{ + return(DBGMCU->IDCODE_B.WVR); +} + +/*! + * @brief Enable the specified peripheral and low power mode behavior + * when the MCU under Debug mode + * + * @param periph: Specifies the peripheral and low power mode + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP : Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP : Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY : Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDT_STOP : Debug IWDT stopped when Core is halted + * @arg DBGMCU_WWDT_STOP : Debug WWDT stopped when Core is halted + * @arg DBGMCU_TMR1_STOP : TMR1 counter stopped when Core is halted + * @arg DBGMCU_TMR2_STOP : TMR2 counter stopped when Core is halted + * @arg DBGMCU_TMR3_STOP : TMR3 counter stopped when Core is halted + * @arg DBGMCU_TMR4_STOP : TMR4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP : Debug CAN1 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TMR5_STOP : TMR5 counter stopped when Core is halted + * @arg DBGMCU_TMR6_STOP : TMR6 counter stopped when Core is halted + * @arg DBGMCU_TMR7_STOP : TMR7 counter stopped when Core is halted + * @arg DBGMCU_TMR8_STOP : TMR8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP : Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TMR15_STOP : TMR15 counter stopped when Core is halted + * @arg DBGMCU_TMR16_STOP : TMR16 counter stopped when Core is halted + * @arg DBGMCU_TMR17_STOP : TMR17 counter stopped when Core is halted + * @arg DBGMCU_TMR9_STOP : TMR9 counter stopped when Core is halted + * @arg DBGMCU_TMR10_STOP : TMR10 counter stopped when Core is halted + * @arg DBGMCU_TMR11_STOP : TMR11 counter stopped when Core is halted + * @arg DBGMCU_TMR12_STOP : TMR12 counter stopped when Core is halted + * @arg DBGMCU_TMR13_STOP : TMR13 counter stopped when Core is halted + * @arg DBGMCU_TMR14_STOP : TMR14 counter stopped when Core is halted + * + * @retval None + */ +void DBGMCU_Enable(uint32_t periph) +{ + DBGMCU->CFG |= periph; +} + +/*! + * @brief Enable the specified peripheral and low power mode behavior + * when the MCU under Debug mode + * + * @param periph: Specifies the peripheral and low power mode + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP : Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP : Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY : Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDT_STOP : Debug IWDT stopped when Core is halted + * @arg DBGMCU_WWDT_STOP : Debug WWDT stopped when Core is halted + * @arg DBGMCU_TMR1_STOP : TMR1 counter stopped when Core is halted + * @arg DBGMCU_TMR2_STOP : TMR2 counter stopped when Core is halted + * @arg DBGMCU_TMR3_STOP : TMR3 counter stopped when Core is halted + * @arg DBGMCU_TMR4_STOP : TMR4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP : Debug CAN1 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TMR5_STOP : TMR5 counter stopped when Core is halted + * @arg DBGMCU_TMR6_STOP : TMR6 counter stopped when Core is halted + * @arg DBGMCU_TMR7_STOP : TMR7 counter stopped when Core is halted + * @arg DBGMCU_TMR8_STOP : TMR8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP : Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TMR15_STOP : TMR15 counter stopped when Core is halted + * @arg DBGMCU_TMR16_STOP : TMR16 counter stopped when Core is halted + * @arg DBGMCU_TMR17_STOP : TMR17 counter stopped when Core is halted + * @arg DBGMCU_TMR9_STOP : TMR9 counter stopped when Core is halted + * @arg DBGMCU_TMR10_STOP : TMR10 counter stopped when Core is halted + * @arg DBGMCU_TMR11_STOP : TMR11 counter stopped when Core is halted + * @arg DBGMCU_TMR12_STOP : TMR12 counter stopped when Core is halted + * @arg DBGMCU_TMR13_STOP : TMR13 counter stopped when Core is halted + * @arg DBGMCU_TMR14_STOP : TMR14 counter stopped when Core is halted + * + * @retval None + */ +void DBGMCU_Disable(uint32_t periph) +{ + DBGMCU->CFG &= ~periph; +} + +/**@} end of group DBGMCU_Fuctions*/ +/**@} end of group DBGMCU_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c new file mode 100644 index 0000000000..0df9c93fa7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c @@ -0,0 +1,546 @@ +/*! + * @file apm32f10x_dma.c + * + * @brief This file provides all the DMA firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_dma.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMA_Driver DMA Driver + @{ +*/ + +/** @addtogroup DMA_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset specified DMA Channel registers to their default reset + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5). + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Reset(DMA_Channel_T *channel) +{ + channel->CHCFG_B.CHEN = BIT_RESET; + channel->CHCFG = 0; + channel->CHNDATA = 0; + channel->CHMADDR = 0; + channel->CHPADDR = 0; + + if(channel == DMA1_Channel1) + { + DMA1->INTFCLR |= 0xFFFFFFF0; + } + else if(channel == DMA1_Channel2) + { + DMA1->INTFCLR |= 0xFFFFFF0F; + } + else if(channel == DMA1_Channel3) + { + DMA1->INTFCLR |= 0xFFFFF0FF; + } + else if(channel == DMA1_Channel4) + { + DMA1->INTFCLR |= 0xFFFF0FFF; + } + else if(channel == DMA1_Channel5) + { + DMA1->INTFCLR |= 0xFFF0FFFF; + } + else if(channel == DMA1_Channel6) + { + DMA1->INTFCLR |= 0xFF0FFFFF; + } + else if(channel == DMA1_Channel7) + { + DMA1->INTFCLR |= 0xF0FFFFFF; + } + else if(channel == DMA2_Channel1) + { + DMA2->INTFCLR |= 0xFFFFFFF0; + } + else if(channel == DMA2_Channel2) + { + DMA2->INTFCLR |= 0xFFFFFF0F; + } + else if(channel == DMA2_Channel3) + { + DMA2->INTFCLR |= 0xFFFFF0FF; + } + else if(channel == DMA2_Channel4) + { + DMA2->INTFCLR |= 0xFFFF0FFF; + } + else if(channel == DMA2_Channel5) + { + DMA2->INTFCLR |= 0xFFF0FFFF; + } +} + +/*! + * @brief Configs specified DMA Channel through a structure. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param dmaConfig: Point to a DMA_Config_T structure + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig) +{ + channel->CHCFG_B.DIRCFG = dmaConfig->dir; + channel->CHCFG_B.CIRMODE = dmaConfig->loopMode; + channel->CHCFG_B.PERIMODE = dmaConfig->peripheralInc; + channel->CHCFG_B.MIMODE = dmaConfig->memoryInc; + channel->CHCFG_B.PERSIZE = dmaConfig->peripheralDataSize; + channel->CHCFG_B.MEMSIZE = dmaConfig->memoryDataSize; + channel->CHCFG_B.CHPL = dmaConfig->priority; + channel->CHCFG_B.M2MMODE = dmaConfig->M2M; + + channel->CHNDATA = dmaConfig->bufferSize; + channel->CHPADDR = dmaConfig->peripheralBaseAddr; + channel->CHMADDR = dmaConfig->memoryBaseAddr; +} + +/*! + * @brief Populate the structure with default values. + * + * @param dmaConfig: Point to a DMA_Config_T structure. + * + * @retval None + */ +void DMA_ConfigStructInit( DMA_Config_T* dmaConfig) +{ + dmaConfig->peripheralBaseAddr = 0; + dmaConfig->memoryBaseAddr = 0; + dmaConfig->dir = DMA_DIR_PERIPHERAL_SRC; + dmaConfig->bufferSize = 0; + dmaConfig->peripheralInc = DMA_PERIPHERAL_INC_DISABLE; + dmaConfig->memoryInc = DMA_MEMORY_INC_DISABLE; + dmaConfig->peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_BYTE; + dmaConfig->memoryDataSize = DMA_MEMORY_DATA_SIZE_BYTE; + dmaConfig->loopMode = DMA_MODE_NORMAL; + dmaConfig->priority = DMA_PRIORITY_LOW; + dmaConfig->M2M = DMA_M2MEN_DISABLE; +} + +/*! + * @brief Enable the specified DMA Channel + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Enable(DMA_Channel_T *channel) +{ + channel->CHCFG_B.CHEN = ENABLE; +} + +/*! + * @brief Disable the specified DMA Channel + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_Disable(DMA_Channel_T *channel) +{ + channel->CHCFG_B.CHEN = DISABLE; +} + +/*! + * @brief Configs the number of data units in the channel. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param dataNumber:The number of data units in the current DMA Channel transfer. + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber) +{ + channel->CHNDATA = dataNumber; +} + +/*! + * @brief Read the number of data units in the channel + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @retval The number of CHNDATA value + * + * @note DMA2 Channel only for APM32 High density devices. + */ +uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel) +{ + return channel->CHNDATA; +} + +/*! + * @brief Enables the specified DMA Channel interrupts. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param interrupt: DMA interrupts sources to selsct + * This parameter can be any combination of the following values: + * @arg DMA_INT_TC : All Transfer Complete Interrupt + * @arg DMA_INT_HT : Half Transfer Complete Interrupt + * @arg DMA_INT_TERR : Transfer Error Occur Interrupt + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) +{ + channel->CHCFG |= interrupt; +} + +/*! + * @brief Disable the specified DMA Channel interrupts. + * + * @param channel:DMA1_channelx(x can be from 1 to 7) or DMA2_channely(y can be from 1 to 5) + * + * @param interrupt: DMA interrupts sources to selsct + * This parameter can be any combination of the following values: + * @arg DMA_INT_TC : All Transfer Complete Interrupt + * @arg DMA_INT_HT : Half Transfer Complete Interrupt + * @arg DMA_INT_TERR : Transfer Error Occur Interrupt + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt) +{ + channel->CHCFG &= ~interrupt; +} + +/*! + * @brief Read whether the specifie DMA Channel flag is set or not. + * + * @param flag: the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag. + * @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag. + * @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag. + * + * @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag. + * @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag. + * @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag. + * @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag. + * @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag. + * @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag. + * @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag. + * @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag. + * @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag. + * @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag. + * + * @retval Flag State + * + * @note DMA2 Channel only for APM32 High density devices. + */ +uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag) +{ + if((flag & 0x10000000) != RESET ) + { + if((DMA2->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } + else + { + if((DMA1->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } +} + +/*! + * @brief Clears the specifie DMA Channel's flags. + * + * @param flag:the flag to Clear. + * This parameter can be any combination of the following values: + * @arg DMA1_FLAG_GINT1: DMA1 Channel 1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel 1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel 1 half transfer flag. + * @arg DMA1_FLAG_TERR1: DMA1 Channel 1 transfer error flag. + * @arg DMA1_FLAG_GINT2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TERR2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GINT3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TERR3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GINT4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TERR4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GINT5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TERR5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GINT6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TERR6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GINT7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TERR7: DMA1 Channel7 transfer error flag. + + * @arg DMA2_FLAG_GINT1: DMA2 Channel 1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel 1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel 1 half transfer flag. + * @arg DMA2_FLAG_TERR1: DMA2 Channel 1 transfer error flag. + * @arg DMA2_FLAG_GINT2: DMA2 Channel 2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel 2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel 2 half transfer flag. + * @arg DMA2_FLAG_TERR2: DMA2 Channel 2 transfer error flag. + * @arg DMA2_FLAG_GINT3: DMA2 Channel 3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel 3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel 3 half transfer flag. + * @arg DMA2_FLAG_TERR3: DMA2 Channel 3 transfer error flag. + * @arg DMA2_FLAG_GINT4: DMA2 Channel 4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel 4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel 4 half transfer flag. + * @arg DMA2_FLAG_TERR4: DMA2 Channel 4 transfer error flag. + * @arg DMA2_FLAG_GINT5: DMA2 Channel 5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel 5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel 5 half transfer flag. + * @arg DMA2_FLAG_TERR5: DMA2 Channel 5 transfer error flag. + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_ClearStatusFlag(uint32_t flag) +{ + if((flag & 0x10000000) != RESET) + { + DMA2->INTFCLR = flag; + } else + { + DMA1->INTFCLR = flag; + } +} + +/*! + * @brief Read whether the specified DMA Channel interrupts is set or not. + * + * @param interrupt: interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt. + * @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt. + * @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt. + * @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt. + * @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt. + * @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt. + * @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt. + * @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt. + + * @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt. + * @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt. + * @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt. + * @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt. + * @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt. + * @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt. + * + * @retval interrupt State + * + * @note DMA2 Channel only for APM32 High density devices. + */ +uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag) +{ + if((flag & 0x10000000) != RESET ) + { + if((DMA2->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } else + { + if((DMA1->INTSTS & flag ) != RESET ) + { + return SET ; + } else + { + return RESET ; + } + } +} +/*! + * @brief Clears the specified DMA Channel's interrupts. + * + * @param flag: the interrupt flag to Clear. + * This parameter can be any combination of the following values: + * @arg DMA1_INT_FLAG_GINT1 : DMA1 Channel 1 global interrupt. + * @arg DMA1_INT_FLAG_TC1 : DMA1 Channel 1 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT1 : DMA1 Channel 1 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR1 : DMA1 Channel 1 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT2 : DMA1 Channel2 global interrupt. + * @arg DMA1_INT_FLAG_TC2 : DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT2 : DMA1 Channel2 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR2 : DMA1 Channel2 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT3 : DMA1 Channel3 global interrupt. + * @arg DMA1_INT_FLAG_TC3 : DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT3 : DMA1 Channel3 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR3 : DMA1 Channel3 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT4 : DMA1 Channel4 global interrupt. + * @arg DMA1_INT_FLAG_TC4 : DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT4 : DMA1 Channel4 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR4 : DMA1 Channel4 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT5 : DMA1 Channel5 global interrupt. + * @arg DMA1_INT_FLAG_TC5 DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT5 DMA1 Channel5 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR5 : DMA1 Channel5 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT6 : DMA1 Channel6 global interrupt. + * @arg DMA1_INT_FLAG_TC6 : DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT6 : DMA1 Channel6 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR6 : DMA1 Channel6 transfer error interrupt. + * @arg DMA1_INT_FLAG_GINT7 : DMA1 Channel7 global interrupt. + * @arg DMA1_INT_FLAG_TC7 : DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_INT_FLAG_HT7 : DMA1 Channel7 half transfer interrupt. + * @arg DMA1_INT_FLAG_TERR7 : DMA1 Channel7 transfer error interrupt. + + * @arg DMA2_INT_FLAG_GINT1 : DMA2 Channel 1 global interrupt. + * @arg DMA2_INT_FLAG_TC1 : DMA2 Channel 1 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT1 : DMA2 Channel 1 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR1 : DMA2 Channel 1 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT2 : DMA2 Channel 2 global interrupt. + * @arg DMA2_INT_FLAG_TC2 : DMA2 Channel 2 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT2 : DMA2 Channel 2 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR2 : DMA2 Channel 2 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT3 : DMA2 Channel 3 global interrupt. + * @arg DMA2_INT_FLAG_TC3 : DMA2 Channel 3 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT3 : DMA2 Channel 3 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR3 : DMA2 Channel 3 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT4 : DMA2 Channel 4 global interrupt. + * @arg DMA2_INT_FLAG_TC4 : DMA2 Channel 4 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT4 : DMA2 Channel 4 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR4 : DMA2 Channel 4 transfer error interrupt. + * @arg DMA2_INT_FLAG_GINT5 : DMA2 Channel 5 global interrupt. + * @arg DMA2_INT_FLAG_TC5 : DMA2 Channel 5 transfer complete interrupt. + * @arg DMA2_INT_FLAG_HT5 : DMA2 Channel 5 half transfer interrupt. + * @arg DMA2_INT_FLAG_TERR5 : DMA2 Channel 5 transfer error interrupt. + * + * @retval None + * + * @note DMA2 Channel only for APM32 High density devices. + */ +void DMA_ClearIntFlag(uint32_t flag) +{ + if((flag & 0x10000000) != RESET) + { + DMA2->INTFCLR = flag; + } else + { + DMA1->INTFCLR = flag; + } +} + +/**@} end of group DMA_Fuctions*/ +/**@} end of group DMA_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c new file mode 100644 index 0000000000..619550794f --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c @@ -0,0 +1,409 @@ +/*! + * @file apm32f10x_dmc.c + * + * @brief This file contains all the functions for the DMC controler peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#include "apm32f10x_dmc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup DMC_Driver DMC Driver + @{ +*/ + +/** @addtogroup DMC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief DMC controler configuration + * + * @param dmcConfig: pointer to a DMC_Config_T structure + * + * @retval None + */ +void DMC_Config(DMC_Config_T * dmcConfig) +{ + DMC->SW_B.MCSW = 1; + while(!DMC->CTRL1_B.INIT); + + DMC->CFG_B.BAWCFG = dmcConfig->bankWidth; + DMC->CFG_B.RAWCFG = dmcConfig->rowWidth; + DMC->CFG_B.CAWCFG = dmcConfig->colWidth; + + DMC->MASK_B.MSIZESEL = dmcConfig->memorySize; + DMC->CTRL2_B.CPHACFG = dmcConfig->clkPhase; + + DMC_ConfigTiming(&dmcConfig->timing); + + DMC->CTRL1_B.MODESET = 1; + while(!DMC->CTRL1_B.MODESET); + + DMC->CTRL2_B.RDDEN = 1; + DMC->CTRL2_B.RDDCFG = 7; +} + +/*! + * @brief Fills each dmcConfig member with its default value + * + * @param dmcConfig: pointer to a DMC_Config_T structure + * + * @retval None + */ +void DMC_ConfigStructInit(DMC_Config_T * dmcConfig) +{ + dmcConfig->bankWidth = DMC_BANK_WIDTH_2; + dmcConfig->clkPhase = DMC_CLK_PHASE_REVERSE; + dmcConfig->colWidth = DMC_COL_WIDTH_10; + dmcConfig->rowWidth = DMC_ROW_WIDTH_13; + dmcConfig->memorySize = DMC_MEMORY_SIZE_8MB; + + DMC_ConfigTimingStructInit(&dmcConfig->timing); +} + +/*! + * @brief Timing configuration + * + * @param timingConfig: pointer to a DMC_TimingConfig_T structure + * + * @retval None + */ +void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig) +{ + DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS; + DMC->TIM0_B.DTIMSEL = timingConfig->tRCD; + DMC->TIM0_B.PCPSEL = timingConfig->tRP; + DMC->TIM0_B.WRTIMSEL = timingConfig->tWR; + DMC->TIM0_B.ARPSEL = timingConfig->tARP; + DMC->TIM0_B.ATACP = timingConfig->tCMD; + + DMC->TIM0_B.CASLSEL0 = timingConfig->latencyCAS & 0x03; + DMC->TIM0_B.ECASLSEL1 = (timingConfig->latencyCAS >> 2) & 0x01; + + DMC->TIM0_B.XSR0 = timingConfig->tXSR & 0X0F; + DMC->TIM0_B.EXSR1 = (timingConfig->tXSR >> 4) & 0X1F; + + DMC->REF_B.RCYCCFG = timingConfig->tRFP; +} + +/*! + * @brief Fills each config member with its default value + * + * @param timingConfig: pointer to a DMC_TimingConfig_T structure + * + * @retval None + */ +void DMC_ConfigTimingStructInit(DMC_TimingConfig_T * timingConfig) +{ + timingConfig->latencyCAS = DMC_CAS_LATENCY_3; + timingConfig->tARP = DMC_AUTO_REFRESH_10; + timingConfig->tRAS = DMC_RAS_MINIMUM_5; + timingConfig->tCMD = DMC_ATA_CMD_7; + timingConfig->tRCD = DMC_DELAY_TIME_2; + timingConfig->tRP = DMC_PRECHARGE_2; + timingConfig->tWR = DMC_NEXT_PRECHARGE_2; + timingConfig->tXSR = 6; + timingConfig->tRFP = 0xC3; +} + +/*! + * @brief Set number of bank bits + * + * @param bankWidth: Specifies the bank bits number + * This parameter can be one of the following values: + * @arg DMC_BANK_WIDTH_1 + * @arg DMC_BANK_WIDTH_2 + * @retval None + */ +void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth) +{ + DMC->CFG_B.BAWCFG = bankWidth; +} + +/*! + * @brief Set address bus width + * + * @param rowWidth: Specifies the row address bits number + * This parameter can be one of the following values: + * @arg DMC_ROW_WIDTH_11 + * @arg DMC_ROW_WIDTH_12 + * @arg DMC_ROW_WIDTH_13 + * @arg DMC_ROW_WIDTH_14 + * @arg DMC_ROW_WIDTH_15 + * @arg DMC_ROW_WIDTH_16 + * @param colWidth: Specifies the column address bits number + * This parameter can be one of the following values: + * @arg DMC_COL_WIDTH_8 + * @arg DMC_COL_WIDTH_9 + * @arg DMC_COL_WIDTH_10 + * @arg DMC_COL_WIDTH_11 + * @arg DMC_COL_WIDTH_12 + * @arg DMC_COL_WIDTH_13 + * @arg DMC_COL_WIDTH_14 + * @arg DMC_COL_WIDTH_15 + * @retval None + */ +void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth) +{ + DMC->CFG_B.RAWCFG = rowWidth; + DMC->CFG_B.CAWCFG = colWidth; +} + +/*! + * @brief Set stable time after power up + * + * @param stableTime: Numper of the clock, can be 0x0000 to 0xFFFF + * + * @retval None + */ +void DMC_ConfigStableTimePowerup(uint16_t stableTime) +{ + DMC->TIM1_B.STBTIM = stableTime; +} + +/*! + * @brief Number of auto-refreshes during initialization + * + * @param num: Number of auto-refreshes can 1 to 16 + * This parameter can be one of the following values: + * @arg DMC_AUTO_REFRESH_1 + * @arg DMC_AUTO_REFRESH_2 + * ...... + * @arg DMC_AUTO_REFRESH_15 + * @arg DMC_AUTO_REFRESH_16 + * + * @retval None + */ +void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num) +{ + DMC->TIM1_B.ARNUMCFG = num; +} + +/*! + * @brief Number of DMC internal banks to be open at any time; + * + * @param num: Number of banks can 1 to 16 + * This parameter can be one of the following values: + * @arg DMC_BANK_NUMBER_1 + * @arg DMC_BANK_NUMBER_2 + * ...... + * @arg DMC_BANK_NUMBER_15 + * @arg DMC_BANK_NUMBER_16 + * @retval None + */ +void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num) +{ + DMC->CTRL1_B.BANKNUMCFG = num; +} + +/*! + * @brief Read self-refresh status + * + * @param None + * + * @retval The status of self-refresh (SET or RESET) + */ +uint8_t DMC_ReadSelfRefreshStatus(void) +{ + uint8_t ret; + + ret = DMC->CTRL1_B.SRMFLG ? SET : RESET; + + return ret; +} + +/*! + * @brief Set update mode bit + * + * @param None + * + * @retval None + */ +void DMC_EnableUpdateMode(void) +{ + DMC->CTRL1_B.MODESET = 1; +} + +/*! + * @brief Enter power down mode + * + * @param None + * + * @retval None + */ +void DMC_EnterPowerdownMode(void) +{ + DMC->CTRL1_B.PDMEN = 1; +} + +/*! + * @brief Exit self-refresh mode + * + * @param None + * + * @retval None + */ +void DMC_EixtSlefRefreshMode(void) +{ + DMC->CTRL1_B.SRMEN = 0; +} + +/*! + * @brief Enter self-refresh mode + * + * @param None + * + * @retval None + */ +void DMC_EnterSlefRefreshMode(void) +{ + DMC->CTRL1_B.SRMEN = 1; +} + +/*! + * @brief Init DMC + * + * @param None + * + * @retval None + */ +void DMC_EnableInit(void) +{ + DMC->CTRL1_B.INIT = 1; +} + +/*! + * @brief Set refresh type before enter self-refresh + * + * @param refresh: Specifies the refresh type + * The parameter can be one of following values: + * @arg DMC_REFRESH_ROW_ONE: Refresh one row + * @arg DMC_REFRESH_ROW_ALL: Refresh all row + * + * @retval None + */ +void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh) +{ + DMC->CTRL1_B.FRBSREN = refresh; +} + +/*! + * @brief Set refresh type after exit self-refresh + * + * @param refresh: Specifies the refresh type + * The parameter can be one of following values: + * @arg DMC_REFRESH_ROW_ONE: Refresh one row + * @arg DMC_REFRESH_ROW_ALL: Refresh all row + * + * @retval None + */ +void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh) +{ + DMC->CTRL1_B.FRASREN = refresh; +} + +/*! + * @brief Config precharge type + * + * @param precharge: Specifies the precharge type + * The parameter can be one of following values: + * @arg DMC_PRECHARGE_IM: Immediate precharge + * @arg DMC_PRECHARGE_DELAY: Delayed precharge + * + * @retval None + */ +void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge) +{ + DMC->CTRL1_B.PCACFG = precharge; +} + +/*! + * @brief Config refresh period + * + * @param period: Specifies the refresh period, can be 0x0000 to 0xFFFF + * + * @retval None + */ +void DMC_ConfigRefreshPeriod(uint16_t period) +{ + DMC->REF_B.RCYCCFG = period; +} + +/*! + * @brief Config memory size + * + * @param memorySize: Specifies memory size + * The parameter can be one of following values: + * @arg DMC_MEMORY_SIZE_0: Memory size is no link + * @arg DMC_MEMORY_SIZE_64KB: Memory size is 64KB + * @arg DMC_MEMORY_SIZE_128KB: Memory size is 128KB + * @arg DMC_MEMORY_SIZE_256KB: Memory size is 256KB + * @arg DMC_MEMORY_SIZE_512KB: Memory size is 512KB + * @arg DMC_MEMORY_SIZE_1MB: Memory size is 1MB + * @arg DMC_MEMORY_SIZE_2MB: Memory size is 2MB + * @arg DMC_MEMORY_SIZE_4MB: Memory size is 4MB + * @arg DMC_MEMORY_SIZE_8MB: Memory size is 8MB + * @arg DMC_MEMORY_SIZE_16MB: Memory size is 16MB + * @arg DMC_MEMORY_SIZE_32MB: Memory size is 32MB + * @arg DMC_MEMORY_SIZE_64MB: Memory size is 64MB + * @arg DMC_MEMORY_SIZE_128MB: Memory size is 128MB + * @arg DMC_MEMORY_SIZE_256MB: Memory size is 256MB + * + * @retval None + */ +void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize) +{ + DMC->MASK_B.MSIZESEL = memorySize; +} + +/*! + * @brief Enable DMC controler + * + * @param None + * + * @retval None + */ +void DMC_Enable(void) +{ + DMC->SW_B.MCSW = 1; +} + +/*! + * @brief Disable DMC controler + * + * @param None + * + * @retval None + */ +void DMC_Disable(void) +{ + DMC->SW_B.MCSW = 0; +} + +/*! + * @brief Set DMC clock phase + * + * @param clkPhase: Specifies clock phase + * The parameter can be one of following values: + * @arg DMC_CLK_PHASE_NORMAL: Clock phase is normal + * @arg DMC_CLK_PHASE_REVERSE: Clock phase is reverse + * + * @retval None + * + */ +void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase) +{ + DMC->CTRL2_B.CPHACFG = clkPhase; +} + +/**@} end of group DMC_Fuctions*/ +/**@} end of group DMC_Driver */ +/**@} end of group Peripherals_Library*/ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c new file mode 100644 index 0000000000..cc0eafe579 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c @@ -0,0 +1,176 @@ +/*! + * @file apm32f10x_eint.c + * + * @brief This file provides all the EINT firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_eint.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EINT_Driver EINT Driver + @{ +*/ + +/** @addtogroup EINT_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the EINT peripheral registers to their default reset values. + * + * @param None + * + * @retval None + */ +void EINT_Reset(void) +{ + EINT->IMASK = 0x00000000; + EINT->EMASK = 0x00000000; + EINT->RTEN = 0x00000000; + EINT->FTEN = 0x00000000; + EINT->IPEND = 0x000FFFFF; +} + +/*! + * @brief Configure the EINT + * + * @param eintConfig: pointer to a EINT_Config_T structure. + * + * @retval None + */ +void EINT_Config(EINT_Config_T* eintConfig) +{ + uint32_t temp = 0; + temp = (uint32_t)EINT_BASE; + + if(eintConfig->lineCmd != DISABLE) + { + EINT->IMASK &= ~eintConfig->line; + EINT->EMASK &= ~eintConfig->line; + + temp += eintConfig->mode; + *(__IOM uint32_t *) temp |= eintConfig->line; + + EINT->RTEN &= ~eintConfig->line; + EINT->FTEN &= ~eintConfig->line; + + if (eintConfig->trigger == EINT_TRIGGER_RISING_FALLING) + { + EINT->RTEN |= eintConfig->line; + EINT->FTEN |= eintConfig->line; + } + else + { + temp = (uint32_t)EINT_BASE; + temp += eintConfig->trigger; + + *(__IOM uint32_t *) temp |= eintConfig->line; + } + } + else + { + temp += eintConfig->mode; + + *(__IOM uint32_t *) temp &= ~eintConfig->line; + } +} + +/*! + * @brief Select Software interrupt on EINT line + * + * @param line: specifies the EINT lines. + * This parameter can be any combination of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +void EINT_SelectSWInterrupt(uint32_t line) +{ + EINT->SWINTE |= line; +} + +/*! + * @brief Read the specified EINT_Line flag + * + * @param line: Select the EINT_Line. + * This parameter can be one of EINT_LINE_T(can be from 0 to 18) + * + * @retval status: The new state of flag (SET or RESET) + */ +uint8_t EINT_ReadStatusFlag(EINT_LINE_T line) +{ + uint8_t status = RESET; + + if((EINT->IPEND & line) != (uint32_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the EINT_Line pending bits + * + * @param line: Select the EINT_Line. + * This parameter can be any combination of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +void EINT_ClearStatusFlag(uint32_t line) +{ + EINT->IPEND = line; +} + +/*! + * @brief Read the specified EINT_Line Interrupt Flag. + * + * @param line: Select the EINT_Line. + * This parameter can be one of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +uint8_t EINT_ReadIntFlag(EINT_LINE_T line) +{ + uint8_t status = RESET; + uint32_t enablestatus = 0; + + enablestatus = EINT->IMASK & line; + + if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + +/*! + * @brief Clears the EINT_Line pending bits + * + * @param line: Select the EINT_Line + * This parameter can be any combination of EINT_LINE_T(can be from 0 to 18) + * + * @retval None + */ +void EINT_ClearIntFlag(uint32_t line) +{ + EINT->IPEND = line; +} + +/**@} end of group EINT_Fuctions*/ +/**@} end of group EINT_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c new file mode 100644 index 0000000000..8d79d213d8 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c @@ -0,0 +1,735 @@ +/*! + * @file apm32f10x_emmc.c + * + * @brief This file provides all the EMMC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_emmc.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup EMMC_Driver EMMC Driver + @{ +*/ + +/** @addtogroup EMMC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Rest the EMMMC NOR/SRAM Banks registers + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1 + * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2 + * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3 + * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank) +{ + /** EMMC_BANK1_NORSRAM_1 */ + if(bank == EMMC_BANK1_NORSRAM_1) + { + EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB; + } + /** EMMC_BANK1_NORSRAM_2, EMMC_BANK1_NORSRAM_3 or EMMC_BANK1_NORSRAM_4 */ + else + { + EMMC_Bank1->SNCTRL_T[bank] = 0x000030D2; + } + EMMC_Bank1->SNCTRL_T[bank + 1] = 0x0FFFFFFF; + EMMC_Bank1E->WRTTIM[bank] = 0x0FFFFFFF; +} + +/*! + * @brief Rest the EMMMC NAND Banks registers + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_ResetNAND(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + /** Set the EMMC_Bank2 registers to their reset values */ + EMMC_Bank2->CTRL2 = 0x00000018; + EMMC_Bank2->STSINT2 = 0x00000040; + EMMC_Bank2->CMSTIM2 = 0xFCFCFCFC; + EMMC_Bank2->AMSTIM2 = 0xFCFCFCFC; + } + /** EMMC_BANK3_NAND */ + else + { + /* Set the EMMC_Bank3 registers to their reset values */ + EMMC_Bank3->CTRL3 = 0x00000018; + EMMC_Bank3->STSINT3 = 0x00000040; + EMMC_Bank3->CMSTIM3 = 0xFCFCFCFC; + EMMC_Bank3->AMSTIM3 = 0xFCFCFCFC; + } +} + +/*! + * @brief Reset the EMMMC PCCARD Banks registers + * + * @param None + * + * @retval None + */ +void EMMC_ResetPCCard(void) +{ + /** Set the EMMC_Bank4 registers to their reset values */ + EMMC_Bank4->CTRL4 = 0x00000018; + EMMC_Bank4->STSINT4 = 0x00000040; + EMMC_Bank4->CMSTIM4 = 0xFCFCFCFC; + EMMC_Bank4->AMSTIM4 = 0xFCFCFCFC; + EMMC_Bank4->IOSTIM4 = 0xFCFCFCFC; +} + +/*! + * @brief Config the EMMC NOR/SRAM Banks according to the specified parameters in the emmcNORSRAMConfig. + * + * @param emmcNORSRAMConfig: Point to a EMMC_NORSRAMConfig_T structure + * + * @retval None + */ +void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) +{ + /* Bank1 NOR/SRAM control register configuration */ + EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] = + (uint32_t)emmcNORSRAMConfig->dataAddressMux | + emmcNORSRAMConfig->memoryType | + emmcNORSRAMConfig->memoryDataWidth | + emmcNORSRAMConfig->burstAcceesMode | + emmcNORSRAMConfig->asynchronousWait | + emmcNORSRAMConfig->waitSignalPolarity | + emmcNORSRAMConfig->wrapMode | + emmcNORSRAMConfig->waitSignalActive | + emmcNORSRAMConfig->writeOperation | + emmcNORSRAMConfig->waiteSignal | + emmcNORSRAMConfig->extendedMode | + emmcNORSRAMConfig->writeBurst; + + if(emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR) + { + EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040; + } + + /* Bank1 NOR/SRAM timing register configuration */ + EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank + 1] = + (uint32_t)emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime | + (emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) | + (emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime << 8) | + (emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime << 16) | + (emmcNORSRAMConfig->readWriteTimingStruct->clockDivision << 20) | + (emmcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) | + emmcNORSRAMConfig->readWriteTimingStruct->accessMode; + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE) + { + EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] = + (uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime | + (emmcNORSRAMConfig->writeTimingStruct->addressHodeTime << 4) | + (emmcNORSRAMConfig->writeTimingStruct->dataSetupTime << 8) | + (emmcNORSRAMConfig->writeTimingStruct->clockDivision << 20) | + (emmcNORSRAMConfig->writeTimingStruct->dataLatency << 24) | + emmcNORSRAMConfig->writeTimingStruct->accessMode; + } + else + { + EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] = 0x0FFFFFFF; + } +} + +/*! + * @brief Config the EMMC NAND Banks according to the specified parameters in the emmcNANDConfig. + * + * @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Set the tmppcr value according to EMMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)emmcNANDConfig->waitFeature | 0x00000008 | + emmcNANDConfig->memoryDataWidth | + emmcNANDConfig->ECC | + emmcNANDConfig->ECCPageSize | + (emmcNANDConfig->TCLRSetupTime << 9) | + (emmcNANDConfig->TARSetupTime << 13); + + /* Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)emmcNANDConfig->commonSpaceTimingStruct->setupTime | + (emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) | + (emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) | + (emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24); + + /* Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)emmcNANDConfig->attributeSpaceTimingStruct->setupTime | + (emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | + (emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | + (emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); + + if(emmcNANDConfig->bank == EMMC_BANK2_NAND) + { + /* EMMC_BANK2_NAND registers configuration */ + EMMC_Bank2->CTRL2 = tmppcr; + EMMC_Bank2->CMSTIM2 = tmppmem; + EMMC_Bank2->AMSTIM2 = tmppatt; + } + else + { + /* EMMC_BANK3_NAND registers configuration */ + EMMC_Bank3->CTRL3 = tmppcr; + EMMC_Bank3->CMSTIM3 = tmppmem; + EMMC_Bank3->AMSTIM3 = tmppatt; + } + +} + +/*! + * @brief Config the EMMC PCCARD according to the specified parameters in the emmcPCCardConfig. + * + * @param emmcPCCardConfig: Point to a EMMC_PCCARDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig) +{ + /* Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */ + EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT | + (emmcPCCardConfig->TCLRSetupTime << 9) | + (emmcPCCardConfig->TARSetupTime << 13); + + /* Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */ + EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime | + (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24); + + /* Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */ + EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime | + (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24); + + /* Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */ + EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime | + (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) | + (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) | + (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24); +} + +/*! + * @brief Fills each emmcNORSRAMConfig member with its default value. + * + * @param emmcNORSRAMConfig : Point to a EMMC_NORSRAMConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig) +{ + /* Reset NOR/SRAM Init structure parameters values */ + emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1; + emmcNORSRAMConfig->dataAddressMux = EMMC_DATA_ADDRESS_MUX_ENABLE; + emmcNORSRAMConfig->memoryType = EMMC_MEMORY_TYPE_SRAM; + emmcNORSRAMConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT; + emmcNORSRAMConfig->burstAcceesMode = EMMC_BURST_ACCESS_MODE_DISABLE; + emmcNORSRAMConfig->asynchronousWait = EMMC_ASYNCHRONOUS_WAIT_DISABLE; + emmcNORSRAMConfig->waitSignalPolarity = EMMC_WAIT_SIGNAL_POLARITY_LOW; + emmcNORSRAMConfig->wrapMode = EMMC_WRAP_MODE_DISABLE; + emmcNORSRAMConfig->waitSignalActive = EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT; + emmcNORSRAMConfig->writeOperation = EMMC_WRITE_OPERATION_ENABLE; + emmcNORSRAMConfig->waiteSignal = EMMC_WAITE_SIGNAL_ENABLE; + emmcNORSRAMConfig->extendedMode = EMMC_EXTENDEN_MODE_DISABLE; + emmcNORSRAMConfig->writeBurst = EMMC_WRITE_BURST_DISABLE; + emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF; + emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF; + emmcNORSRAMConfig->readWriteTimingStruct->accessMode = EMMC_ACCESS_MODE_A; + emmcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF; + emmcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF; + emmcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF; + emmcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF; + emmcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF; + emmcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF; + emmcNORSRAMConfig->writeTimingStruct->accessMode = EMMC_ACCESS_MODE_A; + +} + +/*! + * @brief Fills each emmcNANDConfig member with its default value. + * + * @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig) +{ + /* Reset NAND Init structure parameters values */ + emmcNANDConfig->bank = EMMC_BANK2_NAND; + emmcNANDConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE; + emmcNANDConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT; + emmcNANDConfig->ECC = EMMC_ECC_DISABLE; + emmcNANDConfig->ECCPageSize = EMMC_ECC_PAGE_SIZE_BYTE_256; + emmcNANDConfig->TCLRSetupTime = 0x0; + emmcNANDConfig->TARSetupTime = 0x0; + emmcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC; + emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC; + emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC; + emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC; + emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC; +} + +/*! + * @brief Fills each emmcPCCardConfig member with its default value. + * + * @param emmcPCCardConfig : Point to a EMMC_PCCARDConfig_T structure. + * + * @retval None + */ +void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig) +{ + /* Reset PCCARD Init structure parameters values */ + emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE; + emmcPCCardConfig->TCLRSetupTime = 0x0; + emmcPCCardConfig->TARSetupTime = 0x0; + emmcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC; + emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC; + emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC; + emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC; + emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC; + emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC; +} + +/*! + * @brief Enables the specified NOR/SRAM Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1 + * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2 + * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3 + * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank) +{ + EMMC_Bank1->SNCTRL_T[bank] |= 0x00000001; +} + +/*! + * @brief Disbles the specified NOR/SRAM Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1 + * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2 + * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3 + * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4 + * + * @retval None + */ +void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank) +{ + EMMC_Bank1->SNCTRL_T[bank] &= 0x000FFFFE; +} + +/*! + * @brief Enables the specified NAND Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_EnableNAND(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET; + } + else + { + EMMC_Bank3->CTRL3_B.MBKEN = BIT_SET; + } +} + +/*! + * @brief Disbles the specified NAND Memory Bank. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_DisableNAND(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET; + } + else + { + EMMC_Bank3->CTRL3_B.MBKEN = BIT_RESET; + } +} + +/*! + * @brief Enables the specified PC Card Memory Bank. + * + * @param None + * + * @retval None + */ +void EMMC_EnablePCCARD(void) +{ + EMMC_Bank4->CTRL4_B.MBKEN = BIT_SET; +} + +/*! + * @brief Disables the specified PC Card Memory Bank. + * + * @param None + * + * @retval None + */ +void EMMC_DisablePCCARD(void) +{ + EMMC_Bank4->CTRL4_B.MBKEN = BIT_RESET; +} + +/*! + * @brief Enbles the EMMC NAND ECC feature. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + */ +void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2 |= 0x00000040; + } + else + { + EMMC_Bank3->CTRL3 |= 0x00000040; + } +} + +/*! + * @brief Disbles or disables the EMMC NAND ECC feature. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval None + * + * @note + */ +void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->CTRL2 &= 0x000FFFBF; + } + else + { + EMMC_Bank3->CTRL3 &= 0x000FFFBF; + } +} + +/*! + * @brief Read the error correction code register value. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND + * + * @retval The value of Error Correction Code (ECC). + */ +uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank) +{ + uint32_t eccval = 0x00000000; + + if(bank == EMMC_BANK2_NAND) + { + eccval = EMMC_Bank2->ECCRS2; + } + else + { + eccval = EMMC_Bank3->ECCRS3; + } + return eccval; +} + +/*! + * @brief Enables the specified EMMC interrupts. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 |= interrupt; + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 |= interrupt; + } + else + { + EMMC_Bank4->STSINT4 |= interrupt; + } +} + +/*! + * @brief Enables the specified EMMC interrupts. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 &= ~interrupt; + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 &= ~interrupt; + } + else + { + EMMC_Bank4->STSINT4 &= ~interrupt; + } +} + +/*! + * @brief Read the status of specified EMMC flag. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param flag: Select the EMMC interrupt sources. + * This parameter can be one of the following values: + * @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag. + * @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag. + * @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag. + * @arg EMMC_FLAG_FIFO_EMPTY : FIFO empty Flag. + * + * @retval SET or RESET + * + * @note + */ +uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag) +{ + uint32_t tmpsr = 0x00000000; + + if(bank == EMMC_BANK2_NAND) + { + tmpsr = EMMC_Bank2->STSINT2; + } + else if(bank == EMMC_BANK3_NAND) + { + tmpsr = EMMC_Bank3->STSINT3; + } + else + { + tmpsr = EMMC_Bank4->STSINT4; + } + /* Get the flag status */ + if((tmpsr & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the EMMC's pending flags. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param flag: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag. + * @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag. + * @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag. + * + * @retval None + */ +void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 &= ~flag; + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 &= ~flag; + } + else + { + EMMC_Bank4->STSINT4 &= ~flag; + } +} + +/*! + * @brief Read the specified EMMC interrupt has occurred or not. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt source. + * This parameter can be one of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval The status of specified EMMC interrupt source. + */ +uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag) +{ + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + if(bank == EMMC_BANK2_NAND) + { + tmpsr = EMMC_Bank2->STSINT2; + } + else if(bank == EMMC_BANK3_NAND) + { + tmpsr = EMMC_Bank3->STSINT3; + } + else + { + tmpsr = EMMC_Bank4->STSINT4; + } + + itstatus = tmpsr & flag; + itenable = tmpsr & (flag >> 3); + + if((itstatus != RESET) && (itenable != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the EMMC's interrupt Flag. + * + * @param bank: Selects the EMMMC Bank. + * The parameter can be one of following values: + * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND + * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND + * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD + * + * @param interrupt: Select the EMMC interrupt sources. + * This parameter can be any combination of the following values: + * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt. + * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt. + * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt. + * + * @retval None + */ +void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag) +{ + if(bank == EMMC_BANK2_NAND) + { + EMMC_Bank2->STSINT2 &= ~(flag >> 3); + } + else if(bank == EMMC_BANK3_NAND) + { + EMMC_Bank3->STSINT3 &= ~(flag >> 3); + } + else + { + EMMC_Bank4->STSINT4 &= ~(flag >> 3); + } +} + +/**@} end of group EMMC_Fuctions*/ +/**@} end of group EMMC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c new file mode 100644 index 0000000000..357ecf637a --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c @@ -0,0 +1,753 @@ +/*! + * @file apm32f10x_fmc.c + * + * @brief This file provides all the FMC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_fmc.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Configs the code latency value. + * + * @param latency: the FMC Latency value. + * + * @retval None + */ +void FMC_ConfigLatency(FMC_LATENCY_T latency) +{ + FMC->CTRL1_B.WS = latency; +} + +/*! + * @brief Enables the Half cycle flash access. + * + * @param None + * + * @retval None + */ +void FMC_EnableHalfCycleAccess(void) +{ + FMC->CTRL1_B.HCAEN = BIT_SET; +} + +/*! + * @brief Disable the Half cycle flash access. + * + * @param None + * + * @retval None + */ +void FMC_DisableHalfCycleAccess(void) +{ + FMC->CTRL1_B.HCAEN = BIT_RESET; +} + +/*! + * @brief Enables the Prefetch Buffer. + * + * @param None + * + * @retval None + */ +void FMC_EnablePrefetchBuffer(void) +{ + FMC->CTRL1_B.PBEN = ENABLE; +} + +/*! + * @brief Disables the Prefetch Buffer. + * + * @param None + * + * @retval None + */ +void FMC_DisablePrefetchBuffer(void) +{ + FMC->CTRL1_B.PBEN = DISABLE; +} + +/*! + * @brief Unlocks the FMC Program Erase Controller + * + * @param None + * + * @retval None + */ +void FMC_Unlock(void) +{ + FMC->KEY = 0x45670123; + FMC->KEY = 0xCDEF89AB; +} + +/*! + * @brief Locks the FMC Program Erase Controller. + * + * @param None + * + * @retval None + */ +void FMC_Lock(void) +{ + FMC->CTRL2_B.LOCK = BIT_SET; +} + +/*! + * @brief Erases a specified FMC page. + * + * @param pageAddr: The page address to be erased. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_BUSY + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.PAGEERA = BIT_SET; + FMC->ADDR = pageAddr; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.PAGEERA = BIT_RESET; + } + return status; +} + +/*! + * @brief Erases all FMC pages. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EraseAllPage(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.MASSERA = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.MASSERA = BIT_RESET; + } + return status; +} + +/*! + * @brief Erases the FMC option bytes. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EraseOptionBytes(void) +{ + uint16_t rdtemp = 0x00A5; + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + if(FMC_GetReadProtectionStatus() != RESET) + { + rdtemp = 0x00; + } + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + FMC->CTRL2_B.OBP = BIT_SET; + OB->RDP = rdtemp; + status = FMC_WaitForLastOperation(0x000B0000); + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Programs a word at a specified address. + * + * @param address:the address to be programmed. + * + * @param data: the data to be programmed. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + __IOM uint32_t temp = 0; + + #ifdef APM32F10X_HD + __set_PRIMASK(1); + #endif + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.PG = BIT_SET; + + *(__IOM uint16_t *)address = data; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + temp = address + 2; + + *(__IOM uint16_t*) temp = data >> 16; + + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.PG = BIT_RESET; + } + else + { + FMC->CTRL2_B.PG = BIT_RESET; + } + } + + #ifdef APM32F10X_HD + __set_PRIMASK(0); + #endif + + return status; +} + +/*! + * @brief Programs a half word at a specified address. + * + * @param address:the address to be programmed. + * + * @param data: the data to be programmed. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + #ifdef APM32F10X_HD + __set_PRIMASK(1); + #endif + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.PG = BIT_SET; + *(__IOM uint16_t *)address = data; + status = FMC_WaitForLastOperation(0x000B0000); + FMC->CTRL2_B.PG = BIT_RESET; + } + + #ifdef APM32F10X_HD + __set_PRIMASK(0); + #endif + + return status; +} + +/*! + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param address:the address to be programmed. + * + * @param data: the data to be programmed. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + FMC->CTRL2_B.OBP = BIT_SET; + *(__IOM uint16_t *)address = data; + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Write protects the desired pages + * + * @param page:the address of the pages to be write protection + * This parameter can be any combination of the following values: + * for APM32F10X_LD £º + * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31 + * for APM32F10X_MD £º + * @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127 + * for APM32F10X_HD £º + * @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127 + * @arg FMC_WRP_PAGE_ALL + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page) +{ + uint16_t WPP0_Data = 0xFFFF, WPP1_Data = 0xFFFF, WPP2_Data = 0xFFFF, WPP3_Data = 0xFFFF; + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + page = ~page; + WPP0_Data = (page & 0x000000FF); + WPP1_Data = (page & 0x0000FF00) >> 8; + WPP2_Data = (page & 0x00FF0000) >> 16; + WPP3_Data = (page & 0xFF000000) >> 24; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + FMC->CTRL2_B.OBP = BIT_SET; + + if(WPP0_Data != 0xFF) + { + OB->WRP0 = WPP0_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + if((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF)) + { + OB->WRP1 = WPP1_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + if((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF)) + { + OB->WRP2 = WPP2_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + if((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF)) + { + OB->WRP3 = WPP3_Data; + status = FMC_WaitForLastOperation(0x000B0000); + } + + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Enables the read out protection. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_EnableReadOutProtection(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + FMC->CTRL2_B.OBP = BIT_SET; + OB->RDP = 0x00A5; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBE = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Disables the read out protection. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_DisableReadOutProtection(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + FMC->CTRL2_B.OBE = BIT_SET; + FMC->CTRL2_B.STA = BIT_SET; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBE = BIT_RESET; + FMC->CTRL2_B.OBP = BIT_SET; + OB->RDP = 0x00; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + else if(status != FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBE = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Programs the FMC User Option Byte. + * + * @param userConfig: Point to a FMC_UserConfig_T structure. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + FMC->OBKEY = 0x45670123; + FMC->OBKEY = 0xCDEF89AB; + + status = FMC_WaitForLastOperation(0x000B0000); + + if(status == FMC_STATUS_COMPLETE) + { + FMC->CTRL2_B.OBP = BIT_SET; + OB->USER = userConfig->iwdtSet | userConfig->stopSet | userConfig->stdbySet | 0xF8; + status = FMC_WaitForLastOperation(0x000B0000); + if(status == FMC_STATUS_TIMEOUT) + { + FMC->CTRL2_B.OBP = BIT_RESET; + } + } + return status; +} + +/*! + * @brief Read the FMC User Option Bytes values. + * + * @param None + * + * @retval Returns User Option Bytes values + */ +uint32_t FMC_ReadUserOptionByte(void) +{ + return (FMC->OBCS_B.UOB >> 2); +} + +/*! + * @brief Read the FMC Write Protection Option Bytes Register value. + * + * @param None + * + * @retval Returns the value of Option Bytes Write Protection Register. + */ +uint32_t FMC_ReadOptionByteWriteProtection(void) +{ + return FMC->WRTPROT; +} + +/*! + * @brief Get the FMC Read Out Protection Status is set or not. + * + * @param None + * + * @retval status : set or reset. + */ +uint8_t FMC_GetReadProtectionStatus(void) +{ + uint8_t flagstatus = RESET; + + if(FMC->OBCS_B.READPROT != RESET) + { + flagstatus = SET; + } + else + { + flagstatus = RESET; + } + return flagstatus; +} + +/*! + * @brief FMC Prefetch Buffer status is set or not. + * + * @param None + * + * @retval status : set or reset. + */ +uint8_t FMC_ReadPrefetchBufferStatus(void) +{ + return FMC->CTRL1_B.PBSF; +} + +/*! + * @brief Enables the specified FMC interrupts. + * + * @param interrupt: Select the FMC interrupt sources + * This parameter can be one of the following values: + * @arg FMC_INT_ERR : Error Interrupt + * @arg FMC_INT_OC : Operation Complete Interrupt + * + * @retval None + */ +void FMC_EnableInterrupt(FMC_INT_T interrupt) +{ + if(interrupt == FMC_INT_ERR) + { + FMC->CTRL2_B.ERRIE = ENABLE; + } + else + { + FMC->CTRL2_B.OCIE = ENABLE; + } +} + +/*! + * @brief Disable the specified FMC interrupts. + * + * @param interrupt: Select the FMC interrupt sources + * This parameter can be one of the following values: + * @arg FMC_INT_ERR : Error Interrupt + * @arg FMC_INT_OC : Operation Complete Interrupt + * + * @retval None + */ +void FMC_DisableInterrupt(FMC_INT_T interrupt) +{ + if(interrupt == FMC_INT_ERR) + { + FMC->CTRL2_B.ERRIE = DISABLE; + } + else + { + FMC->CTRL2_B.OCIE = DISABLE; + } +} + +/*! + * @brief Read FMC flag is set or not + * + * @param flag: status flag of FMC + * This parameter can be one of the following values: + * @arg FMC_FLAG_BUSY : FMC Busy flag + * @arg FMC_FLAG_OC : FMC Operation Complete flag + * @arg FMC_FLAG_PE : FMC Program error flag + * @arg FMC_FLAG_WPE : FMC Write protected error flag + * @arg FMC_FLAG_OBE : FMC Option Byte error flag + * + * @retval flag status : set or reset + */ +uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag) +{ + if(flag == FMC_FLAG_OBE) + { + return FMC->OBCS_B.OBE; + } + else if((FMC->STS & flag ) != RESET) + { + return SET; + } + return RESET; +} + +/*! + * @brief Clears the FMC's flag. + * + * @param flag: status flag of FMC + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_OC : FMC Operation Complete flag + * @arg FMC_FLAG_PE : FMC Program error flag + * @arg FMC_FLAG_WPE : FMC Write protected error flag + * + * @retval None + * + * @note + */ +void FMC_ClearStatusFlag(FMC_FLAG_T flag) +{ + FMC->STS = flag; +} + +/*! + * @brief Read the FMC Status. + * + * @param None + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_BUSY + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + */ +FMC_STATUS_T FMC_ReadStatus(void) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + if(FMC->STS_B.BUSYF == BIT_SET) + { + status = FMC_STATUS_BUSY; + } + else if(FMC->STS_B.PEF == BIT_SET) + { + status = FMC_STATUS_ERROR_PG; + } + else if(FMC->STS_B.WPEF == BIT_SET) + { + status = FMC_STATUS_ERROR_WRP; + } + else + { + status = FMC_STATUS_COMPLETE; + } + return status; +} + +/*! + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param timeOut:FMC programming timeout value. + * + * @retval Returns the flash state.It can be one of value: + * @arg FMC_STATUS_ERROR_PG + * @arg FMC_STATUS_ERROR_WRP + * @arg FMC_STATUS_COMPLETE + * @arg FMC_STATUS_TIMEOUT + */ +FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut) +{ + FMC_STATUS_T status = FMC_STATUS_COMPLETE; + + /** Check for the Flash Status */ + status = FMC_ReadStatus(); + + /** Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FMC_STATUS_BUSY) && (timeOut !=0)) + { + status = FMC_ReadStatus(); + timeOut--; + } + if(timeOut == 0x00) + { + status = FMC_STATUS_TIMEOUT; + } + return status; +} + +/**@} end of group FMC_Fuctions*/ +/**@} end of group FMC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c new file mode 100644 index 0000000000..9182ae9290 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c @@ -0,0 +1,531 @@ +/*! + * @file apm32f10x_gpio.c + * + * @brief This file provides all the GPIO firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_gpio.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset GPIO peripheral registers to their default reset values + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @retval None + */ +void GPIO_Reset(GPIO_T* port) +{ + RCM_APB2_PERIPH_T APB2Periph; + + if (port == GPIOA) + { + APB2Periph = RCM_APB2_PERIPH_GPIOA; + } + else if (port == GPIOB) + { + APB2Periph = RCM_APB2_PERIPH_GPIOB; + } + else if (port == GPIOC) + { + APB2Periph = RCM_APB2_PERIPH_GPIOC; + } + else if (port == GPIOD) + { + APB2Periph = RCM_APB2_PERIPH_GPIOD; + } + else if (port == GPIOE) + { + APB2Periph = RCM_APB2_PERIPH_GPIOE; + } + else if (port == GPIOF) + { + APB2Periph = RCM_APB2_PERIPH_GPIOF; + } + else if (port == GPIOG) + { + APB2Periph = RCM_APB2_PERIPH_GPIOG; + } + + RCM_EnableAPB2PeriphReset(APB2Periph); + RCM_DisableAPB2PeriphReset(APB2Periph); +} + +/*! + * @brief Reset Alternate Functions registers to their default reset values + * + * @param None + * + * @retval None + */ +void GPIO_AFIOReset(void) +{ + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_AFIO); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_AFIO); +} + +/*! + * @brief Config the GPIO peripheral according to the specified parameters in the gpioConfig + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param gpioConfig: pointer to a GPIO_Config_T structure + * + * @retval None + */ +void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig) +{ + uint8_t i; + uint32_t mode; + uint32_t CR; + uint32_t temp; + uint32_t shift; + + mode = gpioConfig->mode & 0x0f; + + if (gpioConfig->mode & 0x80) + { + mode |= gpioConfig->speed; + } + + if (gpioConfig->pin & 0xff) + { + CR = port->CFGLOW; + + for (i = 0, shift = 0x01; i < 8; i++, shift <<= 1) + { + if (gpioConfig->pin & shift) + { + temp = i << 2; + CR &= (uint32_t)~(0x0f << temp); + CR |= mode << temp; + + if (gpioConfig->mode == GPIO_MODE_IN_PD) + { + port->BC = shift; + } + else if (gpioConfig->mode == GPIO_MODE_IN_PU) + { + port->BSC = shift; + } + } + } + + port->CFGLOW = CR; + } + + if (gpioConfig->pin & 0xff00) + { + CR = port->CFGHIG; + + for (i = 8, shift = 0x100; i < 16; i++, shift <<= 1) + { + if (gpioConfig->pin & shift) + { + temp = (i - 8) << 2; + CR &= (uint32_t)~(0x0f << temp); + CR |= mode << temp; + + if (gpioConfig->mode == GPIO_MODE_IN_PD) + { + port->BC = shift; + } + else if (gpioConfig->mode == GPIO_MODE_IN_PU) + { + port->BSC = shift; + } + } + } + + port->CFGHIG = CR; + } +} + +/*! + * @brief Fills each gpioConfig member with its default value. + * + * @param gpioConfig : pointer to a GPIO_Config_T structure which will be initialized. + * + * @retval None + */ +void GPIO_StructInit(GPIO_Config_T* gpioConfig) +{ + gpioConfig->pin = GPIO_PIN_ALL; + gpioConfig->speed = GPIO_SPEED_2MHz; + gpioConfig->mode = GPIO_MODE_IN_FLOATING; +} + +/*! + * @brief Reads the specified input port pin + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to read. + * This parameter can be one of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval The input port pin value + */ +uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin) +{ + uint8_t ret; + + ret = (port->IDATA & pin) ? BIT_SET : BIT_RESET; + + return ret; +} + +/*! + * @brief Reads the specified GPIO input data port + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @retval GPIO input data port value + */ +uint16_t GPIO_ReadInputPort(GPIO_T* port) +{ + return ((uint16_t)port->IDATA); +} + +/*! + * @brief Reads the specified output data port bit + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to read. + * This parameter can be one of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval The output port pin value + */ +uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin) +{ + + uint8_t ret; + + ret = (port->ODATA & pin) ? BIT_SET : BIT_RESET; + + return ret; +} + +/*! + * @brief Reads the specified GPIO output data port + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @retval output data port value + */ +uint16_t GPIO_ReadOutputPort(GPIO_T* port) +{ + return ((uint16_t)port->ODATA); +} + +/*! + * @brief Sets the selected data port bits + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to be written. + * This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_SetBits(GPIO_T* port, uint16_t pin) +{ + port->BSC = (uint32_t)pin; +} + +/*! + * @brief Clears the selected data port bits + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : specifies pin to be cleared. + * This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ResetBits(GPIO_T* port, uint16_t pin) +{ + port->BC = (uint32_t)pin; +} + +/*! + * @brief Writes data to the specified GPIO data port bit + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : Select specifies pin. + * This parameter can be one of GPIO_PIN_x( x can be from 0 to 15). + * + * + * @param bitVal : specifies the value to be written to the port output data register + * This parameter can be one of the following values: + * @arg BIT_RESET: Reset the port pin + * @arg BIT_SET : Set the port pin + * + * @retval None + */ +void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal) +{ + if (bitVal != BIT_RESET) + { + port->BSC = pin; + } + else + { + port->BC = pin ; + } +} + +/*! + * @brief Writes data to the specified GPIO data port + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param portValue : specifies the value to be written to the port output data register. + * + * @retval None + */ +void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue) +{ + port->ODATA = (uint32_t)portValue; +} + +/*! + * @brief Locks GPIO Pins configuration registers + * + * @param port: Select the GPIO port. + * This parameter can be one of GPIOx( x can be from A to G). + * + * @param pin : Select specifies pin. + * This parameter can be any combination of GPIO_PIN_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin) +{ + uint32_t val = 0x00010000; + + val |= pin; + /* Set LCKK bit */ + port->LOCK = val ; + /* Reset LCKK bit */ + port->LOCK = pin; + /* Set LCKK bit */ + port->LOCK = val; + /* Read LCKK bit*/ + val = port->LOCK; + /* Read LCKK bit*/ + val = port->LOCK; +} + +/*! + * @brief Selects the GPIO pin used as Event output + * + * @param portSource : selects the GPIO port to be used as source for Event output. + * This parameter can be one of GPIO_PORT_SOURCE_x( x can be from A to E). + * + * @param pinSource specifies the pin for the Event output + * This parameter can be GPIO_PIN_SOURCE_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource) +{ + AFIO->EVCTRL_B.PORTSEL = portSource; + AFIO->EVCTRL_B.PINSEL = pinSource; +} + +/*! + * @brief Enables the Event Output + * + * @param None + * + * @retval None + */ +void GPIO_EnableEventOutput(void) +{ + AFIO->EVCTRL_B.EVOEN = BIT_SET; +} + +/*! + * @brief Disable the Event Output + * + * @param None + * + * @retval None + */ +void GPIO_DisableEventOutput(void) +{ + AFIO->EVCTRL_B.EVOEN = BIT_RESET; +} + +/*! + * @brief Changes the mapping of the specified pin + * + * @param remap : selects the pin to remap + * This parameter can be one of the following values: + * @arg GPIO_NO_REMAP_SPI1 : No SPI1 Alternate Function mapping + * @arg GPIO_REMAP_SPI1 : SPI1 Alternate Function mapping + * @arg GPIO_NO_REMAP_I2C1 : No I2C1 Alternate Function mapping + * @arg GPIO_REMAP_I2C1 : I2C1 Alternate Function mapping + * @arg GPIO_NO_REMAP_USART1 : No USART1 Alternate Function mapping + * @arg GPIO_REMAP_USART1 : USART1 Alternate Function mapping + * @arg GPIO_NO_REMAP_USART2 : No USART2 Alternate Function mapping + * @arg GPIO_REMAP_USART2 : USART2 Alternate Function mapping + * @arg GPIO_NO_REMAP_USART3 : No USART3 Partial Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP_USART3 : USART3 Partial Alternate Function mapping + * @arg GPIO_FULL_REMAP_USART3 : USART3 Full Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR1 : No TIM1 Partial Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP_TMR1 : TIM1 Partial Alternate Function mapping + * @arg GPIO_FULL_REMAP_TMR1 : TIM1 Full Alternate Function mapping + * @arg GPIO_NO_REMAP1_TMR2 : No TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP1_TMR2 : TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP2_TMR2 : TIM2 Partial2 Alternate Function mapping + * @arg GPIO_FULL_REMAP_TMR2 : TIM2 Full Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR3 : No TIM3 Partial Alternate Function mapping + * @arg GPIO_PARTIAL_REMAP_TMR3 : TIM3 Partial Alternate Function mapping + * @arg GPIO_FULL_REMAP_TMR3 : TIM3 Full Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR4 : No TIM4 Alternate Function mapping + * @arg GPIO_REMAP_TMR4 : TIM4 Alternate Function mapping + * @arg GPIO_NO_REMAP_CAN1 : No CAN1 Alternate Function mapping + * @arg GPIO_REMAP1_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_REMAP2_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_NO_REMAP_PD01 : No PD01 Alternate Function mapping + * @arg GPIO_REMAP_PD01 : PD01 Alternate Function mapping + * @arg GPIO_NO_REMAP_TMR5CH4_LSI : No LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_REMAP_TMR5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_NO_REMAP_ADC1_ETRGINJ : No ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_REMAP_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_NO_REMAP_ADC1_ETRGREG : No ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_REMAP_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_NO_REMAP_ADC2_ETRGINJ : No ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_REMAP_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_NO_REMAP_ADC2_ETRGREG : No ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_REMAP_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_NO_REMAP_CAN2 : No CAN2 Alternate Function mapping + * @arg GPIO_REMAP_CAN2 : CAN2 Alternate Function mapping + * @arg GPIO_NO_REMAP_SWJ : Full SWJ Enabled (JTAG-DP + SW-DP) + * @arg GPIO_REMAP_SWJ_NOJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_REMAP_SWJ_JTAGDISABLE : JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_REMAP_SWJ_DISABLE : Full SWJ Disabled (JTAG-DP + SW-DP) + * + * @retval When you use GPIO_REMAP_CAN2, you must put this function last of all other ConfigPinRemap Function. + */ +void GPIO_ConfigPinRemap(GPIO_REMAP_T remap) +{ + uint32_t val, mask, bitOffset, regOffset; + uint32_t regVal; + + val = remap & 0x0f; + mask = (remap >> 4) & 0x0f; + bitOffset = (remap >> 8) & 0xff; + regOffset = (remap >> 16) & 0x0f; + + if (regOffset) + { + regVal = AFIO->REMAP2; + } + else + { + regVal = AFIO->REMAP1; + } + + if(remap >> 8 == 0x18) + { + regVal &= 0xF0FFFFFF; + AFIO->REMAP1 &= 0xF0FFFFFF; + } + else + { + regVal |= 0x0F000000; + } + + mask <<= bitOffset; + regVal &= (uint32_t)~mask; + val <<= bitOffset; + regVal |= val; + + if (regOffset) + { + AFIO->REMAP2 = regVal; + } + else + { + AFIO->REMAP1 = regVal; + } +} + +/*! + * @brief Selects the GPIO pin used as EINT Line + * + * @param portSource : selects the GPIO port to be used as source for EINT line. + * This parameter can be one of GPIO_PORT_SOURCE_x( x can be from A to G). + * + * @param pinSource : Specifies the EINT line to be configured. + * This parameter can be GPIO_PIN_SOURCE_x( x can be from 0 to 15). + * + * @retval None + */ +void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource) +{ + uint32_t shift; + + if (pinSource <= GPIO_PIN_SOURCE_3) + { + shift = pinSource << 2; + AFIO->EINTSEL1 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL1 |= portSource << shift; + } + + else if (pinSource <= GPIO_PIN_SOURCE_7) + { + shift = (pinSource - GPIO_PIN_SOURCE_4) << 2; + AFIO->EINTSEL2 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL2 |= portSource << shift; + } + + else if (pinSource <= GPIO_PIN_SOURCE_11) + { + shift = (pinSource - GPIO_PIN_SOURCE_8) << 2; + AFIO->EINTSEL3 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL3 |= portSource << shift; + } + + else if (pinSource <= GPIO_PIN_SOURCE_15) + { + shift = (pinSource - GPIO_PIN_SOURCE_12) << 2; + AFIO->EINTSEL4 &= (uint32_t )~(0x0f << shift); + AFIO->EINTSEL4 |= portSource << shift; + } +} + +/**@} end of group GPIO_Fuctions*/ +/**@} end of group GPIO_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c new file mode 100644 index 0000000000..319866723b --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c @@ -0,0 +1,1013 @@ +/*! + * @file apm32f10x_i2c.c + * + * @brief This file provides all the I2C firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_i2c.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset I2C + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_Reset(I2C_T* i2c) +{ + if(i2c == I2C1) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + } + else + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + } +} + +/*! + * @brief Configure I2C by configuring the structure + * + * @param i2c: I2C selet 1 or 2 + * + * @param i2cConfig: pointer to a I2C_Config_T structure + * + * @retval None + */ +void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint32_t PCLK1 = 8000000, PCLK2 = 0; + uint16_t result = 0x04; + + i2c->SWITCH = 0; + + /** I2C CTRL2 Configuration */ + RCM_ReadPCLKFreq(&PCLK1, &PCLK2); + freqrange = PCLK1 / 1000000; + i2c->CTRL2_B.CLKFCFG= freqrange; + + /** I2C CLKCTRL Configuration */ + i2c->CTRL1_B.I2CEN = BIT_RESET; + + if(i2cConfig->clockSpeed <= 100000) + { + result = (PCLK1 / (i2cConfig->clockSpeed << 1)); + if(result < 0x04) + { + result = 0x04; + } + i2c->RISETMAX = freqrange + 1; + tmpreg |= result; + } + /** Configure speed in fast mode */ + else + { + if(i2cConfig->dutyCycle == I2C_DUTYCYCLE_2) + { + result = (PCLK1 / (i2cConfig->clockSpeed * 3)); + } + else + { + result = (PCLK1 / (i2cConfig->clockSpeed * 25)); + result |= I2C_DUTYCYCLE_16_9; + } + + if((result & 0x0FFF) == 0) + { + result |= 0x0001; + } + + tmpreg |= (uint16_t)(result | 0x8000); + i2c->RISETMAX = ((((freqrange) * 300) / 1000) + 1); + } + i2c->CLKCTRL = tmpreg; + i2c->CTRL1_B.I2CEN = BIT_SET; + + /** i2c CTRL1 Configuration */ + i2c->CTRL1_B.ACKEN = BIT_RESET; + i2c->CTRL1_B.SMBTCFG = BIT_RESET; + i2c->CTRL1_B.SMBEN = BIT_RESET; + + i2c->CTRL1 |= i2cConfig->mode; + i2c->CTRL1_B.ACKEN = i2cConfig->ack; + + i2c->SADDR1 = i2cConfig->ackAddress | i2cConfig->ownAddress1; +} + +/*! + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param i2cConfig: pointer to a I2C_Config_T structure + * + * @retval None + */ +void I2C_ConfigStructInit(I2C_Config_T* i2cConfig) +{ + i2cConfig->clockSpeed = 5000; + i2cConfig->mode = I2C_MODE_I2C; + i2cConfig->dutyCycle = I2C_DUTYCYCLE_2; + i2cConfig->ownAddress1 = 0; + i2cConfig->ack = I2C_ACK_DISABLE; + i2cConfig->ackAddress = I2C_ACK_ADDRESS_7BIT; +} + +/*! + * @brief Enable I2C + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_Enable(I2C_T* i2c) +{ + i2c->CTRL1_B.I2CEN = ENABLE; +} + +/*! + * @brief Disable I2C + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_Disable(I2C_T* i2c) +{ + i2c->CTRL1_B.I2CEN = DISABLE; +} + +/*! + * @brief Enable Generates i2c communication START condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableGenerateStart(I2C_T* i2c) +{ + i2c->CTRL1_B.START = BIT_SET; +} + +/*! + * @brief Disable Generates i2c communication START condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableGenerateStart(I2C_T* i2c) +{ + i2c->CTRL1_B.START = BIT_RESET; +} + +/*! + * @brief Enable Generates i2c communication STOP condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableGenerateStop(I2C_T* i2c) +{ + i2c->CTRL1_B.STOP = BIT_SET; +} + +/*! + * @brief Disable Generates i2c communication STOP condition. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableGenerateStop(I2C_T* i2c) +{ + i2c->CTRL1_B.STOP = BIT_RESET; +} + +/*! + * @brief Enables the specified I2C acknowledge feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableAcknowledge(I2C_T* i2c) +{ + i2c->CTRL1_B.ACKEN = ENABLE; +} + +/*! + * @brief Disables the specified I2C acknowledge feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableAcknowledge(I2C_T* i2c) +{ + i2c->CTRL1_B.ACKEN = DISABLE; +} + +/*! + * @brief Config the specified I2C own address2. + * + * @param i2c: I2C selet 1 or 2 + * + * @param address:specifies the 7bit I2C own address2. + * + * @retval None + */ +void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address) +{ + i2c->SADDR2_B.ADDR2 = address; +} + +/*! + * @brief Enables the specified I2C dual addressing mode. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableDualAddress(I2C_T* i2c) +{ + i2c->SADDR2_B.ADDRNUM = ENABLE; +} + +/*! + * @brief Disables the specified I2C dual addressing mode. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableDualAddress(I2C_T* i2c) +{ + i2c->SADDR2_B.ADDRNUM = DISABLE; +} + +/*! + * @brief Enables the specified I2C general call feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableGeneralCall(I2C_T* i2c) +{ + i2c->CTRL1_B.SRBEN = ENABLE; +} + +/*! + * @brief Disables the specified I2C general call feature. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableGeneralCall(I2C_T* i2c) +{ + i2c->CTRL1_B.SRBEN = DISABLE; +} + +/*! + * @brief Send one byte + * + * @param i2c: I2C selet 1 or 2 + * + * @param data: data to send + * + * @retval None + */ +void I2C_TxData(I2C_T* i2c, uint8_t data) +{ + i2c->DATA_B.DATA = data; +} + +/*! + * @brief Returns the recevie data + * + * @param i2c: I2C selet 1 or 2 + * + * @retval received data + */ +uint8_t I2C_RxData(I2C_T* i2c) +{ + return i2c->DATA_B.DATA; +} + +/*! + * @brief Transmits the address byte to select the slave device. + * + * @param i2c: I2C selet 1 or 2 + * + * @param address: slave address which will be transmitted + * + * @param direction: Direction mode + * The parameter can be one of following values: + * @arg I2C_DIRECTION_TX: Transmitter mode + * @arg I2C_DIRECTION_RX: Receiver mode + * @retval None + */ +void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction) +{ + if(direction != I2C_DIRECTION_TX) + { + i2c->DATA_B.DATA = address | 0x0001; + } + else + { + i2c->DATA_B.DATA = address & 0xFFFE; + } +} + +/*! + * @brief Reads the I2C register and returns its value. + * + * @param i2c: I2C selet 1 or 2 + * + * @param i2cRegister : register to read + * The parameter can be one of following values: + * @arg I2C_REGISTER_CTRL1: CTRL1 register + * @arg I2C_REGISTER_CTRL2: CTRL2 register + * @arg I2C_REGISTER_SADDR1: SADDR1 register + * @arg I2C_REGISTER_SADDR2: SADDR2 register + * @arg I2C_REGISTER_DATA: DATA register + * @arg I2C_REGISTER_STS1: STS1 register + * @arg I2C_REGISTER_STS2: STS2 register + * @arg I2C_REGISTER_CLKCTRL: CLKCTRL register + * @arg I2C_REGISTER_RISETMAX: RISETMAX register + * @arg I2C_REGISTER_SWITCH: SWITCH register + * + * @retval The value of the read register + */ +uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister) +{ + switch (i2cRegister) + { + case I2C_REGISTER_CTRL1: + return i2c->CTRL1; + case I2C_REGISTER_CTRL2: + return i2c->CTRL2; + case I2C_REGISTER_SADDR1: + return i2c->SADDR1; + case I2C_REGISTER_SADDR2: + return i2c->SADDR2; + case I2C_REGISTER_DATA: + return i2c->DATA; + case I2C_REGISTER_STS1: + return i2c->STS1; + case I2C_REGISTER_STS2: + return i2c->STS2; + case I2C_REGISTER_CLKCTRL: + return i2c->CLKCTRL; + case I2C_REGISTER_RISETMAX: + return i2c->RISETMAX; + case I2C_REGISTER_SWITCH: + return i2c->SWITCH; + default: + return 0; + } +} + +/*! + * @brief Enables the I2C software reset. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableSoftwareReset(I2C_T* i2c) +{ + i2c->CTRL1_B.SWRST = ENABLE; +} + +/*! + * @brief Disables the I2C software reset. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableSoftwareReset(I2C_T* i2c) +{ + i2c->CTRL1_B.SWRST = DISABLE; +} + +/*! + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param i2c: I2C selet 1 or 2 + * + * @param NACKPosition: specifies the NACK position. + * + * @retval None + */ +void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition) +{ + if(NACKPosition == I2C_NACK_POSITION_NEXT) + { + i2c->CTRL1_B.ACKPOS = BIT_SET; + } + else + { + i2c->CTRL1_B.ACKPOS = BIT_RESET; + } +} + +/*! + * @brief Control the height of pin of SMBusAlert + * + * @param i2c: I2C selet 1 or 2 + * + * @param SMBusState: SMBAlert pin level. + * The parameter can be one of following values: + * @arg I2C_SMBUSALER_LOW: SMBus Alert pin low + * @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high + * @retval None + */ +void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState) +{ + if(SMBusState == I2C_SMBUSALER_LOW) + { + i2c->CTRL1_B.ALERTEN = BIT_SET; + } + else + { + i2c->CTRL1_B.ALERTEN = BIT_RESET; + } +} + +/*! + * @brief Enables the I2C PEC transfer. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnablePECTransmit(I2C_T* i2c) +{ + i2c->CTRL1_B.PEC = BIT_SET; +} + +/*! + * @brief Disables the I2C PEC transfer. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisablePECTransmit(I2C_T* i2c) +{ + i2c->CTRL1_B.PEC = BIT_RESET; +} + +/*! + * @brief Selects the I2C PEC position. + * + * @param i2c: I2C selet 1 or 2 + * + * @param PECPosition: PEC position + * The parameter can be one of following values: + * @arg I2C_PEC_POSITION_NEXT: indicates that the next byte is PEC + * @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC + * @retval None + */ +void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition) +{ + if(PECPosition == I2C_PEC_POSITION_NEXT) + { + i2c->CTRL1_B.ACKPOS = BIT_SET; + } + else + { + i2c->CTRL1_B.ACKPOS = BIT_RESET; + } +} + +/*! + * @brief Enables the PEC value calculation of the transferred bytes. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnablePEC(I2C_T* i2c) +{ + i2c->CTRL1_B.PECEN = BIT_SET; +} + +/*! + * @brief Disables the PEC value calculation of the transferred bytes. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisablePEC(I2C_T* i2c) +{ + i2c->CTRL1_B.PECEN = BIT_RESET; +} + +/*! + * @brief Read the PEC value for the I2C. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval value of PEC + */ +uint8_t I2C_ReadPEC(I2C_T* i2c) +{ + return i2c->STS2_B.PECVALUE; +} + +/*! + * @brief Enables the I2C ARP. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableARP(I2C_T* i2c) +{ + i2c->CTRL1_B.ARPEN = BIT_SET; +} + +/*! +* @brief Disables the I2C ARP. +* +* @param i2c: I2C selet 1 or 2 +* +* @retval None +*/ +void I2C_DisableARP(I2C_T* i2c) +{ + i2c->CTRL1_B.ARPEN = BIT_RESET; +} + +/*! + * @brief Enables the I2C Clock stretching. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableStretchClock(I2C_T* i2c) +{ + i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET; +} + +/*! + * @brief Disables the I2C Clock stretching. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableStretchClock(I2C_T* i2c) +{ + i2c->CTRL1_B.CLKSTRETCHD = BIT_SET; +} + +/*! + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param i2c: I2C selet 1 or 2 + * + * @param dutyCycle: the fast mode duty cycle. + * The parameter can be one of following values: + * @arg I2C_DUTYCYCLE_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2 + * @retval None + */ +void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle) +{ + if(dutyCycle == I2C_DUTYCYCLE_16_9) + { + i2c->CLKCTRL_B.FDUTYCFG = BIT_SET; + } + else + { + i2c->CLKCTRL_B.FDUTYCFG = BIT_RESET; + } +} + +/*! + * @brief Enables the specified I2C DMA requests. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableDMA(I2C_T* i2c) +{ + i2c->CTRL2_B.DMAEN = ENABLE; +} + +/*! + * @brief Disable the specified I2C DMA requests. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableDMA(I2C_T* i2c) +{ + i2c->CTRL2_B.DMAEN = DISABLE; +} + +/*! + * @brief Enable DMA to receive the last transfer + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_EnableDMALastTransfer(I2C_T* i2c) +{ + i2c->CTRL2_B.LTCFG = BIT_SET; +} + +/*! + * @brief Disable DMA to receive the last transfer + * + * @param i2c: I2C selet 1 or 2 + * + * @retval None + */ +void I2C_DisableDMALastTransfer(I2C_T* i2c) +{ + i2c->CTRL2_B.LTCFG = BIT_RESET; +} + +/*! + * @brief Enables the specified I2C interrupts. + * + * @param i2c: I2C selet 1 or 2 + * + * @param interrupt:I2C interrupts sources + * The parameter can be any combination of following values: + * @arg I2C_INT_BUF: Buffer interrupt + * @arg I2C_INT_EVT: Event interrupt + * @arg I2C_INT_ERR: Error interrupt + * + * @retval None + */ +void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt) +{ + i2c->CTRL2 |= interrupt; +} + +/*! + * @brief Disable the specified I2C interrupts. + * + * @param i2c: I2C selet 1 or 2 + * + * @param interrupt:I2C interrupts sources + * The parameter can be any combination of following values: + * @arg I2C_INT_BUF: Buffer interrupt + * @arg I2C_INT_EVT: Event interrupt + * @arg I2C_INT_ERR: Error interrupt + * + * @retval None + */ +void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt) +{ + i2c->CTRL2 &= ~interrupt; +} + +/*! + * @brief Check that the last event is equal to the last passed event + * + * @param i2c: I2C selet 1 or 2 + * + * @param i2cEvent: the event to be checked. + * The parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @retval Status: SUCCESS or ERROR + */ +uint8_t I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = i2c->STS1 & 0x0000FFFF; + flag2 = i2c->STS2 & 0x0000FFFF; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & 0x00FFFFFF; + + if((lastevent & i2cEvent) == i2cEvent) + { + return SUCCESS; + } + return ERROR; +} + +/*! + * @brief Read the last i2c Event. + * + * @param i2c: I2C selet 1 or 2 + * + * @retval The last event + */ +uint32_t I2C_ReadLastEvent(I2C_T* i2c) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = i2c->STS1 & 0x0000FFFF; + flag2 = i2c->STS2 & 0x0000FFFF; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & 0x00FFFFFF; + + return lastevent; +} + +/*! + * @brief Check whether the I2C flag is set + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C flag + * The parameter can be one of the following values: + * @arg I2C_FLAG_DUALADDR: Dual flag (Slave mode) + * @arg I2C_FLAG_SMMHADDR: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDADDR: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TR: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSBSY: Bus busy flag + * @arg I2C_FLAG_MS: Master/Slave flag + * @arg I2C_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_FLAG_PECE: PEC error in reception flag + * @arg I2C_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AE: Acknowledge error flag + * @arg I2C_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXBE: Transmitter data register empty flag + * @arg I2C_FLAG_RXBNE: Receiver data register not empty flag + * @arg I2C_FLAG_STOP: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADDR10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTC: Byte transfer complete flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) + * @arg I2C_FLAG_START: Start bit flag (Master mode) + * + * @retval Status: flag SET or RESET + */ +uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) +{ + + uint8_t status = 0; + switch (flag) + { + case I2C_FLAG_DUALADDR: + status = i2c->STS2_B.DUALADDRFLG; + break; + case I2C_FLAG_SMMHADDR: + status = i2c->STS2_B.SMMHADDR; + break; + case I2C_FLAG_SMBDADDR: + status = i2c->STS2_B.SMBDADDRFLG; + break; + case I2C_FLAG_GENCALL: + status = i2c->STS2_B.GENCALLFLG; + break; + case I2C_FLAG_TR: + status = i2c->STS2_B.TRFLG; + break; + case I2C_FLAG_BUSBSY: + status = i2c->STS2_B.BUSBSYFLG; + break; + case I2C_FLAG_MS: + status = i2c->STS2_B.MSFLG; + break; + case I2C_FLAG_SMBALT: + status = i2c->STS1_B.SMBALTFLG; + break; + case I2C_FLAG_TTE: + status = i2c->STS1_B.TTEFLG; + break; + case I2C_FLAG_PECE: + status = i2c->STS1_B.PECEFLG; + break; + case I2C_FLAG_OVRUR: + status = i2c->STS1_B.OVRURFLG; + break; + case I2C_FLAG_AE: + status = i2c->STS1_B.AEFLG; + break; + case I2C_FLAG_AL: + status = i2c->STS1_B.ALFLG; + break; + case I2C_FLAG_BERR: + status = i2c->STS1_B.BERRFLG; + break; + case I2C_FLAG_TXBE: + status = i2c->STS1_B.TXBEFLG; + break; + case I2C_FLAG_RXBNE: + status = i2c->STS1_B.RXBNEFLG; + break; + case I2C_FLAG_STOP: + status = i2c->STS1_B.STOPFLG; + break; + case I2C_FLAG_ADDR10: + status = i2c->STS1_B.ADDR10FLG; + break; + case I2C_FLAG_BTC: + status = i2c->STS1_B.BTCFLG; + break; + case I2C_FLAG_ADDR: + status = i2c->STS1_B.ADDRFLG; + break; + case I2C_FLAG_START: + status = i2c->STS1_B.STARTFLG; + break; + default: + break; + } + return status; +} + +/*! + * @brief Clear the I2C flag + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C flag + * The parameter can be one of the following values: + * @arg I2C_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_FLAG_PECE: PEC error in reception flag + * @arg I2C_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AE: Acknowledge error flag + * @arg I2C_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @retval None + * + * @note 1)I2C_FLAG_STOP: Stop detection flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a write operation to I2C_CRTL1 register (I2C_Enable()). + * 2)I2C_FLAG_ADDR10: 10-bit header sent flag is cleared by software sequence: + * a read operation to I2C_STS1 (I2C_ReadStatusFlag()) + * followed by writing the second byte of the address in I2C_DATA register. + * 3)I2C_FLAG_BTC: Byte transfer complete flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a read/write to I2C_DATA register (I2C_TxData()). + * 4)I2C_FLAG_ADDR: Address sent flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a read operation to I2C_STS2 register ((void)(I2Cx->STS2)). + * 5)I2C_FLAG_START: Start bit flag is cleared software sequence: + * a read operation to I2C_STS1 register (I2C_ReadStatusFlag()) + * followed by a write operation to I2C_DATA register (I2C_TxData()). + */ +void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag) +{ + switch (flag) + { + case I2C_FLAG_SMBALT: + i2c->STS1_B.SMBALTFLG = BIT_RESET; + break; + case I2C_FLAG_TTE: + i2c->STS1_B.TTEFLG = BIT_RESET; + break; + case I2C_FLAG_PECE: + i2c->STS1_B.PECEFLG = BIT_RESET; + break; + case I2C_FLAG_OVRUR: + i2c->STS1_B.OVRURFLG = BIT_RESET; + break; + case I2C_FLAG_AE: + i2c->STS1_B.AEFLG = BIT_RESET; + break; + case I2C_FLAG_AL: + i2c->STS1_B.ALFLG = BIT_RESET; + break; + case I2C_FLAG_BERR: + i2c->STS1_B.BERRFLG = BIT_RESET; + break; + default: + break; + } +} + +/*! + * @brief Check whether the I2C interrupts is set + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C interrupts + * The parameter can be one of the following values: + * @arg I2C_INT_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_INT_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_INT_FLAG_PECE: PEC error in reception flag + * @arg I2C_INT_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_FLAG_AE: Acknowledge error flag + * @arg I2C_INT_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_INT_FLAG_BERR: Bus error flag + * @arg I2C_INT_FLAG_TXBE: Transmitter data register empty flag + * @arg I2C_INT_FLAG_RXBNE: Receiver data register not empty flag + * @arg I2C_INT_FLAG_STOP: Stop detection flag (Slave mode) + * @arg I2C_INT_FLAG_ADDR10: 10-bit header sent flag (Master mode) + * @arg I2C_INT_FLAG_BTC: Byte transfer complete flag + * @arg I2C_INT_FLAG_ADDR: Address sent flag (Master mode) + * @arg I2C_INT_FLAG_START: Start bit flag (Master mode) + * + * @retval Status: flag SET or RESET + */ +uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) +{ + uint32_t enablestatus = 0; + + enablestatus = ((flag & 0x07000000) >> 16) & (i2c->CTRL2); + flag &= 0x00FFFFFF; + if(((i2c->STS1 & flag) != RESET) && enablestatus) + { + return SET; + } + return RESET; +} + +/*! + * @brief Clears the I2C interrupt flag bits. + * + * @param i2c: I2C selet 1 or 2 + * + * @param flag: specifies the I2C flag + * The parameter can be one of the following values: + * @arg I2C_INT_FLAG_SMBALT: SMBus Alert flag + * @arg I2C_INT_FLAG_TTE: Timeout or Tlow error flag + * @arg I2C_INT_FLAG_PECE: PEC error in reception flag + * @arg I2C_INT_FLAG_OVRUR: Overrun/Underrun flag (Slave mode) + * @arg I2C_INT_FLAG_AE: Acknowledge error flag + * @arg I2C_INT_FLAG_AL: Arbitration lost flag (Master mode) + * @arg I2C_INT_FLAG_BERR: Bus error flag + * + * @retval None + * + * @note 1)I2C_INT_FLAG_STOP: Stop detection flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a write operation to I2C_CRTL1 register (I2C_Enable()). + * 2)I2C_INT_FLAG_ADDR10: 10-bit header sent flag is cleared by software sequence: + * a read operation to I2C_STS1 (I2C_ReadIntFlag()) + * followed by writing the second byte of the address in I2C_DATA register. + * 3)I2C_INT_FLAG_BTC: Byte transfer complete flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a read/write to I2C_DATA register (I2C_TxData()). + * 4)I2C_INT_FLAG_ADDR: Address sent flag is cleared by software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a read operation to I2C_STS2 register ((void)(I2Cx->STS2)). + * 5)I2C_INT_FLAG_START: Start bit flag is cleared software sequence: + * a read operation to I2C_STS1 register (I2C_ReadIntFlag()) + * followed by a write operation to I2C_DATA register (I2C_TxData()). + */ +void I2C_ClearIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag) +{ + uint32_t flagpos = 0; + + flagpos = flag & 0x00FFFFFF; + i2c->STS1 = ~flagpos; +} + +/**@} end of group I2C_Fuctions*/ +/**@} end of group I2C_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c new file mode 100644 index 0000000000..a4a743749c --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c @@ -0,0 +1,135 @@ +/*! + * @file apm32f10x_iwdt.c + * + * @brief This file provides all the IWDT firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_iwdt.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup IWDT_Driver IWDT Driver + @{ +*/ + +/** @addtogroup IWDT_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Enable IWDT + * + * @param None + * + * @retval None + */ +void IWDT_Enable(void) +{ + IWDT->KEY = IWDT_KEYWORD_ENABLE; +} + +/*! + * @brief Reload the IWDT counter with value + * + * @param None + * + * @retval None + */ +void IWDT_Refresh(void) +{ + IWDT->KEY = IWDT_KEYWORD_RELOAD; +} + +/*! + * @brief Set IWDT count reload values + * + * @param reload: IWDT count reload values + * + * @retval None + */ +void IWDT_ConfigReload(uint16_t reload) +{ + IWDT->CNTRLD = reload; +} + +/*! + * @brief Enable the IWDT write access + * + * @param None + * + * @retval None + */ +void IWDT_EnableWriteAccess(void) +{ + IWDT->KEY_B.KEY = IWDT_WRITEACCESS_ENABLE; +} + +/*! + * @brief Disable the IWDT write access + * + * @param None + * + * @retval None + */ +void IWDT_DisableWriteAccess(void) +{ + IWDT->KEY_B.KEY = IWDT_WRITEACCESS_DISABLE; +} + +/*! + * @brief Set IWDT frequency divider values + * + * @param div: IWDT frequency divider values + * This parameter can be one of the following values: + * @arg IWDT_DIVIDER_4 : prescaler divider equal to 4 + * @arg IWDT_DIVIDER_8 : prescaler divider equal to 8 + * @arg IWDT_DIVIDER_16 : prescaler divider equal to 16 + * @arg IWDT_DIVIDER_32 : prescaler divider equal to 32 + * @arg IWDT_DIVIDER_64 : prescaler divider equal to 64 + * @arg IWDT_DIVIDER_128: prescaler divider equal to 128 + * @arg IWDT_DIVIDER_256: prescaler divider equal to 256 + * + * @retval None + */ +void IWDT_ConfigDivider(uint8_t div) +{ + IWDT->PSC = div; +} + +/*! + * @brief Read the specified IWDT flag + * + * @param flag: specifies the flag to read + * This parameter can be one of the following values: + * @arg IWDT_FLAG_PSCU : Watchdog Prescaler Factor Update flag + * @arg IWDT_FLAG_CNTU : Watchdog Counter Reload Value Update flag + * + * @retval status of IWDT_FLAG (SET or RESET) + * + * @note + */ +uint8_t IWDT_ReadStatusFlag(uint16_t flag) +{ + uint8_t bitStatus = RESET; + + if((IWDT->STS & flag) != (uint32_t)RESET) + { + bitStatus = SET; + } + else + { + bitStatus = RESET; + } + return bitStatus; +} + +/**@} end of group IWDT_Fuctions*/ +/**@} end of group IWDT_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c new file mode 100644 index 0000000000..92b925b937 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c @@ -0,0 +1,207 @@ +/*! + * @file apm32f10x_misc.c + * + * @brief This file provides all the miscellaneous firmware functions. + * Include NVIC,SystemTick and Power management. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_misc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup MISC_Driver MISC Driver + @{ +*/ + +/** @addtogroup MISC_Macros Macros + @{ +*/ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/**@} end of group I2C_Macros*/ + + +/** @addtogroup MISC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * + * @param priorityGroup : specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITY_GROUP_0 + * @arg NVIC_PRIORITY_GROUP_1 + * @arg NVIC_PRIORITY_GROUP_2 + * @arg NVIC_PRIORITY_GROUP_3 + * @arg NVIC_PRIORITY_GROUP_4 + * + * @retval None + */ +void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup; +} + +/*! + * @brief Enable NVIC request + * + * @param irq: the NVIC interrupt request, detailed in IRQn_Type + * For the complete APM32 Devices IRQ Channels list,please refer to apm32f10x.h file + * + * @param preemptionPriority: the pre-emption priority needed to set + * + * @param subPriority: the subpriority needed to set + * + * @retval None + */ +void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority) +{ + uint32_t tempPriority, tempPrePri, tempSubPri; + uint32_t priorityGrp; + + /** Get priority group */ + priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U; + + /** get pre-emption priority and subpriority */ + switch(priorityGrp) + { + case NVIC_PRIORITY_GROUP_0: + tempPrePri = 0; + tempSubPri = 4; + break; + + case NVIC_PRIORITY_GROUP_1: + tempPrePri = 1; + tempSubPri = 3; + break; + + case NVIC_PRIORITY_GROUP_2: + tempPrePri = 2; + tempSubPri = 2; + break; + + case NVIC_PRIORITY_GROUP_3: + tempPrePri = 3; + tempSubPri = 1; + break; + + case NVIC_PRIORITY_GROUP_4: + tempPrePri = 4; + tempSubPri = 0; + break; + + default: + NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0); + tempPrePri = 0; + tempSubPri = 4; + break; + } + + tempPrePri = 4 - tempPrePri; + tempSubPri = 4 - tempSubPri; + tempPriority = preemptionPriority << tempPrePri; + tempPriority |= subPriority & (0x0f >> tempSubPri); + tempPriority <<= 4; + NVIC->IP[irq] = (uint8_t)tempPriority; + + /* enable the selected IRQ */ + NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); +} + +/*! + * @brief Disable NVIC request + * + * @param irq: the NVIC interrupt request, detailed in IRQn_Type + * + * @retval None + */ +void NVIC_DisableIRQRequest(IRQn_Type irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU); +} + +/*! + * @brief Configs the vector table location and Offset. + * + * @param vectTab: specifies if the vector table is in RAM or FLASH memory + * This parameter can be one of the following values: + * @arg NVIC_VECT_TAB_RAM + * @arg NVIC_VECT_TAB_FLASH + * + * @param Offset Vector Table base offset field. This value must be a multiple of 0x200 + * + * @retval None + */ +void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset) +{ + SCB->VTOR = vectTab | (offset & (uint32_t)0x1FFFFF80); +} + +/*! + * @brief set the state of the low power mode + * + * @param lowPowerMode: the low power mode state + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * + * @retval None + */ +void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode) +{ + SCB->SCR |= lowPowerMode; +} + + +/*! + * @brief reset the state of the low power mode + * + * @param lowPowerMode: the low power mode state + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * + * @retval None + */ +void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode) +{ + SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode); +} + +/*! + * @brief Configures the SysTick clock source + * + * @param clkSource: specifies the SysTick clock source + * This parameter can be one of the following values: + * @arg SYSTICK_CLK_SOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLK_SOURCE_HCLK: AHB clock selected as SysTick clock source. + * + * @retval None + */ +void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource) +{ + if (clkSource == SYSTICK_CLK_SOURCE_HCLK) + { + SysTick->CTRL |= (uint32_t)BIT2; + } + else + { + SysTick->CTRL &= (uint32_t)(~BIT2); + } +} + +/**@} end of group MISC_Fuctions*/ +/**@} end of group MISC_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c new file mode 100644 index 0000000000..2398ebe0e4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c @@ -0,0 +1,249 @@ +/*! + * @file apm32f10x_pmu.c + * + * @brief This file provides all the PMU firmware functions. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_pmu.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup PMU_Driver PMU Driver + @{ +*/ + +/** @addtogroup PMU_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the PMU peripheral register. + * + * @param None + * + * @retval None + */ +void PMU_Reset(void) +{ + RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); + RCM_DisableAPB1PeriphClock(RCM_APB1_PERIPH_PMU); +} + +/*! + * @brief Enables access to the RTC and backup registers. + * + * @param None + * + * @retval None + */ +void PMU_EnableBackupAccess(void) +{ + PMU->CTRL_B.BPWEN = ENABLE ; +} + +/*! + * @brief Disables access to the RTC and backup registers. + * + * @param None + * + * @retval None + */ +void PMU_DisableBackupAccess(void) +{ + PMU->CTRL_B.BPWEN = DISABLE; +} + +/*! + * @brief Enables the Power Voltage Detector(PVD). + * + * @param None + * + * @retval None + */ +void PMU_EnablePVD(void) +{ + PMU->CTRL_B.PVDEN = ENABLE; +} + +/*! + * @brief Disables the Power Voltage Detector(PVD). + * + * @param None + * + * @retval None + */ +void PMU_DisablePVD(void) +{ + PMU->CTRL_B.PVDEN = DISABLE; +} + +/*! + * @brief Configure a voltage threshold detected by a power supply voltage detector (PVD). + * + * @param level£ºspecifies the PVD detection level + * This parameter can be one of the following values: + * @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V + * @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V + * @arg PMU_PVD_LEVEL_2V4 : Config PVD detection level to 2.4V + * @arg PMU_PVD_LEVEL_2V5 : Config PVD detection level to 2.5V + * @arg PMU_PVD_LEVEL_2V6 : Config PVD detection level to 2.6V + * @arg PMU_PVD_LEVEL_2V7 : Config PVD detection level to 2.7V + * @arg PMU_PVD_LEVEL_2V8 : Config PVD detection level to 2.8V + * @arg PMU_PVD_LEVEL_2V9 : Config PVD detection level to 2.9V + * + * @retval None + */ +void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level) +{ + + /* Clear PLS[7:5] bits */ + PMU->CTRL_B.PLSEL = 0x0000; + /* Store the new value */ + PMU->CTRL_B.PLSEL = level; +} + +/*! + * @brief Enables the WakeUp Pin functionality. + * + * @param None + * + * @retval None + */ +void PMU_EnableWakeUpPin(void) +{ + PMU->CSTS_B.WKUPCFG = ENABLE ; +} + +/*! + * @brief Diaables the WakeUp Pin functionality. + * + * @param None + * + * @retval None + */ +void PMU_DisableWakeUpPin(void) +{ + PMU->CSTS_B.WKUPCFG = DISABLE ; +} + +/*! + * @brief Enters STOP mode. + * + * @param regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PMU_REGULATOR_ON : STOP mode with regulator ON + * @arg PMU_REGULATOR_LOWPOWER: STOP mode with regulator in low power mode + * + * @param entry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PMU_STOP_ENTRY_WFI: Enter STOP mode with WFI instruction + * @arg PMU_STOP_ENTRY_WFE: Enter STOP mode with WFE instruction + * + * @retval None + */ +void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry) +{ + /** Clear PLS and LPSM bits */ + PMU->CTRL_B.PDDSCFG = 0x00; + PMU->CTRL_B.LPDSCFG = 0x00; + /** Set LPSM bit according to PWR_Regulator value */ + PMU->CTRL_B.PDDSCFG = regulator; + /** Select STOP mode entry*/ + if(entry == PMU_STOP_ENTRY_WFI) + { + /** Request Wait For Interrupt */ + __WFI(); + } else + { + /** Request Wait For Event */ + __WFE(); + } + + /** Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)0x04); + +} + +/*! + * @brief Enters STANDBY mode. + * + * @param None + * + * @retval None + */ +void PMU_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PMU->CTRL_B.WUFLGCLR = BIT_SET; + /* Select STANDBY mode */ + PMU->CTRL_B.PDDSCFG = BIT_SET; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= (uint8_t )0x04; +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); + +} + +/*! + * @brief Read the specified PWR flag is set or not. + * + * @param flag£ºReads the status of specifies the flag. + * This parameter can be one of the following values: + * @arg PMU_FLAG_WUE : Wake Up flag + * @arg PMU_FLAG_SB : StandBy flag + * @arg PMU_FLAG_PVDO: PVD Output flag + * + * @retval The new state of PMU_FLAG (SET or RESET). + */ +uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag) +{ + uint8_t BitStatus = BIT_RESET; + + if(flag == PMU_FLAG_WUE) + { + BitStatus = PMU->CSTS_B.WUEFLG; + } else if(flag == PMU_FLAG_SB) + { + BitStatus = PMU->CSTS_B.SBFLG; + } else if(flag == PMU_FLAG_PVDO) + { + BitStatus = PMU->CSTS_B.PVDOFLG; + } + return BitStatus; +} + +/*! + * @brief Clears the PWR's pending flags. + * + * @param flag£ºClears the status of specifies the flag. + * This parameter can be one of the following values: + * @arg PMU_FLAG_WUE : Wake Up flag + * @arg PMU_FLAG_SB : StandBy flag + * + * @retval None + */ +void PMU_ClearStatusFlag(PMU_FLAG_T flag) +{ + if(flag == PMU_FLAG_WUE) + { + PMU->CTRL_B.WUFLGCLR = BIT_SET; + } else if(flag == PMU_FLAG_SB) + { + PMU->CTRL_B.SBFLGCLR = BIT_SET; + } +} + +/**@} end of group PMU_Fuctions*/ +/**@} end of group PMU_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c new file mode 100644 index 0000000000..5706b95e1a --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c @@ -0,0 +1,594 @@ +/*! + * @file qpm32f10x_qspi.c + * + * @brief This file contains all the functions for the QSPI peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_qspi.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset QSPI peripheral registers to their default values + * + * @param None + * + * @retval None + */ +void QSPI_Reset(void) +{ + volatile uint32_t dummy = 0; + + QSPI->IOSW = QSPI_IOSW_RESET_VALUE; + QSPI->SSIEN = QSPI_SSIEN_RESET_VALUE; + QSPI->INTEN = QSPI_INTEN_RESET_VALUE; + dummy = QSPI->ICF; + QSPI->CTRL1 = QSPI_CTRL1_RESET_VALUE; + QSPI->CTRL2 = QSPI_CTRL2_RESET_VALUE; + QSPI->CTRL3 = QSPI_CTRL3_RESET_VALUE; + QSPI->SLAEN = QSPI_SLAEN_RESET_VALUE; + QSPI->BR = QSPI_BR_RESET_VALUE; + QSPI->TFL = QSPI_TFL_RESET_VALUE; + QSPI->RFL = QSPI_RFL_RESET_VALUE; + QSPI->TFTL = QSPI_TFTL_RESET_VALUE; + QSPI->RFTL = QSPI_RFTL_RESET_VALUE; + QSPI->STS = QSPI_STS_RESET_VALUE; + QSPI->RSD = QSPI_RSD_RESET_VALUE; +} + +/*! + * @brief Config the QSPI peripheral according to the specified parameters in the qspiConfig + * + * @param qspiConfig: Pointer to a QSPI_Config_T structure that contains the configuration information + * + * @retval None + */ +void QSPI_Config(QSPI_Config_T * qspiConfig) +{ + QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase; + QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity; + QSPI->CTRL1_B.FRF = qspiConfig->frameFormat; + QSPI->CTRL1_B.DFS = qspiConfig->dataFrameSize;; + QSPI->CTRL1_B.SSTEN = qspiConfig->selectSlaveToggle; + + QSPI->BR = qspiConfig->clockDiv; + +} + +/*! + * @brief Fills each qspiConfig member with its default value + * + * @param qspiConfig: Pointer to a QSPI_Config_T structure which will be initialized + * + * @retval None + */ +void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig) +{ + qspiConfig->clockPhase = QSPI_CLKPHA_2EDGE; + qspiConfig->clockPolarity = QSPI_CLKPOL_LOW; + qspiConfig->clockDiv = 0; + + qspiConfig->frameFormat = QSPI_FRF_STANDARD; + qspiConfig->dataFrameSize = QSPI_DFS_8BIT; + qspiConfig->selectSlaveToggle = QSPI_SST_DISABLE; +} + +/*! + * @brief Configs frame number + * + * @param num: Configs a 16bit frame number + * + * @retval None + */ +void QSPI_ConfigFrameNum(uint16_t num) +{ + QSPI->CTRL2_B.NDF = num; +} + +/*! + * @brief Configs data frame size + * + * @param dfs: Specifies the data frame size + * The parameter can be one of following values: + * @arg QSPI_DFS_4BIT : Specifies data frame size to 4bit + * @arg QSPI_DFS_5BIT : Specifies data frame size to 5bit + * @arg QSPI_DFS_6BIT : Specifies data frame size to 6bit + * @arg QSPI_DFS_7BIT : Specifies data frame size to 7bit + * @arg QSPI_DFS_8BIT : Specifies data frame size to 8bit + * @arg QSPI_DFS_9BIT : Specifies data frame size to 9bit + * @arg QSPI_DFS_10BIT : Specifies data frame size to 10bit + * @arg QSPI_DFS_11BIT : Specifies data frame size to 11bit + * @arg QSPI_DFS_12BIT : Specifies data frame size to 12bit + * @arg QSPI_DFS_13BIT : Specifies data frame size to 13bit + * @arg QSPI_DFS_14BIT : Specifies data frame size to 14bit + * @arg QSPI_DFS_15BIT : Specifies data frame size to 15bit + * @arg QSPI_DFS_16BIT : Specifies data frame size to 16bit + * @arg QSPI_DFS_17BIT : Specifies data frame size to 17bit + * @arg QSPI_DFS_18BIT : Specifies data frame size to 18bit + * @arg QSPI_DFS_19BIT : Specifies data frame size to 19bit + * @arg QSPI_DFS_20BIT : Specifies data frame size to 20bit + * @arg QSPI_DFS_21BIT : Specifies data frame size to 21bit + * @arg QSPI_DFS_22BIT : Specifies data frame size to 22bit + * @arg QSPI_DFS_23BIT : Specifies data frame size to 23bit + * @arg QSPI_DFS_24BIT : Specifies data frame size to 24bit + * @arg QSPI_DFS_25BIT : Specifies data frame size to 25bit + * @arg QSPI_DFS_26BIT : Specifies data frame size to 26bit + * @arg QSPI_DFS_27BIT : Specifies data frame size to 27bit + * @arg QSPI_DFS_28BIT : Specifies data frame size to 28bit + * @arg QSPI_DFS_29BIT : Specifies data frame size to 29bit + * @arg QSPI_DFS_30BIT : Specifies data frame size to 30bit + * @arg QSPI_DFS_31BIT : Specifies data frame size to 31bit + * @arg QSPI_DFS_32BIT : Specifies data frame size to 32bit + * + * @retval None + */ +void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs) +{ + QSPI->CTRL1_B.DFS = dfs; +} + +/*! + * @brief Configs frame format + * + * @param frameFormat + * + * @retval None + */ +void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat) +{ + QSPI->CTRL1_B.FRF = frameFormat; +} + +/*! + * @brief Enable QSPI + * + * @param None + * + * @retval None + */ +void QSPI_Enable(void) +{ + QSPI->SSIEN_B.EN = BIT_SET; +} + +/*! + * @brief Disable QSPI + * + * @param None + * + * @retval None + */ +void QSPI_Disable(void) +{ + QSPI->SSIEN_B.EN = BIT_RESET; +} + +/*! + * @brief Read Tx FIFO number of data + * + * @param None + * + * @retval None + */ +uint8_t QSPI_ReadTxFifoDataNum(void) +{ + return (uint8_t)QSPI->TFL_B.TFL; +} + +/*! + * @brief Read Rx FIFO number of data + * + * @param None + * + * @retval Returns Rx FIFO number of data + */ +uint8_t QSPI_ReadRxFifoDataNum(void) +{ + return (uint8_t)QSPI->RFL_B.RFL; +} + +/*! + * @brief Configs rx FIFO threshold + * + * @param threshold: Speicifes rx FIFO threshold with a 3bit value + * + * @retval None + */ +void QSPI_ConfigRxFifoThreshold(uint8_t threshold) +{ + QSPI->RFTL_B.RFT = threshold; +} + +/*! + * @brief Congfigs Tx FIFO threshold + * + * @param threshold: Speicifes Tx FIFO threshold with a 3bit value + * + * @retval None + */ +void QSPI_ConfigTxFifoThreshold(uint8_t threshold) +{ + QSPI->TFTL_B.TFTH = threshold; +} + +/*! + * @brief Congfigs Tx FIFO empty threshold + * + * @param threshold: Speicifes Tx FIFO empty threshold with a 3bit value + * + * @retval None + */ +void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold) +{ + QSPI->TFTL_B.TFT = threshold; +} + +/*! + * @brief Configs RX sample edge + * + * @param rse: Specifies the sample edge + * The parameter can be one of following values: + * @arg QSPI_RSE_RISING : rising edge sample + * @arg QSPI_RSE_FALLING: falling edge sample + * + * @retval None + */ +void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse) +{ + QSPI->RSD_B.RSE = rse; +} + +/*! + * @brief Set RX sample delay + * + * @param delay: Specifies the sample delay with a 8-bit value + * + * @retval None + */ +void QSPI_ConfigRxSampleDelay(uint8_t delay) +{ + QSPI->RSD_B.RSD = delay; +} + +/*! + * @brief Clock stretch enable + * + * @param None + * + * @retval None + */ +void QSPI_EnableClockStretch(void) +{ + QSPI->CTRL3_B.CSEN = BIT_SET; +} + +/*! + * @brief Clock stretch disable + * + * @param None + * + * @retval None + */ +void QSPI_DisableClockStretch(void) +{ + QSPI->CTRL3_B.CSEN = BIT_RESET; +} + +/*! + * @brief Configs instruction length + * + * @param len: Specifies the length of instruction + * The parameter can be one of following values: + * @arg QSPI_INST_LEN_0 : no instruction + * @arg QSPI_INST_LEN_4BIT : 4-bit instruction + * @arg QSPI_INST_LEN_8BIT : 8-bit instruction + * @arg QSPI_INST_LEN_16BIT : 16-bit instruction + * + * @retval None + */ +void QSPI_ConfigInstLen(QSPI_INST_LEN_T len) +{ + QSPI->CTRL3_B.INSLEN = len; +} + +/*! + * @brief Configs address length + * + * @param len: Specifies the address length + * The parameter can be one of following values: + * @arg QSPI_ADDR_LEN_0 : no address + * @arg QSPI_ADDR_LEN_4BIT : 4-bit address length + * @arg QSPI_ADDR_LEN_8BIT, : 8-bit address length + * @arg QSPI_ADDR_LEN_12BIT : 12-bit address length + * @arg QSPI_ADDR_LEN_16BIT : 16-bit address length + * @arg QSPI_ADDR_LEN_20BIT : 20-bit address length + * @arg QSPI_ADDR_LEN_24BIT : 24-bit address length + * @arg QSPI_ADDR_LEN_28BIT : 28-bit address length + * @arg QSPI_ADDR_LEN_32BIT : 32-bit address length + * @arg QSPI_ADDR_LEN_36BIT : 36-bit address length + * @arg QSPI_ADDR_LEN_40BIT : 40-bit address length + * @arg QSPI_ADDR_LEN_44BIT : 44-bit address length + * @arg QSPI_ADDR_LEN_48BIT : 48-bit address length + * @arg QSPI_ADDR_LEN_52BIT : 52-bit address length + * @arg QSPI_ADDR_LEN_56BIT : 56-bit address length + * @arg QSPI_ADDR_LEN_60BIT : 60-bit address length + * + * @retval None + */ +void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len) +{ + QSPI->CTRL3_B.ADDRLEN = len; +} + +/*! + * @brief Configs instruction and address type + * + * @param type: Specifies the instruction and address type + * The parameter can be one of following values: + * @arg QSPI_INST_ADDR_TYPE_STANDARD : Tx instruction in standard SPI mode, + * Tx address in standard SPI mode + * @arg QSPI_INST_TYPE_STANDARD : Tx instruction in standard SPI mode, + * Tx address in mode of SPI_FRF + * @arg QSPI_INST_ADDR_TYPE_FRF : Tx instruction in mode of SPI_FRF, + * Tx address in mode of SPI_FRF + * + * @retval None + */ +void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type) +{ + QSPI->CTRL3_B.IAT = type; +} + +/*! + * @brief Configs wait cycle number + * + * @param cycle: Specifies the wait cycle number with a 5-bit value + * + * @retval None + */ +void QSPI_ConfigWaitCycle(uint8_t cycle) +{ + QSPI->CTRL3_B.WAITCYC = cycle; +} + +/*! + * @brief Open QSPI GPIO + * + * @param None + * + * @retval None + */ +void QSPI_OpenIO(void) +{ + QSPI->IOSW_B.IOSW = BIT_SET; +} + +/*! + * @brief Close QSPI GPIO + * + * @param None + * + * @retval None + */ +void QSPI_CloseIO(void) +{ + QSPI->IOSW_B.IOSW = BIT_RESET; +} + +/*! + * @brief Set transmission mode + * + * @param mode: Specifies the transmission mode + * The parameter can be one of following values: + * @arg QSPI_TRANS_MODE_TX_RX : TX and RX mode + * @arg QSPI_TRANS_MODE_TX : TX mode only + * @arg QSPI_TRANS_MODE_RX : RX mode only + * @arg QSPI_TRANS_MODE_EEPROM_READ : EEPROM read mode + * + * @retval None + */ +void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode) +{ + QSPI->CTRL1_B.TXMODE = mode; +} + +/*! + * @brief Transmit data + * + * @param data: Data to be transmited + * + * @retval None + */ +void QSPI_TxData(uint32_t data) +{ + QSPI->DATA = data; +} + +/*! + * @brief Returns the most recent received data + * + * @param None + * + * @retval The received data + */ +uint32_t QSPI_RxData(void) +{ + return (uint32_t)QSPI->DATA; +} + +/*! + * @brief Enable Slave + * + * @param None + * + * @retval None + */ +void QSPI_EnableSlave(void) +{ + QSPI->SLAEN_B.SLAEN = BIT_SET; +} + +/*! + * @brief Disable slave + * + * @param None + * + * @retval None + */ +void QSPI_DisableSlave(void) +{ + QSPI->SLAEN_B.SLAEN = BIT_RESET; +} + +/*! + * @brief Enable the specified QSPI interrupts + * + * @param interrupt: Specifies the QSPI interrupt sources + * The parameter can be combination of following values: + * @arg QSPI_INT_TFE: TX FIFO empty interrupt + * @arg QSPI_INT_TFO: TX FIFO overflow interrupt + * @arg QSPI_INT_RFU: RX FIFO underflow interrupt + * @arg QSPI_INT_RFO: RX FIFO overflow interrupt + * @arg QSPI_INT_RFF: RX FIFO full interrupt + * @arg QSPI_INT_MST: Master interrupt + * + * @retval None + */ +void QSPI_EnableInterrupt(uint32_t interrupt) +{ + QSPI->INTEN |= interrupt; +} + +/*! + * @brief Disable the specified QSPI interrupts + * + * @param interrupt: Specifies the QSPI interrupt sources + * The parameter can be combination of following values: + * @arg QSPI_INT_TFE: TX FIFO empty interrupt + * @arg QSPI_INT_TFO: TX FIFO overflow interrupt + * @arg QSPI_INT_RFU: RX FIFO underflow interrupt + * @arg QSPI_INT_RFO: RX FIFO overflow interrupt + * @arg QSPI_INT_RFF: RX FIFO full interrupt + * @arg QSPI_INT_MST: Master interrupt + * + * @retval None + */ +void QSPI_DisableInterrupt(uint32_t interrupt) +{ + QSPI->INTEN &= (uint32_t)~interrupt; +} + +/*! + * @brief Read specified QSPI flag + * + * @param flag: Specifies the flag to be checked + * The parameter can be one of following values: + * @arg QSPI_FLAG_BUSY: Busy flag + * @arg QSPI_FLAG_TFNF: TX FIFO not full flag + * @arg QSPI_FLAG_TFE: TX FIFO empty flag + * @arg QSPI_FLAG_RFNE: RX FIFO not empty flag + * @arg QSPI_FLAG_RFF: RX FIFO full flag + * @arg QSPI_FLAG_DCE: Data collision error + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag) +{ + uint8_t ret = RESET; + + ret = QSPI->STS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Clear specified QSPI flag + * + * @param None + * + * @retval None + * + * @note This funtion only clear Data collision error flag(QSPI_FLAG_DCE) + */ +void QSPI_ClearStatusFlag(void) +{ + volatile uint32_t dummy = 0; + + dummy = QSPI->STS; +} + +/*! + * @brief Read specified QSPI interrupt flag + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg QSPI_INT_FLAG_TFE: TX FIFO empty interrupt flag + * @arg QSPI_INT_FLAG_TFO: TX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_RFU: RX FIFO underflow interrupt flag + * @arg QSPI_INT_FLAG_RFO: RX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_RFF: RX FIFO full interrupt flag + * @arg QSPI_INT_FLAG_MST: Master interrupt flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag) +{ + uint8_t ret = RESET; + + ret = QSPI->ISTS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Clear specified QSPI interrupt flag + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg QSPI_INT_FLAG_TFO: TX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_RFU: RX FIFO underflow interrupt flag + * @arg QSPI_INT_FLAG_RFO: RX FIFO overflow interrupt flag + * @arg QSPI_INT_FLAG_MST: Master interrupt flag + * + * @retval None + */ +void QSPI_ClearIntFlag(uint32_t flag) +{ + volatile uint32_t dummy = 0; + + if(flag & QSPI_INT_FLAG_TFO) + { + dummy = QSPI->TFOIC; + } + else if(flag & QSPI_INT_FLAG_RFO) + { + dummy = QSPI->RFOIC; + } + else if(flag & QSPI_INT_FLAG_RFU) + { + dummy = QSPI->RFUIC; + } + else if(flag & QSPI_INT_FLAG_MST) + { + dummy = QSPI->MIC; + } +} + +/**@} end of group QSPI_Fuctions*/ +/**@} end of group QSPI_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c new file mode 100644 index 0000000000..71151193e2 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c @@ -0,0 +1,1078 @@ +/*! + * @file apm32f10x_rcm.c + * + * @brief This file provides all the RCM firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RCM_Driver RCM Driver + @{ +*/ + +/** @addtogroup RCM_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Resets the clock configuration to the default state + * + * @param None + * + * @retval None + */ +void RCM_Reset(void) +{ + /** Open HSI clock */ + RCM->CTRL_B.HSIEN = BIT_SET; + /** Config HSI to system clock and Reset AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ + RCM->CFG &= (uint32_t)0xF8FF0000; + /** Reset HSEEN, CSSEN and PLLEN bits */ + RCM->CTRL &= (uint32_t)0xFEF6FFFF; + /** Reset HSEBCFG bit */ + RCM->CTRL_B.HSEBCFG = BIT_RESET; + /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ + RCM->CFG &= (uint32_t)0xFF00FFFF; + /** Disable all interrupts and clear pending bits */ + RCM->INT = 0x009F0000; +} + +/*! + * @brief Configs the HSE oscillator + * + * @param state: state of the HSE + * This parameter can be one of the following values: + * @arg RCM_HSE_CLOSE: Turn off the HSE oscillator + * @arg RCM_HSE_OPEN: Turn on the HSE oscillator + * @arg RCM_HSE_BYPASS: HSE oscillator bypassed with external clock + * + * @retval None + * + * @note When HSE is not used directly or through the PLL as system clock, it can be stopped. + */ +void RCM_ConfigHSE(RCM_HSE_T state) +{ + /** Reset HSEEN bit */ + RCM->CTRL_B.HSEEN = BIT_RESET; + + /** Reset HSEBCFG bit */ + RCM->CTRL_B.HSEBCFG = BIT_RESET; + + if (state == RCM_HSE_OPEN) + { + RCM->CTRL_B.HSEEN = BIT_SET; + } + else if (state == RCM_HSE_BYPASS) + { + RCM->CTRL_B.HSEBCFG = BIT_SET; + RCM->CTRL_B.HSEEN = BIT_SET; + } +} + +/*! + * @brief Waits for HSE to be ready + * + * @param None + * + * @retval SUCCESS: HSE oscillator is ready + * ERROR : HSE oscillator is not ready + */ +uint8_t RCM_WaitHSEReady(void) +{ + __IO uint32_t cnt; + + for (cnt = 0; cnt < HSE_STARTUP_TIMEOUT; cnt++) + { + if (RCM->CTRL_B.HSERDYFLG == BIT_SET) + { + return SUCCESS; + } + } + + return ERROR; +} + +/*! + * @brief Set HSI trimming value + * + * @param HSITrim: HSI trimming value + * This parameter must be a number between 0 and 0x1F. + * + * @retval None + */ +void RCM_SetHSITrim(uint8_t HSITrim) +{ + RCM->CTRL_B.HSITRIM = HSITrim; +} + +/*! + * @brief Enable the HSI + * + * @param None + * + * @retval None + */ +void RCM_EnableHSI(void) +{ + RCM->CTRL_B.HSIEN = BIT_SET; +} + +/*! + * @brief Disable the HSI + * + * @param None + * + * @retval None + * + * @note When HSI is not used directly or through the PLL as system clock, it can be stopped. + */ + +void RCM_DisableHSI(void) +{ + RCM->CTRL_B.HSIEN = BIT_RESET; +} + +/*! + * @brief Configures the External Low Speed oscillator (LSE) + * + * @param state : Specifies the new state of the LSE + * + * @retval None + * + * @note + */ +void RCM_ConfigLSE(RCM_LSE_T state) +{ + RCM->BDCTRL_B.LSEEN = BIT_RESET; + RCM->BDCTRL_B.LSEBCFG = BIT_RESET; + + if (state == RCM_LSE_OPEN) + { + RCM->BDCTRL_B.LSEEN = BIT_SET; + } + else if (state == RCM_LSE_BYPASS) + { + RCM->BDCTRL_B.LSEBCFG = BIT_SET; + RCM->BDCTRL_B.LSEEN = BIT_SET; + } +} + +/*! + * @brief Enables the Internal Low Speed oscillator (LSI) + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_EnableLSI(void) +{ + RCM->CSTS_B.LSIEN = BIT_SET; +} + +/*! + * @brief Disables the Internal Low Speed oscillator (LSI) + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_DisableLSI(void) +{ + RCM->CSTS_B.LSIEN = BIT_RESET; +} + +/*! + * @brief Configs the PLL clock source and multiplication factor + * + * @param pllSelect: PLL entry clock source select + * This parameter can be one of the following values: + * @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source + * @arg RCM_PLLSEL_HSE: HSE clock selected as PLL clock source + * @arg RCM_PLLSEL_HSE_DIV2: HSE clock divided by 2 selected as PLL clock source + * + * @param pllMf: PLL multiplication factor + * This parameter can be RCM_PLLMF_x where x can be a value from 2 to 16. + * + * @retval None + * + * @note PLL should be disabled while use this function. + */ +void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf) +{ + RCM->CFG_B.PLLMULCFG = pllMf; + RCM->CFG_B.PLLSRCSEL = pllSelect & 0x01; + RCM->CFG_B.PLLHSEPSC = (pllSelect >> 1) & 0x01; +} + +/*! + * @brief Enables the PLL + * + * @param None + * + * @retval None + */ +void RCM_EnablePLL(void) +{ + RCM->CTRL_B.PLLEN = BIT_SET; +} + +/*! +* @brief Disable the PLL +* +* @param None +* +* @retval None +* +* @note When PLL is not used as system clock, it can be stopped. +*/ +void RCM_DisablePLL(void) +{ + RCM->CTRL_B.PLLEN = BIT_RESET; +} + +/*! + * @brief Enable the Clock Security System + * + * @param None + * + * @retval None + */ +void RCM_EnableCSS(void) +{ + RCM->CTRL_B.CSSEN = BIT_SET; +} + +/*! + * @brief Disable the Clock Security System + * + * @param None + * + * @retval None + */ +void RCM_DisableCSS(void) +{ + RCM->CTRL_B.CSSEN = BIT_RESET; +} + +/*! + * @brief Selects the MCO pin clock ouput source + * + * @param mcoClock: specifies the clock source to output + * This parameter can be one of the following values: + * @arg RCM_MCOCLK_NO_CLOCK : No clock selected. + * @arg RCM_MCOCLK_SYSCLK : HSI14 oscillator clock selected. + * @arg RCM_MCOCLK_HSI : LSI oscillator clock selected. + * @arg RCM_MCOCLK_HSE : LSE oscillator clock selected. + * @arg RCM_MCOCLK_PLLCLK_DIV_2 : System clock selected. + * + * @retval None + * + * @note + */ +void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock) +{ + RCM->CFG_B.MCOSEL = mcoClock; +} + +/*! + * @brief Configures the system clock source + * + * @param sysClkSelect: specifies the clock source used as system clock + * This parameter can be one of the following values: + * @arg RCM_SYSCLK_SEL_HSI: HSI is selected as system clock source + * @arg RCM_SYSCLK_SEL_HSE: HSE is selected as system clock source + * @arg RCM_SYSCLK_SEL_PLL: PLL is selected as system clock source + * + * @retva None + */ +void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect) +{ + RCM->CFG_B.SCLKSW = sysClkSelect; +} + +/*! + * @brief Returns the clock source which is used as system clock + * + * @param None + * + * @retval The clock source used as system clock + */ +RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void) +{ + RCM_SYSCLK_SEL_T sysClock; + + sysClock = (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSWSTS; + + return sysClock; +} + +/*! + * @brief Configs the AHB clock prescaler. + * + * @param AHBDiv : Specifies the AHB clock prescaler from the system clock. + * This parameter can be one of the following values: + * @arg RCM_AHB_DIV_1 : HCLK = SYSCLK + * @arg RCM_AHB_DIV_2 : HCLK = SYSCLK / 2 + * @arg RCM_AHB_DIV_4 : HCLK = SYSCLK / 4 + * @arg RCM_AHB_DIV_8 : HCLK = SYSCLK / 8 + * @arg RCM_AHB_DIV_16 : HCLK = SYSCLK / 16 + * @arg RCM_AHB_DIV_64 : HCLK = SYSCLK / 64 + * @arg RCM_AHB_DIV_128 : HCLK = SYSCLK / 128 + * @arg RCM_AHB_DIV_256 : HCLK = SYSCLK / 256 + * @arg RCM_AHB_DIV_512 : HCLK = SYSCLK / 512 + * + * @retval None + * + * @note + */ +void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv) +{ + RCM->CFG_B.AHBPSC = AHBDiv; +} + +/*! + * @brief Configs the APB1 clock prescaler. + * + * @param APB1Div: Specifies the APB1 clock prescaler from the AHB clock. + * This parameter can be one of the following values: + * @arg RCM_APB_DIV_1 : PCLK1 = HCLK + * @arg RCM_APB_DIV_2 : PCLK1 = HCLK / 2 + * @arg RCM_APB_DIV_4 : PCLK1 = HCLK / 4 + * @arg RCM_APB_DIV_8 : PCLK1 = HCLK / 8 + * @arg RCM_APB_DIV_16 : PCLK1 = HCLK / 16 + * + * @retval None + */ +void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div) +{ + RCM->CFG_B.APB1PSC = APB1Div; +} + +/*! + * @brief Configs the APB2 clock prescaler + * + * @param APB2Div: Specifies the APB2 clock prescaler from the AHB clock. + * This parameter can be one of the following values: + * @arg RCM_APB_DIV_1 : PCLK2 = HCLK + * @arg RCM_APB_DIV_2 : PCLK2 = HCLK / 2 + * @arg RCM_APB_DIV_4 : PCLK2 = HCLK / 4 + * @arg RCM_APB_DIV_8 : PCLK2 = HCLK / 8 + * @arg RCM_APB_DIV_16 : PCLK2 = HCLK / 16 + * + * @retval None + */ +void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div) +{ + RCM->CFG_B.APB2PSC = APB2Div; +} + +/*! + * @brief Configs the USB clock prescaler + * + * @param USBDiv: Specifies the USB clock prescaler from the PLL clock. + * This parameter can be one of the following values: + * @arg RCM_USB_DIV_1_5 : USBCLK = PLL clock /1.5 + * @arg RCM_USB_DIV_1 : USBCLK = PLL clock + * @arg RCM_USB_DIV_2 : USBCLK = PLL clock / 2 + * @arg RCM_USB_DIV_2_5 : USBCLK = PLL clock / 2.5 (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv) +{ + RCM->CFG_B.USBDPSC = USBDiv; +} + +/*! + * @brief Configs the FPU clock prescaler + * + * @param FPUDiv: Specifies the FPU clock prescaler from the AHB clock. + * This parameter can be one of the following values: + * @arg RCM_FPU_DIV_1 : FPUCLK = HCLK + * @arg RCM_FPU_DIV_2 : FPUCLK = HCLK /2 + * + * @retval None + */ +void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv) +{ + RCM->CFG_B.FPUPSC = FPUDiv; +} + +/*! + * @brief Configs the ADC clock prescaler + * + * @param ADCDiv : Specifies the ADC clock prescaler from the APB2 clock. + * This parameter can be one of the following values: + * @arg RCM_PCLK2_DIV_2: ADCCLK = PCLK2 / 2 + * @arg RCM_PCLK2_DIV_4: ADCCLK = PCLK2 / 4 + * @arg RCM_PCLK2_DIV_6: ADCCLK = PCLK2 / 6 + * @arg RCM_PCLK2_DIV_8: ADCCLK = PCLK2 / 8 + * + * @retval None + */ +void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv) +{ + RCM->CFG_B.ADCPSC = ADCDiv; +} + +/*! + * @brief Configures the RTC clock source + * + * @param rtcClkSelect : specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCM_RTCCLK_LSE : RTCCLK = LSE clock + * @arg RCM_RTCCLK_LSI : RTCCLK = LSI clock + * @arg RCM_RTCCLK_HSE_DIV_128: RTCCLK = HSE clock / 128 + * + * @retval None + * + * @note Once the RTC clock is configed it can't be changed unless reset the Backup domain. + */ +void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect) +{ + RCM->BDCTRL_B.RTCSRCSEL = rtcClkSelect; +} + +/*! + * @brief Enables the RTC clock + * + * @param None + * + * @retval None + */ +void RCM_EnableRTCCLK(void) +{ + RCM->BDCTRL_B.RTCCLKEN = BIT_SET; +} + +/*! + * @brief Disables the RTC clock + * + * @param None + * + * @retval None + */ +void RCM_DisableRTCCLK(void) +{ + RCM->BDCTRL_B.RTCCLKEN = BIT_RESET; +} + +/*! + * @brief Reads the frequency of SYSCLK + * + * @param None + * + * @retval Return the frequency of SYSCLK + */ +uint32_t RCM_ReadSYSCLKFreq(void) +{ + uint32_t sysClock, pllMull, pllSource; + + /** get sys clock */ + sysClock = RCM->CFG_B.SCLKSW; + + switch (sysClock) + { + /** sys clock is HSI */ + case RCM_SYSCLK_SEL_HSI: + sysClock = HSI_VALUE; + break; + + /** sys clock is HSE */ + case RCM_SYSCLK_SEL_HSE: + sysClock = HSE_VALUE; + break; + + /** sys clock is PLL */ + case RCM_SYSCLK_SEL_PLL: + pllMull = RCM->CFG_B.PLLMULCFG + 2; + pllSource = RCM->CFG_B.PLLSRCSEL; + + /** PLL entry clock source is HSE */ + if (pllSource == BIT_SET) + { + sysClock = HSE_VALUE * pllMull; + + /** HSE clock divided by 2 */ + if (pllSource == RCM->CFG_B.PLLHSEPSC) + { + sysClock >>= 1; + } + } + /** PLL entry clock source is HSI/2 */ + else + { + sysClock = (HSI_VALUE >> 1) * pllMull; + } + + break; + + default: + sysClock = HSI_VALUE; + break; + } + + return sysClock; +} + +/*! + * @brief Reads the frequency of HCLK(AHB) + * + * @param None + * + * @retval Return the frequency of HCLK + */ +uint32_t RCM_ReadHCLKFreq(void) +{ + uint32_t divider; + uint32_t sysClk, hclk; + uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sysClk = RCM_ReadSYSCLKFreq(); + divider = AHBPrescTable[RCM->CFG_B.AHBPSC]; + hclk = sysClk >> divider; + + return hclk; +} + +/*! + * @brief Reads the frequency of PCLK1 And PCLK2 + * + * @param PCLK1 : Return the frequency of PCLK1 + * + * @param PCLK1 : Return the frequency of PCLK2 + * + * @retval None + */ +void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2) +{ + uint32_t hclk, divider; + uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + hclk = RCM_ReadHCLKFreq(); + + if (PCLK1) + { + divider = APBPrescTable[RCM->CFG_B.APB1PSC]; + *PCLK1 = hclk >> divider; + } + + if (PCLK2) + { + divider = APBPrescTable[RCM->CFG_B.APB2PSC]; + *PCLK2 = hclk >> divider; + } +} + +/*! + * @brief Reads the frequency of ADCCLK + * + * @param None + * + * @retval Return the frequency of ADCCLK + */ +uint32_t RCM_ReadADCCLKFreq(void) +{ + uint32_t adcClk, pclk2, divider; + uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + + RCM_ReadPCLKFreq(NULL, &pclk2); + + /** Get ADC CLK */ + divider = ADCPrescTable[RCM->CFG_B.ADCPSC]; + adcClk = pclk2 / divider; + + return adcClk; +} + +/*! + * @brief Enables AHB peripheral clock. + * + * @param AHBPeriph : Enable the specifies clock of AHB peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_DMA1 : Enable DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2 : Enable DMA2 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SRAM : Enable SRAM clock + * @arg RCM_AHB_PERIPH_FPU : Enable FPU clock + * @arg RCM_AHB_PERIPH_FMC : Enable FMC clock + * @arg RCM_AHB_PERIPH_QSPI : Enable QSPI clock + * @arg RCM_AHB_PERIPH_CRC : Enable CRC clock + * @arg RCM_AHB_PERIPH_EMMC : Enable EMMC clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SDIO : Enable SDIO clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph) +{ + RCM->AHBCLKEN |= AHBPeriph; +} + +/*! + * @brief Disable AHB peripheral clock. + * + * @param AHBPeriph : Disable the specifies clock of AHB peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_AHB_PERIPH_DMA1 : Disable DMA1 clock + * @arg RCM_AHB_PERIPH_DMA2 : Disable DMA2 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SRAM : Disable SRAM clock + * @arg RCM_AHB_PERIPH_FPU : Disable FPU clock + * @arg RCM_AHB_PERIPH_FMC : Disable FMC clock + * @arg RCM_AHB_PERIPH_QSPI : Disable QSPI clock + * @arg RCM_AHB_PERIPH_CRC : Disable CRC clock + * @arg RCM_AHB_PERIPH_EMMC : Disable EMMC clock (Only for High-density devices for APM32F103xx) + * @arg RCM_AHB_PERIPH_SDIO : Disable SDIO clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph) +{ + RCM->AHBCLKEN &= (uint32_t)~AHBPeriph; +} + +/*! + * @brief Enable the High Speed APB (APB2) peripheral clock + * + * @param APB2Periph : Enable specifies clock of the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Enable AFIO clock + * @arg RCM_APB2_PERIPH_GPIOA : Enable GPIOA clock + * @arg RCM_APB2_PERIPH_GPIOB : Enable GPIOB clock + * @arg RCM_APB2_PERIPH_GPIOC : Enable GPIOC clock + * @arg RCM_APB2_PERIPH_GPIOD : Enable GPIOD clock + * @arg RCM_APB2_PERIPH_GPIOE : Enable GPIOE clock + * @arg RCM_APB2_PERIPH_GPIOF : Enable GPIOF clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Enable GPIOG clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Enable ADC1 clock + * @arg RCM_APB2_PERIPH_ADC2 : Enable ADC2 clock + * @arg RCM_APB2_PERIPH_TMR1 : Enable TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1 : Enable SPI1 clock + * @arg RCM_APB2_PERIPH_TMR8 : Enable TMR8 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Enable USART1 clock + * @arg RCM_APB2_PERIPH_ADC3 : Enable ADC3 clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph) +{ + RCM->APB2CLKEN |= APB2Periph; +} + +/*! + * @brief Disable the High Speed APB (APB2) peripheral clock + * + * @param APB2Periph : Disable specifies clock of the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Disable AFIO clock + * @arg RCM_APB2_PERIPH_GPIOA : Disable GPIOA clock + * @arg RCM_APB2_PERIPH_GPIOB : Disable GPIOB clock + * @arg RCM_APB2_PERIPH_GPIOC : Disable GPIOC clock + * @arg RCM_APB2_PERIPH_GPIOD : Disable GPIOD clock + * @arg RCM_APB2_PERIPH_GPIOE : Disable GPIOE clock + * @arg RCM_APB2_PERIPH_GPIOF : Disable GPIOF clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Disable GPIOG clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Disable ADC1 clock + * @arg RCM_APB2_PERIPH_ADC2 : Disable ADC2 clock + * @arg RCM_APB2_PERIPH_TMR1 : Disable TMR1 clock + * @arg RCM_APB2_PERIPH_SPI1 : Disable SPI1 clock + * @arg RCM_APB2_PERIPH_TMR8 : Disable TMR8 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Disable USART1 clock + * @arg RCM_APB2_PERIPH_ADC3 : Disable ADC3 clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph) +{ + RCM->APB2CLKEN &= (uint32_t)~APB2Periph; +} + +/*! + * @brief Enable the Low Speed APB (APB1) peripheral clock + * + * @param APB1Periph : Enable specifies clock of the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 clock + * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 clock + * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 clock + * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT clock + * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 clock + * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 clock + * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 clock + * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 clock + * @arg RCM_APB1_PERIPH_USB : Enable USB clock + * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 clock + * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 clock (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Enable BAKR clock + * @arg RCM_APB1_PERIPH_PMU : Enable PMU clock + * @arg RCM_APB1_PERIPH_DAC : Enable DAC clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph) +{ + RCM->APB1CLKEN |= APB1Periph; +} + +/*! + * @brief Disable the Low Speed APB (APB1) peripheral clock + * + * @param APB1Periph : Disable specifies clock of the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 clock + * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 clock + * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 clock + * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT clock + * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 clock + * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 clock + * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 clock + * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 clock (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 clock + * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 clock + * @arg RCM_APB1_PERIPH_USB : Disable USB clock + * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 clock + * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 clock (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Disable BAKR clock + * @arg RCM_APB1_PERIPH_PMU : Disable PMU clock + * @arg RCM_APB1_PERIPH_DAC : Disable DAC clock (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph) +{ + RCM->APB1CLKEN &= (uint32_t)~APB1Periph; +} + +/*! + * @brief Enable High Speed APB (APB2) peripheral reset + * + * @param APB2Periph : Enable specifies APB2 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Enable AFIO reset + * @arg RCM_APB2_PERIPH_GPIOA : Enable GPIOA reset + * @arg RCM_APB2_PERIPH_GPIOB : Enable GPIOB reset + * @arg RCM_APB2_PERIPH_GPIOC : Enable GPIOC reset + * @arg RCM_APB2_PERIPH_GPIOD : Enable GPIOD reset + * @arg RCM_APB2_PERIPH_GPIOE : Enable GPIOE reset + * @arg RCM_APB2_PERIPH_GPIOF : Enable GPIOF reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Enable GPIOG reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Enable ADC1 reset + * @arg RCM_APB2_PERIPH_ADC2 : Enable ADC2 reset + * @arg RCM_APB2_PERIPH_TMR1 : Enable TMR1 reset + * @arg RCM_APB2_PERIPH_SPI1 : Enable SPI1 reset + * @arg RCM_APB2_PERIPH_TMR8 : Enable TMR8 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Enable USART1 reset + * @arg RCM_APB2_PERIPH_ADC3 : Enable ADC3 reset (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph) +{ + RCM->APB2RST |= APB2Periph; +} + +/*! + * @brief Disable High Speed APB (APB2) peripheral reset + * + * @param APB2Periph : Disable specifies APB2 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB2_PERIPH_AFIO : Disable AFIO reset + * @arg RCM_APB2_PERIPH_GPIOA : Disable GPIOA reset + * @arg RCM_APB2_PERIPH_GPIOB : Disable GPIOB reset + * @arg RCM_APB2_PERIPH_GPIOC : Disable GPIOC reset + * @arg RCM_APB2_PERIPH_GPIOD : Disable GPIOD reset + * @arg RCM_APB2_PERIPH_GPIOE : Disable GPIOE reset + * @arg RCM_APB2_PERIPH_GPIOF : Disable GPIOF reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_GPIOG : Disable GPIOG reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_ADC1 : Disable ADC1 reset + * @arg RCM_APB2_PERIPH_ADC2 : Disable ADC2 reset + * @arg RCM_APB2_PERIPH_TMR1 : Disable TMR1 reset + * @arg RCM_APB2_PERIPH_SPI1 : Disable SPI1 reset + * @arg RCM_APB2_PERIPH_TMR8 : Disable TMR8 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB2_PERIPH_USART1 : Disable USART1 reset + * @arg RCM_APB2_PERIPH_ADC3 : Disable ADC3 reset (Only for High-density devices for APM32F103xx) + * + * @retval None + */ +void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph) +{ + RCM->APB2RST &= (uint32_t)~APB2Periph; +} + +/*! + * @brief Enable Low Speed APB (APB1) peripheral reset + * + * @param APB1Periph : Enable specifies APB1 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 reset + * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 reset + * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 reset + * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT reset + * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 reset + * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 reset + * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 reset + * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 reset + * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 reset + * @arg RCM_APB1_PERIPH_USB : Enable USB reset + * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 reset + * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 reset (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Enable BAKR reset + * @arg RCM_APB1_PERIPH_PMU : Enable PMU reset + * @arg RCM_APB1_PERIPH_DAC : Enable DAC reset + * + * @retval None + */ +void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph) +{ + RCM->APB1RST |= APB1Periph; +} + +/*! + * @brief Disable Low Speed APB (APB1) peripheral reset + * + * @param APB1Periph : Disable specifies APB1 peripheral reset. + * This parameter can be any combination of the following values: + * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 reset + * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 reset + * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 reset + * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT reset + * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 reset + * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 reset + * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 reset + * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 reset (Only for High-density devices for APM32F103xx) + * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 reset + * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 reset + * @arg RCM_APB1_PERIPH_USB : Disable USB reset + * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 reset + * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 reset (only for APM32F103xC device) + * @arg RCM_APB1_PERIPH_BAKR : Disable BAKR reset + * @arg RCM_APB1_PERIPH_PMU : Disable PMU reset + * @arg RCM_APB1_PERIPH_DAC : Disable DAC reset + * + * @retval None + */ +void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph) +{ + RCM->APB1RST &= (uint32_t)~APB1Periph; +} + +/*! + * @brief Enable the Backup domain reset + * + * @param None + * + * @retval None + * + * @note + */ +void RCM_EnableBackupReset(void) +{ + RCM->BDCTRL_B.BDRST = BIT_SET; +} + +/*! + * @brief Disable the Backup domain reset + * + * @param None + * + * @retval None + */ +void RCM_DisableBackupReset(void) +{ + RCM->BDCTRL_B.BDRST = BIT_RESET; +} + +/*! + * @brief Enable RCM interrupts + * + * @param interrupt : Enable specifies RCM interrupt sources. + * This parameter can be any combination of the following values: + * @arg RCM_INT_LSIRDY : LSI ready interrupt + * @arg RCM_INT_LSERDY : LSE ready interrupt + * @arg RCM_INT_HSIRDY : HSI ready interrupt + * @arg RCM_INT_HSERDY : HSE ready interrupt + * @arg RCM_INT_PLLRDY : PLL ready interrupt + * + * @retval None + */ +void RCM_EnableInterrupt(uint32_t interrupt) +{ + uint32_t temp; + + temp = interrupt << 8; + + RCM->INT |= temp; +} + +/*! + * @brief Disable RCM interrupts + * + * @param interrupt : Disable specifies RCM interrupt sources. + * This parameter can be any combination of the following values: + * @arg RCM_INT_LSIRDY : LSI ready interrupt + * @arg RCM_INT_LSERDY : LSE ready interrupt + * @arg RCM_INT_HSIRDY : HSI ready interrupt + * @arg RCM_INT_HSERDY : HSE ready interrupt + * @arg RCM_INT_PLLRDY : PLL ready interrupt +RCM_DisableInterrupt(RCM_INT_LSIRDY) * + * @retval None + */ +void RCM_DisableInterrupt(uint32_t interrupt) +{ + uint32_t temp; + + temp = interrupt << 8; + + RCM->INT &= (uint32_t)~temp; +} + +/*! + * @brief Read the specified RCM flag status + * + * @param flag : Returns specifies the flag status. + * This parameter can be one of the following values: + * @arg RCM_FLAG_HSIRDY : HSI ready flag + * @arg RCM_FLAG_HSERDY : HSE ready flag + * @arg RCM_FLAG_PLLRDY : PLL ready flag + * @arg RCM_FLAG_LSERDY : LSE ready flag + * @arg RCM_FLAG_LSIRDY : LSI ready flag + * @arg RCM_FLAG_PINRST : NRST PIN Reset Occur Flag + * @arg RCM_FLAG_PORRST : POR/PDR Reset Occur Flag + * @arg RCM_FLAG_SWRST : Software Reset Occur Flag + * @arg RCM_FLAG_IWDTRST : Independent Watchdog Reset Occur Flag + * @arg RCM_FLAG_WWDTRST : Window Watchdog Reset Occur Flag + * @arg RCM_FLAG_LPRRST : Low Power Reset Occur Flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag) +{ + uint32_t reg, bit; + + bit = (uint32_t)(1 << (flag & 0xff)); + + reg = (flag >> 8) & 0xff; + + switch (reg) + { + case 0: + reg = RCM->CTRL; + break; + + case 1: + reg = RCM->BDCTRL; + break; + + case 2: + reg = RCM->CSTS; + break; + + default: + break; + } + + if (reg & bit) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears all the RCM reset flags + * + * @param None + * + * @retval None + * + * @note The reset flags are: + * RCM_FLAG_PINRST, RCM_FLAG_PWRST, RCM_FLAG_SWRST + * RCM_FLAG_IWDTRST, RCM_FLAG_WWDTRST, RCM_FLAG_LPRRST + */ +void RCM_ClearStatusFlag(void) +{ + RCM->CSTS_B.RSTFLGCLR = BIT_SET; +} + +/*! + * @brief Reads the specified RCM interrupt Flag + * + * @param flag £ºReads specifies RCM interrupt flag. + * This parameter can be one of the following values: + * @arg RCM_INT_LSIRDY : LSI ready interrupt flag + * @arg RCM_INT_LSERDY : LSE ready interrupt flag + * @arg RCM_INT_HSIRDY : HSI ready interrupt flag + * @arg RCM_INT_HSERDY : HSE ready interrupt flag + * @arg RCM_INT_PLLRDY : PLL ready interrupt flag + * @arg RCM_INT_CSS : Clock Security System interrupt flag + * + * @retval The new state of intFlag (SET or RESET) + */ +uint8_t RCM_ReadIntFlag(RCM_INT_T flag) +{ + uint8_t ret; + + ret = (RCM->INT& flag) ? SET : RESET; + + return ret; +} + +/*! + * @brief Clears the interrupt flag + * + * @param flag : Clears specifies interrupt flag. + * @arg RCM_INT_LSIRDY : Clear LSI ready interrupt flag + * @arg RCM_INT_LSERDY : Clear LSE ready interrupt flag + * @arg RCM_INT_HSIRDY : Clear HSI ready interrupt flag + * @arg RCM_INT_HSERDY : Clear HSE ready interrupt flag + * @arg RCM_INT_PLLRDY : Clear PLL ready interrupt flag + * @arg RCM_INT_CSS : Clear Clock Security System interrupt flag + * + * @retval None + */ +void RCM_ClearIntFlag(uint32_t flag) +{ + uint32_t temp; + + temp = flag << 16; + RCM->INT |= temp; +} + +/**@} end of group RCM_Fuctions*/ +/**@} end of group RCM_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c new file mode 100644 index 0000000000..71db57ceb7 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c @@ -0,0 +1,221 @@ +/*! + * @file apm32f10x_rtc.c + * + * @brief This file provides all the RTC firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ +#include "apm32f10x_rtc.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Enter RTC configuration mode. + * + * @param None + * + * @retval None + */ +void RTC_EnableConfigMode(void) +{ + RTC->CSTS_B.CFGMFLG = BIT_SET; +} + +/*! + * @brief Exit RTC configuration mode. + * + * @param None + * + * @retval None + */ +void RTC_DisableConfigMode(void) +{ + RTC->CSTS_B.CFGMFLG = BIT_RESET; +} + +/*! + * @brief Read the RTC counter value. + * + * @param None + * + * @retval RTC counter value. + */ +uint32_t RTC_ReadCounter(void) +{ + return (((RTC->CNTH_B.CNTH) << 16) | (RTC->CNTL_B.CNTL)); +} + +/*! + * @brief Config the RTC counter value. + * + * @param value: RTC counter new value. + * + * @retval None + */ +void RTC_ConfigCounter(uint32_t value) +{ + RTC_EnableConfigMode(); + RTC->CNTH_B.CNTH = value >> 16; + RTC->CNTL_B.CNTL = value & 0x0000FFFF; + RTC_DisableConfigMode(); +} + +/*! + * @brief Config the RTC prescaler value. + * + * @param value: RTC prescaler new value. + * + * @retval None + */ +void RTC_ConfigPrescaler(uint32_t value) +{ + RTC_EnableConfigMode(); + RTC->PSCRLDH_B.PSCRLDH = value >> 16; + RTC->PSCRLDL_B.PSCRLDL = value & 0x0000FFFF; + RTC_DisableConfigMode(); +} + +/*! + * @brief Config the RTC alarm value. + * + * @param value: RTC alarm new value. + * + * @retval None + */ +void RTC_ConfigAlarm(uint32_t value) +{ + RTC_EnableConfigMode(); + RTC->ALRH_B.ALRH = value >> 16; + RTC->ALRL_B.ALRL = value & 0x0000FFFF; + RTC_DisableConfigMode(); +} + +/*! + * @brief Reads the RTC divider value. + * + * @param None + * + * @retval RTC Divider value. + */ +uint32_t RTC_ReadDivider(void) +{ + return ((RTC->PSCH_B.PSCH & 0x000F) << 16 ) | (RTC->PSCL_B.PSCL); +} + +/*! + * @brief Waits until last write operation on RTC registers has finished. + * + * @param None + * + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + while(RTC->CSTS_B.OCFLG == BIT_RESET) + { + } +} + +/*! + * @brief Waits until the RTC registers + * + * @param None + * + * @retval None + */ +void RTC_WaitForSynchor(void) +{ + RTC->CSTS_B.RSYNCFLG = BIT_RESET; + while(RTC->CSTS_B.RSYNCFLG == BIT_RESET) + { + } +} + +/*! + * @brief Enable RTC interrupts. + * + * @param interrupt: RTC interrupt + * + * @retval None + */ +void RTC_EnableInterrupt(uint16_t interrupt) +{ + RTC->CTRL |= interrupt; +} + +/*! + * @brief Disable RTC interrupts. + * + * @param interrupt: RTC interrupt + * + * @retval None + */ +void RTC_DisableInterrupt(uint16_t interrupt) +{ + RTC->CTRL &= (uint32_t )~interrupt; +} + +/*! + * @brief Read flag bit + * + * @param flag: Flags to read + * + * @retval flag bit + */ +uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag) +{ + return (RTC->CSTS & flag) ? SET : RESET; +} + +/*! + * @brief Clear flag bit + * + * @param flag: Flags to clear + * + * @retval None + */ +void RTC_ClearStatusFlag(uint16_t flag) +{ + RTC->CSTS &= (uint32_t)~flag; +} + +/*! + * @brief Read interrupt flag bit is set + * + * @param flag:Flag bit to check + * + * @retval None + */ +uint8_t RTC_ReadIntFlag(RTC_INT_T flag) +{ + return (RTC->CSTS & flag) ? SET : RESET; +} + +/*! + * @brief Clear RTC interrupt flag bit + * + * @param flag: Clears the specified interrupt flag bit + * + * @retval None + */ +void RTC_ClearIntFlag(uint16_t flag) +{ + RTC->CSTS &= (uint32_t)~flag; +} + +/**@} end of group RTC_Fuctions*/ +/**@} end of group RTC_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c new file mode 100644 index 0000000000..4b5ea1276a --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c @@ -0,0 +1,898 @@ +/*! + * @file apm32f10x_sci2c.c + * + * @brief This file contains all the functions for the SCI2C peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_sci2c.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SCI2C_Driver SCI2C Driver + @{ +*/ + +/** @addtogroup SCI2C_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Set I2C peripheral registers to their default reset values + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_Reset(SCI2C_T *i2c) +{ + if(i2c == I2C3) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1); + } + else + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C2); + } + + i2c->SW = 0; + i2c->SW = 1; + i2c->INTEN = 0; +} + +/*! + * @brief Config the I2C peripheral according to the specified parameters in the sci2cConfig + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param sci2cConfig: pointer to a SCI2C_Config_T structure + * + * @retval None + */ +void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig) +{ + i2c->SW = BIT_SET; + + i2c->CTRL2_B.I2CEN = BIT_RESET; + + if(sci2cConfig->mode == SCI2C_MODE_MASTER) + { + i2c->CTRL1_B.MST = BIT_SET; + i2c->CTRL1_B.SLADIS = BIT_SET; + } + else + { + i2c->CTRL1_B.MST = BIT_RESET; + } + + i2c->CTRL1_B.SPD = sci2cConfig->speed; + i2c->CTRL1_B.RSTAEN = sci2cConfig->restart; + + i2c->TFT = sci2cConfig->txFifoThreshold; + i2c->RFT = sci2cConfig->rxFifoThreshold; + + i2c->TARADDR_B.MAM = sci2cConfig->addrMode; + i2c->CTRL1_B.SAM = sci2cConfig->addrMode; + i2c->SLAADDR = sci2cConfig->slaveAddr; + + if(sci2cConfig->speed == SCI2C_SPEED_STANDARD) + { + i2c->SSCLC = sci2cConfig->clkLowPeriod; + i2c->SSCHC = sci2cConfig->clkHighPeriod; + } + else if(sci2cConfig->speed == SCI2C_SPEED_FAST) + { + i2c->FSCLC = sci2cConfig->clkLowPeriod; + i2c->FSCHC = sci2cConfig->clkHighPeriod; + } + else if(sci2cConfig->speed == SCI2C_SPEED_HIGH) + { + i2c->HSCLC = sci2cConfig->clkLowPeriod; + i2c->HSCHC = sci2cConfig->clkHighPeriod; + } +} + +/*! + * @brief Fills each sci2cConfig member with its default value + * + * @param sci2cConfig: pointer to a SCI2C_Config_T structure + * + * @retval None + */ +void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig) +{ + sci2cConfig->addrMode = SCI2C_ADDR_MODE_7BIT; + sci2cConfig->slaveAddr = 0x55; + sci2cConfig->clkHighPeriod = 0x3C; + sci2cConfig->clkLowPeriod = 0x82; + sci2cConfig->mode = SCI2C_MODE_MASTER; + sci2cConfig->restart = SCI2C_RESTART_ENABLE; + sci2cConfig->rxFifoThreshold = 0; + sci2cConfig->txFifoThreshold = 0; + sci2cConfig->speed = SCI2C_SPEED_FAST; +} + +/*! + * @brief Read specified flag + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_FLAG_ACT: Activity flag + * @arg SCI2C_FLAG_TFNF: Tx FIFO not full flag + * @arg SCI2C_FLAG_TFE: TX FIFO empty flag + * @arg SCI2C_FLAG_RFNE: Rx FIFO not empty flag + * @arg SCI2C_FLAG_RFF: Rx FIFO full flag + * @arg SCI2C_FLAG_MA: Master activity flag + * @arg SCI2C_FLAG_SA: Slave activity flag + * @arg SCI2C_FLAG_I2CEN: I2C enable flag + * @arg SCI2C_FLAG_SDWB: Slave disable while busy flag + * @arg SCI2C_FLAG_SRDL: Slave receive data lost flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag) +{ + uint8_t ret = RESET; + + if(flag & BIT8) + { + ret = i2c->STS2 & flag ? SET : RESET; + } + else + { + ret = i2c->STS1 & flag ? SET : RESET; + } + + return ret; +} + +/*! + * @brief Read specified interrupt flag + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt flag + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt flag + * @arg SCI2C_INT_RR: Read request interrupt flag + * @arg SCI2C_INT_TA: Tx abort interrupt flag + * @arg SCI2C_INT_RD: Read done interrupt flag + * @arg SCI2C_INT_ACT: Activity interrupt flag + * @arg SCI2C_INT_STPD: Stop detect interrupt flag + * @arg SCI2C_INT_STAD: Start detect interrupt flag + * @arg SCI2C_INT_GC: Gernal call interrupt flag + * @arg SCI2C_INT_RSTAD: Restart detect interrupt flag + * @arg SCI2C_INT_MOH: Master on hold interrupt flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +{ + uint8_t ret = RESET; + + ret = i2c->INTSTS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Clear specified interrupt flag + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag + * @arg SCI2C_INT_RR: Read request interrupt flag + * @arg SCI2C_INT_TA: Tx abort interrupt flag + * @arg SCI2C_INT_RD: Read done interrupt flag + * @arg SCI2C_INT_ACT: Activity interrupt flag + * @arg SCI2C_INT_STPD: Stop detect interrupt flag + * @arg SCI2C_INT_STAD: Start detect interrupt flag + * @arg SCI2C_INT_GC: Gernal call interrupt flag + * @arg SCI2C_INT_ALL: All interrupt flag + * @retval The new state of flag (SET or RESET) + */ +void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +{ + volatile uint32_t dummy = 0; + + if(flag == SCI2C_INT_ALL) + { + dummy = i2c->INTCLR; + } + else if(flag == SCI2C_INT_RFU) + { + dummy = i2c->RFUIC; + } + else if(flag == SCI2C_INT_RFO) + { + dummy = i2c->RFOIC; + } + else if(flag == SCI2C_INT_TFO) + { + dummy = i2c->TFOIC; + } + else if(flag == SCI2C_INT_RR) + { + dummy = i2c->RRIC; + } + else if(flag == SCI2C_INT_TA) + { + dummy = i2c->TAIC; + } + else if(flag == SCI2C_INT_RD) + { + dummy = i2c->RDIC; + } + else if(flag == SCI2C_INT_ACT) + { + dummy = i2c->AIC; + } + else if(flag == SCI2C_INT_STPD) + { + dummy = i2c->STPDIC; + } + else if(flag == SCI2C_INT_STAD) + { + dummy = i2c->STADIC; + } + else if(flag == SCI2C_INT_GC) + { + dummy = i2c->GCIC; + } +} + +/*! + * @brief Read specified interrupt flag(Raw register) + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param flag: Specifies the interrupt flag to be checked + * The parameter can be one of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt flag + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt flag + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt flag + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt flag + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt flag + * @arg SCI2C_INT_RR: Read request interrupt flag + * @arg SCI2C_INT_TA: Tx abort interrupt flag + * @arg SCI2C_INT_RD: Read done interrupt flag + * @arg SCI2C_INT_ACT: Activity interrupt flag + * @arg SCI2C_INT_STPD: Stop detect interrupt flag + * @arg SCI2C_INT_STAD: Start detect interrupt flag + * @arg SCI2C_INT_GC: Gernal call interrupt flag + * @arg SCI2C_INT_RSTAD: Restart detect interrupt flag + * @arg SCI2C_INT_MOH: Master on hold interrupt flag + * + * @retval The new state of flag (SET or RESET) + */ +uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag) +{ + uint8_t ret = RESET; + + ret = i2c->RIS & flag ? SET : RESET; + + return ret; +} + +/*! + * @brief Enable the specified interrupts + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param interrupt: Specifies the interrupt sources + * The parameter can be any combination of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt + * @arg SCI2C_INT_RR: Read request interrupt + * @arg SCI2C_INT_TA: Tx abort interrupt + * @arg SCI2C_INT_RD: Read done interrupt + * @arg SCI2C_INT_ACT: Activity interrupt + * @arg SCI2C_INT_STPD: Stop detect interrupt + * @arg SCI2C_INT_STAD: Start detect interrupt + * @arg SCI2C_INT_GC: Gernal call interrupt + * @arg SCI2C_INT_RSTAD: Restart detect interrupt + * @arg SCI2C_INT_MOH: Master on hold interrupt + * + * @retval None + */ +void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt) +{ + i2c->INTEN |= interrupt; +} + +/*! + * @brief Disable the specified interrupts + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param interrupt: Specifies the interrupt sources + * The parameter can be any combination of following values: + * @arg SCI2C_INT_RFU: Rx FIFO underflow interrupt + * @arg SCI2C_INT_RFO: Rx FIFO onverflow interrupt + * @arg SCI2C_INT_RFF: Rx FIFO full interrupt + * @arg SCI2C_INT_TFO: Tx FIFO onverflow interrupt + * @arg SCI2C_INT_TFE: Tx FIFO empty interrupt + * @arg SCI2C_INT_RR: Read request interrupt + * @arg SCI2C_INT_TA: Tx abort interrupt + * @arg SCI2C_INT_RD: Read done interrupt + * @arg SCI2C_INT_ACT: Activity interrupt + * @arg SCI2C_INT_STPD: Stop detect interrupt + * @arg SCI2C_INT_STAD: Start detect interrupt + * @arg SCI2C_INT_GC: Gernal call interrupt + * @arg SCI2C_INT_RSTAD: Restart detect interrupt + * @arg SCI2C_INT_MOH: Master on hold interrupt + * + * @retval None + */ +void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt) +{ + i2c->INTEN &= ~interrupt; +} + +/*! + * @brief Enable stop detected only master in activity. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSMA = BIT_SET; +} + +/*! + * @brief Disable stop detected only master in activity. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSMA = BIT_RESET; +} + +/*! + * @brief Enable stop detected only address is matched in slave mode. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSA = BIT_SET; +} + +/*! + * @brief Disable stop detected only address is matched in slave mode. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + */ +void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c) +{ + i2c->CTRL1_B.DSA = BIT_RESET; +} + +/*! + * @brief Enable restart + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_EnableRestart(SCI2C_T *i2c) +{ + i2c->CTRL1_B.RSTAEN = BIT_SET; +} + +/*! + * @brief Disable restart + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_DisableRestart(SCI2C_T *i2c) +{ + i2c->CTRL1_B.RSTAEN = BIT_RESET; +} + +/*! + * @brief Config speed. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param speed: Specifies the speed. + * @arg SCI2C_SPEED_STANDARD: Standard speed. + * @arg SCI2C_SPEED_FAST: Fast speed. + * @arg SCI2C_SPEED_HIGH: High speed. + * + * @retval None + */ +void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed) +{ + i2c->CTRL1_B.SPD = speed; +} + +/*! + * @brief Config master address. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param mode: Specifies the address mode. + * @arg SCI2C_ADDR_MODE_7BIT: 7-bit address mode. + * @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode. + * + * @param addr: Specifies the address. + + * @retval None + */ +void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) +{ + i2c->TARADDR_B.MAM = mode; + i2c->TARADDR_B.ADDR = addr; +} + + +/*! + * @brief Config slave address. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param mode: Specifies the address mode. + * @arg SCI2C_ADDR_MODE_7BIT: 7-bit address mode. + * @arg SCI2C_ADDR_MODE_10BIT: 10-bit address mode. + * + * @param addr: Specifies the address. + + * @retval None + */ +void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr) +{ + i2c->CTRL1_B.SAM = mode; + i2c->SLAADDR = addr; +} + +/*! + * @brief Enable master mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_EnableMasterMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.MST = BIT_SET; +} + +/*! + * @brief Disable master mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_DisableMasterMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.MST = BIT_RESET; +} + +/*! + * @brief Enable slave mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_EnableSlaveMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.SLADIS = BIT_RESET; +} + +/*! + * @brief Disable slave mode + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_DisableSlaveMode(SCI2C_T *i2c) +{ + i2c->CTRL1_B.SLADIS = BIT_SET; +} + +/*! + * @brief Config master code + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param code: Master code + * + * @retval None + */ +void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code) +{ + i2c->HSMC = code; +} + +/*! + * @brief Config data direction + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param dir: Data direction + * @arg SCI2C_DATA_DIR_WRITE: Write data + * @arg SCI2C_DATA_DIR_READ: Read data + * + * @retval None + */ +void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir) +{ + i2c->DATA = (uint32_t)(dir << 8); +} + +/*! + * @brief Transmit data + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param data: Data to be transmited + * + * @retval None + */ +void SCI2C_TxData(SCI2C_T *i2c, uint8_t data) +{ + i2c->DATA_B.DATA = data; +} + +/*! + * @brief Returns the most recent received data + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval Received data + * + * @note + */ +uint8_t SCI2C_RxData(SCI2C_T *i2c) +{ + return (uint8_t)(i2c->DATA & 0XFF); +} + +/*! + * @brief Config data register + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param stop: Enable or disable generate stop condition + * + * @param dataDir: Data direction. Read or write + * @arg SCI2C_DATA_DIR_WRITE: Write data + * @arg SCI2C_DATA_DIR_READ: Read data + * + * @param data: Data to be transmited + * + * @retval None + */ +void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data) +{ + i2c->DATA = (uint32_t)((stop << 9) | (dataDir << 8) | data); +} + +/*! + * @brief Read Rx FIFO data number + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c) +{ + return (uint8_t)i2c->RFL; +} + +/*! + * @brief Read Tx FIFO data number + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c) +{ + return (uint8_t)i2c->TFL; +} + +/*! + * @brief Config Rx FIFO threshold + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param threshold: FIFO threshold + * + * @retval None + */ +void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold) +{ + i2c->RFT = threshold; +} + +/*! + * @brief Config Tx FIFO threshold + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param threshold: FIFO threshold + * + * @retval None + */ +void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold) +{ + i2c->TFT = threshold; +} + +/*! + * @brief Enable I2C peripheral + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + + */ +void SCI2C_Enable(SCI2C_T *i2c) +{ + i2c->CTRL2_B.I2CEN = BIT_SET; +} + +/*! + * @brief Disable I2C peripheral + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_Disable(SCI2C_T *i2c) +{ + i2c->CTRL2_B.I2CEN = BIT_RESET; +} + +/*! + * @brief Abort I2C transmit + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval None + */ +void SCI2C_Abort(SCI2C_T *i2c) +{ + i2c->CTRL2_B.ABR = BIT_SET; +} + +/*! + * @brief Tx command block + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param enable: ENABLE or DISABLE + * + * @retval None + */ +void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable) +{ + i2c->CTRL2_B.TCB = enable; +} + +/*! + * @brief Config SCL high and low period + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param speed: Specifies the speed. + * @arg SCI2C_SPEED_STANDARD: Standard speed. + * @arg SCI2C_SPEED_FAST: Fast speed. + * @arg SCI2C_SPEED_HIGH: High speed. + * + * @param highPeriod: SCL high period + * + * @param lowPeriod: SCL low period + * + * @retval None + */ +void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod) +{ + if(speed == SCI2C_SPEED_STANDARD) + { + i2c->SSCLC = lowPeriod; + i2c->SSCHC = highPeriod; + } + else if(speed == SCI2C_SPEED_FAST) + { + i2c->FSCLC = lowPeriod; + i2c->FSCHC = highPeriod; + } + else if(speed == SCI2C_SPEED_HIGH) + { + i2c->HSCLC = lowPeriod; + i2c->HSCHC = highPeriod; + } +} + +/*! + * @brief Config SDA hold time length + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param txHold: Tx SDA hold time length + * + * @param rxHold: Rx SDA hold time length + * + * @retval None + */ +void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold) +{ + i2c->SDAHOLD_B.TXHOLD = txHold; + i2c->SDAHOLD_B.RXHOLD = rxHold; +} + +/*! + * @brief Config SDA delay time + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param delay: SDA delay time + * + * @retval None + */ +void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay) +{ + i2c->SDADLY = delay; +} + +/*! + * @brief Enable or disable generate gernal call ack + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param enable: SDA delay time + * + * @retval None + */ +void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable) +{ + i2c->GCA = enable; +} + +/*! + * @brief When received data no ack generated in slave mode. + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param enable: ENABLE or DISABLE + * + * @retval None + */ +void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable) +{ + i2c->SDNO = enable; +} + +/*! + * @brief Read Tx abort source + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @retval Return Tx abort source + */ +uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c) +{ + return (uint32_t)i2c->TAS; +} + +/*! + * @brief Enable DMA + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param dma: DMA requst source + * @arg SCI2C_DMA_RX: DMA RX channel + * @arg SCI2C_DMA_TX: DMA TX channel + * + * @retval None + */ +void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) +{ + i2c->DMACTRL |= dma; +} + +/*! + * @brief Disable DMA + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param dma: DMA requst source + * @arg SCI2C_DMA_RX: DMA RX channel + * @arg SCI2C_DMA_TX: DMA TX channel + * + * @retval None + */ +void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma) +{ + i2c->DMACTRL &= (uint32_t)~dma; +} + +/*! + * @brief Config DMA Tx data level + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param cnt: DMA Tx data level + * + * @retval None + */ +void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt) +{ + i2c->DTDL = cnt; +} + +/*! + * @brief Config DMA Rx data level + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param cnt: DMA Rx data level + * + * @retval None + */ +void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt) +{ + i2c->DRDL = cnt; +} + +/*! + * @brief Config spike suppressio limit + * + * @param i2c: Select the the I2C peripheral.It can be I2C3 or I2C4 + * + * @param speed: I2C speed mode + * @arg SCI2C_SPEED_STANDARD: Standard speed. + * @arg SCI2C_SPEED_FAST: Fast speed. + * @arg SCI2C_SPEED_HIGH: High speed. + * + * @param limit: Spike suppressio limit value + * + * @retval None + */ +void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit) +{ + if(speed == SCI2C_SPEED_HIGH) + { + i2c->HSSSL = limit; + } + else + { + i2c->LSSSL = limit; + } +} + +/**@} end of group SCI2C_Fuctions*/ +/**@} end of group SCI2C_Driver*/ +/**@} end of group Peripherals_Library*/ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c new file mode 100644 index 0000000000..3c76e77076 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c @@ -0,0 +1,730 @@ +/*! + * @file apm32f10x_sdio.c + * + * @brief This file provides all the SDIO firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_sdio.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SDIO_Driver SDIO Driver + @{ +*/ + +/** @addtogroup SDIO_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset sdio peripheral registers to their default reset values + * + * @param None + * + * @retval None + */ +void SDIO_Reset(void) +{ + SDIO->PWRCTRL = 0x00000000; + SDIO->CLKCTRL = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DATATIME = 0x00000000; + SDIO->DATALEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICF = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/*! + * @brief Config the SDIO peripheral according to the specified parameters in the sdioConfig + * + * @param sdioConfig: pointer to a SDIO_Config_T structure + * + * @retval None + */ +void SDIO_Config(SDIO_Config_T* sdioConfig) +{ + uint32_t tmp = 0; + + tmp = SDIO->CLKCTRL; + tmp &= 0xFFFF8100; + + tmp |= (sdioConfig->clockDiv | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide | + sdioConfig->clockEdge | sdioConfig->hardwareFlowControl); + + SDIO->CLKCTRL = tmp; +} + +/*! + * @brief Fills each SDIO_Config_T member with its default value + * + * @param sdioConfig: pointer to a SDIO_Config_T structure + * + * @retval None + */ +void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig) +{ + sdioConfig->clockDiv = 0x00; + sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING; + sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE; + sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + sdioConfig->busWide = SDIO_BUSWIDE_1B; + sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; +} + +/*! + * @brief Enables the SDIO clock + * + * @param None + * + * @retval None + */ +void SDIO_EnableClock(void) +{ + *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)SET; +} + +/*! + * @brief Disables the SDIO clock + * + * @param None + * + * @retval None + */ +void SDIO_DisableClock(void) +{ + *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)RESET; +} + +/*! + * @brief Sets the power status of the controller + * + * @param powerState: new state of the Power state + * The parameter can be one of following values: + * @arg SDIO_POWER_STATE_OFF + * @arg SDIO_POWER_STATE_ON + * @retval None + */ +void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState) +{ + SDIO->PWRCTRL &= 0xFFFFFFFC; + SDIO->PWRCTRL |= powerState; +} + +/*! + * @brief Reads the SDIO power state + * + * @param None + * + * @retval The new state SDIO power + * + * @note 0x00:Power OFF, 0x02:Power UP, 0x03:Power ON + */ +uint32_t SDIO_ReadPowerState(void) +{ + return (SDIO->PWRCTRL & (~0xFFFFFFFC)); +} + +/*! + * @brief Enables the SDIO DMA request + * + * @param None + * + * @retval None + */ +void SDIO_EnableDMA(void) +{ + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)SET; +} + +/*! + * @brief Disables the SDIO DMA request + * + * @param None + * + * @retval None + */ +void SDIO_DisableDMA(void) +{ + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)RESET; +} + +/*! + * @brief Configs the SDIO Command and send the command + * + * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure + * + * @retval None + * + * @note + */ +void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig) +{ + uint32_t tmpreg = 0; + + SDIO->ARG = cmdConfig->argument; + tmpreg = SDIO->CMD; + tmpreg &= 0xFFFFF800; + tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response + | cmdConfig->wait | cmdConfig->CPSM; + SDIO->CMD = tmpreg; +} + +/*! + * @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value + * + * @param cmdConfig: pointer to a SDIO_CMDConfig_T structure + * + * @retval None + * + * @note + */ +void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdConfig) +{ + cmdConfig->argument = 0x00; + cmdConfig->cmdIndex = 0x00; + cmdConfig->response = SDIO_RESPONSE_NO; + cmdConfig->wait = SDIO_WAIT_NO; + cmdConfig->CPSM = SDIO_CPSM_DISABLE; +} + +/*! + * @brief Reads the SDIO command response + * + * @param None + * + * @retval The command index of the last command response received + * + * @note + */ +uint8_t SDIO_ReadCommandResponse(void) +{ + return (uint8_t)(SDIO->CMDRES); +} + +/*! + * @brief Reads the SDIO response + * + * @param res: Specifies the SDIO response register + * The parameter can be one of following values: + * @arg SDIO_RES1: Response Register 1 + * @arg SDIO_RES2: Response Register 2 + * @arg SDIO_RES3: Response Register 3 + * @arg SDIO_RES4: Response Register 4 + * + * @retval The Corresponding response register value + */ +uint32_t SDIO_ReadResponse(SDIO_RES_T res) +{ + __IO uint32_t tmp = 0; + + tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res; + + return (*(__IO uint32_t *) tmp); +} + +/*! + * @brief Configs the SDIO Dataaccording to the specified parameters in the dataConfig + * + * @param dataConfig: pointer to a SDIO_DataConfig_T structure + * + * @retval None + */ +void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) +{ + uint32_t tmpreg = 0; + + SDIO->DATATIME = dataConfig->dataTimeOut; + + SDIO->DATALEN = dataConfig->dataLength; + + tmpreg = SDIO->DCTRL; + + tmpreg &= 0xFFFFFF08; + + tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir + | dataConfig->transferMode | dataConfig->DPSM; + + SDIO->DCTRL = tmpreg; +} + +/*! + * @brief Fills each SDIO_DataConfig_T member with its default value + * + * @param dataConfig: pointer to a SDIO_DataConfig_T structure + * + * @retval None + */ +void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig) +{ + dataConfig->dataTimeOut = 0xFFFFFFFF; + dataConfig->dataLength = 0x00; + dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B; + dataConfig->transferDir = SDIO_TRANSFER_DIR_TOCARD; + dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK; + dataConfig->DPSM = SDIO_DPSM_DISABLE; +} + +/*! + * @brief Reads the SDIO Data counter + * + * @param None + * + * @retval The SDIO Data counter value + */ +uint32_t SDIO_ReadDataCounter(void) +{ + return SDIO->DCNT; +} + +/*! + * @brief Write the SDIO Data + * + * @param Data£ºWrite 32-bit data + * + * @retval None + */ +void SDIO_WriteData(uint32_t data) +{ + SDIO->FIFODATA = data; +} + +/*! + * @brief Reads the SDIO Data + * + * @param None + * + * @retval The SDIO FIFO Data value + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFODATA; +} + +/*! + * @brief Reads the SDIO FIFO count value + * + * @param None + * + * @retval The SDIO FIFO count value + */ +uint32_t SDIO_ReadFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/*! + * @brief Enables SDIO start read wait + * + * @param None + * + * @retval None + */ +void SDIO_EnableStartReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) SET; +} + +/*! + * @brief Disables SDIO start read wait + * + * @param None + * + * @retval None + */ +void SDIO_DisableStopReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) RESET; +} + +/*! + * @brief Enables SDIO stop read wait + * + * @param None + * + * @retval None + */ +void SDIO_EnableStopReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) SET; +} + +/*! + * @brief Disables SDIO stop read wait + * + * @param None + * + * @retval None + */ +void SDIO_DisableStartReadWait(void) +{ + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) RESET; +} + +/*! + * @brief Sets the read wait interval + * + * @param readWaitMode: SDIO read Wait Mode + * The parameter can be one of following values: + * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 + * + * @retval None + * + * @note + */ +void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode) +{ + *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode; +} +/*! + * @brief Enables SDIO SD I/O Mode Operation + * + * @param None + * + * @retval None + */ +void SDIO_EnableSDIO(void) +{ + *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET; +} + +/*! + * @brief Disables SDIO SD I/O Mode Operation + * + * @param None + * + * @retval None + */ +void SDIO_DisableSDIO(void) +{ + *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET; +} + +/*! + * @brief Ensables SDIO SD I/O Mode suspend command sending + * + * @param None + * + * @retval None + */ +void SDIO_EnableTxSDIOSuspend(void) +{ + *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)SET; +} + +/*! + * @brief Disables SDIO SD I/O Mode suspend command sending + * + * @param None + * + * @retval None + */ +void SDIO_DisableTxSDIOSuspend(void) +{ + *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)RESET; +} + +/*! + * @brief Enables the command completion signal + * + * @param None + * + * @retval None + */ +void SDIO_EnableCommandCompletion(void) +{ + *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)SET; +} + +/*! + * @brief Disables the command completion signal + * + * @param None + * + * @retval None + */ +void SDIO_DisableCommandCompletion(void) +{ + *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)RESET; +} + +/*! + * @brief Enables the CE-ATA interrupt + * + * @param None + * + * @retval None + */ +void SDIO_EnableCEATAInterrupt(void) +{ + *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1)); +} + +/*! + * @brief Disables the CE-ATA interrupt + * + * @param None + * + * @retval None + */ +void SDIO_DisableCEATAInterrupt(void) +{ + *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1)); +} + +/*! + * @brief Ensables Sends CE-ATA command + * + * @param None + * + * @retval None + */ +void SDIO_EnableTxCEATA(void) +{ + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)SET; +} + +/*! + * @brief Disables Sends CE-ATA command + * + * @param None + * + * @retval None + */ +void SDIO_DisableTxCEATA(void) +{ + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)RESET; +} + +/*! + * @brief Enables the specified SDIO interrupt + * + * @param interrupt: Select the SDIO interrupt source + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +void SDIO_EnableInterrupt(uint32_t interrupt) +{ + SDIO->MASK |= interrupt; +} + +/*! + * @brief Disables the specified SDIO interrupt + * + * @param interrupt: Select the SDIO interrupt source + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval None + */ +void SDIO_DisableInterrupt(uint32_t interrupt) +{ + SDIO->MASK &= ~interrupt; +} + +/*! + * @brief Reads the specified SDIO flag + * + * @param flag: Select the flag to read + * The parameter can be one of following values: + * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag + * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag + * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag + * @arg SDIO_FLAG_DATATO: Data timeout flag + * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag + * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag + * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag + * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag + * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag + * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag + * @arg SDIO_FLAG_CMDACT: Command transfer in progress flag + * @arg SDIO_FLAG_TXACT: Data transmit in progress flag + * @arg SDIO_FLAG_RXACT: Data receive in progress flag + * @arg SDIO_FLAG_TXFHF: Transmit FIFO Half Empty flag + * @arg SDIO_FLAG_RXFHF: Receive FIFO Half Full flag + * @arg SDIO_FLAG_TXFF: Transmit FIFO full flag + * @arg SDIO_FLAG_RXFF: Receive FIFO full flag + * @arg SDIO_FLAG_TXFE: Transmit FIFO empty flag + * @arg SDIO_FLAG_RXFE: Receive FIFO empty flag + * @arg SDIO_FLAG_TXDA: Data available in transmit FIFO flag + * @arg SDIO_FLAG_RXDA: Data available in receive FIFO flag + * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag + * + * @retval SET or RESET + */ +uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag) +{ + uint8_t bitstatus = RESET; + + if ((SDIO->STS & flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/*! + * @brief Clears the specified SDIO flag + * + * @param flag: Select the flag to clear + * The parameter can be any combination of following values: + * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag + * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag + * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag + * @arg SDIO_FLAG_DATATO: Data timeout flag + * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag + * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag + * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag + * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag + * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag + * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag + * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag + * + * @retval None + */ +void SDIO_ClearStatusFlag(uint32_t flag) +{ + SDIO->ICF = flag; +} + +/*! + * @brief Reads the specified SDIO Interrupt flag + * + * @param flag: Select the SDIO interrupt source + * The parameter can be one of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_INT_TXACT: Data transmit in progress interrupt + * @arg SDIO_INT_RXACT: Data receive in progress interrupt + * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt + * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt + * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt + * @arg SDIO_INT_RXFF: Receive FIFO full interrupt + * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt + * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt + * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt + * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * + * @retval SET or RESET + */ +uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag) +{ + uint32_t intEnable; + uint32_t intStatus; + + intEnable = (uint32_t)(SDIO->MASK & flag); + intStatus = (uint32_t)(SDIO->STS & flag); + + if (intEnable && intStatus) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the specified SDIO Interrupt pending bits + * + * @param flag: Select the SDIO interrupt source + * The parameter can be any combination of following values: + * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt + * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt + * @arg SDIO_INT_DATATO: Data timeout interrupt + * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt + * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt + * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt + * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt + * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt + * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt + * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt + * + * @retval None + */ +void SDIO_ClearIntFlag(uint32_t flag) +{ + SDIO->ICF = flag; +} + +/**@} end of group SDIO_Fuctions*/ +/**@} end of group SDIO_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c new file mode 100644 index 0000000000..079685b148 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c @@ -0,0 +1,598 @@ +/*! + * @file apm32f10x_spi.c + * + * @brief This file provides all the SPI firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_spi.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the specified SPIx peripheral + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_I2S_Reset(SPI_T* spi) +{ + if(spi == SPI1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1); + } + else if(spi == SPI2) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2); + } + else if(spi == SPI3) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3); + } +} + +/*! + * @brief Config the SPI peripheral according to the specified parameters in the spiConfig + * + * @param spi: The SPIx can be 1,2,3 + * + * @param spiConfig: pointer to a SPI_Config_T structure + * + * @retval None + */ +void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig) +{ + spi->CTRL1 &= 0x3040; + spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode | + spiConfig->length | spiConfig->polarity | + spiConfig->phase | spiConfig->nss | + spiConfig->baudrateDiv | spiConfig->firstBit); + spi->CRCPOLY = spiConfig->crcPolynomial; +} + +/*! + * @brief Config the I2S peripheral according to the specified parameters in the spiConfig + * + * @param spi: The SPIx can be 2,3 + * + * @param i2sConfig: pointer to a I2S_Config_T structure + * + * @retval None + */ +void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig) +{ + uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1; + uint32_t tmp = 0; + uint32_t sysClock = 0; + + /* Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */ + spi->I2SCFG &= 0xF040; + spi->I2SPSC = 0x0002; + + if(i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT) + { + spi->I2SPSC_B.ODDPSC = 0; + spi->I2SPSC_B.I2SPSC = 2; + } + else + { + if(i2sConfig->length == I2S_DATA_LENGHT_16B) + { + packetSize = 1; + } + else + { + packetSize = 2; + } + + sysClock = RCM_ReadSYSCLKFreq(); + + if(i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE) + { + tmp = (uint16_t)(((((sysClock / 256) * 10) / i2sConfig ->audioDiv)) + 5); + } + else + { + tmp = (uint16_t)(((((sysClock / (32 * packetSize)) *10 ) / i2sConfig ->audioDiv )) + 5); + } + tmp = tmp / 10; + + i2sOdd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sDiv = (uint16_t)((tmp - i2sOdd) / 2); + + if ((i2sDiv < 2) || (i2sDiv > 0xFF)) + { + i2sDiv = 2; + i2sOdd = 0; + } + } + + spi->I2SPSC_B.I2SPSC = i2sDiv; + spi->I2SPSC_B.ODDPSC = i2sOdd; + spi->I2SPSC |= i2sConfig->MCLKOutput; + + spi->I2SCFG = i2sConfig->mode | i2sConfig->standard | i2sConfig->length | i2sConfig->polarity; + + /** select I2S mode */ + spi->I2SCFG_B.MODESEL = BIT_SET; +} + +/*! + * @brief Fills each SPI_Config_T member with its default value + * + * @param spiConfig: pointer to a SPI_Config_T structure + * + * @retval None + */ +void SPI_ConfigStructInit(SPI_Config_T* spiConfig) +{ + spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX; + spiConfig->mode = SPI_MODE_SLAVE; + spiConfig->length = SPI_DATA_LENGTH_8B; + spiConfig->polarity = SPI_CLKPOL_LOW; + spiConfig->phase = SPI_CLKPHA_1EDGE; + spiConfig->nss = SPI_NSS_HARD; + spiConfig->baudrateDiv = SPI_BAUDRATE_DIV_2; + spiConfig->firstBit = SPI_FIRSTBIT_MSB; + spiConfig->crcPolynomial = 7; +} + +/*! + * @brief Fills each I2S_Config_T member with its default value + * + * @param i2sConfig: pointer to a I2S_Config_T structure + * + * @retval None + */ +void I2S_ConfigStructInit(I2S_Config_T* i2sConfig) +{ + i2sConfig->mode = I2S_MODE_SLAVE_TX; + i2sConfig->standard = I2S_STANDARD_PHILLIPS; + i2sConfig->length = I2S_DATA_LENGHT_16B; + i2sConfig->MCLKOutput = I2S_MCLK_OUTPUT_DISABLE; + i2sConfig->audioDiv = I2S_AUDIO_DIV_DEFAULT; + i2sConfig->polarity = I2S_CLKPOL_LOW; +} +/*! + * @brief Enables the specified SPI peripheral + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_Enable(SPI_T* spi) +{ + spi->CTRL1_B.SPIEN = BIT_SET; +} + +/*! + * @brief Disable the specified SPI peripheral + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_Disable(SPI_T* spi) +{ + spi->CTRL1_B.SPIEN = BIT_RESET; +} + +/*! + * @brief Enables the specified I2S peripheral + * + * @param spi: The I2S can be SPI2,SPI3 + * + * @retval None + */ +void I2S_Enable(SPI_T* spi) +{ + spi->I2SCFG_B.I2SEN = BIT_SET; +} + +/*! + * @brief Disable the specified I2S peripheral + * + * @param spi: The I2S can be SPI2,SPI3 + * + * @retval None + */ +void I2S_Disable(SPI_T* spi) +{ + spi->I2SCFG_B.I2SEN = BIT_RESET; +} + +/*! + * @brief Enables the SPIx/I2Sx DMA interface. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param dmaReq: specifies the SPI/I2S DMA transfer request + * The parameter can be one of following values: + * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request + * @retval None + */ +void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) +{ + if(dmaReq == SPI_I2S_DMA_REQ_TX) + { + spi->CTRL2_B.TXDEN = ENABLE; + } + else + { + spi->CTRL2_B.RXDEN = ENABLE; + } +} + +/*! + * @brief Disables the SPIx/I2Sx DMA interface. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param dmaReq: specifies the SPI/I2S DMA transfer request + * The parameter can be one of following values: + * @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request + * @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request + * @retval None + */ +void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq) +{ + if(dmaReq == SPI_I2S_DMA_REQ_TX) + { + spi->CTRL2_B.TXDEN = DISABLE; + } + else + { + spi->CTRL2_B.RXDEN = DISABLE; + } +} + +/*! + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param data: Data to be transmitted + * + * @retval None + */ +void SPI_I2S_TxData(SPI_T* spi, uint16_t data) +{ + spi->DATA = data; +} + +/*! + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @retval data :The value of the received data + * + * @retval None + */ +uint16_t SPI_I2S_RxData(SPI_T* spi) +{ + return spi->DATA; +} + +/*! + * @brief Set the SPI NSS internal by Software + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_SetSoftwareNSS(SPI_T* spi) +{ + spi->CTRL1_B.ISSEL = BIT_SET; +} + +/*! + * @brief Reset the SPI NSS internal by Software + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_ResetSoftwareNSS(SPI_T* spi) +{ + spi->CTRL1_B.ISSEL = BIT_RESET; +} + +/*! + * @brief Enables the specified SPI SS output + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_EnableSSOutput(SPI_T* spi) +{ + spi->CTRL2_B.SSOEN = BIT_SET; +} + +/*! + * @brief Disable the specified SPI SS output + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_DisableSSOutput(SPI_T* spi) +{ + spi->CTRL2_B.SSOEN = BIT_RESET; +} + +/*! + * @brief Configures the specified SPI data size + * + * @param spi: The SPIx can be 1,2,3 + * + * @param length: Select the SPI data Size + * + * @retval None + */ +void SPI_ConfigDataSize(SPI_T* spi, uint16_t length) +{ + spi->CTRL1_B.DFLSEL = BIT_RESET; + spi->CTRL1 |= length; +} + +/*! + * @brief Transmit CRC value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_TxCRC(SPI_T* spi) +{ + spi->CTRL1_B.CECNXT = BIT_SET; +} + +/*! + * @brief Enables the specified SPI CRC value calculation of the transferred bytes + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval None + */ +void SPI_EnableCRC(SPI_T* spi) +{ + spi->CTRL1_B.CRCEN = BIT_SET; +} + +/*! + * @brief Disable the specified SPI CRC value calculation of the transferred bytes + * + * @param spi: The SPIx can be 1,2,3 + * + */ +void SPI_DisableCRC(SPI_T* spi) +{ + spi->CTRL1_B.CRCEN = BIT_RESET; +} + +/*! + * @brief Reads the specified SPI transmit CRC register value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval The SPI transmit CRC register value + */ +uint16_t SPI_ReadTxCRC(SPI_T* spi) +{ + return spi->TXCRC_B.TXCRC; +} + +/*! + * @brief Reads the specified SPI receive CRC register value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval The SPI receive CRC register value + */ +uint16_t SPI_ReadRxCRC(SPI_T* spi) +{ + return spi->RXCRC_B.RXCRC; +} + +/*! + * @brief Reads the specified SPI CRC Polynomial register value + * + * @param spi: The SPIx can be 1,2,3 + * + * @retval The SPI CRC Polynomial register value + */ +uint16_t SPI_ReadCRCPolynomial(SPI_T* spi) +{ + return spi->CRCPOLY_B.CRCPOLY; +} + +/*! + * @brief Configures the specified SPI data transfer direction + * + * @param spi: The SPIx can be 1,2,3 + * + * @param direction: Select the SPI data transfer direction + * The parameter can be one of following values: + * @arg SPI_DIRECTION_RX: Selects Rx receive direction + * @arg SPI_DIRECTION_TX: Selects Tx transmission direction + * @retval None + */ +void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction) +{ + if(direction == SPI_DIRECTION_TX) + { + spi->CTRL1 |= SPI_DIRECTION_TX; + } + else + { + spi->CTRL1 &= SPI_DIRECTION_RX; + } +} + +/*! + * @brief Enables the specified SPI/I2S interrupts. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be one of following values: + * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt + * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt + * @arg SPI_I2S_INT_ERR: Error interrupt + * @retval None + */ +void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) +{ + spi->CTRL2 |= (interrupt >> 8); +} + +/*! + * @brief Disables the specified SPI/I2S interrupts. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be one of following values: + * @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt + * @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt + * @arg SPI_I2S_INT_ERR: Error interrupt + * @retval None + */ +void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt) +{ + spi->CTRL2 &= ~(interrupt >> 8); +} + +/*! + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param flag: specifies the SPI/I2S flag to check + * The parameter can be one of following values: + * @arg SPI_FLAG_RXBNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXBE: Transmit buffer empty flag + * @arg I2S_FLAG_SCHDIR: Side Channel flag + * @arg I2S_FLAG_UDR: Underrun Error flag + * @arg SPI_FLAG_CRCE: CRC Error flag + * @arg SPI_FLAG_ME: Mode Error flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * + * @retval SET or RESET + */ +uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag) +{ + if((spi->STS & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the SPIx CRC Error flag + * + * @param spi: The SPIx can be 1,2,3 + * + * @param flag: only clears SPI_FLAG_CRCE(CRC Error flag) + * + * @retval None + * + * @note 1)SPI_FLAG_OVR: (OverRun error) flag is cleared by software sequence: + * a read operation to SPI_DATA register (SPI_I2S_RxData()) + * followed by a read operation to SPI_STS register (SPI_I2S_ReadStatusFlag()). + * 2)I2S_FLAG_UDR: (UnderRun error) flag is cleared: + * a read operation to SPI_STS register (SPI_I2S_ReadStatusFlag()). + * 3)SPI_FLAG_ME: (Mode Fault) flag is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). + */ +void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag) +{ + spi->STS_B.CRCEFLG = BIT_RESET; +} + +/*! + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param spi: The SPIx can be 1,2,3, When the I2S can be 2,3 + * + * @param flag: specifies the SPI/I2S interrupt flag to check. + * The parameter can be one of following values: + * @arg SPI_I2S_INT_RXBNE: Receive buffer not empty interrupt flag + * @arg SPI_I2S_INT_TXBE: Transmit buffer empty interrupt flag + * @arg SPI_I2S_INT_OVR: Overrun interrupt flag + * @arg SPI_INT_CRCE: CRC Error interrupt flag + * @arg SPI_INT_ME: Mode Error interrupt flag + * @arg I2S_INT_UDR: Underrun Error interrupt flag + * + * @retval SET or RESET + */ +uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) +{ + uint32_t intEnable; + uint32_t intStatus; + + intEnable = (uint32_t)(spi->CTRL2 & (flag>>8)); + intStatus = (uint32_t)(spi->STS & flag); + + if (intEnable && intStatus) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the SPIx CRC Error interrupt flag + * + * @param spi: The SPIx can be 1,2,3 + * + * @param flag: only clears SPI_INT_CRCE(CRC Error interrupt flag) + * + * @retval None + * + * @note 1)SPI_I2S_INT_OVR: (OverRun interrupt error) flag is cleared by software sequence: + * a read operation to SPI_DATA register (SPI_I2S_RxData()) + * followed by a read operation to SPI_STS register (SPI_I2S_ReadIntFlag()). + * 2)I2S_INT_UDR: (UnderRun interrupt error) flag is cleared: + * a read operation to SPI_STS register (SPI_I2S_ReadIntFlag()). + * 3)SPI_INT_ME: (Mode interrupt Fault) flag is cleared by software sequence: + * a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag()) + * followed by a write operation to SPI_CTRL1 register (SPI_Enable()). + */ +void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag) +{ + spi->STS_B.CRCEFLG = BIT_RESET; +} + +/**@} end of group SPI_Fuctions*/ +/**@} end of group SPI_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c new file mode 100644 index 0000000000..343cb19770 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c @@ -0,0 +1,2133 @@ +/*! + * @file apm32f10x_tmr.c + * + * @brief This file provides all the TMR firmware functions. + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_tmr.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup TMR_Driver TMR Driver + @{ +*/ + +/** @addtogroup TMR_Fuctions Fuctions + @{ +*/ + +static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); +static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter); + +/*! + * @brief Deinitializes the TMRx peripheral registers to their default reset values. + * + * @param tmr: Select TMRx peripheral, The x can be 1 to 8 + * + * @retval None + * + * @note + */ +void TMR_Reset(TMR_T* tmr) +{ + if (tmr == TMR1) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR1); + } + else if (tmr == TMR2) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR2); + } + else if (tmr == TMR3) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR3); + } + else if (tmr == TMR4) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR4); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR4); + } + else if (tmr == TMR5) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR5); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR5); + } + else if (tmr == TMR6) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR6); + } + else if (tmr == TMR7) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_TMR7); + } + else if (tmr == TMR8) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_TMR8); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_TMR8); + } +} + +/*! + * @brief Initializes the base timer through the structure + * + * @param tmr: Select TMRx peripheral, The x can be 1 to 8 + * + * @param baseConfig: Pointer to a TMR_BaseConfig_T structure + * + * @retval None + */ +void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig) +{ + uint16_t temp; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + temp = tmr->CTRL1; + temp &= 0x038F; + temp |= baseConfig->countMode; + tmr->CTRL1 = temp; + } + + if ((tmr != TMR6) && (tmr != TMR7)) + { + tmr->CTRL1_B.CLKDIV = baseConfig->clockDivision; + } + + tmr->AUTORLD = baseConfig->period; + tmr->PSC = baseConfig->division; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->REPCNT = baseConfig->repetitionCounter; + } + tmr->CEG_B.BEG = 0x01; +} + +/*! + * @brief Configure channel 1 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC1Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OC1Config) +{ + tmr->CCEN_B.CC1EN = BIT_RESET; + + tmr->CCM1_COMPARE_B.CC1SEL = BIT_RESET; + tmr->CCM1_COMPARE_B.OC1MOD = OC1Config->mode; + + tmr->CCEN_B.CC1POL = OC1Config->polarity; + tmr->CCEN_B.CC1EN = OC1Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CCEN_B.CC1NPOL = OC1Config->nPolarity; + tmr->CCEN_B.CC1NEN = OC1Config->outputNState; + + tmr->CTRL2_B.OC1OIS = BIT_RESET; + tmr->CTRL2_B.OC1NOIS = BIT_RESET; + tmr->CTRL2_B.OC1OIS = OC1Config->idleState; + tmr->CTRL2_B.OC1NOIS = OC1Config->nIdleState; + } + tmr->CC1 = OC1Config->pulse; +} + +/*! + * @brief Configure channel 2 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC2Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OC2Config) +{ + tmr->CCEN_B.CC2EN = BIT_RESET; + + tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; + tmr->CCM1_COMPARE_B.CC2SEL = BIT_RESET; + tmr->CCM1_COMPARE_B.OC2MOD = OC2Config->mode; + + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN_B.CC2POL = OC2Config->polarity; + tmr->CCEN_B.CC2EN = OC2Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CCEN_B.CC2NPOL = BIT_RESET; + tmr->CCEN_B.CC2NPOL = OC2Config->nPolarity; + + tmr->CCEN_B.CC2NEN = BIT_RESET; + tmr->CCEN_B.CC2NEN = OC2Config->outputNState; + + tmr->CTRL2_B.OC2OIS = BIT_RESET; + tmr->CTRL2_B.OC2NOIS = BIT_RESET; + tmr->CTRL2_B.OC2OIS = OC2Config->idleState; + tmr->CTRL2_B.OC2NOIS = OC2Config->nIdleState; + } + tmr->CC2 = OC2Config->pulse; +} + +/*! + * @brief Configure channel 3 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC3Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OC3Config) +{ + tmr->CCEN_B.CC3EN = BIT_RESET; + + tmr->CCM2_COMPARE_B.OC3MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.CC3SEL = BIT_RESET; + tmr->CCM2_COMPARE_B.OC3MODE = OC3Config->mode; + + tmr->CCEN_B.CC3POL = BIT_RESET; + tmr->CCEN_B.CC3POL = OC3Config->polarity; + tmr->CCEN_B.CC3EN = OC3Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CCEN_B.CC3NPOL = BIT_RESET; + tmr->CCEN_B.CC3NPOL = OC3Config->nPolarity; + tmr->CCEN_B.CC3NEN = BIT_RESET; + tmr->CCEN_B.CC3NEN = OC3Config->outputNState; + + tmr->CTRL2_B.OC3OIS = BIT_RESET; + tmr->CTRL2_B.OC3NOIS = BIT_RESET; + tmr->CTRL2_B.OC3OIS = OC3Config->idleState; + tmr->CTRL2_B.OC3NOIS = OC3Config->nIdleState; + } + tmr->CC3 = OC3Config->pulse; +} + +/*! + * @brief Configure channel 4 according to parameters + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OC4Config: Pointer to a TMR_OCConfig_T structure + * + * @retval None + */ +void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OC4Config) +{ + tmr->CCEN_B.CC4EN = BIT_RESET; + + tmr->CCM2_COMPARE_B.OC4MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.CC4SEL = BIT_RESET; + tmr->CCM2_COMPARE_B.OC4MODE = OC4Config->mode; + + tmr->CCEN_B.CC4POL = BIT_RESET; + tmr->CCEN_B.CC4POL = OC4Config->polarity; + tmr->CCEN_B.CC4EN = OC4Config->outputState; + + if ((tmr == TMR1) || (tmr == TMR8)) + { + tmr->CTRL2_B.OC4OIS = BIT_RESET; + tmr->CTRL2_B.OC4OIS = OC4Config->idleState; + } + tmr->CC4 = OC4Config->pulse; +} + +/*! + * @brief Configure Peripheral equipment + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICConfig: Pointer to a TMR_ICConfig_T structure + * + * @retval None + */ +void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig) +{ + if (ICConfig->channel == TMR_CHANNEL_1) + { + TI1Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC1Prescal(tmr, ICConfig->prescaler); + } + else if (ICConfig->channel == TMR_CHANNEL_2) + { + TI2Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC2Prescal(tmr, ICConfig->prescaler); + } + else if (ICConfig->channel == TMR_CHANNEL_3) + { + TI3Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC3Prescal(tmr, ICConfig->prescaler); + } + else if (ICConfig->channel == TMR_CHANNEL_4) + { + TI4Config(tmr, ICConfig->polarity, ICConfig->selection, ICConfig->filter); + TMR_ConfigIC4Prescal(tmr, ICConfig->prescaler); + } +} + +/*! + * @brief Configures the: Break feature, dead time, Lock level, the IMOS + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param BDTConfig: Pointer to a TMR_BDTConfig_T structure + * + * @retval None + */ +void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig) +{ + tmr->BDT = (BDTConfig->IMOS)<<10 |\ + (BDTConfig->RMOS)<<11 |\ + (BDTConfig->lockLevel)<<8 |\ + (BDTConfig->deadTime) |\ + (BDTConfig->BRKState)<<12 |\ + (BDTConfig->BRKPolarity)<<13 |\ + (BDTConfig->automaticOutput)<<14; +} + +/*! + * @brief Initialize the Base timer with its default value. + * + * @param baseConfig: pointer to a TMR_BaseConfig_T + * + * @retval None + */ +void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig) +{ + baseConfig->period = 0xFFFF; + baseConfig->division = 0x0000; + baseConfig->clockDivision = TMR_CLOCK_DIV_1; + baseConfig->countMode = TMR_COUNTER_MODE_UP; + baseConfig->repetitionCounter = 0x0000; +} + +/*! + * @brief Initialize the OC timer with its default value. + * + * @param OCConfig: pointer to a TMR_OCConfig_T + * + * @retval None + */ +void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig) +{ + OCConfig->mode = TMR_OC_MODE_TMRING; + OCConfig->outputState = TMR_OC_STATE_DISABLE; + OCConfig->outputNState = TMR_OC_NSTATE_DISABLE; + OCConfig->pulse = 0x0000; + OCConfig->polarity = TMR_OC_POLARITY_HIGH; + OCConfig->nPolarity = TMR_OC_NPOLARITY_HIGH; + OCConfig->idleState = TMR_OC_IDLE_STATE_RESET; + OCConfig->nIdleState = TMR_OC_NIDLE_STATE_RESET; +} + +/*! + * @brief Initialize the IC timer with its default value. + * + * @param ICConfig: pointer to a TMR_ICConfig_T + * + * @retval None + */ +void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig) +{ + ICConfig->channel = TMR_CHANNEL_1; + ICConfig->polarity = TMR_IC_POLARITY_RISING; + ICConfig->selection = TMR_IC_SELECTION_DIRECT_TI; + ICConfig->prescaler = TMR_IC_PSC_1; + ICConfig->filter = 0x00; +} + +/*! + * @brief Initialize the BDT timer with its default value. + * + * @param BDTConfig: pointer to a TMR_BDTConfig_T + * + * @retval None + */ +void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig) +{ + BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE; + BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE; + BDTConfig->lockLevel = TMR_LOCK_LEVEL_OFF; + BDTConfig->deadTime = 0x00; + BDTConfig->BRKState = TMR_BRK_STATE_DISABLE; + BDTConfig->BRKPolarity = TMR_BRK_POLARITY_LOW; + BDTConfig->automaticOutput = TMR_AUTOMATIC_OUTPUT_DISABLE; +} + +/*! + * @brief Enable the specified TMR peripheral + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_Enable(TMR_T* tmr) +{ + tmr->CTRL1_B.CNTEN = ENABLE; +} + +/*! + * @brief Disable the specified TMR peripheral + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_Disable(TMR_T* tmr) +{ + tmr->CTRL1_B.CNTEN = DISABLE; +} + +/*! + * @brief Config of TMR to PWM + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param PWMConfig: pointer to a TMR_ICConfig_T + * + * @retval None + */ +void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig) +{ + uint16_t icpolarity = TMR_IC_POLARITY_RISING; + uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI; + + if (PWMConfig->polarity == TMR_IC_POLARITY_RISING) + { + icpolarity = TMR_IC_POLARITY_FALLING; + } + else + { + icpolarity = TMR_IC_POLARITY_RISING; + } + + if (PWMConfig->selection == TMR_IC_SELECTION_DIRECT_TI) + { + icselection = TMR_IC_SELECTION_INDIRECT_TI; + } + else + { + icselection = TMR_IC_SELECTION_DIRECT_TI; + } + + if (PWMConfig->channel == TMR_CHANNEL_1) + { + TI1Config(tmr, PWMConfig->polarity, PWMConfig->selection, PWMConfig->filter); + TMR_ConfigIC1Prescal(tmr, PWMConfig->prescaler); + TI2Config(tmr, icpolarity, icselection, PWMConfig->filter); + TMR_ConfigIC2Prescal(tmr, PWMConfig->prescaler); + } + else + { + TI2Config(tmr, PWMConfig->polarity, PWMConfig->selection, PWMConfig->filter); + TMR_ConfigIC2Prescal(tmr, PWMConfig->prescaler); + TI1Config(tmr, icpolarity, icselection, PWMConfig->filter); + TMR_ConfigIC1Prescal(tmr, PWMConfig->prescaler); + } +} + +/*! + * @brief Enable TMRx PWM output + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_EnablePWMOutputs(TMR_T* tmr) +{ + tmr->BDT_B.MOEN = ENABLE; +} + +/*! + * @brief Disable TMRx PWM output. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_DisablePWMOutputs(TMR_T* tmr) +{ + tmr->BDT_B.MOEN = DISABLE; +} + +/*! + * @brief Configures the TMRx's DMA interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param baseAddress: pointer to a TMR_DMA_BASE_T + * + * @param burstLength: pointer to a TMR_DMA_BURSTLENGTH_T + * + * @retval None + */ +void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength) +{ + tmr->DCTRL = baseAddress | burstLength; +} + +/*! + * @brief Enable TMRx Requests. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param souces: specifies the TMR DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces + * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces + * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces + * @retval None + * + * @note + */ +void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource) +{ + tmr->DIEN |= dmaSource; +} + +/*! + * @brief Disable TMRx Requests. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param souces: specifies the TMR DMA souces + * The parameter can be any combination of following values: + * @arg TMR_DMA_SOURCE_UPDATE: TMR update DMA souces + * @arg TMR_DMA_SOURCE_CC1: TMR Capture Compare 1 DMA souces + * @arg TMR_DMA_SOURCE_CC2: TMR Capture Compare 2 DMA souces + * @arg TMR_DMA_SOURCE_CC3: TMR Capture Compare 3 DMA souces + * @arg TMR_DMA_SOURCE_CC4: TMR Capture Compare 4 DMA souces + * @arg TMR_DMA_SOURCE_COM: TMR Commutation DMA souces + * @arg TMR_DMA_SOURCE_TRG: TMR Trigger DMA souces + * @retval None + * + * @note + */ +void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource) +{ + tmr->DIEN &= ~dmaSource; +} + +/*! + * @brief Configures the TMRx internal Clock + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_ConfigInternalClock(TMR_T* tmr) +{ + tmr->SMCTRL_B.SMFSEL = DISABLE; +} + +/*! + * @brief Configures the TMRx Internal Trigger as External Clock + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param triggerSource: specifies the TMR trigger souces + * The parameter can be one of following values: + * @arg TMR_TRIGGER_SOURCE_ITR0: TMR Internal Trigger 0 + * @arg TMR_TRIGGER_SOURCE_ITR1: TMR Internal Trigger 1 + * @arg TMR_TRIGGER_SOURCE_ITR2: TMR Internal Trigger 2 + * @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3 + * @retval None + */ +void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) +{ + TMR_SelectInputTrigger(tmr, triggerSource); + tmr->SMCTRL_B.SMFSEL = 0x07; +} + +/*! + * @brief Configures the TMRx Trigger as External Clock + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param triggerSource: specifies the TMR trigger souces + * The parameter can be one of following values: + * @arg TMR_TRIGGER_SOURCE_TI1F_ED: TI1 Edge Detector + * @arg TMR_TRIGGER_SOURCE_TI1FP1: Filtered Timer Input 1 + * @arg TMR_TRIGGER_SOURCE_TI2FP2: Filtered Timer Input 2 + * + * @param ICpolarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_IC_POLARITY_RISING: TMR IC polarity rising + * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, + TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter) +{ + if (triggerSource == 0x06) + { + TI2Config(tmr, ICpolarity, TMR_IC_SELECTION_DIRECT_TI, ICfilter); + } + else + { + TI1Config(tmr, ICpolarity, TMR_IC_SELECTION_DIRECT_TI, ICfilter); + } + + TMR_SelectInputTrigger(tmr, triggerSource); + tmr->SMCTRL_B.SMFSEL = 0x07; +} + +/*! + * @brief Configures the External clock Mode1 + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the external Trigger Prescaler + * The parameter can be one of following values: + * @arg TMR_EXTTRG_PSC_OFF: ETRP Prescaler OFF + * @arg TMR_EXTTRG_PSC_DIV2: ETRP frequency divided by 2 + * @arg TMR_EXTTRG_PSC_DIV4: ETRP frequency divided by 4 + * @arg TMR_EXTTRG_PSC_DIV8: ETRP frequency divided by 8 + * + * @param polarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_EXTTRG_POL_INVERTED: Active low or falling edge active + * @arg TMR_EXTTGR_POL_NONINVERTED: Active high or rising edge active + * + * @param filter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter) +{ + TMR_ConfigETR(tmr, prescaler, polarity, filter); + tmr->SMCTRL_B.SMFSEL = BIT_RESET; + tmr->SMCTRL_B.SMFSEL = 0x07; + tmr->SMCTRL_B.TRGSEL = 0x07; +} + +/*! + * @brief Configures the External clock Mode2 + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the external Trigger Prescaler + * The parameter can be one of following values: + * @arg TMR_EXTTRG_PSC_OFF: ETRP Prescaler OFF + * @arg TMR_EXTTRG_PSC_DIV2: ETRP frequency divided by 2 + * @arg TMR_EXTTRG_PSC_DIV4: ETRP frequency divided by 4 + * @arg TMR_EXTTRG_PSC_DIV8: ETRP frequency divided by 8 + * + * @param polarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_EXTTRG_POL_INVERTED: Active low or falling edge active + * @arg TMR_EXTTGR_POL_NONINVERTED: Active high or rising edge active + * + * @param filter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter) +{ + TMR_ConfigETR(tmr, prescaler, polarity, filter); + tmr->SMCTRL_B.ECEN = ENABLE; +} +/*! + * @brief Configures the TMRx External Trigger (ETR). + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the external Trigger Prescaler + * The parameter can be one of following values: + * @arg TMR_EXTTRG_PSC_OFF: ETRP Prescaler OFF + * @arg TMR_EXTTRG_PSC_DIV2: ETRP frequency divided by 2 + * @arg TMR_EXTTRG_PSC_DIV4: ETRP frequency divided by 4 + * @arg TMR_EXTTRG_PSC_DIV8: ETRP frequency divided by 8 + * + * @param polarity: specifies the TMR IC polarity + * The parameter can be one of following values: + * @arg TMR_EXTTRG_POL_INVERTED: Active low or falling edge active + * @arg TMR_EXTTGR_POL_NONINVERTED: Active high or rising edge active + * + * @param filter: This parameter must be a value between 0x00 and 0x0F. + * + * @retval None + */ +void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, + TMR_EXTTRG_POL_T polarity, uint16_t filter) +{ + tmr->SMCTRL &= 0x00FF; + tmr->SMCTRL_B.ETPCFG = prescaler; + tmr->SMCTRL_B.ETPOL = polarity; + tmr->SMCTRL_B.ETFCFG = filter; +} + +/*! + * @brief Configures the TMRx prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the prescaler Register value + * + * @param pscReloadMode: specifies the TMR prescaler Reload mode + * The parameter can be one of following values: + * @arg TMR_PRESCALER_RELOAD_UPDATA: The Prescaler is loaded at the update event + * @arg TMR_PRESCALER_RELOAD_IMMEDIATE: The Prescaler is loaded immediately + * @retval None + */ +void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode) +{ + tmr->PSC = prescaler; + tmr->CEG_B.UEG = pscReloadMode; +} + +/*! + * @brief Config counter mode + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param countMode:specifies the Counter Mode to be used + * The parameter can be one of following values: + * @arg TMR_COUNTER_MODE_UP: Timer Up Counting Mode + * @arg TMR_COUNTER_MODE_DOWN: Timer Down Counting Mode + * @arg TMR_COUNTER_MODE_CENTERALIGNED1: Timer Center Aligned Mode1 + * @arg TMR_COUNTER_MODE_CENTERALIGNED2: Timer Center Aligned Mode2 + * @arg TMR_COUNTER_MODE_CENTERALIGNED3: Timer Center Aligned Mode3 + * @retval None + */ +void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode) +{ + tmr->CTRL1_B.CNTDIR = BIT_RESET; + tmr->CTRL1_B.CAMSEL = BIT_RESET; + tmr->CTRL1 |= countMode; +} + +/*! + * @brief Selects the Input Trigger source + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param triggerSource: specifies the Input Trigger source + * The parameter can be one of following values: + * @arg TMR_TRIGGER_SOURCE_ITR0: Internal Trigger 0 + * @arg TMR_TRIGGER_SOURCE_ITR1: Internal Trigger 1 + * @arg TMR_TRIGGER_SOURCE_ITR2: Internal Trigger 2 + * @arg TMR_TRIGGER_SOURCE_ITR3: Internal Trigger 3 + * @arg TMR_TRIGGER_SOURCE_TI1F_ED: TI1 Edge Detector + * @arg TMR_TRIGGER_SOURCE_TI1FP1: Filtered Timer Input 1 + * @arg TMR_TRIGGER_SOURCE_TI2FP2: Filtered Timer Input 2 + * @arg TMR_TRIGGER_SOURCE_ETRF: External Trigger input + * + * @retval None + */ +void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource) +{ + tmr->SMCTRL_B.TRGSEL = BIT_RESET; + tmr->SMCTRL_B.TRGSEL = triggerSource; +} + +/*! + * @brief Configures the Encoder Interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param encodeMode: specifies the Encoder Mode + * The parameter can be one of following values: + * @arg TMR_ENCODER_MODE_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level + * @arg TMR_ENCODER_MODE_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level + * @arg TMR_ENCODER_MODE_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input + * + * @param IC1Polarity: specifies the TMR IC1 polarity + * The parameter can be one of following values: + * @arg TMR_IC_POLARITY_RISING: TMR IC polarity rising + * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling + * + * @param IC2Polarity: specifies the TMR IC2 polarity + * The parameter can be one of following values: + * @arg TMR_IC_POLARITY_RISING: TMR IC polarity rising + * @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling + * @retval None + */ +void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, + TMR_IC_POLARITY_T IC2Polarity) +{ + tmr->SMCTRL_B.SMFSEL = BIT_RESET; + tmr->SMCTRL_B.SMFSEL = encodeMode; + + tmr->CCM1_CAPTURE_B.CC1SEL = BIT_RESET ; + tmr->CCM1_CAPTURE_B.CC2SEL = BIT_RESET ; + tmr->CCM1_CAPTURE_B.CC1SEL = 0x01 ; + tmr->CCM1_CAPTURE_B.CC2SEL = 0x01 ; + + tmr->CCEN_B.CC1POL = BIT_RESET; + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN |= ((IC1Polarity | (IC2Polarity << 4))); +} + +/*! + * @brief Forces the output 1 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * @retval None + */ +void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM1_COMPARE_B.OC1MOD = BIT_RESET; + tmr->CCM1_COMPARE_B.OC1MOD = forcesAction; +} + +/*! + * @brief Forces the output 2 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * @retval None + */ +void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET; + tmr->CCM1_COMPARE_B.OC2MOD = forcesAction; +} + +/*! + * @brief Forces the output 3 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * + * @retval None + */ +void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM2_COMPARE_B.OC3MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.OC3MODE = forcesAction; +} + +/*! + * @brief Forces the output 4 waveform to active or inactive level. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param forcesAction: specifies the forced Action to be set to the output waveform + * The parameter can be one of following values: + * @arg TMR_FORCED_ACTION_ACTIVE: Force active level on OC1REF + * @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF + * + * @retval None + */ +void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction) +{ + tmr->CCM2_COMPARE_B.OC4MODE = BIT_RESET; + tmr->CCM2_COMPARE_B.OC4MODE = forcesAction; +} + +/*! + * @brief Enables peripheral Preload register on AUTORLD. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_EnableAUTOReload(TMR_T* tmr) +{ + tmr->CTRL1_B.ARPEN = ENABLE; +} + +/*! + * @brief Disable peripheral Preload register on AUTORLD. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_DisableAUTOReload(TMR_T* tmr) +{ + tmr->CTRL1_B.ARPEN = DISABLE; +} + +/*! + * @brief Enable Selects the TMR peripheral Commutation event. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_EnableSelectCOM(TMR_T* tmr) +{ + tmr->CTRL2_B.CCUSEL = ENABLE; +} +/*! + * @brief Disable Selects the TMR peripheral Commutation event. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_DisableSelectCOM(TMR_T* tmr) +{ + tmr->CTRL2_B.CCUSEL = DISABLE; +} + +/*! + * @brief Enable Capture Compare DMA source. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_EnableCCDMA(TMR_T* tmr) +{ + tmr->CTRL2_B.CCDSEL = ENABLE; +} + +/*! + * @brief Disable Capture Compare DMA source. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_DisableCCDMA(TMR_T* tmr) +{ + tmr->CTRL2_B.CCDSEL = DISABLE; +} + +/*! + * @brief Enable Capture Compare Preload Control bit. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_EnableCCPreload(TMR_T* tmr) +{ + tmr->CTRL2_B.CCPEN = ENABLE; +} + +/*! + * @brief Disable Capture Compare Preload Control bit. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @retval None + */ +void TMR_DisableCCPreload(TMR_T* tmr) +{ + tmr->CTRL2_B.CCPEN = DISABLE; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM1. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + */ +void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM1_COMPARE_B.OC1PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM2. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + */ +void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM1_COMPARE_B.OC2PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM3. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval None + */ +void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM2_COMPARE_B.OC3PEN = OCPreload; +} + +/*! + * @brief Enables or disables the peripheral Preload register on CCM4. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCPreload: specifies the Output Compare Channel Preload + * The parameter can be one of following values: + * @arg TMR_OC_PRELOAD_DISABLE + * @arg TMR_OC_PRELOAD_ENABLE + * @retval Nonee + */ +void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload) +{ + tmr->CCM2_COMPARE_B.OC4PEN = OCPreload; +} + +/*! + * @brief Configures the Output Compare 1 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM1_COMPARE_B.OC1FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 2 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM1_COMPARE_B.OC2FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 2 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM2_COMPARE_B.OC3FEN = OCFast; +} + +/*! + * @brief Configures the Output Compare 4 Fast feature. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCFast: specifies the Output Compare Channel Fast + * The parameter can be one of following values: + * @arg TMR_OC_FAST_DISABLE + * @arg TMR_OC_FAST_ENABLE + * @retval None + */ +void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast) +{ + tmr->CCM2_COMPARE_B.OC4FEN = OCFast; +} + +/*! + * @brief Clears or safeguards the OCREF1 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM1_COMPARE_B.OC1CEN = OCClear; +} + +/*! + * @brief Clears or safeguards the OCREF2 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM1_COMPARE_B.OC2CEN = OCClear; +} + +/*! + * @brief Clears or safeguards the OCREF3 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM2_COMPARE_B.OC3CEN = OCClear; +} + +/*! + * @brief Clears or safeguards the OCREF4 signal on an external event + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param OCClear: specifies the Output Compare Channel1 Clear + * The parameter can be one of following values: + * @arg TMR_OC_CLEAR_DISABLE + * @arg TMR_OC_CLEAR_ENABLE + * @retval None + */ +void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear) +{ + tmr->CCM2_COMPARE_B.OC4CEN = OCClear; +} + +/*! + * @brief Configures the channel 1 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC1 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval Nonee + */ +void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC1POL = polarity; +} + +/*! + * @brief Configures the channel 1 nPolarity. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param nPolarity: specifies the OC1 nPolarity + * The parameter can be one of following values: + * @arg TMR_OC_NPOLARITY_HIGH: Output Compare active high + * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +{ + tmr->CCEN_B.CC1NPOL = nPolarity; +} + +/*! + * @brief Configures the channel 2 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC2 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC2POL = polarity; +} + +/*! + * @brief Configures the channel 2 nPolarity. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param nPolarity: specifies the OC2 nPolarity + * The parameter can be one of following values: + * @arg TMR_OC_NPOLARITY_HIGH: Output Compare active high + * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +{ + tmr->CCEN_B.CC2NPOL = nPolarity; +} + +/*! + * @brief Configures the channel 3 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC3 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC3POL = polarity; +} + +/*! + * @brief Configures the channel 3 nPolarity. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param nPolarity: specifies the OC3 nPolarity + * The parameter can be one of following values: + * @arg TMR_OC_NPOLARITY_HIGH: Output Compare active high + * @arg TMR_OC_NPOLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity) +{ + tmr->CCEN_B.CC3NPOL = nPolarity; +} + +/*! + * @brief Configures the channel 4 polarity. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param polarity: specifies the OC4 Polarity + * The parameter can be one of following values: + * @arg TMR_OC_POLARITY_HIGH: Output Compare active high + * @arg TMR_OC_POLARITY_LOW: Output Compare active low + * @retval None + */ +void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity) +{ + tmr->CCEN_B.CC4POL = polarity; +} + +/*! + * @brief Enables the Capture Compare Channel x. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @arg TMR_CHANNEL_4: Timer Channel 4 + * @retval None + */ +void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN |= BIT_SET << channel; +} + +/*! + * @brief Disables the Capture Compare Channel x. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @arg TMR_CHANNEL_4: Timer Channel 4 + * @retval None + */ +void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN &= BIT_RESET << channel; +} + +/*! + * @brief Enables the Capture Compare Channelx N. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @retval None + */ +void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN |= 0x04 << channel; +} + +/*! + * @brief Disables the Capture Compare Channelx N. + * + * @param tmr: The TMRx it can be TMR1 and TMR8 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @retval None + */ +void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel) +{ + tmr->CCEN &= BIT_RESET << channel; +} + +/*! + * @brief Selects the Output Compare Mode. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param channel: specifies the Channel + * The parameter can be one of following values: + * @arg TMR_CHANNEL_1: Timer Channel 1 + * @arg TMR_CHANNEL_2: Timer Channel 2 + * @arg TMR_CHANNEL_3: Timer Channel 3 + * @arg TMR_CHANNEL_4: Timer Channel 4 + * + * @param mode: specifies the Output Compare Mode + * The parameter can be one of following values: + * @arg TMR_OC_MODE_TMRING + * @arg TMR_OC_MODE_ACTIVE + * @arg TMR_OC_MODE_INACTIVE + * @arg TMR_OC_MODE_TOGGEL + * @arg TMR_OC_MODE_LOWLEVEL + * @arg TMR_OC_MODE_HIGHLEVEL + * @arg TMR_OC_MODE_PWM1 + * @arg TMR_OC_MODE_PWM2 + * @retval None + */ +void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode) +{ + tmr->CCEN &= BIT_RESET << channel; + + if (channel == TMR_CHANNEL_1) + { + tmr->CCM1_COMPARE_B.OC1MOD = mode; + } + else if (channel == TMR_CHANNEL_2) + { + tmr->CCM1_COMPARE_B.OC2MOD = mode; + } + else if (channel == TMR_CHANNEL_3) + { + tmr->CCM2_COMPARE_B.OC3MODE = mode; + } + else if (channel == TMR_CHANNEL_4) + { + tmr->CCM2_COMPARE_B.OC4MODE = mode; + } +} + +/*! + * @brief Enable the TMRx update event + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_EnableNoUpdate(TMR_T* tmr) +{ + tmr->CTRL1_B.UD = ENABLE; +} + +/*! + * @brief Disable the TMRx update event + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval None + */ +void TMR_DisableNoUpdate(TMR_T* tmr) +{ + tmr->CTRL1_B.UD = DISABLE; +} + +/*! + * @brief Configures the Update Request Interrupt source + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param updateSource: Config the Update source + * The parameter can be one of following values: + * @arg TMR_UPDATE_SOURCE_GLOBAL + * @arg TMR_UPDATE_SOURCE_REGULAR + * @retval None + */ +void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource) +{ + if (updateSource != TMR_UPDATE_SOURCE_GLOBAL) + { + tmr->CTRL1_B.URSSEL = BIT_SET; + } + else + { + tmr->CTRL1_B.URSSEL = BIT_RESET; + } +} + +/*! + * @brief Enables Hall sensor interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_EnableHallSensor(TMR_T* tmr) +{ + tmr->CTRL2_B.TI1SEL = ENABLE; +} + +/*! + * @brief Disable Hall sensor interface. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_DisableHallSensor(TMR_T* tmr) +{ + tmr->CTRL2_B.TI1SEL = DISABLE; +} + +/*! + * @brief Selects the Sing pulse Mode. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param singlePulseMode: specifies the Single Pulse Mode + * The parameter can be one of following values: + * @arg TMR_SPM_REPETITIVE + * @arg TMR_SPM_SINGLE + * @retval None + */ +void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode) +{ + tmr->CTRL1_B.SPMEN = singlePulseMode; +} + +/*! + * @brief Selects the Trigger Output Mode. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param TRGOSource: specifies the Trigger Output source + * The parameter can be one of following values: + * @arg TMR_TRGO_SOURCE_RESET + * @arg TMR_TRGO_SOURCE_ENABLE + * @arg TMR_TRGO_SOURCE_UPDATE + * The under is not for TMR6 and TMR7 + * @arg TMR_TRGO_SOURCE_OC1 + * @arg TMR_TRGO_SOURCE_OC1REF + * @arg TMR_TRGO_SOURCE_OC2REF + * @arg TMR_TRGO_SOURCE_OC3REF + * @arg TMR_TRGO_SOURCE_OC4REF + * @retval None + */ +void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource) +{ + tmr->CTRL2_B.MMSEL = TRGOSource; +} + +/*! + * @brief Selects the Slave Mode. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param slaveMode: specifies the Timer Slave Mode. + * The parameter can be one of following values: + * @arg TMR_SLAVE_MODE_RESET + * @arg TMR_SLAVE_MODE_GATED + * @arg TMR_SLAVE_MODE_TRIGGER + * @arg TMR_SLAVE_MODE_EXTERNALL + * @retval None + */ +void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode) +{ + tmr->SMCTRL_B.SMFSEL = slaveMode; +} + +/*! + * @brief Enable the Master Slave Mode + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_EnableMasterSlaveMode(TMR_T* tmr) +{ + tmr->SMCTRL_B.MSMEN = ENABLE; +} + +/*! + * @brief Disable the Master Slave Mode + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval None + */ +void TMR_DisableMasterSlaveMode(TMR_T* tmr) +{ + tmr->SMCTRL_B.MSMEN = DISABLE; +} + +/*! + * @brief Configs the Counter Register value + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param counter: Counter register new value + * + * @retval None + */ +void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter) +{ + tmr->CNT = counter; +} + +/*! + * @brief Configs the AutoReload Register value + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param autoReload: autoReload register new value + * + * @retval None + */ +void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload) +{ + tmr->AUTORLD = autoReload; +} + +/*! + * @brief Configs the Capture Compare1 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare1: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1) +{ + tmr->CC1 = compare1; +} + +/*! + * @brief Configs the Capture Compare2 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare2: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2) +{ + tmr->CC2 = compare2; +} + +/*! + * @brief Configs the Capture Compare3 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare3: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3) +{ + tmr->CC3 = compare3; +} + +/*! + * @brief Configs the Capture Compare4 Register value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param compare4: specifies the Capture Compare1 value. + * + * @retval None + */ +void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4) +{ + tmr->CC4 = compare4; +} + +/*! + * @brief Configs the TMRx Input Capture 1 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel1 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM1_CAPTURE_B.IC1PSC = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC1PSC = prescaler; +} +/*! + * @brief Sets the TMRx Input Capture 2 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel2 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM1_CAPTURE_B.IC2PSC = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC2PSC = prescaler; +} + +/*! + * @brief Configs the TMRx Input Capture 3 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel3 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM2_CAPTURE_B.IC3PSC = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC3PSC = prescaler; +} + +/*! + * @brief Configs the TMRx Input Capture 4 prescaler. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param prescaler: specifies the Input Capture Channel4 Perscaler + * The parameter can be one of following values: + * @arg TMR_IC_PSC_1: no prescaler + * @arg TMR_IC_PSC_2: capture is done once every 2 events + * @arg TMR_IC_PSC_4: capture is done once every 4 events + * @arg TMR_IC_PSC_8: capture is done once every 8 events + * @retval None + */ +void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler) +{ + tmr->CCM2_CAPTURE_B.IC4PSC = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC4PSC = prescaler; +} + +/*! + * @brief Configs the Clock Division value + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param clockDivision: specifies the clock division value. + * The parameter can be one of following values: + * @arg TMR_CLOCK_DIV_1: TDTS = Tck_tim + * @arg TMR_CLOCK_DIV_2: TDTS = 2*Tck_tim + * @arg TMR_CLOCK_DIV_4: TDTS = 4*Tck_tim + * @retval None + */ +void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision) +{ + tmr->CTRL1_B.CLKDIV = clockDivision; +} + +/*! + * @brief Read Input Capture 1 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 1 Register value. + */ +uint16_t TMR_ReadCaputer1(TMR_T* tmr) +{ + return tmr->CC1; +} + +/*! + * @brief Read Input Capture 2 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 2 Register value. + */ +uint16_t TMR_ReadCaputer2(TMR_T* tmr) +{ + return tmr->CC2; +} + +/*! + * @brief Read Input Capture 3 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 3 Register value. + */ +uint16_t TMR_ReadCaputer3(TMR_T* tmr) +{ + return tmr->CC3; +} + +/*! + * @brief Read Input Capture 4 value. + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @retval Capture Compare 4 Register value. + */ +uint16_t TMR_ReadCaputer4(TMR_T* tmr) +{ + return tmr->CC4; +} + +/*! + * @brief Read the TMRx Counter value. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval Counter Register value. + */ +uint16_t TMR_ReadCounter(TMR_T* tmr) +{ + return tmr->CNT; +} + +/*! + * @brief Read the TMRx Prescaler value. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @retval Prescaler Register value. + */ +uint16_t TMR_ReadPrescaler(TMR_T* tmr) +{ + return tmr->PSC; +} + +/*! + * @brief Enable intterupts + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt) +{ + tmr->DIEN |= interrupt; +} + +/*! + * @brief Disable intterupts + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt) +{ + tmr->DIEN &= ~interrupt; +} + +/*! + * @brief Configures the TMRx event to be generate by software. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param eventSources: specifies the TMR event sources + * The parameter can be any combination of following values: + * @arg TMR_EVENT_UPDATE: Timer update Interrupt source + * @arg TMR_EVENT_CC1: Timer Capture Compare 1 Event source + * @arg TMR_EVENT_CC2: Timer Capture Compare 1 Event source + * @arg TMR_EVENT_CC3: Timer Capture Compare 3 Event source + * @arg TMR_EVENT_CC4: Timer Capture Compare 4 Event source + * @arg TMR_EVENT_COM: Timer Commutation Event source (Only for TMR1 and TMR8) + * @arg TMR_EVENT_TRG: Timer Trigger Event source + * @arg TMR_EVENT_BRK: Timer Break Event source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE. + */ +void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources) +{ + tmr->CEG = eventSources; +} + +/*! + * @brief Check whether the flag is set or reset + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_FLAG_UPDATE: Timer update Flag + * @arg TMR_FLAG_CC1: Timer Capture Compare 1 Flag + * @arg TMR_FLAG_CC2: Timer Capture Compare 2 Flag + * @arg TMR_FLAG_CC3: Timer Capture Compare 3 Flag + * @arg TMR_FLAG_CC4: Timer Capture Compare 4 Flag + * @arg TMR_FLAG_COM: Timer Commutation Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_TRG: Timer Trigger Flag + * @arg TMR_FLAG_BRK: Timer Break Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_CC1RC: Timer Capture Compare 1 Repetition Flag + * @arg TMR_FLAG_CC2RC: Timer Capture Compare 2 Repetition Flag + * @arg TMR_FLAG_CC3RC: Timer Capture Compare 3 Repetition Flag + * @arg TMR_FLAG_CC4RC: Timer Capture Compare 4 Repetition Flag + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. + */ +uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag) +{ + if ((tmr->STS & flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the TMR's pending flags. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination of following values: + * @arg TMR_FLAG_UPDATE: Timer update Flag + * @arg TMR_FLAG_CC1: Timer Capture Compare 1 Flag + * @arg TMR_FLAG_CC2: Timer Capture Compare 2 Flag + * @arg TMR_FLAG_CC3: Timer Capture Compare 3 Flag + * @arg TMR_FLAG_CC4: Timer Capture Compare 4 Flag + * @arg TMR_FLAG_COM: Timer Commutation Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_TRG: Timer Trigger Flag + * @arg TMR_FLAG_BRK: Timer Break Flag (Only for TMR1 and TMR8) + * @arg TMR_FLAG_CC1RC: Timer Capture Compare 1 Repetition Flag + * @arg TMR_FLAG_CC2RC: Timer Capture Compare 2 Repetition Flag + * @arg TMR_FLAG_CC3RC: Timer Capture Compare 3 Repetition Flag + * @arg TMR_FLAG_CC4RC: Timer Capture Compare 4 Repetition Flag + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE. + */ +void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag) +{ + tmr->STS = ~flag; +} + +/*! + * @brief Check whether the ITflag is set or reset + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be one of following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag) +{ + if (((tmr->STS & flag) != RESET ) && ((tmr->DIEN & flag) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/*! + * @brief Clears the TMR's interrupt pending bits. + * + * @param tmr: The TMRx can be 1 to 8 + * + * @param interrupt: specifies the TMR interrupts sources + * The parameter can be any combination following values: + * @arg TMR_INT_UPDATE: Timer update Interrupt source + * @arg TMR_INT_CC1: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC2: Timer Capture Compare 1 Interrupt source + * @arg TMR_INT_CC3: Timer Capture Compare 3 Interrupt source + * @arg TMR_INT_CC4: Timer Capture Compare 4 Interrupt source + * @arg TMR_INT_COM: Timer Commutation Interrupt source (Only for TMR1 and TMR8) + * @arg TMR_INT_TRG: Timer Trigger Interrupt source + * @arg TMR_INT_BRK: Timer Break Interrupt source (Only for TMR1 and TMR8) + * @retval None + * + * @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE. + */ +void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag) +{ + tmr->STS = ~flag; +} + +/*! + * @brief Configure the TI1 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC1EN = BIT_RESET; + + tmr->CCM1_CAPTURE_B.CC1SEL = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC1F = BIT_RESET; + tmr->CCM1_CAPTURE_B.CC1SEL = ICselection; + tmr->CCM1_CAPTURE_B.IC1F = ICfilter; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + tmr->CCEN_B.CC1POL = BIT_RESET; + tmr->CCEN_B.CC1EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= ICpolarity; + tmr->CCEN = tmpchctrl; + } + else + { + tmr->CCEN_B.CC1POL = BIT_RESET; + tmr->CCEN_B.CC1NPOL = BIT_RESET; + tmr->CCEN_B.CC1EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= ICpolarity; + tmr->CCEN = tmpchctrl; + } +} + +/*! + * @brief Configure the TI2 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC2EN = BIT_RESET; + + tmr->CCM1_CAPTURE_B.CC2SEL = BIT_RESET; + tmr->CCM1_CAPTURE_B.IC2F = BIT_RESET; + tmr->CCM1_CAPTURE_B.CC2SEL = ICselection; + tmr->CCM1_CAPTURE_B.IC2F = ICfilter; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN_B.CC2EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 4); + tmr->CCEN = tmpchctrl; + } + else + { + tmr->CCEN_B.CC2POL = BIT_RESET; + tmr->CCEN_B.CC2NPOL = BIT_RESET; + tmr->CCEN_B.CC2EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 4); + tmr->CCEN = tmpchctrl; + } +} + +/*! + * @brief Configure the TI3 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC3EN = BIT_RESET; + + tmr->CCM2_CAPTURE_B.CC3SEL = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC3F = BIT_RESET; + tmr->CCM2_CAPTURE_B.CC3SEL = ICselection; + tmr->CCM2_CAPTURE_B.IC3F = ICfilter; + + if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) || + (tmr == TMR4) || (tmr == TMR5)) + { + tmr->CCEN_B.CC3POL = BIT_RESET; + tmr->CCEN_B.CC3EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 8); + tmr->CCEN = tmpchctrl; + } + else + { + tmr->CCEN_B.CC3POL = BIT_RESET; + tmr->CCEN_B.CC3NPOL = BIT_RESET; + tmr->CCEN_B.CC3EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 8); + tmr->CCEN = tmpchctrl; + } +} + +/*! + * @brief Configure the TI4 as Input + * + * @param tmr: The TMRx can be 1 to 8 except 6 and 7 + * + * @param ICpolarity: pointer to a TMR_IC_POLARITY_T + * + * @param ICselection: pointer to a TMR_IC_SELECTION_T + * + * @param ICfilter: This parameter must be a value between 0x00 and 0x0F + * + * @retval None + */ +static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter) +{ + uint16_t tmpchctrl = 0; + + tmr->CCEN_B.CC4EN = BIT_RESET; + + tmr->CCM2_CAPTURE_B.CC4SEL = BIT_RESET; + tmr->CCM2_CAPTURE_B.IC4F = BIT_RESET; + tmr->CCM2_CAPTURE_B.CC4SEL = ICselection; + tmr->CCM2_CAPTURE_B.IC4F = ICfilter; + + tmr->CCEN_B.CC4POL = BIT_RESET; + tmr->CCEN_B.CC4EN = BIT_SET; + tmpchctrl = tmr->CCEN; + tmpchctrl |= (ICpolarity << 12); + tmr->CCEN = tmpchctrl; +} + +/**@} end of group TMR_Fuctions*/ +/**@} end of group TMR_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c new file mode 100644 index 0000000000..23eb7fa355 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c @@ -0,0 +1,816 @@ +/*! + * @file apm32f10x_usart.c + * + * @brief This file provides all the USART firmware functions + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_usart.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup USART_Driver USART Driver + @{ +*/ + +/** @addtogroup USART_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset usart peripheral registers to their default reset values + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Reset(USART_T* usart) +{ + if (USART1 == usart) + { + RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_USART1); + RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_USART1); + } + else if (USART2 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART2); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART2); + } + else if (USART3 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_USART3); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_USART3); + } + else if (UART4 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_UART4); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_UART4); + } + else if (UART5 == usart) + { + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_UART5); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_UART5); + } +} + +/*! + * @brief Config the USART peripheral according to the specified parameters in the usartConfig + * + * @param uart: Select the USART or the UART peripheral + * + * @param usartConfig: pointer to a USART_Config_T structure + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Config(USART_T* uart, USART_Config_T* usartConfig) +{ + uint32_t temp, fCLK, intDiv, fractionalDiv; + + temp = uart->CTRL1; + temp &= 0xE9F3; + temp |= usartConfig->mode | usartConfig->parity | usartConfig->wordLength; + uart->CTRL1 = temp; + + temp = uart->CTRL2; + temp &= 0xCFFF; + temp |= usartConfig->stopBits; + uart->CTRL2 = temp; + + temp = uart->CTRL3; + temp &= 0xFCFF; + temp |= (uint32_t)usartConfig->hardwareFlow; + uart->CTRL3 = temp; + + if (uart == USART1) + { + RCM_ReadPCLKFreq(NULL, &fCLK); + } + else + { + RCM_ReadPCLKFreq(&fCLK, NULL); + } + + intDiv = ((25 * fCLK) / (4 * (usartConfig->baudRate))); + temp = (intDiv / 100) << 4; + fractionalDiv = intDiv - (100 * (temp >> 4)); + temp |= ((((fractionalDiv * 16) + 50) / 100)) & ((uint8_t)0x0F); + + uart->BR = temp; +} + +/*! + * @brief Fills each USART_InitStruct member with its default value + * + * @param usartConfig: pointer to a USART_Config_T structure which will be initialized + * + * @retval None + */ +void USART_ConfigStructInit(USART_Config_T* usartConfig) +{ + usartConfig->baudRate = 9600; + usartConfig->wordLength = USART_WORD_LEN_8B; + usartConfig->stopBits = USART_STOP_BIT_1; + usartConfig->parity = USART_PARITY_NONE ; + usartConfig->mode = USART_MODE_TX_RX; + usartConfig->hardwareFlow = USART_HARDWARE_FLOW_NONE; +} + +/*! + * @brief Configuration communication clock + * + * @param usart: Select the USART or the UART peripheral + * + * @param clockConfig: Pointer to a USART_clockConfig_T structure + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3 + */ +void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig) +{ + usart->CTRL2_B.CLKEN = clockConfig->clock; + usart->CTRL2_B.CPHA = clockConfig->phase; + usart->CTRL2_B.CPOL = clockConfig->polarity; + usart->CTRL2_B.LBCPOEN = clockConfig->lastBit; +} + +/*! + * @brief Fills each clockConfig member with its default value + * + * @param clockConfig: Pointer to a USART_clockConfig_T structure + * + * @retval None + * + * @note + */ +void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig) +{ + clockConfig->clock = USART_CLKEN_DISABLE; + clockConfig->phase = USART_CLKPHA_1EDGE; + clockConfig->polarity = USART_CLKPOL_LOW; + clockConfig->lastBit = USART_LBCP_DISABLE; +} + +/*! + * @brief Enables the specified USART peripheral + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Enable(USART_T* usart) +{ + usart->CTRL1_B.UEN = BIT_SET; +} + +/*! + * @brief Disable the specified USART peripheral + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Disable(USART_T* usart) +{ + usart->CTRL1_B.UEN = BIT_RESET; +} + +/*! + * @brief Enables the USART DMA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @param dmaReq: Specifies the DMA request + * This parameter can be one of the following values: + * @arg USART_DMA_TX: USART DMA receive request + * @arg USART_DMA_RX: USART DMA transmit request + * @arg USART_DMA_TX_RX: USART DMA transmit/receive request + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq) +{ + usart->CTRL3 |= dmaReq; +} + +/*! + * @brief Disable the USART DMA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @param dmaReq: Specifies the DMA request + * This parameter can be one of the following values: + * @arg USART_DMA_TX: USART DMA receive request + * @arg USART_DMA_RX: USART DMA transmit request + * @arg USART_DMA_TX_RX: USART DMA transmit/receive request + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq) +{ + usart->CTRL3 &= (uint32_t)~dmaReq; +} + +/*! + * @brief Configures the address of the USART node + * + * @param usart: Select the USART or the UART peripheral + * + * @param address: Indicates the address of the USART node + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_Address(USART_T* usart, uint8_t address) +{ + usart->CTRL2_B.ADDR = address; +} + +/*! + * @brief Selects the USART WakeUp method. + * + * @param usart: Select the USART or the UART peripheral + * + * @param wakeup: Specifies the selected USART auto baud rate method + * This parameter can be one of the following values: + * @arg USART_WAKEUP_IDLE_LINE: WakeUp by an idle line detection + * @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup) +{ + usart->CTRL1_B.WUPMCFG = wakeup; +} + +/*! + * @brief Enable USART Receiver in mute mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableMuteMode(USART_T* usart) +{ + usart->CTRL1_B.RXMUTEEN = BIT_SET; +} + +/*! + * @brief Disable USART Receiver in active mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableMuteMode(USART_T* usart) +{ + usart->CTRL1_B.RXMUTEEN = BIT_RESET; +} + +/*! + * @brief Sets the USART LIN Break detection length + * + * @param usart: Select the USART or the UART peripheral + * + * @param length: Specifies the LIN break detection length + * This parameter can be one of the following values: + * @arg USART_LBDL_10B: 10-bit break detection + * @arg USART_LBDL_10B: 11-bit break detection + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length) +{ + usart->CTRL2_B.LBDLCFG = length; +} + +/*! + * @brief Enables the USART LIN MODE + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableLIN(USART_T* usart) +{ + usart->CTRL2_B.LINMEN = BIT_SET; +} + +/*! + * @brief Disable the USART LIN MODE + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableLIN(USART_T* usart) +{ + usart->CTRL2_B.LINMEN = BIT_RESET; +} + +/*! + * @brief Transmitter Enable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableTx(USART_T* usart) +{ + usart->CTRL1_B.TXEN = BIT_SET; +} + +/*! + * @brief Transmitter Disable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableTx(USART_T* usart) +{ + usart->CTRL1_B.TXEN = BIT_RESET; +} + +/*! + * @brief Receiver enable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableRx(USART_T* usart) +{ + usart->CTRL1_B.RXEN = BIT_SET; +} + +/*! + * @brief Receiver disable + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableRx(USART_T* usart) +{ + usart->CTRL1_B.RXEN = BIT_RESET; +} + +/*! + * @brief Transmits single data + * + * @param usart: Select the USART or the UART peripheral + * + * @param data: the data to transmit + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_TxData(USART_T* usart, uint16_t data) +{ + usart->DATA_B.DATA = data; +} + +/*! + * @brief Returns the most recent received data + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +uint16_t USART_RxData(USART_T* usart) +{ + return (uint16_t)(usart->DATA_B.DATA); +} + +/*! + * @brief Transmits break characters + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_TxBreak(USART_T* usart) +{ + usart->CTRL1_B.TXBF = BIT_SET; +} + +/*! + * @brief Sets the specified USART guard time + * + * @param usart: Select the USART or the UART peripheral + * + * @param guardTime: Specifies the guard time + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3 + */ +void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime) +{ + usart->GTPSC_B.GRDT = guardTime; +} + +/*! + * @brief Sets the system clock divider number + * + * @param usart: Select the USART or the UART peripheral + * + * @param div: specifies the divider number + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3 + */ +void USART_ConfigPrescaler(USART_T* usart, uint8_t div) +{ + usart->GTPSC_B.PSC = div; +} + +/*! + * @brief Enables the USART Smart Card mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_EnableSmartCard(USART_T* usart) +{ + usart->CTRL3_B.SCEN = BIT_SET; +} + +/*! + * @brief Disable the USART Smart Card mode + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_DisableSmartCard(USART_T* usart) +{ + usart->CTRL3_B.SCEN = BIT_RESET; +} + +/*! + * @brief Enables NACK transmission + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_EnableSmartCardNACK(USART_T* usart) +{ + usart->CTRL3_B.SCNACKEN = BIT_SET; +} + +/*! + * @brief Disable NACK transmission + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The Smart Card mode is not available for UART4 and UART5 + */ +void USART_DisableSmartCardNACK(USART_T* usart) +{ + usart->CTRL3_B.SCNACKEN = BIT_RESET; +} + +/*! + * @brief Enables USART Half Duplex communication + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableHalfDuplex(USART_T* usart) +{ + usart->CTRL3_B.HDEN = BIT_SET; +} + +/*! + * @brief Disable USART Half Duplex communication + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableHalfDuplex(USART_T* usart) +{ + usart->CTRL3_B.HDEN = BIT_RESET; +} + +/*! + * @brief Configures the USART's IrDA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @param IrDAMode: Specifies the IrDA mode + * This parameter can be one of the following values: + * @arg USART_IRDALP_NORMAL: Normal + * @arg USART_IRDALP_LOWPOWER: Low-Power + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode) +{ + usart->CTRL3_B.IRLPEN = IrDAMode; +} + +/*! + * @brief Enables the USART's IrDA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableIrDA(USART_T* usart) +{ + usart->CTRL3_B.IREN = BIT_SET; +} + +/*! + * @brief Disable the USART's IrDA interface + * + * @param usart: Select the USART or the UART peripheral + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableIrDA(USART_T* usart) +{ + usart->CTRL3_B.IREN = BIT_RESET; +} + +/*! + * @brief Enable the specified USART interrupts + * + * @param usart: Select the USART or the UART peripheral + * + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_PE: Parity error interrupt + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt) +{ + uint32_t temp; + + temp = (uint32_t)(interrupt & 0xffff); + + if (interrupt & 0X10000) + { + usart->CTRL1 |= temp; + } + + if (interrupt & 0X20000) + { + usart->CTRL2 |= temp; + } + + if (interrupt & 0X40000) + { + usart->CTRL3 |= temp; + } +} + +/*! + * @brief Disables the specified USART interrupts + * + * @param usart: Select the USART or the UART peripheral + * + * @param interrupt: Specifies the USART interrupts sources + * The parameter can be one of following values: + * @arg USART_INT_PE: Parity error interrupt + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_ERR: Error interrupt(Frame error, noise error, overrun error) + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt) +{ + uint32_t temp; + + temp = (uint32_t)~(interrupt & 0xffff); + + if (interrupt & 0X10000) + { + usart->CTRL1 &= temp; + } + + if (interrupt & 0X20000) + { + usart->CTRL2 &= temp; + } + + if (interrupt & 0X40000) + { + usart->CTRL3 &= temp; + } +} + +/*! + * @brief Read the specified USART flag + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the flag to check + * The parameter can be one of following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXBE: Transmit data buffer empty flag + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_OVRE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * + * @retval The new state of flag (SET or RESET) + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag) +{ + return (usart->STS & flag) ? SET : RESET; +} + +/*! + * @brief Clears the USARTx's pending flags + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the flag to clear + * The parameter can be one of following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXC: Transmission Complete flag + * @arg USART_FLAG_RXBNE: Receive data buffer not empty flag + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag) +{ + usart->STS &= (uint32_t)~flag; +} + +/*! + * @brief Read the specified USART interrupt flag + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the USART interrupt source to check + * The parameter can be one of following values: + * @arg USART_INT_TXBE: Tansmit data buffer empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_IDLE: Idle line detection interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * @arg USART_INT_OVRE: OverRun Error interruptpt + * @arg USART_INT_NE: Noise Error interrupt + * @arg USART_INT_FE: Framing Error interrupt + * @arg USART_INT_PE: Parity error interrupt + * + * @retval The new state of flag (SET or RESET) + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag) +{ + uint32_t itFlag, srFlag; + + if (flag & 0x10000) + { + itFlag = usart->CTRL1 & flag & 0xffff; + } + else if (flag & 0x20000) + { + itFlag = usart->CTRL2 & flag & 0xffff; + } + else + { + itFlag = usart->CTRL3 & flag & 0xffff; + } + + srFlag = flag >> 24; + srFlag = (uint32_t)(1 << srFlag); + srFlag = usart->STS & srFlag; + + if (srFlag && itFlag) + { + return SET; + } + + return RESET; +} + +/*! + * @brief Clears the USART interrupt pending bits + * + * @param usart: Select the USART or the UART peripheral + * + * @param flag: Specifies the interrupt pending bit to clear + * The parameter can be one of following values: + * @arg USART_INT_RXBNE: Receive data buffer not empty interrupt + * @arg USART_INT_TXC: Transmission complete interrupt + * @arg USART_INT_LBD: LIN break detection interrupt + * @arg USART_INT_CTS: CTS change interrupt + * + * @retval None + * + * @note The usart can be USART1, USART2, USART3, UART4 and UART5 + */ +void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag) +{ + uint32_t srFlag; + + srFlag = flag >> 24; + srFlag = (uint32_t)(1 << srFlag); + + usart->STS &= (uint32_t)~srFlag; +} + +/**@} end of group USART_Fuctions*/ +/**@} end of group USART_Driver*/ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c new file mode 100644 index 0000000000..fb8fee5481 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usb.c @@ -0,0 +1,378 @@ +/*! + * @file apm32f10x_usb.c + * + * @brief This file contains all the functions for the USBD peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_usb.h" + +/*! + * @brief Set Endpoint type + * + * @param ep: Endpoint number + * + * @param type: Endpoint type + * + * @retval None + */ +void USBD_SetEPType(USBD_EP_T ep, USBD_EP_TYPE_T type) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_TYPE; + reg |= type << 9; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP kind + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_SetEPKind(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_KIND; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset EP kind + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPKind(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_KIND; + + USBD->EP[ep].EP = reg; +} + + +/*! + * @brief Reset EP CTFR bit + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPRxFlag(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_CTFR; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset EP CTFT bit + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetEPTxFlag(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_CTFT; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Toggle Tx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ToggleTx(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_TXDTOG; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Toggle Rx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ToggleRx(USBD_EP_T ep) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg |= USBD_EP_BIT_RXDTOG; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Reset Toggle Tx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetTxToggle(USBD_EP_T ep) +{ + if(USBD->EP[ep].EP_B.TXDTOG) + { + USBD_ToggleTx(ep); + } +} + +/*! + * @brief Reset Toggle Rx DTOG + * + * @param ep: Endpoint number + * + * @retval None + */ +void USBD_ResetRxToggle(USBD_EP_T ep) +{ + if(USBD->EP[ep].EP_B.RXDTOG) + { + USBD_ToggleRx(ep); + } +} + +/*! + * @brief Set EP address + * + * @param ep: Endpoint number + * + * @param addr: Address + * + * @retval None + */ +void USBD_SetEpAddr(USBD_EP_T ep, uint8_t addr) +{ + __IOM uint32_t reg; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT); + reg &= ~USBD_EP_BIT_ADDR; + reg |= addr; + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Tx status + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) +{ + __IOM uint32_t reg; + + status <<= 4; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_TXSTS); + reg ^= (status & USBD_EP_BIT_TXSTS); + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Rx status + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPRxStatus(USBD_EP_T ep, USBD_EP_STATUS_T status) +{ + __IOM uint32_t reg; + uint32_t tmp; + + tmp = status << 12; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS); + reg ^= (tmp & USBD_EP_BIT_RXSTS); + + USBD->EP[ep].EP = reg; +} + + +/*! + * @brief Set EP Rx and Txstatus + * + * @param ep: Endpoint number + * + * @param status: status + * + * @retval None + */ +void USBD_SetEPRxTxStatus(USBD_EP_T ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus) +{ + __IOM uint32_t reg; + uint32_t tmp; + + reg = USBD->EP[ep].EP; + + reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS | USBD_EP_BIT_TXSTS); + + tmp = rxStatus << 12; + reg ^= (tmp & USBD_EP_BIT_RXSTS); + + tmp = txStatus << 4; + reg ^= (tmp & USBD_EP_BIT_TXSTS); + + USBD->EP[ep].EP = reg; +} + +/*! + * @brief Set EP Rx Count + * + * @param ep: Endpoint number + * + * @param cnt: Rx count + * + * @retval None + */ +void USBD_SetEPRxCnt(USBD_EP_T ep, uint32_t cnt) +{ + __IOM uint32_t *p; + __IOM uint32_t block = 0; + + p = USBD_ReadEPRxCntPointer(ep); + + if(cnt > 62) + { + block = cnt >> 5; + + if(!(cnt & 0x1f)) + { + block -= 1; + } + + *p = (block << 10) | 0x8000; + } + else + { + block = cnt >> 1; + + if(cnt & 0x01) + { + block += 1; + } + + *p = (block << 10); + } +} + +/*! + * @brief Write a buffer of data to a selected endpoint + * + * @param ep: Endpoint number + * + * @retval wBuf: The pointer to the buffer of data to be written to the endpoint + * + * @param wLen: Number of data to be written (in bytes) + * + * @retval None + */ +void USBD_WriteDataToEP(USBD_EP_T ep, uint8_t *wBuf, uint32_t wLen) +{ + uint32_t i; + uint32_t *addrEP; + uint32_t tmp; + + wLen = (wLen + 1) >> 1; + + addrEP = (uint32_t *)USBD_ReadEPTxAddr(ep); + addrEP = (uint32_t *)(((uint32_t)addrEP << 1) + USBD_PMA_ADDR); + + for(i = 0; i < wLen; i++) + { + tmp = *wBuf++; + tmp = ((*wBuf++) << 8) | tmp; + + *addrEP++ = tmp; + } +} + +/*! + * @brief Read a buffer of data to a selected endpoint + * + * @param ep: Endpoint number + * + * @retval wBuf: The pointer to the buffer of data to be read to the endpoint + * + * @param wLen: Number of data to be read (in bytes) + * + * @retval None + */ +void USBD_ReadDataFromEP(USBD_EP_T ep, uint8_t *rBuf, uint32_t rLen) +{ + uint32_t i; + uint32_t *addrEP; + uint32_t tmp; + + rLen = (rLen + 1) >> 1; + + addrEP = (uint32_t *)USBD_ReadEPRxAddr(ep); + addrEP = (uint32_t *)(((uint32_t)addrEP << 1) + USBD_PMA_ADDR); + + for(i = 0; i < rLen; i++) + { + tmp = *addrEP++; + *rBuf++ = tmp & 0XFF; + *rBuf++ = (tmp >> 8) & 0xff; + } +} + diff --git a/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c new file mode 100644 index 0000000000..6e374cd5b4 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c @@ -0,0 +1,145 @@ +/*! + * @file apm32f10x_wwdt.c + * + * @brief This file contains all the functions for the WWDT peripheral + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x_wwdt.h" +#include "apm32f10x_rcm.h" + +/** @addtogroup Peripherals_Library Standard Peripheral Library + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_Fuctions Fuctions + @{ +*/ + +/*! + * @brief Reset the WWDT peripheral registers + * + * @param None + * + * @retval None + */ +void WWDT_Reset(void) +{ + RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT); + RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_WWDT); +} + +/*! + * @brief Config the WWDT Timebase + * + * @param timebase: WWDT Prescaler + * The parameter can be one of following values: + * @arg WWDT_TIME_BASE_1: WWDT counter clock = (PCLK1/4096)/1 + * @arg WWDT_TIME_BASE_2: WWDT counter clock = (PCLK1/4096)/2 + * @arg WWDT_TIME_BASE_4: WWDT counter clock = (PCLK1/4096)/4 + * @arg WWDT_TIME_BASE_8: WWDT counter clock = (PCLK1/4096)/8 + * + * @retval None + */ +void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase) +{ + __IO uint32_t reg; + + reg = WWDT->CFG & 0xFFFFFE7F; + reg |= timeBase; + WWDT->CFG = reg; +} + +/*! + * @brief Config the WWDT Window data + * + * @param windowdata: window data which compare with the downcounter + * + * @retval None + * + * @note The windowdata must be lower than 0x80 + */ +void WWDT_ConfigWindowData(uint8_t windowData) +{ + __IO uint32_t reg; + + reg = WWDT->CFG & 0xFFFFFF80; + reg |= windowData & 0x7F; + WWDT->CFG = reg; +} + +/*! + * @brief Config the WWDT counter value + * + * @param counter: Specifies the watchdog counter value + * + * @retval None + * + * @note The counter between 0x40 and 0x7F + */ +void WWDT_ConfigCounter(uint8_t counter) +{ + WWDT->CTRL = counter & 0x7F; +} + +/*! + * @brief Enable the WWDT Early Wakeup interrupt + * + * @param None + * + * @retval None + */ +void WWDT_EnableEWI(void) +{ + WWDT->CFG_B.EWIEN = SET; +} + +/*! + * @brief Enable WWDT and set the counter value + * + * @param counter: the window watchdog counter value + * + * @retval None + * + * @note The counter between 0x40 and 0x7F + */ +void WWDT_Enable(uint8_t counter) +{ + WWDT->CTRL = counter | 0x00000080; +} + +/*! + * @brief Read the Early Wakeup interrupt flag + * + * @param None + * + * @retval the state of the Early Wakeup interrupt flagte + */ +uint8_t WWDT_ReadFlag(void) +{ + return (uint8_t) (WWDT->STS); +} + +/*! + * @brief Clear the Early Wakeup interrupt flag + * + * @param None + * + * @retval None + */ +void WWDT_ClearFlag(void) +{ + WWDT->STS_B.EWIFLG = RESET; +} + +/**@} end of group WWDT_Fuctions*/ +/**@} end of group WWDT_Driver */ +/**@} end of group Peripherals_Library*/ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..a19425d9fe --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/**@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..ef919934c5 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/**@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..356182c5f9 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/**@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/**@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h new file mode 100644 index 0000000000..f5edd39559 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/apm32f10x.h @@ -0,0 +1,6158 @@ +/*! + * @file apm32f10x.h + * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * + * @details This file contains all the peripheral register's definitions, bits definitions and memory mapping + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __APM32F10x_H +#define __APM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*! + * APM32F10X_LD: APM32 Low density devices, the Flash memory density ranges between 16 and 32 Kbytes. + * APM32F10X_MD: APM32 Medium density devices, the Flash memory density ranges between 64 and 128 Kbytes. + * APM32F10X_HD: APM32 High density devices, the Flash memory density ranges between 256 and 512 Kbytes. + */ +#if !defined (APM32F10X_LD) && !defined (APM32F10X_MD) && !defined (APM32F10X_HD) +#error "Please select a the target APM32F10x device used in your application (in apm32f10x.h file)" +#endif + +/** + * @brief Define Value of the External oscillator in Hz + */ +#ifndef HSE_VALUE + #define HSE_VALUE ((uint32_t)8000000) +#endif + +/** Time out for HSE start up */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) + +/** Value of the Internal oscillator in Hz */ +#define HSI_VALUE ((uint32_t)8000000) + +/** + * @brief APM32F10x Standard Peripheral Library version number + */ +#define __APM32F10X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __APM32F10X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __APM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __APM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __APM32F10X_STDPERIPH_VERSION ( (__APM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__APM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__APM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__APM32F10X_STDPERIPH_VERSION_RC)) + + +/** APM32 devices does not provide an MPU */ + #define __MPU_PRESENT 0 +/** APM32 uses 4 Bits for the Priority Levels */ +#define __NVIC_PRIO_BITS 4 +/** Set to 1 if different SysTick Config is used */ +#define __Vendor_SysTickConfig 0 + +/** + * @brief APM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** APM32 specific Interrupt Numbers *********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EINT Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FMC_IRQn = 4, /*!< FMC global Interrupt */ + RCM_IRQn = 5, /*!< RCM global Interrupt */ + EINT0_IRQn = 6, /*!< EINT Line0 Interrupt */ + EINT1_IRQn = 7, /*!< EINT Line1 Interrupt */ + EINT2_IRQn = 8, /*!< EINT Line2 Interrupt */ + EINT3_IRQn = 9, /*!< EINT Line3 Interrupt */ + EINT4_IRQn = 10, /*!< EINT Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#if defined (APM32F10X_LD) + /** APM32F10X Low-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + +#elif defined (APM32F10X_MD) + /** APM32F10X Medium-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + FPU_IRQn = 43, /*!< FPU Global Interrupt */ + QSPI_IRQn = 44, /*!< QSPI Global Interrupt */ + USBD2_HP_IRQn = 45, /*!< USB Device 2 High Priority */ + USBD2_LP_IRQn = 46 /*!< USB Device 2 Low Priority */ + +#elif defined (APM32F10X_HD) + /** APM32F10X High-density devices specific Interrupt Numbers */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USBD1_HP_CAN1_TX_IRQn = 19, /*!< USB Device 1 High Priority or CAN1 TX Interrupts */ + USBD1_LP_CAN1_RX0_IRQn = 20, /*!< USB Device 1 Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EINT9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TMR1_BRK_IRQn = 24, /*!< TMR1 Break Interrupt */ + TMR1_UP_IRQn = 25, /*!< TMR1 Update Interrupt */ + TMR1_TRG_COM_IRQn = 26, /*!< TMR1 Trigger and Commutation Interrupt */ + TMR1_CC_IRQn = 27, /*!< TMR1 Capture Compare Interrupt */ + TMR2_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EINT15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EINT Line Interrupt */ + USBDWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EINT Line Interrupt */ + TMR8_BRK_IRQn = 43, /*!< TMR8 Break Interrupt */ + TMR8_UP_IRQn = 44, /*!< TMR8 Update Interrupt */ + TMR8_TRG_COM_IRQn = 45, /*!< TMR8 Trigger and Commutation Interrupt */ + TMR8_CC_IRQn = 46, /*!< TMR8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + EMMC_IRQn = 48, /*!< EMMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TMR5_IRQn = 50, /*!< TMR5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TMR6_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + USBD2_HP_CAN2_TX_IRQn = 61, /*!< USB Device 2 High Priority or CAN2 TX Interrupts */ + USBD2_LP_CAN2_RX0_IRQn = 62, /*!< USB Device 2 Low Priority or CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 63, /*!< CAN2 RX1 Interrupts */ + CAN2_SCE_IRQn = 64, /*!< CAN2 SCE Interrupts */ +#endif +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_apm32f10x.h" +#include + + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; +typedef const int16_t sc16; +typedef const int8_t sc8; + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; +typedef __I int16_t vsc16; +typedef __I int8_t vsc8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; +typedef const uint16_t uc16; +typedef const uint8_t uc8; + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; +typedef __I uint16_t vuc16; +typedef __I uint8_t vuc8; + +#ifndef __IM + #define __IM __I +#endif +#ifndef __OM + #define __OM __O +#endif +#ifndef __IOM + #define __IOM __IO +#endif + +enum {BIT_RESET, BIT_SET}; +enum {RESET, SET}; +enum {DISABLE, ENABLE}; +enum {ERROR, SUCCESS}; + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#if defined (__CC_ARM ) +#pragma anon_unions +#endif + +/** + * @brief Reset and clock management unit (RCM) + */ +typedef struct +{ + /** Clock control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t HSIEN : 1; + __IM uint32_t HSIRDYFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t HSITRIM : 5; + __IM uint32_t HSICAL : 8; + __IOM uint32_t HSEEN : 1; + __IM uint32_t HSERDYFLG : 1; + __IOM uint32_t HSEBCFG : 1; + __IOM uint32_t CSSEN : 1; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t PLLEN : 1; + __IM uint32_t PLLRDYFLG : 1; + __IM uint32_t RESERVED3 : 6; + } CTRL_B; + }; + + /** Clock configuration register */ + union + { + __IOM uint32_t CFG; + + struct + { + __IOM uint32_t SCLKSW : 2; + __IM uint32_t SCLKSWSTS : 2; + __IOM uint32_t AHBPSC : 4; + __IOM uint32_t APB1PSC : 3; + __IOM uint32_t APB2PSC : 3; + __IOM uint32_t ADCPSC : 2; + __IOM uint32_t PLLSRCSEL : 1; + __IOM uint32_t PLLHSEPSC : 1; + __IOM uint32_t PLLMULCFG : 4; + __IOM uint32_t USBDPSC : 2; + __IOM uint32_t MCOSEL : 3; + __IOM uint32_t FPUPSC : 1; + __IM uint32_t RESERVED : 4; + } CFG_B; + } ; + + /** Clock interrupt control register */ + union + { + __IOM uint32_t INT; + + struct + { + __IM uint32_t LSIRDYFLG : 1; + __IM uint32_t LSERDYFLG : 1; + __IM uint32_t HSIRDYFLG : 1; + __IM uint32_t HSERDYFLG : 1; + __IM uint32_t PLLRDYFLG : 1; + __IM uint32_t RESERVED1 : 2; + __IM uint32_t CSSIF : 1; + __IOM uint32_t LSIRDYEN : 1; + __IOM uint32_t LSERDYEN : 1; + __IOM uint32_t HSIRDYEN : 1; + __IOM uint32_t HSERDYEN : 1; + __IOM uint32_t PLLRDYEN : 1; + __IM uint32_t RESERVED2 : 3; + __OM uint32_t LSIRDYCLR : 1; + __OM uint32_t LSERDYCLR : 1; + __OM uint32_t HSIRDYCLR : 1; + __OM uint32_t HSERDYCLR : 1; + __OM uint32_t PLLRDYCLR : 1; + __IM uint32_t RESERVED3 : 2; + __OM uint32_t CSSCLR : 1; + __IM uint32_t RESERVED4 : 8; + } INT_B; + } ; + + /** APB2 peripheral reset register */ + union + { + __IOM uint32_t APB2RST; + + struct + { + __IOM uint32_t AFIO : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PA : 1; + __IOM uint32_t PB : 1; + __IOM uint32_t PC : 1; + __IOM uint32_t PD : 1; + __IOM uint32_t PE : 1; + __IOM uint32_t PF : 1; + __IOM uint32_t PG : 1; + __IOM uint32_t ADC1 : 1; + __IOM uint32_t ADC2 : 1; + __IOM uint32_t TMR1 : 1; + __IOM uint32_t SPI1 : 1; + __IOM uint32_t TMR8 : 1; + __IOM uint32_t USART1 : 1; + __IOM uint32_t ADC3 : 1; + __IM uint32_t RESERVED2 : 16; + } APB2RST_B; + } ; + + /** APB1 peripheral reset register */ + union + { + __IOM uint32_t APB1RST; + + struct + { + __IOM uint32_t TMR2 : 1; + __IOM uint32_t TMR3 : 1; + __IOM uint32_t TMR4 : 1; + __IOM uint32_t TMR5 : 1; + __IOM uint32_t TMR6 : 1; + __IOM uint32_t TMR7 : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t WWDT : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t SPI2 : 1; + __IOM uint32_t SPI3 : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t USART2 : 1; + __IOM uint32_t USART3 : 1; + __IOM uint32_t UART4 : 1; + __IOM uint32_t UART5 : 1; + __IOM uint32_t I2C1 : 1; + __IOM uint32_t I2C2 : 1; + __IOM uint32_t USBD : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t CAN1 : 1; + __IM uint32_t CAN2 : 1; + __IOM uint32_t BAKP : 1; + __IOM uint32_t PMU : 1; + __IOM uint32_t DAC : 1; + __IM uint32_t RESERVED5 : 2; + } APB1RST_B; + } ; + + /** AHB clock enable register */ + union + { + __IOM uint32_t AHBCLKEN; + + struct + { + __IOM uint32_t DMA1 : 1; + __IOM uint32_t DMA2 : 1; + __IOM uint32_t SRAM : 1; + __IOM uint32_t FPU : 1; + __IOM uint32_t FMC : 1; + __IOM uint32_t QSPI : 1; + __IOM uint32_t CRC : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t EMMC : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t SDIO : 1; + __IM uint32_t RESERVED3 : 21; + } AHBCLKEN_B; + } ; + + /** APB2 clock enable register */ + union + { + __IOM uint32_t APB2CLKEN; + + struct + { + __IOM uint32_t AFIO : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PA : 1; + __IOM uint32_t PB : 1; + __IOM uint32_t PC : 1; + __IOM uint32_t PD : 1; + __IOM uint32_t PE : 1; + __IOM uint32_t PF : 1; + __IOM uint32_t PG : 1; + __IOM uint32_t ADC1 : 1; + __IOM uint32_t ADC2 : 1; + __IOM uint32_t TMR1 : 1; + __IOM uint32_t SPI1 : 1; + __IOM uint32_t TMR8 : 1; + __IOM uint32_t USART1 : 1; + __IOM uint32_t ADC3 : 1; + __IM uint32_t RESERVED2 : 16; + } APB2CLKEN_B; + }; + + /** APB1 clock enable register */ + union + { + __IOM uint32_t APB1CLKEN; + + struct + { + __IOM uint32_t TMR2 : 1; + __IOM uint32_t TMR3 : 1; + __IOM uint32_t TMR4 : 1; + __IOM uint32_t TMR5 : 1; + __IOM uint32_t TMR6 : 1; + __IOM uint32_t TMR7 : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t WWDT : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t SPI2 : 1; + __IOM uint32_t SPI3 : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t USART2 : 1; + __IOM uint32_t USART3 : 1; + __IOM uint32_t UART4 : 1; + __IOM uint32_t UART5 : 1; + __IOM uint32_t I2C1 : 1; + __IOM uint32_t I2C2 : 1; + __IOM uint32_t USBD : 1; + __IM uint32_t RESERVED4 : 1; + __IOM uint32_t CAN1 : 1; + __IM uint32_t CAN2 : 1; + __IOM uint32_t BAKP : 1; + __IOM uint32_t PMU : 1; + __IOM uint32_t DAC : 1; + __IM uint32_t RESERVED5 : 2; + } APB1CLKEN_B; + } ; + + /** Backup domain control register */ + union + { + __IOM uint32_t BDCTRL; + + struct + { + __IOM uint32_t LSEEN : 1; + __IM uint32_t LSERDYFLG : 1; + __IOM uint32_t LSEBCFG : 1; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t RTCSRCSEL : 2; + __IM uint32_t RESERVED2 : 5; + __IOM uint32_t RTCCLKEN : 1; + __IOM uint32_t BDRST : 1; + __IM uint32_t RESERVED3 : 15; + } BDCTRL_B; + } ; + + /** Control/status register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IOM uint32_t LSIEN : 1; + __IM uint32_t LSIRDYFLG : 1; + __IM uint32_t RESERVED1 : 22; + __IOM uint32_t RSTFLGCLR : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t NRSTFLG : 1; + __IOM uint32_t PODRSTFLG : 1; + __IOM uint32_t SWRSTFLG : 1; + __IOM uint32_t IWDTRSTFLG : 1; + __IOM uint32_t WWDTRSTFLG : 1; + __IOM uint32_t LPWRRSTFLG : 1; + } CSTS_B; + } ; +} RCM_T; + +/** + * @brief General purpose I/O (GPIO) + */ +typedef struct +{ + /** Port configure register low */ + union + { + __IOM uint32_t CFGLOW; + + struct + { + __IOM uint32_t MODE0 : 2; + __IOM uint32_t CFG0 : 2; + __IOM uint32_t MODE1 : 2; + __IOM uint32_t CFG1 : 2; + __IOM uint32_t MODE2 : 2; + __IOM uint32_t CFG2 : 2; + __IOM uint32_t MODE3 : 2; + __IOM uint32_t CFG3 : 2; + __IOM uint32_t MODE4 : 2; + __IOM uint32_t CFG4 : 2; + __IOM uint32_t MODE5 : 2; + __IOM uint32_t CFG5 : 2; + __IOM uint32_t MODE6 : 2; + __IOM uint32_t CFG6 : 2; + __IOM uint32_t MODE7 : 2; + __IOM uint32_t CFG7 : 2; + } CFGLOW_B; + } ; + + /** Port configure register high */ + union + { + __IOM uint32_t CFGHIG; + + struct + { + __IOM uint32_t MODE8 : 2; + __IOM uint32_t CFG8 : 2; + __IOM uint32_t MODE9 : 2; + __IOM uint32_t CFG9 : 2; + __IOM uint32_t MODE10 : 2; + __IOM uint32_t CFG10 : 2; + __IOM uint32_t MODE11 : 2; + __IOM uint32_t CFG11 : 2; + __IOM uint32_t MODE12 : 2; + __IOM uint32_t CFG12 : 2; + __IOM uint32_t MODE13 : 2; + __IOM uint32_t CFG13 : 2; + __IOM uint32_t MODE14 : 2; + __IOM uint32_t CFG14 : 2; + __IOM uint32_t MODE15 : 2; + __IOM uint32_t CFG15 : 2; + } CFGHIG_B; + } ; + + /** Port data in register */ + union + { + __IM uint32_t IDATA; + + struct + { + __IM uint32_t IDATA0 : 1; + __IM uint32_t IDATA1 : 1; + __IM uint32_t IDATA2 : 1; + __IM uint32_t IDATA3 : 1; + __IM uint32_t IDATA4 : 1; + __IM uint32_t IDATA5 : 1; + __IM uint32_t IDATA6 : 1; + __IM uint32_t IDATA7 : 1; + __IM uint32_t IDATA8 : 1; + __IM uint32_t IDATA9 : 1; + __IM uint32_t IDATA10 : 1; + __IM uint32_t IDATA11 : 1; + __IM uint32_t IDATA12 : 1; + __IM uint32_t IDATA13 : 1; + __IM uint32_t IDATA14 : 1; + __IM uint32_t IDATA15 : 1; + __IM uint32_t RESERVED : 16; + } IDATA_B; + } ; + + /** Port data output register */ + union + { + __IOM uint32_t ODATA; + + struct + { + __IOM uint32_t ODATA0 : 1; + __IOM uint32_t ODATA1 : 1; + __IOM uint32_t ODATA2 : 1; + __IOM uint32_t ODATA3 : 1; + __IOM uint32_t ODATA4 : 1; + __IOM uint32_t ODATA5 : 1; + __IOM uint32_t ODATA6 : 1; + __IOM uint32_t ODATA7 : 1; + __IOM uint32_t ODATA8 : 1; + __IOM uint32_t ODATA9 : 1; + __IOM uint32_t ODATA10 : 1; + __IOM uint32_t ODATA11 : 1; + __IOM uint32_t ODATA12 : 1; + __IOM uint32_t ODATA13 : 1; + __IOM uint32_t ODATA14 : 1; + __IOM uint32_t ODATA15 : 1; + __IM uint32_t RESERVED : 16; + } ODATA_B; + } ; + + /** Port bit set/clear register */ + union + { + __OM uint32_t BSC; + + struct + { + __OM uint32_t BS0 : 1; + __OM uint32_t BS1 : 1; + __OM uint32_t BS2 : 1; + __OM uint32_t BS3 : 1; + __OM uint32_t BS4 : 1; + __OM uint32_t BS5 : 1; + __OM uint32_t BS6 : 1; + __OM uint32_t BS7 : 1; + __OM uint32_t BS8 : 1; + __OM uint32_t BS9 : 1; + __OM uint32_t BS10 : 1; + __OM uint32_t BS11 : 1; + __OM uint32_t BS12 : 1; + __OM uint32_t BS13 : 1; + __OM uint32_t BS14 : 1; + __OM uint32_t BS15 : 1; + __OM uint32_t BR0 : 1; + __OM uint32_t BC1 : 1; + __OM uint32_t BC2 : 1; + __OM uint32_t BR3 : 1; + __OM uint32_t BC4 : 1; + __OM uint32_t BC5 : 1; + __OM uint32_t BC6 : 1; + __OM uint32_t BC7 : 1; + __OM uint32_t BC8 : 1; + __OM uint32_t BC9 : 1; + __OM uint32_t BC10 : 1; + __OM uint32_t BC11 : 1; + __OM uint32_t BC12 : 1; + __OM uint32_t BC13 : 1; + __OM uint32_t BC14 : 1; + __OM uint32_t BC15 : 1; + } BSC_B; + } ; + + /** Port bit clear register */ + union + { + __OM uint32_t BC; + + struct + { + __OM uint32_t BC0 : 1; + __OM uint32_t BC1 : 1; + __OM uint32_t BC2 : 1; + __OM uint32_t BC3 : 1; + __OM uint32_t BC4 : 1; + __OM uint32_t BC5 : 1; + __OM uint32_t BC6 : 1; + __OM uint32_t BC7 : 1; + __OM uint32_t BC8 : 1; + __OM uint32_t BC9 : 1; + __OM uint32_t BC10 : 1; + __OM uint32_t BC11 : 1; + __OM uint32_t BC12 : 1; + __OM uint32_t BC13 : 1; + __OM uint32_t BC14 : 1; + __OM uint32_t BC15 : 1; + __IM uint32_t RESERVED : 16; + } BC_B; + } ; + + /** Port configuration lock register */ + union + { + __IOM uint32_t LOCK; + + struct + { + __IOM uint32_t LOCK0 : 1; + __IOM uint32_t LOCK1 : 1; + __IOM uint32_t LOCK2 : 1; + __IOM uint32_t LOCK3 : 1; + __IOM uint32_t LOCK4 : 1; + __IOM uint32_t LOCK5 : 1; + __IOM uint32_t LOCK6 : 1; + __IOM uint32_t LOCK7 : 1; + __IOM uint32_t LOCK8 : 1; + __IOM uint32_t LOCK9 : 1; + __IOM uint32_t LOCK10 : 1; + __IOM uint32_t LOCK11 : 1; + __IOM uint32_t LOCK12 : 1; + __IOM uint32_t LOCK13 : 1; + __IOM uint32_t LOCK14 : 1; + __IOM uint32_t LOCK15 : 1; + __IOM uint32_t LOCKKEY : 1; + __IM uint32_t RESERVED : 16; + } LOCK_B; + } ; +} GPIO_T; + +/** + * @brief Alternate function I/O (AFIO) + */ +typedef struct +{ + /** Event control register */ + union + { + __IOM uint32_t EVCTRL; + + struct + { + __IOM uint32_t PINSEL : 4; + __IOM uint32_t PORTSEL : 3; + __IOM uint32_t EVOEN : 1; + __IM uint32_t RESERVED : 24; + } EVCTRL_B; + } ; + + /** Alternate function IO remap and Serial wire JTAG configuration register */ + union + { + __IOM uint32_t REMAP1; + + struct + { + __IOM uint32_t SPI1RMP : 1; + __IOM uint32_t I2C1RMP : 1; + __IOM uint32_t USART1RMP : 1; + __IOM uint32_t USART2RMP : 1; + __IOM uint32_t USART3RMP : 2; + __IOM uint32_t TMR1RMP : 2; + __IOM uint32_t TMR2RMP : 2; + __IOM uint32_t TMR3RMP : 2; + __IOM uint32_t TMR4RMP : 1; + __IOM uint32_t CAN1RMP : 2; + __IOM uint32_t PD01RMP : 1; + __IOM uint32_t TMR5CH4IRMP : 1; + __IOM uint32_t ADC1_ETRGINJC_RMP : 1; + __IOM uint32_t ADC1_ETRGREGC_RMP : 1; + __IOM uint32_t ADC2_ETRGINJC_RMP : 1; + __IOM uint32_t ADC2_ETRGREGC_RMP : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CAN2RMP : 1; + __IM uint32_t RESERVED2 : 1; + __OM uint32_t SWJCFG : 3; + __IM uint32_t RESERVED3 : 5; + } REMAP1_B; + } ; + + /** External interrupt select register1 */ + union + { + __IOM uint32_t EINTSEL1; + + struct + { + __IOM uint32_t EINT0 : 4; + __IOM uint32_t EINT1 : 4; + __IOM uint32_t EINT2 : 4; + __IOM uint32_t EINT3 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL1_B; + } ; + + /** External interrupt select register2 */ + union + { + __IOM uint32_t EINTSEL2; + + struct + { + __IOM uint32_t EINT4 : 4; + __IOM uint32_t EINT5 : 4; + __IOM uint32_t EINT6 : 4; + __IOM uint32_t EINT7 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL2_B; + } ; + + /** External interrupt select register3 */ + union + { + __IOM uint32_t EINTSEL3; + + struct + { + __IOM uint32_t EINT8 : 4; + __IOM uint32_t EINT9 : 4; + __IOM uint32_t EINT10 : 4; + __IOM uint32_t EINT11 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL3_B; + } ; + + /** External interrupt select register4 */ + union + { + __IOM uint32_t EINTSEL4; + + struct + { + __IOM uint32_t EINT12 : 4; + __IOM uint32_t EINT13 : 4; + __IOM uint32_t EINT14 : 4; + __IOM uint32_t EINT15 : 4; + __IM uint32_t RESERVED : 16; + } EINTSEL4_B; + } ; + __IM uint32_t RESERVED; + + /** Alternate function IO remap register2 */ + union + { + __IOM uint32_t REMAP2; + + struct + { + __IM uint32_t RESERVED1 : 10; + __IOM uint32_t EMMCNADV : 1; + __IM uint32_t RESERVED2 : 21; + } REMAP2_B; + } ; +} AFIO_T; + +/** + * @brief Universal synchronous asynchronous receiver transmitter (USART) + */ +typedef struct +{ + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t PEFLG : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t NEFLG : 1; + __IM uint32_t OVREFLG : 1; + __IM uint32_t IDLEFLG : 1; + __IOM uint32_t RXBNEFLG : 1; + __IOM uint32_t TXCFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IOM uint32_t LBDFLG : 1; + __IOM uint32_t CTSFLG : 1; + __IM uint32_t RESERVED : 22; + } STS_B; + } ; + + /** TX Buffer Data Register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 9; + __IM uint32_t RESERVED : 23; + } DATA_B; + } ; + + /** Baud rate register */ + union + { + __IOM uint32_t BR; + + struct + { + __IOM uint32_t FBR : 4; + __IOM uint32_t IBR : 12; + __IM uint32_t RESERVED : 16; + } BR_B; + } ; + + /** Control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t TXBF : 1; + __IOM uint32_t RXMUTEEN : 1; + __IOM uint32_t RXEN : 1; + __IOM uint32_t TXEN : 1; + __IOM uint32_t IDLEIEN : 1; + __IOM uint32_t RXBNEIEN : 1; + __IOM uint32_t TXCIEN : 1; + __IOM uint32_t TXBEIEN : 1; + __IOM uint32_t PEIEN : 1; + __IOM uint32_t PCFG : 1; + __IOM uint32_t PCEN : 1; + __IOM uint32_t WUPMCFG : 1; + __IOM uint32_t DBLCFG : 1; + __IOM uint32_t UEN : 1; + __IM uint32_t RESERVED : 18; + } CTRL1_B; + } ; + + /** Control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t ADDR : 4; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t LBDLCFG : 1; + __IOM uint32_t LBDIEN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t LBCPOEN : 1; + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t CLKEN : 1; + __IOM uint32_t STOPCFG : 2; + __IOM uint32_t LINMEN : 1; + __IM uint32_t RESERVED3 : 17; + } CTRL2_B; + } ; + + /** Control register 3 */ + union + { + __IOM uint32_t CTRL3; + + struct + { + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t IREN : 1; + __IOM uint32_t IRLPEN : 1; + __IOM uint32_t HDEN : 1; + __IOM uint32_t SCNACKEN : 1; + __IOM uint32_t SCEN : 1; + __IOM uint32_t DMARXEN : 1; + __IOM uint32_t DMATXEN : 1; + __IOM uint32_t RTSEN : 1; + __IOM uint32_t CTSEN : 1; + __IOM uint32_t CTSIEN : 1; + __IM uint32_t RESERVED : 21; + } CTRL3_B; + } ; + + /** Guard TMRe and divider number register */ + union + { + __IOM uint32_t GTPSC; + + struct + { + __IOM uint32_t PSC : 8; + __IOM uint32_t GRDT : 8; + __IM uint32_t RESERVED : 16; + } GTPSC_B; + } ; +} USART_T; + +/** + * @brief Flash memory controller(FMC) + */ +typedef struct +{ + /** FMC access control register */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t WS : 3; + __IOM uint32_t HCAEN : 1; + __IOM uint32_t PBEN : 1; + __IM uint32_t PBSF : 1; + __IM uint32_t RESERVED : 26; + } CTRL1_B; + } ; + + /** key register */ + union + { + __OM uint32_t KEY; + + struct + { + __OM uint32_t KEY : 32; + } KEY_B; + } ; + + /** option byte key register */ + union + { + __OM uint32_t OBKEY; + + struct + { + __OM uint32_t OBKEY : 32; + } OBKEY_B; + }; + + /** status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t BUSYF : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PEF : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t WPEF : 1; + __IOM uint32_t OCF : 1; + __IM uint32_t RESERVED3 : 26; + } STS_B; + }; + + /** status register */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t PG : 1; + __IOM uint32_t PAGEERA : 1; + __IOM uint32_t MASSERA : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t OBP : 1; + __IOM uint32_t OBE : 1; + __IOM uint32_t STA : 1; + __IOM uint32_t LOCK : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t OBWEN : 1; + __IOM uint32_t ERRIE : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t OCIE : 1; + __IM uint32_t RESERVED4 : 19; + } CTRL2_B; + } ; + + /** address register */ + union + { + __OM uint32_t ADDR; + + struct + { + __OM uint32_t ADDR : 32; + } ADDR_B; + }; + + __IM uint32_t RESERVED; + + /** Option byte register */ + union + { + __IOM uint32_t OBCS; + + struct + { + __IM uint32_t OBE : 1; + __IM uint32_t READPROT : 1; + __IM uint32_t WDTSEL : 1; + __IM uint32_t RSTSTOP : 1; + __IM uint32_t RSTSTDB : 1; + __IM uint32_t UOB : 5; + __IM uint32_t DATA0 : 8; + __IM uint32_t DATA1 : 8; + __IM uint32_t RESERVED : 6; + } OBCS_B; + }; + + /** Write protection register */ + union + { + __IM uint32_t WRTPROT; + + struct + { + __IM uint32_t WRTPORT : 32; + } WRTPORT_B; + }; +} FMC_T; + +/** + * @brief CRC calculation unit (CRC) + */ +typedef struct +{ + /** @brief DATA register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 32; + } DATA_B; + } ; + + /** @brief independent DATA register */ + union + { + __IOM uint32_t INDATA; + + struct + { + __IOM uint32_t INDATA : 8; + __IM uint32_t RESERVED : 24; + } INDATA_B; + }; + + /** @brief Countrol register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t RST : 1; + __IM uint32_t RESERVED : 31; + } CTRL_B; + }; +} CRC_T; + +/** + * @brief Real time clock (RTC) + */ +typedef struct +{ + /** @brief Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t SECIEN : 1; + __IOM uint32_t ALRIEN : 1; + __IOM uint32_t OVRIEN : 1; + __IM uint32_t RESERVED : 29; + } CTRL_B; + }; + + /** @brief Control and State register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IOM uint32_t SECFLG : 1; + __IOM uint32_t ALRFLG : 1; + __IOM uint32_t OVRFLG : 1; + __IOM uint32_t RSYNCFLG : 1; + __IOM uint32_t CFGMFLG : 1; + __IM uint32_t OCFLG : 1; + __IM uint32_t RESERVED : 26; + } CSTS_B; + }; + + /** @brief RTC predivision loading register High Bit */ + union + { + __OM uint32_t PSCRLDH; + + struct + { + __OM uint32_t PSCRLDH : 4; + __IM uint32_t RESERVED : 28; + } PSCRLDH_B; + }; + + /** @brief RTC predivision loading register Low Bit */ + union + { + __OM uint32_t PSCRLDL; + + struct + { + __OM uint32_t PSCRLDL : 16; + __IM uint32_t RESERVED : 16; + } PSCRLDL_B; + }; + + /** @brief RTC predivider remainder register High Bit */ + union + { + __IM uint32_t PSCH; + + struct + { + __IM uint32_t PSCH : 4; + __IM uint32_t RESERVED : 28; + } PSCH_B; + }; + + /** @brief RTC predivider remainder register Low Bit */ + union + { + __IM uint32_t PSCL; + + struct + { + __IM uint32_t PSCL : 16; + __IM uint32_t RESERVED : 16; + } PSCL_B; + }; + + /** @brief RTC count register High Bit */ + union + { + __IOM uint32_t CNTH; + + struct + { + __IOM uint32_t CNTH : 16; + __IM uint32_t RESERVED : 16; + } CNTH_B; + }; + + /** @brief RTC count register Low Bit */ + union + { + __IOM uint32_t CNTL; + + struct + { + __IOM uint32_t CNTL : 16; + __IM uint32_t RESERVED : 16; + } CNTL_B; + }; + + /** @brief RTC alarm clock register High Bit */ + union + { + __OM uint32_t ALRH; + + struct + { + __OM uint32_t ALRH : 16; + __IM uint32_t RESERVED : 16; + } ALRH_B; + }; + + /** @brief RTC alarm clock register Low Bit */ + union + { + __OM uint32_t ALRL; + + struct + { + __OM uint32_t ALRL : 16; + __IM uint32_t RESERVED : 16; + } ALRL_B; + }; +} RTC_T; + +/** + * @brief Power Management Unit(PMU) + */ +typedef struct +{ + /** @brief Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t LPDSCFG : 1; + __IOM uint32_t PDDSCFG : 1; + __IOM uint32_t WUFLGCLR : 1; + __IOM uint32_t SBFLGCLR : 1; + __IOM uint32_t PVDEN : 1; + __IOM uint32_t PLSEL : 3; + __IOM uint32_t BPWEN : 1; + __IM uint32_t RESERVED : 23; + } CTRL_B; + }; + + /** @brief PMU Status register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __IM uint32_t WUEFLG : 1; + __IM uint32_t SBFLG : 1; + __IM uint32_t PVDOFLG : 1; + __IM uint32_t RESERVED : 5; + __IOM uint32_t WKUPCFG : 1; + __IM uint32_t RESERVED2 : 23; + } CSTS_B; + }; +} PMU_T; + +/** + * @brief Backup register (BAKPR) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + /** @brief BAKPR DATA1 register */ + union + { + __IOM uint32_t DATA1; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA1_B; + }; + + /** @brief BAKPR DATA2 register */ + union + { + __IOM uint32_t DATA2; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA2_B; + }; + + /** @brief BAKPR DATA3 register */ + union + { + __IOM uint32_t DATA3; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA3_B; + }; + + /** @brief BAKPR DATA4 register */ + union + { + __IOM uint32_t DATA4; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA4_B; + }; + + /** @brief BAKPR DATA5 register */ + union + { + __IOM uint32_t DATA5; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA5_B; + }; + + /** @brief BAKPR DATA6 register */ + union + { + __IOM uint32_t DATA6; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA6_B; + }; + + /** @brief BAKPR DATA7 register */ + union + { + __IOM uint32_t DATA7; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA7_B; + }; + + /** @brief BAKPR DATA8 register */ + union + { + __IOM uint32_t DATA8; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA8_B; + }; + + /** @brief BAKPR DATA9 register */ + union + { + __IOM uint32_t DATA9; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA9_B; + }; + + /** @brief BAKPR DATA10 register */ + union + { + __IOM uint32_t DATA10; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA10_B; + }; + + /** @brief BAKPR Clock Calibration register */ + union + { + __IOM uint32_t CLKCAL; + + struct + { + __IOM uint32_t CALVALUE : 7; + __IOM uint32_t CALCOEN : 1; + __IOM uint32_t ASPOEN : 1; + __IOM uint32_t ASPOSEL : 1; + __IM uint32_t RESERVED : 22; + } CLKCAL_B; + } ; + + /** @brief BAKPR Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t TPFCFG : 1; + __IOM uint32_t TPALCFG : 1; + __IM uint32_t RESERVED : 30; + } CTRL_B; + }; + + /** @brief BAKPR Control register */ + union + { + __IOM uint32_t CSTS; + + struct + { + __OM uint32_t TECLR : 1; + __OM uint32_t TICLR : 1; + __IOM uint32_t TPIEN : 1; + __IM uint32_t RESERVED1 : 5; + __IM uint32_t TEFLG : 1; + __IM uint32_t TIFLG : 1; + __IM uint32_t RESERVED2 : 22; + } CSTS_B; + }; + + __IM uint32_t RESERVED1[2]; + + /** @briefBAKPR DATA11 register */ + union + { + __IOM uint32_t DATA11; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA11_B; + }; + + /** @briefBAKPR DATA12 register */ + union + { + __IOM uint32_t DATA12; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA12_B; + }; + + /** @briefBAKPR DATA13 register */ + union + { + __IOM uint32_t DATA13; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA13_B; + }; + + /** @briefBAKPR DATA14 register */ + union + { + __IOM uint32_t DATA14; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA14_B; + }; + + /** @briefBAKPR DATA15 register */ + union + { + __IOM uint32_t DATA15; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA15_B; + }; + + /** @briefBAKPR DATA16 register */ + union + { + __IOM uint32_t DATA16; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA16_B; + }; + + /** @briefBAKPR DATA17 register */ + union + { + __IOM uint32_t DATA17; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA17_B; + }; + + /** @briefBAKPR DATA18 register */ + union + { + __IOM uint32_t DATA18; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA18_B; + }; + + /** @briefBAKPR DATA19 register */ + union + { + __IOM uint32_t DATA19; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA19_B; + }; + + /** @briefBAKPR DATA20 register */ + union + { + __IOM uint32_t DATA20; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA20_B; + }; + + /** @briefBAKPR DATA21 register */ + union + { + __IOM uint32_t DATA21; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA21_B; + }; + + /** @briefBAKPR DATA22 register */ + union + { + __IOM uint32_t DATA22; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA22_B; + }; + + /** @briefBAKPR DATA23 register */ + union + { + __IOM uint32_t DATA23; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA23_B; + }; + + /** @briefBAKPR DATA24 register */ + union + { + __IOM uint32_t DATA24; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA24_B; + }; + + /** @briefBAKPR DATA25 register */ + union + { + __IOM uint32_t DATA25; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA25_B; + }; + + /** @briefBAKPR DATA26 register */ + union + { + __IOM uint32_t DATA26; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA26_B; + }; + + /** @briefBAKPR DATA27 register */ + union + { + __IOM uint32_t DATA27; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA27_B; + }; + + /** @briefBAKPR DATA28 register */ + union + { + __IOM uint32_t DATA28; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA28_B; + }; + + /** @briefBAKPR DATA29 register */ + union + { + __IOM uint32_t DATA29; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA29_B; + }; + + /** @briefBAKPR DATA30 register */ + union + { + __IOM uint32_t DATA30; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA30_B; + }; + + /** @briefBAKPR DATA31 register */ + union + { + __IOM uint32_t DATA31; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA31_B; + }; + + /** @briefBAKPR DATA32 register */ + union + { + __IOM uint32_t DATA32; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA32_B; + }; + + /** @briefBAKPR DATA33 register */ + union + { + __IOM uint32_t DATA33; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA33_B; + }; + + /** @briefBAKPR DATA34 register */ + union + { + __IOM uint32_t DATA34; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA34_B; + }; + + /** @briefBAKPR DATA35 register */ + union + { + __IOM uint32_t DATA35; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA35_B; + }; + + /** @briefBAKPR DATA36 register */ + union + { + __IOM uint32_t DATA36; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA36_B; + }; + + /** @briefBAKPR DATA37 register */ + union + { + __IOM uint32_t DATA37; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA37_B; + }; + + /** @briefBAKPR DATA38 register */ + union + { + __IOM uint32_t DATA38; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA38_B; + }; + + /** @briefBAKPR DATA39 register */ + union + { + __IOM uint32_t DATA39; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA39_B; + }; + + /** @briefBAKPR DATA40 register */ + union + { + __IOM uint32_t DATA40; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA40_B; + }; + + /** @briefBAKPR DATA41 register */ + union + { + __IOM uint32_t DATA41; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA41_B; + }; + + /** @briefBAKPR DATA42 register */ + union + { + __IOM uint32_t DATA42; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA42_B; + }; +} BAKPR_T; + +/** + * @brief Timer register(TMR) + */ +typedef struct +{ + /** @brief Countrol register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t CNTEN : 1; + __IOM uint32_t UD : 1; + __IOM uint32_t URSSEL : 1; + __IOM uint32_t SPMEN : 1; + __IOM uint32_t CNTDIR : 1; + __IOM uint32_t CAMSEL : 2; + __IOM uint32_t ARPEN : 1; + __IOM uint32_t CLKDIV : 2; + __IM uint32_t RESERVED : 22; + } CTRL1_B; + }; + + /** @brief Countrol register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t CCPEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CCUSEL : 1; + __IOM uint32_t CCDSEL : 1; + __IOM uint32_t MMSEL : 3; + __IOM uint32_t TI1SEL : 1; + __IOM uint32_t OC1OIS : 1; + __IOM uint32_t OC1NOIS : 1; + __IOM uint32_t OC2OIS : 1; + __IOM uint32_t OC2NOIS : 1; + __IOM uint32_t OC3OIS : 1; + __IOM uint32_t OC3NOIS : 1; + __IOM uint32_t OC4OIS : 1; + __IM uint32_t RESERVED2 : 17; + } CTRL2_B; + }; + + /** @brief Control register from mode */ + union + { + __IOM uint32_t SMCTRL; + + struct + { + __IOM uint32_t SMFSEL : 3; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t TRGSEL : 3; + __IOM uint32_t MSMEN : 1; + __IOM uint32_t ETFCFG : 4; + __IOM uint32_t ETPCFG : 2; + __IOM uint32_t ECEN : 1; + __IOM uint32_t ETPOL : 1; + __IM uint32_t RESERVED2 : 16; + } SMCTRL_B; + }; + + /** @brief DMA and Interrupt enable register */ + union + { + __IOM uint32_t DIEN; + + struct + { + __IOM uint32_t UIEN : 1; + __IOM uint32_t CC1IEN : 1; + __IOM uint32_t CC2IEN : 1; + __IOM uint32_t CC3IEN : 1; + __IOM uint32_t CC4IEN : 1; + __IOM uint32_t COMIEN : 1; + __IOM uint32_t TRGIEN : 1; + __IOM uint32_t BRKIEN : 1; + __IOM uint32_t UDIEN : 1; + __IOM uint32_t CC1DEN : 1; + __IOM uint32_t CC2DEN : 1; + __IOM uint32_t CC3DEN : 1; + __IOM uint32_t CC4DEN : 1; + __IOM uint32_t COMDEN : 1; + __IOM uint32_t TRGDEN : 1; + __IM uint32_t RESERVED : 17; + } DIEN_B; + }; + + /** @brief Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t UIFLG : 1; + __IOM uint32_t CC1IFLG : 1; + __IOM uint32_t CC2IFLG : 1; + __IOM uint32_t CC3IFLG : 1; + __IOM uint32_t CC4IFLG : 1; + __IOM uint32_t COMIFLG : 1; + __IOM uint32_t TRGIFLG : 1; + __IOM uint32_t BRKIFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t CC1RCFLG : 1; + __IOM uint32_t CC2RCFLG : 1; + __IOM uint32_t CC3RCFLG : 1; + __IOM uint32_t CC4RCFLG : 1; + __IM uint32_t RESERVED2 : 19; + } STS_B; + }; + + /** @brief Software controls event generation registers */ + union + { + __OM uint32_t CEG; + + struct + { + __OM uint32_t UEG : 1; + __OM uint32_t CC1EG : 1; + __OM uint32_t CC2EG : 1; + __OM uint32_t CC3EG : 1; + __OM uint32_t CC4EG : 1; + __OM uint32_t COMG : 1; + __OM uint32_t TEG : 1; + __OM uint32_t BEG : 1; + __OM uint32_t RESERVED : 24; + } CEG_B; + }; + + /** @brief Capture the compare mode register 1 */ + union + { + __IOM uint32_t CCM1; + + /** @brief Compare mode */ + struct + { + __IOM uint32_t CC1SEL : 2; + __IOM uint32_t OC1FEN : 1; + __IOM uint32_t OC1PEN : 1; + __IOM uint32_t OC1MOD : 3; + __IOM uint32_t OC1CEN : 1; + __IOM uint32_t CC2SEL : 2; + __IOM uint32_t OC2FEN : 1; + __IOM uint32_t OC2PEN : 1; + __IOM uint32_t OC2MOD : 3; + __IOM uint32_t OC2CEN : 1; + __IM uint32_t RESERVED : 16; + } CCM1_COMPARE_B; + + /** @brief Capture mode */ + struct + { + __IOM uint32_t CC1SEL : 2; + __IOM uint32_t IC1PSC : 2; + __IOM uint32_t IC1F : 4; + __IOM uint32_t CC2SEL : 2; + __IOM uint32_t IC2PSC : 2; + __IOM uint32_t IC2F : 4; + __IM uint32_t RESERVED : 16; + } CCM1_CAPTURE_B; + }; + + /** @brief Capture the compare mode register 2 */ + union + { + __IOM uint32_t CCM2; + + /** @brief Compare mode */ + struct + { + __IOM uint32_t CC3SEL : 2; + __IOM uint32_t OC3FEN : 1; + __IOM uint32_t OC3PEN : 1; + __IOM uint32_t OC3MODE : 3; + __IOM uint32_t OC3CEN : 1; + __IOM uint32_t CC4SEL : 2; + __IOM uint32_t OC4FEN : 1; + __IOM uint32_t OC4PEN : 1; + __IOM uint32_t OC4MODE : 3; + __IOM uint32_t OC4CEN : 1; + __IM uint32_t RESERVED : 16; + } CCM2_COMPARE_B; + + /** @brief Capture mode */ + struct + { + __IOM uint32_t CC3SEL : 2; + __IOM uint32_t IC3PSC : 2; + __IOM uint32_t IC3F : 4; + __IOM uint32_t CC4SEL : 2; + __IOM uint32_t IC4PSC : 2; + __IOM uint32_t IC4F : 4; + __IM uint32_t RESERVED : 16; + } CCM2_CAPTURE_B; + }; + + /** @brief Channel control register */ + union + { + __IOM uint32_t CCEN; + + struct + { + __IOM uint32_t CC1EN : 1; + __IOM uint32_t CC1POL : 1; + __IOM uint32_t CC1NEN : 1; + __IOM uint32_t CC1NPOL : 1; + __IOM uint32_t CC2EN : 1; + __IOM uint32_t CC2POL : 1; + __IOM uint32_t CC2NEN : 1; + __IOM uint32_t CC2NPOL : 1; + __IOM uint32_t CC3EN : 1; + __IOM uint32_t CC3POL : 1; + __IOM uint32_t CC3NEN : 1; + __IOM uint32_t CC3NPOL : 1; + __IOM uint32_t CC4EN : 1; + __IOM uint32_t CC4POL : 1; + __IM uint32_t RESERVED : 18; + } CCEN_B; + }; + + /** @brief Counting register */ + union + { + __IOM uint32_t CNT; + + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + } CNT_B; + }; + + /** @brief Division register */ + union + { + __IOM uint32_t PSC; + + struct + { + __IOM uint32_t PSC : 16; + __IM uint32_t RESERVED : 16; + } PSC_B; + }; + + /** @brief Automatic reload register */ + union + { + __IOM uint32_t AUTORLD; + + struct + { + __IOM uint32_t AUTORLD : 16; + __IM uint32_t RESERVED : 16; + } AUTORLD_B; + }; + + /** @brief Repeat count register */ + union + { + __IOM uint32_t REPCNT; + + struct + { + __IOM uint32_t REPCNT : 8; + __IM uint32_t RESERVED : 24; + } REPCNT_B; + }; + + /** @brief Capture comparison register channel 1 */ + union + { + __IOM uint32_t CC1; + + struct + { + __IOM uint32_t CC1 : 16; + __IM uint32_t RESERVED : 16; + } CC1_B; + }; + + /** @brief Capture comparison register channel 2 */ + union + { + __IOM uint32_t CC2; + + struct + { + __IOM uint32_t CC2 : 16; + __IM uint32_t RESERVED : 16; + } CC2_B; + }; + + /** @brief Capture comparison register channel 3 */ + union + { + __IOM uint32_t CC3; + + struct + { + __IOM uint32_t CC3 : 16; + __IM uint32_t RESERVED : 16; + } CC3_B; + }; + + /** @brief Capture comparison register channel 4 */ + union + { + __IOM uint32_t CC4; + + struct + { + __IOM uint32_t CC4 : 16; + __IM uint32_t RESERVED : 16; + } CC4_B; + }; + + /** @brief Brake and dead zone registers */ + union + { + __IOM uint32_t BDT; + + struct + { + __IOM uint32_t DTS : 8; + __IOM uint32_t LOCKCFG : 2; + __IOM uint32_t IMOS : 1; + __IOM uint32_t RMOS : 1; + __IOM uint32_t BRKEN : 1; + __IOM uint32_t BRKPOL : 1; + __IOM uint32_t AOEN : 1; + __IOM uint32_t MOEN : 1; + __IM uint32_t RESERVED : 16; + } BDT_B; + }; + + /** @brief DMA control register */ + union + { + __IOM uint32_t DCTRL; + + struct + { + __IOM uint32_t DBADDR : 5; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t DBLEN : 5; + __IM uint32_t RESERVED2 : 19; + } DCTRL_B; + }; + + /** @brief Consecutive DMA addresses */ + union + { + __IOM uint32_t DMADDR; + struct + { + __IOM uint32_t DMADDR : 16; + __IM uint32_t RESERVED2 : 16; + } DMADDR_B; + }; +} TMR_T; + +/** + * @brief Direct Memory Access register(DMA) + */ +typedef struct +{ + /** @brief Interrupt status register */ + union + { + __IM uint32_t INTSTS; + + struct + { + __IM uint32_t GINTFLG1 : 1; + __IM uint32_t TCFLG1 : 1; + __IM uint32_t HTFLG1 : 1; + __IM uint32_t TERRFLG1 : 1; + __IM uint32_t GINTFLG2 : 1; + __IM uint32_t TCFLG2 : 1; + __IM uint32_t HTFLG2 : 1; + __IM uint32_t TERRFLG2 : 1; + __IM uint32_t GINTFLG3 : 1; + __IM uint32_t TCFLG3 : 1; + __IM uint32_t HTFLG3 : 1; + __IM uint32_t TERRFLG3 : 1; + __IM uint32_t GINTFLG4 : 1; + __IM uint32_t TCFLG4 : 1; + __IM uint32_t HTFLG4 : 1; + __IM uint32_t TERRFLG4 : 1; + __IM uint32_t GINTFLG5 : 1; + __IM uint32_t TCFLG5 : 1; + __IM uint32_t HTFLG5 : 1; + __IM uint32_t TERRFLG5 : 1; + __IM uint32_t GINTFLG6 : 1; + __IM uint32_t TCFLG6 : 1; + __IM uint32_t HTFLG6 : 1; + __IM uint32_t TERRFLG6 : 1; + __IM uint32_t GINTFLG7 : 1; + __IM uint32_t TCFLG7 : 1; + __IM uint32_t HTFLG7 : 1; + __IM uint32_t TERRFLG7 : 1; + __IM uint32_t RESERVED : 4; + } INTSTS_B; + }; + + /** @brief Interrupt reset register */ + union + { + __OM uint32_t INTFCLR; + + struct + { + __OM uint32_t GINTCLR1 : 1; + __OM uint32_t TCCLR1 : 1; + __OM uint32_t HTCLR1 : 1; + __OM uint32_t TERRCLR1 : 1; + __OM uint32_t GINTCLR2 : 1; + __OM uint32_t TCCLR2 : 1; + __OM uint32_t HTCLR2 : 1; + __OM uint32_t TERRCLR2 : 1; + __OM uint32_t GINTCLR3 : 1; + __OM uint32_t TCCLR3 : 1; + __OM uint32_t HTCLR3 : 1; + __OM uint32_t TERRCLR3 : 1; + __OM uint32_t GINTCLR4 : 1; + __OM uint32_t TCCLR4 : 1; + __OM uint32_t HTCLR4 : 1; + __OM uint32_t TERRCLR4 : 1; + __OM uint32_t GINTCLR5 : 1; + __OM uint32_t TCCLR5 : 1; + __OM uint32_t HTCLR5 : 1; + __OM uint32_t TERRCLR5 : 1; + __OM uint32_t GINTCLR6 : 1; + __OM uint32_t TCCLR6 : 1; + __OM uint32_t HTCLR6 : 1; + __OM uint32_t TERRCLR6 : 1; + __OM uint32_t GINTCLR7 : 1; + __OM uint32_t TCCLR7 : 1; + __OM uint32_t HTCLR7 : 1; + __OM uint32_t TERRCLR7 : 1; + __IM uint32_t RESERVED : 4; + } INTFCLR_B; + }; +} DMA_T; + +/** + * @brief DMA Channel register + */ +typedef struct +{ + /** @brief DMA Channel setup register */ + union + { + + __IOM uint32_t CHCFG; + + struct + { + __IOM uint32_t CHEN : 1; + __IOM uint32_t TCINTEN : 1; + __IOM uint32_t HTINTEN : 1; + __IOM uint32_t TERRINTEN : 1; + __IOM uint32_t DIRCFG : 1; + __IOM uint32_t CIRMODE : 1; + __IOM uint32_t PERIMODE : 1; + __IOM uint32_t MIMODE : 1; + __IOM uint32_t PERSIZE : 2; + __IOM uint32_t MEMSIZE : 2; + __IOM uint32_t CHPL : 2; + __IOM uint32_t M2MMODE : 1; + __IM uint32_t RESERVED : 17; + } CHCFG_B; + }; + + /** @brief DMA Channel transfer number register*/ + union + { + __IOM uint32_t CHNDATA; + + struct + { + __IOM uint32_t NDATA : 16; + __IM uint32_t RESERVED : 16; + } CHNDATA_B; + }; + + /** @brief DMA Channel peripheral address register */ + union + { + __IOM uint32_t CHPADDR; + + struct + { + __IOM uint32_t PERADDR : 32; + } CHPADDR_B; + }; + + /** @brief DMA Channel memory address register */ + union + { + __IOM uint32_t CHMADDR; + + struct + { + __IOM uint32_t MEMADDR : 32; + } CHMADDR_B; + }; +} DMA_Channel_T; + +/** + * @brief CAN sending mailbox + */ +typedef struct +{ + /** @brief CAN Each mailbox contains the sending mailbox identifier register */ + union + { + __IOM uint32_t TXMID; + + struct + { + __IOM uint32_t TXMREQ : 1; + __IOM uint32_t TXRFREQ : 1; + __IOM uint32_t IDTYPESEL : 1; + __IOM uint32_t EXTID : 18; + __IOM uint32_t STDID : 11; + } TXMID_B; + }; + + /** @brief CAN Send the mailbox data length and timestamp register */ + union + { + __IOM uint32_t TXDLEN; + + struct + { + __IOM uint32_t DLCODE : 4; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t TXTS : 1; + __IM uint32_t RESERVED2 : 7; + __IOM uint32_t MTS : 16; + } TXDLEN_B; + }; + + /** @brief CAN Send mailbox low byte data register */ + union + { + __IOM uint32_t TXMDL; + + struct + { + __IOM uint32_t DATABYTE0 : 8; + __IOM uint32_t DATABYTE1 : 8; + __IOM uint32_t DATABYTE2 : 8; + __IOM uint32_t DATABYTE3 : 8; + } TXMDL_B; + }; + + /** @brief CAN Send mailbox High byte data register */ + union + { + __IOM uint32_t TXMDH; + + struct + { + __IOM uint32_t DATABYTE4 : 8; + __IOM uint32_t DATABYTE5 : 8; + __IOM uint32_t DATABYTE6 : 8; + __IOM uint32_t DATABYTE7 : 8; + } TXMDH_B; + }; +} CAN_TxMailBox_T; + +/** + * @brief CAN receive mailbox + */ +typedef struct +{ + /** @brief CAN Each mailbox contains the receive mailbox identifier register */ + union + { + __IM uint32_t RXMID; + + struct + { + __IM uint32_t RESERVED : 1; + __IM uint32_t RFTXREQ : 1; + __IM uint32_t IDTYPESEL : 1; + __IM uint32_t EXTID : 18; + __IM uint32_t STDID : 11; + } RXMID_B; + }; + + /** @brief CAN receive the mailbox data length and timestamp register */ + union + { + __IM uint32_t RXDLEN; + + struct + { + __IM uint32_t DLCODE : 4; + __IM uint32_t RESERVED : 4; + __IM uint32_t FMIDX : 8; + __IM uint32_t MTS : 16; + } RXDLEN_B; + }; + + /** @brief CAN receive mailbox low byte data register */ + union + { + __IM uint32_t RXMDL; + + struct + { + __IM uint32_t DATABYTE1 : 8; + __IM uint32_t DATABYTE2 : 8; + __IM uint32_t DATABYTE3 : 8; + __IM uint32_t DATABYTE4 : 8; + } RXMDL_B; + }; + + /** @briefCAN receive mailbox High byte data register */ + union + { + __IOM uint32_t RXMDH; + + struct + { + __IM uint32_t DATABYTE5 : 8; + __IM uint32_t DATABYTE6 : 8; + __IM uint32_t DATABYTE7 : 8; + __IM uint32_t DATABYTE8 : 8; + } RXMDH_B; + }; +} CAN_RxMailBox_T; + +/** + * @brief CAN Filter bank register + */ +typedef struct +{ + /** @brief CAN Filter bank register 1 */ + union + { + __IOM uint32_t FBANK1; + + struct + { + __IOM uint32_t FBIT0 : 1; + __IOM uint32_t FBIT1 : 1; + __IOM uint32_t FBIT2 : 1; + __IOM uint32_t FBIT3 : 1; + __IOM uint32_t FBIT4 : 1; + __IOM uint32_t FBIT5 : 1; + __IOM uint32_t FBIT6 : 1; + __IOM uint32_t FBIT7 : 1; + __IOM uint32_t FBIT8 : 1; + __IOM uint32_t FBIT9 : 1; + __IOM uint32_t FBIT10 : 1; + __IOM uint32_t FBIT11 : 1; + __IOM uint32_t FBIT12 : 1; + __IOM uint32_t FBIT13 : 1; + __IOM uint32_t FBIT14 : 1; + __IOM uint32_t FBIT15 : 1; + __IOM uint32_t FBIT16 : 1; + __IOM uint32_t FBIT17 : 1; + __IOM uint32_t FBIT18 : 1; + __IOM uint32_t FBIT19 : 1; + __IOM uint32_t FBIT20 : 1; + __IOM uint32_t FBIT21 : 1; + __IOM uint32_t FBIT22 : 1; + __IOM uint32_t FBIT23 : 1; + __IOM uint32_t FBIT24 : 1; + __IOM uint32_t FBIT25 : 1; + __IOM uint32_t FBIT26 : 1; + __IOM uint32_t FBIT27 : 1; + __IOM uint32_t FBIT28 : 1; + __IOM uint32_t FBIT29 : 1; + __IOM uint32_t FBIT30 : 1; + __IOM uint32_t FBIT31 : 1; + } FBANK1_B; + }; + + /** @brief CAN Filter bank register 1 */ + union + { + __IOM uint32_t FBANK2; + + struct + { + __IOM uint32_t FBIT0 : 1; + __IOM uint32_t FBIT1 : 1; + __IOM uint32_t FBIT2 : 1; + __IOM uint32_t FBIT3 : 1; + __IOM uint32_t FBIT4 : 1; + __IOM uint32_t FBIT5 : 1; + __IOM uint32_t FBIT6 : 1; + __IOM uint32_t FBIT7 : 1; + __IOM uint32_t FBIT8 : 1; + __IOM uint32_t FBIT9 : 1; + __IOM uint32_t FBIT10 : 1; + __IOM uint32_t FBIT11 : 1; + __IOM uint32_t FBIT12 : 1; + __IOM uint32_t FBIT13 : 1; + __IOM uint32_t FBIT14 : 1; + __IOM uint32_t FBIT15 : 1; + __IOM uint32_t FBIT16 : 1; + __IOM uint32_t FBIT17 : 1; + __IOM uint32_t FBIT18 : 1; + __IOM uint32_t FBIT19 : 1; + __IOM uint32_t FBIT20 : 1; + __IOM uint32_t FBIT21 : 1; + __IOM uint32_t FBIT22 : 1; + __IOM uint32_t FBIT23 : 1; + __IOM uint32_t FBIT24 : 1; + __IOM uint32_t FBIT25 : 1; + __IOM uint32_t FBIT26 : 1; + __IOM uint32_t FBIT27 : 1; + __IOM uint32_t FBIT28 : 1; + __IOM uint32_t FBIT29 : 1; + __IOM uint32_t FBIT30 : 1; + __IOM uint32_t FBIT31 : 1; + } FBANK2_B; + }; +} CAN_FilterRegister_T; + +/** + * @brief Controller Area Network(CAN) + */ +typedef struct +{ + /** @brief CAN Master control register */ + union + { + __IOM uint32_t MCTRL; + + struct + { + __IOM uint32_t INITREQ : 1; + __IOM uint32_t SLEEPREQ : 1; + __IOM uint32_t TXFPCFG : 1; + __IOM uint32_t RXFLOCK : 1; + __IOM uint32_t ARTXMD : 1; + __IOM uint32_t AWUPCFG : 1; + __IOM uint32_t ALBOFFM : 1; + __IOM uint32_t TTCM : 1; + __IM uint32_t RESERVED1 : 7; + __IOM uint32_t SWRST : 1; + __IOM uint32_t DBGFRZE : 1; + __IM uint32_t RESERVED2 : 15; + } MCTRL_B; + }; + + /** @brief CAN Master States register */ + union + { + __IOM uint32_t MSTS; + + struct + { + __IM uint32_t INITFLG : 1; + __IM uint32_t SLEEPFLG : 1; + __IOM uint32_t ERRIFLG : 1; + __IOM uint32_t WUPIFLG : 1; + __IOM uint32_t SLEEPIFLG : 1; + __IM uint32_t RESERVED1 : 3; + __IM uint32_t TXMFLG : 1; + __IM uint32_t RXMFLG : 1; + __IM uint32_t LSAMVALUE : 1; + __IM uint32_t RXSIGL : 1; + __IM uint32_t RESERVED2 : 20; + } MSTS_B; + }; + + /** @brief CAN Send States register */ + union + { + __IOM uint32_t TXSTS; + + struct + { + __IOM uint32_t REQCFLG0 : 1; + __IOM uint32_t TXSUSFLG0 : 1; + __IOM uint32_t ARBLSTFLG0 : 1; + __IOM uint32_t TXERRFLG0 : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ABREQFLG0 : 1; + __IOM uint32_t REQCFLG1 : 1; + __IOM uint32_t TXSUSFLG1 : 1; + __IOM uint32_t ARBLSTFLG1 : 1; + __IOM uint32_t TXERRFLG1 : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t ABREQFLG1 : 1; + __IOM uint32_t REQCFLG2 : 1; + __IOM uint32_t TXSUSFLG2 : 1; + __IOM uint32_t ARBLSTFLG2 : 1; + __IOM uint32_t TXERRFLG2 : 1; + __IM uint32_t RESERVED3 : 3; + __IOM uint32_t ABREQFLG2 : 1; + __IM uint32_t EMNUM : 2; + __IM uint32_t TXMEFLG0 : 1; + __IM uint32_t TXMEFLG1 : 1; + __IM uint32_t TXMEFLG2 : 1; + __IM uint32_t LOWESTP0 : 1; + __IM uint32_t LOWESTP1 : 1; + __IM uint32_t LOWESTP2 : 1; + } TXSTS_B; + }; + + /** @brief CAN Receive FIFO 0 register */ + union + { + __IOM uint32_t RXF0; + + struct + { + __IM uint32_t FMNUM0 : 2; + __IM uint32_t RESERVED : 1; + __IOM uint32_t FFULLFLG0 : 1; + __IOM uint32_t FOVRFLG0 : 1; + __IOM uint32_t RFOM0 : 1; + __IM uint32_t RESERVED2 : 26; + } RXF0_B; + }; + + /** @brief CAN Receive FIFO 1 register */ + union + { + __IOM uint32_t RXF1; + + struct + { + __IM uint32_t FMNUM1 : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t FFULLFLG1 : 1; + __IOM uint32_t FOVRFLG1 : 1; + __IOM uint32_t RFOM1 : 1; + __IM uint32_t RESERVED2 : 26; + } RXF1_B; + }; + + /** @brief CAN Interrupts register */ + union + { + __IOM uint32_t INTEN; + + struct + { + __IOM uint32_t TXMEIEN : 1; + __IOM uint32_t FMIEN0 : 1; + __IOM uint32_t FFULLIEN0 : 1; + __IOM uint32_t FOVRIEN0 : 1; + __IOM uint32_t FMIEN1 : 1; + __IOM uint32_t FFULLIEN1 : 1; + __IOM uint32_t FOVRIEN1 : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t ERRWIEN : 1; + __IOM uint32_t ERRPIEN : 1; + __IOM uint32_t BOFFIEN : 1; + __IOM uint32_t LECIEN : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t WUPIEN : 1; + __IOM uint32_t SLEEPIEN : 1; + __IM uint32_t RESERVED3 : 14; + } INTEN_B; + }; + + /** @brief CAN Error States register */ + union + { + __IOM uint32_t ERRSTS; + + struct + { + __IM uint32_t ERRWFLG : 1; + __IM uint32_t ERRPFLG : 1; + __IM uint32_t BOFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t LERRC : 3; + __IM uint32_t RESERVED2 : 9; + __IM uint32_t TXERRCNT : 8; + __IM uint32_t RXERRCNT : 8; + } ERRSTS_B; + }; + + /** @brief CAN Bit Time register */ + union + { + __IOM uint32_t BITTIM; + + struct + { + __IOM uint32_t BRPSC : 10; + __IM uint32_t RESERVED1 : 6; + __IOM uint32_t TIMSEG1 : 4; + __IOM uint32_t TIMSEG2 : 3; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t RSYNJW : 2; + __IM uint32_t RESERVED3 : 4; + __IOM uint32_t LBKMEN : 1; + __IOM uint32_t SILMEN : 1; + } BITTIM_B; + }; + + __IM uint32_t RESERVED0[88]; + + CAN_TxMailBox_T sTxMailBox[3]; + CAN_RxMailBox_T sRxMailBox[2]; + + __IM uint32_t RESERVED1[12]; + + /** @brief CAN Filter the master control register */ + union + { + __IOM uint32_t FCTRL; + + struct + { + __IOM uint32_t FINITEN : 1; + __IM uint32_t RESERVED : 31; + } FCTRL_B; + }; + + /** @brief CAN Filter register */ + union + { + __IOM uint32_t FMCFG; + + struct + { + __IOM uint32_t FMCFG0 : 1; + __IOM uint32_t FMCFG1 : 1; + __IOM uint32_t FMCFG2 : 1; + __IOM uint32_t FMCFG3 : 1; + __IOM uint32_t FMCFG4 : 1; + __IOM uint32_t FMCFG5 : 1; + __IOM uint32_t FMCFG6 : 1; + __IOM uint32_t FMCFG7 : 1; + __IOM uint32_t FMCFG8 : 1; + __IOM uint32_t FMCFG9 : 1; + __IOM uint32_t FMCFG10 : 1; + __IOM uint32_t FMCFG11 : 1; + __IOM uint32_t FMCFG12 : 1; + __IOM uint32_t FMCFG13 : 1; + __IM uint32_t RESERVED : 18; + } FMCFG_B; + }; + + __IM uint32_t RESERVED2; + + /** @brief CAN Filter bit scale register */ + union + { + __IOM uint32_t FSCFG; + + struct + { + __IOM uint32_t FSCFG0 : 1; + __IOM uint32_t FSCFG1 : 1; + __IOM uint32_t FSCFG2 : 1; + __IOM uint32_t FSCFG3 : 1; + __IOM uint32_t FSCFG4 : 1; + __IOM uint32_t FSCFG5 : 1; + __IOM uint32_t FSCFG6 : 1; + __IOM uint32_t FSCFG7 : 1; + __IOM uint32_t FSCFG8 : 1; + __IOM uint32_t FSCFG9 : 1; + __IOM uint32_t FSCFG10 : 1; + __IOM uint32_t FSCFG11 : 1; + __IOM uint32_t FSCFG12 : 1; + __IOM uint32_t FSCFG13 : 1; + __IM uint32_t RESERVED : 18; + }FSCFG_B; + }; + + __IM uint32_t RESERVED3; + + /** @brief CAN Filter FIFO associated registers */ + union + { + __IOM uint32_t FFASS; + + struct + { + __IOM uint32_t FFASS0 : 1; + __IOM uint32_t FFASS1 : 1; + __IOM uint32_t FFASS2 : 1; + __IOM uint32_t FFASS3 : 1; + __IOM uint32_t FFASS4 : 1; + __IOM uint32_t FFASS5 : 1; + __IOM uint32_t FFASS6 : 1; + __IOM uint32_t FFASS7 : 1; + __IOM uint32_t FFASS8 : 1; + __IOM uint32_t FFASS9 : 1; + __IOM uint32_t FFASS10 : 1; + __IOM uint32_t FFASS11 : 1; + __IOM uint32_t FFASS12 : 1; + __IOM uint32_t FFASS13 : 1; + __IM uint32_t RESERVED : 18; + } FFASS_B; + }; + + __IM uint32_t RESERVED4; + + /** @brief CAN Filter activation register */ + union + { + __IOM uint32_t FACT; + + struct + { + __IOM uint32_t FACT0 : 1; + __IOM uint32_t FACT1 : 1; + __IOM uint32_t FACT2 : 1; + __IOM uint32_t FACT3 : 1; + __IOM uint32_t FACT4 : 1; + __IOM uint32_t FACT5 : 1; + __IOM uint32_t FACT6 : 1; + __IOM uint32_t FACT7 : 1; + __IOM uint32_t FACT8 : 1; + __IOM uint32_t FACT9 : 1; + __IOM uint32_t FACT10 : 1; + __IOM uint32_t FACT11 : 1; + __IOM uint32_t FACT12 : 1; + __IOM uint32_t FACT13 : 1; + __IM uint32_t RESERVED : 18; + } FACT_B; + }; + + __IM uint32_t RESERVED5[8]; + + CAN_FilterRegister_T sFilterRegister[14]; + +} CAN_T; + +/** + * @brief I2C register (I2C) + */ +typedef struct +{ + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t I2CEN : 1; + __IOM uint32_t SMBEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t SMBTCFG : 1; + __IOM uint32_t ARPEN : 1; + __IOM uint32_t PECEN : 1; + __IOM uint32_t SRBEN : 1; + __IOM uint32_t CLKSTRETCHD : 1; + __IOM uint32_t START : 1; + __IOM uint32_t STOP : 1; + __IOM uint32_t ACKEN : 1; + __IOM uint32_t ACKPOS : 1; + __IOM uint32_t PEC : 1; + __IOM uint32_t ALERTEN : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t SWRST : 1; + __IM uint32_t RESERVED3 : 16; + } CTRL1_B; + } ; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t CLKFCFG : 6; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t EVIEN : 1; + __IOM uint32_t BUFIEN : 1; + __IOM uint32_t DMAEN : 1; + __IOM uint32_t LTCFG : 1; + __IM uint32_t RESERVED2 : 19; + } CTRL2_B; + } ; + + /** @brief Slave machine address register 1 */ + union + { + __IOM uint32_t SADDR1; + + struct + { + __IOM uint32_t ADDR0 : 1; + __IOM uint32_t ADDR1_7 : 7; + __IOM uint32_t ADDR8_9 : 2; + __IM uint32_t RESERVED1 : 5; + __IOM uint32_t ADDRLEN : 1; + __IM uint32_t RESERVED2 : 16; + } SADDR1_B; + }; + + /** @brief Slave machine address register 2 */ + union + { + __IOM uint32_t SADDR2; + + struct + { + __IOM uint32_t ADDRNUM : 1; + __IOM uint32_t ADDR2 : 7; + __IM uint32_t RESERVED : 24; + } SADDR2_B; + }; + + /** @brief Cache data register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED : 24; + } DATA_B; + }; + + /** @brief Status register 1 */ + union + { + __IOM uint32_t STS1; + + struct + { + __IM uint32_t STARTFLG : 1; + __IM uint32_t ADDRFLG : 1; + __IM uint32_t BTCFLG : 1; + __IM uint32_t ADDR10FLG : 1; + __IM uint32_t STOPFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t RXBNEFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IOM uint32_t BERRFLG : 1; + __IOM uint32_t ALFLG : 1; + __IOM uint32_t AEFLG : 1; + __IOM uint32_t OVRURFLG : 1; + __IOM uint32_t PECEFLG : 1; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t TTEFLG : 1; + __IOM uint32_t SMBALTFLG : 1; + __IM uint32_t RESERVED3 : 16; + } STS1_B; + }; + + /** @brief Status register 2 */ + union + { + __IOM uint32_t STS2; + + struct + { + __IM uint32_t MSFLG : 1; + __IM uint32_t BUSBSYFLG : 1; + __IM uint32_t TRFLG : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t GENCALLFLG : 1; + __IM uint32_t SMBDADDRFLG : 1; + __IM uint32_t SMMHADDR : 1; + __IM uint32_t DUALADDRFLG : 1; + __IM uint32_t PECVALUE : 8; + __IM uint32_t RESERVED2 : 16; + } STS2_B; + }; + + /** @brief Clock control register */ + union + { + __IOM uint32_t CLKCTRL; + + struct + { + __IOM uint32_t CLKS : 12; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t FDUTYCFG : 1; + __IOM uint32_t SPEEDCFG : 1; + __IM uint32_t RESERVED2 : 16; + } CLKCTRL_B; + }; + + /** @brief Maximum rise time */ + union + { + __IOM uint32_t RISETMAX; + + struct + { + __IOM uint32_t RISETMAX : 6; + __IM uint32_t RESERVED : 26; + } RISETMAX_B; + }; + + __IM uint32_t RESERVED[55]; + + /** @brief I2C Switching register */ + union + { + __IOM uint32_t SWITCH; + + struct + { + __IOM uint32_t SWITCH : 1; + __IM uint32_t RESERVED1 : 31; + } SWITCH_B; + }; +} I2C_T; + + +typedef struct +{ + __IOM uint16_t RDP; + __IOM uint16_t USER; + __IOM uint16_t Data0; + __IOM uint16_t Data1; + __IOM uint16_t WRP0; + __IOM uint16_t WRP1; + __IOM uint16_t WRP2; + __IOM uint16_t WRP3; +} OB_T; + +/** + * @brief Analog to Digital Converter(ADC) + */ +typedef struct +{ + + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t AWDFLG : 1; + __IOM uint32_t EOCFLG : 1; + __IOM uint32_t INJEOCFLG : 1; + __IOM uint32_t INJCSFLG : 1; + __IOM uint32_t REGCSFLG : 1; + __IM uint32_t RESERVED : 27; + } STS_B; + }; + + /** Control register1*/ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t AWDCHSEL : 5; + __IOM uint32_t EOCIEN : 1; + __IOM uint32_t AWDIEN : 1; + __IOM uint32_t INJEOCIEN : 1; + __IOM uint32_t SCANEN : 1; + __IOM uint32_t AWDSGLEN : 1; + __IOM uint32_t INJGACEN : 1; + __IOM uint32_t REGDISCEN : 1; + __IOM uint32_t INJDISCEN : 1; + __IOM uint32_t DISCNUMCFG : 3; + __IOM uint32_t DUALMCFG : 4; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t INJAWDEN : 1; + __IOM uint32_t REGAWDEN : 1; + __IM uint32_t RESERVED2 : 8; + } CTRL1_B; + }; + + /** Control register2*/ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t ADCEN : 1; + __IOM uint32_t CONTCEN : 1; + __IOM uint32_t CAL : 1; + __IOM uint32_t CALRST : 1; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DMAEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t DALIGNCFG : 1; + __IOM uint32_t INJGEXTTRGSEL : 3; + __IOM uint32_t INJEXTTRGEN : 1; + __IM uint32_t RESERVED3 : 1; + __IOM uint32_t REGEXTTRGSEL : 3; + __IOM uint32_t REGEXTTRGEN : 1; + __IOM uint32_t INJSWSC : 1; + __IOM uint32_t REGSWSC : 1; + __IOM uint32_t TSVREFEN : 1; + __IM uint32_t RESERVED4 : 8; + } CTRL2_B; + }; + + /** Sample time register1*/ + union + { + __IOM uint32_t SMPTIM1; + + struct + { + __IOM uint32_t SMPCYCCFG10 : 3; + __IOM uint32_t SMPCYCCFG11 : 3; + __IOM uint32_t SMPCYCCFG12 : 3; + __IOM uint32_t SMPCYCCFG13 : 3; + __IOM uint32_t SMPCYCCFG14 : 3; + __IOM uint32_t SMPCYCCFG15 : 3; + __IOM uint32_t SMPCYCCFG16 : 3; + __IOM uint32_t SMPCYCCFG17 : 3; + __IM uint32_t RESERVED : 8; + } SMPTIM1_B; + }; + + /** Sample time register2*/ + union + { + __IOM uint32_t SMPTIM2; + + struct + { + __IOM uint32_t SMPCYCCFG0 : 3; + __IOM uint32_t SMPCYCCFG1 : 3; + __IOM uint32_t SMPCYCCFG2 : 3; + __IOM uint32_t SMPCYCCFG3 : 3; + __IOM uint32_t SMPCYCCFG4 : 3; + __IOM uint32_t SMPCYCCFG5 : 3; + __IOM uint32_t SMPCYCCFG6 : 3; + __IOM uint32_t SMPCYCCFG7 : 3; + __IOM uint32_t SMPCYCCFG8 : 3; + __IOM uint32_t SMPCYCCFG9 : 3; + __IM uint32_t RESERVED : 2; + } SMPTIM2_B; + }; + + /** Injected channel Data offset register1*/ + union + { + __IOM uint32_t INJDOF1; + + struct + { + __IOM uint32_t INJDOF1 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF1_B; + }; + + /** Injected channel Data offset register2*/ + union + { + __IOM uint32_t INJDOF2; + + struct + { + __IOM uint32_t INJDOF2 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF2_B; + }; + + /** Injected channel Data offset register3*/ + union + { + __IOM uint32_t INJDOF3; + + struct + { + __IOM uint32_t INJDOF3 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF3_B; + }; + + /** Injected channel Data offset register4*/ + union + { + __IOM uint32_t INJDOF4; + + struct + { + __IOM uint32_t INJDOF4 : 12; + __IM uint32_t RESERVED : 20; + } INJDOF4_B; + }; + + /** Analog watchdog high threshold register*/ + union + { + __IOM uint32_t AWDHT; + + struct + { + __IOM uint32_t AWDHT : 12; + __IM uint32_t RESERVED : 20; + } AWDHT_B; + }; + + /** Analog watchdog low threshold register*/ + union + { + __IOM uint32_t AWDLT; + + struct + { + __IOM uint32_t AWDLT : 12; + __IM uint32_t RESERVED : 20; + } AWDLT_B; + }; + + /** Regular channel sequence register1*/ + union + { + __IOM uint32_t REGSEQ1; + + struct + { + __IOM uint32_t REGSEQC13 : 5; + __IOM uint32_t REGSEQC14 : 5; + __IOM uint32_t REGSEQC15 : 5; + __IOM uint32_t REGSEQC16 : 5; + __IOM uint32_t REGSEQLEN : 4; + __IM uint32_t RESERVED : 8; + } REGSEQ1_B; + }; + + /** Regular channel sequence register2*/ + union + { + __IOM uint32_t REGSEQ2; + + struct + { + __IOM uint32_t REGSEQC7 : 5; + __IOM uint32_t REGSEQC8 : 5; + __IOM uint32_t REGSEQC9 : 5; + __IOM uint32_t REGSEQC10 : 5; + __IOM uint32_t REGSEQC11 : 5; + __IOM uint32_t REGSEQC12 : 5; + __IM uint32_t RESERVED : 2; + } REGSEQ2_B; + }; + + /** Regular channel sequence register3*/ + union + { + __IOM uint32_t REGSEQ3; + + struct + { + __IOM uint32_t REGSEQC1 : 5; + __IOM uint32_t REGSEQC2 : 5; + __IOM uint32_t REGSEQC3 : 5; + __IOM uint32_t REGSEQC4 : 5; + __IOM uint32_t REGSEQC5 : 5; + __IOM uint32_t REGSEQC6 : 5; + __IM uint32_t RESERVED : 2; + } REGSEQ3_B; + }; + + /** Injected sequence register*/ + union + { + __IOM uint32_t INJSEQ; + + struct + { + __IOM uint32_t INJSEQC1 : 5; + __IOM uint32_t INJSEQC2 : 5; + __IOM uint32_t INJSEQC3 : 5; + __IOM uint32_t INJSEQC4 : 5; + __IOM uint32_t INJSEQLEN : 2; + __IM uint32_t RESERVED : 10; + } INJSEQ_B; + }; + + /** Injected Data register1*/ + union + { + __IM uint32_t INJDATA1; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA1_B; + }; + + /** Injected Data register2*/ + union + { + __IM uint32_t INJDATA2; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA2_B; + }; + + /** Injected Data register3*/ + union + { + __IM uint32_t INJDATA3; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA3_B; + }; + + /** Injected Data register4*/ + union + { + __IM uint32_t INJDATA4; + + struct + { + __IM uint32_t INJDATA : 16; + __IM uint32_t RESERVED : 16; + } INJDATA4_B; + }; + + /** Regular Data register*/ + union + { + __IOM uint32_t REGDATA; + + struct + { + __IM uint32_t REGDATA : 16; + __IM uint32_t ADC2DATA : 16; + } REGDATA_B; + }; +}ADC_T; + +/** + * @brief External Interrupt(EINT) + */ +typedef struct +{ + /** Interrupt mask register */ + union + { + __IOM uint32_t IMASK; + + struct + { + __IOM uint32_t IMASK0 : 1; + __IOM uint32_t IMASK1 : 1; + __IOM uint32_t IMASK2 : 1; + __IOM uint32_t IMASK3 : 1; + __IOM uint32_t IMASK4 : 1; + __IOM uint32_t IMASK5 : 1; + __IOM uint32_t IMASK6 : 1; + __IOM uint32_t IMASK7 : 1; + __IOM uint32_t IMASK8 : 1; + __IOM uint32_t IMASK9 : 1; + __IOM uint32_t IMASK10 : 1; + __IOM uint32_t IMASK11 : 1; + __IOM uint32_t IMASK12 : 1; + __IOM uint32_t IMASK13 : 1; + __IOM uint32_t IMASK14 : 1; + __IOM uint32_t IMASK15 : 1; + __IOM uint32_t IMASK16 : 1; + __IOM uint32_t IMASK17 : 1; + __IOM uint32_t IMASK18 : 1; + __IM uint32_t RESERVED : 12; + } IMASK_B; + }; + + /** Event mask register */ + union + { + __IOM uint32_t EMASK; + + struct + { + __IOM uint32_t EMASK0 : 1; + __IOM uint32_t EMASK1 : 1; + __IOM uint32_t EMASK2 : 1; + __IOM uint32_t EMASK3 : 1; + __IOM uint32_t EMASK4 : 1; + __IOM uint32_t EMASK5 : 1; + __IOM uint32_t EMASK6 : 1; + __IOM uint32_t EMASK7 : 1; + __IOM uint32_t EMASK8 : 1; + __IOM uint32_t EMASK9 : 1; + __IOM uint32_t EMASK10 : 1; + __IOM uint32_t EMASK11 : 1; + __IOM uint32_t EMASK12 : 1; + __IOM uint32_t EMASK13 : 1; + __IOM uint32_t EMASK14 : 1; + __IOM uint32_t EMASK15 : 1; + __IOM uint32_t EMASK16 : 1; + __IOM uint32_t EMASK17 : 1; + __IOM uint32_t EMASK18 : 1; + __IM uint32_t RESERVED : 12; + } EEN_B; + }; + + /** Rising Trigger Event Enable register */ + union + { + __IOM uint32_t RTEN; + + struct + { + __IOM uint32_t PTEN0 : 1; + __IOM uint32_t PTEN1 : 1; + __IOM uint32_t PTEN2 : 1; + __IOM uint32_t PTEN3 : 1; + __IOM uint32_t PTEN4 : 1; + __IOM uint32_t PTEN5 : 1; + __IOM uint32_t PTEN6 : 1; + __IOM uint32_t PTEN7 : 1; + __IOM uint32_t PTEN8 : 1; + __IOM uint32_t PTEN9 : 1; + __IOM uint32_t PTEN10 : 1; + __IOM uint32_t PTEN11 : 1; + __IOM uint32_t PTEN12 : 1; + __IOM uint32_t PTEN13 : 1; + __IOM uint32_t PTEN14 : 1; + __IOM uint32_t PTEN15 : 1; + __IOM uint32_t PTEN16 : 1; + __IOM uint32_t PTEN17 : 1; + __IOM uint32_t PTEN18 : 1; + __IM uint32_t RESERVED : 12; + } RTEN_B; + }; + + /** Falling Trigger Event Enable register */ + union + { + __IOM uint32_t FTEN; + + struct + { + __IOM uint32_t FTEN0 : 1; + __IOM uint32_t FTEN1 : 1; + __IOM uint32_t FTEN2 : 1; + __IOM uint32_t FTEN3 : 1; + __IOM uint32_t FTEN4 : 1; + __IOM uint32_t FTEN5 : 1; + __IOM uint32_t FTEN6 : 1; + __IOM uint32_t FTEN7 : 1; + __IOM uint32_t FTEN8 : 1; + __IOM uint32_t FTEN9 : 1; + __IOM uint32_t FTEN10 : 1; + __IOM uint32_t FTEN11 : 1; + __IOM uint32_t FTEN12 : 1; + __IOM uint32_t FTEN13 : 1; + __IOM uint32_t FTEN14 : 1; + __IOM uint32_t FTEN15 : 1; + __IOM uint32_t FTEN16 : 1; + __IOM uint32_t FTEN17 : 1; + __IOM uint32_t FTEN18 : 1; + __IM uint32_t RESERVED : 12; + } FTEN_B; + }; + + /** Software Interrupt Enable register */ + union + { + __IOM uint32_t SWINTE; + + struct + { + __IOM uint32_t SWINTE0 : 1; + __IOM uint32_t SWINTE1 : 1; + __IOM uint32_t SWINTE2 : 1; + __IOM uint32_t SWINTE3 : 1; + __IOM uint32_t SWINTE4 : 1; + __IOM uint32_t SWINTE5 : 1; + __IOM uint32_t SWINTE6 : 1; + __IOM uint32_t SWINTE7 : 1; + __IOM uint32_t SWINTE8 : 1; + __IOM uint32_t SWINTE9 : 1; + __IOM uint32_t SWINTE10 : 1; + __IOM uint32_t SWINTE11 : 1; + __IOM uint32_t SWINTE12 : 1; + __IOM uint32_t SWINTE13 : 1; + __IOM uint32_t SWINTE14 : 1; + __IOM uint32_t SWINTE15 : 1; + __IOM uint32_t SWINTE16 : 1; + __IOM uint32_t SWINTE17 : 1; + __IOM uint32_t SWINTE18 : 1; + __IM uint32_t RESERVED : 12; + } SWINTE_B; + }; + + /** Interrupt Flag Enable register */ + union + { + __IOM uint32_t IPEND; + + struct + { + __IOM uint32_t IPEND0 : 1; + __IOM uint32_t IPEND1 : 1; + __IOM uint32_t IPEND2 : 1; + __IOM uint32_t IPEND3 : 1; + __IOM uint32_t IPEND4 : 1; + __IOM uint32_t IPEND5 : 1; + __IOM uint32_t IPEND6 : 1; + __IOM uint32_t IPEND7 : 1; + __IOM uint32_t IPEND8 : 1; + __IOM uint32_t IPEND9 : 1; + __IOM uint32_t IPEND10 : 1; + __IOM uint32_t IPEND11 : 1; + __IOM uint32_t IPEND12 : 1; + __IOM uint32_t IPEND13 : 1; + __IOM uint32_t IPEND14 : 1; + __IOM uint32_t IPEND15 : 1; + __IOM uint32_t IPEND16 : 1; + __IOM uint32_t IPEND17 : 1; + __IOM uint32_t IPEND18 : 1; + __IM uint32_t RESERVED : 12; + } IF_B; + }; +}EINT_T; + +/** + * @brief Independent watchdog(IWDT) + */ +typedef struct +{ + + /** Keyword register */ + union + { + __OM uint32_t KEY; + + struct + { + __OM uint32_t KEY : 16; + __IM uint32_t RESERVED : 16; + } KEY_B; + }; + + /** Frequency Divider register */ + union + { + __IOM uint32_t PSC; + + struct + { + __IOM uint32_t PSC : 3; + __IM uint32_t RESERVED : 29; + } DIV_B; + }; + + /** Reload values register */ + union + { + __IOM uint32_t CNTRLD; + + struct + { + __IOM uint32_t CNTRLD : 12; + __IM uint32_t RESERVED : 20; + } CNTRLD_B; + }; + + /** Status register */ + union + { + __IM uint32_t STS; + + struct + { + __IM uint32_t PSCUFLG : 1; + __IM uint32_t CNTUFLG : 1; + __IM uint32_t RESERVED : 30; + } STS_B; + }; +}IWDT_T; + +/** + * @brief Serial peripheral interface(SPI) + */ +typedef struct +{ + /** Control register 1 */ + union + { + __IOM uint32_t CTRL1; + + struct + { + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t MSMCFG : 1; + __IOM uint32_t BRSEL : 3; + __IOM uint32_t SPIEN : 1; + __IOM uint32_t LSBSEL : 1; + __IOM uint32_t ISSEL : 1; + __IOM uint32_t SSEN : 1; + __IOM uint32_t RXOMEN : 1; + __IOM uint32_t DFLSEL : 1; + __IOM uint32_t CECNXT : 1; + __IOM uint32_t CRCEN : 1; + __IOM uint32_t BMOEN : 1; + __IOM uint32_t BMEN : 1; + __IM uint32_t RESERVED : 16; + } CTRL1_B; + }; + + /** Control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IOM uint32_t RXDEN : 1; + __IOM uint32_t TXDEN : 1; + __IOM uint32_t SSOEN : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t RXBNEIEN : 1; + __IOM uint32_t TXBEIEN : 1; + __IM uint32_t RESERVED2 : 24; + } CTRL2_B; + }; + + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IM uint32_t RXBNEFLG : 1; + __IM uint32_t TXBEFLG : 1; + __IM uint32_t SCHDIR : 1; + __IM uint32_t UDRFLG : 1; + __IOM uint32_t CRCEFLG : 1; + __IM uint32_t MEFLG : 1; + __IM uint32_t OVRFLG : 1; + __IM uint32_t BSYFLG : 1; + __IM uint32_t RESERVED : 24; + } STS_B; + }; + + /** Data register */ + union + { + __IOM uint32_t DATA; + + struct + { + __IOM uint32_t DATA : 16; + __IM uint32_t RESERVED : 16; + } DATA_B; + }; + + /** CRC polynomial register */ + union + { + __IOM uint32_t CRCPOLY; + + struct + { + __IOM uint32_t CRCPOLY : 16; + __IM uint32_t RESERVED : 16; + } CRCPOLY_B; + }; + + /** Receive CRC register */ + union + { + __IM uint32_t RXCRC; + + struct + { + __IM uint32_t RXCRC : 16; + __IM uint32_t RESERVED : 16; + }RXCRC_B; + }; + + /** Transmit CRC register */ + union + { + __IM uint32_t TXCRC; + + struct + { + __IM uint32_t TXCRC : 16; + __IM uint32_t RESERVED : 16; + }TXCRC_B; + }; + + /** Transmit I2S CTRL register */ + union + { + __IOM uint32_t I2SCFG; + + struct + { + __IOM uint32_t CHLEN : 1; + __IOM uint32_t DATLEN : 2; + __IOM uint32_t CPOL : 1; + __IOM uint32_t I2SSSEL : 2; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t PFSSEL : 1; + __IOM uint32_t I2SMOD : 2; + __IOM uint32_t I2SEN : 1; + __IOM uint32_t MODESEL : 1; + __IM uint32_t RESERVED2 : 20; + }I2SCFG_B; + }; + + /** Transmit I2S DIV register */ + union + { + __IOM uint32_t I2SPSC; + + struct + { + __IOM uint32_t I2SPSC : 8; + __IOM uint32_t ODDPSC : 1; + __IOM uint32_t MCIEN : 1; + __IM uint32_t RESERVED1 : 22; + }I2SPSC_B; + }; +}SPI_T; + +/** + * @brief Window watchdog (WWDT) + */ +typedef struct +{ + + /** Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t CNT : 7; + __IOM uint32_t WWDTEN : 1; + __IM uint32_t RESERVED : 24; + } CTRL_B; + }; + + /** Configure register */ + union + { + __IOM uint32_t CFG; + + struct + { + __IOM uint32_t WIN : 7; + __IOM uint32_t TBPSC : 2; + __IOM uint32_t EWIEN : 1; + __IM uint32_t RESERVED : 22; + } CFG_B; + }; + + /** Status register */ + union + { + __IOM uint32_t STS; + + struct + { + __IOM uint32_t EWIFLG : 1; + __IM uint32_t RESERVED : 31; + } STS_B; + }; +}WWDT_T; + +/** + * @brief Secure digital input/output interface (SDIO) + */ +typedef struct +{ + /** Power control register */ + union + { + __IOM uint32_t PWRCTRL; + + struct + { + __IOM uint32_t PWRCTRL : 2; + __IM uint32_t RESERVED : 30; + } PWRCTRL_B; + }; + + /** Clock control register */ + union + { + __IOM uint32_t CLKCTRL; + + struct + { + __IOM uint32_t CLKDIV : 8; + __IOM uint32_t CLKEN : 1; + __IOM uint32_t PWRSAV : 1; + __IOM uint32_t BYPASSEN : 1; + __IOM uint32_t WBSEL : 2; + __IOM uint32_t DEPSEL : 1; + __IOM uint32_t HFCEN : 1; + __IM uint32_t RESERVED : 17; + } CLKCTRL_B; + }; + + /** Argument register */ + union + { + __IOM uint32_t ARG; + + struct + { + __IOM uint32_t CMDARG : 32; + } ARG_B; + }; + + /** Command register */ + union + { + __IOM uint32_t CMD; + + struct + { + __IOM uint32_t CMDINDEX : 6; + __IOM uint32_t WAITRES : 2; + __IOM uint32_t WAITINT : 1; + __IOM uint32_t WENDDATA : 1; + __IOM uint32_t CPSMEN : 1; + __IOM uint32_t SDIOSC : 1; + __IOM uint32_t CMDCPEN : 1; + __IOM uint32_t INTEN : 1; + __IOM uint32_t ATACMD : 1; + __IM uint32_t RESERVED : 17; + } CMD_B; + }; + + /** Command response register */ + union + { + __IM uint32_t CMDRES; + + struct + { + __IM uint32_t CMDRES : 6; + __IM uint32_t RESERVED : 26; + } CMDRES_B; + }; + + /** SDIO response register1 */ + union + { + __IM uint32_t RES1; + + struct + { + __IM uint32_t CARDSTS1 : 32; + } RES1_B; + }; + + /** SDIO response register2 */ + union + { + __IM uint32_t RES2; + + struct + { + __IM uint32_t CARDSTS2 : 32; + } RES2_B; + }; + + /** SDIO response register3 */ + union + { + __IM uint32_t RES3; + + struct + { + __IM uint32_t CARDSTS3 : 32; + } RES3_B; + }; + + /** SDIO response register4 */ + union + { + __IM uint32_t RES4; + + struct + { + __IM uint32_t CARDSTS4 : 32; + } RES4_B; + }; + + /** Data timer register */ + union + { + __IOM uint32_t DATATIME; + + struct + { + __IOM uint32_t DATATIME : 32; + } DTMR_B; + }; + + /** Data length register */ + union + { + __IOM uint32_t DATALEN; + + struct + { + __IOM uint32_t DATALEN : 25; + __IM uint32_t RESERVED : 7; + } DLEN_B; + }; + + /** Data control register */ + union + { + __IOM uint32_t DCTRL; + + struct + { + __IOM uint32_t DTEN : 1; + __IOM uint32_t DTDRCFG : 1; + __IOM uint32_t DTSEL : 1; + __IOM uint32_t DMAEN : 1; + __IOM uint32_t DBSIZE : 4; + __IOM uint32_t RWSTR : 1; + __IOM uint32_t PWSTOP : 1; + __IOM uint32_t RDWAIT : 1; + __IOM uint32_t SDIOF : 1; + __IM uint32_t RESERVED : 20; + } DCTRL_B; + }; + + /** Data count register */ + union + { + __IM uint32_t DCNT; + + struct + { + __IM uint32_t DATACNT : 25; + __IM uint32_t RESERVED : 7; + } DCNT_B; + }; + + /** SDIO status register */ + union + { + __IM uint32_t STS; + + struct + { + __IM uint32_t COMRESP : 1; + __IM uint32_t DBDR : 1; + __IM uint32_t CMDRESTO : 1; + __IM uint32_t DATATO : 1; + __IM uint32_t TXUDRER : 1; + __IM uint32_t RXOVRER : 1; + __IM uint32_t CMDRES : 1; + __IM uint32_t CMDSENT : 1; + __IM uint32_t DATAEND : 1; + __IM uint32_t SBE : 1; + __IM uint32_t DBCP : 1; + __IM uint32_t CMDACT : 1; + __IM uint32_t TXACT : 1; + __IM uint32_t RXACT : 1; + __IM uint32_t TXFHF : 1; + __IM uint32_t RXFHF : 1; + __IM uint32_t TXFF : 1; + __IM uint32_t RXFF : 1; + __IM uint32_t TXFE : 1; + __IM uint32_t RXFE : 1; + __IM uint32_t TXDA : 1; + __IM uint32_t RXDA : 1; + __IM uint32_t SDIOINT : 1; + __IM uint32_t ATAEND : 1; + __IM uint32_t RESERVED : 8; + } STS_B; + }; + + /** SDIO interrupt clear register */ + union + { + __IOM uint32_t ICF; + + struct + { + __IOM uint32_t DBCE : 1; + __IOM uint32_t CRCE : 1; + __IOM uint32_t CRTO : 1; + __IOM uint32_t DTO : 1; + __IOM uint32_t TXFUE : 1; + __IOM uint32_t RXFOE : 1; + __IOM uint32_t CMDRES : 1; + __IOM uint32_t CMDSENT : 1; + __IOM uint32_t DATAEND : 1; + __IOM uint32_t SBE : 1; + __IOM uint32_t DBCP : 1; + __IM uint32_t RESERVED1 : 11; + __IOM uint32_t SDIOIT : 1; + __IOM uint32_t ATAEND : 1; + __IM uint32_t RESERVED2 : 8; + } ICF_B; + }; + + /** SDIO interrupt mask register */ + union + { + __IOM uint32_t MASK; + + struct + { + __IOM uint32_t CCRCFAIL : 1; + __IOM uint32_t DCRCFAIL : 1; + __IOM uint32_t CMDTO : 1; + __IOM uint32_t DATATO : 1; + __IOM uint32_t TXURER : 1; + __IOM uint32_t RXORER : 1; + __IOM uint32_t CMDRESRC : 1; + __IOM uint32_t CMDSENT : 1; + __IOM uint32_t DATAEND : 1; + __IOM uint32_t STRTER : 1; + __IOM uint32_t DBEND : 1; + __IOM uint32_t CMDACT : 1; + __IOM uint32_t TXACT : 1; + __IOM uint32_t RXACT : 1; + __IOM uint32_t TXHFERT : 1; + __IOM uint32_t RXHFFUL : 1; + __IOM uint32_t TXFUL : 1; + __IOM uint32_t RXFUL : 1; + __IOM uint32_t TXEPT : 1; + __IOM uint32_t RXFEIE : 1; + __IOM uint32_t TXDAVB : 1; + __IOM uint32_t RXDAVB : 1; + __IOM uint32_t SDIOINTREC : 1; + __IOM uint32_t ATACLPREC : 1; + __IM uint32_t RESERVEDIE : 8; + } MASK_B; + }; + + __IM uint32_t RESERVED[2]; + + /** SDIO FIFO count register */ + union + { + __IM uint32_t FIFOCNT; + + struct + { + __IM uint32_t FIFOCNT : 24; + __IM uint32_t RESERVED : 8; + } FIFOCNT_B; + }; + + __IM uint32_t RESERVED1[13]; + + /** SDIO data FIFO register */ + union + { + __IOM uint32_t FIFODATA; + + struct + { + __IOM uint32_t FIFODATA : 32; + } FIFODATA_B; + }; +}SDIO_T; + +/** + * @brief Digital to Analog Converter(DAC) + */ +typedef struct +{ + /** Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t ENCH1 : 1; + __IOM uint32_t BUFFDCH1 : 1; + __IOM uint32_t TRGENCH1 : 1; + __IOM uint32_t TRGSELCH1 : 3; + __IOM uint32_t WAVENCH1 : 2; + __IOM uint32_t MAMPSELCH1 : 4; + __IOM uint32_t DMAENCH1 : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ENCH2 : 1; + __IOM uint32_t BUFFDCH2 : 1; + __IOM uint32_t TRGENCH2 : 1; + __IOM uint32_t TRGSELCH2 : 3; + __IOM uint32_t WAVENCH2 : 2; + __IOM uint32_t MAMPSELCH2 : 4; + __IOM uint32_t DMAENCH2 : 1; + __IM uint32_t RESERVED2 : 3; + } CTRL_B; + }; + + /** Software trigger register */ + union + { + __IOM uint32_t SWTRG; + + struct + { + __IOM uint32_t SWTRG1 : 1; + __IOM uint32_t SWTRG2 : 1; + __IM uint32_t RESERVED : 30; + } SWTRG_B; + }; + + /** Channel1 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12R1; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DH12R1_B; + }; + + /** Channel1 12-bit left-aligned register */ + union + { + __IOM uint32_t DH12L1; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED2 : 16; + } DH12L1_B; + }; + + /** Channel1 8-bit right-aligned register */ + union + { + __IOM uint32_t DH8R1; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED : 24; + } DH8R1_B; + }; + + /** Channel2 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12R2; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DH12R2_B; + }; + + /** Channel2 12-bit left-aligned register */ + union + { + __IOM uint32_t DH12L2; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED2 : 16; + }DH12L2_B; + }; + + /** Channel2 8-bit right-aligned register */ + union + { + __IOM uint32_t DH8R2; + + struct + { + __IOM uint32_t DATA : 8; + __IM uint32_t RESERVED : 24; + } DH8R2_B; + }; + + /** Channel1,Channel2 12-bit right-aligned register */ + union + { + __IOM uint32_t DH12RDUAL; + + struct + { + __IOM uint32_t DATACH1 : 12; + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATACH2 : 12; + __IM uint32_t RESERVED2 : 4; + } DH12RDUAL_B; + }; + + /** Channel1,Channel2 12-bit left-aligned register */ + union + { + __IOM uint32_t DH12LDUAL; + + struct + { + __IM uint32_t RESERVED1 : 4; + __IOM uint32_t DATACH1 : 12; + __IM uint32_t RESERVED2 : 4; + __IOM uint32_t DATACH2 : 12; + } DH12LDUAL_B; + }; + + /** Channel1,Channel2 8-bit right-aligned register */ + union + { + __IOM uint32_t DH8RDUAL; + + struct + { + __IOM uint32_t CH1DH : 8; + __IOM uint32_t CH2DH : 8; + __IM uint32_t RESERVED : 16; + } DH8RDUAL_B; + }; + + /** Channel1 data output register */ + union + { + __IOM uint32_t DATAOCH1; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DATAOCH1_B; + }; + + /** Channel2 data output register */ + union + { + __IOM uint32_t DATAOCH2; + + struct + { + __IOM uint32_t DATA : 12; + __IM uint32_t RESERVED : 20; + } DATAOCH2_B; + }; +}DAC_T; + +/** + * @brief EMMC Register + */ +typedef struct +{ + /** SRAM/NOR-Flash chip-select control register */ + union + { + __IOM uint32_t CSCTRL; + + struct + { + __IOM uint32_t MBKEN : 1; + __IOM uint32_t ADMUXEN : 1; + __IOM uint32_t MTYPECFG : 2; + __IOM uint32_t MDBWIDCFG : 2; + __IOM uint32_t NORFMACCEN : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t BURSTEN : 1; + __IOM uint32_t WSPOLCFG : 1; + __IOM uint32_t WRAPBEN : 1; + __IOM uint32_t WTIMCFG : 1; + __IOM uint32_t WREN : 1; + __IOM uint32_t WAITEN : 1; + __IOM uint32_t EXTMODEEN : 1; + __IOM uint32_t WSASYNCEN : 1; + __IOM uint32_t CRAMPSIZECFG : 3; + __IOM uint32_t WRBURSTEN : 1; + __IOM uint32_t RESERVED2 : 12; + }CSCTRL_B; + }; +}SNCTRL_T; + +typedef struct +{ + /** SRAM/NOR-Flash write timing registers */ + union + { + __IOM uint32_t WRTTIM; + + struct + { + __IOM uint32_t ADDRSETCFG : 4; + __IOM uint32_t ADDRHLDCFG : 4; + __IOM uint32_t DATASETCFG : 8; + __IOM uint32_t BUSTURNCFG : 4; + __IOM uint32_t CLKDIVCFG : 4; + __IOM uint32_t DATALATCFG : 4; + __IOM uint32_t ACCMODECFG : 2; + __IM uint32_t RESERVED2 : 2; + }WRTTIM_T; + }; +}SNWCLK_T; + +/** + * @brief Flexible Static Memory Controller + */ +typedef struct +{ + __IO uint32_t SNCTRL_T[8]; +} EMMC_Bank1_T; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t WRTTIM[7]; +} EMMC_Bank1E_T; + +/** + * @brief Flexible Static Memory Controller Bank 2 + */ +typedef struct +{ + /** PC Card/NAND Flash control register 2 */ + union + { + __IOM uint32_t CTRL2; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t WAITFEN : 1; + __IOM uint32_t MBKEN : 1; + __IOM uint32_t MTYPECFG : 1; + __IOM uint32_t DBWIDCFG : 2; + __IOM uint32_t ECCEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t C2RDCFG : 4; + __IOM uint32_t A2RDCFG : 4; + __IOM uint32_t ECCPSCFG : 3; + __IM uint32_t RESERVED3 : 12; + }CTRL2_B; + }; + + /** FIFO status and interrupt register 2 */ + union + { + __IOM uint32_t STSINT2; + + struct + { + __IOM uint32_t IREFLG : 1; + __IOM uint32_t IHLFLG : 1; + __IOM uint32_t IFEFLG : 1; + __IOM uint32_t IREDEN : 1; + __IOM uint32_t IHLDEN : 1; + __IOM uint32_t IFEDEN : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t RESERVED :25; + }STSINT2_B; + }; + /** Common memory space timing register 2 */ + union + { + __IOM uint32_t CMSTIM2; + + struct + { + __IOM uint32_t SET2 : 8; + __IOM uint32_t WAIT2 : 8; + __IOM uint32_t HLD2 : 8; + __IOM uint32_t HIZ2 : 8; + }CMSTIM2_B; + }; + + /** Attribute memory space timing register 2 */ + union + { + __IOM uint32_t AMSTIM2; + + struct + { + __IOM uint32_t SET2 : 8; + __IOM uint32_t WAIT2 : 8; + __IOM uint32_t HLD2 : 8; + __IOM uint32_t HIZ2 : 8; + }AMSTIM2_B; + }; + + __IOM uint32_t RESERVED; + + /** ECC result register 2 */ + union + { + __IM uint32_t ECCRS2; + + struct + { + __IM uint32_t ECCRS2 : 32; + } ECCRS2_B; + }; +}EMMC_Bank2_T; + +/** + * @brief Flexible Static Memory Controller Bank 3 + */ +typedef struct +{ + /** PC Card/NAND Flash control register 3 */ + union + { + __IOM uint32_t CTRL3; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t WAITFEN : 1; + __IOM uint32_t MBKEN : 1; + __IOM uint32_t MTYPECFG : 1; + __IOM uint32_t DBWIDCFG : 2; + __IOM uint32_t ECCEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t C2RDCFG : 4; + __IOM uint32_t A2RDCFG : 4; + __IOM uint32_t ECCPSCFG : 3; + __IM uint32_t RESERVED3 : 12; + }CTRL3_B; + }; + + /** FIFO status and interrupt register 3 */ + union + { + __IOM uint32_t STSINT3; + + struct + { + __IOM uint32_t IREFLG : 1; + __IOM uint32_t IHLFLG : 1; + __IOM uint32_t IFEFLG : 1; + __IOM uint32_t IREDEN : 1; + __IOM uint32_t IHLDEN : 1; + __IOM uint32_t IFEDEN : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t RESERVED :16; + }STSINT3_B; + }; + + /** Common memory space timing register 3 */ + union + { + __IOM uint32_t CMSTIM3; + + struct + { + __IOM uint32_t SET3 : 8; + __IOM uint32_t WAIT3 : 8; + __IOM uint32_t HLD3 : 8; + __IOM uint32_t HIZ3 : 8; + }CMSTIM3_B; + }; + + /** Attribute memory space timing register 3 */ + union + { + __IOM uint32_t AMSTIM3; + + struct + { + __IOM uint32_t SET3 : 8; + __IOM uint32_t WAIT3 : 8; + __IOM uint32_t HLD3 : 8; + __IOM uint32_t HIZ3 : 8; + }AMSTIM3_B; + }; + + __IOM uint32_t RESERVED; + + /** ECC result register 3 */ + union + { + __IM uint32_t ECCRS3; + + struct + { + __IM uint32_t ECCRS3 : 32; + } ECCRS3_B; + }; +}EMMC_Bank3_T; + +/** + * @brief Flexible Static Memory Controller Bank 4 + */ +typedef struct +{ + /** PC Card/NAND Flash control register 4 */ + union + { + __IOM uint32_t CTRL4; + + struct + { + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t WAITFEN : 1; + __IOM uint32_t MBKEN : 1; + __IOM uint32_t MTYPECFG : 1; + __IOM uint32_t DBWIDCFG : 2; + __IOM uint32_t ECCEN : 1; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t C2RDCFG : 4; + __IOM uint32_t A2RDCFG : 4; + __IOM uint32_t ECCPSCFG : 3; + __IM uint32_t RESERVED3 : 12; + }CTRL4_B; + }; + + /** FIFO status and interrupt register 4 */ + union + { + __IOM uint32_t STSINT4; + + struct + { + __IOM uint32_t IREFLG : 1; + __IOM uint32_t IHLFLG : 1; + __IOM uint32_t IFEFLG : 1; + __IOM uint32_t IREDEN : 1; + __IOM uint32_t IHLDEN : 1; + __IOM uint32_t IFEDEN : 1; + __IM uint32_t FEFLG : 1; + __IM uint32_t RESERVED :16; + }STSINT4_B; + }; + + /** Common memory space timing register 4 */ + union + { + __IOM uint32_t CMSTIM4; + + struct + { + __IOM uint32_t SET4 : 8; + __IOM uint32_t WAIT4 : 8; + __IOM uint32_t HLD4 : 8; + __IOM uint32_t HIZ4 : 8; + }CMSTIM4_B; + }; + + /** Attribute memory space timing register 4 */ + union + { + __IOM uint32_t AMSTIM4; + + struct + { + __IOM uint32_t SET4 : 8; + __IOM uint32_t WAIT4 : 8; + __IOM uint32_t HLD4 : 8; + __IOM uint32_t HIZ4 : 8; + }AMSTIM4_B; + }; + + /** I/O space timing register 4 */ + union + { + __IOM uint32_t IOSTIM4; + + struct + { + __IOM uint32_t SET4 : 8; + __IOM uint32_t WAIT4 : 8; + __IOM uint32_t HLD4 : 8; + __IOM uint32_t HIZ4 : 8; + }IOSTIM4_B; + }; +}EMMC_Bank4_T; + +/** + * @brief Queued serial peripheral interface(QSPI) + */ +typedef struct +{ + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + struct + { + __IOM uint32_t DFS : 5; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t CPHA : 1; + __IOM uint32_t CPOL : 1; + __IOM uint32_t TXMODE : 2; + __IM uint32_t RESERVED2 : 2; + __IOM uint32_t SSTEN : 1; + __IM uint32_t RESERVED3 : 7; + __IOM uint32_t FRF : 2; + __IM uint32_t RESERVED4 : 8; + }CTRL1_B; + }; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + struct + { + __IOM uint32_t NDF : 16; + __IM uint32_t RESERVED : 16; + }CTRL2_B; + }; + + /** @brief QSPI Enable register */ + union + { + __IOM uint32_t SSIEN; + struct + { + __IOM uint32_t EN : 1; + __IM uint32_t RESERVED : 31; + }SSIEN_B; + }; + + __IM uint32_t RESERVED; + + /** @brief QSPI Slave enable register */ + union + { + __IOM uint32_t SLAEN; + struct + { + __IOM uint32_t SLAEN : 1; + __IM uint32_t RESERVED : 31; + }SLAEN_B; + }; + + /** @brief Baudrate register */ + union + { + __IOM uint32_t BR; + struct + { + __IOM uint32_t CLKDIV : 16; + __IM uint32_t RESERVED : 16; + }BR_B; + }; + + /** @brief Transmission FIFO threshhold level register */ + union + { + __IOM uint32_t TFTL; + struct + { + __IOM uint32_t TFT : 3; + __IM uint32_t RESERVED1 : 13; + __IOM uint32_t TFTH : 3; + __IM uint32_t RESERVED2 : 13; + }TFTL_B; + }; + + /** @brief Reception FIFO threshhold level register */ + union + { + __IOM uint32_t RFTL; + struct + { + __IOM uint32_t RFT : 3; + __IM uint32_t RESERVED : 29; + }RFTL_B; + }; + + /** @brief Transmission FIFO level register */ + union + { + __IOM uint32_t TFL; + struct + { + __IOM uint32_t TFL : 3; + __IM uint32_t RESERVED : 29; + }TFL_B; + }; + + /** @brief Reception FIFO level register */ + union + { + __IOM uint32_t RFL; + struct + { + __IOM uint32_t RFL : 3; + __IM uint32_t RESERVED : 29; + }RFL_B; + }; + + /** @brief Status register */ + union + { + __IOM uint32_t STS; + struct + { + __IOM uint32_t BUSYF : 1; + __IOM uint32_t TFNF : 1; + __IOM uint32_t TFEF : 1; + __IOM uint32_t RFNEF : 1; + __IOM uint32_t RFFF : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t DCEF : 1; + __IM uint32_t RESERVED2 : 25; + }STS_B; + }; + + /** @brief Interrupt enable register */ + union + { + __IOM uint32_t INTEN; + struct + { + __IOM uint32_t TFEIE : 1; + __IOM uint32_t TFOIE : 1; + __IOM uint32_t RFUIE : 1; + __IOM uint32_t RFOIE : 1; + __IOM uint32_t RFFIE : 1; + __IOM uint32_t MSTIE : 1; + __IM uint32_t RESERVED : 26; + }INTEN_B; + }; + + /** @brief Interrupt status register */ + union + { + __IM uint32_t ISTS; + struct + { + __IM uint32_t TFEIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t RFUIF : 1; + __IM uint32_t RFOIF : 1; + __IM uint32_t RFFIF : 1; + __IM uint32_t MSTIF : 1; + __IM uint32_t RESERVED : 26; + }ISTS_B; + }; + + /** @brief Raw interrupt register */ + union + { + __IM uint32_t RIS; + struct + { + __IM uint32_t TFEIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t RFUIF : 1; + __IM uint32_t RXOIR : 1; + __IM uint32_t RXFIR : 1; + __IM uint32_t MSTIR : 1; + __IM uint32_t RESERVED : 26; + }RIS_B; + }; + + /** @brief Transmission FIFO overflow interrupt clear register */ + union + { + __IM uint32_t TFOIC; + struct + { + __IM uint32_t TFOIC : 1; + __IM uint32_t RESERVED : 31; + }TFOIC_B; + }; + + /** @brief Reception FIFO overflow interrupt clear register */ + union + { + __IM uint32_t RFOIC; + struct + { + __IM uint32_t RFOIC : 1; + __IM uint32_t RESERVED : 31; + }RFOIC_B; + }; + + /** @brief Reception FIFO underflow interrupt clear register */ + union + { + __IM uint32_t RFUIC; + struct + { + __IM uint32_t RFUIC : 1; + __IM uint32_t RESERVED : 31; + }RFUIC_B; + }; + + /** @brief Master interrupt clear register */ + union + { + __IM uint32_t MIC; + struct + { + __IM uint32_t MIC : 1; + __IM uint32_t RESERVED : 31; + }MIC_B; + }; + + /** @brief Interrupt clear register */ + union + { + __IM uint32_t ICF; + struct + { + __IM uint32_t ICF : 1; + __IM uint32_t RESERVED : 31; + }ICF_B; + }; + + __IM uint32_t RESERVED1[5]; + + /** @brief Data register */ + union + { + __IOM uint32_t DATA; + struct + { + __IOM uint32_t DATA : 32; + }DATA_B; + }; + + __IM uint32_t RESERVED2[35]; + + /** @brief Reception sample register */ + union + { + __IOM uint32_t RSD; + struct + { + __IOM uint32_t RSD : 8; + __IM uint32_t RESERVED1 : 8; + __IOM uint32_t RSE : 1; + __IM uint32_t RESERVED2 : 15; + }RSD_B; + }; + + /** @brief Reception sample register */ + union + { + __IOM uint32_t CTRL3; + struct + { + __IOM uint32_t IAT : 2; + __IOM uint32_t ADDRLEN : 4; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t INSLEN : 2; + __IM uint32_t RESERVED2 : 1; + __IOM uint32_t WAITCYC : 5; + __IM uint32_t RESERVED3 : 14; + __IOM uint32_t CSEN : 1; + __IM uint32_t RESERVED4 : 1; + }CTRL3_B; + }; + + __IM uint32_t RESERVED3[66]; + + /** @brief IO switch register */ + union + { + __IOM uint32_t IOSW; + struct + { + __IOM uint32_t IOSW : 1; + __IM uint32_t RESERVED : 31; + }IOSW_B; + }; +}QSPI_T; + +/** + * @brief SEC Inter-integrated circuit (SCI2C) + */ +typedef struct +{ + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + struct + { + __IOM uint32_t MST : 1; + __IOM uint32_t SPD : 2; + __IOM uint32_t SAM : 1; + __IM uint32_t RESERVED1 : 1; + __IOM uint32_t RSTAEN : 1; + __IOM uint32_t SLADIS : 1; + __IOM uint32_t DSA : 1; + __IOM uint32_t TFEIC : 1; + __IOM uint32_t RFFIE : 1; + __IOM uint32_t DSMA : 1; + __IM uint32_t RESERVED2 : 21; + }CTRL1_B; + }; + + /** @brief Master address register */ + union + { + __IOM uint32_t TARADDR; + struct + { + __IOM uint32_t ADDR : 10; + __IOM uint32_t STA : 1; + __IOM uint32_t GCEN : 1; + __IOM uint32_t MAM : 1; + __IM uint32_t RESERVED : 19; + }TARADDR_B; + }; + + /** @brief Slave address register */ + union + { + __IOM uint32_t SLAADDR; + struct + { + __IOM uint32_t ADDR : 10; + __IM uint32_t RESERVED : 22; + }SLAADDR_B; + }; + + /** @brief High speed master code register */ + union + { + __IOM uint32_t HSMC; + struct + { + __IOM uint32_t HSMC : 4; + __IM uint32_t RESERVED : 28; + }HSMC_B; + }; + + /** @brief Data register */ + union + { + __IOM uint32_t DATA; + struct + { + __IOM uint32_t DATA : 8; + __IOM uint32_t CMD : 1; + __IOM uint32_t STOP : 1; + __IM uint32_t RESERVED : 22; + }DATA_B; + }; + + /** @brief Standard speed clock high counter register */ + union + { + __IOM uint32_t SSCHC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }SSCHC_B; + }; + + /** @brief Standard speed clock low counter register */ + union + { + __IOM uint32_t SSCLC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }SSCLC_B; + }; + + /** @brief Fast speed clock high counter register */ + union + { + __IOM uint32_t FSCHC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }FSCHC_B; + }; + + /** @brief Fast speed clock low counter register */ + union + { + __IOM uint32_t FSCLC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }FSCLC_B; + }; + + /** @brief High speed clock high counter */ + union + { + __IOM uint32_t HSCHC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }HSCHC_B; + }; + + /** @brief High speed clock low counter register */ + union + { + __IOM uint32_t HSCLC; + struct + { + __IOM uint32_t CNT : 16; + __IM uint32_t RESERVED : 16; + }HSCLC_B; + }; + + /** @brief Interrupt status register */ + union + { + __IM uint32_t INTSTS; + struct + { + __IM uint32_t RFUIF : 1; + __IM uint32_t RFOIF : 1; + __IM uint32_t RFFIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t TFEIF : 1; + __IM uint32_t RRIF : 1; + __IM uint32_t TAIF : 1; + __IM uint32_t RDIF : 1; + __IM uint32_t ACTIF : 1; + __IM uint32_t STPDIF : 1; + __IM uint32_t STADIF : 1; + __IM uint32_t GCIF : 1; + __IM uint32_t RSTADIF : 1; + __IM uint32_t MOHIF : 1; + __IM uint32_t RESERVED : 18; + }INTSTS_B; + }; + + /** @brief Interrupt enable register */ + union + { + __IOM uint32_t INTEN; + struct + { + __IOM uint32_t RFUIE : 1; + __IOM uint32_t RFOIE : 1; + __IOM uint32_t RFFIE : 1; + __IOM uint32_t TFOIE : 1; + __IOM uint32_t TFEIE : 1; + __IOM uint32_t RRIE : 1; + __IOM uint32_t TAIE : 1; + __IOM uint32_t RDIE : 1; + __IOM uint32_t ACTIE : 1; + __IOM uint32_t STPDIE : 1; + __IOM uint32_t STADIE : 1; + __IOM uint32_t GCIE : 1; + __IOM uint32_t RSTADIE : 1; + __IOM uint32_t MOHIE : 1; + __IM uint32_t RESERVED : 18; + }INTEN_B; + }; + + /** @brief Raw interrupt status register */ + union + { + __IM uint32_t RIS; + struct + { + __IM uint32_t RFUIF : 1; + __IM uint32_t RFOIF : 1; + __IM uint32_t RFFIF : 1; + __IM uint32_t TFOIF : 1; + __IM uint32_t TFEIF : 1; + __IM uint32_t RRIF : 1; + __IM uint32_t TAIF : 1; + __IM uint32_t RDIF : 1; + __IM uint32_t ACTIF : 1; + __IM uint32_t STPDIF : 1; + __IM uint32_t STADIF : 1; + __IM uint32_t GCIF : 1; + __IM uint32_t RSTADIF : 1; + __IM uint32_t RESERVED : 18; + }RIS_B; + }; + + /** @brief Reception FIFO threshold register */ + union + { + __IOM uint32_t RFT; + struct + { + __IOM uint32_t RFT : 8; + __IM uint32_t RESERVED : 24; + }RFT_B; + }; + + /** @brief Transmission FIFO threshold register */ + union + { + __IOM uint32_t TFT; + struct + { + __IOM uint32_t TFT : 8; + __IM uint32_t RESERVED : 24; + }TFT_B; + }; + + /** @brief Interruption clear register */ + union + { + __IM uint32_t INTCLR; + struct + { + __IM uint32_t INTCLR : 1; + __IM uint32_t RESERVED : 31; + }INTCLR_B; + }; + + /** @brief Reception FIFO underflow interruption clear register */ + union + { + __IM uint32_t RFUIC; + struct + { + __IM uint32_t RFUIC : 1; + __IM uint32_t RESERVED : 31; + }RFUIC_B; + }; + + /** @brief Reception FIFO overflow interruption clear register */ + union + { + __IM uint32_t RFOIC; + struct + { + __IM uint32_t RFOIC : 1; + __IM uint32_t RESERVED : 31; + }RFOIC_B; + }; + + /** @brief Transmission FIFO overflow interruption clear register */ + union + { + __IM uint32_t TFOIC; + struct + { + __IM uint32_t TFOIC : 1; + __IM uint32_t RESERVED : 31; + }TFOIC_B; + }; + + /** @brief Reception request interruption clear register */ + union + { + __IM uint32_t RRIC; + struct + { + __IM uint32_t RRIC : 1; + __IM uint32_t RESERVED : 31; + }RRIC_B; + }; + + /** @brief Transmission abort interruption clear register */ + union + { + __IM uint32_t TAIC; + struct + { + __IM uint32_t TAIC : 1; + __IM uint32_t RESERVED : 31; + }TAIC_B; + }; + + /** @brief Receive done interruption clear register */ + union + { + __IM uint32_t RDIC; + struct + { + __IM uint32_t RDIC : 1; + __IM uint32_t RESERVED : 31; + }RDIC_B; + }; + + /** @brief Activity interruption clear register */ + union + { + __IM uint32_t AIC; + struct + { + __IM uint32_t AIC : 1; + __IM uint32_t RESERVED : 31; + }AIC_B; + }; + + /** @brief Stop detection interruption clear register */ + union + { + __IM uint32_t STPDIC; + struct + { + __IM uint32_t STPDIC : 1; + __IM uint32_t RESERVED : 31; + }STPDIC_B; + }; + + /** @brief Start detection interruption clear register */ + union + { + __IM uint32_t STADIC; + struct + { + __IM uint32_t STADIC : 1; + __IM uint32_t RESERVED : 31; + }STADIC_B; + }; + + /** @brief General call interruption clear register */ + union + { + __IM uint32_t GCIC; + struct + { + __IM uint32_t GCIC : 1; + __IM uint32_t RESERVED : 31; + }GCIC_B; + }; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + struct + { + __IOM uint32_t I2CEN : 1; + __IOM uint32_t ABR : 1; + __IOM uint32_t TCB : 1; + __IM uint32_t RESERVED : 29; + }CTRL2_B; + }; + + /** @brief Status register 1 */ + union + { + __IM uint32_t STS1; + struct + { + __IM uint32_t ACTF : 1; + __IM uint32_t TFNFF : 1; + __IM uint32_t TFEF : 1; + __IM uint32_t RFNEF : 1; + __IM uint32_t RFFF : 1; + __IM uint32_t MAF : 1; + __IM uint32_t SAF : 1; + __IM uint32_t RESERVED : 24; + }STS1_B; + }; + + /** @brief Transmission FIFO level */ + union + { + __IOM uint32_t TFL; + struct + { + __IOM uint32_t TFL : 4; + __IM uint32_t RESERVED : 28; + }TFL_B; + }; + + /** @brief Reception FIFO level */ + union + { + __IOM uint32_t RFL; + struct + { + __IOM uint32_t RFL : 4; + __IM uint32_t RESERVED : 28; + }RFL_B; + }; + + /** @brief SDA hold time length register */ + union + { + __IOM uint32_t SDAHOLD; + struct + { + __IOM uint32_t TXHOLD : 16; + __IOM uint32_t RXHOLD : 8; + __IM uint32_t RESERVED : 8; + }SDAHOLD_B; + }; + + /** @brief Transmission abort source register */ + union + { + __IM uint32_t TAS; + struct + { + __IM uint32_t AD7NA : 1; + __IM uint32_t AD10NA1 : 1; + __IM uint32_t AD10NA2 : 1; + __IM uint32_t TDNA : 1; + __IM uint32_t GCNA : 1; + __IM uint32_t GCR : 1; + __IM uint32_t HSAD : 1; + __IM uint32_t SNR : 1; + __IM uint32_t RNR10B : 1; + __IM uint32_t MSTDIS : 1; + __IM uint32_t ARBLOST : 1; + __IM uint32_t LFTF : 1; + __IM uint32_t SAL : 1; + __IM uint32_t SRI : 1; + __IM uint32_t USRARB : 1; + __IM uint32_t FLUCNT : 1; + __IM uint32_t RESERVED : 16; + }TAS_B; + }; + + /** @brief Slave data NACK only register */ + union + { + __IOM uint32_t SDNO; + struct + { + __IOM uint32_t NACK : 1; + __IM uint32_t RESERVED : 31; + }SDNO_B; + }; + + /** @brief DMA control register */ + union + { + __IOM uint32_t DMACTRL; + struct + { + __IOM uint32_t RXEN : 1; + __IOM uint32_t TXEN : 1; + __IM uint32_t RESERVED : 30; + }DMACTRL_B; + }; + + /** @brief DMA transmission data level register */ + union + { + __IOM uint32_t DTDL; + struct + { + __IOM uint32_t DTDL : 4; + __IM uint32_t RESERVED : 28; + }DTDL_B; + }; + + /** @brief DMA teception data level register */ + union + { + __IOM uint32_t DRDL; + struct + { + __IOM uint32_t DRDL : 4; + __IM uint32_t RESERVED : 28; + }DRDL_B; + }; + + /** @brief SDA delay register */ + union + { + __IOM uint32_t SDADLY; + struct + { + __IOM uint32_t SDADLY : 8; + __IM uint32_t RESERVED : 24; + }SDADLY_B; + }; + + /** @brief Genernal call ACK register */ + union + { + __IOM uint32_t GCA; + struct + { + __IOM uint32_t GCA : 1; + __IM uint32_t RESERVED : 31; + }GCA_B; + }; + + /** @brief Status register 2 */ + union + { + __IM uint32_t STS2; + struct + { + __IM uint32_t I2CEN : 1; + __IM uint32_t SDWB : 1; + __IM uint32_t SRDL : 1; + __IM uint32_t RESERVED : 29; + }STS2_B; + }; + + /** @brief Low speed spike suppression limit */ + union + { + __IOM uint32_t LSSSL; + struct + { + __IOM uint32_t LSSSL : 8; + __IM uint32_t RESERVED : 24; + }LSSSL_B; + }; + + /** @brief High speed spike suppression limit */ + union + { + __IOM uint32_t HSSSL; + struct + { + __IOM uint32_t HSSSL : 8; + __IM uint32_t RESERVED : 24; + }HSSSL_B; + }; + + uint32_t RESERVED[22]; + + /** @brief Switch register */ + union + { + __IOM uint32_t SW; + struct + { + __IOM uint32_t SW : 1; + __IM uint32_t RESERVED : 31; + }SW_B; + }; +}SCI2C_T; + +/** + * @brief Dynamic memory controler (DMC) + */ +typedef struct +{ + /** @brief Configuraion register */ + union + { + __IOM uint32_t CFG; + struct + { + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t BAWCFG : 2; + __IOM uint32_t RAWCFG : 4; + __IOM uint32_t CAWCFG : 4; + __IOM uint32_t DWCFG : 2; + __IM uint32_t RESERVED2 : 16; + }CFG_B; + }; + + /** @brief Timing register 0 */ + union + { + __IOM uint32_t TIM0; + struct + { + __IOM uint32_t CASLSEL0 : 2; + __IOM uint32_t RASMINTSEL : 4; + __IOM uint32_t DTIMSEL : 3; + __IOM uint32_t PCPSEL : 3; + __IOM uint32_t WRTIMSEL : 2; + __IOM uint32_t ARPSEL : 4; + __IOM uint32_t XSR0 : 4; + __IOM uint32_t ATACP : 4; + __IOM uint32_t ECASLSEL1 : 1; + __IOM uint32_t EXSR1 : 5; + }TIM0_B; + }; + + /** @brief Timing register 1 */ + union + { + __IOM uint32_t TIM1; + struct + { + __IOM uint32_t STBTIM : 16; + __IOM uint32_t ARNUMCFG : 4; + __IM uint32_t RESERVED : 12; + }TIM1_B; + }; + + /** @brief Control register 1 */ + union + { + __IOM uint32_t CTRL1; + struct + { + __IOM uint32_t INIT : 1; + __IOM uint32_t SRMEN : 1; + __IOM uint32_t PDMEN : 1; + __IOM uint32_t PCACFG : 1; + __IOM uint32_t FRBSREN : 1; + __IOM uint32_t FRASREN : 1; + __IOM uint32_t RDNUMMCFG : 3; + __IOM uint32_t MODESET : 1; + __IM uint32_t RESERVED1 : 1; + __IM uint32_t SRMFLG : 1; + __IOM uint32_t BANKNUMCFG : 5; + __IM uint32_t RESERVED2 : 15; + }CTRL1_B; + }; + + /** @brief Refresh register */ + union + { + __IOM uint32_t REF; + struct + { + __IOM uint32_t RCYCCFG : 16; + __IM uint32_t RESERVED : 16; + }REF_B; + }; + + /** @brief Chip select register */ + union + { + __IOM uint32_t CHIPSEL; + struct + { + __IM uint32_t RESERVED : 16; + __IOM uint32_t BACHIPSEL : 16; + + }CHIPSEL_B; + }; + + __IM uint32_t RESERVED[15]; + + /** @brief Mask register */ + union + { + __IOM uint32_t MASK; + struct + { + __IOM uint32_t MSIZESEL : 5; + __IOM uint32_t MTYPESEL : 3; + __IM uint32_t RESERVED : 24; + }MASK_B; + }; + + __IM uint32_t RESERVED1[234]; + + /** @brief Switch register */ + union + { + __IOM uint32_t SW; + struct + { + __IOM uint32_t MCSW : 1; + __IM uint32_t RESERVED : 31; + }SW_B; + }; + + /** @brief Control register 2 */ + union + { + __IOM uint32_t CTRL2; + struct + { + __IOM uint32_t CPHACFG : 1; + __IOM uint32_t RDDEN : 1; + __IOM uint32_t RDDCFG : 3; + __IOM uint32_t WPEN : 1; + __IM uint32_t RESERVED : 26; + }CTRL2_B; + }; +}DMC_T; + +/** + * @brief Debug MCU(DBGMCU) + */ +typedef struct +{ + /** @brief ID register */ + union + { + __IOM uint32_t IDCODE; + struct + { + __IOM uint32_t EQR : 12; + __IM uint32_t RESERVED : 4; + __IOM uint32_t WVR : 16; + }IDCODE_B; + }; + + /** @brief Control register */ + union + { + __IOM uint32_t CFG; + struct + { + __IOM uint32_t SLEEP_CLK_STS : 1; + __IOM uint32_t STOP_CLK_STS : 1; + __IOM uint32_t STANDBY_CLK_STS : 1; + __IM uint32_t RESERVED1 : 2; + __IOM uint32_t IOEN : 1; + __IOM uint32_t MODE : 2; + __IOM uint32_t IWDT_STS : 1; + __IOM uint32_t WWDT_STS : 1; + __IOM uint32_t TMR1_STS : 1; + __IOM uint32_t TMR2_STS : 1; + __IOM uint32_t TMR3_STS : 1; + __IOM uint32_t TMR4_STS : 1; + __IOM uint32_t CAN1_STS : 1; + __IOM uint32_t I2C1_SMBUS_TIMEOUT_STS : 1; + __IOM uint32_t I2C2_SMBUS_TIMEOUT_STS : 1; + __IOM uint32_t TMR8_STS : 1; + __IOM uint32_t TMR5_STS : 1; + __IOM uint32_t TMR6_STS : 1; + __IOM uint32_t TMR7_STS : 1; + __IOM uint32_t CAN2_STS : 1; + __IM uint32_t RESERVED2 : 3; + __IOM uint32_t TMR12_STS : 1; + __IOM uint32_t TMR13_STS : 1; + __IOM uint32_t TMR14_STS : 1; + __IOM uint32_t TMR9_STS : 1; + __IOM uint32_t TMR10_STS : 1; + __IOM uint32_t TMR11_STS : 1; + __IM uint32_t RESERVED3 : 1; + }CFG_B; + }; +}DBGMCU_T; + +/** + * @brief USB Device controler(USBD) + */ +typedef union +{ + __IOM uint32_t EP; + + struct + { + __IOM uint32_t ADDR : 4; + __IOM uint32_t TXSTS : 2; + __IOM uint32_t TXDTOG : 1; + __IOM uint32_t CTFT : 1; + __IOM uint32_t KIND : 1; + __IOM uint32_t TYPE : 2; + __IOM uint32_t SETUP : 1; + __IOM uint32_t RXSTS : 2; + __IOM uint32_t RXDTOG : 1; + __IOM uint32_t CTFR : 1; + __IM uint32_t RESERVED : 16; + }EP_B; +}USB_EP_REG_T; + +typedef struct +{ + /** Endpoint */ + USB_EP_REG_T EP[8]; + + __IM uint32_t RESERVED[8]; + + /** @brief Control register */ + union + { + __IOM uint32_t CTRL; + + struct + { + __IOM uint32_t FORRST : 1; + __IOM uint32_t PWRDOWN : 1; + __IOM uint32_t LPWREN : 1; + __IOM uint32_t FORSUS : 1; + __IOM uint32_t WUPREQ : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ESOFIEN : 1; + __IOM uint32_t SOFIEN : 1; + __IOM uint32_t RSTIEN : 1; + __IOM uint32_t SUSIEN : 1; + __IOM uint32_t WUPIEN : 1; + __IOM uint32_t ERRIEN : 1; + __IOM uint32_t PMAOUIEN : 1; + __IOM uint32_t CTRIEN : 1; + __IM uint32_t RESERVED2 : 16; + }CTRL_B; + }; + + /** @brief Interrupt status register */ + union + { + __IOM uint32_t INTSTS; + + struct + { + __IOM uint32_t EPID : 4; + __IOM uint32_t DOT : 1; + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t ESOFFLG : 1; + __IOM uint32_t SOFFLG : 1; + __IOM uint32_t RSTREQ : 1; + __IOM uint32_t SUSREQ : 1; + __IOM uint32_t WUPREQ : 1; + __IOM uint32_t ERRFLG : 1; + __IOM uint32_t PMOFLG : 1; + __IOM uint32_t CTFLG : 1; + __IM uint32_t RESERVED2 : 16; + }INTSTS_B; + }; + + /** @brief Frame number register */ + union + { + __IM uint32_t FRANUM; + + struct + { + __IM uint32_t FRANUM : 11; + __IM uint32_t LSOFNUM : 2; + __IM uint32_t LOCK : 1; + __IM uint32_t RXDMSTS : 1; + __IM uint32_t RXDPSTS : 1; + __IM uint32_t RESERVED : 16; + }FRANUM_B; + }; + + /** @brief Device address register */ + union + { + __IOM uint32_t ADDR; + + struct + { + __IOM uint32_t ADDR : 7; + __IOM uint32_t USBDEN : 1; + __IM uint32_t RESERVED : 24; + }ADDR_B; + }; + + /** @brief Buffer table address register */ + union + { + __IOM uint32_t BUFFTB; + + struct + { + __IM uint32_t RESERVED1 : 3; + __IOM uint32_t BUFFTB : 13; + __IM uint32_t RESERVED2 : 16; + }BUFFTB_B; + }; + + __IM uint32_t RESERVED1[43]; + + /** @brief Buffer table address register */ + union + { + __IOM uint32_t SWITCH; + + struct + { + __IOM uint32_t SWITCH : 1; + __IM uint32_t RESERVED : 31; + }SWITCH_B; + }; +}USBD_T; + +/** FMC base address in the alias region */ +#define FMC_BASE ((uint32_t)0x08000000) +/** SRAM base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) +/** Peripheral base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) + +/** SRAM base address in the bit-band region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) +/** Peripheral base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) + +/** EMMC registers base address */ +#define EMMC_R_BASE ((uint32_t)0xA0000000) +/** QSPI registers base address */ +#define QSPI_BASE ((uint32_t)0xA0000000) +/** DMC registers base address */ +#define DMC_BASE ((uint32_t)0xA0000000) + +/** Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TMR2_BASE (APB1PERIPH_BASE + 0x0000) +#define TMR3_BASE (APB1PERIPH_BASE + 0x0400) +#define TMR4_BASE (APB1PERIPH_BASE + 0x0800) +#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TMR6_BASE (APB1PERIPH_BASE + 0x1000) +#define TMR7_BASE (APB1PERIPH_BASE + 0x1400) +#define TMR12_BASE (APB1PERIPH_BASE + 0x1800) +#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TMR14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDT_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define USBD_BASE (APB1PERIPH_BASE + 0X5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BAKPR_BASE (APB1PERIPH_BASE + 0x6C00) +#define PMU_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EINT_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TMR1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TMR8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TMR15_BASE (APB2PERIPH_BASE + 0x4000) +#define TMR16_BASE (APB2PERIPH_BASE + 0x4400) +#define TMR17_BASE (APB2PERIPH_BASE + 0x4800) +#define TMR9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TMR10_BASE (APB2PERIPH_BASE + 0x5000) +#define TMR11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCM_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +/** FMC registers base address */ +#define FMC_R_BASE (AHBPERIPH_BASE + 0x2000) +/** FMC Option Bytes base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) + +/** EMMC Bank1 registers base address */ +#define EMMC_Bank1_R_BASE (EMMC_R_BASE + 0x0000) +/** EMMC Bank1E registers base address */ +#define EMMC_Bank1E_R_BASE (EMMC_R_BASE + 0x0104) +/** EMMC Bank2 registers base address */ +#define EMMC_Bank2_R_BASE (EMMC_R_BASE + 0x0060) +/** EMMC Bank3 registers base address */ +#define EMMC_Bank3_R_BASE (EMMC_R_BASE + 0x0080) +/**EMMC Bank4 registers base address */ +#define EMMC_Bank4_R_BASE (EMMC_R_BASE + 0x00A0) + +/** Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t)0xE0042000) + +#define CRC ((CRC_T *) CRC_BASE) +#define RTC ((RTC_T *) RTC_BASE) +#define PMU ((PMU_T *) PMU_BASE) +#define BAKPR ((BAKPR_T *) BAKPR_BASE) +#define TMR1 ((TMR_T *) TMR1_BASE) +#define TMR2 ((TMR_T *) TMR2_BASE) +#define TMR3 ((TMR_T *) TMR3_BASE) +#define TMR4 ((TMR_T *) TMR4_BASE) +#define TMR5 ((TMR_T *) TMR5_BASE) +#define TMR6 ((TMR_T *) TMR6_BASE) +#define TMR7 ((TMR_T *) TMR7_BASE) +#define TMR8 ((TMR_T *) TMR8_BASE) +#define TMR9 ((TMR_T *) TMR9_BASE) +#define TMR10 ((TMR_T *) TMR10_BASE) +#define TMR11 ((TMR_T *) TMR11_BASE) +#define TMR12 ((TMR_T *) TMR12_BASE) +#define TMR13 ((TMR_T *) TMR13_BASE) +#define TMR14 ((TMR_T *) TMR14_BASE) +#define TMR15 ((TMR_T *) TMR15_BASE) +#define TMR16 ((TMR_T *) TMR16_BASE) +#define TMR17 ((TMR_T *) TMR17_BASE) + +#define DMA1 ((DMA_T *) DMA1_BASE) +#define DMA2 ((DMA_T *) DMA2_BASE) + +#define DMA1_Channel1 ((DMA_Channel_T *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_T *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_T *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_T *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_T *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_T *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_T *) DMA1_Channel7_BASE) + +#define DMA2_Channel1 ((DMA_Channel_T *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_T *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_T *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_T *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_T *) DMA2_Channel5_BASE) + +#define CAN1 ((CAN_T *) CAN1_BASE) +#define CAN2 ((CAN_T *) CAN2_BASE) + +#define I2C1 ((I2C_T *) I2C1_BASE) +#define I2C2 ((I2C_T *) I2C2_BASE) + +#define OB ((OB_T *) OB_BASE) + +#define ADC1 ((ADC_T *) ADC1_BASE) +#define ADC2 ((ADC_T *) ADC2_BASE) +#define ADC3 ((ADC_T *) ADC3_BASE) + +#define EINT ((EINT_T *) EINT_BASE) + +#define IWDT ((IWDT_T *) IWDT_BASE) +#define SDIO ((SDIO_T *) SDIO_BASE) +#define DAC ((DAC_T *) DAC_BASE) + +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) + +#define WWDT ((WWDT_T *) WWDT_BASE) +#define USART2 ((USART_T *) USART2_BASE) +#define USART3 ((USART_T *) USART3_BASE) +#define UART4 ((USART_T *) UART4_BASE) +#define UART5 ((USART_T *) UART5_BASE) +#define AFIO ((AFIO_T *) AFIO_BASE) +#define GPIOA ((GPIO_T *) GPIOA_BASE) +#define GPIOB ((GPIO_T *) GPIOB_BASE) +#define GPIOC ((GPIO_T *) GPIOC_BASE) +#define GPIOD ((GPIO_T *) GPIOD_BASE) +#define GPIOE ((GPIO_T *) GPIOE_BASE) +#define GPIOF ((GPIO_T *) GPIOF_BASE) +#define GPIOG ((GPIO_T *) GPIOG_BASE) +#define USART1 ((USART_T *) USART1_BASE) +#define RCM ((RCM_T *) RCM_BASE) +#define FMC ((FMC_T *) FMC_R_BASE) +#define USBD ((USBD_T *)USBD_BASE) + +#define EMMC_Bank1 ((EMMC_Bank1_T *) EMMC_Bank1_R_BASE) +#define EMMC_Bank1E ((EMMC_Bank1E_T *)EMMC_Bank1E_R_BASE) +#define EMMC_Bank2 ((EMMC_Bank2_T *) EMMC_Bank2_R_BASE) +#define EMMC_Bank3 ((EMMC_Bank3_T *) EMMC_Bank3_R_BASE) +#define EMMC_Bank4 ((EMMC_Bank4_T *) EMMC_Bank4_R_BASE) + +#define DBGMCU ((DBGMCU_T *) DBGMCU_BASE) + +#define I2C3 ((SCI2C_T *)(I2C1_BASE)) +#define I2C4 ((SCI2C_T *)(I2C2_BASE)) + +#if defined (APM32F10X_MD) || defined (APM32F10X_LD) +#define QSPI ((QSPI_T *)QSPI_BASE) +#elif defined (APM32F10X_HD) +#define DMC ((DMC_T *)DMC_BASE) +#endif + +/* Define one bit mask */ +#define BIT0 ((uint32_t)0x00000001) +#define BIT1 ((uint32_t)0x00000002) +#define BIT2 ((uint32_t)0x00000004) +#define BIT3 ((uint32_t)0x00000008) +#define BIT4 ((uint32_t)0x00000010) +#define BIT5 ((uint32_t)0x00000020) +#define BIT6 ((uint32_t)0x00000040) +#define BIT7 ((uint32_t)0x00000080) +#define BIT8 ((uint32_t)0x00000100) +#define BIT9 ((uint32_t)0x00000200) +#define BIT10 ((uint32_t)0x00000400) +#define BIT11 ((uint32_t)0x00000800) +#define BIT12 ((uint32_t)0x00001000) +#define BIT13 ((uint32_t)0x00002000) +#define BIT14 ((uint32_t)0x00004000) +#define BIT15 ((uint32_t)0x00008000) +#define BIT16 ((uint32_t)0x00010000) +#define BIT17 ((uint32_t)0x00020000) +#define BIT18 ((uint32_t)0x00040000) +#define BIT19 ((uint32_t)0x00080000) +#define BIT20 ((uint32_t)0x00100000) +#define BIT21 ((uint32_t)0x00200000) +#define BIT22 ((uint32_t)0x00400000) +#define BIT23 ((uint32_t)0x00800000) +#define BIT24 ((uint32_t)0x01000000) +#define BIT25 ((uint32_t)0x02000000) +#define BIT26 ((uint32_t)0x04000000) +#define BIT27 ((uint32_t)0x08000000) +#define BIT28 ((uint32_t)0x10000000) +#define BIT29 ((uint32_t)0x20000000) +#define BIT30 ((uint32_t)0x40000000) +#define BIT31 ((uint32_t)0x80000000) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +#ifdef __cplusplus +} +#endif + +#endif /* __APM32F10x_H */ + + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h new file mode 100644 index 0000000000..2054757063 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h @@ -0,0 +1,29 @@ +/*! + * @file system_apm32f10x.h + * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#ifndef __SYSTEM_APM32F10X_H +#define __SYSTEM_APM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_APM32F10X_H */ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s new file mode 100644 index 0000000000..d82311b15e --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s @@ -0,0 +1,354 @@ +;/*! +; * @file startup_apm32f10x_hd.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd +; * +; * @version V1.0.1 +; * +; * @date 2021-03-23 +; * +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FMC_IRQHandler ; Flash + DCD RCM_IRQHandler ; RCM + DCD EINT0_IRQHandler ; EINT Line 0 + DCD EINT1_IRQHandler ; EINT Line 1 + DCD EINT2_IRQHandler ; EINT Line 2 + DCD EINT3_IRQHandler ; EINT Line 3 + DCD EINT4_IRQHandler ; EINT Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX + DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EINT9_5_IRQHandler ; EINT Line 9..5 + DCD TMR1_BRK_IRQHandler ; TMR1 Break + DCD TMR1_UP_IRQHandler ; TMR1 Update + DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR4_IRQHandler ; TMR4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EINT15_10_IRQHandler ; EINT Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line + DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend + DCD TMR8_BRK_IRQHandler ; TMR8 Break + DCD TMR8_UP_IRQHandler ; TMR8 Update + DCD TMR8_TRG_COM_IRQHandler ; TMR8 Trigger and Commutation + DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD EMMC_IRQHandler ; EMMC + DCD SDIO_IRQHandler ; SDIO + DCD TMR5_IRQHandler ; TMR5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TMR6_IRQHandler ; TMR6 + DCD TMR7_IRQHandler ; TMR7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD 0 ; Reserved + DCD USBD2_HP_CAN2_TX_IRQHandler ; USBD2 High Priority or CAN2 TX + DCD USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low Priority or CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EINT9_5_IRQHandler [WEAK] + EXPORT TMR1_BRK_IRQHandler [WEAK] + EXPORT TMR1_UP_IRQHandler [WEAK] + EXPORT TMR1_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EINT15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBDWakeUp_IRQHandler [WEAK] + EXPORT TMR8_BRK_IRQHandler [WEAK] + EXPORT TMR8_UP_IRQHandler [WEAK] + EXPORT TMR8_TRG_COM_IRQHandler [WEAK] + EXPORT TMR8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT EMMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TMR5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TMR6_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + EXPORT USBD2_HP_CAN2_TX_IRQHandler [WEAK] + EXPORT USBD2_LP_CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + +WWDT_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCM_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USBD1_HP_CAN1_TX_IRQHandler +USBD1_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EINT9_5_IRQHandler +TMR1_BRK_IRQHandler +TMR1_UP_IRQHandler +TMR1_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EINT15_10_IRQHandler +RTCAlarm_IRQHandler +USBDWakeUp_IRQHandler +TMR8_BRK_IRQHandler +TMR8_UP_IRQHandler +TMR8_TRG_COM_IRQHandler +TMR8_CC_IRQHandler +ADC3_IRQHandler +EMMC_IRQHandler +SDIO_IRQHandler +TMR5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TMR6_IRQHandler +TMR7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler +USBD2_HP_CAN2_TX_IRQHandler +USBD2_LP_CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;*******************************END OF FILE************************************ + diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s new file mode 100644 index 0000000000..95ea8f5f22 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s @@ -0,0 +1,301 @@ +;/*! +; * @file startup_apm32f10x_md.s +; * +; * @brief CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md +; * +; * @version V1.0.1 +; * +; * @date 2021-03-23 +; * +; */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDT_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EINT Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FMC_IRQHandler ; Flash + DCD RCM_IRQHandler ; RCM + DCD EINT0_IRQHandler ; EINT Line 0 + DCD EINT1_IRQHandler ; EINT Line 1 + DCD EINT2_IRQHandler ; EINT Line 2 + DCD EINT3_IRQHandler ; EINT Line 3 + DCD EINT4_IRQHandler ; EINT Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USBD1_HP_CAN1_TX_IRQHandler ; USBD1 High Priority or CAN1 TX + DCD USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EINT9_5_IRQHandler ; EINT Line 9..5 + DCD TMR1_BRK_IRQHandler ; TMR1 Break + DCD TMR1_UP_IRQHandler ; TMR1 Update + DCD TMR1_TRG_COM_IRQHandler ; TMR1 Trigger and Commutation + DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare + DCD TMR2_IRQHandler ; TMR2 + DCD TMR3_IRQHandler ; TMR3 + DCD TMR4_IRQHandler ; TMR4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EINT15_10_IRQHandler ; EINT Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EINT Line + DCD USBDWakeUp_IRQHandler ; USBD Wakeup from suspend + DCD FPU_IRQHandler ; FPU + DCD QSPI_IRQHandler ; QSPI + DCD USBD2_HP_IRQHandler ; USBD2 High Priority + DCD USBD2_LP_IRQHandler ; USBD2 Low Priority +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCM_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USBD1_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USBD1_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EINT9_5_IRQHandler [WEAK] + EXPORT TMR1_BRK_IRQHandler [WEAK] + EXPORT TMR1_UP_IRQHandler [WEAK] + EXPORT TMR1_TRG_COM_IRQHandler [WEAK] + EXPORT TMR1_CC_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EINT15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBDWakeUp_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USBD2_HP_IRQHandler [WEAK] + EXPORT USBD2_LP_IRQHandler [WEAK] + +WWDT_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCM_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USBD1_HP_CAN1_TX_IRQHandler +USBD1_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EINT9_5_IRQHandler +TMR1_BRK_IRQHandler +TMR1_UP_IRQHandler +TMR1_TRG_COM_IRQHandler +TMR1_CC_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EINT15_10_IRQHandler +RTCAlarm_IRQHandler +USBDWakeUp_IRQHandler +FPU_IRQHandler +QSPI_IRQHandler +USBD2_HP_IRQHandler +USBD2_LP_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;*******************************END OF FILE************************************ diff --git a/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c new file mode 100644 index 0000000000..aad3575613 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c @@ -0,0 +1,557 @@ +/*! + * @file system_apm32f10x.c + * + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File + * + * @version V1.0.1 + * + * @date 2021-03-23 + * + */ + +#include "apm32f10x.h" + +//#define SYSTEM_CLOCK_HSE HSE_VALUE +//#define SYSTEM_CLOCK_24MHz (24000000) +//#define SYSTEM_CLOCK_36MHz (36000000) +//#define SYSTEM_CLOCK_48MHz (48000000) +//#define SYSTEM_CLOCK_56MHz (56000000) +#define SYSTEM_CLOCK_72MHz (72000000) +//#define SYSTEM_CLOCK_96MHz (96000000) + + +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 + +#ifdef SYSTEM_CLOCK_HSE +uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE; +#elif defined SYSTEM_CLOCK_24MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz; +#elif defined SYSTEM_CLOCK_36MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz; +#elif defined SYSTEM_CLOCK_48MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz; +#elif defined SYSTEM_CLOCK_56MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz; +#elif defined SYSTEM_CLOCK_72MHz +uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz; +#else +uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz; +#endif + + +static void SystemClockConfig(void); + +#ifdef SYSTEM_CLOCK_HSE +static void SystemClockHSE(void); +#elif defined SYSTEM_CLOCK_24MHz +static void SystemClock24M(void); +#elif defined SYSTEM_CLOCK_36MHz +static void SystemClock36M(void); +#elif defined SYSTEM_CLOCK_48MHz +static void SystemClock48M(void); +#elif defined SYSTEM_CLOCK_56MHz +static void SystemClock56M(void); +#elif defined SYSTEM_CLOCK_72MHz +static void SystemClock72M(void); +#elif defined SYSTEM_CLOCK_96MHz +static void SystemClock96M(void); +#endif + +/*! + * @brief Setup the microcontroller system + * + * @param None + * + * @retval None + * + * @note + */ +void SystemInit (void) +{ + /** Set HSIEN bit */ + RCM->CTRL_B.HSIEN = BIT_SET; + /** Reset SCLKSW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */ + RCM->CFG &= (uint32_t)0xF8FF0000; + /** Reset HSEEN, CSSEN and PLLEN bits */ + RCM->CTRL &= (uint32_t)0xFEF6FFFF; + /** Reset HSEBCFG bit */ + RCM->CTRL_B.HSEBCFG = BIT_RESET; + /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */ + RCM->CFG &= (uint32_t)0xFF80FFFF; + /** Disable all interrupts and clear pending bits */ + RCM->INT = 0x009F0000; + + SystemClockConfig(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; +#else + SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET; +#endif +} + +/*! + * @brief Update SystemCoreClock variable according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK) + * + * @param None + * + * @retval None + * + * @note + */ +void SystemCoreClockUpdate (void) +{ + uint32_t sysClock, pllMull, pllSource, Prescaler; + uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sysClock = RCM->CFG_B.SCLKSWSTS; + + switch(sysClock) + { + /** sys clock is HSI */ + case 0: + SystemCoreClock = HSI_VALUE; + break; + + /** sys clock is HSE */ + case 1: + SystemCoreClock = HSE_VALUE; + break; + + /** sys clock is PLL */ + case 2: + pllMull = RCM->CFG_B.PLLMULCFG + 2; + pllSource = RCM->CFG_B.PLLSRCSEL; + + /** PLL entry clock source is HSE */ + if(pllSource == BIT_SET) + { + SystemCoreClock = HSE_VALUE * pllMull; + + /** HSE clock divided by 2 */ + if(pllSource == RCM->CFG_B.PLLHSEPSC) + { + SystemCoreClock >>= 1; + } + } + /** PLL entry clock source is HSI/2 */ + else + { + SystemCoreClock = (HSI_VALUE >> 1) * pllMull; + } + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + Prescaler = AHBPrescTable[RCM->CFG_B.AHBPSC]; + SystemCoreClock >>= Prescaler; +} + +/*! + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClockConfig(void) +{ +#ifdef SYSTEM_CLOCK_HSE + SystemClockHSE(); +#elif defined SYSTEM_CLOCK_24MHz + SystemClock24M(); +#elif defined SYSTEM_CLOCK_36MHz + SystemClock36M(); +#elif defined SYSTEM_CLOCK_48MHz + SystemClock48M(); +#elif defined SYSTEM_CLOCK_56MHz + SystemClock56M(); +#elif defined SYSTEM_CLOCK_72MHz + SystemClock72M(); +#elif defined SYSTEM_CLOCK_96MHz + SystemClock96M(); +#endif +} + +#if defined SYSTEM_CLOCK_HSE +/*! + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClockHSE(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 0 wait state */ + FMC->CTRL1_B.WS = 0; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK */ + RCM->CFG_B.APB1PSC = 0; + + /* Select HSE as system clock source */ + RCM->CFG_B.SCLKSW = 1; + + /** Wait till HSE is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x01); + } +} + + +#elif defined SYSTEM_CLOCK_24MHz +/*! + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock24M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 0 wait state */ + FMC->CTRL1_B.WS = 0; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK */ + RCM->CFG_B.APB1PSC = 0; + + /** PLL: (HSE / 2) * 6 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLHSEPSC = 1; + RCM->CFG_B.PLLMULCFG = 4; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} + +#elif defined SYSTEM_CLOCK_36MHz +/*! + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock36M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK */ + RCM->CFG_B.APB1PSC = 0; + + /** PLL: (HSE / 2) * 9 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLHSEPSC = 1; + RCM->CFG_B.PLLMULCFG = 7; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS != 0x02); + } +} + +#elif defined SYSTEM_CLOCK_48MHz +/*! + * @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock48M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 1 wait state */ + FMC->CTRL1_B.WS = 1; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 6 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 4; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} + +#elif defined SYSTEM_CLOCK_56MHz +/*! + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock56M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 2 wait state */ + FMC->CTRL1_B.WS = 2; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 7 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 5; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} + +#elif defined SYSTEM_CLOCK_72MHz +/*! + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock72M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 2 wait state */ + FMC->CTRL1_B.WS = 2; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 9 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 7; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } + +} + +#elif defined SYSTEM_CLOCK_96MHz +/*! + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers + * + * @param None + * + * @retval None + * + * @note + */ +static void SystemClock96M(void) +{ + __IO uint32_t i; + + RCM->CTRL_B.HSEEN= BIT_SET; + + for(i = 0; i < HSE_STARTUP_TIMEOUT; i++) + { + if(RCM->CTRL_B.HSERDYFLG) + { + break; + } + } + + if(RCM->CTRL_B.HSERDYFLG) + { + /* Enable Prefetch Buffer */ + FMC->CTRL1_B.PBEN = BIT_SET; + /* Flash 3 wait state */ + FMC->CTRL1_B.WS = 3; + + /* HCLK = SYSCLK */ + RCM->CFG_B.AHBPSC= 0X00; + /* PCLK2 = HCLK */ + RCM->CFG_B.APB2PSC= 0; + /* PCLK1 = HCLK / 2 */ + RCM->CFG_B.APB1PSC = 4; + + /** PLL: HSE * 12 */ + RCM->CFG_B.PLLSRCSEL = 1; + RCM->CFG_B.PLLMULCFG = 10; + + /** Enable PLL */ + RCM->CTRL_B.PLLEN = 1; + /** Wait PLL Ready */ + while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET); + + /* Select PLL as system clock source */ + RCM->CFG_B.SCLKSW = 2; + /* Wait till PLL is used as system clock source */ + while(RCM->CFG_B.SCLKSWSTS!= 0x02); + } +} +#endif + diff --git a/bsp/apm32/libraries/APM32F10x_Library/SConscript b/bsp/apm32/libraries/APM32F10x_Library/SConscript new file mode 100644 index 0000000000..84a2e5e2f6 --- /dev/null +++ b/bsp/apm32/libraries/APM32F10x_Library/SConscript @@ -0,0 +1,25 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +Device/Geehy/APM32F10x/Source/system_apm32f10x.c +APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c +APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c +APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c +APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c +APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c +""") + +path = [cwd + '/Device/Geehy/APM32F10x/Include', + cwd + '/APM32F10x_StdPeriphDriver/inc', + cwd + '/CMSIS/Include'] + +CPPDEFINES = ['USE_STDPERIPH_DRIVER'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/apm32/libraries/Drivers/SConscript b/bsp/apm32/libraries/Drivers/SConscript new file mode 100644 index 0000000000..aa3dcad878 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/SConscript @@ -0,0 +1,27 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + if GetDepend(['RT_USING_SERIAL_V2']): + src += ['drv_usart_v2.c'] + else: + src += ['drv_usart.c'] + +src += ['drv_common.c'] + +path = [cwd] +path += [cwd + '/config'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/apm32/libraries/Drivers/drv_common.c b/bsp/apm32/libraries/Drivers/drv_common.c new file mode 100644 index 0000000000..dd029321f8 --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_common.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include "drv_common.h" +#include "board.h" + +#ifdef RT_USING_SERIAL +#ifdef RT_USING_SERIAL_V2 +#include "drv_usart_v2.h" +#else +#include "drv_usart.h" +#endif +#endif + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + SysTick_Config(RCM_ReadHCLKFreq()/RT_TICK_PER_SECOND); + + /* AHB clock selected as SysTick clock source. */ + SysTick->CTRL |= 0x00000004U; + + NVIC_SetPriority(SysTick_IRQn, 0xFF); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function will initial STM32 board. + */ +RT_WEAK void rt_hw_board_init() +{ + /* Systick initialization */ + rt_hw_systick_init(); + + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* Pin driver initialization is open by default */ +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + diff --git a/bsp/apm32/libraries/Drivers/drv_common.h b/bsp/apm32/libraries/Drivers/drv_common.h new file mode 100644 index 0000000000..5218b1189b --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_common.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include +#ifdef RT_USING_DEVICE +#include +#endif + + + +#ifdef __cplusplus +extern "C" { +#endif + +void _Error_Handler(char *s, int num); + +#ifndef Error_Handler +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#endif + +#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.c b/bsp/apm32/libraries/Drivers/drv_gpio.c new file mode 100644 index 0000000000..7f8413d7fb --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_gpio.c @@ -0,0 +1,573 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_APMPORT(pin) ((GPIO_T *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) + +#define PIN_APMPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + +#if defined(GPIOZ) + #define __APM32_PORT_MAX 12u +#elif defined(GPIOK) + #define __APM32_PORT_MAX 11u +#elif defined(GPIOJ) + #define __APM32_PORT_MAX 10u +#elif defined(GPIOI) + #define __APM32_PORT_MAX 9u +#elif defined(GPIOH) + #define __APM32_PORT_MAX 8u +#elif defined(GPIOG) + #define __APM32_PORT_MAX 7u +#elif defined(GPIOF) + #define __APM32_PORT_MAX 6u +#elif defined(GPIOE) + #define __APM32_PORT_MAX 5u +#elif defined(GPIOD) + #define __APM32_PORT_MAX 4u +#elif defined(GPIOC) + #define __APM32_PORT_MAX 3u +#elif defined(GPIOB) + #define __APM32_PORT_MAX 2u +#elif defined(GPIOA) + #define __APM32_PORT_MAX 1u +#else + #define __APM32_PORT_MAX 0u + #error Unsupported APM32 GPIO peripheral. +#endif + +#define PIN_APMPORT_MAX __APM32_PORT_MAX + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EINT0_IRQn}, + {GPIO_PIN_1, EINT1_IRQn}, + {GPIO_PIN_2, EINT2_IRQn}, + {GPIO_PIN_3, EINT3_IRQn}, + {GPIO_PIN_4, EINT4_IRQn}, + {GPIO_PIN_5, EINT9_5_IRQn}, + {GPIO_PIN_6, EINT9_5_IRQn}, + {GPIO_PIN_7, EINT9_5_IRQn}, + {GPIO_PIN_8, EINT9_5_IRQn}, + {GPIO_PIN_9, EINT9_5_IRQn}, + {GPIO_PIN_10, EINT15_10_IRQn}, + {GPIO_PIN_11, EINT15_10_IRQn}, + {GPIO_PIN_12, EINT15_10_IRQn}, + {GPIO_PIN_13, EINT15_10_IRQn}, + {GPIO_PIN_14, EINT15_10_IRQn}, + {GPIO_PIN_15, EINT15_10_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static rt_base_t _pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 4) || (name_len >= 6)) + { + return -RT_EINVAL; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + return -RT_EINVAL; + } + + if ((name[1] >= 'A') && (name[1] <= 'Z')) + { + hw_port_num = (int)(name[1] - 'A'); + } + else + { + return -RT_EINVAL; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; +} + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + GPIO_T *gpio_port; + uint16_t gpio_pin; + + if (PIN_PORT(pin) < PIN_APMPORT_MAX) + { + gpio_port = PIN_APMPORT(pin); + gpio_pin = PIN_APMPIN(pin); + + GPIO_WriteBitValue(gpio_port, gpio_pin, (uint8_t)value); + } +} + +static int _pin_read(rt_device_t dev, rt_base_t pin) +{ + GPIO_T *gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (PIN_PORT(pin) < PIN_APMPORT_MAX) + { + gpio_port = PIN_APMPORT(pin); + gpio_pin = PIN_APMPIN(pin); + value = GPIO_ReadInputBit(gpio_port, gpio_pin); + } + + return value; +} + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + GPIO_Config_T gpioConfig; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return; + } + + /* Configure gpioConfigure */ + gpioConfig.pin = PIN_APMPIN(pin); + gpioConfig.mode = GPIO_MODE_OUT_PP; + gpioConfig.speed = GPIO_SPEED_50MHz; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpioConfig.mode = GPIO_MODE_OUT_PP; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpioConfig.mode = GPIO_MODE_IN_PU; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpioConfig.mode = GPIO_MODE_IN_PU; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpioConfig.mode = GPIO_MODE_IN_PD; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpioConfig.mode = GPIO_MODE_OUT_OD; + } + + GPIO_Config(PIN_APMPORT(pin), &gpioConfig); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_APMPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_APMPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_Config_T gpioConfig; + + if (PIN_PORT(pin) >= PIN_APMPORT_MAX) + { + return -RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(PIN_APMPIN(pin)); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + /* Configure gpioConfigure */ + gpioConfig.pin = PIN_APMPIN(pin); + gpioConfig.speed = GPIO_SPEED_50MHz; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + gpioConfig.mode = GPIO_MODE_IN_PD; + break; + case PIN_IRQ_MODE_FALLING: + gpioConfig.mode = GPIO_MODE_IN_PU; + break; + case PIN_IRQ_MODE_RISING_FALLING: + gpioConfig.mode = GPIO_MODE_IN_FLOATING; + break; + } + GPIO_Config(PIN_APMPORT(pin), &gpioConfig); + + NVIC_EnableIRQRequest(irqmap->irqno, 5, 0); + pin_irq_enable_mask |= irqmap->pinbit; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(PIN_APMPIN(pin)); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + pin_irq_enable_mask &= ~irqmap->pinbit; + + if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQRequest(irqmap->irqno); + } + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _apm32_pin_ops = +{ + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_dettach_irq, + _pin_irq_enable, + _pin_get, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + + +void GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + pin_irq_hdr(bit2bitno(GPIO_Pin)); +} + + +void EINT0_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (EINT_ReadIntFlag(EINT_LINE_0)) + { + EINT_ClearIntFlag(EINT_LINE_0); + GPIO_EXTI_IRQHandler(GPIO_PIN_0); + } + + rt_interrupt_leave(); +} + +void EINT1_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_1)) + { + EINT_ClearIntFlag(EINT_LINE_1); + GPIO_EXTI_IRQHandler(GPIO_PIN_1); + } + rt_interrupt_leave(); +} + +void EINT2_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_2)) + { + EINT_ClearIntFlag(EINT_LINE_2); + GPIO_EXTI_IRQHandler(GPIO_PIN_2); + } + rt_interrupt_leave(); +} + +void EINT3_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_3)) + { + EINT_ClearIntFlag(EINT_LINE_3); + GPIO_EXTI_IRQHandler(GPIO_PIN_3); + } + rt_interrupt_leave(); +} + +void EINT4_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_4)) + { + EINT_ClearIntFlag(EINT_LINE_4); + GPIO_EXTI_IRQHandler(GPIO_PIN_4); + } + rt_interrupt_leave(); +} + +void EINT9_5_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_5)) + { + EINT_ClearIntFlag(EINT_LINE_5); + GPIO_EXTI_IRQHandler(GPIO_PIN_5); + } + if (EINT_ReadIntFlag(EINT_LINE_6)) + { + EINT_ClearIntFlag(EINT_LINE_6); + GPIO_EXTI_IRQHandler(GPIO_PIN_6); + } + if (EINT_ReadIntFlag(EINT_LINE_7)) + { + EINT_ClearIntFlag(EINT_LINE_7); + GPIO_EXTI_IRQHandler(GPIO_PIN_7); + } + if (EINT_ReadIntFlag(EINT_LINE_8)) + { + EINT_ClearIntFlag(EINT_LINE_8); + GPIO_EXTI_IRQHandler(GPIO_PIN_8); + } + if (EINT_ReadIntFlag(EINT_LINE_9)) + { + EINT_ClearIntFlag(EINT_LINE_9); + GPIO_EXTI_IRQHandler(GPIO_PIN_9); + } + rt_interrupt_leave(); +} + +void EINT15_10_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EINT_ReadIntFlag(EINT_LINE_10)) + { + EINT_ClearIntFlag(EINT_LINE_10); + GPIO_EXTI_IRQHandler(GPIO_PIN_10); + } + if (EINT_ReadIntFlag(EINT_LINE_11)) + { + EINT_ClearIntFlag(EINT_LINE_11); + GPIO_EXTI_IRQHandler(GPIO_PIN_11); + } + if (EINT_ReadIntFlag(EINT_LINE_12)) + { + EINT_ClearIntFlag(EINT_LINE_12); + GPIO_EXTI_IRQHandler(GPIO_PIN_12); + } + if (EINT_ReadIntFlag(EINT_LINE_13)) + { + EINT_ClearIntFlag(EINT_LINE_13); + GPIO_EXTI_IRQHandler(GPIO_PIN_13); + } + if (EINT_ReadIntFlag(EINT_LINE_14)) + { + EINT_ClearIntFlag(EINT_LINE_14); + GPIO_EXTI_IRQHandler(GPIO_PIN_14); + } + if (EINT_ReadIntFlag(EINT_LINE_15)) + { + EINT_ClearIntFlag(EINT_LINE_15); + GPIO_EXTI_IRQHandler(GPIO_PIN_15); + } + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ +#ifdef GPIOA + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA); +#endif +#ifdef GPIOB + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB); +#endif +#ifdef GPIOC + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOC); +#endif +#ifdef GPIOD + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOD); +#endif +#ifdef GPIOE + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOE); +#endif +#ifdef GPIOF + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOF); +#endif +#ifdef GPIOG + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOG); +#endif + + RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO); + + return rt_device_pin_register("pin", &_apm32_pin_ops, RT_NULL); +} + +#endif /* RT_USING_PIN */ diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.h b/bsp/apm32/libraries/Drivers/drv_gpio.h new file mode 100644 index 0000000000..1da4fdb97b --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_gpio.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __APM32_PORT(port) GPIO##port##_BASE + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__APM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +int rt_hw_pin_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/apm32/libraries/Drivers/drv_usart.c b/bsp/apm32/libraries/Drivers/drv_usart.c new file mode 100644 index 0000000000..c3141be55c --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_usart.c @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#include "board.h" +#include "drv_usart.h" + + +#ifdef RT_USING_SERIAL +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +/* stm32 config class */ +struct apm32_usart +{ + const char *name; + USART_T *usartx; + IRQn_Type irq_type; + struct rt_serial_device serial; +}; + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +}; + +static struct apm32_usart usart_config[] = +{ +#ifdef BSP_USING_UART1 + { + "uart1", + USART1, + USART1_IRQn, + }, +#endif +#ifdef BSP_USING_UART2 + { + "uart2", + USART2, + USART2_IRQn, + }, +#endif +}; + +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + USART_Config_T USART_ConfigStruct; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + struct apm32_usart *usart_instance = (struct apm32_usart *) serial->parent.user_data; + + apm32_usart_init(); + + USART_ConfigStruct.baudRate = cfg->baud_rate;; + USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_NONE; + USART_ConfigStruct.mode = USART_MODE_TX_RX; + USART_ConfigStruct.parity = USART_PARITY_NONE; + + switch (cfg->data_bits) + { + case DATA_BITS_8: + if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) + USART_ConfigStruct.wordLength = USART_WORD_LEN_9B; + else + USART_ConfigStruct.wordLength = USART_WORD_LEN_8B; + break; + case DATA_BITS_9: + USART_ConfigStruct.wordLength = USART_WORD_LEN_9B; + break; + default: + USART_ConfigStruct.wordLength = USART_WORD_LEN_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_ConfigStruct.stopBits = USART_STOP_BIT_1; + break; + case STOP_BITS_2: + USART_ConfigStruct.stopBits = USART_STOP_BIT_2; + break; + default: + USART_ConfigStruct.stopBits = USART_STOP_BIT_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + USART_ConfigStruct.parity = USART_PARITY_NONE; + break; + case PARITY_ODD: + USART_ConfigStruct.parity = USART_PARITY_ODD; + break; + case PARITY_EVEN: + USART_ConfigStruct.parity = USART_PARITY_EVEN; + break; + default: + USART_ConfigStruct.parity = USART_PARITY_NONE; + break; + } + + USART_Config(usart_instance->usartx, &USART_ConfigStruct); + USART_Enable(usart_instance->usartx); + + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct apm32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + + usart = (struct apm32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + + /* disable rx irq */ + NVIC_DisableIRQRequest(usart->irq_type); + + /* disable interrupt */ + USART_DisableInterrupt(usart->usartx, USART_INT_RXBNE); + + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQRequest(usart->irq_type, 1, 0); + + /* enable interrupt */ + USART_EnableInterrupt(usart->usartx, USART_INT_RXBNE); + break; + + } + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char c) +{ + struct apm32_usart *usart; + RT_ASSERT(serial != RT_NULL); + + usart = (struct apm32_usart *) serial->parent.user_data; + + RT_ASSERT(usart != RT_NULL); + + USART_TxData(usart->usartx, (uint8_t) c); + + while (USART_ReadStatusFlag(usart->usartx, USART_FLAG_TXC) == RESET); + + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct apm32_usart *usart; + RT_ASSERT(serial != RT_NULL); + usart = (struct apm32_usart *) serial->parent.user_data; + + RT_ASSERT(usart != RT_NULL); + + ch = -1; + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) + { + ch = USART_RxData(usart->usartx); + } + return ch; +} + +/** + * Uart common interrupt process. This need add to usart ISR. + * + * @param serial serial device + */ +static void usart_isr(struct rt_serial_device *serial) +{ + struct apm32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); + usart = (struct apm32_usart *) serial->parent.user_data; + + RT_ASSERT(usart != RT_NULL); + + /* UART in mode Receiver -------------------------------------------------*/ + if ((USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) && + (USART_ReadIntFlag(usart->usartx, USART_INT_RXBNE) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + USART_ClearStatusFlag(usart->usartx, USART_FLAG_RXBNE); + USART_ClearIntFlag(usart->usartx, USART_INT_RXBNE); + } + + else + { + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_CTS) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_CTS); + } + + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_LBD) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_LBD); + } + + if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_TXBE) != RESET) + { + USART_ClearStatusFlag(usart->usartx, USART_FLAG_TXBE); + } + } +} + + + +#if defined(BSP_USING_UART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + usart_isr(&(usart_config[UART2_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART2 */ + +static const struct rt_uart_ops apm32_usart_ops = +{ + .configure = _uart_configure, + .control = _uart_control, + .putc = _uart_putc, + .getc = _uart_getc, + .dma_transmit = RT_NULL +}; + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num; + int index; + + obj_num = sizeof(usart_config) / sizeof(struct apm32_usart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (index = 0; index < obj_num; index++) + { + usart_config[index].serial.ops = &apm32_usart_ops; + usart_config[index].serial.config = config; + + /* register USART device */ + result = rt_hw_serial_register(&usart_config[index].serial, + usart_config[index].name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX, &usart_config[index]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/apm32/libraries/Drivers/drv_usart.h b/bsp/apm32/libraries/Drivers/drv_usart.h new file mode 100644 index 0000000000..a9040cc14c --- /dev/null +++ b/bsp/apm32/libraries/Drivers/drv_usart.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Abbcc first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include "rtdevice.h" +#include +#include +#include + +int rt_hw_usart_init(void); + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/apm32/libraries/Kconfig b/bsp/apm32/libraries/Kconfig new file mode 100644 index 0000000000..bb335315fa --- /dev/null +++ b/bsp/apm32/libraries/Kconfig @@ -0,0 +1,8 @@ +config SOC_FAMILY_APM32 + bool + +config SOC_SERIES_APM32F1 + bool + select ARCH_ARM_CORTEX_M3 + select SOC_FAMILY_APM32 + diff --git a/bsp/at32/Libraries/rt_drivers/drv_rtc.c b/bsp/at32/Libraries/rt_drivers/drv_rtc.c index d943123e88..0a6808802d 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_rtc.c +++ b/bsp/at32/Libraries/rt_drivers/drv_rtc.c @@ -4,12 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2020-05-19 shelton first version + * Date Author Notes + * 2020-05-19 shelton first version + * 2021-08-125 Dozingfiretruck implement RTC framework V2.0 */ #include "board.h" #include +#include #include #ifdef BSP_USING_RTC @@ -24,8 +26,6 @@ #define BKUP_REG_DATA 0xA5A5 -static struct rt_device rtc; - static time_t get_rtc_timestamp(void) { #ifdef SOC_SERIES_AT32F415 @@ -93,25 +93,7 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) return RT_EOK; } -static void rt_rtc_init(void) -{ -#if defined (SOC_SERIES_AT32F415) - RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, ENABLE); -#else - RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR | RCC_APB1PERIPH_BKP, ENABLE); -#endif - -#ifdef BSP_RTC_USING_LSI - RCC_LSICmd(ENABLE); - while(RCC_GetFlagStatus(RCC_FLAG_LSISTBL) == RESET); -#else - PWR_BackupAccessCtrl(ENABLE); - RCC_LSEConfig(RCC_LSE_ENABLE); - while(RCC_GetFlagStatus(RCC_FLAG_LSESTBL) == RESET); -#endif /* BSP_RTC_USING_LSI */ -} - -static rt_err_t rt_rtc_config(struct rt_device *dev) +static rt_err_t rt_rtc_config(void) { #if defined (SOC_SERIES_AT32F415) ERTC_InitType ERTC_InitStructure; @@ -166,73 +148,70 @@ static rt_err_t rt_rtc_config(struct rt_device *dev) return RT_EOK; } -static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) +static rt_err_t _rtc_init(void) +{ +#if defined (SOC_SERIES_AT32F415) + RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, ENABLE); +#else + RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR | RCC_APB1PERIPH_BKP, ENABLE); +#endif + +#ifdef BSP_RTC_USING_LSI + RCC_LSICmd(ENABLE); + while(RCC_GetFlagStatus(RCC_FLAG_LSISTBL) == RESET); +#else + PWR_BackupAccessCtrl(ENABLE); + RCC_LSEConfig(RCC_LSE_ENABLE); + while(RCC_GetFlagStatus(RCC_FLAG_LSESTBL) == RESET); +#endif /* BSP_RTC_USING_LSI */ + if (rt_rtc_config() != RT_EOK) + { + LOG_E("rtc init failed."); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t _rtc_get_secs(void *args) +{ + *(rt_uint32_t *)args = get_rtc_timestamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + + return RT_EOK; +} + +static rt_err_t _rtc_set_secs(void *args) { rt_err_t result = RT_EOK; - RT_ASSERT(dev != RT_NULL); - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - *(rt_uint32_t *)args = get_rtc_timestamp(); - LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); - break; - case RT_DEVICE_CTRL_RTC_SET_TIME: - if (set_rtc_time_stamp(*(rt_uint32_t *)args)) - { - result = -RT_ERROR; - } - LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); - break; + if (set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); return result; } -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops rtc_ops = +static const struct rt_rtc_ops _rtc_ops = { + _rtc_init, + _rtc_get_secs, + _rtc_set_secs, RT_NULL, RT_NULL, RT_NULL, RT_NULL, - RT_NULL, - rt_rtc_control }; -#endif -static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag) -{ - RT_ASSERT(device != RT_NULL); - - rt_rtc_init(); - if (rt_rtc_config(device) != RT_EOK) - { - return -RT_ERROR; - } -#ifdef RT_USING_DEVICE_OPS - device->ops = &rtc_ops; -#else - device->init = RT_NULL; - device->open = RT_NULL; - device->close = RT_NULL; - device->read = RT_NULL; - device->write = RT_NULL; - device->control = rt_rtc_control; -#endif - device->type = RT_Device_Class_RTC; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->user_data = RT_NULL; - - /* register a character device */ - return rt_device_register(device, name, flag); -} +static rt_rtc_dev_t at32_rtc_dev; int rt_hw_rtc_init(void) { rt_err_t result; - result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + at32_rtc_dev.ops = &_rtc_ops; + result = rt_hw_rtc_register(&at32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR,RT_NULL); if (result != RT_EOK) { LOG_E("rtc register err code: %d", result); diff --git a/bsp/at32/at32f403a-start/template.uvopt b/bsp/at32/at32f403a-start/template.uvopt index 33eee51f0d..98f84ef5ce 100644 --- a/bsp/at32/at32f403a-start/template.uvopt +++ b/bsp/at32/at32f403a-start/template.uvopt @@ -10,9 +10,10 @@ *.s*; *.src; *.a* *.obj *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp + 0 @@ -31,6 +32,7 @@ 1 1 0 + 0 1 @@ -96,10 +98,12 @@ 0 1 1 - 0 0 0 - 6 + 1 + 0 + 0 + 3 @@ -110,9 +114,14 @@ - Segger\JL2CM3.dll + BIN\CMSIS_AGDI.dll + + 0 + CMSIS_AGDI + -X"AT-Link-EZ-CMSIS-DAP" -U9BE164220040B56D0117B002 -O78 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0AT32F403A_1024 -FS08000000 -FL0100000 + 0 JL2CM3 @@ -151,11 +160,22 @@ 0 0 0 - 1 + 0 0 + 0 + 0 + 0 + + + + + + + + diff --git a/bsp/at32/at32f403a-start/template.uvoptx b/bsp/at32/at32f403a-start/template.uvoptx index 769c7372f0..88ac49dacd 100644 --- a/bsp/at32/at32f403a-start/template.uvoptx +++ b/bsp/at32/at32f403a-start/template.uvoptx @@ -10,7 +10,7 @@ *.s*; *.src; *.a* *.obj; *.o *.lib - *.txt; *.h; *.inc + *.txt; *.h; *.inc; *.md *.plm *.cpp 0 @@ -101,7 +101,9 @@ 0 0 1 - 6 + 0 + 0 + 3 @@ -112,7 +114,7 @@ - Segger\JL2CM3.dll + BIN\CMSIS_AGDI.dll @@ -170,6 +172,10 @@ + + + + diff --git a/bsp/at32/at32f403a-start/template.uvproj b/bsp/at32/at32f403a-start/template.uvproj index 7f6d829aff..eeb9d55126 100644 --- a/bsp/at32/at32f403a-start/template.uvproj +++ b/bsp/at32/at32f403a-start/template.uvproj @@ -10,6 +10,7 @@ rt-thread 0x4 ARM-ADS + 0 AT32F403AVGT7 @@ -72,6 +73,8 @@ 0 0 + 0 + 0 1 @@ -80,6 +83,8 @@ 0 0 + 0 + 0 0 @@ -141,10 +146,9 @@ 1 0 1 - 0 0 - 6 + 3 @@ -158,7 +162,7 @@ - Segger\JL2CM3.dll + BIN\CMSIS_AGDI.dll @@ -168,11 +172,11 @@ 0 1 1 - 4096 + 4099 1 - BIN\UL2CM3.DLL - + BIN\CMSIS_AGDI.dll + "" () @@ -218,12 +222,15 @@ 0 0 2 + 0 + 0 0 0 8 0 0 0 + 0 3 3 0 @@ -357,7 +364,15 @@ 0 0 1 + 0 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 @@ -375,6 +390,7 @@ 0 0 0 + 1 diff --git a/bsp/at32/at32f403a-start/template.uvprojx b/bsp/at32/at32f403a-start/template.uvprojx index 9f3a44663d..3809082825 100644 --- a/bsp/at32/at32f403a-start/template.uvprojx +++ b/bsp/at32/at32f403a-start/template.uvprojx @@ -11,11 +11,12 @@ 0x4 ARM-ADS 5060750::V5.06 update 6 (build 750)::ARMCC + 0 AT32F403AVGT7 ArteryTek - Keil.AT32F4xx_DFP.1.3.1 + Keil.AT32F4xx_DFP.1.3.2 IRAM(0x20000000,0x38000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -132,11 +133,11 @@ 0 1 1 - 4096 + 4099 1 - BIN\UL2CM3.DLL - + BIN\CMSIS_AGDI.dll + "" () @@ -182,6 +183,8 @@ 0 0 2 + 0 + 0 0 0 8 @@ -322,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -347,7 +351,7 @@ 0 0 0 - 0 + 4 diff --git a/bsp/at32/tools/sdk_dist.py b/bsp/at32/tools/sdk_dist.py index 4c36c9b6e3..e3db1e519a 100644 --- a/bsp/at32/tools/sdk_dist.py +++ b/bsp/at32/tools/sdk_dist.py @@ -4,6 +4,24 @@ import shutil cwd_path = os.getcwd() sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) +def bsp_update_kconfig_library(dist_dir): + # change RTT_ROOT in Kconfig + if not os.path.isfile(os.path.join(dist_dir, 'Kconfig')): + return + + with open(os.path.join(dist_dir, 'Kconfig'), 'r') as f: + data = f.readlines() + with open(os.path.join(dist_dir, 'Kconfig'), 'w') as f: + found = 0 + for line in data: + if line.find('RTT_ROOT') != -1: + found = 1 + if line.find('../Libraries') != -1 and found: + position = line.find('../Libraries') + line = line[0:position] + 'Libraries/Kconfig"\n' + found = 0 + f.write(line) + # BSP dist function def dist_do_building(BSP_ROOT, dist_dir): from mkdist import bsp_copy_files @@ -18,3 +36,4 @@ def dist_do_building(BSP_ROOT, dist_dir): print("=> copy bsp drivers") bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers')) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + bsp_update_kconfig_library(dist_dir) \ No newline at end of file diff --git a/bsp/hc32l136/.config b/bsp/hc32l136/.config new file mode 100644 index 0000000000..732d1347cc --- /dev/null +++ b/bsp/hc32l136/.config @@ -0,0 +1,574 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=512 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=512 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set + +# +# Hardware Drivers Config +# +CONFIG_MCU_HC32L136=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_I2C1 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/hc32l136/.ignore_format.yml b/bsp/hc32l136/.ignore_format.yml new file mode 100644 index 0000000000..53148ea970 --- /dev/null +++ b/bsp/hc32l136/.ignore_format.yml @@ -0,0 +1,9 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: + + +dir_path: +- libraries \ No newline at end of file diff --git a/bsp/hc32l136/Kconfig b/bsp/hc32l136/Kconfig new file mode 100644 index 0000000000..f4ed99b3fa --- /dev/null +++ b/bsp/hc32l136/Kconfig @@ -0,0 +1,23 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/base_types.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/base_types.h new file mode 100644 index 0000000000..d3feeaff73 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/base_types.h @@ -0,0 +1,155 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file base_types.h + ** + ** base type common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include +#include +#include +#include + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0u) +#endif + +#if defined (__ICCARM__) +#define __WEAKDEF __WEAK __ATTRIBUTES +#elif defined (__CC_ARM) +#define __WEAKDEF __weak +#else +#error "unsupported compiler!!" +#endif + +/** Returns the minimum value out of two values */ +#define MINIMUM( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAXIMUM( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define ARRAY_SZ( X ) (sizeof(X) / sizeof((X)[0])) + +#ifdef __DEBUG_ASSERT + #define ASSERT(x) do{ assert((x)> 0u) ; }while(0); +#else + #define ASSERT(x) {} +#endif +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCII character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t u8Param); + +/** generic error codes */ +typedef enum en_result +{ + Ok = 0u, ///< No error + Error = 1u, ///< Non-specific error code + ErrorAddressAlignment = 2u, ///< Address alignment does not match + ErrorAccessRights = 3u, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4u, ///< Provided parameter is not valid + ErrorOperationInProgress = 5u, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6u, ///< Operation not allowed in current mode + ErrorUninitialized = 7u, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8u, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9u, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10u, ///< A requested final state is not reached + OperationInProgress = 11u ///< Indicator for operation in progress +} en_result_t; + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/board_stkhc32l13x.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/board_stkhc32l13x.h new file mode 100644 index 0000000000..e5c194c7c2 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/board_stkhc32l13x.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file stkhc32l13x.h + ** + ** stk board common define. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ +#ifndef __BOARD_STKHC32L13X_H__ +#define __BOARD_STKHC32L13X_H__ + +///< STK GPIO DEFINE +///< USER KEY +#define STK_USER_PORT GpioPortD +#define STK_USER_PIN GpioPin4 + +///< LED +#define STK_LED_PORT GpioPortD +#define STK_LED_PIN GpioPin5 + +///< XTH +#define SYSTEM_XTH (32*1000*1000u) ///< 32MHz + +#define STK_XTHI_PORT GpioPortD +#define STK_XTHI_PIN GpioPin0 +#define STK_XTHO_PORT GpioPortD +#define STK_XTHO_PIN GpioPin1 + +///< XTL +#define SYSTEM_XTL (32768u) ///< 32768Hz +#define STK_XTLI_PORT GpioPortC +#define STK_XTLI_PIN GpioPin14 +#define STK_XTLO_PORT GpioPortC +#define STK_XTLO_PIN GpioPin15 + +///< LCD +#define STK_LCD_COM0_PORT GpioPortA +#define STK_LCD_COM0_PIN GpioPin9 +#define STK_LCD_COM1_PORT GpioPortA +#define STK_LCD_COM1_PIN GpioPin10 +#define STK_LCD_COM2_PORT GpioPortA +#define STK_LCD_COM2_PIN GpioPin11 +#define STK_LCD_COM3_PORT GpioPortA +#define STK_LCD_COM3_PIN GpioPin12 +#define STK_LCD_SEG0_PORT GpioPortA +#define STK_LCD_SEG0_PIN GpioPin8 +#define STK_LCD_SEG1_PORT GpioPortC +#define STK_LCD_SEG1_PIN GpioPin9 +#define STK_LCD_SEG2_PORT GpioPortC +#define STK_LCD_SEG2_PIN GpioPin8 +#define STK_LCD_SEG3_PORT GpioPortC +#define STK_LCD_SEG3_PIN GpioPin7 +#define STK_LCD_SEG4_PORT GpioPortC +#define STK_LCD_SEG4_PIN GpioPin6 +#define STK_LCD_SEG5_PORT GpioPortB +#define STK_LCD_SEG5_PIN GpioPin15 +#define STK_LCD_SEG6_PORT GpioPortB +#define STK_LCD_SEG6_PIN GpioPin14 +#define STK_LCD_SEG7_PORT GpioPortB +#define STK_LCD_SEG7_PIN GpioPin13 + +///< I2C EEPROM +#define EVB_I2C0_EEPROM_SCL_PORT GpioPortB +#define EVB_I2C0_EEPROM_SCL_PIN GpioPin6 +#define EVB_I2C0_EEPROM_SDA_PORT GpioPortB +#define EVB_I2C0_EEPROM_SDA_PIN GpioPin7 + +///< SPI0 +#define EVB_SPI0_FLASH_CS_PORT GpioPortE +#define EVB_SPI0_FLASH_CS_PIN GpioPin12 +#define EVB_SPI0_FLASH_SCK_PORT GpioPortE +#define EVB_SPI0_FLASH_SCK_PIN GpioPin13 +#define EVB_SPI0_FLASH_MISO_PORT GpioPortE +#define EVB_SPI0_FLASH_MISO_PIN GpioPin14 +#define EVB_SPI0_FLASH_MOSI_PORT GpioPortE +#define EVB_SPI0_FLASH_MOSI_PIN GpioPin15 + +#endif diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/ddl_device.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/ddl_device.h new file mode 100644 index 0000000000..6ee91e5f2e --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/ddl_device.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl_device.h + ** + ** Device define + ** @link SampleGroup Some description @endlink + ** + ** - 2018-04-15 + ** + *****************************************************************************/ + +#ifndef __DDL_DEVICE_H__ +#define __DDL_DEVICE_H__ + +/** + ******************************************************************************* + ** \brief Global device series definition + ** + ** \note + ******************************************************************************/ +#define DDL_MCU_SERIES DDL_DEVICE_SERIES_HC32L13X + + +/** + ******************************************************************************* + ** \brief Global package definition + ** + ** \note This definition is used for device package settings + ******************************************************************************/ +#define DDL_MCU_PACKAGE DDL_DEVICE_PACKAGE_HC_K + +#endif /* __DDL_DEVICE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/hc32l136.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/hc32l136.h new file mode 100644 index 0000000000..a162e9e5a2 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/hc32l136.h @@ -0,0 +1,9620 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \\file HC32L136.h +** +** Auto generate. +** Headerfile for HC32L136 series MCU +** +** History: +** +** - 2018-09-14 0.1 Lux First version. +** +******************************************************************************/ + +#ifndef __HC32L136_H__ +#define __HC32L136_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** +* Configuration of the Cortex-M0P Processor and Core Peripherals +******************************************************************************/ +#define __MPU_PRESENT 0 /* No MPU */ +#define __NVIC_PRIO_BITS 2 /* M0P uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +/****************************************************************************** +* Interrupt Number Definition +******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + PORTA_IRQn = 0 , + PORTB_IRQn = 1 , + PORTC_IRQn = 2 , + PORTD_IRQn = 3 , + DMAC_IRQn = 4 , + TIM3_IRQn = 5 , + UART0_IRQn = 6 , + UART1_IRQn = 7 , + LPUART0_IRQn = 8 , + LPUART1_IRQn = 9 , + SPI0_IRQn = 10, + SPI1_IRQn = 11, + I2C0_IRQn = 12, + I2C1_IRQn = 13, + TIM0_IRQn = 14, + TIM1_IRQn = 15, + TIM2_IRQn = 16, + LPTIM_IRQn = 17, + TIM4_IRQn = 18, + TIM5_IRQn = 19, + TIM6_IRQn = 20, + PCA_IRQn = 21, + WDT_IRQn = 22, + RTC_IRQn = 23, + ADC_IRQn = 24, + PCNT_IRQn = 25, + VC0_IRQn = 26, + VC1_IRQn = 27, + LVD_IRQn = 28, + LCD_IRQn = 29, + FLASH_RAM_IRQn = 30, + CLK_TRIM_IRQn = 31, + + +} IRQn_Type; + + +#include +#include + +#define SUCCESS (0) +#define ERROR (-1) + +#ifndef NULL +#define NULL (0) +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +typedef struct +{ + __IO uint32_t EN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CLKDIV : 2; + __IO uint32_t SGLMUX : 5; + __IO uint32_t REF : 2; + __IO uint32_t BUF : 1; + __IO uint32_t SAM : 2; + __IO uint32_t INREFEN : 1; + __IO uint32_t IE : 1; +} stc_adc_cr0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t ALIGN : 1; + __IO uint32_t THCH : 5; + __IO uint32_t DMASQR : 1; + __IO uint32_t DMAJQR : 1; + __IO uint32_t MODE : 1; + __IO uint32_t RACCEN : 1; + __IO uint32_t LTCMP : 1; + __IO uint32_t HTCMP : 1; + __IO uint32_t REGCMP : 1; + __IO uint32_t RACCCLR : 1; +} stc_adc_cr1_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CH4MUX : 5; + __IO uint32_t CH5MUX : 5; +} stc_adc_sqr0_field_t; + +typedef struct +{ + __IO uint32_t CH6MUX : 5; + __IO uint32_t CH7MUX : 5; + __IO uint32_t CH8MUX : 5; + __IO uint32_t CH9MUX : 5; + __IO uint32_t CH10MUX : 5; + __IO uint32_t CH11MUX : 5; +} stc_adc_sqr1_field_t; + +typedef struct +{ + __IO uint32_t CH12MUX : 5; + __IO uint32_t CH13MUX : 5; + __IO uint32_t CH14MUX : 5; + __IO uint32_t CH15MUX : 5; + __IO uint32_t CNT : 4; +} stc_adc_sqr2_field_t; + +typedef struct +{ + __IO uint32_t CH0MUX : 5; + __IO uint32_t CH1MUX : 5; + __IO uint32_t CH2MUX : 5; + __IO uint32_t CH3MUX : 5; + __IO uint32_t CNT : 2; +} stc_adc_jqr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult4_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult5_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult6_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult7_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult8_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult9_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult10_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult11_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult12_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqr_result13_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult14_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_sqrresult15_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult0_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult1_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult2_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_jqrresult3_field_t; + +typedef struct +{ + __IO uint32_t RESULT :12; +} stc_adc_result_field_t; + +typedef struct +{ + __IO uint32_t RESULTACC :20; +} stc_adc_resultacc_field_t; + +typedef struct +{ + __IO uint32_t HT :12; +} stc_adc_ht_field_t; + +typedef struct +{ + __IO uint32_t LT :12; +} stc_adc_lt_field_t; + +typedef struct +{ + __IO uint32_t SGLIF : 1; + __IO uint32_t LTIF : 1; + __IO uint32_t HTIF : 1; + __IO uint32_t REGIF : 1; + __IO uint32_t SQRIF : 1; + __IO uint32_t JQRIF : 1; +} stc_adc_ifr_field_t; + +typedef struct +{ + __IO uint32_t SGLIC : 1; + __IO uint32_t LTIC : 1; + __IO uint32_t HTIC : 1; + __IO uint32_t REGIC : 1; + __IO uint32_t SQRIC : 1; + __IO uint32_t JQRIC : 1; +} stc_adc_icr_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger0_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t TIM3 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t VC0 : 1; + __IO uint32_t VC1 : 1; + __IO uint32_t RTC : 1; + __IO uint32_t PCA : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t DMA : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PD07 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PA15 : 1; + __IO uint32_t PB15 : 1; + __IO uint32_t PC15 : 1; +} stc_adc_exttrigger1_field_t; + +typedef struct +{ + __IO uint32_t START : 1; +} stc_adc_sglstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; +} stc_adc_sqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; +} stc_adc_jqrstart_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 1; +} stc_aes_cr_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data1_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data2_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_aes_data3_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key0_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key1_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key2_field_t; + +typedef struct +{ + __IO uint32_t KEY0 :32; +} stc_aes_key3_field_t; + +typedef struct +{ + __IO uint32_t BGR_EN : 1; + __IO uint32_t TS_EN : 1; +} stc_bgr_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM_START : 1; + __IO uint32_t REFCLK_SEL : 3; + __IO uint32_t CALCLK_SEL : 2; + __IO uint32_t MON_EN : 1; + __IO uint32_t IE : 1; + __IO uint32_t CALCLK_SEL2 : 1; +} stc_clk_trim_cr_field_t; + +typedef struct +{ + __IO uint32_t RCNTVAL :32; +} stc_clk_trim_refcon_field_t; + +typedef struct +{ + __IO uint32_t REFCNT :32; +} stc_clk_trim_refcnt_field_t; + +typedef struct +{ + __IO uint32_t CALCNT :32; +} stc_clk_trim_calcnt_field_t; + +typedef struct +{ + __IO uint32_t STOP : 1; + __IO uint32_t CALCNT_OF : 1; + __IO uint32_t XTL_FAULT : 1; + __IO uint32_t XTH_FAULT : 1; + __IO uint32_t PLL_FAULT : 1; +} stc_clk_trim_ifr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t XTL_FAULT_CLR : 1; + __IO uint32_t XTH_FAULT_CLR : 1; + __IO uint32_t PLL_FAULT_CLR : 1; +} stc_clk_trim_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCNTVAL :32; +} stc_clk_trim_calcon_field_t; + +typedef struct +{ + __IO uint32_t CR : 1; + __IO uint32_t FLAG : 1; +} stc_crc_cr_field_t; + +typedef struct +{ + __IO uint32_t RESULT :32; +} stc_crc_result_field_t; + +typedef struct +{ + __IO uint32_t DATA :32; +} stc_crc_data_field_t; + +typedef struct +{ + __IO uint32_t TIM0 : 1; + __IO uint32_t TIM1 : 1; + __IO uint32_t TIM2 : 1; + __IO uint32_t LPTIM : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t RTC : 1; + uint32_t RESERVED10 : 1; + __IO uint32_t TIM3 : 1; +} stc_debug_active_field_t; + +typedef struct +{ + uint32_t RESERVED0 :24; + __IO uint32_t HALT : 4; + __IO uint32_t PRIO : 1; + uint32_t RESERVED29 : 1; + __IO uint32_t ST : 1; + __IO uint32_t EN : 1; +} stc_dmac_conf_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 3; + __IO uint32_t TRI_SEL : 6; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa0_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb0_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr0_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr0_field_t; + +typedef struct +{ + __IO uint32_t TC :16; + __IO uint32_t BC : 4; + uint32_t RESERVED20 : 3; + __IO uint32_t TRI_SEL : 6; + __IO uint32_t ST : 1; + __IO uint32_t PAS : 1; + __IO uint32_t ENS : 1; +} stc_dmac_confa1_field_t; + +typedef struct +{ + __IO uint32_t MSK : 1; + uint32_t RESERVED1 :15; + __IO uint32_t STAT : 3; + __IO uint32_t FIS_IE : 1; + __IO uint32_t ERR_IE : 1; + __IO uint32_t RD : 1; + __IO uint32_t RS : 1; + __IO uint32_t RC : 1; + __IO uint32_t FD : 1; + __IO uint32_t FS : 1; + __IO uint32_t WIDTH : 2; + __IO uint32_t MODE : 2; +} stc_dmac_confb1_field_t; + +typedef struct +{ + __IO uint32_t SRCADR :32; +} stc_dmac_srcadr1_field_t; + +typedef struct +{ + __IO uint32_t DSTADR :32; +} stc_dmac_dstadr1_field_t; + +typedef struct +{ + __IO uint32_t TNVS : 9; +} stc_flash_tnvs_field_t; + +typedef struct +{ + __IO uint32_t TPGS : 8; +} stc_flash_tpgs_field_t; + +typedef struct +{ + __IO uint32_t TPROG : 9; +} stc_flash_tprog_field_t; + +typedef struct +{ + __IO uint32_t TSERASE :18; +} stc_flash_tserase_field_t; + +typedef struct +{ + __IO uint32_t TMERASE :21; +} stc_flash_tmerase_field_t; + +typedef struct +{ + __IO uint32_t TPRCV :12; +} stc_flash_tprcv_field_t; + +typedef struct +{ + __IO uint32_t TSRCV :12; +} stc_flash_tsrcv_field_t; + +typedef struct +{ + __IO uint32_t TMRCV :13; +} stc_flash_tmrcv_field_t; + +typedef struct +{ + __IO uint32_t OP : 2; + __IO uint32_t WAIT : 2; + __IO uint32_t BUSY : 1; + __IO uint32_t IE : 2; + uint32_t RESERVED7 : 2; + __IO uint32_t DPSTB_EN : 1; +} stc_flash_cr_field_t; + +typedef struct +{ + __IO uint32_t IF0 : 1; + __IO uint32_t IF1 : 1; +} stc_flash_ifr_field_t; + +typedef struct +{ + __IO uint32_t ICLR0 : 1; + __IO uint32_t ICLR1 : 1; +} stc_flash_iclr_field_t; + +typedef struct +{ + __IO uint32_t BYSEQ :16; +} stc_flash_bypass_field_t; + +typedef struct +{ + __IO uint32_t SLOCK :32; +} stc_flash_slock_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pa15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pb15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc07_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc08_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc09_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc10_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc11_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc12_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc13_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc14_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pc15_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd00_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd01_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd02_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd03_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd04_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd05_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd06_sel_field_t; + +typedef struct +{ + __IO uint32_t SEL : 3; +} stc_gpio_pd07_sel_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_padir_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pain_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_paout_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_paads_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pabset_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pabclr_field_t; + +typedef struct +{ + __IO uint32_t PABCLR :16; + __IO uint32_t PABSET :16; +} stc_gpio_pabsetclr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_padr_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_papu_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_papd_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_paod_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pahie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_palie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_parie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pafie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbdir_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbin_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbout_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbads_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbbset_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbbclr_field_t; + +typedef struct +{ + __IO uint32_t PBBCLR :16; + __IO uint32_t PBBSET :16; +} stc_gpio_pbbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbdr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbpu_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbpd_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbod_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbhie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pblie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbrie_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pbfie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcdir_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcin_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcout_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcads_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcbset_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcbclr_field_t; + +typedef struct +{ + __IO uint32_t PCBCLR :16; + __IO uint32_t PCBSET :16; +} stc_gpio_pcbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcdr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcpu_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcpd_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcod_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pchie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pclie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcrie_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pcfie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pddir_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdin_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdout_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdads_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdbset_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdbclr_field_t; + +typedef struct +{ + __IO uint32_t PDBCLR : 8; + uint32_t RESERVED8 : 8; + __IO uint32_t PDBSET : 8; +} stc_gpio_pdbsetclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pddr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdpu_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdpd_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdod_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdhie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdlie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdrie_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pdfie_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pa_stat_field_t; + +typedef struct +{ + __IO uint32_t PA00 : 1; + __IO uint32_t PA01 : 1; + __IO uint32_t PA02 : 1; + __IO uint32_t PA03 : 1; + __IO uint32_t PA04 : 1; + __IO uint32_t PA05 : 1; + __IO uint32_t PA06 : 1; + __IO uint32_t PA07 : 1; + __IO uint32_t PA08 : 1; + __IO uint32_t PA09 : 1; + __IO uint32_t PA10 : 1; + __IO uint32_t PA11 : 1; + __IO uint32_t PA12 : 1; + __IO uint32_t PA13 : 1; + __IO uint32_t PA14 : 1; + __IO uint32_t PA15 : 1; +} stc_gpio_pa_iclr_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pb_stat_field_t; + +typedef struct +{ + __IO uint32_t PB00 : 1; + __IO uint32_t PB01 : 1; + __IO uint32_t PB02 : 1; + __IO uint32_t PB03 : 1; + __IO uint32_t PB04 : 1; + __IO uint32_t PB05 : 1; + __IO uint32_t PB06 : 1; + __IO uint32_t PB07 : 1; + __IO uint32_t PB08 : 1; + __IO uint32_t PB09 : 1; + __IO uint32_t PB10 : 1; + __IO uint32_t PB11 : 1; + __IO uint32_t PB12 : 1; + __IO uint32_t PB13 : 1; + __IO uint32_t PB14 : 1; + __IO uint32_t PB15 : 1; +} stc_gpio_pb_iclr_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pc_stat_field_t; + +typedef struct +{ + __IO uint32_t PC00 : 1; + __IO uint32_t PC01 : 1; + __IO uint32_t PC02 : 1; + __IO uint32_t PC03 : 1; + __IO uint32_t PC04 : 1; + __IO uint32_t PC05 : 1; + __IO uint32_t PC06 : 1; + __IO uint32_t PC07 : 1; + __IO uint32_t PC08 : 1; + __IO uint32_t PC09 : 1; + __IO uint32_t PC10 : 1; + __IO uint32_t PC11 : 1; + __IO uint32_t PC12 : 1; + __IO uint32_t PC13 : 1; + __IO uint32_t PC14 : 1; + __IO uint32_t PC15 : 1; +} stc_gpio_pc_iclr_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pd_stat_field_t; + +typedef struct +{ + __IO uint32_t PD00 : 1; + __IO uint32_t PD01 : 1; + __IO uint32_t PD02 : 1; + __IO uint32_t PD03 : 1; + __IO uint32_t PD04 : 1; + __IO uint32_t PD05 : 1; + __IO uint32_t PD06 : 1; + __IO uint32_t PD07 : 1; +} stc_gpio_pd_iclr_field_t; + +typedef struct +{ + __IO uint32_t IESEL : 1; +} stc_gpio_ctrl0_field_t; + +typedef struct +{ + __IO uint32_t EXT_CLK_SEL : 4; + __IO uint32_t SSN0_SEL : 4; + __IO uint32_t PCLK_SEL : 2; + __IO uint32_t HCLK_SEL : 2; + __IO uint32_t PCLK_EN : 1; + __IO uint32_t HCLK_EN : 1; + __IO uint32_t IR_POL : 1; +} stc_gpio_ctrl1_field_t; + +typedef struct +{ + __IO uint32_t SSN1_SEL : 4; + uint32_t RESERVED4 :11; + __IO uint32_t AHB_SEL : 1; +} stc_gpio_ctrl2_field_t; + +typedef struct +{ + __IO uint32_t TIM0_G : 3; + __IO uint32_t TIM1_G : 3; + __IO uint32_t TIM2_G : 3; + __IO uint32_t TIM3_G : 3; + __IO uint32_t LPTIM_G : 3; +} stc_gpio_timgs_field_t; + +typedef struct +{ + __IO uint32_t TIM0_E : 3; + __IO uint32_t TIM1_E : 3; + __IO uint32_t TIM2_E : 3; + __IO uint32_t TIM3_E : 3; + __IO uint32_t LPTIM_E : 3; +} stc_gpio_times_field_t; + +typedef struct +{ + __IO uint32_t TIM0_CA : 3; + __IO uint32_t TIM1_CA : 3; + __IO uint32_t TIM2_CA : 3; + __IO uint32_t TIM3_CA : 3; + __IO uint32_t TIM3_CB : 3; +} stc_gpio_timcps_field_t; + +typedef struct +{ + __IO uint32_t PCA_CH0 : 3; + __IO uint32_t PCA_ECI : 3; +} stc_gpio_pcas_field_t; + +typedef struct +{ + __IO uint32_t DIVIDEND :32; +} stc_hdiv_dividend_field_t; + +typedef struct +{ + __IO uint32_t DIVISOR :16; +} stc_hdiv_divisor_field_t; + +typedef struct +{ + __IO uint32_t QUOTIENT :32; +} stc_hdiv_quotient_field_t; + +typedef struct +{ + __IO uint32_t REMAINDER :32; +} stc_hdiv_remainder_field_t; + +typedef struct +{ + __IO uint32_t SIGN : 1; +} stc_hdiv_sign_field_t; + +typedef struct +{ + __IO uint32_t END : 1; + __IO uint32_t ZERO : 1; +} stc_hdiv_stat_field_t; + +typedef struct +{ + __IO uint32_t TME : 1; +} stc_i2c_tmrun_field_t; + +typedef struct +{ + __IO uint32_t TM : 8; +} stc_i2c_tm_field_t; + +typedef struct +{ + __IO uint32_t H1M : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t AA : 1; + __IO uint32_t SI : 1; + __IO uint32_t STO : 1; + __IO uint32_t STA : 1; + __IO uint32_t ENS : 1; +} stc_i2c_cr_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; +} stc_i2c_data_field_t; + +typedef struct +{ + __IO uint32_t GC : 1; + __IO uint32_t ADR : 7; +} stc_i2c_addr_field_t; + +typedef struct +{ + __IO uint32_t STA : 8; +} stc_i2c_stat_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t LCDCLK : 2; + __IO uint32_t CPCLK : 2; + __IO uint32_t BIAS : 1; + __IO uint32_t DUTY : 3; + __IO uint32_t BSEL : 3; + __IO uint32_t CONTRAST : 4; +} stc_lcd_cr0_field_t; + +typedef struct +{ + __IO uint32_t BLINKCNT : 6; + __IO uint32_t BLINKEN : 1; + __IO uint32_t CLKSRC : 1; + __IO uint32_t MODE : 1; + __IO uint32_t IE : 1; + __IO uint32_t DMAEN : 1; + __IO uint32_t INTF : 1; +} stc_lcd_cr1_field_t; + +typedef struct +{ + uint32_t RESERVED0 :10; + __IO uint32_t INTF : 1; +} stc_lcd_intclr_field_t; + +typedef struct +{ + __IO uint32_t S0 : 1; + __IO uint32_t S1 : 1; + __IO uint32_t S2 : 1; + __IO uint32_t S3 : 1; + __IO uint32_t S4 : 1; + __IO uint32_t S5 : 1; + __IO uint32_t S6 : 1; + __IO uint32_t S7 : 1; + __IO uint32_t S8 : 1; + __IO uint32_t S9 : 1; + __IO uint32_t S10 : 1; + __IO uint32_t S11 : 1; + __IO uint32_t S12 : 1; + __IO uint32_t S13 : 1; + __IO uint32_t S14 : 1; + __IO uint32_t S15 : 1; + __IO uint32_t S16 : 1; + __IO uint32_t S17 : 1; + __IO uint32_t S18 : 1; + __IO uint32_t S19 : 1; + __IO uint32_t S20 : 1; + __IO uint32_t S21 : 1; + __IO uint32_t S22 : 1; + __IO uint32_t S23 : 1; + __IO uint32_t S24 : 1; + __IO uint32_t S25 : 1; + __IO uint32_t S26 : 1; + __IO uint32_t S27 : 1; + __IO uint32_t S28 : 1; + __IO uint32_t S29 : 1; + __IO uint32_t S30 : 1; + __IO uint32_t S31 : 1; +} stc_lcd_poen0_field_t; + +typedef struct +{ + __IO uint32_t S32 : 1; + __IO uint32_t S33 : 1; + __IO uint32_t S34 : 1; + __IO uint32_t S35 : 1; + __IO uint32_t S36C7 : 1; + __IO uint32_t S37C6 : 1; + __IO uint32_t S38C5 : 1; + __IO uint32_t S39C4 : 1; + __IO uint32_t C0 : 1; + __IO uint32_t C1 : 1; + __IO uint32_t C2 : 1; + __IO uint32_t C3 : 1; + __IO uint32_t MUX : 1; +} stc_lcd_poen1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram0_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram1_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram2_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram3_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram4_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram5_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram6_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; + __IO uint32_t D8 : 1; + __IO uint32_t D9 : 1; + __IO uint32_t D10 : 1; + __IO uint32_t D11 : 1; + __IO uint32_t D12 : 1; + __IO uint32_t D13 : 1; + __IO uint32_t D14 : 1; + __IO uint32_t D15 : 1; + __IO uint32_t D16 : 1; + __IO uint32_t D17 : 1; + __IO uint32_t D18 : 1; + __IO uint32_t D19 : 1; + __IO uint32_t D20 : 1; + __IO uint32_t D21 : 1; + __IO uint32_t D22 : 1; + __IO uint32_t D23 : 1; + __IO uint32_t D24 : 1; + __IO uint32_t D25 : 1; + __IO uint32_t D26 : 1; + __IO uint32_t D27 : 1; + __IO uint32_t D28 : 1; + __IO uint32_t D29 : 1; + __IO uint32_t D30 : 1; + __IO uint32_t D31 : 1; +} stc_lcd_ram7_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ram8_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ram9_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_rama_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramb_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramc_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramd_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_rame_field_t; + +typedef struct +{ + __IO uint32_t D0 : 1; + __IO uint32_t D1 : 1; + __IO uint32_t D2 : 1; + __IO uint32_t D3 : 1; + __IO uint32_t D4 : 1; + __IO uint32_t D5 : 1; + __IO uint32_t D6 : 1; + __IO uint32_t D7 : 1; +} stc_lcd_ramf_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_lptimer_cnt_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_lptimer_arr_field_t; + +typedef struct +{ + __IO uint32_t TR : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOG_EN : 1; + __IO uint32_t TCK_SEL : 2; + uint32_t RESERVED6 : 1; + __IO uint32_t WT_FLAG : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATE_P : 1; + __IO uint32_t IE : 1; +} stc_lptimer_cr_field_t; + +typedef struct +{ + __IO uint32_t TF : 1; +} stc_lptimer_ifr_field_t; + +typedef struct +{ + __IO uint32_t TFC : 1; +} stc_lptimer_iclr_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; +} stc_lpuart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 2; + __IO uint32_t SCLKSEL : 2; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; +} stc_lpuart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; +} stc_lpuart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; +} stc_lpuart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; +} stc_lpuart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; +} stc_lpuart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; +} stc_lpuart_scnt_field_t; + +typedef struct +{ + __IO uint32_t LVDEN : 1; + __IO uint32_t ACT : 1; + __IO uint32_t SOURCE_SEL : 2; + __IO uint32_t VTDS : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FTEN : 1; + __IO uint32_t RTEN : 1; + __IO uint32_t HTEN : 1; + __IO uint32_t IE : 1; +} stc_lvd_cr_field_t; + +typedef struct +{ + __IO uint32_t INTF : 1; + __IO uint32_t FILTER : 1; +} stc_lvd_ifr_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t MODE : 1; + __IO uint32_t UBUFSEL : 1; + __IO uint32_t RESSEL : 1; + __IO uint32_t BIASSEL : 3; + __IO uint32_t NEGSEL : 2; + __IO uint32_t POSSEL : 2; + __IO uint32_t PGAGAIN : 3; + __IO uint32_t POEN : 1; + __IO uint32_t RESINMUX : 2; +} stc_opa_cr0_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t MODE : 1; + __IO uint32_t UBUFSEL : 1; + __IO uint32_t RESSEL : 1; + __IO uint32_t BIASSEL : 3; + __IO uint32_t NEGSEL : 2; + __IO uint32_t POSSEL : 2; + __IO uint32_t PGAGAIN : 3; + __IO uint32_t POEN : 1; + __IO uint32_t RESINMUX : 2; +} stc_opa_cr1_field_t; + +typedef struct +{ + __IO uint32_t EN : 1; + __IO uint32_t AZEN : 1; + __IO uint32_t MODE : 1; + __IO uint32_t UBUFSEL : 1; + __IO uint32_t RESSEL : 1; + __IO uint32_t BIASSEL : 3; + __IO uint32_t NEGSEL : 2; + __IO uint32_t POSSEL : 2; + __IO uint32_t PGAGAIN : 3; + __IO uint32_t POEN : 1; + __IO uint32_t RESINMUX : 2; +} stc_opa_cr2_field_t; + +typedef struct +{ + __IO uint8_t ADCTR_EN : 1; + __IO uint8_t TRIGGER : 1; + __IO uint8_t AZ_PULSE : 1; + __IO uint8_t CLK_SW_SET : 1; + __IO uint8_t CLK_SEL : 4; +} stc_opa_cr_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t CR : 1; + __IO uint32_t CF : 1; +} stc_pca_ccon_field_t; + +typedef struct +{ + __IO uint32_t CFIE : 1; + __IO uint32_t CPS : 3; + uint32_t RESERVED4 : 2; + __IO uint32_t WDTE : 1; + __IO uint32_t CIDL : 1; +} stc_pca_cmod_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_pca_cnt_field_t; + +typedef struct +{ + __IO uint32_t CCF0 : 1; + __IO uint32_t CCF1 : 1; + __IO uint32_t CCF2 : 1; + __IO uint32_t CCF3 : 1; + __IO uint32_t CCF4 : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t CF : 1; +} stc_pca_iclr_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm0_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm1_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm2_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm3_field_t; + +typedef struct +{ + __IO uint32_t CCIE : 1; + __IO uint32_t PWM : 1; + __IO uint32_t TOG : 1; + __IO uint32_t MAT : 1; + __IO uint32_t CAPN : 1; + __IO uint32_t CAPP : 1; + __IO uint32_t ECOM : 1; +} stc_pca_ccapm4_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; +} stc_pca_ccap0h_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 : 8; +} stc_pca_ccap0l_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; +} stc_pca_ccap1h_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 : 8; +} stc_pca_ccap1l_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; +} stc_pca_ccap2h_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 : 8; +} stc_pca_ccap2l_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; +} stc_pca_ccap3h_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 : 8; +} stc_pca_ccap3l_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; +} stc_pca_ccap4h_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 : 8; +} stc_pca_ccap4l_field_t; + +typedef struct +{ + __IO uint32_t CCAPO0 : 1; + __IO uint32_t CCAPO1 : 1; + __IO uint32_t CCAPO2 : 1; + __IO uint32_t CCAPO3 : 1; + __IO uint32_t CCAPO4 : 1; +} stc_pca_ccapo_field_t; + +typedef struct +{ + __IO uint32_t CCAP0 :16; +} stc_pca_ccap0_field_t; + +typedef struct +{ + __IO uint32_t CCAP1 :16; +} stc_pca_ccap1_field_t; + +typedef struct +{ + __IO uint32_t CCAP2 :16; +} stc_pca_ccap2_field_t; + +typedef struct +{ + __IO uint32_t CCAP3 :16; +} stc_pca_ccap3_field_t; + +typedef struct +{ + __IO uint32_t CCAP4 :16; +} stc_pca_ccap4_field_t; + +typedef struct +{ + __IO uint32_t CARR :16; +} stc_pca_carr_field_t; + +typedef struct +{ + __IO uint32_t EPWM : 1; +} stc_pca_epwm_field_t; + +typedef struct +{ + __IO uint8_t RUN : 1; +} stc_pcnt_run_field_t; + +typedef struct +{ + __IO uint8_t MODE : 2; + __IO uint8_t CLKSEL : 2; + __IO uint8_t DIR : 1; + __IO uint8_t S0P : 1; + __IO uint8_t S1P : 1; +} stc_pcnt_cr_field_t; + +typedef struct +{ + __IO uint32_t CLKDIV :13; + __IO uint32_t DEBTOP : 3; + __IO uint32_t EN : 1; +} stc_pcnt_flt_field_t; + +typedef struct +{ + __IO uint32_t TH :12; + uint32_t RESERVED12 : 4; + __IO uint32_t EN : 1; +} stc_pcnt_tocr_field_t; + +typedef struct +{ + __IO uint8_t T2C : 1; + __IO uint8_t B2T : 1; + __IO uint8_t B2C : 1; +} stc_pcnt_cmd_field_t; + +typedef struct +{ + __IO uint8_t DIR : 1; +} stc_pcnt_sr1_field_t; + +typedef struct +{ + __IO uint16_t CNT :16; +} stc_pcnt_cnt_field_t; + +typedef struct +{ + __IO uint16_t TOP :16; +} stc_pcnt_top_field_t; + +typedef struct +{ + __IO uint16_t BUF :16; +} stc_pcnt_buf_field_t; + +typedef struct +{ + __IO uint8_t UF : 1; + __IO uint8_t OV : 1; + __IO uint8_t TO : 1; + __IO uint8_t DIR : 1; + __IO uint8_t FE : 1; + __IO uint8_t BB : 1; + __IO uint8_t S0E : 1; + __IO uint8_t S1E : 1; +} stc_pcnt_ifr_field_t; + +typedef struct +{ + __IO uint8_t UF : 1; + __IO uint8_t OV : 1; + __IO uint8_t TO : 1; + __IO uint8_t DIR : 1; + __IO uint8_t FE : 1; + __IO uint8_t BB : 1; + __IO uint8_t S0E : 1; + __IO uint8_t S1E : 1; +} stc_pcnt_icr_field_t; + +typedef struct +{ + __IO uint8_t UF : 1; + __IO uint8_t OV : 1; + __IO uint8_t TO : 1; + __IO uint8_t DIR : 1; + __IO uint8_t FE : 1; + __IO uint8_t BB : 1; + __IO uint8_t S0E : 1; + __IO uint8_t S1E : 1; +} stc_pcnt_ien_field_t; + +typedef struct +{ + __IO uint8_t T2C : 1; + __IO uint8_t B2T : 1; + __IO uint8_t B2C : 1; +} stc_pcnt_sr2_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t IE : 1; +} stc_ram_cr_field_t; + +typedef struct +{ + __IO uint32_t ERRADDR :13; +} stc_ram_erraddr_field_t; + +typedef struct +{ + __IO uint32_t ERR : 1; +} stc_ram_ifr_field_t; + +typedef struct +{ + __IO uint32_t ERRCLR : 1; +} stc_ram_iclr_field_t; + +typedef struct +{ + __IO uint32_t POR5V : 1; + __IO uint32_t POR15V : 1; + __IO uint32_t LVD : 1; + __IO uint32_t WDT : 1; + __IO uint32_t PCA : 1; + __IO uint32_t LOCKUP : 1; + __IO uint32_t SYSREQ : 1; + __IO uint32_t RSTB : 1; +} stc_reset_flag_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + uint32_t RESERVED15 : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; + __IO uint32_t DIV : 1; +} stc_reset_prei_field_t; + +typedef struct +{ + __IO uint32_t RNGCIR_EN : 1; + __IO uint32_t RNG_RUN : 1; +} stc_rng_cr_field_t; + +typedef struct +{ + __IO uint32_t LOAD : 1; + __IO uint32_t FDBK : 1; + __IO uint32_t CNT : 3; +} stc_rng_mode_field_t; + +typedef struct +{ + __IO uint32_t DATA0 :32; +} stc_rng_data0_field_t; + +typedef struct +{ + __IO uint32_t DATA1 :32; +} stc_rng_data1_field_t; + +typedef struct +{ + __IO uint32_t PRDS : 3; + __IO uint32_t AMPM : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t HZ1OE : 1; + __IO uint32_t HZ1SEL : 1; + __IO uint32_t START : 1; + __IO uint32_t PRDX : 6; + __IO uint32_t PRDSEL : 1; +} stc_rtc_cr0_field_t; + +typedef struct +{ + __IO uint32_t WAIT : 1; + __IO uint32_t WAITF : 1; + uint32_t RESERVED2 : 1; + __IO uint32_t PRDF : 1; + __IO uint32_t ALMF : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t ALMIE : 1; + __IO uint32_t ALMEN : 1; + __IO uint32_t CKSEL : 3; +} stc_rtc_cr1_field_t; + +typedef struct +{ + __IO uint32_t SECL : 4; + __IO uint32_t SECH : 3; +} stc_rtc_sec_field_t; + +typedef struct +{ + __IO uint32_t MINL : 4; + __IO uint32_t MINH : 3; +} stc_rtc_min_field_t; + +typedef struct +{ + __IO uint32_t HOURL : 4; + __IO uint32_t HOURH : 2; +} stc_rtc_hour_field_t; + +typedef struct +{ + __IO uint32_t WEEK : 3; +} stc_rtc_week_field_t; + +typedef struct +{ + __IO uint32_t DAYL : 4; + __IO uint32_t DAYH : 2; +} stc_rtc_day_field_t; + +typedef struct +{ + __IO uint32_t MON : 5; +} stc_rtc_mon_field_t; + +typedef struct +{ + __IO uint32_t YEARL : 4; + __IO uint32_t YEARH : 4; +} stc_rtc_year_field_t; + +typedef struct +{ + __IO uint32_t ALMMINL : 4; + __IO uint32_t ALMMINH : 3; +} stc_rtc_almmin_field_t; + +typedef struct +{ + __IO uint32_t ALMHOURL : 4; + __IO uint32_t ALMHOURH : 2; +} stc_rtc_almhour_field_t; + +typedef struct +{ + __IO uint32_t ALMWEEK : 7; +} stc_rtc_almweek_field_t; + +typedef struct +{ + __IO uint32_t CR : 9; + uint32_t RESERVED9 : 6; + __IO uint32_t EN : 1; +} stc_rtc_compen_field_t; + +typedef struct +{ + __IO uint32_t SPR0 : 1; + __IO uint32_t SPR1 : 1; + __IO uint32_t CPHA : 1; + __IO uint32_t CPOL : 1; + __IO uint32_t MSTR : 1; + uint32_t RESERVED5 : 1; + __IO uint32_t SPEN : 1; + __IO uint32_t SPR2 : 1; +} stc_spi_cr_field_t; + +typedef struct +{ + __IO uint32_t SSN : 1; +} stc_spi_ssn_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t RXNE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t BUSY : 1; + __IO uint32_t MDF : 1; + __IO uint32_t SSERR : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t SPIF : 1; +} stc_spi_stat_field_t; + +typedef struct +{ + __IO uint32_t DAT : 8; +} stc_spi_data_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 2; + __IO uint32_t INT_EN : 1; + __IO uint32_t HDMA_RX : 1; + __IO uint32_t HDMA_TX : 1; + __IO uint32_t TXEIE : 1; + __IO uint32_t RXNEIE : 1; +} stc_spi_cr2_field_t; + +typedef struct +{ + __IO uint32_t INT_CLR : 1; +} stc_spi_iclr_field_t; + +typedef struct +{ + __IO uint32_t RCH_EN : 1; + __IO uint32_t XTH_EN : 1; + __IO uint32_t RCL_EN : 1; + __IO uint32_t XTL_EN : 1; + __IO uint32_t PLL_EN : 1; + __IO uint32_t CLK_SW5_SEL : 3; + __IO uint32_t HCLK_PRS : 3; + __IO uint32_t PCLK_PRS : 2; + uint32_t RESERVED13 : 2; + __IO uint32_t WAKEUP_BYRCH : 1; +} stc_sysctrl_sysctrl0_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 1; + __IO uint32_t EXTH_EN : 1; + __IO uint32_t EXTL_EN : 1; + __IO uint32_t XTL_ALWAYS_ON : 1; + uint32_t RESERVED4 : 1; + __IO uint32_t RTC_LPW : 1; + __IO uint32_t LOCKUP_EN : 1; + uint32_t RESERVED7 : 1; + __IO uint32_t SWD_USE_IO : 1; + __IO uint32_t RTC_FREQ_ADJUST : 3; +} stc_sysctrl_sysctrl1_field_t; + +typedef struct +{ + __IO uint32_t SYSCTRL2 :16; +} stc_sysctrl_sysctrl2_field_t; + +typedef struct +{ + __IO uint32_t TRIM :11; + __IO uint32_t STABLE : 1; +} stc_sysctrl_rch_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t XTH_FSEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; +} stc_sysctrl_xth_cr_field_t; + +typedef struct +{ + __IO uint32_t TRIM :10; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; +} stc_sysctrl_rcl_cr_field_t; + +typedef struct +{ + __IO uint32_t DRIVER : 2; + __IO uint32_t AMP_SEL : 2; + __IO uint32_t STARTUP : 2; + __IO uint32_t STABLE : 1; +} stc_sysctrl_xtl_cr_field_t; + +typedef struct +{ + __IO uint32_t UART0 : 1; + __IO uint32_t UART1 : 1; + __IO uint32_t LPUART0 : 1; + __IO uint32_t LPUART1 : 1; + __IO uint32_t I2C0 : 1; + __IO uint32_t I2C1 : 1; + __IO uint32_t SPI0 : 1; + __IO uint32_t SPI1 : 1; + __IO uint32_t BASETIM : 1; + __IO uint32_t LPTIM : 1; + __IO uint32_t ADVTIM : 1; + __IO uint32_t TIM3 : 1; + uint32_t RESERVED12 : 1; + __IO uint32_t OPA : 1; + __IO uint32_t PCA : 1; + __IO uint32_t WDT : 1; + __IO uint32_t ADC : 1; + __IO uint32_t VC : 1; + __IO uint32_t RNG : 1; + __IO uint32_t PCNT : 1; + __IO uint32_t RTC : 1; + __IO uint32_t TRIM : 1; + __IO uint32_t LCD : 1; + uint32_t RESERVED23 : 1; + __IO uint32_t TICK : 1; + __IO uint32_t SWD : 1; + __IO uint32_t CRC : 1; + __IO uint32_t AES : 1; + __IO uint32_t GPIO : 1; + __IO uint32_t DMA : 1; + __IO uint32_t DIV : 1; + __IO uint32_t FLASH : 1; +} stc_sysctrl_peri_clken_field_t; + +typedef struct +{ + __IO uint32_t REFSEL : 2; + __IO uint32_t FOSC : 3; + __IO uint32_t DIVN : 4; + __IO uint32_t IBSEL : 2; + __IO uint32_t LFSEL : 2; + __IO uint32_t FRSEL : 2; + __IO uint32_t STARTUP : 3; + __IO uint32_t STABLE : 1; +} stc_sysctrl_pll_cr_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim0_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim0_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim0_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim0_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim0_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim0_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim0_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim0_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim0_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim0_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim0_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim0_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim0_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim0_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim0_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim0_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim0_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim0_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim0_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim0_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim0_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; +} stc_tim0_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim0_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim0_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim0_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim0_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim0_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim0_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim1_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim1_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim1_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim1_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim1_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim1_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim1_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim1_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim1_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim1_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim1_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim1_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim1_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim1_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim1_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim1_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim1_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim1_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim1_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim1_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim1_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; +} stc_tim1_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim1_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim1_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim1_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim1_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim1_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim1_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim2_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim2_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim2_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim2_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim2_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim2_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim2_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim2_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim2_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim2_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim2_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim2_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim2_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim2_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim2_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim2_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim2_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim2_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + uint32_t RESERVED3 : 2; + __IO uint32_t CB0F : 1; + uint32_t RESERVED6 : 2; + __IO uint32_t CA0E : 1; + uint32_t RESERVED9 : 2; + __IO uint32_t CB0E : 1; + uint32_t RESERVED12 : 2; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim2_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim2_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + uint32_t RESERVED8 :16; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim2_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + uint32_t RESERVED2 : 2; + __IO uint32_t CMB0E : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t ADTE : 1; +} stc_tim2_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim2_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim2_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim2_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim2_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim2_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim2_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim3_mode0_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim3_mode0_cnt_field_t; + +typedef struct +{ + __IO uint32_t CNT32 :32; +} stc_tim3_mode0_cnt32_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t MD : 1; + __IO uint32_t CT : 1; + __IO uint32_t TOGEN : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t GATE : 1; + __IO uint32_t GATEP : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; +} stc_tim3_mode0_m0cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim3_mode0_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; +} stc_tim3_mode0_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 :12; + __IO uint32_t MOE : 1; +} stc_tim3_mode0_dtr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim3_mode1_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CT : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PRS : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t EDG1ST : 1; + __IO uint32_t EDG2ND : 1; + __IO uint32_t UIE : 1; + uint32_t RESERVED11 : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; +} stc_tim3_mode1_m1cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim3_mode1_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; +} stc_tim3_mode1_iclr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 5; + __IO uint32_t TS : 3; + uint32_t RESERVED8 : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim3_mode1_mscr_field_t; + +typedef struct +{ + __IO uint32_t FLTA0 : 3; + uint32_t RESERVED3 : 1; + __IO uint32_t FLTB0 : 3; + uint32_t RESERVED7 :21; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode1_fltr_field_t; + +typedef struct +{ + uint32_t RESERVED0 : 8; + __IO uint32_t CIEA : 1; +} stc_tim3_mode1_cr0_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim3_mode1_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t ARR :16; +} stc_tim3_mode23_arr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim3_mode23_cnt_field_t; + +typedef struct +{ + __IO uint32_t CTEN : 1; + __IO uint32_t COMP : 1; + __IO uint32_t CT : 1; + __IO uint32_t PWM2S : 1; + __IO uint32_t PRS : 3; + __IO uint32_t BUFPEN : 1; + __IO uint32_t CRG : 1; + __IO uint32_t CFG : 1; + __IO uint32_t UIE : 1; + __IO uint32_t UDE : 1; + __IO uint32_t MODE : 2; + __IO uint32_t ONESHOT : 1; + __IO uint32_t CSG : 1; + __IO uint32_t OCCS : 1; + __IO uint32_t URS : 1; + __IO uint32_t TDE : 1; + __IO uint32_t TIE : 1; + __IO uint32_t BIE : 1; + __IO uint32_t CIS : 2; + __IO uint32_t OCCE : 1; + __IO uint32_t TG : 1; + __IO uint32_t UG : 1; + __IO uint32_t BG : 1; + __IO uint32_t DIR : 1; +} stc_tim3_mode23_m23cr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim3_mode23_ifr_field_t; + +typedef struct +{ + __IO uint32_t UIF : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t CA0F : 1; + __IO uint32_t CA1F : 1; + __IO uint32_t CA2F : 1; + __IO uint32_t CB0F : 1; + __IO uint32_t CB1F : 1; + __IO uint32_t CB2F : 1; + __IO uint32_t CA0E : 1; + __IO uint32_t CA1E : 1; + __IO uint32_t CA2E : 1; + __IO uint32_t CB0E : 1; + __IO uint32_t CB1E : 1; + __IO uint32_t CB2E : 1; + __IO uint32_t BIF : 1; + __IO uint32_t TIF : 1; +} stc_tim3_mode23_iclr_field_t; + +typedef struct +{ + __IO uint32_t MMS : 3; + __IO uint32_t CCDS : 1; + __IO uint32_t MSM : 1; + __IO uint32_t TS : 3; + __IO uint32_t SMS : 3; + __IO uint32_t IA0S : 1; + __IO uint32_t IB0S : 1; +} stc_tim3_mode23_mscr_field_t; + +typedef struct +{ + __IO uint32_t OCMA0_FLTA0 : 3; + __IO uint32_t CCPA0 : 1; + __IO uint32_t OCMB0_FLTB0 : 3; + __IO uint32_t CCPB0 : 1; + __IO uint32_t OCMA1_FLTA1 : 3; + __IO uint32_t CCPA1 : 1; + __IO uint32_t OCMB1_FLTB1 : 3; + __IO uint32_t CCPB1 : 1; + __IO uint32_t OCMA2_FLTA2 : 3; + __IO uint32_t CCPA2 : 1; + __IO uint32_t OCMB2_FLTB2 : 3; + __IO uint32_t CCPB2 : 1; + __IO uint32_t FLTBK : 3; + __IO uint32_t BKP : 1; + __IO uint32_t FLTET : 3; + __IO uint32_t ETP : 1; +} stc_tim3_mode23_fltr_field_t; + +typedef struct +{ + __IO uint32_t UEVE : 1; + __IO uint32_t CMA0E : 1; + __IO uint32_t CMA1E : 1; + __IO uint32_t CMA2E : 1; + __IO uint32_t CMB0E : 1; + __IO uint32_t CMB1E : 1; + __IO uint32_t CMB2E : 1; + __IO uint32_t ADTE : 1; +} stc_tim3_mode23_adtr_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim3_mode23_crch0_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim3_mode23_crch1_field_t; + +typedef struct +{ + __IO uint32_t CFA_CRA_BKSA : 2; + __IO uint32_t CFB_CRB_BKSB : 2; + __IO uint32_t CSA : 1; + __IO uint32_t CSB : 1; + __IO uint32_t BUFEA : 1; + __IO uint32_t BUFEB : 1; + __IO uint32_t CIEA : 1; + __IO uint32_t CIEB : 1; + __IO uint32_t CDEA : 1; + __IO uint32_t CDEB : 1; + __IO uint32_t CISB : 2; + __IO uint32_t CCGA : 1; + __IO uint32_t CCGB : 1; +} stc_tim3_mode23_crch2_field_t; + +typedef struct +{ + __IO uint32_t DTR : 8; + __IO uint32_t BKSEL : 1; + __IO uint32_t DTEN : 1; + __IO uint32_t BKE : 1; + __IO uint32_t AOE : 1; + __IO uint32_t MOE : 1; + __IO uint32_t SAFEEN : 1; + __IO uint32_t VC0E : 1; + __IO uint32_t VC1E : 1; +} stc_tim3_mode23_dtr_field_t; + +typedef struct +{ + __IO uint32_t RCR : 8; +} stc_tim3_mode23_rcr_field_t; + +typedef struct +{ + __IO uint32_t ARRDM :16; +} stc_tim3_mode23_arrdm_field_t; + +typedef struct +{ + __IO uint32_t CCR0A :16; +} stc_tim3_mode23_ccr0a_field_t; + +typedef struct +{ + __IO uint32_t CCR0B :16; +} stc_tim3_mode23_ccr0b_field_t; + +typedef struct +{ + __IO uint32_t CCR1A :16; +} stc_tim3_mode23_ccr1a_field_t; + +typedef struct +{ + __IO uint32_t CCR1B :16; +} stc_tim3_mode23_ccr1b_field_t; + +typedef struct +{ + __IO uint32_t CCR2A :16; +} stc_tim3_mode23_ccr2a_field_t; + +typedef struct +{ + __IO uint32_t CCR2B :16; +} stc_tim3_mode23_ccr2b_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim4_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; +} stc_tim4_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; +} stc_tim4_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; +} stc_tim4_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; +} stc_tim4_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; +} stc_tim4_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; +} stc_tim4_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; +} stc_tim4_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; +} stc_tim4_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; +} stc_tim4_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; +} stc_tim4_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; +} stc_tim4_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; +} stc_tim4_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; +} stc_tim4_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; +} stc_tim4_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; +} stc_tim4_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; +} stc_tim4_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; +} stc_tim4_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tim4_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim4_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_tim4_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim4_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; +} stc_tim4_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; +} stc_tim4_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; +} stc_tim4_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; +} stc_tim4_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; +} stc_tim4_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; +} stc_tim4_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; +} stc_tim4_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; +} stc_tim4_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; +} stc_tim4_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; +} stc_tim4_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; +} stc_tim4_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; +} stc_tim4_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; +} stc_tim4_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; +} stc_tim4_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; +} stc_tim4_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; +} stc_tim4_sclrr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim5_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; +} stc_tim5_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; +} stc_tim5_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; +} stc_tim5_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; +} stc_tim5_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; +} stc_tim5_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; +} stc_tim5_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; +} stc_tim5_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; +} stc_tim5_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; +} stc_tim5_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; +} stc_tim5_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; +} stc_tim5_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; +} stc_tim5_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; +} stc_tim5_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; +} stc_tim5_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; +} stc_tim5_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; +} stc_tim5_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; +} stc_tim5_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tim5_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim5_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_tim5_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim5_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; +} stc_tim5_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; +} stc_tim5_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; +} stc_tim5_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; +} stc_tim5_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; +} stc_tim5_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; +} stc_tim5_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; +} stc_tim5_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; +} stc_tim5_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; +} stc_tim5_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; +} stc_tim5_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; +} stc_tim5_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; +} stc_tim5_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; +} stc_tim5_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; +} stc_tim5_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; +} stc_tim5_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; +} stc_tim5_sclrr_field_t; + +typedef struct +{ + __IO uint32_t CNT :16; +} stc_tim6_cnter_field_t; + +typedef struct +{ + __IO uint32_t PERA :16; +} stc_tim6_perar_field_t; + +typedef struct +{ + __IO uint32_t PERB :16; +} stc_tim6_perbr_field_t; + +typedef struct +{ + __IO uint32_t GCMA :16; +} stc_tim6_gcmar_field_t; + +typedef struct +{ + __IO uint32_t GCMB :16; +} stc_tim6_gcmbr_field_t; + +typedef struct +{ + __IO uint32_t GCMC :16; +} stc_tim6_gcmcr_field_t; + +typedef struct +{ + __IO uint32_t GCMD :16; +} stc_tim6_gcmdr_field_t; + +typedef struct +{ + __IO uint32_t SCMA :16; +} stc_tim6_scmar_field_t; + +typedef struct +{ + __IO uint32_t SCMB :16; +} stc_tim6_scmbr_field_t; + +typedef struct +{ + __IO uint32_t DTUA :16; +} stc_tim6_dtuar_field_t; + +typedef struct +{ + __IO uint32_t DTDA :16; +} stc_tim6_dtdar_field_t; + +typedef struct +{ + __IO uint32_t START : 1; + __IO uint32_t MODE : 3; + __IO uint32_t CKDIV : 3; + uint32_t RESERVED7 : 1; + __IO uint32_t DIR : 1; + uint32_t RESERVED9 : 7; + __IO uint32_t ZMSKREV : 1; + __IO uint32_t ZMSKPOS : 1; + __IO uint32_t ZMSK : 2; +} stc_tim6_gconr_field_t; + +typedef struct +{ + __IO uint32_t INTENA : 1; + __IO uint32_t INTENB : 1; + __IO uint32_t INTENC : 1; + __IO uint32_t INTEND : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t INTENOVF : 1; + __IO uint32_t INTENUDF : 1; + __IO uint32_t INTENDE : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t INTENSAML : 1; + __IO uint32_t INTENSAMH : 1; + __IO uint32_t INTENSAU : 1; + __IO uint32_t INTENSAD : 1; + __IO uint32_t INTENSBU : 1; + __IO uint32_t INTENSBD : 1; +} stc_tim6_iconr_field_t; + +typedef struct +{ + __IO uint32_t CAPCA : 1; + __IO uint32_t STACA : 1; + __IO uint32_t STPCA : 1; + __IO uint32_t STASTPSA : 1; + __IO uint32_t CMPCA : 2; + __IO uint32_t PERCA : 2; + __IO uint32_t OUTENA : 1; + __IO uint32_t DISSELA : 2; + __IO uint32_t DISVALA : 2; + uint32_t RESERVED13 : 3; + __IO uint32_t CAPCB : 1; + __IO uint32_t STACB : 1; + __IO uint32_t STPCB : 1; + __IO uint32_t STASTPSB : 1; + __IO uint32_t CMPCB : 2; + __IO uint32_t PERCB : 2; + __IO uint32_t OUTENB : 1; + __IO uint32_t DISSELB : 2; + __IO uint32_t DISVALB : 2; +} stc_tim6_pconr_field_t; + +typedef struct +{ + __IO uint32_t BENA : 1; + uint32_t RESERVED1 : 1; + __IO uint32_t BENB : 1; + uint32_t RESERVED3 : 5; + __IO uint32_t BENP : 1; +} stc_tim6_bconr_field_t; + +typedef struct +{ + __IO uint32_t DTCEN : 1; + uint32_t RESERVED1 : 7; + __IO uint32_t SEPA : 1; +} stc_tim6_dconr_field_t; + +typedef struct +{ + __IO uint32_t NOFIENGA : 1; + __IO uint32_t NOFICKGA : 2; + uint32_t RESERVED3 : 1; + __IO uint32_t NOFIENGB : 1; + __IO uint32_t NOFICKGB : 2; + uint32_t RESERVED7 : 9; + __IO uint32_t NOFIENTA : 1; + __IO uint32_t NOFICKTA : 2; + uint32_t RESERVED19 : 1; + __IO uint32_t NOFIENTB : 1; + __IO uint32_t NOFICKTB : 2; + uint32_t RESERVED23 : 1; + __IO uint32_t NOFIENTC : 1; + __IO uint32_t NOFICKTC : 2; + uint32_t RESERVED27 : 1; + __IO uint32_t NOFIENTD : 1; + __IO uint32_t NOFICKTD : 2; +} stc_tim6_fconr_field_t; + +typedef struct +{ + __IO uint32_t GEPERIA : 1; + __IO uint32_t GEPERIB : 1; + __IO uint32_t GEPERIC : 1; + __IO uint32_t GEPERID : 1; + uint32_t RESERVED4 :12; + __IO uint32_t PCNTE : 2; + __IO uint32_t PCNTS : 3; +} stc_tim6_vperr_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + __IO uint32_t CMSAUF : 1; + __IO uint32_t CMSADF : 1; + __IO uint32_t CMSBUF : 1; + __IO uint32_t CMSBDF : 1; + uint32_t RESERVED13 : 8; + __IO uint32_t VPERNUM : 3; + uint32_t RESERVED24 : 7; + __IO uint32_t DIRF : 1; +} stc_tim6_stflr_field_t; + +typedef struct +{ + __IO uint32_t HSTA0 : 1; + __IO uint32_t HSTA1 : 1; + __IO uint32_t HSTA2 : 1; + __IO uint32_t HSTA3 : 1; + __IO uint32_t HSTA4 : 1; + __IO uint32_t HSTA5 : 1; + __IO uint32_t HSTA6 : 1; + __IO uint32_t HSTA7 : 1; + __IO uint32_t HSTA8 : 1; + __IO uint32_t HSTA9 : 1; + __IO uint32_t HSTA10 : 1; + __IO uint32_t HSTA11 : 1; + __IO uint32_t HSTA12 : 1; + __IO uint32_t HSTA13 : 1; + __IO uint32_t HSTA14 : 1; + __IO uint32_t HSTA15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim6_hstar_field_t; + +typedef struct +{ + __IO uint32_t HSTP0 : 1; + __IO uint32_t HSTP1 : 1; + __IO uint32_t HSTP2 : 1; + __IO uint32_t HSTP3 : 1; + __IO uint32_t HSTP4 : 1; + __IO uint32_t HSTP5 : 1; + __IO uint32_t HSTP6 : 1; + __IO uint32_t HSTP7 : 1; + __IO uint32_t HSTP8 : 1; + __IO uint32_t HSTP9 : 1; + __IO uint32_t HSTP10 : 1; + __IO uint32_t HSTP11 : 1; + __IO uint32_t HSTP12 : 1; + __IO uint32_t HSTP13 : 1; + __IO uint32_t HSTP14 : 1; + __IO uint32_t HSTP15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STOPS : 1; +} stc_tim6_hstpr_field_t; + +typedef struct +{ + __IO uint32_t HCEL0 : 1; + __IO uint32_t HCEL1 : 1; + __IO uint32_t HCEL2 : 1; + __IO uint32_t HCEL3 : 1; + __IO uint32_t HCEL4 : 1; + __IO uint32_t HCEL5 : 1; + __IO uint32_t HCEL6 : 1; + __IO uint32_t HCEL7 : 1; + __IO uint32_t HCEL8 : 1; + __IO uint32_t HCEL9 : 1; + __IO uint32_t HCEL10 : 1; + __IO uint32_t HCEL11 : 1; + __IO uint32_t HCEL12 : 1; + __IO uint32_t HCEL13 : 1; + __IO uint32_t HCEL14 : 1; + __IO uint32_t HCEL15 : 1; + uint32_t RESERVED16 :15; + __IO uint32_t STARTS : 1; +} stc_tim6_hcelr_field_t; + +typedef struct +{ + __IO uint32_t HCPA0 : 1; + __IO uint32_t HCPA1 : 1; + __IO uint32_t HCPA2 : 1; + __IO uint32_t HCPA3 : 1; + __IO uint32_t HCPA4 : 1; + __IO uint32_t HCPA5 : 1; + __IO uint32_t HCPA6 : 1; + __IO uint32_t HCPA7 : 1; + __IO uint32_t HCPA8 : 1; + __IO uint32_t HCPA9 : 1; + __IO uint32_t HCPA10 : 1; + __IO uint32_t HCPA11 : 1; + __IO uint32_t HCPA12 : 1; + __IO uint32_t HCPA13 : 1; + __IO uint32_t HCPA14 : 1; + __IO uint32_t HCPA15 : 1; +} stc_tim6_hcpar_field_t; + +typedef struct +{ + __IO uint32_t HCPB0 : 1; + __IO uint32_t HCPB1 : 1; + __IO uint32_t HCPB2 : 1; + __IO uint32_t HCPB3 : 1; + __IO uint32_t HCPB4 : 1; + __IO uint32_t HCPB5 : 1; + __IO uint32_t HCPB6 : 1; + __IO uint32_t HCPB7 : 1; + __IO uint32_t HCPB8 : 1; + __IO uint32_t HCPB9 : 1; + __IO uint32_t HCPB10 : 1; + __IO uint32_t HCPB11 : 1; + __IO uint32_t HCPB12 : 1; + __IO uint32_t HCPB13 : 1; + __IO uint32_t HCPB14 : 1; + __IO uint32_t HCPB15 : 1; +} stc_tim6_hcpbr_field_t; + +typedef struct +{ + __IO uint32_t HCUP0 : 1; + __IO uint32_t HCUP1 : 1; + __IO uint32_t HCUP2 : 1; + __IO uint32_t HCUP3 : 1; + __IO uint32_t HCUP4 : 1; + __IO uint32_t HCUP5 : 1; + __IO uint32_t HCUP6 : 1; + __IO uint32_t HCUP7 : 1; + __IO uint32_t HCUP8 : 1; + __IO uint32_t HCUP9 : 1; + __IO uint32_t HCUP10 : 1; + __IO uint32_t HCUP11 : 1; + __IO uint32_t HCUP12 : 1; + __IO uint32_t HCUP13 : 1; + __IO uint32_t HCUP14 : 1; + __IO uint32_t HCUP15 : 1; + __IO uint32_t HCUP16 : 1; + __IO uint32_t HCUP17 : 1; + __IO uint32_t HCUP18 : 1; + __IO uint32_t HCUP19 : 1; +} stc_tim6_hcupr_field_t; + +typedef struct +{ + __IO uint32_t HCDO0 : 1; + __IO uint32_t HCDO1 : 1; + __IO uint32_t HCDO2 : 1; + __IO uint32_t HCDO3 : 1; + __IO uint32_t HCDO4 : 1; + __IO uint32_t HCDO5 : 1; + __IO uint32_t HCDO6 : 1; + __IO uint32_t HCDO7 : 1; + __IO uint32_t HCDO8 : 1; + __IO uint32_t HCDO9 : 1; + __IO uint32_t HCDO10 : 1; + __IO uint32_t HCDO11 : 1; + __IO uint32_t HCDO12 : 1; + __IO uint32_t HCDO13 : 1; + __IO uint32_t HCDO14 : 1; + __IO uint32_t HCDO15 : 1; + __IO uint32_t HCDO16 : 1; + __IO uint32_t HCDO17 : 1; + __IO uint32_t HCDO18 : 1; + __IO uint32_t HCDO19 : 1; +} stc_tim6_hcdor_field_t; + +typedef struct +{ + __IO uint32_t CMAF : 1; + __IO uint32_t CMBF : 1; + __IO uint32_t CMCF : 1; + __IO uint32_t CMDF : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFF : 1; + __IO uint32_t UDFF : 1; + __IO uint32_t DTEF : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLF : 1; + __IO uint32_t SAMHF : 1; +} stc_tim6_ifr_field_t; + +typedef struct +{ + __IO uint32_t CMAC : 1; + __IO uint32_t CMBC : 1; + __IO uint32_t CMCC : 1; + __IO uint32_t CMDC : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFC : 1; + __IO uint32_t UDFC : 1; + __IO uint32_t DTEC : 1; + uint32_t RESERVED9 : 5; + __IO uint32_t SAMLC : 1; + __IO uint32_t SAMHC : 1; +} stc_tim6_iclr_field_t; + +typedef struct +{ + __IO uint32_t CMAE : 1; + __IO uint32_t CMBE : 1; + __IO uint32_t CMCE : 1; + __IO uint32_t CMDE : 1; + uint32_t RESERVED4 : 2; + __IO uint32_t OVFE : 1; + __IO uint32_t UDFE : 1; + __IO uint32_t DITENA : 1; + __IO uint32_t DITENB : 1; + __IO uint32_t DITENS : 1; + __IO uint32_t CMSAE : 1; + __IO uint32_t CMSBE : 1; + __IO uint32_t DMA_G_CMA : 1; + __IO uint32_t DMA_G_CMB : 1; + __IO uint32_t DMA_G_CMC : 1; + __IO uint32_t DMA_G_CMD : 1; + uint32_t RESERVED17 : 2; + __IO uint32_t DMA_G_OVF : 1; + __IO uint32_t DMA_G_UDF : 1; + __IO uint32_t DMA_S_CMA : 1; + __IO uint32_t DMA_S_CMB : 1; +} stc_tim6_cr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; + __IO uint32_t BFILTS : 2; + __IO uint32_t BFILTEN : 1; + uint32_t RESERVED5 : 2; + __IO uint32_t SOFTBK : 1; + __IO uint32_t SML0 : 1; + __IO uint32_t SML1 : 1; + __IO uint32_t SML2 : 1; + __IO uint32_t SMH0 : 1; + __IO uint32_t SMH1 : 1; + __IO uint32_t SMH2 : 1; +} stc_tim6_aossr_field_t; + +typedef struct +{ + __IO uint32_t FBRAKE : 1; + __IO uint32_t FSAME : 1; +} stc_tim6_aoscl_field_t; + +typedef struct +{ + __IO uint32_t EN0 : 1; + __IO uint32_t EN1 : 1; + __IO uint32_t EN2 : 1; + __IO uint32_t EN3 : 1; + __IO uint32_t EN4 : 1; + __IO uint32_t EN5 : 1; + __IO uint32_t EN6 : 1; + __IO uint32_t EN7 : 1; + __IO uint32_t EN8 : 1; + __IO uint32_t EN9 : 1; + __IO uint32_t EN10 : 1; + __IO uint32_t EN11 : 1; + __IO uint32_t EN12 : 1; + __IO uint32_t EN13 : 1; + __IO uint32_t EN14 : 1; + __IO uint32_t EN15 : 1; +} stc_tim6_ptbks_field_t; + +typedef struct +{ + __IO uint32_t TRIGAS : 4; + __IO uint32_t TRIGBS : 4; + __IO uint32_t TRIGCS : 4; + __IO uint32_t TRIGDS : 4; +} stc_tim6_ttrig_field_t; + +typedef struct +{ + __IO uint32_t IAOS0S : 4; + __IO uint32_t IAOS1S : 4; + __IO uint32_t IAOS2S : 4; + __IO uint32_t IAOS3S : 4; +} stc_tim6_itrig_field_t; + +typedef struct +{ + __IO uint32_t POL0 : 1; + __IO uint32_t POL1 : 1; + __IO uint32_t POL2 : 1; + __IO uint32_t POL3 : 1; + __IO uint32_t POL4 : 1; + __IO uint32_t POL5 : 1; + __IO uint32_t POL6 : 1; + __IO uint32_t POL7 : 1; + __IO uint32_t POL8 : 1; + __IO uint32_t POL9 : 1; + __IO uint32_t POL10 : 1; + __IO uint32_t POL11 : 1; + __IO uint32_t POL12 : 1; + __IO uint32_t POL13 : 1; + __IO uint32_t POL14 : 1; + __IO uint32_t POL15 : 1; +} stc_tim6_ptbkp_field_t; + +typedef struct +{ + __IO uint32_t SSTA0 : 1; + __IO uint32_t SSTA1 : 1; + __IO uint32_t SSTA2 : 1; +} stc_tim6_sstar_field_t; + +typedef struct +{ + __IO uint32_t SSTP0 : 1; + __IO uint32_t SSTP1 : 1; + __IO uint32_t SSTP2 : 1; +} stc_tim6_sstpr_field_t; + +typedef struct +{ + __IO uint32_t SCLR0 : 1; + __IO uint32_t SCLR1 : 1; + __IO uint32_t SCLR2 : 1; +} stc_tim6_sclrr_field_t; + +typedef struct +{ + __IO uint32_t DATA : 8; + __IO uint32_t DATA8 : 1; +} stc_uart_sbuf_field_t; + +typedef struct +{ + __IO uint32_t RCIE : 1; + __IO uint32_t TCIE : 1; + __IO uint32_t B8CONT : 2; + __IO uint32_t REN : 1; + __IO uint32_t ADRDET : 1; + __IO uint32_t SM : 2; + __IO uint32_t TXEIE : 1; + __IO uint32_t OVER : 1; + uint32_t RESERVED10 : 3; + __IO uint32_t PEIE : 1; + __IO uint32_t STOPBIT : 2; + __IO uint32_t DMARXEN : 1; + __IO uint32_t DMATXEN : 1; + __IO uint32_t RTSEN : 1; + __IO uint32_t CTSEN : 1; + __IO uint32_t CTSIE : 1; + __IO uint32_t FEIE : 1; +} stc_uart_scon_field_t; + +typedef struct +{ + __IO uint32_t SADDR : 8; +} stc_uart_saddr_field_t; + +typedef struct +{ + __IO uint32_t SADEN : 8; +} stc_uart_saden_field_t; + +typedef struct +{ + __IO uint32_t RC : 1; + __IO uint32_t TC : 1; + __IO uint32_t FE : 1; + __IO uint32_t TXE : 1; + __IO uint32_t PE : 1; + __IO uint32_t CTSIF : 1; + __IO uint32_t CTS : 1; +} stc_uart_isr_field_t; + +typedef struct +{ + __IO uint32_t RCCF : 1; + __IO uint32_t TCCF : 1; + __IO uint32_t FECF : 1; + uint32_t RESERVED3 : 1; + __IO uint32_t PECF : 1; + __IO uint32_t CTSIFCF : 1; +} stc_uart_icr_field_t; + +typedef struct +{ + __IO uint32_t SCNT :16; +} stc_uart_scnt_field_t; + +typedef struct +{ + __IO uint32_t DIV : 6; + __IO uint32_t DIV_EN : 1; + __IO uint32_t REF2P5_SEL : 1; + __IO uint32_t VC0_BIAS_SEL : 2; + __IO uint32_t VC0_HYS_SEL : 2; + __IO uint32_t VC1_BIAS_SEL : 2; + __IO uint32_t VC1_HYS_SEL : 2; +} stc_vc_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; +} stc_vc_vc0_cr_field_t; + +typedef struct +{ + __IO uint32_t P_SEL : 4; + __IO uint32_t N_SEL : 4; + __IO uint32_t FLTEN : 1; + __IO uint32_t DEBOUNCE_TIME : 3; + __IO uint32_t FALLING : 1; + __IO uint32_t RISING : 1; + __IO uint32_t LEVEL : 1; + __IO uint32_t IE : 1; + __IO uint32_t EN : 1; +} stc_vc_vc1_cr_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; +} stc_vc_vc0_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t INV_TIMER : 1; + __IO uint32_t TIM0RCLR : 1; + __IO uint32_t TIM1RCLR : 1; + __IO uint32_t TIM2RCLR : 1; + __IO uint32_t TIM3RCLR : 1; + __IO uint32_t TIMBK : 1; + uint32_t RESERVED6 : 3; + __IO uint32_t INV_TIM4 : 1; + __IO uint32_t TIM4 : 1; + __IO uint32_t INV_TIM5 : 1; + __IO uint32_t TIM5 : 1; + __IO uint32_t INV_TIM6 : 1; + __IO uint32_t TIM6 : 1; + __IO uint32_t BRAKE : 1; +} stc_vc_vc1_out_cfg_field_t; + +typedef struct +{ + __IO uint32_t VC0_INTF : 1; + __IO uint32_t VC1_INTF : 1; + __IO uint32_t VC0_FILTER : 1; + __IO uint32_t VC1_FILTER : 1; +} stc_vc_ifr_field_t; + +typedef struct +{ + __IO uint32_t RST : 8; +} stc_wdt_rst_field_t; + +typedef struct +{ + __IO uint32_t WOV : 4; + __IO uint32_t WDTR : 1; + __IO uint32_t WINT_EN : 1; + uint32_t RESERVED6 : 1; + __IO uint32_t WDINT : 1; + __IO uint32_t WCNTL : 8; +} stc_wdt_con_field_t; + + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CR0; + stc_adc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_adc_cr1_field_t CR1_f; + }; + uint8_t RESERVED2[52]; + union + { + __IO uint32_t SQR0; + stc_adc_sqr0_field_t SQR0_f; + }; + union + { + __IO uint32_t SQR1; + stc_adc_sqr1_field_t SQR1_f; + }; + union + { + __IO uint32_t SQR2; + stc_adc_sqr2_field_t SQR2_f; + }; + union + { + __IO uint32_t JQR; + stc_adc_jqr_field_t JQR_f; + }; + union + { + __IO uint32_t SQRRESULT0; + stc_adc_sqrresult0_field_t SQRRESULT0_f; + }; + union + { + __IO uint32_t SQRRESULT1; + stc_adc_sqrresult1_field_t SQRRESULT1_f; + }; + union + { + __IO uint32_t SQRRESULT2; + stc_adc_sqrresult2_field_t SQRRESULT2_f; + }; + union + { + __IO uint32_t SQRRESULT3; + stc_adc_sqrresult3_field_t SQRRESULT3_f; + }; + union + { + __IO uint32_t SQRRESULT4; + stc_adc_sqrresult4_field_t SQRRESULT4_f; + }; + union + { + __IO uint32_t SQRRESULT5; + stc_adc_sqrresult5_field_t SQRRESULT5_f; + }; + union + { + __IO uint32_t SQRRESULT6; + stc_adc_sqrresult6_field_t SQRRESULT6_f; + }; + union + { + __IO uint32_t SQRRESULT7; + stc_adc_sqrresult7_field_t SQRRESULT7_f; + }; + union + { + __IO uint32_t SQRRESULT8; + stc_adc_sqrresult8_field_t SQRRESULT8_f; + }; + union + { + __IO uint32_t SQRRESULT9; + stc_adc_sqrresult9_field_t SQRRESULT9_f; + }; + union + { + __IO uint32_t SQRRESULT10; + stc_adc_sqrresult10_field_t SQRRESULT10_f; + }; + union + { + __IO uint32_t SQRRESULT11; + stc_adc_sqrresult11_field_t SQRRESULT11_f; + }; + union + { + __IO uint32_t SQRRESULT12; + stc_adc_sqrresult12_field_t SQRRESULT12_f; + }; + union + { + __IO uint32_t SQR_RESULT13; + stc_adc_sqr_result13_field_t SQR_RESULT13_f; + }; + union + { + __IO uint32_t SQRRESULT14; + stc_adc_sqrresult14_field_t SQRRESULT14_f; + }; + union + { + __IO uint32_t SQRRESULT15; + stc_adc_sqrresult15_field_t SQRRESULT15_f; + }; + union + { + __IO uint32_t JQRRESULT0; + stc_adc_jqrresult0_field_t JQRRESULT0_f; + }; + union + { + __IO uint32_t JQRRESULT1; + stc_adc_jqrresult1_field_t JQRRESULT1_f; + }; + union + { + __IO uint32_t JQRRESULT2; + stc_adc_jqrresult2_field_t JQRRESULT2_f; + }; + union + { + __IO uint32_t JQRRESULT3; + stc_adc_jqrresult3_field_t JQRRESULT3_f; + }; + union + { + __IO uint32_t RESULT; + stc_adc_result_field_t RESULT_f; + }; + union + { + __IO uint32_t RESULTACC; + stc_adc_resultacc_field_t RESULTACC_f; + }; + union + { + __IO uint32_t HT; + stc_adc_ht_field_t HT_f; + }; + union + { + __IO uint32_t LT; + stc_adc_lt_field_t LT_f; + }; + union + { + __IO uint32_t IFR; + stc_adc_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICR; + stc_adc_icr_field_t ICR_f; + }; + union + { + __IO uint32_t EXTTRIGGER0; + stc_adc_exttrigger0_field_t EXTTRIGGER0_f; + }; + union + { + __IO uint32_t EXTTRIGGER1; + stc_adc_exttrigger1_field_t EXTTRIGGER1_f; + }; + union + { + __IO uint32_t SGLSTART; + stc_adc_sglstart_field_t SGLSTART_f; + }; + union + { + __IO uint32_t SQRSTART; + stc_adc_sqrstart_field_t SQRSTART_f; + }; + union + { + __IO uint32_t JQRSTART; + stc_adc_jqrstart_field_t JQRSTART_f; + }; +}M0P_ADC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_aes_cr_field_t CR_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t DATA0; + stc_aes_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_aes_data1_field_t DATA1_f; + }; + union + { + __IO uint32_t DATA2; + stc_aes_data2_field_t DATA2_f; + }; + union + { + __IO uint32_t DATA3; + stc_aes_data3_field_t DATA3_f; + }; + union + { + __IO uint32_t KEY0; + stc_aes_key0_field_t KEY0_f; + }; + union + { + __IO uint32_t KEY1; + stc_aes_key1_field_t KEY1_f; + }; + union + { + __IO uint32_t KEY2; + stc_aes_key2_field_t KEY2_f; + }; + union + { + __IO uint32_t KEY3; + stc_aes_key3_field_t KEY3_f; + }; +}M0P_AES_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_bgr_cr_field_t CR_f; + }; +}M0P_BGR_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_clk_trim_cr_field_t CR_f; + }; + union + { + __IO uint32_t REFCON; + stc_clk_trim_refcon_field_t REFCON_f; + }; + union + { + __IO uint32_t REFCNT; + stc_clk_trim_refcnt_field_t REFCNT_f; + }; + union + { + __IO uint32_t CALCNT; + stc_clk_trim_calcnt_field_t CALCNT_f; + }; + union + { + __IO uint32_t IFR; + stc_clk_trim_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_clk_trim_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CALCON; + stc_clk_trim_calcon_field_t CALCON_f; + }; +}M0P_CLK_TRIM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_crc_cr_field_t CR_f; + }; + union + { + __IO uint32_t RESULT; + stc_crc_result_field_t RESULT_f; + }; + uint8_t RESERVED2[120]; + union + { + __IO uint32_t DATA; + stc_crc_data_field_t DATA_f; + }; +}M0P_CRC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t DEBUG_ACTIVE; + stc_debug_active_field_t DEBUG_ACTIVE_f; + }; +}M0P_DEBUG_ACTIVE_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CONF; + stc_dmac_conf_field_t CONF_f; + }; + uint8_t RESERVED1[12]; + union + { + __IO uint32_t CONFA0; + stc_dmac_confa0_field_t CONFA0_f; + }; + union + { + __IO uint32_t CONFB0; + stc_dmac_confb0_field_t CONFB0_f; + }; + union + { + __IO uint32_t SRCADR0; + stc_dmac_srcadr0_field_t SRCADR0_f; + }; + union + { + __IO uint32_t DSTADR0; + stc_dmac_dstadr0_field_t DSTADR0_f; + }; + union + { + __IO uint32_t CONFA1; + stc_dmac_confa1_field_t CONFA1_f; + }; + union + { + __IO uint32_t CONFB1; + stc_dmac_confb1_field_t CONFB1_f; + }; + union + { + __IO uint32_t SRCADR1; + stc_dmac_srcadr1_field_t SRCADR1_f; + }; + union + { + __IO uint32_t DSTADR1; + stc_dmac_dstadr1_field_t DSTADR1_f; + }; +}M0P_DMAC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TNVS; + stc_flash_tnvs_field_t TNVS_f; + }; + union + { + __IO uint32_t TPGS; + stc_flash_tpgs_field_t TPGS_f; + }; + union + { + __IO uint32_t TPROG; + stc_flash_tprog_field_t TPROG_f; + }; + union + { + __IO uint32_t TSERASE; + stc_flash_tserase_field_t TSERASE_f; + }; + union + { + __IO uint32_t TMERASE; + stc_flash_tmerase_field_t TMERASE_f; + }; + union + { + __IO uint32_t TPRCV; + stc_flash_tprcv_field_t TPRCV_f; + }; + union + { + __IO uint32_t TSRCV; + stc_flash_tsrcv_field_t TSRCV_f; + }; + union + { + __IO uint32_t TMRCV; + stc_flash_tmrcv_field_t TMRCV_f; + }; + union + { + __IO uint32_t CR; + stc_flash_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_flash_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_flash_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t BYPASS; + stc_flash_bypass_field_t BYPASS_f; + }; + union + { + __IO uint32_t SLOCK; + stc_flash_slock_field_t SLOCK_f; + }; +}M0P_FLASH_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t PA00_SEL; + stc_gpio_pa00_sel_field_t PA00_SEL_f; + }; + union + { + __IO uint32_t PA01_SEL; + stc_gpio_pa01_sel_field_t PA01_SEL_f; + }; + union + { + __IO uint32_t PA02_SEL; + stc_gpio_pa02_sel_field_t PA02_SEL_f; + }; + union + { + __IO uint32_t PA03_SEL; + stc_gpio_pa03_sel_field_t PA03_SEL_f; + }; + union + { + __IO uint32_t PA04_SEL; + stc_gpio_pa04_sel_field_t PA04_SEL_f; + }; + union + { + __IO uint32_t PA05_SEL; + stc_gpio_pa05_sel_field_t PA05_SEL_f; + }; + union + { + __IO uint32_t PA06_SEL; + stc_gpio_pa06_sel_field_t PA06_SEL_f; + }; + union + { + __IO uint32_t PA07_SEL; + stc_gpio_pa07_sel_field_t PA07_SEL_f; + }; + union + { + __IO uint32_t PA08_SEL; + stc_gpio_pa08_sel_field_t PA08_SEL_f; + }; + union + { + __IO uint32_t PA09_SEL; + stc_gpio_pa09_sel_field_t PA09_SEL_f; + }; + union + { + __IO uint32_t PA10_SEL; + stc_gpio_pa10_sel_field_t PA10_SEL_f; + }; + union + { + __IO uint32_t PA11_SEL; + stc_gpio_pa11_sel_field_t PA11_SEL_f; + }; + union + { + __IO uint32_t PA12_SEL; + stc_gpio_pa12_sel_field_t PA12_SEL_f; + }; + union + { + __IO uint32_t PA13_SEL; + stc_gpio_pa13_sel_field_t PA13_SEL_f; + }; + union + { + __IO uint32_t PA14_SEL; + stc_gpio_pa14_sel_field_t PA14_SEL_f; + }; + union + { + __IO uint32_t PA15_SEL; + stc_gpio_pa15_sel_field_t PA15_SEL_f; + }; + union + { + __IO uint32_t PB00_SEL; + stc_gpio_pb00_sel_field_t PB00_SEL_f; + }; + union + { + __IO uint32_t PB01_SEL; + stc_gpio_pb01_sel_field_t PB01_SEL_f; + }; + union + { + __IO uint32_t PB02_SEL; + stc_gpio_pb02_sel_field_t PB02_SEL_f; + }; + union + { + __IO uint32_t PB03_SEL; + stc_gpio_pb03_sel_field_t PB03_SEL_f; + }; + union + { + __IO uint32_t PB04_SEL; + stc_gpio_pb04_sel_field_t PB04_SEL_f; + }; + union + { + __IO uint32_t PB05_SEL; + stc_gpio_pb05_sel_field_t PB05_SEL_f; + }; + union + { + __IO uint32_t PB06_SEL; + stc_gpio_pb06_sel_field_t PB06_SEL_f; + }; + union + { + __IO uint32_t PB07_SEL; + stc_gpio_pb07_sel_field_t PB07_SEL_f; + }; + union + { + __IO uint32_t PB08_SEL; + stc_gpio_pb08_sel_field_t PB08_SEL_f; + }; + union + { + __IO uint32_t PB09_SEL; + stc_gpio_pb09_sel_field_t PB09_SEL_f; + }; + union + { + __IO uint32_t PB10_SEL; + stc_gpio_pb10_sel_field_t PB10_SEL_f; + }; + union + { + __IO uint32_t PB11_SEL; + stc_gpio_pb11_sel_field_t PB11_SEL_f; + }; + union + { + __IO uint32_t PB12_SEL; + stc_gpio_pb12_sel_field_t PB12_SEL_f; + }; + union + { + __IO uint32_t PB13_SEL; + stc_gpio_pb13_sel_field_t PB13_SEL_f; + }; + union + { + __IO uint32_t PB14_SEL; + stc_gpio_pb14_sel_field_t PB14_SEL_f; + }; + union + { + __IO uint32_t PB15_SEL; + stc_gpio_pb15_sel_field_t PB15_SEL_f; + }; + union + { + __IO uint32_t PC00_SEL; + stc_gpio_pc00_sel_field_t PC00_SEL_f; + }; + union + { + __IO uint32_t PC01_SEL; + stc_gpio_pc01_sel_field_t PC01_SEL_f; + }; + union + { + __IO uint32_t PC02_SEL; + stc_gpio_pc02_sel_field_t PC02_SEL_f; + }; + union + { + __IO uint32_t PC03_SEL; + stc_gpio_pc03_sel_field_t PC03_SEL_f; + }; + union + { + __IO uint32_t PC04_SEL; + stc_gpio_pc04_sel_field_t PC04_SEL_f; + }; + union + { + __IO uint32_t PC05_SEL; + stc_gpio_pc05_sel_field_t PC05_SEL_f; + }; + union + { + __IO uint32_t PC06_SEL; + stc_gpio_pc06_sel_field_t PC06_SEL_f; + }; + union + { + __IO uint32_t PC07_SEL; + stc_gpio_pc07_sel_field_t PC07_SEL_f; + }; + union + { + __IO uint32_t PC08_SEL; + stc_gpio_pc08_sel_field_t PC08_SEL_f; + }; + union + { + __IO uint32_t PC09_SEL; + stc_gpio_pc09_sel_field_t PC09_SEL_f; + }; + union + { + __IO uint32_t PC10_SEL; + stc_gpio_pc10_sel_field_t PC10_SEL_f; + }; + union + { + __IO uint32_t PC11_SEL; + stc_gpio_pc11_sel_field_t PC11_SEL_f; + }; + union + { + __IO uint32_t PC12_SEL; + stc_gpio_pc12_sel_field_t PC12_SEL_f; + }; + union + { + __IO uint32_t PC13_SEL; + stc_gpio_pc13_sel_field_t PC13_SEL_f; + }; + union + { + __IO uint32_t PC14_SEL; + stc_gpio_pc14_sel_field_t PC14_SEL_f; + }; + union + { + __IO uint32_t PC15_SEL; + stc_gpio_pc15_sel_field_t PC15_SEL_f; + }; + union + { + __IO uint32_t PD00_SEL; + stc_gpio_pd00_sel_field_t PD00_SEL_f; + }; + union + { + __IO uint32_t PD01_SEL; + stc_gpio_pd01_sel_field_t PD01_SEL_f; + }; + union + { + __IO uint32_t PD02_SEL; + stc_gpio_pd02_sel_field_t PD02_SEL_f; + }; + union + { + __IO uint32_t PD03_SEL; + stc_gpio_pd03_sel_field_t PD03_SEL_f; + }; + union + { + __IO uint32_t PD04_SEL; + stc_gpio_pd04_sel_field_t PD04_SEL_f; + }; + union + { + __IO uint32_t PD05_SEL; + stc_gpio_pd05_sel_field_t PD05_SEL_f; + }; + union + { + __IO uint32_t PD06_SEL; + stc_gpio_pd06_sel_field_t PD06_SEL_f; + }; + union + { + __IO uint32_t PD07_SEL; + stc_gpio_pd07_sel_field_t PD07_SEL_f; + }; + uint8_t RESERVED56[32]; + union + { + __IO uint32_t PADIR; + stc_gpio_padir_field_t PADIR_f; + }; + union + { + __IO uint32_t PAIN; + stc_gpio_pain_field_t PAIN_f; + }; + union + { + __IO uint32_t PAOUT; + stc_gpio_paout_field_t PAOUT_f; + }; + union + { + __IO uint32_t PAADS; + stc_gpio_paads_field_t PAADS_f; + }; + union + { + __IO uint32_t PABSET; + stc_gpio_pabset_field_t PABSET_f; + }; + union + { + __IO uint32_t PABCLR; + stc_gpio_pabclr_field_t PABCLR_f; + }; + union + { + __IO uint32_t PABSETCLR; + stc_gpio_pabsetclr_field_t PABSETCLR_f; + }; + union + { + __IO uint32_t PADR; + stc_gpio_padr_field_t PADR_f; + }; + union + { + __IO uint32_t PAPU; + stc_gpio_papu_field_t PAPU_f; + }; + union + { + __IO uint32_t PAPD; + stc_gpio_papd_field_t PAPD_f; + }; + uint8_t RESERVED66[4]; + union + { + __IO uint32_t PAOD; + stc_gpio_paod_field_t PAOD_f; + }; + union + { + __IO uint32_t PAHIE; + stc_gpio_pahie_field_t PAHIE_f; + }; + union + { + __IO uint32_t PALIE; + stc_gpio_palie_field_t PALIE_f; + }; + union + { + __IO uint32_t PARIE; + stc_gpio_parie_field_t PARIE_f; + }; + union + { + __IO uint32_t PAFIE; + stc_gpio_pafie_field_t PAFIE_f; + }; + union + { + __IO uint32_t PBDIR; + stc_gpio_pbdir_field_t PBDIR_f; + }; + union + { + __IO uint32_t PBIN; + stc_gpio_pbin_field_t PBIN_f; + }; + union + { + __IO uint32_t PBOUT; + stc_gpio_pbout_field_t PBOUT_f; + }; + union + { + __IO uint32_t PBADS; + stc_gpio_pbads_field_t PBADS_f; + }; + union + { + __IO uint32_t PBBSET; + stc_gpio_pbbset_field_t PBBSET_f; + }; + union + { + __IO uint32_t PBBCLR; + stc_gpio_pbbclr_field_t PBBCLR_f; + }; + union + { + __IO uint32_t PBBSETCLR; + stc_gpio_pbbsetclr_field_t PBBSETCLR_f; + }; + union + { + __IO uint32_t PBDR; + stc_gpio_pbdr_field_t PBDR_f; + }; + union + { + __IO uint32_t PBPU; + stc_gpio_pbpu_field_t PBPU_f; + }; + union + { + __IO uint32_t PBPD; + stc_gpio_pbpd_field_t PBPD_f; + }; + uint8_t RESERVED81[4]; + union + { + __IO uint32_t PBOD; + stc_gpio_pbod_field_t PBOD_f; + }; + union + { + __IO uint32_t PBHIE; + stc_gpio_pbhie_field_t PBHIE_f; + }; + union + { + __IO uint32_t PBLIE; + stc_gpio_pblie_field_t PBLIE_f; + }; + union + { + __IO uint32_t PBRIE; + stc_gpio_pbrie_field_t PBRIE_f; + }; + union + { + __IO uint32_t PBFIE; + stc_gpio_pbfie_field_t PBFIE_f; + }; + union + { + __IO uint32_t PCDIR; + stc_gpio_pcdir_field_t PCDIR_f; + }; + union + { + __IO uint32_t PCIN; + stc_gpio_pcin_field_t PCIN_f; + }; + union + { + __IO uint32_t PCOUT; + stc_gpio_pcout_field_t PCOUT_f; + }; + union + { + __IO uint32_t PCADS; + stc_gpio_pcads_field_t PCADS_f; + }; + union + { + __IO uint32_t PCBSET; + stc_gpio_pcbset_field_t PCBSET_f; + }; + union + { + __IO uint32_t PCBCLR; + stc_gpio_pcbclr_field_t PCBCLR_f; + }; + union + { + __IO uint32_t PCBSETCLR; + stc_gpio_pcbsetclr_field_t PCBSETCLR_f; + }; + union + { + __IO uint32_t PCDR; + stc_gpio_pcdr_field_t PCDR_f; + }; + union + { + __IO uint32_t PCPU; + stc_gpio_pcpu_field_t PCPU_f; + }; + union + { + __IO uint32_t PCPD; + stc_gpio_pcpd_field_t PCPD_f; + }; + uint8_t RESERVED96[4]; + union + { + __IO uint32_t PCOD; + stc_gpio_pcod_field_t PCOD_f; + }; + union + { + __IO uint32_t PCHIE; + stc_gpio_pchie_field_t PCHIE_f; + }; + union + { + __IO uint32_t PCLIE; + stc_gpio_pclie_field_t PCLIE_f; + }; + union + { + __IO uint32_t PCRIE; + stc_gpio_pcrie_field_t PCRIE_f; + }; + union + { + __IO uint32_t PCFIE; + stc_gpio_pcfie_field_t PCFIE_f; + }; + union + { + __IO uint32_t PDDIR; + stc_gpio_pddir_field_t PDDIR_f; + }; + union + { + __IO uint32_t PDIN; + stc_gpio_pdin_field_t PDIN_f; + }; + union + { + __IO uint32_t PDOUT; + stc_gpio_pdout_field_t PDOUT_f; + }; + union + { + __IO uint32_t PDADS; + stc_gpio_pdads_field_t PDADS_f; + }; + union + { + __IO uint32_t PDBSET; + stc_gpio_pdbset_field_t PDBSET_f; + }; + union + { + __IO uint32_t PDBCLR; + stc_gpio_pdbclr_field_t PDBCLR_f; + }; + union + { + __IO uint32_t PDBSETCLR; + stc_gpio_pdbsetclr_field_t PDBSETCLR_f; + }; + union + { + __IO uint32_t PDDR; + stc_gpio_pddr_field_t PDDR_f; + }; + union + { + __IO uint32_t PDPU; + stc_gpio_pdpu_field_t PDPU_f; + }; + union + { + __IO uint32_t PDPD; + stc_gpio_pdpd_field_t PDPD_f; + }; + uint8_t RESERVED111[4]; + union + { + __IO uint32_t PDOD; + stc_gpio_pdod_field_t PDOD_f; + }; + union + { + __IO uint32_t PDHIE; + stc_gpio_pdhie_field_t PDHIE_f; + }; + union + { + __IO uint32_t PDLIE; + stc_gpio_pdlie_field_t PDLIE_f; + }; + union + { + __IO uint32_t PDRIE; + stc_gpio_pdrie_field_t PDRIE_f; + }; + union + { + __IO uint32_t PDFIE; + stc_gpio_pdfie_field_t PDFIE_f; + }; + union + { + __IO uint32_t PA_STAT; + stc_gpio_pa_stat_field_t PA_STAT_f; + }; + uint8_t RESERVED117[12]; + union + { + __IO uint32_t PA_ICLR; + stc_gpio_pa_iclr_field_t PA_ICLR_f; + }; + uint8_t RESERVED118[44]; + union + { + __IO uint32_t PB_STAT; + stc_gpio_pb_stat_field_t PB_STAT_f; + }; + uint8_t RESERVED119[12]; + union + { + __IO uint32_t PB_ICLR; + stc_gpio_pb_iclr_field_t PB_ICLR_f; + }; + uint8_t RESERVED120[44]; + union + { + __IO uint32_t PC_STAT; + stc_gpio_pc_stat_field_t PC_STAT_f; + }; + uint8_t RESERVED121[12]; + union + { + __IO uint32_t PC_ICLR; + stc_gpio_pc_iclr_field_t PC_ICLR_f; + }; + uint8_t RESERVED122[44]; + union + { + __IO uint32_t PD_STAT; + stc_gpio_pd_stat_field_t PD_STAT_f; + }; + uint8_t RESERVED123[12]; + union + { + __IO uint32_t PD_ICLR; + stc_gpio_pd_iclr_field_t PD_ICLR_f; + }; + uint8_t RESERVED124[44]; + union + { + __IO uint32_t CTRL0; + stc_gpio_ctrl0_field_t CTRL0_f; + }; + union + { + __IO uint32_t CTRL1; + stc_gpio_ctrl1_field_t CTRL1_f; + }; + union + { + __IO uint32_t CTRL2; + stc_gpio_ctrl2_field_t CTRL2_f; + }; + union + { + __IO uint32_t TIMGS; + stc_gpio_timgs_field_t TIMGS_f; + }; + union + { + __IO uint32_t TIMES; + stc_gpio_times_field_t TIMES_f; + }; + union + { + __IO uint32_t TIMCPS; + stc_gpio_timcps_field_t TIMCPS_f; + }; + union + { + __IO uint32_t PCAS; + stc_gpio_pcas_field_t PCAS_f; + }; +}M0P_GPIO_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t DIVIDEND; + stc_hdiv_dividend_field_t DIVIDEND_f; + }; + union + { + __IO uint32_t DIVISOR; + stc_hdiv_divisor_field_t DIVISOR_f; + }; + union + { + __IO uint32_t QUOTIENT; + stc_hdiv_quotient_field_t QUOTIENT_f; + }; + union + { + __IO uint32_t REMAINDER; + stc_hdiv_remainder_field_t REMAINDER_f; + }; + union + { + __IO uint32_t SIGN; + stc_hdiv_sign_field_t SIGN_f; + }; + union + { + __IO uint32_t STAT; + stc_hdiv_stat_field_t STAT_f; + }; +}M0P_HDIV_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t TMRUN; + stc_i2c_tmrun_field_t TMRUN_f; + }; + union + { + __IO uint32_t TM; + stc_i2c_tm_field_t TM_f; + }; + union + { + __IO uint32_t CR; + stc_i2c_cr_field_t CR_f; + }; + union + { + __IO uint32_t DATA; + stc_i2c_data_field_t DATA_f; + }; + union + { + __IO uint32_t ADDR; + stc_i2c_addr_field_t ADDR_f; + }; + union + { + __IO uint32_t STAT; + stc_i2c_stat_field_t STAT_f; + }; +}M0P_I2C_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_lcd_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_lcd_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t INTCLR; + stc_lcd_intclr_field_t INTCLR_f; + }; + union + { + __IO uint32_t POEN0; + stc_lcd_poen0_field_t POEN0_f; + }; + union + { + __IO uint32_t POEN1; + stc_lcd_poen1_field_t POEN1_f; + }; + uint8_t RESERVED5[44]; + union + { + __IO uint32_t RAM0; + stc_lcd_ram0_field_t RAM0_f; + }; + union + { + __IO uint32_t RAM1; + stc_lcd_ram1_field_t RAM1_f; + }; + union + { + __IO uint32_t RAM2; + stc_lcd_ram2_field_t RAM2_f; + }; + union + { + __IO uint32_t RAM3; + stc_lcd_ram3_field_t RAM3_f; + }; + union + { + __IO uint32_t RAM4; + stc_lcd_ram4_field_t RAM4_f; + }; + union + { + __IO uint32_t RAM5; + stc_lcd_ram5_field_t RAM5_f; + }; + union + { + __IO uint32_t RAM6; + stc_lcd_ram6_field_t RAM6_f; + }; + union + { + __IO uint32_t RAM7; + stc_lcd_ram7_field_t RAM7_f; + }; + union + { + __IO uint32_t RAM8; + stc_lcd_ram8_field_t RAM8_f; + }; + union + { + __IO uint32_t RAM9; + stc_lcd_ram9_field_t RAM9_f; + }; + union + { + __IO uint32_t RAMA; + stc_lcd_rama_field_t RAMA_f; + }; + union + { + __IO uint32_t RAMB; + stc_lcd_ramb_field_t RAMB_f; + }; + union + { + __IO uint32_t RAMC; + stc_lcd_ramc_field_t RAMC_f; + }; + union + { + __IO uint32_t RAMD; + stc_lcd_ramd_field_t RAMD_f; + }; + union + { + __IO uint32_t RAME; + stc_lcd_rame_field_t RAME_f; + }; + union + { + __IO uint32_t RAMF; + stc_lcd_ramf_field_t RAMF_f; + }; +}M0P_LCD_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNT; + stc_lptimer_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ARR; + stc_lptimer_arr_field_t ARR_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t CR; + stc_lptimer_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lptimer_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_lptimer_iclr_field_t ICLR_f; + }; +}M0P_LPTIMER_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_lpuart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_lpuart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_lpuart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_lpuart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_lpuart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_lpuart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_lpuart_scnt_field_t SCNT_f; + }; +}M0P_LPUART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[40]; + union + { + __IO uint32_t CR; + stc_lvd_cr_field_t CR_f; + }; + union + { + __IO uint32_t IFR; + stc_lvd_ifr_field_t IFR_f; + }; +}M0P_LVD_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[48]; + union + { + __IO uint32_t CR0; + stc_opa_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_opa_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t CR2; + stc_opa_cr2_field_t CR2_f; + }; + union + { + __IO uint8_t CR; + stc_opa_cr_field_t CR_f; + }; +}M0P_OPA_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CCON; + stc_pca_ccon_field_t CCON_f; + }; + union + { + __IO uint32_t CMOD; + stc_pca_cmod_field_t CMOD_f; + }; + union + { + __IO uint32_t CNT; + stc_pca_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t ICLR; + stc_pca_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CCAPM0; + stc_pca_ccapm0_field_t CCAPM0_f; + }; + union + { + __IO uint32_t CCAPM1; + stc_pca_ccapm1_field_t CCAPM1_f; + }; + union + { + __IO uint32_t CCAPM2; + stc_pca_ccapm2_field_t CCAPM2_f; + }; + union + { + __IO uint32_t CCAPM3; + stc_pca_ccapm3_field_t CCAPM3_f; + }; + union + { + __IO uint32_t CCAPM4; + stc_pca_ccapm4_field_t CCAPM4_f; + }; + union + { + __IO uint32_t CCAP0H; + stc_pca_ccap0h_field_t CCAP0H_f; + }; + union + { + __IO uint32_t CCAP0L; + stc_pca_ccap0l_field_t CCAP0L_f; + }; + union + { + __IO uint32_t CCAP1H; + stc_pca_ccap1h_field_t CCAP1H_f; + }; + union + { + __IO uint32_t CCAP1L; + stc_pca_ccap1l_field_t CCAP1L_f; + }; + union + { + __IO uint32_t CCAP2H; + stc_pca_ccap2h_field_t CCAP2H_f; + }; + union + { + __IO uint32_t CCAP2L; + stc_pca_ccap2l_field_t CCAP2L_f; + }; + union + { + __IO uint32_t CCAP3H; + stc_pca_ccap3h_field_t CCAP3H_f; + }; + union + { + __IO uint32_t CCAP3L; + stc_pca_ccap3l_field_t CCAP3L_f; + }; + union + { + __IO uint32_t CCAP4H; + stc_pca_ccap4h_field_t CCAP4H_f; + }; + union + { + __IO uint32_t CCAP4L; + stc_pca_ccap4l_field_t CCAP4L_f; + }; + union + { + __IO uint32_t CCAPO; + stc_pca_ccapo_field_t CCAPO_f; + }; + union + { + __IO uint32_t CCAP0; + stc_pca_ccap0_field_t CCAP0_f; + }; + union + { + __IO uint32_t CCAP1; + stc_pca_ccap1_field_t CCAP1_f; + }; + union + { + __IO uint32_t CCAP2; + stc_pca_ccap2_field_t CCAP2_f; + }; + union + { + __IO uint32_t CCAP3; + stc_pca_ccap3_field_t CCAP3_f; + }; + union + { + __IO uint32_t CCAP4; + stc_pca_ccap4_field_t CCAP4_f; + }; + union + { + __IO uint32_t CARR; + stc_pca_carr_field_t CARR_f; + }; + union + { + __IO uint32_t EPWM; + stc_pca_epwm_field_t EPWM_f; + }; +}M0P_PCA_TypeDef; + +typedef struct +{ + union + { + __IO uint8_t RUN; + stc_pcnt_run_field_t RUN_f; + }; + uint8_t RESERVED1[3]; + union + { + __IO uint8_t CR; + stc_pcnt_cr_field_t CR_f; + }; + uint8_t RESERVED2[3]; + union + { + __IO uint32_t FLT; + stc_pcnt_flt_field_t FLT_f; + }; + union + { + __IO uint32_t TOCR; + stc_pcnt_tocr_field_t TOCR_f; + }; + union + { + __IO uint8_t CMD; + stc_pcnt_cmd_field_t CMD_f; + }; + uint8_t RESERVED5[3]; + union + { + __IO uint8_t SR1; + stc_pcnt_sr1_field_t SR1_f; + }; + uint8_t RESERVED6[3]; + union + { + __IO uint16_t CNT; + stc_pcnt_cnt_field_t CNT_f; + }; + uint8_t RESERVED7[2]; + union + { + __IO uint16_t TOP; + stc_pcnt_top_field_t TOP_f; + }; + uint8_t RESERVED8[2]; + union + { + __IO uint16_t BUF; + stc_pcnt_buf_field_t BUF_f; + }; + uint8_t RESERVED9[2]; + union + { + __IO uint8_t IFR; + stc_pcnt_ifr_field_t IFR_f; + }; + uint8_t RESERVED10[3]; + union + { + __IO uint8_t ICR; + stc_pcnt_icr_field_t ICR_f; + }; + uint8_t RESERVED11[3]; + union + { + __IO uint8_t IEN; + stc_pcnt_ien_field_t IEN_f; + }; + uint8_t RESERVED12[3]; + union + { + __IO uint8_t SR2; + stc_pcnt_sr2_field_t SR2_f; + }; +}M0P_PCNT_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_ram_cr_field_t CR_f; + }; + union + { + __IO uint32_t ERRADDR; + stc_ram_erraddr_field_t ERRADDR_f; + }; + union + { + __IO uint32_t IFR; + stc_ram_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_ram_iclr_field_t ICLR_f; + }; +}M0P_RAM_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t RESET_FLAG; + stc_reset_flag_field_t RESET_FLAG_f; + }; + uint8_t RESERVED1[8]; + union + { + __IO uint32_t PREI_RESET; + stc_reset_prei_field_t PREI_RESET_f; + }; +}M0P_RESET_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_rng_cr_field_t CR_f; + }; + union + { + __IO uint32_t MODE; + stc_rng_mode_field_t MODE_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t DATA0; + stc_rng_data0_field_t DATA0_f; + }; + union + { + __IO uint32_t DATA1; + stc_rng_data1_field_t DATA1_f; + }; +}M0P_RNG_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR0; + stc_rtc_cr0_field_t CR0_f; + }; + union + { + __IO uint32_t CR1; + stc_rtc_cr1_field_t CR1_f; + }; + union + { + __IO uint32_t SEC; + stc_rtc_sec_field_t SEC_f; + }; + union + { + __IO uint32_t MIN; + stc_rtc_min_field_t MIN_f; + }; + union + { + __IO uint32_t HOUR; + stc_rtc_hour_field_t HOUR_f; + }; + union + { + __IO uint32_t WEEK; + stc_rtc_week_field_t WEEK_f; + }; + union + { + __IO uint32_t DAY; + stc_rtc_day_field_t DAY_f; + }; + union + { + __IO uint32_t MON; + stc_rtc_mon_field_t MON_f; + }; + union + { + __IO uint32_t YEAR; + stc_rtc_year_field_t YEAR_f; + }; + union + { + __IO uint32_t ALMMIN; + stc_rtc_almmin_field_t ALMMIN_f; + }; + union + { + __IO uint32_t ALMHOUR; + stc_rtc_almhour_field_t ALMHOUR_f; + }; + union + { + __IO uint32_t ALMWEEK; + stc_rtc_almweek_field_t ALMWEEK_f; + }; + union + { + __IO uint32_t COMPEN; + stc_rtc_compen_field_t COMPEN_f; + }; +}M0P_RTC_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CR; + stc_spi_cr_field_t CR_f; + }; + union + { + __IO uint32_t SSN; + stc_spi_ssn_field_t SSN_f; + }; + union + { + __IO uint32_t STAT; + stc_spi_stat_field_t STAT_f; + }; + union + { + __IO uint32_t DATA; + stc_spi_data_field_t DATA_f; + }; + union + { + __IO uint32_t CR2; + stc_spi_cr2_field_t CR2_f; + }; + union + { + __IO uint32_t ICLR; + stc_spi_iclr_field_t ICLR_f; + }; +}M0P_SPI_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SYSCTRL0; + stc_sysctrl_sysctrl0_field_t SYSCTRL0_f; + }; + union + { + __IO uint32_t SYSCTRL1; + stc_sysctrl_sysctrl1_field_t SYSCTRL1_f; + }; + union + { + __IO uint32_t SYSCTRL2; + stc_sysctrl_sysctrl2_field_t SYSCTRL2_f; + }; + union + { + __IO uint32_t RCH_CR; + stc_sysctrl_rch_cr_field_t RCH_CR_f; + }; + union + { + __IO uint32_t XTH_CR; + stc_sysctrl_xth_cr_field_t XTH_CR_f; + }; + union + { + __IO uint32_t RCL_CR; + stc_sysctrl_rcl_cr_field_t RCL_CR_f; + }; + union + { + __IO uint32_t XTL_CR; + stc_sysctrl_xtl_cr_field_t XTL_CR_f; + }; + uint8_t RESERVED7[4]; + union + { + __IO uint32_t PERI_CLKEN; + stc_sysctrl_peri_clken_field_t PERI_CLKEN_f; + }; + uint8_t RESERVED8[24]; + union + { + __IO uint32_t PLL_CR; + stc_sysctrl_pll_cr_field_t PLL_CR_f; + }; +}M0P_SYSCTRL_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim0_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim0_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim0_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM0_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim0_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim0_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim0_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM0_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim0_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim0_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim0_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim0_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim0_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim0_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim0_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim0_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim0_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim0_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim0_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim0_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim0_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim0_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM0_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim1_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim1_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim1_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM1_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim1_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim1_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim1_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM1_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim1_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim1_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim1_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim1_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim1_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim1_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim1_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim1_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim1_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim1_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim1_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim1_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim1_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim1_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM1_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim2_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim2_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim2_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM2_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim2_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim2_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim2_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM2_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim2_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim2_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim2_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim2_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim2_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim2_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim2_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim2_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim2_mode23_crch0_field_t CRCH0_f; + }; + uint8_t RESERVED9[8]; + union + { + __IO uint32_t DTR; + stc_tim2_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim2_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim2_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim2_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim2_mode23_ccr0b_field_t CCR0B_f; + }; +}M0P_TIM2_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode0_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode0_cnt_field_t CNT_f; + }; + union + { + __IO uint32_t CNT32; + stc_tim3_mode0_cnt32_field_t CNT32_f; + }; + union + { + __IO uint32_t M0CR; + stc_tim3_mode0_m0cr_field_t M0CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode0_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode0_iclr_field_t ICLR_f; + }; + uint8_t RESERVED6[24]; + union + { + __IO uint32_t DTR; + stc_tim3_mode0_dtr_field_t DTR_f; + }; +}M0P_TIM3_MODE0_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[4]; + union + { + __IO uint32_t CNT; + stc_tim3_mode1_cnt_field_t CNT_f; + }; + uint8_t RESERVED1[4]; + union + { + __IO uint32_t M1CR; + stc_tim3_mode1_m1cr_field_t M1CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode1_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode1_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode1_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode1_fltr_field_t FLTR_f; + }; + uint8_t RESERVED6[4]; + union + { + __IO uint32_t CR0; + stc_tim3_mode1_cr0_field_t CR0_f; + }; + uint8_t RESERVED7[20]; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode1_ccr0a_field_t CCR0A_f; + }; +}M0P_TIM3_MODE1_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t ARR; + stc_tim3_mode23_arr_field_t ARR_f; + }; + union + { + __IO uint32_t CNT; + stc_tim3_mode23_cnt_field_t CNT_f; + }; + uint8_t RESERVED2[4]; + union + { + __IO uint32_t M23CR; + stc_tim3_mode23_m23cr_field_t M23CR_f; + }; + union + { + __IO uint32_t IFR; + stc_tim3_mode23_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim3_mode23_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t MSCR; + stc_tim3_mode23_mscr_field_t MSCR_f; + }; + union + { + __IO uint32_t FLTR; + stc_tim3_mode23_fltr_field_t FLTR_f; + }; + union + { + __IO uint32_t ADTR; + stc_tim3_mode23_adtr_field_t ADTR_f; + }; + union + { + __IO uint32_t CRCH0; + stc_tim3_mode23_crch0_field_t CRCH0_f; + }; + union + { + __IO uint32_t CRCH1; + stc_tim3_mode23_crch1_field_t CRCH1_f; + }; + union + { + __IO uint32_t CRCH2; + stc_tim3_mode23_crch2_field_t CRCH2_f; + }; + union + { + __IO uint32_t DTR; + stc_tim3_mode23_dtr_field_t DTR_f; + }; + union + { + __IO uint32_t RCR; + stc_tim3_mode23_rcr_field_t RCR_f; + }; + union + { + __IO uint32_t ARRDM; + stc_tim3_mode23_arrdm_field_t ARRDM_f; + }; + union + { + __IO uint32_t CCR0A; + stc_tim3_mode23_ccr0a_field_t CCR0A_f; + }; + union + { + __IO uint32_t CCR0B; + stc_tim3_mode23_ccr0b_field_t CCR0B_f; + }; + union + { + __IO uint32_t CCR1A; + stc_tim3_mode23_ccr1a_field_t CCR1A_f; + }; + union + { + __IO uint32_t CCR1B; + stc_tim3_mode23_ccr1b_field_t CCR1B_f; + }; + union + { + __IO uint32_t CCR2A; + stc_tim3_mode23_ccr2a_field_t CCR2A_f; + }; + union + { + __IO uint32_t CCR2B; + stc_tim3_mode23_ccr2b_field_t CCR2B_f; + }; +}M0P_TIM3_MODE23_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tim4_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tim4_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tim4_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_tim4_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tim4_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tim4_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tim4_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_tim4_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tim4_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_tim4_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tim4_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_tim4_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tim4_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tim4_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tim4_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tim4_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_tim4_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tim4_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tim4_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tim4_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tim4_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_tim4_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tim4_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tim4_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tim4_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tim4_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_tim4_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim4_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_tim4_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_tim4_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_tim4_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_tim4_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_tim4_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_tim4_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_tim4_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_tim4_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tim4_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tim4_sclrr_field_t SCLRR_f; + }; +}M0P_TIM4_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tim5_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tim5_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tim5_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_tim5_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tim5_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tim5_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tim5_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_tim5_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tim5_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_tim5_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tim5_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_tim5_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tim5_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tim5_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tim5_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tim5_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_tim5_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tim5_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tim5_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tim5_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tim5_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_tim5_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tim5_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tim5_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tim5_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tim5_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_tim5_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim5_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_tim5_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_tim5_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_tim5_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_tim5_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_tim5_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_tim5_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_tim5_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_tim5_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tim5_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tim5_sclrr_field_t SCLRR_f; + }; +}M0P_TIM5_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t CNTER; + stc_tim6_cnter_field_t CNTER_f; + }; + union + { + __IO uint32_t PERAR; + stc_tim6_perar_field_t PERAR_f; + }; + union + { + __IO uint32_t PERBR; + stc_tim6_perbr_field_t PERBR_f; + }; + uint8_t RESERVED3[4]; + union + { + __IO uint32_t GCMAR; + stc_tim6_gcmar_field_t GCMAR_f; + }; + union + { + __IO uint32_t GCMBR; + stc_tim6_gcmbr_field_t GCMBR_f; + }; + union + { + __IO uint32_t GCMCR; + stc_tim6_gcmcr_field_t GCMCR_f; + }; + union + { + __IO uint32_t GCMDR; + stc_tim6_gcmdr_field_t GCMDR_f; + }; + uint8_t RESERVED7[8]; + union + { + __IO uint32_t SCMAR; + stc_tim6_scmar_field_t SCMAR_f; + }; + union + { + __IO uint32_t SCMBR; + stc_tim6_scmbr_field_t SCMBR_f; + }; + uint8_t RESERVED9[16]; + union + { + __IO uint32_t DTUAR; + stc_tim6_dtuar_field_t DTUAR_f; + }; + union + { + __IO uint32_t DTDAR; + stc_tim6_dtdar_field_t DTDAR_f; + }; + uint8_t RESERVED11[8]; + union + { + __IO uint32_t GCONR; + stc_tim6_gconr_field_t GCONR_f; + }; + union + { + __IO uint32_t ICONR; + stc_tim6_iconr_field_t ICONR_f; + }; + union + { + __IO uint32_t PCONR; + stc_tim6_pconr_field_t PCONR_f; + }; + union + { + __IO uint32_t BCONR; + stc_tim6_bconr_field_t BCONR_f; + }; + union + { + __IO uint32_t DCONR; + stc_tim6_dconr_field_t DCONR_f; + }; + uint8_t RESERVED16[4]; + union + { + __IO uint32_t FCONR; + stc_tim6_fconr_field_t FCONR_f; + }; + union + { + __IO uint32_t VPERR; + stc_tim6_vperr_field_t VPERR_f; + }; + union + { + __IO uint32_t STFLR; + stc_tim6_stflr_field_t STFLR_f; + }; + union + { + __IO uint32_t HSTAR; + stc_tim6_hstar_field_t HSTAR_f; + }; + union + { + __IO uint32_t HSTPR; + stc_tim6_hstpr_field_t HSTPR_f; + }; + union + { + __IO uint32_t HCELR; + stc_tim6_hcelr_field_t HCELR_f; + }; + union + { + __IO uint32_t HCPAR; + stc_tim6_hcpar_field_t HCPAR_f; + }; + union + { + __IO uint32_t HCPBR; + stc_tim6_hcpbr_field_t HCPBR_f; + }; + union + { + __IO uint32_t HCUPR; + stc_tim6_hcupr_field_t HCUPR_f; + }; + union + { + __IO uint32_t HCDOR; + stc_tim6_hcdor_field_t HCDOR_f; + }; + uint8_t RESERVED26[112]; + union + { + __IO uint32_t IFR; + stc_tim6_ifr_field_t IFR_f; + }; + union + { + __IO uint32_t ICLR; + stc_tim6_iclr_field_t ICLR_f; + }; + union + { + __IO uint32_t CR; + stc_tim6_cr_field_t CR_f; + }; + uint8_t RESERVED29[4]; + union + { + __IO uint32_t AOSSR; + stc_tim6_aossr_field_t AOSSR_f; + }; + union + { + __IO uint32_t AOSCL; + stc_tim6_aoscl_field_t AOSCL_f; + }; + union + { + __IO uint32_t PTBKS; + stc_tim6_ptbks_field_t PTBKS_f; + }; + union + { + __IO uint32_t TTRIG; + stc_tim6_ttrig_field_t TTRIG_f; + }; + union + { + __IO uint32_t ITRIG; + stc_tim6_itrig_field_t ITRIG_f; + }; + union + { + __IO uint32_t PTBKP; + stc_tim6_ptbkp_field_t PTBKP_f; + }; + uint8_t RESERVED35[716]; + union + { + __IO uint32_t SSTAR; + stc_tim6_sstar_field_t SSTAR_f; + }; + union + { + __IO uint32_t SSTPR; + stc_tim6_sstpr_field_t SSTPR_f; + }; + union + { + __IO uint32_t SCLRR; + stc_tim6_sclrr_field_t SCLRR_f; + }; +}M0P_TIM6_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t SBUF; + stc_uart_sbuf_field_t SBUF_f; + }; + union + { + __IO uint32_t SCON; + stc_uart_scon_field_t SCON_f; + }; + union + { + __IO uint32_t SADDR; + stc_uart_saddr_field_t SADDR_f; + }; + union + { + __IO uint32_t SADEN; + stc_uart_saden_field_t SADEN_f; + }; + union + { + __IO uint32_t ISR; + stc_uart_isr_field_t ISR_f; + }; + union + { + __IO uint32_t ICR; + stc_uart_icr_field_t ICR_f; + }; + union + { + __IO uint32_t SCNT; + stc_uart_scnt_field_t SCNT_f; + }; +}M0P_UART_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[16]; + union + { + __IO uint32_t CR; + stc_vc_cr_field_t CR_f; + }; + union + { + __IO uint32_t VC0_CR; + stc_vc_vc0_cr_field_t VC0_CR_f; + }; + union + { + __IO uint32_t VC1_CR; + stc_vc_vc1_cr_field_t VC1_CR_f; + }; + union + { + __IO uint32_t VC0_OUT_CFG; + stc_vc_vc0_out_cfg_field_t VC0_OUT_CFG_f; + }; + union + { + __IO uint32_t VC1_OUT_CFG; + stc_vc_vc1_out_cfg_field_t VC1_OUT_CFG_f; + }; + union + { + __IO uint32_t IFR; + stc_vc_ifr_field_t IFR_f; + }; +}M0P_VC_TypeDef; + +typedef struct +{ + uint8_t RESERVED0[128]; + union + { + __IO uint32_t RST; + stc_wdt_rst_field_t RST_f; + }; + union + { + __IO uint32_t CON; + stc_wdt_con_field_t CON_f; + }; +}M0P_WDT_TypeDef; + + + +#define M0P_PERIPH_BASE (0x40000000UL) +#define M0P_ADC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_AES_BASE (M0P_PERIPH_BASE + 0x00021400UL) +#define M0P_BGR_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_CLK_TRIM_BASE (M0P_PERIPH_BASE + 0x00001800UL) +#define M0P_CRC_BASE (M0P_PERIPH_BASE + 0x00020900UL) +#define M0P_DEBUG_ACTIVE_BASE (M0P_PERIPH_BASE + 0x00002438UL) +#define M0P_DMAC_BASE (M0P_PERIPH_BASE + 0x00021000UL) +#define M0P_FLASH_BASE (M0P_PERIPH_BASE + 0x00020000UL) +#define M0P_GPIO_BASE (M0P_PERIPH_BASE + 0x00020C00UL) +#define M0P_HDIV_BASE (M0P_PERIPH_BASE + 0x00021800UL) +#define M0P_I2C0_BASE (M0P_PERIPH_BASE + 0x00000400UL) +#define M0P_I2C1_BASE (M0P_PERIPH_BASE + 0x00004400UL) +#define M0P_LCD_BASE (M0P_PERIPH_BASE + 0x00005C00UL) +#define M0P_LPTIMER_BASE (M0P_PERIPH_BASE + 0x00000F00UL) +#define M0P_LPUART0_BASE (M0P_PERIPH_BASE + 0x00000200UL) +#define M0P_LPUART1_BASE (M0P_PERIPH_BASE + 0x00004000UL) +#define M0P_LVD_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_OPA_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_PCA_BASE (M0P_PERIPH_BASE + 0x00001000UL) +#define M0P_PCNT_BASE (M0P_PERIPH_BASE + 0x00005400UL) +#define M0P_RAM_BASE (M0P_PERIPH_BASE + 0x00020400UL) +#define M0P_RESET_BASE (M0P_PERIPH_BASE + 0x0000201CUL) +#define M0P_RNG_BASE (M0P_PERIPH_BASE + 0x00004C00UL) +#define M0P_RTC_BASE (M0P_PERIPH_BASE + 0x00001400UL) +#define M0P_SPI0_BASE (M0P_PERIPH_BASE + 0x00000800UL) +#define M0P_SPI1_BASE (M0P_PERIPH_BASE + 0x00004800UL) +#define M0P_SYSCTRL_BASE (M0P_PERIPH_BASE + 0x00002000UL) +#define M0P_TIM0_MODE0_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE1_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM0_MODE23_BASE (M0P_PERIPH_BASE + 0x00000C00UL) +#define M0P_TIM1_MODE0_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE1_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM1_MODE23_BASE (M0P_PERIPH_BASE + 0x00000D00UL) +#define M0P_TIM2_MODE0_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE1_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM2_MODE23_BASE (M0P_PERIPH_BASE + 0x00000E00UL) +#define M0P_TIM3_MODE0_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE1_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM3_MODE23_BASE (M0P_PERIPH_BASE + 0x00005800UL) +#define M0P_TIM4_BASE (M0P_PERIPH_BASE + 0x00003000UL) +#define M0P_TIM5_BASE (M0P_PERIPH_BASE + 0x00003400UL) +#define M0P_TIM6_BASE (M0P_PERIPH_BASE + 0x00003800UL) +#define M0P_UART0_BASE (M0P_PERIPH_BASE + 0x00000000UL) +#define M0P_UART1_BASE (M0P_PERIPH_BASE + 0x00000100UL) +#define M0P_VC_BASE (M0P_PERIPH_BASE + 0x00002400UL) +#define M0P_WDT_BASE (M0P_PERIPH_BASE + 0x00000F00UL) + + +#define M0P_ADC ((M0P_ADC_TypeDef *)0x40002400UL) +#define M0P_AES ((M0P_AES_TypeDef *)0x40021400UL) +#define M0P_BGR ((M0P_BGR_TypeDef *)0x40002400UL) +#define M0P_CLK_TRIM ((M0P_CLK_TRIM_TypeDef *)0x40001800UL) +#define M0P_CRC ((M0P_CRC_TypeDef *)0x40020900UL) +#define M0P_DEBUG_ACTIVE ((M0P_DEBUG_ACTIVE_TypeDef *)0x40002438UL) +#define M0P_DMAC ((M0P_DMAC_TypeDef *)0x40021000UL) +#define M0P_FLASH ((M0P_FLASH_TypeDef *)0x40020000UL) +#define M0P_GPIO ((M0P_GPIO_TypeDef *)0x40020C00UL) +#define M0P_HDIV ((M0P_HDIV_TypeDef *)0x40021800UL) +#define M0P_I2C0 ((M0P_I2C_TypeDef *)0x40000400UL) +#define M0P_I2C1 ((M0P_I2C_TypeDef *)0x40004400UL) +#define M0P_LCD ((M0P_LCD_TypeDef *)0x40005C00UL) +#define M0P_LPTIMER ((M0P_LPTIMER_TypeDef *)0x40000F00UL) +#define M0P_LPUART0 ((M0P_LPUART_TypeDef *)0x40000200UL) +#define M0P_LPUART1 ((M0P_LPUART_TypeDef *)0x40004000UL) +#define M0P_LVD ((M0P_LVD_TypeDef *)0x40002400UL) +#define M0P_OPA ((M0P_OPA_TypeDef *)0x40002400UL) +#define M0P_PCA ((M0P_PCA_TypeDef *)0x40001000UL) +#define M0P_PCNT ((M0P_PCNT_TypeDef *)0x40005400UL) +#define M0P_RAM ((M0P_RAM_TypeDef *)0x40020400UL) +#define M0P_RESET ((M0P_RESET_TypeDef *)0x4000201CUL) +#define M0P_RNG ((M0P_RNG_TypeDef *)0x40004C00UL) +#define M0P_RTC ((M0P_RTC_TypeDef *)0x40001400UL) +#define M0P_SPI0 ((M0P_SPI_TypeDef *)0x40000800UL) +#define M0P_SPI1 ((M0P_SPI_TypeDef *)0x40004800UL) +#define M0P_SYSCTRL ((M0P_SYSCTRL_TypeDef *)0x40002000UL) +#define M0P_TIM0_MODE0 ((M0P_TIM0_MODE0_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE1 ((M0P_TIM0_MODE1_TypeDef *)0x40000C00UL) +#define M0P_TIM0_MODE23 ((M0P_TIM0_MODE23_TypeDef *)0x40000C00UL) +#define M0P_TIM1_MODE0 ((M0P_TIM1_MODE0_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE1 ((M0P_TIM1_MODE1_TypeDef *)0x40000D00UL) +#define M0P_TIM1_MODE23 ((M0P_TIM1_MODE23_TypeDef *)0x40000D00UL) +#define M0P_TIM2_MODE0 ((M0P_TIM2_MODE0_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE1 ((M0P_TIM2_MODE1_TypeDef *)0x40000E00UL) +#define M0P_TIM2_MODE23 ((M0P_TIM2_MODE23_TypeDef *)0x40000E00UL) +#define M0P_TIM3_MODE0 ((M0P_TIM3_MODE0_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE1 ((M0P_TIM3_MODE1_TypeDef *)0x40005800UL) +#define M0P_TIM3_MODE23 ((M0P_TIM3_MODE23_TypeDef *)0x40005800UL) +#define M0P_TIM4 ((M0P_TIM4_TypeDef *)0x40003000UL) +#define M0P_TIM5 ((M0P_TIM5_TypeDef *)0x40003400UL) +#define M0P_TIM6 ((M0P_TIM6_TypeDef *)0x40003800UL) +#define M0P_UART0 ((M0P_UART_TypeDef *)0x40000000UL) +#define M0P_UART1 ((M0P_UART_TypeDef *)0x40000100UL) +#define M0P_VC ((M0P_VC_TypeDef *)0x40002400UL) +#define M0P_WDT ((M0P_WDT_TypeDef *)0x40000F00UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32L136_H__ */ + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l136.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l136.h new file mode 100644 index 0000000000..708eee7dbd --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l136.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l136.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L136_H__ +#define __SYSTEM_HC32L136_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + + + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L136_H__ */ + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l13x.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l13x.h new file mode 100644 index 0000000000..53575aee59 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Include/system_hc32l13x.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l13x.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L13X_H__ +#define __SYSTEM_HC32L13X_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + + + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L13X_H__ */ + + + + + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s new file mode 100644 index 0000000000..f066d81363 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s @@ -0,0 +1,294 @@ +;/****************************************************************************** +;* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +;* +;* This software is owned and published by: +;* Huada Semiconductor Co.,Ltd ("HDSC"). +;* +;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +;* +;* This software contains source code for use with HDSC +;* components. This software is licensed by HDSC to be adapted only +;* for use in systems utilizing HDSC components. HDSC shall not be +;* responsible for misuse or illegal use of this software for devices not +;* supported herein. HDSC is providing this software "AS IS" and will +;* not be responsible for issues arising from incorrect user implementation +;* of the software. +;* +;* Disclaimer: +;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +;* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +;* WARRANTY OF NONINFRINGEMENT. +;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +;* SAVINGS OR PROFITS, +;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +;* FROM, THE SOFTWARE. +;* +;* This software may be replicated in part or whole for the licensed use, +;* with the restriction that this Disclaimer and Copyright notice must be +;* included with each copy of this software, whether used in part or whole, +;* at all times. +;*/ +;/*****************************************************************************/ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2018-04-15 */ +;/* Target-mcu {HC32L136} */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + + DCD IRQ000_Handler ; + DCD IRQ001_Handler ; + DCD IRQ002_Handler ; + DCD IRQ003_Handler ; + DCD IRQ004_Handler ; + DCD IRQ005_Handler ; + DCD IRQ006_Handler ; + DCD IRQ007_Handler ; + DCD IRQ008_Handler ; + DCD IRQ009_Handler ; + DCD IRQ010_Handler ; + DCD IRQ011_Handler ; + DCD IRQ012_Handler ; + DCD IRQ013_Handler ; + DCD IRQ014_Handler ; + DCD IRQ015_Handler ; + DCD IRQ016_Handler ; + DCD IRQ017_Handler ; + DCD IRQ018_Handler ; + DCD IRQ019_Handler ; + DCD IRQ020_Handler ; + DCD IRQ021_Handler ; + DCD IRQ022_Handler ; + DCD IRQ023_Handler ; + DCD IRQ024_Handler ; + DCD IRQ025_Handler ; + DCD IRQ026_Handler ; + DCD IRQ027_Handler ; + DCD IRQ028_Handler ; + DCD IRQ029_Handler ; + DCD IRQ030_Handler ; + DCD IRQ031_Handler ; + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 + MOVS R1, #0 ; for warning, + ADD R1, PC,#0 ; for A1609W, + CMP R1, R0 + BLS RAMCODE + + ; ram code base address. + ADD R2, R0,R2 +RAMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s new file mode 100644 index 0000000000..14bc83d796 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s @@ -0,0 +1,353 @@ +;******************************************************************************* +; Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +; +; This software is owned and published by: +; Huada Semiconductor Co.,Ltd ("HDSC"). +; +; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +; +; This software contains source code for use with HDSC +; components. This software is licensed by HDSC to be adapted only +; for use in systems utilizing HDSC components. HDSC shall not be +; responsible for misuse or illegal use of this software for devices not +; supported herein. HDSC is providing this software "AS IS" and will +; not be responsible for issues arising from incorrect user implementation +; of the software. +; +; Disclaimer: +; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +; WARRANTY OF NONINFRINGEMENT. +; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +; SAVINGS OR PROFITS, +; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +; FROM, THE SOFTWARE. +; +; This software may be replicated in part or whole for the licensed use, +; with the restriction that this Disclaimer and Copyright notice must be +; included with each copy of this software, whether used in part or whole, +; at all times. +;/ +;/*****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2018-04-15 */ +;/* Target-mcu M0+ Device */ +;/*****************************************************************************/ + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + SECTION .intvec:CODE:ROOT(8) + DATA +__vector_table DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD 0 ; Debug Monitor + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + ;reset NVIC if in rom debug + LDR R0, =0x20000000 + LDR R2, =0x0 ; vector offset + cmp PC, R0 + bls ROMCODE + + ; ram code base address. + ADD R2, R0,R2 +ROMCODE + ; reset Vector table address. + LDR R0, =0xE000ED08 + STR R2, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK IRQ000_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ000_Handler + B IRQ000_Handler + + + PUBWEAK IRQ001_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ001_Handler + B IRQ001_Handler + + + PUBWEAK IRQ002_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ002_Handler + B IRQ002_Handler + + + PUBWEAK IRQ003_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ003_Handler + B IRQ003_Handler + + + PUBWEAK IRQ004_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ004_Handler + B IRQ004_Handler + + + PUBWEAK IRQ005_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ005_Handler + B IRQ005_Handler + + + PUBWEAK IRQ006_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ006_Handler + B IRQ006_Handler + + + PUBWEAK IRQ007_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ007_Handler + B IRQ007_Handler + + + PUBWEAK IRQ008_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ008_Handler + B IRQ008_Handler + + + PUBWEAK IRQ009_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ009_Handler + B IRQ009_Handler + + + PUBWEAK IRQ010_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ010_Handler + B IRQ010_Handler + + + PUBWEAK IRQ011_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ011_Handler + B IRQ011_Handler + + + PUBWEAK IRQ012_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ012_Handler + B IRQ012_Handler + + + PUBWEAK IRQ013_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ013_Handler + B IRQ013_Handler + + + PUBWEAK IRQ014_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ014_Handler + B IRQ014_Handler + + + PUBWEAK IRQ015_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ015_Handler + B IRQ015_Handler + + + PUBWEAK IRQ016_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ016_Handler + B IRQ016_Handler + + + PUBWEAK IRQ017_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ017_Handler + B IRQ017_Handler + + + PUBWEAK IRQ018_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ018_Handler + B IRQ018_Handler + + + PUBWEAK IRQ019_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ019_Handler + B IRQ019_Handler + + + PUBWEAK IRQ020_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ020_Handler + B IRQ020_Handler + + + PUBWEAK IRQ021_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ021_Handler + B IRQ021_Handler + + + PUBWEAK IRQ022_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ022_Handler + B IRQ022_Handler + + + PUBWEAK IRQ023_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ023_Handler + B IRQ023_Handler + + + PUBWEAK IRQ024_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ024_Handler + B IRQ024_Handler + + + PUBWEAK IRQ025_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ025_Handler + B IRQ025_Handler + + + PUBWEAK IRQ026_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ026_Handler + B IRQ026_Handler + + + PUBWEAK IRQ027_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ027_Handler + B IRQ027_Handler + + + PUBWEAK IRQ028_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ028_Handler + B IRQ028_Handler + + + PUBWEAK IRQ029_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ029_Handler + B IRQ029_Handler + + + PUBWEAK IRQ030_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ030_Handler + B IRQ030_Handler + + + PUBWEAK IRQ031_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ031_Handler + B IRQ031_Handler + + END diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c new file mode 100644 index 0000000000..4086444a25 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c @@ -0,0 +1,477 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l136.c + ** + ** Interrupt management + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-15 1.0 Lux First version. + ** + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" +void Gpio_IRQHandler(uint8_t u8Param); +__WEAKDEF void Dma_IRQHandler(uint8_t u8Param); +void Uart_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpUart_IRQHandler(uint8_t u8Param); +__WEAKDEF void Spi_IRQHandler(uint8_t u8Param); +__WEAKDEF void I2c_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim3_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adt_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpTim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pca_IRQHandler(uint8_t u8Param); +__WEAKDEF void Wdt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Vc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Rtc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pcnt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lvd_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lcd_IRQHandler(uint8_t u8Param); +__WEAKDEF void EfRam_IRQHandler(uint8_t u8Param); +__WEAKDEF void ClkTrim_IRQHandler(uint8_t u8Param); + +/** + ******************************************************************************* + ** \brief NVIC 中断使能 + ** + ** \param [in] enIrq 中断å·æžšä¸¾ç±»åž‹ + ** \param [in] enLevel 中断优先级枚举类型 + ** \param [in] bEn 中断开关 + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn) +{ + NVIC_ClearPendingIRQ(enIrq); + NVIC_SetPriority(enIrq, enLevel); + if (TRUE == bEn) + { + NVIC_EnableIRQ(enIrq); + } + else + { + NVIC_DisableIRQ(enIrq); + } +} + +/** + ******************************************************************************* + ** \brief NVIC hardware fault 中断实现 + ** 用于å•æ­¥è°ƒè¯•åŠŸèƒ½ + ** + ** \retval + ******************************************************************************/ +//void HardFault_Handler(void) +//{ +// volatile int a = 0; + +// while( 0 == a) +// { +// ; +// } +//} + +/** + ******************************************************************************* + ** \brief GPIO PortA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTA_IRQHandler(void) +{ + Gpio_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief GPIO PortB 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTB_IRQHandler(void) +{ + Gpio_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief GPIO PortC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTC_IRQHandler(void) +{ + Gpio_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief GPIO PortD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTD_IRQHandler(void) +{ + Gpio_IRQHandler(3); +} + +/** + ******************************************************************************* + ** \brief DMAC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void DMAC_IRQHandler(void) +{ + Dma_IRQHandler(0); +} + + +/** + ******************************************************************************* + ** \brief UART0 串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART0_IRQHandler(void) +{ + Uart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief UART1 串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART1_IRQHandler(void) +{ + Uart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief LPUART0 低功耗串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART0_IRQHandler(void) +{ + LpUart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPUART1 低功耗串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART1_IRQHandler(void) +{ + LpUart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief SPI0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI0_IRQHandler(void) +{ + Spi_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief SPI1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI1_IRQHandler(void) +{ + Spi_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief I2C0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C0_IRQHandler(void) +{ + I2c_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief I2C1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C1_IRQHandler(void) +{ + I2c_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM0 基础时钟0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM0_IRQHandler(void) +{ + Tim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM1 基础时钟1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM1_IRQHandler(void) +{ + Tim_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM2 基础时钟2 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM2_IRQHandler(void) +{ + Tim_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief TIM3 基础时钟3 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM3_IRQHandler(void) +{ + Tim3_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPTIM 低功耗时钟 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPTIM_IRQHandler(void) +{ + LpTim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM4 高级时钟4 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM4_IRQHandler(void) +{ + Adt_IRQHandler(4); +} + +/** + ******************************************************************************* + ** \brief TIM5 高级时钟5 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM5_IRQHandler(void) +{ + Adt_IRQHandler(5); +} + +/** + ******************************************************************************* + ** \brief TIM6 高级时钟6 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM6_IRQHandler(void) +{ + Adt_IRQHandler(6); +} + +/** + ******************************************************************************* + ** \brief PCA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCA_IRQHandler(void) +{ + Pca_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief WDT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void WDT_IRQHandler(void) +{ + Wdt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RTC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void RTC_IRQHandler(void) +{ + Rtc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief ADC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void ADC_IRQHandler(void) +{ + Adc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief PCNT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCNT_IRQHandler(void) +{ + Pcnt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC0_IRQHandler(void) +{ + Vc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC1_IRQHandler(void) +{ + Vc_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief 低电压检测 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LVD_IRQHandler(void) +{ + Lvd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LCD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LCD_IRQHandler(void) +{ + Lcd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RAM 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void EF_RAM_IRQHandler(void) +{ + EfRam_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 时钟校准 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void CLKTRIM_IRQHandler(void) +{ + ClkTrim_IRQHandler(0); +} + + + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l136.h b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l136.h new file mode 100644 index 0000000000..708eee7dbd --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l136.h @@ -0,0 +1,107 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l136.h + ** + ** A detailed description is available at + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-09 1.0 Lux First version. + ** + ******************************************************************************/ + +#ifndef __SYSTEM_HC32L136_H__ +#define __SYSTEM_HC32L136_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ +#define HWWD_DISABLE (1) + + + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern void SystemInit (void); // Initialize the system +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32L136_H__ */ + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c new file mode 100644 index 0000000000..603861ff37 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c @@ -0,0 +1,91 @@ +/******************************************************************************* +* Copyright (C) 2019, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file system_hc32l13x.c + ** + ** System clock initialization. + ** @link SampleGroup Some description @endlink + ** + ** - 2019-03-01 1.0 Lux First version. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" +#include "hc32l136.h" +#include "system_hc32l13x.h" +#include "sysctrl.h" + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = 4000000; + + +//add clock source. +void SystemCoreClockUpdate (void) // Update SystemCoreClock variable +{ + SystemCoreClock = Sysctrl_GetHClkFreq(); +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit(void) +{ + SystemCoreClockUpdate(); + +} + + + + + + diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..e917f357a3 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..feec324059 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..3ddcc58b69 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..12d68fd9a6 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_version.h b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_armv81mml.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000000..8441e57fb1 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000..344dca5148 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000..5ddb8aeda7 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..cafae5a0a7 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..d104965db5 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm1.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm23.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000..b79c6af0b1 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm3.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm33.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000..7fed59a88e --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm35p.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000000..5579c82306 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm4.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..12c023b801 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_cm7.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..c4515d8fa3 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_sc000.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..cf92577b63 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/core_sc300.h b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..40f3af81be --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..66ef59b4a0 --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000..0041d4dc6f --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32l136/Libraries/CMSIS/Include/tz_context.h b/bsp/hc32l136/Libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/hc32l136/Libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adc.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adc.h new file mode 100644 index 0000000000..b0f79183f1 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/adc.h @@ -0,0 +1,486 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adc.h + ** + ** Header file for AD Converter functions + ** @link ADC Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +#ifndef __ADC_H__ +#define __ADC_H__ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup AdcGroup AD Converter (ADC) + ** + ******************************************************************************/ + +//@{ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define ADC_SCAN_CH0_EN (0x1u) /*!< SCAN模å¼ä½¿ç”¨ADC CH0 */ +#define ADC_SCAN_CH1_EN (0x1u<<1) /*!< SCAN模å¼ä½¿ç”¨ADC CH1 */ +#define ADC_SCAN_CH2_EN (0x1u<<2) /*!< SCAN模å¼ä½¿ç”¨ADC CH2 */ +#define ADC_SCAN_CH3_EN (0x1u<<3) /*!< SCAN模å¼ä½¿ç”¨ADC CH3 */ +#define ADC_SCAN_CH4_EN (0x1u<<4) /*!< SCAN模å¼ä½¿ç”¨ADC CH4 */ +#define ADC_SCAN_CH5_EN (0x1u<<5) /*!< SCAN模å¼ä½¿ç”¨ADC CH5 */ +#define ADC_SCAN_CH6_EN (0x1u<<6) /*!< SCAN模å¼ä½¿ç”¨ADC CH6 */ +#define ADC_SCAN_CH7_EN (0x1u<<7) /*!< SCAN模å¼ä½¿ç”¨ADC CH7 */ + + +/****************************************************************************** + ** Global type definitions + *****************************************************************************/ + + /** + ****************************************************************************** + ** \brief ADCé‡‡æ ·æ¨¡å¼ + *****************************************************************************/ +typedef enum en_adc_op_mode +{ + AdcSglMode = 0u, /*!< å•è¾“入通é“å•æ¬¡é‡‡æ ·æ¨¡å¼ */ + AdcSCanMode = 1u, /*!< 多输入通é“顺åºæ‰«æ采样模å¼,多输入通é“æ’队扫æ采样模å¼*/ +} en_adc_op_mode_t; + +/** + ****************************************************************************** + ** \brief ADC时钟选择 + *****************************************************************************/ +typedef enum en_adc_clk_sel +{ + AdcClkSysTDiv1 = 0u, /*!< PCLK */ + AdcClkSysTDiv2 = 1u, /*!< 1/2 PCLK */ + AdcClkSysTDiv4 = 2u, /*!< 1/4 PCLK */ + AdcClkSysTDiv8 = 3u, /*!< 1/8 PCLK */ + +} en_adc_clk_div_t; + +/** + ****************************************************************************** + ** \brief ADCå‚考电压 + *****************************************************************************/ +typedef enum en_adc_ref_vol_sel +{ + RefVolSelInBgr1p5 = 0u, /*!<内部å‚考电压1.5V(SPS<=200kHz)*/ + RefVolSelInBgr2p5 = 1u, /*!<内部å‚考电压2.5V(avdd>3V,SPS<=200kHz)*/ + RefVolSelExtern1 = 2u, /*!<外部输入(max avdd) PB01*/ + RefVolSelAVDD = 3u, /*!>4)*10) + ((x)&0x0F)) + +#define setBit(addr,offset,flag) { if( (flag) > 0u){\ + *((volatile uint32_t *)(addr)) |= ((1UL)<<(offset));\ + }else{\ + *((volatile uint32_t *)(addr)) &= (~(1UL<<(offset)));\ + }\ + } + +#define getBit(addr,offset) ((((*((volatile uint32_t *)(addr))) >> (offset)) & 1u)>0?1u:0) + +/** + ****************************************************************************** + ** Global Device Series List + ******************************************************************************/ +#define DDL_DEVICE_SERIES_HC32L136 (0u) + +/** + ****************************************************************************** + ** Global Device Package List + ******************************************************************************/ +// package definitions of HC device. +#define DDL_DEVICE_PACKAGE_HC_C (0x00u) +#define DDL_DEVICE_PACKAGE_HC_F (0x10u) +#define DDL_DEVICE_PACKAGE_HC_J (0x20u) +#define DDL_DEVICE_PACKAGE_HC_K (0x30u) + +/******************************************************************************/ +/* User Device Setting Include file */ +/******************************************************************************/ +#include "ddl_device.h" // MUST be included here! + +/** + ****************************************************************************** + ** \brief IRQ name definition for all type MCUs + ******************************************************************************/ + + #define PORTA_IRQHandler(void) IRQ000_Handler(void) + #define PORTB_IRQHandler(void) IRQ001_Handler(void) + #define PORTC_IRQHandler(void) IRQ002_Handler(void) + #define PORTD_IRQHandler(void) IRQ003_Handler(void) + #define DMAC_IRQHandler(void) IRQ004_Handler(void) + #define TIM3_IRQHandler(void) IRQ005_Handler(void) + #define UART0_IRQHandler(void) IRQ006_Handler(void) + #define UART1_IRQHandler(void) IRQ007_Handler(void) + #define LPUART0_IRQHandler(void) IRQ008_Handler(void) + #define LPUART1_IRQHandler(void) IRQ009_Handler(void) + #define SPI0_IRQHandler(void) IRQ010_Handler(void) + #define SPI1_IRQHandler(void) IRQ011_Handler(void) + #define I2C0_IRQHandler(void) IRQ012_Handler(void) + #define I2C1_IRQHandler(void) IRQ013_Handler(void) + #define TIM0_IRQHandler(void) IRQ014_Handler(void) + #define TIM1_IRQHandler(void) IRQ015_Handler(void) + #define TIM2_IRQHandler(void) IRQ016_Handler(void) + #define LPTIM_IRQHandler(void) IRQ017_Handler(void) + #define TIM4_IRQHandler(void) IRQ018_Handler(void) + #define TIM5_IRQHandler(void) IRQ019_Handler(void) + #define TIM6_IRQHandler(void) IRQ020_Handler(void) + #define PCA_IRQHandler(void) IRQ021_Handler(void) + #define WDT_IRQHandler(void) IRQ022_Handler(void) + #define RTC_IRQHandler(void) IRQ023_Handler(void) + #define ADC_IRQHandler(void) IRQ024_Handler(void) + #define PCNT_IRQHandler(void) IRQ025_Handler(void) + #define VC0_IRQHandler(void) IRQ026_Handler(void) + #define VC1_IRQHandler(void) IRQ027_Handler(void) + #define LVD_IRQHandler(void) IRQ028_Handler(void) + #define LCD_IRQHandler(void) IRQ029_Handler(void) + #define EF_RAM_IRQHandler(void) IRQ030_Handler(void) + #define CLKTRIM_IRQHandler(void) IRQ031_Handler(void) + +/******************************************************************************/ +/* Global type definitions ('typedef') */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Level + ** + ** Specifies levels. + ** + ******************************************************************************/ +typedef enum en_level +{ + DdlLow = 0u, ///< Low level '0' + DdlHigh = 1u ///< High level '1' +} en_level_t; + +/** + ****************************************************************************** + ** \brief Generic Flag Code + ** + ** Specifies flags. + ** + ******************************************************************************/ +typedef enum en_flag +{ + DdlClr = 0u, ///< Flag clr '0' + DdlSet = 1u ///< Flag set '1' +} en_stat_flag_t, en_irq_flag_t; +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +/******************************************************************************* + * Global function prototypes + ******************************************************************************/ +extern void ddl_memclr(void* pu8Address, uint32_t u32Count); +uint32_t Log2(uint32_t u32Val); +/** + ******************************************************************************* + ** This hook is part of wait loops. + ******************************************************************************/ +extern void DDL_WAIT_LOOP_HOOK(void); + +void Debug_UartInit(void); + +void delay1ms(uint32_t u32Cnt); +void delay100us(uint32_t u32Cnt); +void delay10us(uint32_t u32Cnt); +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/debug.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/debug.h new file mode 100644 index 0000000000..c29060d2b8 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/debug.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file debug.h + ** + ** Headerfile for DEBUG functions + ** @link Debug Group Some description @endlink + ** + ** History: + ** - 2018-04-15 Lux First Version + ** + ******************************************************************************/ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup DebugGroup (DEBUG) + ** + ******************************************************************************/ +//@{ + +/** + ******************************************************************************* + ** function prototypes. + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ******************************************************************************* + ** \brief 调试模å¼ä¸‹å„模å—工作状æ€ç±»åž‹å®šä¹‰ + ** \note + ******************************************************************************/ +typedef enum en_debug_module_active +{ + DebugTim0 = 0x001u, ///< TIM0 + DebugTim1 = 0x002u, ///< TIM1 + DebugTim2 = 0x004u, ///< TIM2 + DebugLpTim = 0x008u, ///< LPTIM + DebugTim4 = 0x010u, ///< TIM4 + DebugTim5 = 0x020u, ///< TIM5 + DebugTim6 = 0x040u, ///< TIM6 + DebugPca = 0x080u, ///< PCA + DebugWdt = 0x100u, ///< WDT + DebugRtc = 0x200u, ///< RTC + DebugTick = 0x400u, ///< TICK + DebugTim3 = 0x800u, ///< TIM3 +}en_debug_module_active_t; + +/******************************************************************************* + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + ******************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + ******************************************************************************/ +///< 在SWD调试界é¢ä¸‹ï¼Œä½¿èƒ½æ¨¡å—功能 +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule); +///< 在SWD调试界é¢ä¸‹ï¼Œæš‚åœæ¨¡å—功能 +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule); + +//@} // Debug Group + +#ifdef __cplusplus +#endif + +#endif /* __DEBUG_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/dmac.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/dmac.h new file mode 100644 index 0000000000..7e68f2547f --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/dmac.h @@ -0,0 +1,327 @@ +/***************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dma.h +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ +#ifndef __DMAC_H__ +#define __DMAC_H__ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + ******************************************************************************* + ** \defgroup DmacGroup Direct Memory Access Control(DMAC) + ** + ******************************************************************************/ + //@{ + + /******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + /** + ******************************************************************************* + ** \brief DMA Channel + ** + ******************************************************************************/ + typedef enum en_dma_channel + { + DmaCh0 = 0U, ///< DMA channel 0 + DmaCh1 = 1U, ///< DMA channel 1 + DmaChMax = 2U ///< DMA channel max + } en_dma_channel_t; + /** + ******************************************************************************* + ** \brief DMA priority + ** + ******************************************************************************/ + typedef enum en_dma_priority + { + DmaPriorityFix = 0U, ///< DMA channel priority fix (CH0>CH1) + DmaPriorityLoop = 1U, ///< DMA channel priority loop + } en_dma_priority_t; + + /** + ******************************************************************************* + ** \brief DMA transfer data width + ** + ******************************************************************************/ + typedef enum en_dma_transfer_width + { + Dma8Bit = 0U, ///< 8 bit transfer via DMA + Dma16Bit = 1U, ///< 16 bit transfer via DMA + Dma32Bit = 2U ///< 32 bit transfer via DMA + } en_dma_transfer_width_t; + + /** + ******************************************************************************* + ** \brief DMA transfer mode + ** + ******************************************************************************/ + typedef enum en_dma_transfer_mode + { + DmaBlock = 0U, ///< block transfer via DMA + DmaBurst = 1U, ///< burst transfer via DMA + } en_dma_transfer_mode_t; + + /** + ******************************************************************************* + ** \brief DMA flag + ** + ******************************************************************************/ + typedef enum en_dma_stat + { + DEFAULT = 0U, ///< Reserve + DmaAddOverflow = 1U, ///< DMA address overflow + DmaHALT = 2U, ///< DMA HALT + DmaAccSCRErr = 3U, ///< DMA access source address error + DmaAccDestErr = 4U, ///< DMA access dest address error + DmaTransferComplete = 5U, ///< DMA transfer complete + DmaTransferPause = 7U, ///< DMA transfer pause + } en_dma_stat_t; + + /** + ******************************************************************************* + ** \brief DMA address mode + ** + ******************************************************************************/ + typedef enum en_address_mode + { + AddressIncrease = 0U, ///< Address increased + AddressFix = 1U, ///< Address fixed + } en_address_mode_t; + + /** + ******************************************************************************* + ** \brief DMA repeat tranfer + ** + ******************************************************************************/ + typedef enum en_dma_msk + { + OneTranfer = 0U, ///< One Tranfer + ContinuousTranfer = 1U, ///< Continuous Tranfer + } en_dma_msk_t; + /** + ******************************************************************************* + ** \brief DMA trigger selection + ** + ******************************************************************************/ + typedef enum stc_dma_trig_sel + { + SWTrig = 0U, ///< Select DMA software trig + SPI0RXTrig = 32U, ///< Select DMA hardware trig 0 + SPI0TXTrig = 33U, ///< Select DMA hardware trig 1 + SPI1RXTrig = 34U, ///< Select DMA hardware trig 2 + SPI1TXTrig = 35U, ///< Select DMA hardware trig 3 + ADCJQRTrig = 36U, ///< Select DMA hardware trig 4 + ADCSQRTrig = 37U, ///< Select DMA hardware trig 5 + LCDTxTrig = 38U, ///< Select DMA hardware trig 6 + Uart0RxTrig = 40U, ///< Select DMA hardware trig 8 + Uart0TxTrig = 41U, ///< Select DMA hardware trig 9 + Uart1RxTrig = 42U, ///< Select DMA hardware trig 10 + Uart1TxTrig = 43U, ///< Select DMA hardware trig 11 + LpUart0RxTrig = 44U, ///< Select DMA hardware trig 12 + LpUart0TxTrig = 45U, ///< Select DMA hardware trig 13 + LpUart1RxTrig = 46U, ///< Select DMA hardware trig 14 + LpUart1TxTrig = 47U, ///< Select DMA hardware trig 15 + TIM0ATrig = 50U, ///< Select DMA hardware trig 18 + TIM0BTrig = 51U, ///< Select DMA hardware trig 19 + TIM1ATrig = 52U, ///< Select DMA hardware trig 20 + TIM1BTrig = 53U, ///< Select DMA hardware trig 21 + TIM2ATrig = 54U, ///< Select DMA hardware trig 22 + TIM2BTrig = 55U, ///< Select DMA hardware trig 23 + TIM3ATrig = 56U, ///< Select DMA hardware trig 24 + TIM3BTrig = 57U, ///< Select DMA hardware trig 25 + TIM4ATrig = 58U, ///< Select DMA hardware trig 26 + TIM4BTrig = 59U, ///< Select DMA hardware trig 27 + TIM5ATrig = 60U, ///< Select DMA hardware trig 28 + TIM5BTrig = 61U, ///< Select DMA hardware trig 29 + TIM6ATrig = 62U, ///< Select DMA hardware trig 30 + TIM6BTrig = 63U, ///< Select DMA hardware trig 31 + }en_dma_trig_sel_t; + /** + ******************************************************************************* + ** \brief DMA interrupt selection + ** + ******************************************************************************/ +typedef struct stc_dma_irq + { + boolean_t TrnErrIrq; ///< Select DMA transfer error interrupt + boolean_t TrnCpltIrq; ///< Select DMA transfer completion interrupt + }stc_dma_irq_sel_t; + + + + /** + ******************************************************************************* + ** \brief DMA configuration + ** + ******************************************************************************/ + typedef struct stc_dma_config + { + en_dma_transfer_mode_t enMode; + + uint16_t u16BlockSize; ///< Transfer Block counter + uint16_t u16TransferCnt; ///< Transfer counter + en_dma_transfer_width_t enTransferWidth; ///< DMA transfer width (see #en_dma_transfer_width_t for details) + + en_address_mode_t enSrcAddrMode; ///< Source address mode(see #en_source_address_mode_t for details) + en_address_mode_t enDstAddrMode; ///< Destination address mode(see #en_dest_address_mode_t for details) + + boolean_t bSrcAddrReloadCtl; ///< Source address reload(TRUE: reload;FALSE: reload forbidden) + boolean_t bDestAddrReloadCtl; ///< Dest address reload(TRUE: reload;FALSE: reload forbidden) + boolean_t bSrcBcTcReloadCtl; ///< Bc/Tc address reload(TRUE: reload;FALSE: reload forbidden) + uint32_t u32SrcAddress; ///< Source address> + uint32_t u32DstAddress; ///< Dest address> + boolean_t bMsk; ///0: clear the bit (CONFA:ENS) after tarnfer;1: remain the bit (CONFA:ENS) after tarnfer + + en_dma_trig_sel_t enRequestNum; ///< DMA trigger request number + } stc_dma_config_t; + /** + ****************************************************************************** + ** \brief DMA中断回调函数 + *****************************************************************************/ +typedef struct stc_dma_irq_calbakfn_pt +{ + /*! Dma传输完æˆä¸­æ–­å›žè°ƒå‡½æ•°æŒ‡é’ˆ*/ + func_ptr_t pfnDma0TranferCompleteIrq; + /*! Dma传输完æˆä¸­æ–­å›žè°ƒå‡½æ•°æŒ‡é’ˆ*/ + func_ptr_t pfnDma1TranferCompleteIrq; + /*! Dma传输错误中断回调函数指针*/ + func_ptr_t pfnDma0TranferErrIrq; + /*! Dma传输错误中断回调函数指针*/ + func_ptr_t pfnDma1TranferErrIrq; +}stc_dma_irq_calbakfn_pt_t; + /******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + + /******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + /******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig); + + void Dma_SwTrigger(en_dma_channel_t enCh); + + void Dma_Enable(void); + void Dma_Disable(void); + + void Dma_Start(en_dma_channel_t enCh); + void Dma_Stop(en_dma_channel_t enCh); + + en_result_t Dma_EnableChannel(en_dma_channel_t enCh); + en_result_t Dma_DisableChannel(en_dma_channel_t enCh); + + en_result_t Dma_SetTriggerSel(en_dma_channel_t enCh, en_dma_trig_sel_t enTrgSel); + + en_result_t Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address); + en_result_t Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address); + + en_result_t Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize); + en_result_t Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt); + + + en_result_t Dma_SetSourceIncMode(en_dma_channel_t enCh, en_address_mode_t enMode); + en_result_t Dma_SetDestinationIncMode(en_dma_channel_t enCh, en_address_mode_t enMode); + + en_result_t Dma_EnableSourceRload(en_dma_channel_t enCh); + en_result_t Dma_DisableSourceRload(en_dma_channel_t enCh); + + en_result_t Dma_EnableDestinationRload(en_dma_channel_t enCh); + en_result_t Dma_DisableDestinationRload(en_dma_channel_t enCh); + + en_result_t Dma_EnableContinusTranfer(en_dma_channel_t enCh); + en_result_t Dma_DisableContinusTranfer(en_dma_channel_t enCh); + + en_result_t Dma_EnableBcTcReload(en_dma_channel_t enCh); + en_result_t Dma_DisableBcTcReload(en_dma_channel_t enCh); + + void Dma_HaltTranfer(void); + void Dma_RecoverTranfer(void); + en_result_t Dma_PauseChannelTranfer(en_dma_channel_t enCh); + en_result_t Dma_RecoverChannelTranfer(en_dma_channel_t enCh); + + en_result_t Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth); + + en_result_t Dma_SetChPriority(en_dma_priority_t enPrio); + + en_result_t Dma_EnableChannelIrq(en_dma_channel_t enCh); + en_result_t Dma_DisableChannelIrq(en_dma_channel_t enCh); + + en_result_t Dma_EnableChannelErrIrq(en_dma_channel_t enCh); + en_result_t Dma_DisableChannelErrIrq(en_dma_channel_t enCh); + + en_result_t Dma_ConfigIrq(en_dma_channel_t enCh,stc_dma_irq_sel_t* stcDmaIrqCfg,stc_dma_irq_calbakfn_pt_t* pstcDmaIrqCalbaks); + + + en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh); + + void Dma_ClrStat(en_dma_channel_t enCh); + //@} // DmacGroup + +#ifdef __cplusplus +} +#endif + +#endif /* __DMAC_H__ */ + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/flash.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/flash.h new file mode 100644 index 0000000000..106e803791 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/flash.h @@ -0,0 +1,196 @@ +/************************************************************************************* +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file flash.h + ** + ** FLASH æ•°æ®ç»“æž„åŠAPI声明. + ** + ** - 2017-05-02 LuX V1.0 + ** + ******************************************************************************/ + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup FlashGroup Flash Controller (Flash) + ** + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief Flash中断类型é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_flash_int_type +{ + FlashPCInt = 1u, ///<擦写PC地å€æŠ¥è­¦ä¸­æ–­ + FlashSlockInt = 0u, ///<擦写ä¿æŠ¤æŠ¥è­¦ä¸­æ–­ +} en_flash_int_type_t; + + +/** + ****************************************************************************** + ** \brief Flash读等待周期类型é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_flash_waitcycle +{ + FlashWaitCycle0 = 0u, ///< 读等待周期设置为0（当HCLKå°äºŽç­‰äºŽ24MHz时） + FlashWaitCycle1 = 1u, ///< 读等待周期设置为1（当HCLK大于24MHz时必须至少为1） + FlashWaitCycle2 = 2u, ///< 读等待周期设置为2（当HCK大于48MHz时必须至少为2） +} en_flash_waitcycle_t; + +/** + ****************************************************************************** + ** \brief Flash擦写ä¿æŠ¤èŒƒå›´é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_flash_sector_lock +{ + FlashSector0_3 = 0x00000001u, ///PCLK=HCLK=SystemClk=RCH4MHz +en_result_t Sysctrl_ClkDeInit(void); + +///< 系统时钟模å—的基本功能设置 +///< 注æ„：使能需è¦ä½¿ç”¨çš„时钟æºä¹‹å‰ï¼Œå¿…须优先设置目标内部时钟æºçš„TRIM值或外部时钟æºçš„频率范围 +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag); + +///<外部晶振驱动é…置：系统åˆå§‹åŒ–Sysctrl_ClkInit()之åŽï¼Œå¯æ ¹æ®éœ€è¦é…置外部晶振的驱动能力，时钟åˆå§‹åŒ–Sysctrl_ClkInit()默认为最大值; +en_result_t Sysctrl_XTHDriverConfig(en_sysctrl_xtal_driver_t enDriver); +en_result_t Sysctrl_XTLDriverConfig(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver); + +///<时钟稳定周期设置:系统åˆå§‹åŒ–Sysctrl_ClkInit()之åŽï¼Œå¯æ ¹æ®éœ€è¦é…置时钟开å¯åŽçš„稳定之间，默认为最大值; +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle); +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle); +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle); +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle); + +///<系统时钟æºåˆ‡æ¢å¹¶æ›´æ–°ç³»ç»Ÿæ—¶é’Ÿï¼šå¦‚果需è¦åœ¨ç³»ç»Ÿæ—¶é’Ÿåˆå§‹åŒ–Sysctrl_ClkInit()之åŽåˆ‡æ¢ä¸»é¢‘时钟æºï¼Œåˆ™ä½¿ç”¨è¯¥å‡½æ•°ï¼› +///< 时钟切æ¢å‰åŽï¼Œå¿…须根æ®ç›®æ ‡é¢‘率值设置Flash读等待周期，å¯é…ç½®æ’入周期为0ã€1ã€2， +///< 注æ„!!!：当HCLK大于24MHz时，FLASH等待周期æ’入必须至少为1,å¦åˆ™ç¨‹åºè¿è¡Œå¯èƒ½äº§ç”ŸæœªçŸ¥é”™è¯¯ +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource); + +///< 时钟æºé¢‘率设定：根æ®ç³»ç»Ÿæƒ…况，å•ç‹¬è®¾ç½®ä¸åŒæ—¶é’Ÿæºçš„频率值; +///< 时钟频率设置å‰ï¼Œå¿…须根æ®ç›®æ ‡é¢‘率值设置Flash读等待周期，å¯é…ç½®æ’入周期为0ã€1ã€2， +///< 其中XTL的时钟由外部晶振决定，无需设置。 +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq); +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq); +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq); +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_config_t *pstcPLLCfg); + +///< 时钟分频设置:æ ¹æ®ç³»ç»Ÿæƒ…况，å•ç‹¬è®¾ç½®HCLKã€PCLK的分é…值; +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv); +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv); + +///< 时钟频率获å–：根æ®ç³»ç»Ÿéœ€è¦ï¼ŒèŽ·å–当å‰HCLKåŠPCLK的频率值 +uint32_t Sysctrl_GetHClkFreq(void); +uint32_t Sysctrl_GetPClkFreq(void); + +///< 外设门控开关/状æ€èŽ·å–：用于控制外设模å—的使能，使用该模å—的功能之å‰ï¼Œå¿…须使能该模å—的门控时钟； +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag); +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral); + +///< 系统功能é…置：用于设置其他系统相关特殊功能； +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag); + +///< RTC高速时钟补å¿:用于设置RTCé«˜é€Ÿæ—¶é’Ÿä¸‹çš„é¢‘çŽ‡è¡¥å¿ +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj); + +//@} // Sysctrl Group + +#ifdef __cplusplus +#endif + +#endif /* __SYSCTRL_H__ */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer0.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer0.h new file mode 100644 index 0000000000..26398b0e6b --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer0.h @@ -0,0 +1,788 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file bt.h + ** + ** 基本定时器数æ®ç»“æž„åŠAPI声明 + ** @link BT Timer3 Group Some description @endlink + ** + ** History: + ** - 2018-04-29 Husj First Version + ** + *****************************************************************************/ + +#ifndef __TIMER0_H__ +#define __TIMER0_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup Tim0Group Base Timer (BT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Timer3 通é“定义 + *****************************************************************************/ +typedef enum en_tim0_channel +{ + Tim0CH0 = 0u, ///< Timer3通é“0 + Tim0CH1 = 1u, ///< Timer3通é“1 + Tim0CH2 = 2u, ///< Timer3通é“2 +}en_tim0_channel_t; + +/** + ****************************************************************************** + ** \brief 工作模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (MODE)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_work_mode +{ + Tim0WorkMode0 = 0u, ///< å®šæ—¶å™¨æ¨¡å¼ + Tim0WorkMode1 = 1u, ///< PWCæ¨¡å¼ + Tim0WorkMode2 = 2u, ///< é”¯é½¿æ³¢æ¨¡å¼ + Tim0WorkMode3 = 3u, ///< ä¸‰è§’æ³¢æ¨¡å¼ +}en_tim0_work_mode_t; + +/** + ****************************************************************************** + ** \brief æžæ€§æŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (GATE_P)(模å¼0) + *****************************************************************************/ +typedef enum en_tim0_m0cr_gatep +{ + Tim0GatePositive = 0u, ///< 高电平有效 + Tim0GateOpposite = 1u, ///< 低电平有效 +}en_tim0_m0cr_gatep_t; + +/** + ****************************************************************************** + ** \brief TIM3 预除频选择 (PRS)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_cr_timclkdiv +{ + Tim0PCLKDiv1 = 0u, ///< Div 1 + Tim0PCLKDiv2 = 1u, ///< Div 2 + Tim0PCLKDiv4 = 2u, ///< Div 4 + Tim0PCLKDiv8 = 3u, ///< Div 8 + Tim0PCLKDiv16 = 4u, ///< Div 16 + Tim0PCLKDiv32 = 5u, ///< Div 32 + Tim0PCLKDiv64 = 6u, ///< Div 64 + Tim0PCLKDiv256 = 7u, ///< Div 256 +}en_tim0_cr_timclkdiv_t; + +/** + ****************************************************************************** + ** \brief 计数/定时器功能选择数æ®ç±»åž‹é‡å®šä¹‰ (CT)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_cr_ct +{ + Tim0Timer = 0u, ///< 定时器功能，计数时钟为内部PCLK + Tim0Counter = 1u, ///< 计数器功能，计数时钟为外部ETR +}en_tim0_cr_ct_t; + + +/** + ****************************************************************************** + ** \brief 定时器工作模å¼æ•°æ®ç±»åž‹é‡å®šä¹‰ (MD)(模å¼0) + *****************************************************************************/ +typedef enum en_tim0_m0cr_md +{ + Tim032bitFreeMode = 0u, ///< 32ä½è®¡æ•°å™¨/定时器 + Tim016bitArrMode = 1u, ///< 自动é‡è£…è½½16ä½è®¡æ•°å™¨/定时器 +}en_tim0_m0cr_md_t; + +/** + ****************************************************************************** +** \brief TIM3中断类型数æ®ç±»åž‹é‡å®šä¹‰(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim0_irq_type +{ + Tim0UevIrq = 0u, ///< 溢出/事件更新中断 + Tim0CA0Irq = 2u, ///< CH0Aæ•èŽ·/比较中断(仅模å¼1/23存在) + Tim0CA1Irq = 3u, ///< CH1Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CA2Irq = 4u, ///< CH2Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CB0Irq = 5u, ///< CH0Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CB1Irq = 6u, ///< CH1Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CB2Irq = 7u, ///< CH2Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim0CA0E = 8u, ///< CH0Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CA1E = 9u, ///< CH1Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CA2E = 10u, ///< CH2Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CB0E = 11u, ///< CH0Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CB1E = 12u, ///< CH1Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0CB2E = 13u, ///< CH2Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim0BkIrq = 14u, ///< 刹车中断(仅模å¼23存在） + Tim0TrigIrq = 15u, ///< 触å‘中断(仅模å¼23存在） +}en_tim0_irq_type_t; + +/** + ****************************************************************************** + ** \brief 测é‡å¼€å§‹ç»“æŸæ•°æ®ç±»åž‹é‡å®šä¹‰ (Edg1stEdg2nd)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1cr_Edge +{ + Tim0PwcRiseToRise = 0u, ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + Tim0PwcFallToRise = 1u, ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + Tim0PwcRiseToFall = 2u, ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + Tim0PwcFallToFall = 3u, ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) +}en_tim0_m1cr_Edge_t; + +/** + ****************************************************************************** + ** \brief PWC测é‡æµ‹è¯•æ¨¡å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (Oneshot)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1cr_oneshot +{ + Tim0PwcCycleDetect = 0u, ///< PWCå¾ªçŽ¯æµ‹é‡ + Tim0PwcOneShotDetect = 1u, ///< PWCå•æ¬¡æµ‹é‡ +}en_tim0_m1cr_oneshot_t; + +/** + ****************************************************************************** + ** \brief PWC IA0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1_mscr_ia0s +{ + Tim0IA0Input = 0u, ///< IAO输入 + Tim0XORInput = 1u, ///< IA0 ETR GATE XOR(TIM0/1/2)/IA0 IA1 IA2 XOR(TIM3) +}en_tim0_m1_mscr_ia0s_t; + +/** + ****************************************************************************** + ** \brief PWC IB0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim0_m1_mscr_ib0s +{ + Tim0IB0Input = 0u, ///< IBO输入 + Tim0TsInput = 1u, ///< 内部触å‘TSé€‰æ‹©ä¿¡å· +}en_tim0_m1_mscr_ib0s_t; + +/** + ****************************************************************************** + ** \brief 输出æžæ€§ã€è¾“å…¥ç›¸ä½ æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCPA0/CCPB0/ETP/BKP)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim0_port_polarity +{ + Tim0PortPositive = 0u, ///< 正常输入输出 + Tim0PortOpposite = 1u, ///< åå‘输入输出 +}en_tim0_port_polarity_t; + +/** + ****************************************************************************** + ** \brief 滤波选择数æ®ç±»åž‹é‡å®šä¹‰ (FLTET/FLTA0/FLAB0)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim0_flt +{ + Tim0FltNone = 0u, ///< 无滤波 + Tim0FltPCLKCnt3 = 4u, ///< PCLK 3个连续有效 + Tim0FltPCLKDiv4Cnt3 = 5u, ///< PCLK/4 3个连续有效 + Tim0FltPCLKDiv16Cnt3 = 6u, ///< PCLK/16 3个连续有效 + Tim0FltPCLKDiv64Cnt3 = 7u, ///< PCLK/64 3个连续有效 +}en_tim0_flt_t; + +/** + ****************************************************************************** + ** \brief 通é“比较控制 æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCMA/OCMB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_fltr_ocm +{ + Tim0ForceLow = 0u, ///< 强制为0 + Tim0ForceHigh = 1u, ///< 强制为1 + Tim0CMPForceLow = 2u, ///< 比较匹é…时强制为0 + Tim0CMPForceHigh = 3u, ///< 比较匹é…时强制为1 + Tim0CMPInverse = 4u, ///< 比较匹é…时翻转电平 + Tim0CMPOnePrdHigh = 5u, ///< 比较匹é…时输出一个计数周期的高电平 + Tim0PWMMode1 = 6u, ///< 通é“控制为PWM mode 1 + Tim0PWMMode2 = 7u, ///< 通é“控制为PWM mode 2 +}en_tim0_m23_fltr_ocm_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼TSæ•°æ®ç±»åž‹é‡å®šä¹‰ (TS)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim0_mscr_ts +{ + Tim0Ts0ETR = 0u, ///< ETR外部输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim0Ts1TIM0TRGO = 1u, ///< Timer0çš„TRGOè¾“å‡ºä¿¡å· + Tim0Ts2TIM1TRGO = 2u, ///< Timer1çš„TRGOè¾“å‡ºä¿¡å· + Tim0Ts3TIM2TRGO = 3u, ///< Timer2çš„TRGOè¾“å‡ºä¿¡å· + Tim0Ts4TIM3TRGO = 4u, ///< Timer3çš„TRGOè¾“å‡ºä¿¡å· + //Tim0Ts5IA0ED = 5u, ///< 无效 + Tim0Ts6IAFP = 6u, ///< CH0A 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim0Ts7IBFP = 7u, ///< CH0B 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡ +}en_tim0_mscr_ts_t; + +/** + ****************************************************************************** + ** \brief PWM输出模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (COMP)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_comp +{ + Tim0IndependentPWM = 0u, ///< 独立PWM输出 + Tim0ComplementaryPWM = 1u, ///< 互补PWM输出 +}en_tim0_m23cr_comp_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (DIR)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_dir +{ + Tim0CntUp = 0u, ///< å‘上计数 + Tim0CntDown = 1u, ///< å‘下计数 +}en_tim0_m23cr_dir_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (PWM2S)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_pwm2s +{ + Tim0DoublePointCmp = 0u, ///< åŒç‚¹æ¯”较使能，使用CCRA,CCRB比较控制OCREFA输出 + Tim0SinglePointCmp = 1u, ///< å•ç‚¹æ¯”较使能，使用CCRA比较控制OCREFA输出 +}en_tim0_m23cr_pwm2s_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 选择数æ®ç±»åž‹é‡å®šä¹‰ (CSG)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23cr_csg +{ + Tim0PWMCompGateCmpOut = 0u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为比较输出 + Tim0PWMCompGateCapIn = 1u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为æ•èŽ·è¾“å…¥ +}en_tim0_m23cr_csg_t; + + +/** + ****************************************************************************** + ** \brief 比较æ•èŽ·å¯„存器 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCR0A,CCR0B)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_ccrx +{ + Tim0CCR0A = 0u, ///< CCR0A比较æ•èŽ·å¯„存器 + Tim0CCR0B = 1u, ///< CCR0B比较æ•èŽ·å¯„存器 + Tim0CCR1A = 2u, ///< CCR1A比较æ•èŽ·å¯„存器 + Tim0CCR1B = 3u, ///< CCR1B比较æ•èŽ·å¯„存器 + Tim0CCR2A = 4u, ///< CCR2A比较æ•èŽ·å¯„存器 + Tim0CCR2B = 5u, ///< CCR2B比较æ•èŽ·å¯„存器 +}en_tim0_m23_ccrx_t; + +/** + ****************************************************************************** + ** \brief OCREFæ¸…é™¤æº é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCCS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23ce_occs +{ + Tim0OC_Ref_Clr = 0u, ///< æ¥è‡ªVCçš„OC_Ref_Clr + Tim0ETRf = 1u, ///< 外部ETRf +}en_tim0_m23ce_occs_t; + +/** + ****************************************************************************** + ** \brief 比较匹é…ä¸­æ–­æ¨¡å¼ é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (CIS/CISB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_cisa_cisb +{ + Tim0CmpIntNone = 0u, ///< 无比较匹é…中断 + Tim0CmpIntRise = 1u, ///< 比较匹é…上å‡æ²¿ä¸­æ–­ + Tim0CmpIntFall = 2u, ///< 比较匹é…下é™æ²¿ä¸­æ–­ + Tim0CmpIntRiseFall = 3u, ///< 比较匹é…上å‡æ²¿ä¸‹é™æ²¿ä¸­æ–­ +}en_tim0_m23_cisa_cisb_t; + +/** + ****************************************************************************** + ** \brief TIM3端å£æŽ§åˆ¶ - 刹车时CHx输出状æ€æŽ§åˆ¶(BKSA/BKSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim0_m23_crchx_bks +{ + Tim0CHxBksHiZ = 0u, ///< 刹车使能时，CHx端å£è¾“å‡ºé«˜é˜»æ€ + Tim0CHxBksNorm = 1u, ///< 刹车使能时，CHx端å£æ­£å¸¸è¾“出 + Tim0CHxBksLow = 2u, ///< 刹车使能时，CHx端å£è¾“出低电平 + Tim0CHxBksHigh = 3u, ///< 刹车使能时，CHx端å£è¾“出高电平 +}en_tim0_m23_crchx_bks_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·(CRx/CFx)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim0_m23_crch0_cfx_crx +{ + Tim0CHxCapNone = 0u, ///< CHx通é“æ•èŽ·ç¦æ­¢ + Tim0CHxCapRise = 1u, ///< CHx通é“上å‡æ²¿æ•èŽ·ä½¿èƒ½ + Tim0CHxCapFall = 2u, ///< CHx通é“下é™æ²¿æ•èŽ·ä½¿èƒ½ + Tim0CHxCapFallRise = 3u, ///< CHx通é“上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·éƒ½ä½¿èƒ½ +}en_tim0_m23_crch0_cfx_crx_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx比较æ•èŽ·æ¨¡å¼(CSA/CSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim0_m23_crch0_csa_csb +{ + Tim0CHxCmpMode = 0u, ///< CHx通é“è®¾ç½®ä¸ºæ¯”è¾ƒæ¨¡å¼ + Tim0CHxCapMode = 1u, ///< CHx通é“设置为æ•èŽ·æ¨¡å¼ +}en_tim0_m23_crch0_csa_csb_t; + +/** + ****************************************************************************** + ** \brief 比较模å¼ä¸‹ DMA比较触å‘选择 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCDS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_ccds +{ + Tim0CmpTrigDMA = 0u, ///< 比较匹é…触å‘DMA + Tim0UEVTrigDMA = 1u, ///< 事件更新代替比较匹é…触å‘DMA +}en_tim0_m23_mscr_ccds_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (MSM)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_msm +{ + Tim0SlaveMode = 0u, ///< ä»Žæ¨¡å¼ + Tim0MasterMode = 1u, ///< ä¸»æ¨¡å¼ +}en_tim0_m23_mscr_msm_t; + +/** + ****************************************************************************** + ** \brief 触å‘主模å¼è¾“å‡ºæº æ•°æ®ç±»åž‹é‡å®šä¹‰ (MMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_mms +{ + Tim0MasterUG = 0u, ///< UG(软件更新)æº + Tim0MasterCTEN = 1u, ///< CTENæº + Tim0MasterUEV = 2u, ///< UEVæ›´æ–°æº + Tim0MasterCMPSO = 3u, ///< 比较匹é…é€‰æ‹©è¾“å‡ºæº + Tim0MasterOCA0Ref = 4u, ///< OCA0_Refæº + Tim0MasterOCB0Ref = 5u, ///< OCB0_Refæº + //Tim0MasterOCB0Ref = 6u, + //Tim0MasterOCB0Ref = 7u, +}en_tim0_m23_mscr_mms_t; + +/** + ****************************************************************************** + ** \brief 触å‘从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (SMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim0_m23_mscr_sms +{ + Tim0SlaveIClk = 0u, ///< 使用内部时钟 + Tim0SlaveResetTIM = 1u, ///< å¤ä½åŠŸèƒ½ + Tim0SlaveTrigMode = 2u, ///< 触å‘æ¨¡å¼ + Tim0SlaveEClk = 3u, ///< å¤–éƒ¨æ—¶é’Ÿæ¨¡å¼ + Tim0SlaveCodeCnt1 = 4u, ///< 正交编ç è®¡æ•°æ¨¡å¼1 + Tim0SlaveCodeCnt2 = 5u, ///< 正交编ç è®¡æ•°æ¨¡å¼2 + Tim0SlaveCodeCnt3 = 6u, ///< 正交编ç è®¡æ•°æ¨¡å¼3 + Tim0SlaveGateCtrl = 7u, ///< 门控功能 +}en_tim0_m23_mscr_sms_t; + +/** + ****************************************************************************** + ** \brief 定时器è¿è¡ŒæŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (CTEN) + *****************************************************************************/ +typedef enum en_tim0_start +{ + Tim0CTENDisable = 0u, ///< åœæ­¢ + Tim0CTENEnable = 1u, ///< è¿è¡Œ +}en_tim0_start_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode0 é…置结构体定义(模å¼0) + *****************************************************************************/ +typedef struct stc_tim0_mode0_config +{ + en_tim0_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim0_m0cr_gatep_t enGateP; ///< 门控æžæ€§æŽ§åˆ¶ + boolean_t bEnGate; ///< 门控使能 + en_tim0_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + boolean_t bEnTog; ///< 翻转输出使能 + en_tim0_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim0_m0cr_md_t enCntMode; ///< 计数模å¼é…ç½® + + func_ptr_t pfnTim0Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim0_mode0_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode1 é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim0_mode1_config +{ + en_tim0_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim0_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + en_tim0_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim0_m1cr_oneshot_t enOneShot; ///< å•æ¬¡æµ‹é‡/循环测é‡é€‰æ‹© + + func_ptr_t pfnTim0Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] + +}stc_tim0_mode1_config_t; + +/** + ****************************************************************************** + ** \brief PWC输入é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim0_pwc_input_config +{ + en_tim0_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© + en_tim0_m1_mscr_ia0s_t enIA0Sel; ///< CHA0输入选择 + en_tim0_m1_mscr_ib0s_t enIB0Sel; ///< CHB0输入选择 + en_tim0_port_polarity_t enETRPhase; ///< ETR相ä½é€‰æ‹© + en_tim0_flt_t enFltETR; ///< ETR滤波设置 + en_tim0_flt_t enFltIA0; ///< CHA0滤波设置 + en_tim0_flt_t enFltIB0; ///< CHB0滤波设置 +}stc_tim0_pwc_input_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode23 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_mode23_config +{ + en_tim0_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim0_m23cr_dir_t enCntDir; ///< è®¡æ•°æ–¹å‘ + en_tim0_cr_timclkdiv_t enPRS; ///< 时钟预除频é…ç½® + en_tim0_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim0_m23cr_comp_t enPWMTypeSel; ///< PWM模å¼é€‰æ‹©ï¼ˆç‹¬ç«‹/互补） + en_tim0_m23cr_pwm2s_t enPWM2sSel; ///< OCREFAåŒç‚¹æ¯”较功能选择 + boolean_t bOneShot; ///< å•æ¬¡è§¦å‘模å¼ä½¿èƒ½/ç¦æ­¢ + boolean_t bURSSel; ///< æ›´æ–°æºé€‰æ‹© + + func_ptr_t pfnTim0Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim0_mode23_config_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_gate_config +{ + en_tim0_m23cr_csg_t enGateFuncSel; ///< Gate比较ã€æ•èŽ·åŠŸèƒ½é€‰æ‹© + boolean_t bGateRiseCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸Šæ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ + boolean_t bGateFallCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸‹æ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ +}stc_tim0_m23_gate_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“比较控制 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_compare_config +{ + en_tim0_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_fltr_ocm_t enCHxACmpCtrl; ///< CH0A通é“比较控制 + en_tim0_port_polarity_t enCHxAPolarity; ///< CH0A输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxACmpBufEn; ///< 比较A缓存功能 使能/ç¦æ­¢ + en_tim0_m23_cisa_cisb_t enCHxACmpIntSel; ///< CHA比较匹é…中断选择 + + en_tim0_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0B比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_fltr_ocm_t enCHxBCmpCtrl; ///< CH0B通é“比较控制 + en_tim0_port_polarity_t enCHxBPolarity; ///< CH0B输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxBCmpBufEn; ///< 比较B缓存功能 使能/ç¦æ­¢ + en_tim0_m23_cisa_cisb_t enCHxBCmpIntSel; ///< CHB0比较匹é…中断选择 +}stc_tim0_m23_compare_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“æ•èŽ·æŽ§åˆ¶ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_input_config +{ + en_tim0_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_crch0_cfx_crx_t enCHxACapSel; ///< CH0Aæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim0_flt_t enCHxAInFlt; ///< CH0A通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim0_port_polarity_t enCHxAPolarity; ///< CH0Aè¾“å…¥ç›¸ä½ + + en_tim0_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim0_m23_crch0_cfx_crx_t enCHxBCapSel; ///< CH0Bæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim0_flt_t enCHxBInFlt; ///< CH0B通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim0_port_polarity_t enCHxBPolarity; ///< CH0Bè¾“å…¥ç›¸ä½ + +}stc_tim0_m23_input_config_t; + +/** + ****************************************************************************** + ** \brief ETR输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_etr_input_config +{ + en_tim0_port_polarity_t enETRPolarity; ///< ETR输入æžæ€§è®¾ç½® + en_tim0_flt_t enETRFlt; ///< ETR滤波设置 +}stc_tim0_m23_etr_input_config_t; + +/** + ****************************************************************************** + ** \brief 刹车BK输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_bk_input_config +{ + boolean_t bEnBrake; ///< 刹车使能 + boolean_t bEnVC0Brake; ///< 使能VC0刹车 + boolean_t bEnVC1Brake; ///< 使能VC1刹车 + boolean_t bEnSafetyBk; ///< 使能safety刹车 + boolean_t bEnBKSync; ///< TIM0/TIM1/TIM2刹车åŒæ­¥ä½¿èƒ½ + en_tim0_m23_crchx_bks_t enBkCH0AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH0BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH1AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH1BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH2AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim0_m23_crchx_bks_t enBkCH2BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim0_port_polarity_t enBrakePolarity; ///< 刹车BK输入æžæ€§è®¾ç½® + en_tim0_flt_t enBrakeFlt; ///< 刹车BK滤波设置 +}stc_tim0_m23_bk_input_config_t; + +/** + ****************************************************************************** +** \brief 死区功能é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_dt_config +{ + boolean_t bEnDeadTime; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + uint8_t u8DeadTimeValue; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® +}stc_tim0_m23_dt_config_t; + +/** + ****************************************************************************** + ** \brief 触å‘ADCé…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_adc_trig_config +{ + boolean_t bEnTrigADC; ///< 触å‘ADC全局控制 + boolean_t bEnUevTrigADC; ///< 事件更新触å‘ADC + boolean_t bEnCH0ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH0BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH1ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH1BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH2ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH2BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC +}stc_tim0_m23_adc_trig_config_t; + +/** + ****************************************************************************** + ** \brief DMAè§¦å‘ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_trig_dma_config +{ + boolean_t bUevTrigDMA; ///< æ›´æ–° 触å‘DMA使能 + boolean_t bTITrigDMA; ///< Trig 触å‘DMA功能 + boolean_t bCmpA0TrigDMA; ///< CH0Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB0TrigDMA; ///< CH0Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA1TrigDMA; ///< CH1Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB1TrigDMA; ///< CH1Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA2TrigDMA; ///< CH2Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB2TrigDMA; ///< CH2Bæ•èŽ·æ¯”较触å‘DMA使能 + en_tim0_m23_mscr_ccds_t enCmpUevTrigDMA; ///< 比较模å¼ä¸‹DMA比较触å‘选择 +}stc_tim0_m23_trig_dma_config_t; + +/** + ****************************************************************************** + ** \brief ä¸»ä»Žæ¨¡å¼ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_master_slave_config +{ + en_tim0_m23_mscr_msm_t enMasterSlaveSel; ///< 主从模å¼é€‰æ‹© + en_tim0_m23_mscr_mms_t enMasterSrc; ///< 主模å¼è§¦å‘æºé€‰æ‹© + en_tim0_m23_mscr_sms_t enSlaveModeSel; ///< 从模å¼é€‰æ‹© + en_tim0_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© +}stc_tim0_m23_master_slave_config_t; + +/** + ****************************************************************************** + ** \brief OCREF清除功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim0_m23_OCREF_Clr_config +{ + en_tim0_m23ce_occs_t enOCRefClrSrcSel; ///< OCREF清除æºé€‰æ‹© + boolean_t bVCClrEn; ///< 是å¦ä½¿èƒ½æ¥è‡ªVCçš„OCREF_Clr +}stc_tim0_m23_OCREF_Clr_config_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//中断相关函数 + +//ä¸­æ–­æ ‡å¿—èŽ·å– +boolean_t Tim0_GetIntFlag(en_tim0_irq_type_t enTim0Irq); +//中断标志清除 +en_result_t Tim0_ClearIntFlag(en_tim0_irq_type_t enTim0Irq); +//所有中断标志清除 +en_result_t Tim0_ClearAllIntFlag(void); +//模å¼0中断使能 +en_result_t Tim0_Mode0_EnableIrq(void); +//模å¼1中断使能 +en_result_t Tim0_Mode1_EnableIrq (en_tim0_irq_type_t enTim0Irq); +//模å¼2中断使能 +en_result_t Tim0_Mode23_EnableIrq (en_tim0_irq_type_t enTim0Irq); +//模å¼0中断ç¦æ­¢ +en_result_t Tim0_Mode0_DisableIrq(void); +//模å¼1中断ç¦æ­¢ +en_result_t Tim0_Mode1_DisableIrq (en_tim0_irq_type_t enTim0Irq); +//模å¼2中断ç¦æ­¢ +en_result_t Tim0_Mode23_DisableIrq (en_tim0_irq_type_t enTim0Irq); + + +//模å¼0åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim0_Mode0_Init(stc_tim0_mode0_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim0_M0_Run(void); +en_result_t Tim0_M0_Stop(void); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim0_M0_ARRSet(uint16_t u16Data); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M0_Cnt16Set(uint16_t u16Data); +uint16_t Tim0_M0_Cnt16Get(void); +//32ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M0_Cnt32Set(uint32_t u32Data); +uint32_t Tim0_M0_Cnt32Get(void); +//翻转输出使能/ç¦æ­¢è®¾å®š +en_result_t Tim0_M0_EnTOG_Output(boolean_t bEnOutput); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim0_Mode1_Init(stc_tim0_mode1_config_t* pstcConfig); +//PWC 输入é…ç½® +en_result_t Tim0_M1_Input_Config(stc_tim0_pwc_input_config_t* pstcConfig); +//PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹© +en_result_t Tim0_M1_PWC_Edge_Sel(en_tim0_m1cr_Edge_t enEdgeSel); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim0_M1_Run(void); +en_result_t Tim0_M1_Stop(void); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M1_Cnt16Set(uint16_t u16Data); +uint16_t Tim0_M1_Cnt16Get(void); +//脉冲宽度测é‡ç»“æžœæ•°å€¼èŽ·å– +uint16_t Tim0_M1_PWC_CapValueGet(void); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim0_Mode23_Init(stc_tim0_mode23_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim0_M23_Run(void); +en_result_t Tim0_M23_Stop(void); +//PWM输出使能 +en_result_t Tim0_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim0_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim0_M23_Cnt16Set(uint16_t u16Data); +uint16_t Tim0_M23_Cnt16Get(void); +//比较æ•èŽ·å¯„存器CCR0A/CCR0B设置/è¯»å– +en_result_t Tim0_M23_CCR_Set(en_tim0_m23_ccrx_t enCCRSel, uint16_t u16Data); +uint16_t Tim0_M23_CCR_Get(en_tim0_m23_ccrx_t enCCRSel); +//PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择 +en_result_t Tim0_M23_GateFuncSel(stc_tim0_m23_gate_config_t* pstcConfig); +//主从模å¼é…ç½® +en_result_t Tim0_M23_MasterSlave_Set(stc_tim0_m23_master_slave_config_t* pstcConfig); +//CH0A/CH0B比较通é“控制 +en_result_t Tim0_M23_PortOutput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_compare_config_t* pstcConfig); +//CH0A/CH0B输入控制 +en_result_t Tim0_M23_PortInput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_input_config_t* pstcConfig); +//ERT输入控制 +en_result_t Tim0_M23_ETRInput_Config(stc_tim0_m23_etr_input_config_t* pstcConfig); +//刹车BK输入控制 +en_result_t Tim0_M23_BrakeInput_Config(stc_tim0_m23_bk_input_config_t* pstcConfig); +//触å‘ADC控制 +en_result_t Tim0_M23_TrigADC_Config(stc_tim0_m23_adc_trig_config_t* pstcConfig); +//死区功能 +en_result_t Tim0_M23_DT_Config(stc_tim0_m23_dt_config_t* pstcConfig); +//é‡å¤å‘¨æœŸè®¾ç½® +en_result_t Tim0_M23_SetValidPeriod(uint8_t u8ValidPeriod); +//OCREF清除功能 +en_result_t Tim0_M23_OCRefClr(stc_tim0_m23_OCREF_Clr_config_t* pstcConfig); +//使能DMA传输 +en_result_t Tim0_M23_EnDMA(stc_tim0_m23_trig_dma_config_t* pstcConfig); +//æ•èŽ·æ¯”较Aè½¯ä»¶è§¦å‘ +en_result_t Tim0_M23_EnSwTrigCapCmpA(en_tim0_channel_t enTim0Chx); +//æ•èŽ·æ¯”较Bè½¯ä»¶è§¦å‘ +en_result_t Tim0_M23_EnSwTrigCapCmpB(en_tim0_channel_t enTim0Chx); +//软件更新使能 +en_result_t Tim0_M23_EnSwUev(void); +//软件触å‘使能 +en_result_t Tim0_M23_EnSwTrig(void); +//软件刹车使能 +en_result_t Tim0_M23_EnSwBk(void); + + +//@} // Tim0Group + +#ifdef __cplusplus +#endif + + +#endif /* __BT_H__ */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer3.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer3.h new file mode 100644 index 0000000000..1ac153ab94 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/timer3.h @@ -0,0 +1,788 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file bt.h + ** + ** 基本定时器数æ®ç»“æž„åŠAPI声明 + ** @link BT Timer3 Group Some description @endlink + ** + ** History: + ** - 2018-04-29 Husj First Version + ** + *****************************************************************************/ + +#ifndef __TIMER3_H__ +#define __TIMER3_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup Tim3Group Base Timer (BT) + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Timer3 通é“定义 + *****************************************************************************/ +typedef enum en_tim3_channel +{ + Tim3CH0 = 0u, ///< Timer3通é“0 + Tim3CH1 = 1u, ///< Timer3通é“1 + Tim3CH2 = 2u, ///< Timer3通é“2 +}en_tim3_channel_t; + +/** + ****************************************************************************** + ** \brief 工作模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (MODE)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_work_mode +{ + Tim3WorkMode0 = 0u, ///< å®šæ—¶å™¨æ¨¡å¼ + Tim3WorkMode1 = 1u, ///< PWCæ¨¡å¼ + Tim3WorkMode2 = 2u, ///< é”¯é½¿æ³¢æ¨¡å¼ + Tim3WorkMode3 = 3u, ///< ä¸‰è§’æ³¢æ¨¡å¼ +}en_tim3_work_mode_t; + +/** + ****************************************************************************** + ** \brief æžæ€§æŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (GATE_P)(模å¼0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_gatep +{ + Tim3GatePositive = 0u, ///< 高电平有效 + Tim3GateOpposite = 1u, ///< 低电平有效 +}en_tim3_m0cr_gatep_t; + +/** + ****************************************************************************** + ** \brief TIM3 预除频选择 (PRS)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_timclkdiv +{ + Tim3PCLKDiv1 = 0u, ///< Div 1 + Tim3PCLKDiv2 = 1u, ///< Div 2 + Tim3PCLKDiv4 = 2u, ///< Div 4 + Tim3PCLKDiv8 = 3u, ///< Div 8 + Tim3PCLKDiv16 = 4u, ///< Div 16 + Tim3PCLKDiv32 = 5u, ///< Div 32 + Tim3PCLKDiv64 = 6u, ///< Div 64 + Tim3PCLKDiv256 = 7u, ///< Div 256 +}en_tim3_cr_timclkdiv_t; + +/** + ****************************************************************************** + ** \brief 计数/定时器功能选择数æ®ç±»åž‹é‡å®šä¹‰ (CT)(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_cr_ct +{ + Tim3Timer = 0u, ///< 定时器功能，计数时钟为内部PCLK + Tim3Counter = 1u, ///< 计数器功能，计数时钟为外部ETR +}en_tim3_cr_ct_t; + + +/** + ****************************************************************************** + ** \brief 定时器工作模å¼æ•°æ®ç±»åž‹é‡å®šä¹‰ (MD)(模å¼0) + *****************************************************************************/ +typedef enum en_tim3_m0cr_md +{ + Tim332bitFreeMode = 0u, ///< 32ä½è®¡æ•°å™¨/定时器 + Tim316bitArrMode = 1u, ///< 自动é‡è£…è½½16ä½è®¡æ•°å™¨/定时器 +}en_tim3_m0cr_md_t; + +/** + ****************************************************************************** +** \brief TIM3中断类型数æ®ç±»åž‹é‡å®šä¹‰(模å¼0/1/23) + *****************************************************************************/ +typedef enum en_tim3_irq_type +{ + Tim3UevIrq = 0u, ///< 溢出/事件更新中断 + Tim3CA0Irq = 2u, ///< CH0Aæ•èŽ·/比较中断(仅模å¼1/23存在) + Tim3CA1Irq = 3u, ///< CH1Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CA2Irq = 4u, ///< CH2Aæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CB0Irq = 5u, ///< CH0Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CB1Irq = 6u, ///< CH1Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CB2Irq = 7u, ///< CH2Bæ•èŽ·/比较中断(仅模å¼23存在) + Tim3CA0E = 8u, ///< CH0Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CA1E = 9u, ///< CH1Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CA2E = 10u, ///< CH2Aæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CB0E = 11u, ///< CH0Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CB1E = 12u, ///< CH1Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3CB2E = 13u, ///< CH2Bæ•èŽ·æ•°æ®ä¸¢å¤±æ ‡å¿—(仅模å¼23存在)(ä¸æ˜¯ä¸­æ–­) + Tim3BkIrq = 14u, ///< 刹车中断(仅模å¼23存在） + Tim3TrigIrq = 15u, ///< 触å‘中断(仅模å¼23存在） +}en_tim3_irq_type_t; + +/** + ****************************************************************************** + ** \brief 测é‡å¼€å§‹ç»“æŸæ•°æ®ç±»åž‹é‡å®šä¹‰ (Edg1stEdg2nd)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_Edge +{ + Tim3PwcRiseToRise = 0u, ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + Tim3PwcFallToRise = 1u, ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + Tim3PwcRiseToFall = 2u, ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + Tim3PwcFallToFall = 3u, ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) +}en_tim3_m1cr_Edge_t; + +/** + ****************************************************************************** + ** \brief PWC测é‡æµ‹è¯•æ¨¡å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (Oneshot)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1cr_oneshot +{ + Tim3PwcCycleDetect = 0u, ///< PWCå¾ªçŽ¯æµ‹é‡ + Tim3PwcOneShotDetect = 1u, ///< PWCå•æ¬¡æµ‹é‡ +}en_tim3_m1cr_oneshot_t; + +/** + ****************************************************************************** + ** \brief PWC IA0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ia0s +{ + Tim3IA0Input = 0u, ///< IAO输入 + Tim3XORInput = 1u, ///< IA0 ETR GATE XOR(TIM0/1/2)/IA0 IA1 IA2 XOR(TIM3) +}en_tim3_m1_mscr_ia0s_t; + +/** + ****************************************************************************** + ** \brief PWC IB0选择数æ®ç±»åž‹é‡å®šä¹‰ (IA0S)(模å¼1) + *****************************************************************************/ +typedef enum en_tim3_m1_mscr_ib0s +{ + Tim3IB0Input = 0u, ///< IBO输入 + Tim3TsInput = 1u, ///< 内部触å‘TSé€‰æ‹©ä¿¡å· +}en_tim3_m1_mscr_ib0s_t; + +/** + ****************************************************************************** + ** \brief 输出æžæ€§ã€è¾“å…¥ç›¸ä½ æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCPA0/CCPB0/ETP/BKP)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim3_port_polarity +{ + Tim3PortPositive = 0u, ///< 正常输入输出 + Tim3PortOpposite = 1u, ///< åå‘输入输出 +}en_tim3_port_polarity_t; + +/** + ****************************************************************************** + ** \brief 滤波选择数æ®ç±»åž‹é‡å®šä¹‰ (FLTET/FLTA0/FLAB0)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim3_flt +{ + Tim3FltNone = 0u, ///< 无滤波 + Tim3FltPCLKCnt3 = 4u, ///< PCLK 3个连续有效 + Tim3FltPCLKDiv4Cnt3 = 5u, ///< PCLK/4 3个连续有效 + Tim3FltPCLKDiv16Cnt3 = 6u, ///< PCLK/16 3个连续有效 + Tim3FltPCLKDiv64Cnt3 = 7u, ///< PCLK/64 3个连续有效 +}en_tim3_flt_t; + +/** + ****************************************************************************** + ** \brief 通é“比较控制 æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCMA/OCMB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_fltr_ocm +{ + Tim3ForceLow = 0u, ///< 强制为0 + Tim3ForceHigh = 1u, ///< 强制为1 + Tim3CMPForceLow = 2u, ///< 比较匹é…时强制为0 + Tim3CMPForceHigh = 3u, ///< 比较匹é…时强制为1 + Tim3CMPInverse = 4u, ///< 比较匹é…时翻转电平 + Tim3CMPOnePrdHigh = 5u, ///< 比较匹é…时输出一个计数周期的高电平 + Tim3PWMMode1 = 6u, ///< 通é“控制为PWM mode 1 + Tim3PWMMode2 = 7u, ///< 通é“控制为PWM mode 2 +}en_tim3_m23_fltr_ocm_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼TSæ•°æ®ç±»åž‹é‡å®šä¹‰ (TS)(模å¼1/23) + *****************************************************************************/ +typedef enum en_tim3_mscr_ts +{ + Tim3Ts0ETR = 0u, ///< ETR外部输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim3Ts1TIM0TRGO = 1u, ///< Timer0çš„TRGOè¾“å‡ºä¿¡å· + Tim3Ts2TIM1TRGO = 2u, ///< Timer1çš„TRGOè¾“å‡ºä¿¡å· + Tim3Ts3TIM2TRGO = 3u, ///< Timer2çš„TRGOè¾“å‡ºä¿¡å· + Tim3Ts4TIM3TRGO = 4u, ///< Timer3çš„TRGOè¾“å‡ºä¿¡å· + //Tim3Ts5IA0ED = 5u, ///< 无效 + Tim3Ts6IAFP = 6u, ///< CH0A 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡å· + Tim3Ts7IBFP = 7u, ///< CH0B 外部输输入滤波åŽçš„相ä½é€‰æ‹©ä¿¡ +}en_tim3_mscr_ts_t; + +/** + ****************************************************************************** + ** \brief PWM输出模å¼é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (COMP)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_comp +{ + Tim3IndependentPWM = 0u, ///< 独立PWM输出 + Tim3ComplementaryPWM = 1u, ///< 互补PWM输出 +}en_tim3_m23cr_comp_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (DIR)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_dir +{ + Tim3CntUp = 0u, ///< å‘上计数 + Tim3CntDown = 1u, ///< å‘下计数 +}en_tim3_m23cr_dir_t; + +/** + ****************************************************************************** + ** \brief 计数方å‘选择数æ®ç±»åž‹é‡å®šä¹‰ (PWM2S)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_pwm2s +{ + Tim3DoublePointCmp = 0u, ///< åŒç‚¹æ¯”较使能，使用CCRA,CCRB比较控制OCREFA输出 + Tim3SinglePointCmp = 1u, ///< å•ç‚¹æ¯”较使能，使用CCRA比较控制OCREFA输出 +}en_tim3_m23cr_pwm2s_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 选择数æ®ç±»åž‹é‡å®šä¹‰ (CSG)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23cr_csg +{ + Tim3PWMCompGateCmpOut = 0u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为比较输出 + Tim3PWMCompGateCapIn = 1u, ///< 在PWM互补模å¼ä¸‹ï¼ŒGate作为æ•èŽ·è¾“å…¥ +}en_tim3_m23cr_csg_t; + + +/** + ****************************************************************************** + ** \brief 比较æ•èŽ·å¯„存器 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCR0A,CCR0B)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_ccrx +{ + Tim3CCR0A = 0u, ///< CCR0A比较æ•èŽ·å¯„存器 + Tim3CCR0B = 1u, ///< CCR0B比较æ•èŽ·å¯„存器 + Tim3CCR1A = 2u, ///< CCR1A比较æ•èŽ·å¯„存器 + Tim3CCR1B = 3u, ///< CCR1B比较æ•èŽ·å¯„存器 + Tim3CCR2A = 4u, ///< CCR2A比较æ•èŽ·å¯„存器 + Tim3CCR2B = 5u, ///< CCR2B比较æ•èŽ·å¯„存器 +}en_tim3_m23_ccrx_t; + +/** + ****************************************************************************** + ** \brief OCREFæ¸…é™¤æº é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (OCCS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23ce_occs +{ + Tim3OC_Ref_Clr = 0u, ///< æ¥è‡ªVCçš„OC_Ref_Clr + Tim3ETRf = 1u, ///< 外部ETRf +}en_tim3_m23ce_occs_t; + +/** + ****************************************************************************** + ** \brief 比较匹é…ä¸­æ–­æ¨¡å¼ é€‰æ‹©æ•°æ®ç±»åž‹é‡å®šä¹‰ (CIS/CISB)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_cisa_cisb +{ + Tim3CmpIntNone = 0u, ///< 无比较匹é…中断 + Tim3CmpIntRise = 1u, ///< 比较匹é…上å‡æ²¿ä¸­æ–­ + Tim3CmpIntFall = 2u, ///< 比较匹é…下é™æ²¿ä¸­æ–­ + Tim3CmpIntRiseFall = 3u, ///< 比较匹é…上å‡æ²¿ä¸‹é™æ²¿ä¸­æ–­ +}en_tim3_m23_cisa_cisb_t; + +/** + ****************************************************************************** + ** \brief TIM3端å£æŽ§åˆ¶ - 刹车时CHx输出状æ€æŽ§åˆ¶(BKSA/BKSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crchx_bks +{ + Tim3CHxBksHiZ = 0u, ///< 刹车使能时，CHx端å£è¾“å‡ºé«˜é˜»æ€ + Tim3CHxBksNorm = 1u, ///< 刹车使能时，CHx端å£æ­£å¸¸è¾“出 + Tim3CHxBksLow = 2u, ///< 刹车使能时，CHx端å£è¾“出低电平 + Tim3CHxBksHigh = 3u, ///< 刹车使能时，CHx端å£è¾“出高电平 +}en_tim3_m23_crchx_bks_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·(CRx/CFx)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_cfx_crx +{ + Tim3CHxCapNone = 0u, ///< CHx通é“æ•èŽ·ç¦æ­¢ + Tim3CHxCapRise = 1u, ///< CHx通é“上å‡æ²¿æ•èŽ·ä½¿èƒ½ + Tim3CHxCapFall = 2u, ///< CHx通é“下é™æ²¿æ•èŽ·ä½¿èƒ½ + Tim3CHxCapFallRise = 3u, ///< CHx通é“上å‡æ²¿ä¸‹é™æ²¿æ•èŽ·éƒ½ä½¿èƒ½ +}en_tim3_m23_crch0_cfx_crx_t; + +/** + ****************************************************************************** +** \brief TIM3端å£æŽ§åˆ¶ - CHx比较æ•èŽ·æ¨¡å¼(CSA/CSB)(模å¼23) + ** + ** \note + ******************************************************************************/ +typedef enum en_tim3_m23_crch0_csa_csb +{ + Tim3CHxCmpMode = 0u, ///< CHx通é“è®¾ç½®ä¸ºæ¯”è¾ƒæ¨¡å¼ + Tim3CHxCapMode = 1u, ///< CHx通é“设置为æ•èŽ·æ¨¡å¼ +}en_tim3_m23_crch0_csa_csb_t; + +/** + ****************************************************************************** + ** \brief 比较模å¼ä¸‹ DMA比较触å‘选择 æ•°æ®ç±»åž‹é‡å®šä¹‰ (CCDS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_ccds +{ + Tim3CmpTrigDMA = 0u, ///< 比较匹é…触å‘DMA + Tim3UEVTrigDMA = 1u, ///< 事件更新代替比较匹é…触å‘DMA +}en_tim3_m23_mscr_ccds_t; + +/** + ****************************************************************************** + ** \brief 主从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (MSM)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_msm +{ + Tim3SlaveMode = 0u, ///< ä»Žæ¨¡å¼ + Tim3MasterMode = 1u, ///< ä¸»æ¨¡å¼ +}en_tim3_m23_mscr_msm_t; + +/** + ****************************************************************************** + ** \brief 触å‘主模å¼è¾“å‡ºæº æ•°æ®ç±»åž‹é‡å®šä¹‰ (MMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_mms +{ + Tim3MasterUG = 0u, ///< UG(软件更新)æº + Tim3MasterCTEN = 1u, ///< CTENæº + Tim3MasterUEV = 2u, ///< UEVæ›´æ–°æº + Tim3MasterCMPSO = 3u, ///< 比较匹é…é€‰æ‹©è¾“å‡ºæº + Tim3MasterOCA0Ref = 4u, ///< OCA0_Refæº + Tim3MasterOCB0Ref = 5u, ///< OCB0_Refæº + //Tim3MasterOCB0Ref = 6u, + //Tim3MasterOCB0Ref = 7u, +}en_tim3_m23_mscr_mms_t; + +/** + ****************************************************************************** + ** \brief 触å‘从模å¼é€‰æ‹© æ•°æ®ç±»åž‹é‡å®šä¹‰ (SMS)(模å¼23) + *****************************************************************************/ +typedef enum en_tim3_m23_mscr_sms +{ + Tim3SlaveIClk = 0u, ///< 使用内部时钟 + Tim3SlaveResetTIM = 1u, ///< å¤ä½åŠŸèƒ½ + Tim3SlaveTrigMode = 2u, ///< 触å‘æ¨¡å¼ + Tim3SlaveEClk = 3u, ///< å¤–éƒ¨æ—¶é’Ÿæ¨¡å¼ + Tim3SlaveCodeCnt1 = 4u, ///< 正交编ç è®¡æ•°æ¨¡å¼1 + Tim3SlaveCodeCnt2 = 5u, ///< 正交编ç è®¡æ•°æ¨¡å¼2 + Tim3SlaveCodeCnt3 = 6u, ///< 正交编ç è®¡æ•°æ¨¡å¼3 + Tim3SlaveGateCtrl = 7u, ///< 门控功能 +}en_tim3_m23_mscr_sms_t; + +/** + ****************************************************************************** + ** \brief 定时器è¿è¡ŒæŽ§åˆ¶æ•°æ®ç±»åž‹é‡å®šä¹‰ (CTEN) + *****************************************************************************/ +typedef enum en_tim3_start +{ + Tim3CTENDisable = 0u, ///< åœæ­¢ + Tim3CTENEnable = 1u, ///< è¿è¡Œ +}en_tim3_start_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode0 é…置结构体定义(模å¼0) + *****************************************************************************/ +typedef struct stc_tim3_mode0_config +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim3_m0cr_gatep_t enGateP; ///< 门控æžæ€§æŽ§åˆ¶ + boolean_t bEnGate; ///< 门控使能 + en_tim3_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + boolean_t bEnTog; ///< 翻转输出使能 + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m0cr_md_t enCntMode; ///< 计数模å¼é…ç½® + + func_ptr_t pfnTim3Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim3_mode0_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode1 é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim3_mode1_config +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim3_cr_timclkdiv_t enPRS; ///< 预除频é…ç½® + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m1cr_oneshot_t enOneShot; ///< å•æ¬¡æµ‹é‡/循环测é‡é€‰æ‹© + + func_ptr_t pfnTim3Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] + +}stc_tim3_mode1_config_t; + +/** + ****************************************************************************** + ** \brief PWC输入é…置结构体定义(模å¼1) + *****************************************************************************/ +typedef struct stc_tim3_pwc_input_config +{ + en_tim3_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© + en_tim3_m1_mscr_ia0s_t enIA0Sel; ///< CHA0输入选择 + en_tim3_m1_mscr_ib0s_t enIB0Sel; ///< CHB0输入选择 + en_tim3_port_polarity_t enETRPhase; ///< ETR相ä½é€‰æ‹© + en_tim3_flt_t enFltETR; ///< ETR滤波设置 + en_tim3_flt_t enFltIA0; ///< CHA0滤波设置 + en_tim3_flt_t enFltIB0; ///< CHB0滤波设置 +}stc_tim3_pwc_input_config_t; + +/** + ****************************************************************************** + ** \brief TIM3 mode23 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_mode23_config +{ + en_tim3_work_mode_t enWorkMode; ///< 工作模å¼è®¾ç½® + en_tim3_m23cr_dir_t enCntDir; ///< è®¡æ•°æ–¹å‘ + en_tim3_cr_timclkdiv_t enPRS; ///< 时钟预除频é…ç½® + en_tim3_cr_ct_t enCT; ///< 定时/计数功能选择 + en_tim3_m23cr_comp_t enPWMTypeSel; ///< PWM模å¼é€‰æ‹©ï¼ˆç‹¬ç«‹/互补） + en_tim3_m23cr_pwm2s_t enPWM2sSel; ///< OCREFAåŒç‚¹æ¯”较功能选择 + boolean_t bOneShot; ///< å•æ¬¡è§¦å‘模å¼ä½¿èƒ½/ç¦æ­¢ + boolean_t bURSSel; ///< æ›´æ–°æºé€‰æ‹© + + func_ptr_t pfnTim3Cb; ///< Timer3中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_tim3_mode23_config_t; + +/** + ****************************************************************************** + ** \brief GATE在PWM互补模å¼ä¸‹æ•èŽ·æˆ–比较功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_gate_config +{ + en_tim3_m23cr_csg_t enGateFuncSel; ///< Gate比较ã€æ•èŽ·åŠŸèƒ½é€‰æ‹© + boolean_t bGateRiseCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸Šæ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ + boolean_t bGateFallCap; ///< GATE作为æ•èŽ·åŠŸèƒ½æ—¶ï¼Œä¸‹æ²¿æ•èŽ·æœ‰æ•ˆæŽ§åˆ¶ +}stc_tim3_m23_gate_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“比较控制 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_compare_config +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_fltr_ocm_t enCHxACmpCtrl; ///< CH0A通é“比较控制 + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0A输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxACmpBufEn; ///< 比较A缓存功能 使能/ç¦æ­¢ + en_tim3_m23_cisa_cisb_t enCHxACmpIntSel; ///< CHA比较匹é…中断选择 + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0B比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_fltr_ocm_t enCHxBCmpCtrl; ///< CH0B通é“比较控制 + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0B输出æžæ€§æŽ§åˆ¶ + boolean_t bCHxBCmpBufEn; ///< 比较B缓存功能 使能/ç¦æ­¢ + en_tim3_m23_cisa_cisb_t enCHxBCmpIntSel; ///< CHB0比较匹é…中断选择 +}stc_tim3_m23_compare_config_t; + +/** + ****************************************************************************** + ** \brief CHA/CHB通é“æ•èŽ·æŽ§åˆ¶ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_input_config +{ + en_tim3_m23_crch0_csa_csb_t enCHxACmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_crch0_cfx_crx_t enCHxACapSel; ///< CH0Aæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim3_flt_t enCHxAInFlt; ///< CH0A通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim3_port_polarity_t enCHxAPolarity; ///< CH0Aè¾“å…¥ç›¸ä½ + + en_tim3_m23_crch0_csa_csb_t enCHxBCmpCap; ///< CH0A比较/æ•èŽ·åŠŸèƒ½é€‰æ‹© + en_tim3_m23_crch0_cfx_crx_t enCHxBCapSel; ///< CH0Bæ•èŽ·è¾¹æ²¿é€‰æ‹© + en_tim3_flt_t enCHxBInFlt; ///< CH0B通é“æ•èŽ·æ»¤æ³¢æŽ§åˆ¶ + en_tim3_port_polarity_t enCHxBPolarity; ///< CH0Bè¾“å…¥ç›¸ä½ + +}stc_tim3_m23_input_config_t; + +/** + ****************************************************************************** + ** \brief ETR输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_etr_input_config +{ + en_tim3_port_polarity_t enETRPolarity; ///< ETR输入æžæ€§è®¾ç½® + en_tim3_flt_t enETRFlt; ///< ETR滤波设置 +}stc_tim3_m23_etr_input_config_t; + +/** + ****************************************************************************** + ** \brief 刹车BK输入相ä½æ»¤æ³¢é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_bk_input_config +{ + boolean_t bEnBrake; ///< 刹车使能 + boolean_t bEnVC0Brake; ///< 使能VC0刹车 + boolean_t bEnVC1Brake; ///< 使能VC1刹车 + boolean_t bEnSafetyBk; ///< 使能safety刹车 + boolean_t bEnBKSync; ///< TIM0/TIM1/TIM2刹车åŒæ­¥ä½¿èƒ½ + en_tim3_m23_crchx_bks_t enBkCH0AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH0BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH1AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH1BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH2AStat; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + en_tim3_m23_crchx_bks_t enBkCH2BStat; ///< 刹车时CHB端å£çŠ¶æ€è®¾ç½® + en_tim3_port_polarity_t enBrakePolarity; ///< 刹车BK输入æžæ€§è®¾ç½® + en_tim3_flt_t enBrakeFlt; ///< 刹车BK滤波设置 +}stc_tim3_m23_bk_input_config_t; + +/** + ****************************************************************************** +** \brief 死区功能é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_dt_config +{ + boolean_t bEnDeadTime; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® + uint8_t u8DeadTimeValue; ///< 刹车时CHA端å£çŠ¶æ€è®¾ç½® +}stc_tim3_m23_dt_config_t; + +/** + ****************************************************************************** + ** \brief 触å‘ADCé…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_adc_trig_config +{ + boolean_t bEnTrigADC; ///< 触å‘ADC全局控制 + boolean_t bEnUevTrigADC; ///< 事件更新触å‘ADC + boolean_t bEnCH0ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH0BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH1ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH1BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC + boolean_t bEnCH2ACmpTrigADC; ///< CH0A比较匹é…触å‘ADC + boolean_t bEnCH2BCmpTrigADC; ///< CH0B比较匹é…触å‘ADC +}stc_tim3_m23_adc_trig_config_t; + +/** + ****************************************************************************** + ** \brief DMAè§¦å‘ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_trig_dma_config +{ + boolean_t bUevTrigDMA; ///< æ›´æ–° 触å‘DMA使能 + boolean_t bTITrigDMA; ///< Trig 触å‘DMA功能 + boolean_t bCmpA0TrigDMA; ///< CH0Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB0TrigDMA; ///< CH0Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA1TrigDMA; ///< CH1Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB1TrigDMA; ///< CH1Bæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpA2TrigDMA; ///< CH2Aæ•èŽ·æ¯”较触å‘DMA使能 + boolean_t bCmpB2TrigDMA; ///< CH2Bæ•èŽ·æ¯”较触å‘DMA使能 + en_tim3_m23_mscr_ccds_t enCmpUevTrigDMA; ///< 比较模å¼ä¸‹DMA比较触å‘选择 +}stc_tim3_m23_trig_dma_config_t; + +/** + ****************************************************************************** + ** \brief ä¸»ä»Žæ¨¡å¼ é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_master_slave_config +{ + en_tim3_m23_mscr_msm_t enMasterSlaveSel; ///< 主从模å¼é€‰æ‹© + en_tim3_m23_mscr_mms_t enMasterSrc; ///< 主模å¼è§¦å‘æºé€‰æ‹© + en_tim3_m23_mscr_sms_t enSlaveModeSel; ///< 从模å¼é€‰æ‹© + en_tim3_mscr_ts_t enTsSel; ///< 触å‘输入æºé€‰æ‹© +}stc_tim3_m23_master_slave_config_t; + +/** + ****************************************************************************** + ** \brief OCREF清除功能 é…置结构体定义(模å¼23) + *****************************************************************************/ +typedef struct stc_tim3_m23_OCREF_Clr_config +{ + en_tim3_m23ce_occs_t enOCRefClrSrcSel; ///< OCREF清除æºé€‰æ‹© + boolean_t bVCClrEn; ///< 是å¦ä½¿èƒ½æ¥è‡ªVCçš„OCREF_Clr +}stc_tim3_m23_OCREF_Clr_config_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +//中断相关函数 + +//ä¸­æ–­æ ‡å¿—èŽ·å– +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq); +//中断标志清除 +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq); +//所有中断标志清除 +en_result_t Tim3_ClearAllIntFlag(void); +//模å¼0中断使能 +en_result_t Tim3_Mode0_EnableIrq(void); +//模å¼1中断使能 +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//模å¼2中断使能 +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq); +//模å¼0中断ç¦æ­¢ +en_result_t Tim3_Mode0_DisableIrq(void); +//模å¼1中断ç¦æ­¢ +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq); +//模å¼2中断ç¦æ­¢ +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq); + + +//模å¼0åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim3_M0_Run(void); +en_result_t Tim3_M0_Stop(void); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim3_M0_ARRSet(uint16_t u16Data); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M0_Cnt16Get(void); +//32ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data); +uint32_t Tim3_M0_Cnt32Get(void); +//翻转输出使能/ç¦æ­¢è®¾å®š +en_result_t Tim3_M0_EnTOG_Output(boolean_t bEnOutput); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_config_t* pstcConfig); +//PWC 输入é…ç½® +en_result_t Tim3_M1_Input_Config(stc_tim3_pwc_input_config_t* pstcConfig); +//PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹© +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim3_M1_Run(void); +en_result_t Tim3_M1_Stop(void); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M1_Cnt16Get(void); +//脉冲宽度测é‡ç»“æžœæ•°å€¼èŽ·å– +uint16_t Tim3_M1_PWC_CapValueGet(void); + + +//模å¼1åˆå§‹åŒ–åŠç›¸å…³åŠŸèƒ½æ“作 + +//timeré…ç½®åŠåˆå§‹åŒ– +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_config_t* pstcConfig); +//timer å¯åŠ¨/åœæ­¢ +en_result_t Tim3_M23_Run(void); +en_result_t Tim3_M23_Stop(void); +//PWM输出使能 +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput); +//é‡è½½å€¼è®¾ç½® +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn); +//16ä½è®¡æ•°å€¼è®¾ç½®/èŽ·å– +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data); +uint16_t Tim3_M23_Cnt16Get(void); +//比较æ•èŽ·å¯„存器CCR0A/CCR0B设置/è¯»å– +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data); +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel); +//PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择 +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_config_t* pstcConfig); +//主从模å¼é…ç½® +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_config_t* pstcConfig); +//CH0A/CH0B比较通é“控制 +en_result_t Tim3_M23_PortOutput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_config_t* pstcConfig); +//CH0A/CH0B输入控制 +en_result_t Tim3_M23_PortInput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_config_t* pstcConfig); +//ERT输入控制 +en_result_t Tim3_M23_ETRInput_Config(stc_tim3_m23_etr_input_config_t* pstcConfig); +//刹车BK输入控制 +en_result_t Tim3_M23_BrakeInput_Config(stc_tim3_m23_bk_input_config_t* pstcConfig); +//触å‘ADC控制 +en_result_t Tim3_M23_TrigADC_Config(stc_tim3_m23_adc_trig_config_t* pstcConfig); +//死区功能 +en_result_t Tim3_M23_DT_Config(stc_tim3_m23_dt_config_t* pstcConfig); +//é‡å¤å‘¨æœŸè®¾ç½® +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod); +//OCREF清除功能 +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_config_t* pstcConfig); +//使能DMA传输 +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_config_t* pstcConfig); +//æ•èŽ·æ¯”较Aè½¯ä»¶è§¦å‘ +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx); +//æ•èŽ·æ¯”较Bè½¯ä»¶è§¦å‘ +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx); +//软件更新使能 +en_result_t Tim3_M23_EnSwUev(void); +//软件触å‘使能 +en_result_t Tim3_M23_EnSwTrig(void); +//软件刹车使能 +en_result_t Tim3_M23_EnSwBk(void); + + +//@} // Tim3Group + +#ifdef __cplusplus +#endif + + +#endif /* __BT_H__ */ +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/trim.h b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/trim.h new file mode 100644 index 0000000000..7534eb0269 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/inc/trim.h @@ -0,0 +1,186 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file trim.h + ** + ** TRIM æ•°æ®ç»“æž„åŠAPI声明 + ** + ** + ** History: + ** - 2018-04-21 Lux V1.0 + ** + *****************************************************************************/ + +#ifndef __TRIM_H__ +#define __TRIM_H__ + +/***************************************************************************** + * Include files + *****************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup TrimGroup Clock Trimming (TRIM) + ** + ******************************************************************************/ +//@{ + +/****************************************************************************** + ** Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + + /** + ****************************************************************************** + ** \brief 监测模å¼ä½¿èƒ½æžšä¸¾é‡å®šä¹‰ (MON_EN) + *****************************************************************************/ +typedef enum en_trim_monitor +{ + TrimMonDisable = 0u, ///< ç¦æ­¢ + TrimMonEnable = 1u, ///< 使能 +}en_trim_monitor_t; + + /** + ****************************************************************************** + ** \brief 待校准/监测时钟选择枚举é‡å®šä¹‰ (CALCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_calclksel +{ + TrimCalRCH = 0u, ///< RCH + TrimCalXTH = 1u, ///< XTH + TrimCalRCL = 2u, ///< RCL + TrimCalXTL = 3u, ///< XTL + TrimCalPLL = 4u, ///< PLL +}en_trim_calclksel_t; + +/** + ****************************************************************************** + ** \brief å‚考时钟选择枚举é‡å®šä¹‰ (REFCLK_SEL) + *****************************************************************************/ +typedef enum en_trim_refclksel +{ + TrimRefRCH = 0u, ///< RCH + TrimRefXTH = 1u, ///< XTH + TrimRefRCL = 2u, ///< RCL + TrimRefXTL = 3u, ///< XTL + TrimRefIRC10K = 4u, ///< IRC10K + TrimRefExtClk = 5u, ///< 外部输入时钟 +}en_trim_refclksel_t; + +/** + ****************************************************************************** + ** \brief 中断标志类型枚举é‡å®šä¹‰ + *****************************************************************************/ +typedef enum en_trim_inttype +{ + TrimStop = 0u, ///< å‚考计数器åœæ­¢æ ‡å¿— + TrimCalCntOf = 1u, ///< 校准计数器溢出标志 + TrimXTLFault = 2u, ///< XTL 失效标志 + TrimXTHFault = 3u, ///< XTH 失效标志 + TrimPLLFault = 4u, ///< PLL 失效标志 +}en_trim_inttype_t; + +/** + ****************************************************************************** + ** \brief TRIM é…置结构体定义 + *****************************************************************************/ +typedef struct stc_trim_config +{ + en_trim_monitor_t enMON; ///< 监测模å¼ä½¿èƒ½ + en_trim_calclksel_t enCALCLK; ///< 校准时钟选择 + uint32_t u32CalCon; ///< 校准计数器溢出值é…ç½® + en_trim_refclksel_t enREFCLK; ///< å‚考时钟选择 + uint32_t u32RefCon; ///< å‚考计数器åˆå€¼é…ç½® + + func_ptr_t pfnTrimCb; ///< TRIM 中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] +}stc_trim_config_t; + +/****************************************************************************** + * Global variable declarations ('extern', definition in C source) + *****************************************************************************/ + +/****************************************************************************** + * Global function prototypes (definition in C source) + *****************************************************************************/ +///<<功能é…ç½®åŠæ“作函数 +///IFR_f.REGIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcRegIrq) + { + stcAdcIrqCalbaks.pfnAdcRegIrq(); + } + M0P_ADC->ICR_f.REGIC = 0u; + } + + if (TRUE == M0P_ADC->IFR_f.HTIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcHhtIrq) + { + stcAdcIrqCalbaks.pfnAdcHhtIrq(); + } + M0P_ADC->ICR_f.HTIC = 0u; + } + + if (TRUE == M0P_ADC->IFR_f.LTIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcLltIrq) + { + stcAdcIrqCalbaks.pfnAdcLltIrq(); + } + M0P_ADC->ICR_f.LTIC = 0u; + } + + if (TRUE == M0P_ADC->IFR_f.SGLIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcIrq) + { + stcAdcIrqCalbaks.pfnAdcIrq(); + } + M0P_ADC->ICR_f.SGLIC = 0u; + } + if(TRUE == M0P_ADC->IFR_f.SQRIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcSQRIrq) + { + stcAdcIrqCalbaks.pfnAdcSQRIrq(); + } + M0P_ADC->ICR_f.SQRIC = 0u; + } + if(TRUE == M0P_ADC->IFR_f.JQRIF) + { + if (NULL != stcAdcIrqCalbaks.pfnAdcJQRIrq) + { + stcAdcIrqCalbaks.pfnAdcJQRIrq(); + } + M0P_ADC->ICR_f.JQRIC = 0u; + } +} + +/** + * \brief + * é…ç½®ADCä¸­æ–­å‡½æ•°å…¥å£ + * + * \param [in] pstcAdcIrqCfg ADC中断é…置指针 + * \param [in] pstcAdcIrqCalbaks ADC中断回调函数指针 + * + * \retval æ—  + */ +void Adc_ConfigIrq(stc_adc_irq_t* pstcAdcIrqCfg, + stc_adc_irq_calbakfn_pt_t* pstcAdcIrqCalbaks) +{ + if (TRUE == pstcAdcIrqCfg->bAdcIrq) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcIrq) + { + stcAdcIrqCalbaks.pfnAdcIrq = pstcAdcIrqCalbaks->pfnAdcIrq; + } + } + if (TRUE == pstcAdcIrqCfg->bAdcJQRIrq) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcJQRIrq) + { + stcAdcIrqCalbaks.pfnAdcJQRIrq = pstcAdcIrqCalbaks->pfnAdcJQRIrq; + } + } + if (TRUE == pstcAdcIrqCfg->bAdcSQRIrq) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcSQRIrq) + { + stcAdcIrqCalbaks.pfnAdcSQRIrq = pstcAdcIrqCalbaks->pfnAdcSQRIrq; + } + } + if (TRUE == pstcAdcIrqCfg->bAdcRegCmp) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcRegIrq) + { + stcAdcIrqCalbaks.pfnAdcRegIrq = pstcAdcIrqCalbaks->pfnAdcRegIrq; + } + } + + if (TRUE == pstcAdcIrqCfg->bAdcHhtCmp) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcHhtIrq) + { + stcAdcIrqCalbaks.pfnAdcHhtIrq = pstcAdcIrqCalbaks->pfnAdcHhtIrq; + } + } + + if (TRUE == pstcAdcIrqCfg->bAdcLltCmp) + { + if (NULL != pstcAdcIrqCalbaks->pfnAdcLltIrq) + { + stcAdcIrqCalbaks.pfnAdcLltIrq = pstcAdcIrqCalbaks->pfnAdcLltIrq; + } + } + +} + +/** + * \brief + * 获å–ADCä¸­æ–­çŠ¶æ€ + * + * \param [in] pstcAdcIrqState ADC中断状æ€æŒ‡é’ˆ + * + * \retval æ—  + */ +void Adc_GetIrqState(stc_adc_irq_t* pstcAdcIrqState) +{ + pstcAdcIrqState->bAdcIrq = M0P_ADC->IFR_f.SGLIF; + pstcAdcIrqState->bAdcRegCmp = M0P_ADC->IFR_f.REGIF; + pstcAdcIrqState->bAdcHhtCmp = M0P_ADC->IFR_f.HTIF; + pstcAdcIrqState->bAdcLltCmp = M0P_ADC->IFR_f.LTIF; + pstcAdcIrqState->bAdcJQRIrq = M0P_ADC->IFR_f.JQRIF; + pstcAdcIrqState->bAdcSQRIrq = M0P_ADC->IFR_f.SQRIF; +} +/** + * \brief + * 清除ADC SGLä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrSglIrqState(void) +{ + M0P_ADC->ICR_f.SGLIC = 0; +} +/** + * \brief + * 清除ADC JQRä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrJqrIrqState(void) +{ + M0P_ADC->ICR_f.JQRIC = 0; +} +/** + * \brief + * 清除ADC SQRä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrSqrIrqState(void) +{ + M0P_ADC->ICR_f.SQRIC = 0; +} + +/** + * \brief + * 清除ADC REGä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrRegIrqState(void) +{ + M0P_ADC->ICR_f.REGIC = 0; +} + +/** + * \brief + * 清除ADC HTä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrHtIrqState(void) +{ + M0P_ADC->ICR_f.HTIC = 0; +} + +/** + * \brief + * 清除ADC LTä¸­æ–­çŠ¶æ€ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrLtIrqState(void) +{ + M0P_ADC->ICR_f.LTIC = 0; +} + + +/** + * \brief + * ADC中断使能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_EnableIrq(void) +{ + M0P_ADC->CR0_f.IE = 1u; +} + +/** + * \brief + * ADC比较使能(比较中断) + * + * \param [in] pstcAdcIrqCfg ADC比较é…ç½® + * + * \retval æ—  + */ + +void Adc_ThresholdCfg(stc_adc_threshold_cfg_t* stcAdcThrCfg) +{ + + M0P_ADC->HT_f.HT = stcAdcThrCfg->u32AdcRegHighThd; //使用比较 + M0P_ADC->LT_f.LT = stcAdcThrCfg->u32AdcRegLowThd; //使用比较 + + M0P_ADC->CR1_f.THCH = stcAdcThrCfg->enThCh; //阈值比较通é“选择 + + if (TRUE == stcAdcThrCfg->bAdcRegCmp) + { + M0P_ADC->CR1_f.REGCMP = 1u; + } + else + { + M0P_ADC->CR1_f.REGCMP = 0u; + } + + if (TRUE == stcAdcThrCfg->bAdcHhtCmp) + { + M0P_ADC->CR1_f.HTCMP = 1u; + } + else + { + M0P_ADC->CR1_f.HTCMP = 0u; + } + + if (TRUE == stcAdcThrCfg->bAdcLltCmp) + { + M0P_ADC->CR1_f.LTCMP = 1u; + } + else + { + M0P_ADC->CR1_f.LTCMP = 0u; + } + +} + +/** + * \brief + * ADC中断除能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_DisableIrq(void) +{ + uint32_t u32Cr1; + + M0P_ADC->CR0_f.IE = 0u; + + u32Cr1 = M0P_ADC->CR1 | (1<<15); // must write 1 to bit 15 to avoid clear ADC_result_acc + u32Cr1 &= ~((1u<<12)|(1u<<13)|(1u<<14)); + M0P_ADC->CR1 = u32Cr1; +} + +/** + * \brief + * ADCåˆå§‹åŒ– + * + * \param [in] pstcAdcConfig ADCé…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_Init(stc_adc_cfg_t* pstcAdcConfig) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + M0P_ADC->CR0_f.CLKDIV = pstcAdcConfig->enAdcClkDiv; + M0P_ADC->CR0_f.SAM = pstcAdcConfig->enAdcSampTimeSel; + M0P_ADC->CR0_f.REF = pstcAdcConfig->enAdcRefVolSel; + M0P_ADC->CR0_f.BUF = pstcAdcConfig->bAdcInBufEn; + M0P_ADC->CR1_f.REGCMP = 0u; + M0P_ADC->CR1_f.HTCMP = 0u; + M0P_ADC->CR1_f.LTCMP = 0u; + + return Ok; +} + +/** + * \brief + * ADC外部中断触å‘æºé…ç½® + * + * \param [in] pstcAdcConfig ADCé…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ExtTrigCfg(stc_adc_ext_trig_cfg_t* pstcExtTrigConfig) +{ + if (NULL == pstcExtTrigConfig) + { + return ErrorInvalidParameter; + } + if(pstcExtTrigConfig->enAdcExtTrigRegSel == AdcExtTrig0) + { + M0P_ADC->EXTTRIGGER0 |= 1u << pstcExtTrigConfig->enAdcTrig0Sel; + } + else if(pstcExtTrigConfig->enAdcExtTrigRegSel == AdcExtTrig1) + { + M0P_ADC->EXTTRIGGER1 |= 1u << pstcExtTrigConfig->enAdcTrig1Sel; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * ADC Deinit + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_DeInit(void) +{ + + M0P_ADC->CR0_f.EN = 0u; + + M0P_ADC->CR0_f.IE = 0u; + M0P_ADC->CR1_f.REGCMP = 0u; + M0P_ADC->CR1_f.HTCMP = 0u; + M0P_ADC->CR1_f.LTCMP = 0u; + + M0P_ADC->ICR_f.SGLIC = 0u; + M0P_ADC->ICR_f.LTIC = 0u; + M0P_ADC->ICR_f.HTIC = 0u; + M0P_ADC->ICR_f.REGIC = 0u; + M0P_ADC->ICR_f.SQRIC = 0u; + M0P_ADC->ICR_f.JQRIC = 0u; + + M0P_ADC->CR0_f.CLKDIV = 0u; + M0P_ADC->CR0_f.SAM = 0x2u; + M0P_ADC->CR0_f.REF = 0x3u; + M0P_ADC->CR0_f.SGLMUX = 0xFu; + M0P_ADC->CR0_f.BUF = 0u; + M0P_ADC->HT_f.HT = 0xFFFu; + M0P_ADC->LT_f.LT = 0u; +} + +/** + * \brief + * ADC å•æ¬¡è½¬æ¢å¼€å§‹ + * + * \param æ—  + * + * \retval æ—  + */ + +void Adc_SGL_Start(void) +{ + M0P_ADC->SGLSTART_f.START = 1u; +} + +/** + * \brief + * ADC å•æ¬¡è½¬æ¢åœæ­¢ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_SGL_Stop(void) +{ + M0P_ADC->SGLSTART_f.START = 0u; +} +/** + * \brief + * ADC 顺åºè½¬æ¢å¼€å§‹ + * + * \param æ—  + * + * \retval æ—  + */ + +void Adc_SQR_Start(void) +{ + M0P_ADC->SQRSTART_f.START = 1u; +} + +/** + * \brief + * ADC 顺åºè½¬æ¢åœæ­¢ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_SQR_Stop(void) +{ + M0P_ADC->SQRSTART_f.START = 0u; +} +/** + * \brief + * ADC æ’队转æ¢å¼€å§‹ + * + * \param æ—  + * + * \retval æ—  + */ + +void Adc_JQR_Start(void) +{ + M0P_ADC->JQRSTART_f.START = 1u; +} + +/** + * \brief + * ADC æ’队转æ¢åœæ­¢ + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_JQR_Stop(void) +{ + M0P_ADC->JQRSTART_f.START = 0u; +} +/** + * \brief + * ADC使能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_Enable(void) +{ + M0P_ADC->CR0_f.EN = 1u; +} + +/** + * \brief + * ADC除能 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_Disable(void) +{ + M0P_ADC->CR0_f.EN = 0u; +} + +/** + * \brief + * é…ç½®å•æ¬¡è½¬æ¢æ¨¡å¼ + * + * \param [in] pstcAdcConfig ADCé…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSglMode(stc_adc_cfg_t* pstcAdcConfig) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.MODE = pstcAdcConfig->enAdcOpMode; + + return Ok; +} + +/** + * \brief + * é…置顺åºæ‰«æ转æ¢æ¨¡å¼ + * + * \param [in] pstcAdcConfig ADCé…置指针 + * \param [in] pstcAdcNormCfg 连续转æ¢æ¨¡å¼é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSqrMode(stc_adc_cfg_t* pstcAdcConfig, uint8_t u8AdcSampCnt,boolean_t bAdcResultAccEn) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.MODE = pstcAdcConfig->enAdcOpMode; + M0P_ADC->CR1_f.RACCCLR = 0;//ADC转æ¢ç»“果累加寄存器（ADC_ResultAcc）清零 + M0P_ADC->CR1_f.RACCEN = bAdcResultAccEn; + if (bAdcResultAccEn) + { + M0P_ADC->CR1_f.RACCCLR = 1u; + } + M0P_ADC->SQR2_f.CNT = u8AdcSampCnt - 1; + + return Ok; +} + +/** + * \brief + * é…ç½®æ’队扫æ转æ¢æ¨¡å¼ + * + * \param [in] pstcAdcConfig ADCé…置指针 + * \param [in] pstcAdcNormCfg 扫æ转æ¢æ¨¡å¼é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigJqrMode(stc_adc_cfg_t* pstcAdcConfig, uint8_t u8AdcSampCnt,boolean_t bAdcResultAccEn) +{ + if (NULL == pstcAdcConfig) + { + return ErrorInvalidParameter; + } + + M0P_ADC->CR1_f.MODE = pstcAdcConfig->enAdcOpMode; + M0P_ADC->CR1_f.RACCEN = bAdcResultAccEn; + M0P_ADC->JQR_f.CNT = u8AdcSampCnt - 1; + + return Ok; +} +/** + * \brief + * é…ç½®å•æ¬¡è½¬æ¢é€šé“ + * + * \param [in]enstcAdcSampCh 转æ¢é€šé“ + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSglChannel( en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + M0P_ADC->CR0_f.SGLMUX = enstcAdcSampCh; + return Ok; +} + +/** + * \brief + * é…置顺åºæ‰«æ转æ¢é€šé“ + * + * \param [in]enstcAdcSqrChMux 顺åºæ‰«æ转æ¢é€šé“é¡ºåº + * \param [in]enstcAdcSampCh 转æ¢é€šé“ + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigSqrChannel(en_adc_sqr_chmux_t enstcAdcSqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + switch(enstcAdcSqrChMux) + { + case CH0MUX: + M0P_ADC->SQR0_f.CH0MUX = enstcAdcSampCh; + break; + case CH1MUX: + M0P_ADC->SQR0_f.CH1MUX = enstcAdcSampCh; + break; + case CH2MUX: + M0P_ADC->SQR0_f.CH2MUX = enstcAdcSampCh; + break; + case CH3MUX: + M0P_ADC->SQR0_f.CH3MUX = enstcAdcSampCh; + break; + case CH4MUX: + M0P_ADC->SQR0_f.CH4MUX = enstcAdcSampCh; + break; + case CH5MUX: + M0P_ADC->SQR0_f.CH5MUX = enstcAdcSampCh; + break; + case CH6MUX: + M0P_ADC->SQR1_f.CH6MUX = enstcAdcSampCh; + break; + case CH7MUX: + M0P_ADC->SQR1_f.CH7MUX = enstcAdcSampCh; + break; + case CH8MUX: + M0P_ADC->SQR1_f.CH8MUX = enstcAdcSampCh; + break; + case CH9MUX: + M0P_ADC->SQR1_f.CH9MUX = enstcAdcSampCh; + break; + case CH10MUX: + M0P_ADC->SQR1_f.CH10MUX = enstcAdcSampCh; + break; + case CH11MUX: + M0P_ADC->SQR1_f.CH11MUX = enstcAdcSampCh; + break; + case CH12MUX: + M0P_ADC->SQR2_f.CH12MUX = enstcAdcSampCh; + break; + case CH13MUX: + M0P_ADC->SQR2_f.CH13MUX = enstcAdcSampCh; + break; + case CH14MUX: + M0P_ADC->SQR2_f.CH14MUX = enstcAdcSampCh; + break; + case CH15MUX: + M0P_ADC->SQR2_f.CH15MUX = enstcAdcSampCh; + break; + default: + break; + + } + return Ok; +} +/** + * \brief + * é…ç½®æ’队扫æ转æ¢é€šé“ + * + * \param [in]enstcAdcSqrChMux æ’队扫æ转æ¢é€šé“é¡ºåº + * \param [in]enstcAdcSampCh 转æ¢é€šé“ + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigJqrChannel(en_adc_jqr_chmux_t enstcAdcJqrChMux, en_adc_samp_ch_sel_t enstcAdcSampCh) +{ + switch(enstcAdcJqrChMux) + { + case CH0MUX: + M0P_ADC->JQR_f.CH0MUX = enstcAdcSampCh; + break; + case CH1MUX: + M0P_ADC->JQR_f.CH1MUX = enstcAdcSampCh; + break; + case CH2MUX: + M0P_ADC->JQR_f.CH2MUX = enstcAdcSampCh; + break; + case CH3MUX: + M0P_ADC->JQR_f.CH3MUX = enstcAdcSampCh; + break; + default: + break; + } + return Ok; +} +/** + * \brief + * é…置触å‘DMA读å–控制 + * + * \param [in]enAdcDmaTrig 触å‘DMA读å–控制 + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_ConfigDmaTrig(en_adc_dmatrig_t enAdcDmaTrig) +{ + if(enAdcDmaTrig == DmaJqr) + { + M0P_ADC->CR1_f.DMAJQR = 1; + }else + { + M0P_ADC->CR1_f.DMASQR = 1; + } + return Ok; +} + +/** + * \brief + * 查询ADCå•æ¬¡è½¬æ¢çŠ¶æ€ + * + * \param none + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + */ +boolean_t Adc_PollSglBusyState(void) +{ + return M0P_ADC->IFR_f.SGLIF; +} + + +/** + * \brief + * 查询ADC顺åºæ‰«æ转æ¢çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollSqrBusyState(void) +{ + return M0P_ADC->IFR_f.SQRIF; +} + +/** + * \brief + * 查询ADCæ’队扫æ转æ¢çŠ¶æ€ + * + * \param none + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + */ +boolean_t Adc_PollJqrBusyState(void) +{ + return M0P_ADC->IFR_f.JQRIF; +} + +/** + * \brief + * 获å–采样值 + * + * \param [out] pu16AdcResult 采样值指针 + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetSglResult(uint16_t* pu16AdcResult) +{ + if (NULL == pu16AdcResult) + { + return ErrorInvalidParameter; + } + + *pu16AdcResult = M0P_ADC->RESULT_f.RESULT; + + return Ok; +} + +/** + * \brief + * 查询ADCç»“æžœæ¯”è¾ƒåŒºé—´çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollRegBusyState(void) +{ + return M0P_ADC->IFR_f.REGIF; +} +/** + * \brief + * 查询ADCç»“æžœæ¯”è¾ƒä¸Šé˜ˆå€¼çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollHTBusyState(void) +{ + return M0P_ADC->IFR_f.HTIF; +} +/** + * \brief + * 查询ADCç»“æžœæ¯”è¾ƒåŒºé—´çŠ¶æ€ + * + * \retval boolean_t TRUE: ADC转æ¢å®Œæˆ + * \retval boolean_t FALSE: ADC转æ¢ä¸­ + * \param none + * + */ +boolean_t Adc_PollLtBusyState(void) +{ + return M0P_ADC->IFR_f.LTIF; +} +/** + * \brief + * 获å–采样值 + * + * \param [out] pu16AdcResult 采样值指针 + * \param [in] SQRChannelIndex 顺åºæ‰«æ通é“åºå· + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetSqrResult(uint16_t* pu16AdcResult,uint8_t SQRChannelIndex) +{ + volatile uint32_t *BaseSqrResultAddress =(volatile uint32_t *) &(M0P_ADC->SQRRESULT0); + + if (NULL == pu16AdcResult) + { + return ErrorInvalidParameter; + } + + if(SQRChannelIndex > 15) + { + return ErrorInvalidParameter; + } + + *pu16AdcResult = (uint16_t)(*(BaseSqrResultAddress + SQRChannelIndex)); + + return Ok; +} + +/** + * \brief + * 获å–æ’队扫æ采样值 + * + * \param [out] pu16AdcResult 采样值指针 + * \param [in] JQRChannelIndex æ’队扫æ通é“åºå· + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetJqrResult(uint16_t* pu16AdcResult,uint8_t JQRChannelIndex) +{ + volatile uint32_t *BaseJqrResultAddress =(volatile uint32_t *) &(M0P_ADC->JQRRESULT0); + if (NULL == pu16AdcResult) + { + return ErrorInvalidParameter; + } + + if(JQRChannelIndex > 3) + { + return ErrorInvalidParameter; + } + *pu16AdcResult = (uint16_t)(*(BaseJqrResultAddress + JQRChannelIndex)); + return Ok; +} +/** + * \brief + * 获å–累加采样值 + * + * \param [out] pu32AdcAccResult 累加采样值指针 + * + * \retval en_result_t Ok: æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_GetAccResult(uint32_t* pu32AdcAccResult) +{ + if (NULL == pu32AdcAccResult) + { + return ErrorInvalidParameter; + } + + *pu32AdcAccResult = M0P_ADC->RESULTACC_f.RESULTACC; + + return Ok; +} + +/** + * \brief + * 清零累加采样值 + * + * \param æ—  + * + * \retval æ—  + */ +void Adc_ClrAccResult(void) +{ + M0P_ADC->CR1_f.RACCCLR = 0u; +} + + +/** + * \brief + * 设置ADCå‚考电压 + * + * \param [in] enAdcRefVolSel ADCå‚考电压 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_SetVref(en_adc_ref_vol_sel_t enAdcRefVolSel) +{ + if (enAdcRefVolSel > RefVolSelAVDD) + { + return ErrorInvalidParameter; + } + if((RefVolSelInBgr1p5 == enAdcRefVolSel) || (RefVolSelInBgr2p5 == enAdcRefVolSel)) + { + M0P_ADC->CR0_f.INREFEN = 1; + }else + { + M0P_ADC->CR0_f.INREFEN = 0; + } + M0P_ADC->CR0_f.REF = enAdcRefVolSel; + return Ok; +} +/** + * \brief + * 设置ADC结果对é½æ–¹å¼ + * + * \param [in] enAlign ADC结果对é½æ–¹å¼ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adc_SetAlign(en_adc_align_t enAlign) +{ + M0P_ADC->CR1_f.ALIGN = enAlign; + return Ok; +} +//@} // AdcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adt.c new file mode 100644 index 0000000000..471cf96a1d --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/adt.c @@ -0,0 +1,1952 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file adt.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2018-04-18 Husj First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "adt.h" + +/** + ****************************************************************************** + ** \addtogroup AdtGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnAdtIrqCbk[3][16] = {NULL}; + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/************************************************* + * \brief + * 使能NVIC中ADT中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + **************************************************/ +static void AdtEnableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_EnableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, DDL_IRQ_LEVEL_DEFAULT); +} + +/************************************************** + * \brief + * 除能NVIC中ADT中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + **************************************************/ +static void AdtDisableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_DisableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, DDL_IRQ_LEVEL_DEFAULT); +} + +/*************************************************** + * \brief + * ADT中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param 未使用 + * + * \retval æ—  + ****************************************************/ +void Adt_IRQHandler(uint8_t u8Param) +{ + uint8_t u8Adt = u8Param - 4; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*u8Adt); + + if (TRUE == pstcM0PAdt->IFR_f.CMAF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMAIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMAIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.CMBF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMBIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMBIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.CMCF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMCIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMCIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.CMDF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtCMDIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtCMDIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.OVFF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtOVFIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtOVFIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.UDFF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtUDFIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtUDFIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.DTEF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtDTEIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtDTEIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.SAMLF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtSAMLIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtSAMLIrq](); + } + pstcM0PAdt->ICLR = ~(1<IFR_f.SAMHF) + { + if (NULL != pfnAdtIrqCbk[u8Adt][AdtSAMHIrq]) + { + pfnAdtIrqCbk[u8Adt][AdtSAMHIrq](); + } + pstcM0PAdt->ICLR = ~(1<ICONR; + if (bEn) + { + u32Val |= 1u<ICONR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 获å–中断标志 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtIrq 中断类型 + * \param [in] pbFlag 中断标志指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *****************************************************************/ +en_result_t Adt_GetIrqFlag(en_adt_unit_t enAdtUnit, + en_adt_irq_type_t enAdtIrq, + boolean_t* pbFlag) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->IFR; + *pbFlag = (u32Val>>enAdtIrq) & 0x1; + + return Ok; +} + +/**************************************************************** + * \brief + * 清除中断标志 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtIrq 中断类型 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ****************************************************************/ +en_result_t Adt_ClearIrqFlag(en_adt_unit_t enAdtUnit, + en_adt_irq_type_t enAdtIrq) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->ICLR = ~(1u<HCUPR; + pstcM0PAdt->HCUPR = u32Val | (1u<HCUPR = 0; + return Ok; +} + + +/** + * \brief + * é…置硬件递å‡äº‹ä»¶ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwCntDwn 硬件递å‡äº‹ä»¶ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Adt_ConfigHwCntDwn(en_adt_unit_t enAdtUnit, en_adt_hw_cnt_t enAdtHwCntDwn) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwCntMax <= enAdtHwCntDwn)) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCDOR; + pstcM0PAdt->HCDOR = u32Val | (1u<HCDOR = 0; + return Ok; +} + +/****************************************************************** + * \brief + * é…置硬件å¯åŠ¨äº‹ä»¶ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwStart 硬件å¯åŠ¨äº‹ä»¶ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_ConfigHwStart(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwStart) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwStart)) + { + return ErrorInvalidParameter; + } + u32Val = pstcM0PAdt->HSTAR; + pstcM0PAdt->HSTAR = u32Val | (1u<HSTAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * 使能硬件å¯åŠ¨ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *********************************************************************/ +en_result_t Adt_EnableHwStart(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTAR; + pstcM0PAdt->HSTAR = u32Val | (1u<<31); + return Ok; +} + +/************************************************************************* + * \brief + * 除能硬件å¯åŠ¨ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_DisableHwStart(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTAR; + pstcM0PAdt->HSTAR = u32Val & 0x7FFFFFFF; + return Ok; +} + +/**************************************************************** + * \brief + * é…置硬件åœæ­¢äº‹ä»¶ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwStop 硬件åœæ­¢äº‹ä»¶ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************/ +en_result_t Adt_ConfigHwStop(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwStop) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwStop)) + { + return ErrorInvalidParameter; + } + u32Val = pstcM0PAdt->HSTPR; + pstcM0PAdt->HSTPR = u32Val | (1u<HSTPR = 0; + return Ok; +} + +/************************************************************* + * \brief + * 使能硬件åœæ­¢ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************/ +en_result_t Adt_EnableHwStop(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTPR; + pstcM0PAdt->HSTPR = u32Val | (1u<<31); + return Ok; +} + +/***************************************************************************** + * \brief + * 除能硬件åœæ­¢ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************************/ +en_result_t Adt_DisableHwStop(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HSTPR; + pstcM0PAdt->HSTPR = u32Val & 0x7FFFFFFF; + return Ok; +} + +/************************************************************************** + * \brief + * é…置硬件清零事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwClear 硬件清零事件 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_ConfigHwClear(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwClear) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwClear)) + { + return ErrorInvalidParameter; + } + u32Val = pstcM0PAdt->HCELR & (1u<<31); + pstcM0PAdt->HCELR = u32Val | (1u<HCELR = 0; + return Ok; +} + +/*************************************************************************** + * \brief + * 使能硬件清零 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_EnableHwClear(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCELR; + pstcM0PAdt->HCELR = u32Val | (1u<<31); + return Ok; +} + +/************************************************************************ + * \brief + * 除能硬件清零 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_DisableHwClear(en_adt_unit_t enAdtUnit) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCELR; + pstcM0PAdt->HCELR = u32Val & 0x7FFFFFFF; + return Ok; +} + +/******************************************************************* + * \brief + * é…置硬件æ•èŽ·A事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwCaptureA 硬件æ•èŽ·A事件选择 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_ConfigHwCaptureA(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwCaptureA) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwCaptureA)) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCPAR; + pstcM0PAdt->HCPAR = u32Val | (1u<PCONR_f.CAPCA = 1; + return Ok; +} + +/************************************************************************ + * \brief + * 清除硬件æ•èŽ·A事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_ClearHwCaptureA(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->HCPAR = 0; + return Ok; +} + +/********************************************************************* + * \brief + * é…置硬件æ•èŽ·B事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtHwCaptureB 硬件æ•èŽ·B事件选择 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ********************************************************************/ +en_result_t Adt_ConfigHwCaptureB(en_adt_unit_t enAdtUnit, en_adt_hw_trig_t enAdtHwCaptureB) +{ + uint32_t u32Val; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (AdtHwTrigEnd <= enAdtHwCaptureB)) + { + return ErrorInvalidParameter; + } + + u32Val = pstcM0PAdt->HCPBR; + pstcM0PAdt->HCPBR = u32Val | (1u<PCONR_f.CAPCB = 1; + return Ok; +} + +/******************************************************************** + * \brief + * 清除硬件æ•èŽ·B事件 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_ClearHwCaptureB(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->HCPBR = 0; + return Ok; +} + +/***************************************************************** + * \brief + * 软件åŒæ­¥å¼€å§‹ + * + * \param [in] pstcAdtSwSyncStart 软件åŒæ­¥å¼€å§‹æŒ‡é’ˆ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************/ +en_result_t Adt_SwSyncStart(stc_adt_sw_sync_t* pstcAdtSwSyncStart) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStart) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStart->bAdTim4) + { + u32Val |= 0x1; + } + if (pstcAdtSwSyncStart->bAdTim5) + { + u32Val |= 0x2; + } + if (pstcAdtSwSyncStart->bAdTim6) + { + u32Val |= 0x4; + } + + M0P_TIM4->SSTAR = u32Val; + return Ok; +} + +/*************************************************************** + * \brief + * 软件åŒæ­¥åœæ­¢ + * + * \param [in] pstcAdtSwSyncStop 软件åŒæ­¥åœæ­¢æŒ‡é’ˆ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***************************************************************/ +en_result_t Adt_SwSyncStop(stc_adt_sw_sync_t* pstcAdtSwSyncStop) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncStop) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncStop->bAdTim4) + { + u32Val |= 0x1; + } + if (pstcAdtSwSyncStop->bAdTim5) + { + u32Val |= 0x2; + } + if (pstcAdtSwSyncStop->bAdTim6) + { + u32Val |= 0x4; + } + + M0P_TIM4->SSTPR = u32Val; + return Ok; +} + +/***************************************************************** + * \brief + * 软件åŒæ­¥æ¸…零 + * + * \param [in] pstcAdtSwSyncClear 软件åŒæ­¥æ¸…零指针 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_SwSyncClear(stc_adt_sw_sync_t* pstcAdtSwSyncClear) +{ + uint32_t u32Val = 0; + + if (NULL == pstcAdtSwSyncClear) + { + return ErrorInvalidParameter; + } + + if (pstcAdtSwSyncClear->bAdTim4) + { + u32Val |= 0x1; + } + if (pstcAdtSwSyncClear->bAdTim5) + { + u32Val |= 0x2; + } + if (pstcAdtSwSyncClear->bAdTim6) + { + u32Val |= 0x4; + } + + M0P_TIM4->SCLRR = u32Val; + return Ok; +} + +/******************************************************************* + * \brief + * 获å–软件åŒæ­¥è¿è¡ŒçŠ¶æ€ + * + * \param [in] pstcAdtSwSyncState ADV Timer软件åŒæ­¥è¿è¡ŒçŠ¶æ€æŒ‡é’ˆ + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_GetSwSyncState(stc_adt_sw_sync_t* pstcAdtSwSyncState) +{ + if (NULL == pstcAdtSwSyncState) + { + return ErrorInvalidParameter; + } + + if (M0P_TIM4->SSTAR & 0x1) + { + pstcAdtSwSyncState->bAdTim4 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim4 = FALSE; + } + if (M0P_TIM4->SSTAR & 0x2) + { + pstcAdtSwSyncState->bAdTim5 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim5 = FALSE; + } + if (M0P_TIM4->SSTAR & 0x4) + { + pstcAdtSwSyncState->bAdTim6 = TRUE; + } + else + { + pstcAdtSwSyncState->bAdTim6 = FALSE; + } + return Ok; +} + +/************************************************************************ + * \brief + * AOS触å‘é…ç½® + * + * \param [in] pstcAdtAosTrigCfg 触å‘é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_AosTrigConfig(stc_adt_aos_trig_cfg_t* pstcAdtAosTrigCfg) +{ + if (NULL == pstcAdtAosTrigCfg) + { + return ErrorInvalidParameter; + } + + M0P_TIM4->ITRIG_f.IAOS0S = pstcAdtAosTrigCfg->enAos0TrigSrc; + M0P_TIM4->ITRIG_f.IAOS1S = pstcAdtAosTrigCfg->enAos1TrigSrc; + M0P_TIM4->ITRIG_f.IAOS2S = pstcAdtAosTrigCfg->enAos2TrigSrc; + M0P_TIM4->ITRIG_f.IAOS3S = pstcAdtAosTrigCfg->enAos3TrigSrc; + return Ok; +} + +/********************************************************************** + * \brief + * 中断触å‘é…ç½® + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtIrqTrigCfg 触å‘é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_IrqTrigConfig(en_adt_unit_t enAdtUnit, + stc_adt_irq_trig_cfg_t* pstcAdtIrqTrigCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtIrqTrigCfg)) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CR_f.CMAE = pstcAdtIrqTrigCfg->bAdtCntMatchATrigEn; + pstcM0PAdt->CR_f.CMBE = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigEn; + pstcM0PAdt->CR_f.CMCE = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigEn; + pstcM0PAdt->CR_f.CMDE = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigEn; + pstcM0PAdt->CR_f.OVFE = pstcAdtIrqTrigCfg->bAdtOverFlowTrigEn; + pstcM0PAdt->CR_f.UDFE = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigEn; + pstcM0PAdt->CR_f.DMA_G_CMA = pstcAdtIrqTrigCfg->bAdtCntMatchATrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_CMB = pstcAdtIrqTrigCfg->bAdtCntMatchBTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_CMC = pstcAdtIrqTrigCfg->bAdtCntMatchCTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_CMD = pstcAdtIrqTrigCfg->bAdtCntMatchDTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_OVF = pstcAdtIrqTrigCfg->bAdtOverFlowTrigDmaEn; + pstcM0PAdt->CR_f.DMA_G_UDF = pstcAdtIrqTrigCfg->bAdtUnderFlowTrigDmaEn; + pstcM0PAdt->CR_f.DMA_S_CMA = pstcAdtIrqTrigCfg->bAdtSpecilMatchATrigDmaEn; + pstcM0PAdt->CR_f.DMA_S_CMB = pstcAdtIrqTrigCfg->bAdtSpecilMatchBTrigDmaEn; + + return Ok; +} + +/************************************************************************* + * \brief + * 端å£è§¦å‘é…ç½® + * + * \param [in] enAdtTrigPort 触å‘ç«¯å£ + * \param [in] pstcAdtPortTrigCfg 触å‘é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_PortTrigConfig(en_adt_trig_port_t enAdtTrigPort, + stc_adt_port_trig_cfg_t* pstcAdtPortTrigCfg) +{ + if (NULL == pstcAdtPortTrigCfg) + { + return ErrorInvalidParameter; + } + + switch (enAdtTrigPort) + { + case AdtTrigA: + M0P_TIM4->TTRIG_f.TRIGAS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTA = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTA = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigB: + M0P_TIM4->TTRIG_f.TRIGBS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTB = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTB = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigC: + M0P_TIM4->TTRIG_f.TRIGCS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTC = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTC = pstcAdtPortTrigCfg->enFltClk; + break; + + case AdtTrigD: + M0P_TIM4->TTRIG_f.TRIGDS = pstcAdtPortTrigCfg->enTrigSrc; + M0P_TIM4->FCONR_f.NOFIENTD = pstcAdtPortTrigCfg->bFltEn; + M0P_TIM4->FCONR_f.NOFICKTD = pstcAdtPortTrigCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * CHxX端å£é…ç½® + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort CHxXç«¯å£ + * \param [in] pstcAdtCHxXCfg CHxX端å£é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *********************************************************************/ +en_result_t Adt_CHxXPortConfig(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + stc_adt_CHxX_port_cfg_t* pstcAdtCHxXCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtCHxXCfg)) + { + return ErrorInvalidParameter; + } + + switch (enAdtCHxXPort) + { + case AdtCHxA: + pstcM0PAdt->PCONR_f.CAPCA = pstcAdtCHxXCfg->enCap; + pstcM0PAdt->PCONR_f.STACA = pstcAdtCHxXCfg->enStaOut; + pstcM0PAdt->PCONR_f.STPCA = pstcAdtCHxXCfg->enStpOut; + pstcM0PAdt->PCONR_f.STASTPSA = pstcAdtCHxXCfg->enStaStp; + pstcM0PAdt->PCONR_f.CMPCA = pstcAdtCHxXCfg->enCmpc; + pstcM0PAdt->PCONR_f.PERCA = pstcAdtCHxXCfg->enPerc; + pstcM0PAdt->PCONR_f.OUTENA = pstcAdtCHxXCfg->bOutEn; + pstcM0PAdt->PCONR_f.DISSELA = pstcAdtCHxXCfg->enDisSel; + pstcM0PAdt->PCONR_f.DISVALA = pstcAdtCHxXCfg->enDisVal; + pstcM0PAdt->FCONR_f.NOFIENGA = pstcAdtCHxXCfg->bFltEn; + pstcM0PAdt->FCONR_f.NOFICKGA = pstcAdtCHxXCfg->enFltClk; + break; + + case AdtCHxB: + pstcM0PAdt->PCONR_f.CAPCB = pstcAdtCHxXCfg->enCap; + pstcM0PAdt->PCONR_f.STACB = pstcAdtCHxXCfg->enStaOut; + pstcM0PAdt->PCONR_f.STPCB = pstcAdtCHxXCfg->enStpOut; + pstcM0PAdt->PCONR_f.STASTPSB = pstcAdtCHxXCfg->enStaStp; + pstcM0PAdt->PCONR_f.CMPCB = pstcAdtCHxXCfg->enCmpc; + pstcM0PAdt->PCONR_f.PERCB = pstcAdtCHxXCfg->enPerc; + pstcM0PAdt->PCONR_f.OUTENB = pstcAdtCHxXCfg->bOutEn; + pstcM0PAdt->PCONR_f.DISSELB = pstcAdtCHxXCfg->enDisSel; + pstcM0PAdt->PCONR_f.DISVALB = pstcAdtCHxXCfg->enDisVal; + pstcM0PAdt->FCONR_f.NOFIENGB = pstcAdtCHxXCfg->bFltEn; + pstcM0PAdt->FCONR_f.NOFICKGB = pstcAdtCHxXCfg->enFltClk; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * 使能端å£åˆ¹è½¦ + * + * \param [in] port ç«¯å£ + * \param [in] pstcAdtBrkPtCfg 端å£åˆ¹è½¦é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_EnableBrakePort(uint8_t port, stc_adt_break_port_cfg_t* pstcAdtBrkPtCfg) +{ + uint32_t u32Val; + + if (NULL == pstcAdtBrkPtCfg) + { + return ErrorInvalidParameter; + } + + u32Val = M0P_TIM4->PTBKP; + u32Val &= ~(1u<PTBKP = u32Val | (pstcAdtBrkPtCfg->enPol<PTBKS; + M0P_TIM4->PTBKS = u32Val | (1u<PTBKS = 0; +} + +/********************************************************************* + * \brief + * 无效æ¡ä»¶3é…ç½® + * + * \param [in] pstcAdtDisable3 无效æ¡ä»¶3é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ********************************************************************/ +en_result_t Adt_Disable3Cfg(stc_adt_disable_3_cfg_t* pstcAdtDisable3) +{ + uint8_t i; + + if (NULL == pstcAdtDisable3) + { + return ErrorInvalidParameter; + } + + Adt_ClearBrakePort(); + for (i = 0; i <= 15; i++) + { + if (TRUE == pstcAdtDisable3->stcBrkPtCfg[i].bPortEn) + { + Adt_EnableBrakePort(i, &pstcAdtDisable3->stcBrkPtCfg[i]); + } + } + + M0P_TIM4->AOSSR_f.BFILTEN = pstcAdtDisable3->bFltEn; + M0P_TIM4->AOSSR_f.BFILTS = pstcAdtDisable3->enFltClk; + M0P_TIM4->AOSSR_f.SOFTBK = pstcAdtDisable3->bSwBrk; + + return Ok; +} + +/******************************************************************* + * \brief + * 获å–端å£åˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval TRUE or FALSE + ******************************************************************/ +boolean_t Adt_GetPortBrakeFlag(void) +{ + return M0P_TIM4->AOSSR_f.FBRAKE; +} + +/****************************************************************** + * \brief + * 清除端å£åˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval none + ******************************************************************/ +void Adt_ClearPortBrakeFlag(void) +{ + M0P_TIM4->AOSCL_f.FBRAKE = 0; +} + +/******************************************************************** + * \brief + * 无效æ¡ä»¶1é…ç½® + * + * \param [in] pstcAdtDisable1 无效æ¡ä»¶1é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ********************************************************************/ +en_result_t Adt_Disable1Cfg(stc_adt_disable_1_cfg_t* pstcAdtDisable1) +{ + + if (NULL == pstcAdtDisable1) + { + return ErrorInvalidParameter; + } + + M0P_TIM4->AOSSR_f.SMH2 = pstcAdtDisable1->bTim6OutSH; + M0P_TIM4->AOSSR_f.SMH1 = pstcAdtDisable1->bTim5OutSH; + M0P_TIM4->AOSSR_f.SMH0 = pstcAdtDisable1->bTim4OutSH; + M0P_TIM4->AOSSR_f.SML2 = pstcAdtDisable1->bTim6OutSL; + M0P_TIM4->AOSSR_f.SML1 = pstcAdtDisable1->bTim5OutSL; + M0P_TIM4->AOSSR_f.SML0 = pstcAdtDisable1->bTim4OutSL; + + return Ok; +} + +/******************************************************************** + * \brief + * 获å–åŒé«˜åŒä½Žåˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval TRUE or FALSE + ********************************************************************/ +boolean_t Adt_GetSameBrakeFlag(void) +{ + return M0P_TIM4->AOSSR_f.FSAME; +} + +/********************************************************************* + * \brief + * 清除åŒé«˜åŒä½Žåˆ¹è½¦æ ‡å¿— + * + * \param none + * + * \retval none + *********************************************************************/ +void Adt_ClearSameBrakeFlag(void) +{ + M0P_TIM4->AOSCL_f.FSAME = 0; +} + +/******************************************************************** + * \brief + * PWM展频é…ç½® + * + * \param [in] pstcAdtPwmDitherCfg PWM展频é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *********************************************************************/ +en_result_t Adt_PwmDitherConfig(en_adt_unit_t enAdtUnit, stc_adt_pwm_dither_cfg_t* pstcAdtPwmDitherCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (NULL == pstcAdtPwmDitherCfg) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CR_f.DITENS = pstcAdtPwmDitherCfg->enAdtPDType; + pstcM0PAdt->CR_f.DITENB = pstcAdtPwmDitherCfg->bTimxBPDEn; + pstcM0PAdt->CR_f.DITENA = pstcAdtPwmDitherCfg->bTimxAPDEn; + + return Ok; +} + +/********************************************************************** + * \brief + * ADTåˆå§‹åŒ– + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtBaseCntCfg 计数é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_Init(en_adt_unit_t enAdtUnit, stc_adt_basecnt_cfg_t* pstcAdtBaseCntCfg) +{ + int32_t i; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtBaseCntCfg)) + { + return ErrorInvalidParameter; + } + + if (AdtTriangleModeB < pstcAdtBaseCntCfg->enCntMode) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.MODE = pstcAdtBaseCntCfg->enCntMode; + pstcM0PAdt->GCONR_f.DIR = pstcAdtBaseCntCfg->enCntDir; + pstcM0PAdt->GCONR_f.CKDIV = pstcAdtBaseCntCfg->enCntClkDiv; + + for (i = 0; i < 16; i++) + { + pfnAdtIrqCbk[enAdtUnit][i] = NULL; + } + + AdtEnableNvic((IRQn_Type)((int32_t)TIM4_IRQn + (int32_t)enAdtUnit)); + + return Ok; +} + +/************************************************************************ + * \brief + * ADT Deinit + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_DeInit(en_adt_unit_t enAdtUnit) +{ + int32_t i; + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.START = 0; + + AdtDisableNvic((IRQn_Type)((int32_t)TIM4_IRQn + (int32_t)enAdtUnit)); + + for (i = 0; i < 16; i++) + { + pfnAdtIrqCbk[enAdtUnit][i] = NULL; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 开始计数 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_StartCount(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.START = 1; + + return Ok; +} + +/*********************************************************************** + * \brief + * åœæ­¢è®¡æ•° + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_StopCount(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.START = 0; + + return Ok; +} + +/******************************************************************** + * \brief + * 设置计数值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 计数值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +en_result_t Adt_SetCount(en_adt_unit_t enAdtUnit, uint16_t u16Value) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CNTER_f.CNT = u16Value; + return Ok; +} + +/******************************************************************** + * \brief + * 获å–计数值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 计数值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * ErrorInvalidParameter: 无效å‚æ•° + *******************************************************************/ +uint16_t Adt_GetCount(en_adt_unit_t enAdtUnit) +{ + uint16_t u16Value; + + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + u16Value = pstcM0PAdt->CNTER_f.CNT; + + return u16Value; +} + +/************************************************************************** + * \brief + * 清除计数值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 计数值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **************************************************************************/ +en_result_t Adt_ClearCount(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->CNTER_f.CNT = 0; + return Ok; +} + +/************************************************************************* + * \brief + * 获å–è®¡æ•°çŠ¶æ€ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtCntState 计数状æ€æŒ‡é’ˆ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_GetCntState(en_adt_unit_t enAdtUnit, stc_adt_cntstate_cfg_t* pstcAdtCntState) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtCntState)) + { + return ErrorInvalidParameter; + } + + pstcAdtCntState->u16Counter = pstcM0PAdt->CNTER_f.CNT; + pstcAdtCntState->enCntDir = pstcM0PAdt->STFLR_f.DIRF; + pstcAdtCntState->u8ValidPeriod = pstcM0PAdt->STFLR_f.VPERNUM; + pstcAdtCntState->bCMSBDF = pstcM0PAdt->STFLR_f.CMSBDF; + pstcAdtCntState->bCMSBUF = pstcM0PAdt->STFLR_f.CMSBUF; + pstcAdtCntState->bCMSADF = pstcM0PAdt->STFLR_f.CMSADF; + pstcAdtCntState->bCMSAUF = pstcM0PAdt->STFLR_f.CMSAUF; + pstcAdtCntState->bDTEF = pstcM0PAdt->STFLR_f.DTEF; + pstcAdtCntState->bUDFF = pstcM0PAdt->STFLR_f.UDFF; + pstcAdtCntState->bOVFF = pstcM0PAdt->STFLR_f.OVFF; + pstcAdtCntState->bCMDF = pstcM0PAdt->STFLR_f.CMDF; + pstcAdtCntState->bCMCF = pstcM0PAdt->STFLR_f.CMCF; + pstcAdtCntState->bCMBF = pstcM0PAdt->STFLR_f.CMBF; + pstcAdtCntState->bCMAF = pstcM0PAdt->STFLR_f.CMAF; + + return Ok; +} + +/*********************************************************************** + * \brief + * é…置计数周期 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Period 计数周期值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetPeriod(en_adt_unit_t enAdtUnit, uint16_t u16Period) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->PERAR = u16Period; + + return Ok; +} + +/*********************************************************************** + * \brief + * é…置计数周期缓冲 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16PeriodBuf 计数周期缓冲值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetPeriodBuf(en_adt_unit_t enAdtUnit, uint16_t u16PeriodBuf) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->PERBR = u16PeriodBuf; + pstcM0PAdt->BCONR_f.BENP = 1u; + + return Ok; +} + +/********************************************************************** + * \brief + * 清除计数周期缓冲 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_ClearPeriodBuf(en_adt_unit_t enAdtUnit) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->BCONR_f.BENP = 0; + pstcM0PAdt->PERBR = 0; + + return Ok; +} + +/*********************************************************************** + * \brief + * é…置有效计数周期 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtValidPerCfg 有效计数周期é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetValidPeriod(en_adt_unit_t enAdtUnit, + stc_adt_validper_cfg_t* pstcAdtValidPerCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtValidPerCfg)) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->VPERR_f.PCNTS = pstcAdtValidPerCfg->enValidCnt; + pstcM0PAdt->VPERR_f.PCNTE = pstcAdtValidPerCfg->enValidCdt; + pstcM0PAdt->VPERR_f.GEPERID = pstcAdtValidPerCfg->bPeriodD; + pstcM0PAdt->VPERR_f.GEPERIC = pstcAdtValidPerCfg->bPeriodC; + pstcM0PAdt->VPERR_f.GEPERIB = pstcAdtValidPerCfg->bPeriodB; + pstcM0PAdt->VPERR_f.GEPERIA = pstcAdtValidPerCfg->bPeriodA; + + return Ok; +} + +/************************************************************************ + * \brief + * é…置比较输出计数基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCompare 比较基准 + * \param [in] u16Compare 比较基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_SetCompareValue(en_adt_unit_t enAdtUnit, + en_adt_compare_t enAdtCompare, + uint16_t u16Compare) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCompareA == enAdtCompare) + { + pstcM0PAdt->GCMAR = u16Compare; + } + else if (AdtCompareB == enAdtCompare) + { + pstcM0PAdt->GCMBR = u16Compare; + } + else if (AdtCompareC == enAdtCompare) + { + pstcM0PAdt->GCMCR = u16Compare; + } + else if (AdtCompareD == enAdtCompare) + { + pstcM0PAdt->GCMDR = u16Compare; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/************************************************************************ + * \brief + * é…置专用比较计数基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtSpclCmp 专用比较基准值寄存器 + * \param [in] u16SpclCmp 比较基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_SetSpecilCompareValue(en_adt_unit_t enAdtUnit, + en_adt_special_compare_t enAdtSpclCmp, + uint16_t u16SpclCmp) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtSpclCompA == enAdtSpclCmp) + { + pstcM0PAdt->SCMAR_f.SCMA = u16SpclCmp; + } + else if (AdtSpclCompB == enAdtSpclCmp) + { + pstcM0PAdt->SCMBR_f.SCMB = u16SpclCmp; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/********************************************************************** + * \brief + * é…置通用比较值/æ•èŽ·å€¼ç¼“å­˜ä¼ é€ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * \param [in] bCompareBufEn 通用比较值缓存传é€ä½¿èƒ½ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_EnableValueBuf(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + boolean_t bCompareBufEn) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + pstcM0PAdt->BCONR_f.BENA = bCompareBufEn; + } + else if (AdtCHxB == enAdtCHxXPort) + { + pstcM0PAdt->BCONR_f.BENB = bCompareBufEn; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 清除比较输出计数值/æ•èŽ·å€¼ç¼“å­˜ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + **********************************************************************/ +en_result_t Adt_ClearValueBuf(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + pstcM0PAdt->GCMCR = 0; + pstcM0PAdt->BCONR_f.BENA = 0; + } + else if (AdtCHxB == enAdtCHxXPort) + { + pstcM0PAdt->GCMDR = 0; + pstcM0PAdt->BCONR_f.BENB = 0; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/*********************************************************************** + * \brief + * 获å–æ•èŽ·å€¼ + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * \param [in] pu16Capture æ•èŽ·å€¼æŒ‡é’ˆ + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_GetCaptureValue(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16Capture) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + *pu16Capture = pstcM0PAdt->GCMAR_f.GCMA; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16Capture = pstcM0PAdt->GCMBR_f.GCMB; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/********************************************************************** + * \brief + * 获å–æ•èŽ·ç¼“存值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] enAdtCHxXPort TIMxXç«¯å£ + * \param [in] pu16CaptureBuf æ•èŽ·ç¼“存值指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_GetCaptureBuf(en_adt_unit_t enAdtUnit, + en_adt_CHxX_port_t enAdtCHxXPort, + uint16_t* pu16CaptureBuf) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + if (AdtCHxA == enAdtCHxXPort) + { + *pu16CaptureBuf = pstcM0PAdt->GCMCR_f.GCMC; + } + else if (AdtCHxB == enAdtCHxXPort) + { + *pu16CaptureBuf = pstcM0PAdt->GCMDR_f.GCMD; + } + else + { + return ErrorInvalidParameter; + } + return Ok; +} + +/*********************************************************************** + * \brief + * 设置死区时间上基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 死区时间上基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ************************************************************************/ +en_result_t Adt_SetDTUA(en_adt_unit_t enAdtUnit, + uint16_t u16Value) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->DTUAR = u16Value; + + + return Ok; +} + +/*********************************************************************** + * \brief + * 设置死区时间下基准值 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] u16Value 死区时间下基准值 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + ***********************************************************************/ +en_result_t Adt_SetDTDA(en_adt_unit_t enAdtUnit, + uint16_t u16Value) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->DTDAR = u16Value; + + + return Ok; +} + +/****************************************************************** + * \brief + * é…置死区时间功能 + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] bDTEn 死区功能使能 + * \param [in] bEqual DTDAR的值和DTUAR的值自动相等 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *****************************************************************/ +en_result_t Adt_ConfigDT(en_adt_unit_t enAdtUnit, + boolean_t bDTEn, + boolean_t bEqual) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if (AdtTIM6 < enAdtUnit) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->DCONR_f.DTCEN = bDTEn; + pstcM0PAdt->DCONR_f.SEPA = bEqual; + + return Ok; +} + +/************************************************************************* + * \brief + * Z相输入å±è”½è®¾ç½® + * + * \param [in] enAdtUnit ADV Timer通é“选择（TIM4ã€TIM5ã€TIM6） + * \param [in] pstcAdtZMaskCfg Z相输入å±è”½åŠŸèƒ½é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + *************************************************************************/ +en_result_t Adt_ConfigZMask(en_adt_unit_t enAdtUnit, stc_adt_zmask_cfg_t* pstcAdtZMaskCfg) +{ + volatile M0P_TIM4_TypeDef *pstcM0PAdt = (M0P_TIM4_TypeDef *)((uint32_t)M0P_TIM4+0x400*enAdtUnit); + + if ((AdtTIM6 < enAdtUnit) || (NULL == pstcAdtZMaskCfg)) + { + return ErrorInvalidParameter; + } + + pstcM0PAdt->GCONR_f.ZMSK = pstcAdtZMaskCfg->enZMaskCycle; + pstcM0PAdt->GCONR_f.ZMSKPOS = pstcAdtZMaskCfg->bFltPosCntMaksEn; + pstcM0PAdt->GCONR_f.ZMSKREV = pstcAdtZMaskCfg->bFltRevCntMaksEn; + + return Ok; +} + +//@} // AdtGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/aes.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/aes.c new file mode 100644 index 0000000000..e28a48275f --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/aes.c @@ -0,0 +1,176 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c + ** + ** Common API of crc. + ** @link crcGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "aes.h" +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * \brief + * ADCåˆå§‹åŒ– + * + * \param [in] pu32Data å¾…åŠ å¯†æ•°æ® + * \param [in] pu32Key 加密KEY + * \param [out] pu32Cipher 加密åŽæ•°æ® + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t AES_Encrypt(uint32_t* pu32Data, uint32_t *pu32Key, uint32_t *pu32Cipher) +{ + if ((NULL == pu32Data)||(NULL == pu32Key)||(NULL == pu32Cipher)) + { + return ErrorInvalidParameter; + } + + //Key config + M0P_AES->KEY0 = pu32Key[0]; + M0P_AES->KEY1 = pu32Key[1]; + M0P_AES->KEY2 = pu32Key[2]; + M0P_AES->KEY3 = pu32Key[3]; + + //Data config + M0P_AES->DATA0 = pu32Data[0]; + M0P_AES->DATA1 = pu32Data[1]; + M0P_AES->DATA2 = pu32Data[2]; + M0P_AES->DATA3 = pu32Data[3]; + + M0P_AES->CR_f.MODE = 0;//Encry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pu32Cipher[0] = M0P_AES->DATA0; + pu32Cipher[1] = M0P_AES->DATA1; + pu32Cipher[2] = M0P_AES->DATA2; + pu32Cipher[3] = M0P_AES->DATA3; + return Ok; +} + + +/** + * \brief + * ADCåˆå§‹åŒ– + * + * \param [in] pu32Cipher å¾…è§£å¯†æ•°æ® + * \param [in] pu32Key 加密KEY + * \param [out] pu32Data 解密åŽæ•°æ® + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t AES_Decrypt(uint32_t *pu32Cipher,uint32_t *pu32Key, uint32_t* pu32Plaintext) +{ + if ((NULL == pu32Plaintext)||(NULL == pu32Key)||(NULL == pu32Cipher)) + { + return ErrorInvalidParameter; + } + + //Key config + M0P_AES->KEY0 = pu32Key[0]; + M0P_AES->KEY1 = pu32Key[1]; + M0P_AES->KEY2 = pu32Key[2]; + M0P_AES->KEY3 = pu32Key[3]; + + //Data config + M0P_AES->DATA0 = pu32Cipher[0]; + M0P_AES->DATA1 = pu32Cipher[1]; + M0P_AES->DATA2 = pu32Cipher[2]; + M0P_AES->DATA3 = pu32Cipher[3]; + + M0P_AES->CR_f.MODE = 1;//UnEncry + M0P_AES->CR_f.START = 1; + while(M0P_AES->CR_f.START == 1) + { + ; + } + pu32Plaintext[0] = M0P_AES->DATA0; + pu32Plaintext[1] = M0P_AES->DATA1; + pu32Plaintext[2] = M0P_AES->DATA2; + pu32Plaintext[3] = M0P_AES->DATA3; + return Ok; +} +//@} // CrcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bgr.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bgr.c new file mode 100644 index 0000000000..87bab21ed6 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bgr.c @@ -0,0 +1,155 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bgr.c + ** + ** Common API of bgr. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "bgr.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief BGR 使能 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_BgrEnable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.BGR_EN = TRUE; + + delay10us(2); + + return Ok; +} + +/** + ***************************************************************************** + ** \brief BGR ç¦æ­¢ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_BgrDisable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.BGR_EN = FALSE; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief BGR 温度传感器使能 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_TempSensorEnable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.TS_EN = TRUE; + + delay10us(2); + + return Ok; +} + +/** + ***************************************************************************** + ** \brief BGR 温度传感器ç¦æ­¢ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Bgr_TempSensorDisable(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralAdcBgr, TRUE); + M0P_BGR->CR_f.TS_EN = FALSE; + + return Ok; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bt.c new file mode 100644 index 0000000000..ea4014e088 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/bt.c @@ -0,0 +1,1608 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file bt.c + ** + ** Common API of base timer. + ** @link btGroup Some description @endlink + ** + ** - 2018-04-18 First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "bt.h" +/** + ******************************************************************************* + ** \addtogroup BtGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_TIM(x) (TIM0 == (x) ||\ + TIM1 == (x) ||\ + TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnTim0Callback = NULL; +static func_ptr_t pfnTim1Callback = NULL; +static func_ptr_t pfnTim2Callback = NULL; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer 中断标志获å–(模å¼0/1/23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Bt_GetIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + u32Val = pstcM0PBt->IFR; + bRetVal = (u32Val>>enBtIrq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断标志清除(模å¼0/1/23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_ClearIntFlag(en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ICLR = ~(1u<ICLR_f.UIF = 0; + pstcM0PBt->ICLR_f.CA0F = 0; + pstcM0PBt->ICLR_f.CB0F = 0; + pstcM0PBt->ICLR_f.BIF = 0; + pstcM0PBt->ICLR_f.TIF = 0; + pstcM0PBt->ICLR_f.CA0E = 0; + pstcM0PBt->ICLR_f.CB0E = 0; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_EnableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断ç¦æ­¢(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_DisableIrq(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断ç¦æ­¢(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M1CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_EnableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = TRUE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = TRUE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = TRUE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = TRUE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_DisableIrq (en_bt_unit_t enUnit, en_bt_irq_type_t enBtIrq) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + + switch (enBtIrq) + { + case BtUevIrq: + pstcM0PBt->M23CR_f.UIE = FALSE; + break; + case BtCA0Irq: + pstcM0PBt->CRCH0_f.CIEA = FALSE; + break; + case BtCB0Irq: + pstcM0PBt->CRCH0_f.CIEB = FALSE; + break; + case BtBkIrq: + pstcM0PBt->M23CR_f.BIE = FALSE; + break; + case BtTrigIrq: + pstcM0PBt->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param Timer通é“选择（0 - TIM0ã€1 - TIM1ã€2 - TIM2） + ** + ** \retval NULL + *****************************************************************************/ +void Tim_IRQHandler(uint8_t u8Param) +{ + switch (u8Param) + { + case 0: + if(NULL != pfnTim0Callback) + { + pfnTim0Callback(); + } + break; + case 1: + if(NULL != pfnTim1Callback) + { + pfnTim1Callback(); + } + break; + case 2: + if(NULL != pfnTim2Callback) + { + pfnTim2Callback(); + } + break; + default: + ; + break; + } +} + + + +/** + ***************************************************************************** + ** \brief Base Timer åˆå§‹åŒ–é…ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode0_Init(en_bt_unit_t enUnit, stc_bt_mode0_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + { + M0P_TIM0_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM0_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM0_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM0_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM0_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + } + break; + case TIM1: + { + M0P_TIM1_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM1_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM1_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM1_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM1_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM1_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM1_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim1Callback = pstcConfig->pfnTim1Cb; + } + break; + case TIM2: + { + M0P_TIM2_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM2_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM2_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM2_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM2_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM2_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM2_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim2Callback = pstcConfig->pfnTim2Cb; + + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer å¯åŠ¨è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer åœæ­¢è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 翻转输出使能/ç¦æ­¢è®¾å®š(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:ç¦æ­¢ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_EnTOG_Output(en_bt_unit_t enUnit, boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE0_TypeDef *pstcM0PBt = (M0P_TIM0_MODE0_TypeDef *)((uint32_t)M0P_TIM0_MODE0+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE0->CNT_f.CNT = u16Data; + break; + case TIM1: + M0P_TIM1_MODE0->CNT_f.CNT = u16Data; + break; + case TIM2: + M0P_TIM2_MODE0->CNT_f.CNT = u16Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M0_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u16CntData = M0P_TIM0_MODE0->CNT_f.CNT; + break; + case TIM1: + u16CntData = M0P_TIM1_MODE0->CNT_f.CNT; + break; + case TIM2: + u16CntData = M0P_TIM2_MODE0->CNT_f.CNT; + break; + default: + u16CntData = 0; + break; + } + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer é‡è½½å€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE0->ARR_f.ARR = u16Data; + break; + case TIM1: + M0P_TIM1_MODE0->ARR_f.ARR = u16Data; + break; + case TIM2: + M0P_TIM2_MODE0->ARR_f.ARR = u16Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u32Data 32ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M0_Cnt32Set(en_bt_unit_t enUnit, uint32_t u32Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE0->CNT32_f.CNT32 = u32Data; + break; + case TIM1: + M0P_TIM1_MODE0->CNT32_f.CNT32 = u32Data; + break; + case TIM2: + M0P_TIM2_MODE0->CNT32_f.CNT32 = u32Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 32ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Bt_M0_Cnt32Get(en_bt_unit_t enUnit) +{ + uint32_t u32CntData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u32CntData = M0P_TIM0_MODE0->CNT32_f.CNT32; + break; + case TIM1: + u32CntData = M0P_TIM1_MODE0->CNT32_f.CNT32; + break; + case TIM2: + u32CntData = M0P_TIM2_MODE0->CNT32_f.CNT32; + break; + default: + u32CntData = 0; + break; + } + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer åˆå§‹åŒ–é…ç½®(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode1_Init(en_bt_unit_t enUnit, stc_bt_mode1_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + { + M0P_TIM0_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM0_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + } + break; + case TIM1: + { + M0P_TIM1_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM1_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM1_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM1_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim1Callback = pstcConfig->pfnTim1Cb; + } + break; + case TIM2: + { + M0P_TIM2_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM2_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM2_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM2_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim2Callback = pstcConfig->pfnTim2Cb; + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC 输入é…ç½®(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Input_Config(en_bt_unit_t enUnit, stc_bt_pwc_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.TS = pstcConfig->enTsSel; + pstcM0PBt->MSCR_f.IA0S = pstcConfig->enIA0Sel; + pstcM0PBt->MSCR_f.IB0S = pstcConfig->enIB0Sel; + pstcM0PBt->FLTR_f.ETP = pstcConfig->enETRPhase; + pstcM0PBt->FLTR_f.FLTET = pstcConfig->enFltETR; + pstcM0PBt->FLTR_f.FLTA0 = pstcConfig->enFltIA0; + pstcM0PBt->FLTR_f.FLTB0 = pstcConfig->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹©(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enEdgeSel pwc测é‡èµ·å§‹ç»ˆæ­¢ç”µå¹³ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_PWC_Edge_Sel(en_bt_unit_t enUnit,en_bt_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enEdgeSel) + { + case 0: ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + pstcM0PBt->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 1: ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + pstcM0PBt->M1CR_f.EDG1ST = 1; //下é™æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 2: ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + pstcM0PBt->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + case 3: ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) + pstcM0PBt->M1CR_f.EDG1ST = 1; //下é™æ²¿ + pstcM0PBt->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer å¯åŠ¨è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer åœæ­¢è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE1_TypeDef *pstcM0PBt = (M0P_TIM0_MODE1_TypeDef *)((uint32_t)M0P_TIM0_MODE1+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M1_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + M0P_TIM0_MODE1->CNT_f.CNT = u16Data; + break; + case TIM1: + M0P_TIM1_MODE1->CNT_f.CNT = u16Data; + break; + case TIM2: + M0P_TIM2_MODE1->CNT_f.CNT = u16Data; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å€¼èŽ·å–(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M1_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u16CntData = M0P_TIM0_MODE1->CNT_f.CNT; + break; + case TIM1: + u16CntData = M0P_TIM1_MODE1->CNT_f.CNT; + break; + case TIM2: + u16CntData = M0P_TIM2_MODE1->CNT_f.CNT; + break; + default: + u16CntData = 0; + break; + } + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 脉冲宽度测é‡ç»“果数值获å–(模å¼1) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits脉冲宽度测é‡ç»“æžœ + *****************************************************************************/ +uint16_t Bt_M1_PWC_CapValueGet(en_bt_unit_t enUnit) +{ + uint16_t u16CapData = 0; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + u16CapData = M0P_TIM0_MODE1->CCR0A_f.CCR0A; + break; + case TIM1: + u16CapData = M0P_TIM1_MODE1->CCR0A_f.CCR0A; + break; + case TIM2: + u16CapData = M0P_TIM2_MODE1->CCR0A_f.CCR0A; + break; + default: + u16CapData = 0; + break; + } + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer åˆå§‹åŒ–é…ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_Mode23_Init(en_bt_unit_t enUnit, stc_bt_mode23_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + ASSERT(IS_VALID_TIM(enUnit)); + + switch (enUnit) + { + case TIM0: + { + M0P_TIM0_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM0_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM0_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM0_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM0_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM0_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + } + break; + case TIM1: + { + M0P_TIM1_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM1_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM1_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM1_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM1_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM1_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM1_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM1_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim1Callback = pstcConfig->pfnTim1Cb; + } + break; + case TIM2: + { + M0P_TIM2_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM2_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM2_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM2_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM2_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM2_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM2_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM2_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim2Callback = pstcConfig->pfnTim2Cb; + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM输出使能/ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] bEnOutput PWM输出使能/ç¦æ­¢è®¾å®š + ** \param [in] bEnAutoOutput PWM自动输出使能/ç¦æ­¢è®¾å®š + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnPWM_Output(en_bt_unit_t enUnit, boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.MOE = bEnOutput; + pstcM0PBt->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer å¯åŠ¨è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Run(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer åœæ­¢è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Stop(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer é‡è½½å€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** \param [in] bArrBufEn ARRé‡è½½ç¼“存使能TRUE/ç¦æ­¢FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ARRSet(en_bt_unit_t enUnit, uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ARR_f.ARR = u16Data; + pstcM0PBt->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_Cnt16Set(en_bt_unit_t enUnit, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 16ä½è®¡æ•°å€¼èŽ·å–(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Bt_M23_Cnt16Get(en_bt_unit_t enUnit) +{ + uint16_t u16CntData = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + u16CntData = pstcM0PBt->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer 比较æ•èŽ·å¯„存器CCR0A/CCR0B设置(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enCCRSel CCR0A/CCR0B设定 + ** \param [in] u16Data CCR0A/CCR0B 16ä½åˆå§‹å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_CCR_Set(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + pstcM0PBt->CCR0A_f.CCR0A = u16Data; + } + else if(BtCCR0B == enCCRSel) + { + pstcM0PBt->CCR0B_f.CCR0B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 比较æ•èŽ·å¯„存器CCR0A/CCR0B读å–(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] enCCRSel CCR0A/CCR0B设定 + ** + ** \retval 16bitsCCR0Aæ•èŽ·å€¼ + *****************************************************************************/ +uint16_t Bt_M23_CCR_Get(en_bt_unit_t enUnit, en_bt_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + if(BtCCR0A == enCCRSel) + { + u16Data = pstcM0PBt->CCR0A_f.CCR0A; + } + else if(BtCCR0B == enCCRSel) + { + u16Data = pstcM0PBt->CCR0B_f.CCR0B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_GateFuncSel(en_bt_unit_t enUnit,stc_bt_m23_gate_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.CSG = pstcConfig->enGateFuncSel; + pstcM0PBt->M23CR_f.CRG = pstcConfig->bGateRiseCap; + pstcM0PBt->M23CR_f.CFG = pstcConfig->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 主从模å¼é…ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_MasterSlave_Set(en_bt_unit_t enUnit, stc_bt_m23_master_slave_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->MSCR_f.MSM = pstcConfig->enMasterSlaveSel; + pstcM0PBt->MSCR_f.MMS = pstcConfig->enMasterSrc; + pstcM0PBt->MSCR_f.SMS = pstcConfig->enSlaveModeSel; + pstcM0PBt->MSCR_f.TS = pstcConfig->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B比较通é“输出控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortOutput_Config(en_bt_unit_t enUnit, stc_bt_m23_compare_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 0; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCH0ACmpCtrl; + pstcM0PBt->FLTR_f.CCPA0 = pstcConfig->enCH0APolarity; + pstcM0PBt->CRCH0_f.BUFEA = pstcConfig->bCh0ACmpBufEn; + pstcM0PBt->M23CR_f.CIS = pstcConfig->enCh0ACmpIntSel; + + pstcM0PBt->CRCH0_f.CSB = 0; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCH0BCmpCtrl; + pstcM0PBt->FLTR_f.CCPB0 = pstcConfig->enCH0BPolarity; + pstcM0PBt->CRCH0_f.BUFEB = pstcConfig->bCH0BCmpBufEn; + pstcM0PBt->CRCH0_f.CISB = pstcConfig->enCH0BCmpIntSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer CH0A/CH0B输入控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_PortInput_Config(en_bt_unit_t enUnit, stc_bt_m23_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CSA = 1; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enCH0ACapSel; + pstcM0PBt->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCH0AInFlt; + pstcM0PBt->FLTR_f.CCPA0 = pstcConfig->enCH0APolarity; + + pstcM0PBt->CRCH0_f.CSB = 1; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enCH0BCapSel; + pstcM0PBt->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCH0BInFlt; + pstcM0PBt->FLTR_f.CCPB0 = pstcConfig->enCH0BPolarity; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer ERT输入控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_ETRInput_Config(en_bt_unit_t enUnit, stc_bt_m23_etr_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->FLTR_f.ETP = pstcConfig->enETRPolarity; + pstcM0PBt->FLTR_f.FLTET = pstcConfig->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 刹车BK输入控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_BrakeInput_Config(en_bt_unit_t enUnit, stc_bt_m23_bk_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.BKE = pstcConfig->bEnBrake; + pstcM0PBt->DTR_f.VC0E = pstcConfig->bEnVC0Brake; + pstcM0PBt->DTR_f.VC1E = pstcConfig->bEnVC1Brake; + pstcM0PBt->DTR_f.SAFEEN = pstcConfig->bEnSafetyBk; + pstcM0PBt->DTR_f.BKSEL = pstcConfig->bEnBKSync; + pstcM0PBt->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enBkCH0AStat; + pstcM0PBt->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enBkCH0BStat; + pstcM0PBt->FLTR_f.BKP = pstcConfig->enBrakePolarity; + pstcM0PBt->FLTR_f.FLTBK = pstcConfig->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 触å‘ADC控制(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_TrigADC_Config(en_bt_unit_t enUnit, stc_bt_m23_adc_trig_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->ADTR_f.ADTE = pstcConfig->bEnTrigADC; + pstcM0PBt->ADTR_f.UEVE = pstcConfig->bEnUevTrigADC; + pstcM0PBt->ADTR_f.CMA0E = pstcConfig->bEnCH0ACmpTrigADC; + pstcM0PBt->ADTR_f.CMB0E = pstcConfig->bEnCH0BCmpTrigADC; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer 死区功能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_DT_Config(en_bt_unit_t enUnit, stc_bt_m23_dt_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->DTR_f.DTEN = pstcConfig->bEnDeadTime; + pstcM0PBt->DTR_f.DTR = pstcConfig->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer é‡å¤å‘¨æœŸè®¾ç½®(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] u8ValidPeriod é‡å¤å‘¨æœŸå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_SetValidPeriod(en_bt_unit_t enUnit, uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer OCREF清除功能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_OCRefClr(en_bt_unit_t enUnit, stc_bt_m23_OCREF_Clr_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.OCCS = pstcConfig->enOCRefClrSrcSel; + pstcM0PBt->M23CR_f.OCCE = pstcConfig->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 使能DMA传输(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnDMA(en_bt_unit_t enUnit, stc_bt_m23_trig_dma_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UDE = pstcConfig->bUevTrigDMA; + pstcM0PBt->M23CR_f.TDE = pstcConfig->bTITrigDMA; + pstcM0PBt->CRCH0_f.CDEA = pstcConfig->bCmpATrigDMA; + pstcM0PBt->CRCH0_f.CDEB = pstcConfig->bCmpBTrigDMA; + pstcM0PBt->MSCR_f.CCDS = pstcConfig->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer æ•èŽ·æ¯”较A软件触å‘(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpA(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGA = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer æ•èŽ·æ¯”较B软件触å‘(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrigCapCmpB(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->CRCH0_f.CCGB = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件更新使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwUev(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件触å‘使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwTrig(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer 软件刹车使能(模å¼23) + ** + ** + ** \param [in] enUnit Timer通é“选择（TIM0ã€TIM1ã€TIM2） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Bt_M23_EnSwBk(en_bt_unit_t enUnit) +{ + en_result_t enResult = Ok; + volatile M0P_TIM0_MODE23_TypeDef *pstcM0PBt = (M0P_TIM0_MODE23_TypeDef *)((uint32_t)M0P_TIM0_MODE23+0x100*enUnit); + ASSERT(IS_VALID_TIM(enUnit)); + + pstcM0PBt->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // BtGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/crc.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/crc.c new file mode 100644 index 0000000000..23b6b0bf69 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/crc.c @@ -0,0 +1,438 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c + ** + ** Common API of crc. + ** @link crcGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "crc.h" +/** + ******************************************************************************* + ** \addtogroup CrcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu8Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—节数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint16_t CRC16_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT = 0xFFFF; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu16Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆåŠå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint16_t CRC16_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu32Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint16_t CRC16_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu8Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—节数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check8(uint8_t* pu8Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((((uint32_t)u16CRC)>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)(((uint32_t)u16CRC>>8)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu16Data 待校验数æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆåŠå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check16(uint16_t* pu16Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFF; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = u16CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu32Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC16_Check32(uint32_t* pu32Data, uint32_t u32Len, uint16_t u16CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 0; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = ((uint16_t)u16CRC); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu8Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—节数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint32_t CRC32_Get8(uint8_t* pu8Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT = 0xFFFFFFFFu; + for(u32Index = 0;u32IndexDATA))) = pu8Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu16Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆåŠå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint32_t CRC32_Get16(uint16_t* pu16Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 ç¼–ç (å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽç”ŸæˆCRC16ç¼–ç . + ** + ** \param [in] pu32Data å¾…ç¼–ç æ•°æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len å¾…ç¼–ç æ•°æ®é•¿åº¦ï¼ˆå­—数） + ** + ** \retval CRC16 CRC16ç¼–ç å€¼. + *****************************************************************************/ +uint32_t CRC32_Get32(uint32_t* pu32Data, uint32_t u32Len) +{ + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA_f.DATA = pu32Data[u32Index]; + } + + return (M0P_CRC->RESULT_f.RESULT); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(字节填充方å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu8Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—节方å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—节数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check8(uint8_t* pu8Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu8Data[u32Index]; + } + + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>0)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>8)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>16)&0xFF); + *((volatile uint8_t*)(&(M0P_CRC->DATA))) = (uint8_t)((u32CRC>>24)&0xFF); + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(åŠå­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu16Data 待校验数æ®æŒ‡é’ˆï¼ˆåŠå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆåŠå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check16(uint16_t* pu16Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu16Data[u32Index]; + } + + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>0)&0xFFFF); + *((volatile uint16_t*)(&(M0P_CRC->DATA))) = (uint16_t)((u32CRC>>16)&0xFFFF); + + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief CRC16 校验(å­—å¡«å……æ–¹å¼) + ** + ** 该函数主è¦ç”¨äºŽå¯¹æ•°æ®åŠCRC16值进行校验. + ** + ** \param [in] pu32Data 待校验数æ®æŒ‡é’ˆï¼ˆå­—æ–¹å¼è¾“入） + ** \param [in] u32Len 待校验数æ®é•¿åº¦ï¼ˆå­—数） + ** \param [in] u16CRC 待校验CRC16值 + ** + ** \retval Ok CRC校验正确 + ** \retval Error CRC校验错误 + *****************************************************************************/ +en_result_t CRC32_Check32(uint32_t* pu32Data, uint32_t u32Len, uint32_t u32CRC) +{ + en_result_t enResult = Ok; + uint32_t u32Index = 0; + + M0P_CRC->CR_f.CR = 1; + M0P_CRC->RESULT_f.RESULT = 0xFFFFFFFFu; + for (u32Index=0; u32IndexDATA))) = pu32Data[u32Index]; + } + + *((volatile uint32_t*)(&(M0P_CRC->DATA))) = u32CRC; + + enResult = M0P_CRC->CR_f.FLAG ? Ok : Error; + + return (enResult); +} +//@} // CrcGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c new file mode 100644 index 0000000000..13d1e25040 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/ddl.c @@ -0,0 +1,292 @@ +/******************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file ddl.c + ** + ** Common API of DDL. + ** @link ddlGroup Some description @endlink + ** + ** - 2018-04-15 + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ddl.h" + +/** + ****************************************************************************** + ** \addtogroup DDL Common Functions + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#ifndef __DEBUG +#define __DEBUG +//#define __CC_ARM +#endif + +uint32_t Log2(uint32_t u32Val) +{ + uint32_t u32V1 = 0; + + if(0u == u32Val) + { + return 0; + } + + while(u32Val > 1u) + { + u32V1++; + u32Val /=2; + } + + return u32V1; +} + + +/** + ******************************************************************************* + ** \brief Memory clear function for DDL_ZERO_STRUCT() + ******************************************************************************/ +void ddl_memclr(void *pu8Address, uint32_t u32Count) +{ + uint8_t *pu8Addr = (uint8_t *)pu8Address; + + if(NULL == pu8Addr) + { + return; + } + + while (u32Count--) + { + *pu8Addr++ = 0; + } +} + +/** + ***************************************************************************** + ** \brief Hook function, which is called in polling loops + *****************************************************************************/ +void DDL_WAIT_LOOP_HOOK(void) +{ + // Place code for triggering Watchdog counters here, if needed +} + +/** + ***************************************************************************** + ** \brief debug printf function. + *****************************************************************************/ +void Debug_UartInit(void) +{ + +} + +void Debug_Output(uint8_t u8Data) +{ + +} + +extern void Debug_UartInit(void); +extern void Debug_Output(uint8_t u8Data); + +#if defined (__CC_ARM) //KEIL +#pragma import(__use_no_semihosting) +void _sys_exit(int x) +{ + (void)x; +} +struct __FILE +{ + int handle; + /* Whatever you require here. If the only file you are using is */ + /* standard output using printf() for debugging, no file handling */ +/* is required. */ +}; +/* FILE is typedef?d in stdio.h. */ +FILE __stdout; + +#endif + +#ifdef __DEBUG +/** + ****************************************************************************** + ** \brief Re-target putchar function + ******************************************************************************/ +int fputc(int ch, FILE *f) +{ + + if (((uint8_t)ch) == '\n') + { + Debug_Output('\r'); + } + Debug_Output(ch); + + return ch; +} +#endif + +void _ttywrch(int c) +{ +} + + +int __backspace(void) +{ + return 0; +} + + + +/** + * \brief delay1ms + * delay approximately 1ms. + * \param [in] u32Cnt + * \retval void + */ +void delay1ms(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + u32end = 0x1000000 - SystemCoreClock/1000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay100us + * delay approximately 100us. + * \param [in] u32Cnt + * \retval void + */ +void delay100us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/10000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + +/** + * \brief delay10us + * delay approximately 10us. + * \param [in] u32Cnt + * \retval void + */ +void delay10us(uint32_t u32Cnt) +{ + uint32_t u32end; + + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + + while(u32Cnt-- > 0) + { + SysTick->VAL = 0; + + u32end = 0x1000000 - SystemCoreClock/100000; + while(SysTick->VAL > u32end) + { + ; + } + } + + SysTick->CTRL = (SysTick->CTRL & (~SysTick_CTRL_ENABLE_Msk)); +} + + +//@} // DDL Functions + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/debug.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/debug.c new file mode 100644 index 0000000000..3084bf3b83 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/debug.c @@ -0,0 +1,119 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file debug.c + ** + ** Common API of debug. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "debug.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief 调试模å¼ä¸‹æ¨¡å—功能使能 + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveEnable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE &= ~enModule; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 调试模å¼ä¸‹æ¨¡å—åŠŸèƒ½æš‚åœ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Debug_ActiveDisable(en_debug_module_active_t enModule) +{ + M0P_DEBUG_ACTIVE->DEBUG_ACTIVE |= enModule; + + return Ok; +} + + +//@} // BgrGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c new file mode 100644 index 0000000000..1003e61def --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/dmac.c @@ -0,0 +1,1537 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file dmac.c +** +** A detailed description is available at +** @link DmacGroup Dmac description @endlink +** +** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac. +** +******************************************************************************/ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "dmac.h" + +/** +******************************************************************************* +** \addtogroup DmacGroup +******************************************************************************/ +//@{ + +/******************************************************************************* +* Local type definitions ('typedef') +******************************************************************************/ + +/******************************************************************************* +* Local pre-processor symbols/macros ('#define') +******************************************************************************/ + +/******************************************************************************/ +/* DMA */ +/******************************************************************************/ +/***************** Bits definition for DMA_INTSTAT0 register ****************/ +#define DMA_INTSTAT0_TRNERR_Pos (0U) /*!< DMA_INTSTAT0: TRNERR Position */ +#define DMA_INTSTAT0_REQERR_Pos (16U) /*!< DMA_INTSTAT0: REQERR Position */ + +/***************** Bits definition for DMA_INTSTAT1 register ****************/ +#define DMA_INTSTAT1_TC_Pos (0U) /*!< DMA_INTSTAT1: TC Position */ +#define DMA_INTSTAT1_BTC_Pos (16U) /*!< DMA_INTSTAT1: BTC Position */ + +/***************** Bits definition for DMA_INTMASK0 register ****************/ +#define DMA_INTMASK0_MSKTRNERR_Pos (0U) /*!< DMA_INTMASK0: MSKTRNERR Position */ +#define DMA_INTMASK0_MSKREQERR_Pos (16U) /*!< DMA_INTMASK0: MSKREQERR Position */ + +/***************** Bits definition for DMA_INTMASK1 register ****************/ +#define DMA_INTMASK1_MSKTC_Pos (0U) /*!< DMA_INTMASK1: MSKTC Position */ +#define DMA_INTMASK1_MSKBTC_Pos (16U) /*!< DMA_INTMASK1: MSKBTC Position */ + +/***************** Bits definition for DMA_INTCLR0 register *****************/ +#define DMA_INTCLR0_CLRTRNERR_Pos (0U) /*!< DMA_INTCLR0: CLRTRNERR Position */ +#define DMA_INTCLR0_CLRREQERR_Pos (16U) /*!< DMA_INTCLR0: CLRREQERR Position */ + +/***************** Bits definition for DMA_INTCLR1 register *****************/ +#define DMA_INTCLR1_CLRTC_Pos (0U) /*!< DMA_INTCLR1: CLRTC Position */ +#define DMA_INTCLR1_CLRBTC_Pos (16U) /*!< DMA_INTCLR1: CLRBTC Position */ + +/******************* Bits definition for DMA_CHEN register ******************/ +#define DMA_CHEN_CHEN_Pos (0U) /*!< DMA_CHEN: CHEN Position */ + +/************** Bits definition for DMA_TRGSELx(x=0~7) register *************/ +#define DMA_TRGSEL_TRGSEL_Pos (0U) /*!< DMA_TRGSELx: TRGSEL Position */ +#define DMA_TRGSEL_TRGSEL_Msk (0x1FFU << DMA_TRGSEL_TRGSEL_Pos) /*!< DMA_TRGSELx: TRGSEL Mask 0x000001FF */ +#define DMA_TRGSEL_TRGSEL DMA_TRGSEL_TRGSEL_Msk +/************** Bits definition for DMA_DTCTLx(x=0~7) register **************/ +#define DMA_DTCTL_BLKSIZE_Pos (0U) /*!< DMA_DTCTLx: BLKSIZE Position */ +#define DMA_DTCTL_BLKSIZE_Msk (0x3FFU << DMA_DTCTL_BLKSIZE_Pos) /*!< DMA_DTCTLx: BLKSIZE Mask 0x000003FF */ +#define DMA_DTCTL_BLKSIZE DMA_DTCTL_BLKSIZE_Msk + +#define DMA_DTCTL_CNT_Pos (16U) /*!< DMA_DTCTLx: CNT Position */ +#define DMA_DTCTL_CNT_Msk (0xFFFFU << DMA_DTCTL_CNT_Pos) /*!< DMA_DTCTLx: CNT Mask 0xFFFF0000 */ +#define DMA_DTCTL_CNT DMA_DTCTL_CNT_Msk + +/*************** Bits definition for DMA_RPTx(x=0~7) register ***************/ +#define DMA_RPT_SRPT_Pos (0U) /*!< DMA_RPTx: SRPT Position */ +#define DMA_RPT_SRPT_Msk (0x1FFU << DMA_RPT_SRPT_Pos) /*!< DMA_RPTx: SRPT Mask 0x000001FF */ +#define DMA_RPT_SRPT DMA_RPT_SRPT_Msk + +#define DMA_RPT_DRPT_Pos (16U) /*!< DMA_RPTx: DRPT Position */ +#define DMA_RPT_DRPT_Msk (0x1FFU << DMA_RPT_DRPT_Pos) /*!< DMA_RPTx: DRPT Mask 0x01FF0000 */ +#define DMA_RPT_DRPT DMA_RPT_DRPT_Msk + +/************* Bits definition for DMA_SNSEQCTLx(x=0~7) register ************/ +#define DMA_SNSEQCTL_SOFFSET_Pos (0U) /*!< DMA_SNSEQCTLx: SOFFSET Position */ +#define DMA_SNSEQCTL_SOFFSET_Msk (0xFFFFFU << DMA_SNSEQCTL_SOFFSET_Pos) /*!< DMA_SNSEQCTLx: SOFFSET Mask 0x000FFFFF */ +#define DMA_SNSEQCTL_SOFFSET DMA_SNSEQCTL_SOFFSET_Msk + +#define DMA_SNSEQCTL_SNSCNT_Pos (20U) /*!< DMA_SNSEQCTLx: SNSCNT Position */ +#define DMA_SNSEQCTL_SNSCNT_Msk (0xFFFU << DMA_SNSEQCTL_SNSCNT_Pos) /*!< DMA_SNSEQCTLx: SNSCNT Mask 0xFFF00000 */ +#define DMA_SNSEQCTL_SNSCNT DMA_SNSEQCTL_SNSCNT_Msk + +/************* Bits definition for DMA_DNSEQCTLx(x=0~7) register ************/ +#define DMA_DNSEQCTL_DOFFSET_Pos (0U) /*!< DMA_DNSEQCTLx: DOFFSET Position */ +#define DMA_DNSEQCTL_DOFFSET_Msk (0xFFFFFU << DMA_DNSEQCTL_DOFFSET_Pos) /*!< DMA_DNSEQCTLx: DOFFSET Mask 0x000FFFFF */ +#define DMA_DNSEQCTL_DOFFSET DMA_DNSEQCTL_DOFFSET_Msk + +#define DMA_DNSEQCTL_DNSCNT_Pos (20U) /*!< DMA_DNSEQCTLx: DNSCNT Position */ +#define DMA_DNSEQCTL_DNSCNT_Msk (0xFFFU << DMA_DNSEQCTL_DNSCNT_Pos) /*!< DMA_DNSEQCTLx: DNSCNT Mask 0xFFF00000 */ +#define DMA_DNSEQCTL_DNSCNT DMA_DNSEQCTL_DNSCNT_Msk + +/*************** Bits definition for DMA_CHxCTL(x=0~7) register *************/ +#define DMA_CHCTL_SINC_Pos (0U) /*!< DMA_CHxCTL: SINC Position */ +#define DMA_CHCTL_SINC_Msk (0x3u << DMA_CHCTL_SINC_Pos) /*!< DMA_CHxCTL: SINC Mask 0x00000003 */ +#define DMA_CHCTL_SINC DMA_CHCTL_SINC_Msk + +#define DMA_CHCTL_DINC_Pos (2U) /*!< DMA_CHxCTL: DINC Position */ +#define DMA_CHCTL_DINC_Msk (0x3U << DMA_CHCTL_DINC_Pos) /*!< DMA_CHxCTL: DINC Mask 0x0000000C */ +#define DMA_CHCTL_DINC DMA_CHCTL_DINC_Msk + +#define DMA_CHCTL_SRPTEN_Pos (4U) /*!< DMA_CHxCTL: SRPTEN Position */ +#define DMA_CHCTL_DRPTEN_Pos (5U) /*!< DMA_CHxCTL: DRPTEN Position */ +#define DMA_CHCTL_SNSEQEN_Pos (6U) /*!< DMA_CHxCTL: SNSEQEN Position */ +#define DMA_CHCTL_DNSEQEN_Pos (7U) /*!< DMA_CHxCTL: DNSEQEN Position */ + +#define DMA_CHCTL_HSIZE_Pos (8U) /*!< DMA_CHxCTL: HSIZE Position */ +#define DMA_CHCTL_HSIZE_Msk (0x3U << DMA_CHCTL_HSIZE_Pos) /*!< DMA_CHxCTL: HSIZE Mask 0x00000300 */ +#define DMA_CHCTL_HSIZE DMA_CHCTL_HSIZE_Msk + +#define DMA_CHCTL_LLPEN_Pos (10U) /*!< DMA_CHxCTL: LLPEN Position */ +#define DMA_CHCTL_LLPRUN_Pos (11U) /*!< DMA_CHxCTL: LLPRUN Position */ +#define DMA_CHCTL_IE_Pos (12U) /*!< DMA_CHxCTL: IE Position */ +#define DMA_CHCTL_PROT_Pos (13U) /*!< DMA_CHxCTL: PROT Position */ + +/************************ DMA_TRGSELx(x=0~7) register ***********************/ +#define DMA_TRGSEL_BASE (0x40010854U) +#define DMA_TRGSEL(x) (*(volatile uint32_t *)((x) * 0x4U + DMA_TRGSEL_BASE)) + +#define INTC_INTSFTTRG_BASE (0x40010800U) +#define INTC_INTSFTTRG (*(volatile uint32_t *)INTC_INTSFTTRG_BASE) + +/*********************** DMA REGISTERx(x=0~7) register **********************/ +#define _DMA_CH_REG_OFFSET(ch) ((ch) * 0x40U) +#define _DMA_CH_REG(reg_base, ch) (*(volatile uint32_t *)((reg_base) + _DMA_CH_REG_OFFSET(ch))) + +#define WRITE_DMA_CH_REG(reg_base, ch, val) (_DMA_CH_REG((reg_base), (ch)) = (val)) +#define READ_DMA_CH_REG(reg_base, ch) (_DMA_CH_REG((reg_base), (ch))) + +#define SET_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) |= (1U << (pos))) +#define CLR_DMA_CH_REG_BIT(reg_base, ch, pos) (_DMA_CH_REG((reg_base), (ch)) &= (~(1U << (pos)))) + + +/********************** SET DMA_TRGSELx(x=0~7) register *********************/ + +#define SET_DMA_CHCTL_PROT(CH, PROT) SET_DMA_CHCTL_PROT((CH), (PROT)) + +/************************** SET INTSFTTRG register **************************/ +#define SOFTWARE_TRIGGER_DMA() (INTC_INTSFTTRG = 1U) + +/*! Parameter valid check for Dmac Channel. */ +#define IS_VALID_CH(x) \ +( (DmaCh0 == (x)) || \ + (DmaCh1 == (x))) + +/*! Parameter valid check for Dmac transfer data width. */ +#define IS_VALID_TRN_WIDTH(x) \ +( (Dma8Bit == (x)) || \ + (Dma16Bit == (x)) || \ + (Dma32Bit == (x))) + +/*! Parameter valid check for Dmac address mode. */ +#define IS_VALID_ADDR_MODE(x) \ +( (AddressFix == (x)) || \ + (AddressIncrease == (x))) + +#define IS_VALID_PRIO_MODE(x) \ +( (DmaPriorityFix == (x)) || \ + (DmaPriorityLoop == (x))) + +/*! Parameter valid check for Dmac transfer block size. */ +#define IS_VALID_BLKSIZE(x) (!((x) & ~(DMA_DTCTL_BLKSIZE_Msk >> DMA_DTCTL_BLKSIZE_Pos))) + +/*! Parameter valid check for Dmac transfer count. */ +#define IS_VALID_TRNCNT(x) (!((x) & ~(DMA_DTCTL_CNT_Msk >> DMA_DTCTL_CNT_Pos))) + +/*! Parameter valid check for Dmac destination repeat size. */ +#define IS_VALID_DRPT_SIZE(x) (!((x) & ~(DMA_RPT_DRPT_Msk >> DMA_RPT_DRPT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence count. */ +#define IS_VALID_SNSCNT(x) (!((x) & ~(DMA_SNSEQCTL_SNSCNT_Msk >> DMA_SNSEQCTL_SNSCNT_Pos))) + +/*! Parameter valid check for Dmac source no-sequence offset. */ +#define IS_VALID_SNSOFFSET(x) (!((x) & ~(DMA_SNSEQCTL_SOFFSET_Msk >> DMA_SNSEQCTL_SOFFSET_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence count. */ +#define IS_VALID_DNSCNT(x) (!((x) & ~(DMA_DNSEQCTL_DNSCNT_Msk >> DMA_DNSEQCTL_DNSCNT_Pos))) + +/*! Parameter valid check for Dmac destination no-sequence offset. */ +#define IS_VALID_DNSOFFSET(x) (!((x) & ~(DMA_DNSEQCTL_DOFFSET_Msk >> DMA_DNSEQCTL_DOFFSET_Pos))) + +/******************************************************************************* +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + +/******************************************************************************* +* Local function prototypes ('static') +******************************************************************************/ + +/******************************************************************************* +* Local variable definitions ('static') +******************************************************************************/ +static stc_dma_irq_calbakfn_pt_t stcDmaIrqCalbaks = {NULL, NULL,NULL, NULL}; +/******************************************************************************* +* Function implementation - global ('extern') and local ('static') +******************************************************************************/ + +/** +******************************************************************************* +** \brief Initializes a DMA channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] pstcConfig The structure pointer of DMA module configuration. +** +** \retval Ok Initializes successfully. +** \retval ErrorInvalidParameter enCh is invalid or the pstcConfig is NULL. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(NULL != pstcConfig); + ASSERT(IS_VALID_BLKSIZE(pstcConfig->u16BlockSize)); + ASSERT(IS_VALID_TRNCNT(pstcConfig->u16TransferCnt)); + ASSERT(IS_VALID_TRN_WIDTH(pstcConfig->enTransferWidth)); + ASSERT(IS_VALID_ADDR_MODE(pstcConfig->enSrcAddrMode)); + ASSERT(IS_VALID_ADDR_MODE(pstcConfig->enDstAddrMode)); + + /* Check for channel and NULL pointer */ + if (!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FIS_IE = 0; + M0P_DMAC->CONFB0_f.ERR_IE = 0; /* Disable DMAC interrupt */ + + /******************* SET DMA MODE ******************/ + M0P_DMAC->CONFB0_f.MODE = pstcConfig->enMode; + /******************* SET DMA_TRGSELx register ******************/ + M0P_DMAC->CONFA0_f.TRI_SEL = pstcConfig->enRequestNum; + /******************* SET DMA_DTCTLx(x=0~7) register ******************/ + /* Block size */ + M0P_DMAC->CONFA0_f.BC = pstcConfig->u16BlockSize - 1; + /* Transfer count */ + M0P_DMAC->CONFA0_f.TC = pstcConfig->u16TransferCnt - 1; + + /******************* SET DMA_CHxCTL(x=0~7) register ******************/ + /* Transfer width */ + M0P_DMAC->CONFB0_f.WIDTH = pstcConfig->enTransferWidth; + + /****************************** source address contrl *******************/ + /* source address mode */ + M0P_DMAC->CONFB0_f.FS = pstcConfig->enSrcAddrMode; + /* Source address */ + M0P_DMAC->SRCADR0_f.SRCADR = pstcConfig->u32SrcAddress; + + /*************************** destination address contrl *******************/ + /* destination address mode */ + M0P_DMAC->CONFB0_f.FD = pstcConfig->enDstAddrMode; + /* Destination address */ + M0P_DMAC->DSTADR0_f.DSTADR = pstcConfig->u32DstAddress; + /********************* Source address reload control ********************/ + M0P_DMAC ->CONFB0_f.RS = pstcConfig->bSrcAddrReloadCtl; + + /******************* Destination address reload control *****************/ + M0P_DMAC ->CONFB0_f.RD = pstcConfig->bDestAddrReloadCtl; + + /******************* Destination bc/tc reload control *****************/ + M0P_DMAC ->CONFB0_f.RC = pstcConfig->bSrcBcTcReloadCtl; + + /******************* MSK control *****************/ + M0P_DMAC->CONFB0_f.MSK = pstcConfig->bMsk; + + } + else{ + M0P_DMAC->CONFB1_f.FIS_IE = 0; + M0P_DMAC->CONFB1_f.ERR_IE = 0; /* Disable DMAC interrupt */ + /******************* SET DMA MODE ******************/ + M0P_DMAC->CONFB1_f.MODE = pstcConfig->enMode; + /******************* SET DMA_TRGSELx register ******************/ + M0P_DMAC->CONFA1_f.TRI_SEL = pstcConfig->enRequestNum; + /******************* SET DMA_DTCTLx(x=0~7) register ******************/ + /* Block size */ + M0P_DMAC->CONFA1_f.BC = pstcConfig->u16BlockSize - 1; + /* Transfer count */ + M0P_DMAC->CONFA1_f.TC = pstcConfig->u16TransferCnt - 1; + + /******************* SET DMA_CHxCTL(x=0~7) register ******************/ + /* Transfer width */ + M0P_DMAC->CONFB1_f.WIDTH = pstcConfig->enTransferWidth; + + /****************************** source address contrl *******************/ + /* source address mode */ + M0P_DMAC->CONFB1_f.FS = pstcConfig->enSrcAddrMode; + /* Source address */ + M0P_DMAC->SRCADR1_f.SRCADR = pstcConfig->u32SrcAddress; + + /*************************** destination address contrl *******************/ + /* destination address mode */ + M0P_DMAC->CONFB1_f.FD = pstcConfig->enDstAddrMode; + /* Destination address */ + M0P_DMAC->DSTADR1_f.DSTADR = pstcConfig->u32DstAddress; + + /********************* Source address reload control ********************/ + M0P_DMAC ->CONFB1_f.RS = pstcConfig->bSrcAddrReloadCtl; + + /******************* Destination address reload control *****************/ + M0P_DMAC ->CONFB1_f.RD = pstcConfig->bDestAddrReloadCtl; + + /******************* Destination bc/tc reload control *****************/ + M0P_DMAC ->CONFB1_f.RC = pstcConfig->bSrcBcTcReloadCtl; + + /******************* MSK control *****************/ + M0P_DMAC->CONFB1_f.MSK = pstcConfig->bMsk; + } + return Ok; +} + +/** +******************************************************************************* +** \brief Trigger dma transfer by software. +** +** \param [in] enCh The specified dma channel. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_SwTrigger(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.TRI_SEL = 0x0000; + } + else{ + M0P_DMAC->CONFA1_f.TRI_SEL = 0x0000; + } +} + +/** +******************************************************************************* +** \brief Enable dma function. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Enable(void) +{ + M0P_DMAC->CONF_f.EN = 1; +} + +/** +******************************************************************************* +** \brief Disable dma function. +** +** \param None +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Disable(void) +{ + M0P_DMAC->CONF_f.EN = 0; +} +/** +******************************************************************************* +** \brief Start dma function. +** +** \param [in] enCh The specified dma channel. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Start(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ST = 1; + } + else{ + M0P_DMAC->CONFA1_f.ST = 1; + } +} + +/** +******************************************************************************* +** \brief Disable dma function. +** +** \param [in] enCh The specified dma channel. +** +** \retval None +** +** \note None +** +******************************************************************************/ +void Dma_Stop(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ST = 0; + } + else{ + M0P_DMAC->CONFA1_f.ST = 0; + } +} +/** +******************************************************************************* +** \brief Enable the specified dma interrupt. +** +** \param [in] enCh The specified dma channel. +** \param [in] enIrqSel The specified dma flag. +** \arg TrnErrIrq The DMA transfer error interrupt. +** \arg TrnReqErrIrq DMA transfer req over error interrupt. +** \arg TrnCpltIrq DMA transfer completion interrupt. +** \arg BlkTrnCpltIrq DMA block completion interrupt. +** +** \retval Ok Interrupt enabled normally. +** \retval ErrorInvalidParameter enCh or enIrqSel is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableIrq(en_dma_channel_t enCh, stc_dma_irq_sel_t stcIrqSel) +{ + en_result_t enRet = Ok; + + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if (TRUE == stcIrqSel.TrnCpltIrq) + { + Dma_EnableChannelIrq(enCh); + } + if(TRUE == stcIrqSel.TrnErrIrq) + { + Dma_EnableChannelErrIrq(enCh); + } + + return enRet; +} + +/** +******************************************************************************* +** \brief Enable the specified dma interrupt. +** +** \param [in] enCh The specified dma channel. +** \param [in] enIrqSel The specified dma flag. +** \arg TrnErrIrq The DMA transfer error interrupt. +** \arg TrnReqErrIrq DMA transfer req over error interrupt. +** \arg TrnCpltIrq DMA transfer completion interrupt. +** \arg BlkTrnCpltIrq DMA block completion interrupt. +** +** \retval Ok Interrupt disabled normally. +** \retval ErrorInvalidParameter enCh or enIrqSel is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableIrq(en_dma_channel_t enCh, stc_dma_irq_sel_t stcIrqSel) +{ + en_result_t enRet = Ok; + + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if (TRUE == stcIrqSel.TrnCpltIrq) + { + Dma_DisableChannelIrq(enCh); + } + if(TRUE == stcIrqSel.TrnErrIrq) + { + Dma_DisableChannelErrIrq(enCh); + } + + return enRet; +} + +/** +******************************************************************************* +** \brief Enable the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable channel successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableChannel(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ENS = 1; + } + else{ + M0P_DMAC->CONFA1_f.ENS = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Disable the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable channel successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableChannel(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.ENS = 0;; + } + else { + M0P_DMAC->CONFA1_f.ENS = 0;; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the specified dma trigger. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16TrgSel The trigger selection number. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16TrgSel is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetTriggerSel(en_dma_channel_t enCh, en_dma_trig_sel_t enTrgSel) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.TRI_SEL = enTrgSel;; + } + else{ + M0P_DMAC->CONFA1_f.TRI_SEL = enTrgSel;; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Setthe source address of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The source address. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->SRCADR0_f.SRCADR = u32Address; + } + else + { + M0P_DMAC->SRCADR1_f.SRCADR = u32Address;; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination address of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The destination address. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->DSTADR0_f.DSTADR = u32Address; + } + else + { + M0P_DMAC->DSTADR1_f.DSTADR = u32Address; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the block size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The block size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16BlkSize is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_BLKSIZE(u16BlkSize)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_BLKSIZE(u16BlkSize))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.BC = u16BlkSize - 1; + } + else + { + M0P_DMAC->CONFA1_f.BC = u16BlkSize - 1; + } + return Ok; +} + +/** +******************************************************************************* +** \brief Set the transfer count of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u32Address The transfer count. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16TrnCnt is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_TRNCNT(u16TrnCnt)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_TRNCNT(u16TrnCnt))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.TC = u16TrnCnt - 1; + } + else + { + M0P_DMAC->CONFA1_f.TC = u16TrnCnt - 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the source repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The source repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableSourceRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RS = 1; + } + else + { + M0P_DMAC ->CONFB1_f.RS = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The destination repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableSourceRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RS = 0; + } + else{ + M0P_DMAC ->CONFB1_f.RS = 0; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the source repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The source repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableDestinationRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RD = 1; + } + else { + M0P_DMAC ->CONFB1_f.RD = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The destination repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableDestinationRload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RD = 0; + } + else{ + M0P_DMAC ->CONFB1_f.RD = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Set the source repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The source repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableBcTcReload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RC = 1; + } + else{ + M0P_DMAC ->CONFB1_f.RC = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination repeat size of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] u16Size The destination repeat size. +** +** \retval Ok Set successfully. +** \retval ErrorInvalidParameter enCh or u16Size is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableBcTcReload(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC ->CONFB0_f.RC = 0; + } + else{ + M0P_DMAC ->CONFB1_f.RC = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Set the source address mode of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enMode The specified dma address mode. +** \arg AddressFix Address fixed. +** \arg AddressIncrease Address increased. +** \arg AddressDecrease Address decreased. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enMode is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetSourceIncMode(en_dma_channel_t enCh, en_address_mode_t enMode) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_ADDR_MODE(enMode)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_ADDR_MODE(enMode))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FS = enMode; + } + else{ + M0P_DMAC->CONFB1_f.FS = enMode; + } + + + return Ok; +} + +/** +******************************************************************************* +** \brief Set the destination address mode of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enMode The specified dma address mode. +** \arg AddressFix Address fixed. +** \arg AddressIncrease Address increased. +** \arg AddressDecrease Address decreased. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enMode is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetDestinationIncMode(en_dma_channel_t enCh, en_address_mode_t enMode) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_ADDR_MODE(enMode)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_ADDR_MODE(enMode))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FD = enMode; + } + else{ + M0P_DMAC->CONFB1_f.FD = enMode; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Enable source repeat function of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableContinusTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.MSK = 1; + } + else{ + M0P_DMAC->CONFB1_f.MSK = 1; + } + return Ok; +} + +/** +******************************************************************************* +** \brief Disable source repeat function of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableContinusTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.MSK = 0; + } + else{ + M0P_DMAC->CONFB1_f.MSK = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Halt the all dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +void Dma_HaltTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x1; +} +/** +******************************************************************************* +** \brief Recover all dma channel from HALT. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +void Dma_RecoverTranfer(void) +{ + M0P_DMAC->CONF_f.HALT = 0x0; +} +/** +******************************************************************************* +** \brief Pause the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_PauseChannelTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.PAS = 1; + } + else{ + M0P_DMAC->CONFA1_f.PAS = 1; + } + return Ok; +} +/** +******************************************************************************* +** \brief Recover the specified dma channel from PAUSE. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_RecoverChannelTranfer(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if((!IS_VALID_CH(enCh))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFA0_f.PAS = 0; + } + else{ + M0P_DMAC->CONFA1_f.PAS = 0; + } + return Ok; +} +/** +******************************************************************************* +** \brief Set transfer data width of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enWidth The specified transfer data width. +** \arg Dma8Bit The 8 bit transfer via DMA. +** \arg Dma16Bit The 16 bit transfer via DMA. +** \arg Dma32Bit The 32 bit transfer via DMA. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enWidth is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth) +{ + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_TRN_WIDTH(enWidth)); + + if((!IS_VALID_CH(enCh)) || (!IS_VALID_TRN_WIDTH(enWidth))) + { + return ErrorInvalidParameter; + } + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.WIDTH = enWidth; + } + else{ + M0P_DMAC->CONFB1_f.WIDTH = enWidth; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Set priority of dma channel. +** +** \param [in] enCh The specified dma channel. +** \param [in] enWidth The specified transfer data width. +** \arg Dma8Bit The 8 bit transfer via DMA. +** \arg Dma16Bit The 16 bit transfer via DMA. +** \arg Dma32Bit The 32 bit transfer via DMA. +** +** \retval Ok Set successfully +** \retval ErrorInvalidParameter enCh or enWidth is invalid +** +** \note None +** +******************************************************************************/ +en_result_t Dma_SetChPriority(en_dma_priority_t enPrio) +{ + ASSERT(IS_VALID_PRIO_MODE(enPrio)); + + if(!IS_VALID_PRIO_MODE(enPrio)) + { + return ErrorInvalidParameter; + } + + M0P_DMAC->CONF_f.PRIO = enPrio; + return Ok; +} +/** +******************************************************************************* +** \brief Enable interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableChannelIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FIS_IE = 1; + } + else{ + M0P_DMAC->CONFB1_f.FIS_IE = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Disable interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableChannelIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.FIS_IE = 0; + } + else{ + M0P_DMAC->CONFB1_f.FIS_IE = 0; + } + + return Ok; +} +/** +******************************************************************************* +** \brief Enable error interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Enable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_EnableChannelErrIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.ERR_IE = 1; + } + else{ + M0P_DMAC->CONFB1_f.ERR_IE = 1; + } + + return Ok; +} + +/** +******************************************************************************* +** \brief Disable error interrupt of the specified dma channel. +** +** \param [in] enCh The specified dma channel. +** +** \retval Ok Disable successfully. +** \retval ErrorInvalidParameter enCh is invalid. +** +** \note None +** +******************************************************************************/ +en_result_t Dma_DisableChannelErrIrq(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.ERR_IE = 0; + } + else{ + M0P_DMAC->CONFB1_f.ERR_IE = 0; + } + + return Ok; +} + +/** + * \brief + * Dma中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param 未使用 + * + * \retval æ—  + */ + +void Dma_IRQHandler(uint8_t u8Param) +{ + if((DmaAddOverflow == M0P_DMAC->CONFB0_f.STAT)||(DmaHALT == M0P_DMAC->CONFB0_f.STAT)||(DmaAccSCRErr == M0P_DMAC->CONFB0_f.STAT) ||(DmaAccDestErr == M0P_DMAC->CONFB0_f.STAT)) + { + if (NULL != stcDmaIrqCalbaks.pfnDma0TranferErrIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq(); + } + M0P_DMAC->CONFB0_f.STAT = 0u; + } + if((DmaAddOverflow == M0P_DMAC->CONFB1_f.STAT)||(DmaHALT == M0P_DMAC->CONFB1_f.STAT)||(DmaAccSCRErr == M0P_DMAC->CONFB1_f.STAT) ||(DmaAccDestErr == M0P_DMAC->CONFB1_f.STAT)) + { + if (NULL != stcDmaIrqCalbaks.pfnDma1TranferErrIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq(); + } + M0P_DMAC->CONFB1_f.STAT = 0u; + } + if(DmaTransferComplete == M0P_DMAC->CONFB0_f.STAT) + { + if (NULL != stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq(); + } + M0P_DMAC->CONFB0_f.STAT = 0u; + } + if(DmaTransferComplete == M0P_DMAC->CONFB1_f.STAT) + { + if (NULL != stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq(); + } + M0P_DMAC->CONFB1_f.STAT = 0u; + } + +} +/** + * \brief + * é…ç½®ADCä¸­æ–­å‡½æ•°å…¥å£ + * + * \param [in] pstcAdcIrqCfg ADC中断é…置指针 + * \param [in] pstcAdcIrqCalbaks ADC中断回调函数指针 + * + * \retval æ—  + */ +en_result_t Dma_ConfigIrq(en_dma_channel_t enCh,stc_dma_irq_sel_t* stcDmaIrqCfg,stc_dma_irq_calbakfn_pt_t* pstcDmaIrqCalbaks) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return ErrorInvalidParameter; + } + if(DmaCh0 == enCh) + { + if (TRUE == stcDmaIrqCfg->TrnErrIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma0TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferErrIrq = pstcDmaIrqCalbaks->pfnDma0TranferErrIrq; + } + } + if (TRUE == stcDmaIrqCfg->TrnCpltIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma0TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma0TranferCompleteIrq = pstcDmaIrqCalbaks->pfnDma0TranferCompleteIrq; + } + } + } + else if(DmaCh1 == enCh) + { + if (TRUE == stcDmaIrqCfg->TrnErrIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma1TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferErrIrq = pstcDmaIrqCalbaks->pfnDma1TranferErrIrq; + } + } + if (TRUE == stcDmaIrqCfg->TrnCpltIrq) + { + if (NULL != pstcDmaIrqCalbaks->pfnDma1TranferCompleteIrq) + { + stcDmaIrqCalbaks.pfnDma1TranferCompleteIrq = pstcDmaIrqCalbaks->pfnDma1TranferCompleteIrq; + } + } + }else + {} + return Ok; +} +/** +** \brief +** 获å–DMAçŠ¶æ€ +** +** \param [in] enCh The specified dma channel. +** +** \retval en_dma_stat_t +** +** +** \retval æ—  +**/ +en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(!IS_VALID_CH(enCh)) + { + return DEFAULT; + } + if(enCh == DmaCh0) + { + return (en_dma_stat_t)M0P_DMAC->CONFB0_f.STAT ; + } + else{ + return (en_dma_stat_t)M0P_DMAC->CONFB1_f.STAT ; + } +} +/** +** \brief +** 获å–DMAçŠ¶æ€ +** +** \param [in] enCh The specified dma channel. +** +** \retval en_dma_stat_t +** +** +** \retval æ—  +**/ +void Dma_ClrStat(en_dma_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + + if(enCh == DmaCh0) + { + M0P_DMAC->CONFB0_f.STAT = 0x0; + } + else{ + M0P_DMAC->CONFB1_f.STAT = 0x0; + } +} + +//@} // DmacGroup + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/flash.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/flash.c new file mode 100644 index 0000000000..33b3f62b8f --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/flash.c @@ -0,0 +1,688 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file flash.c + ** + ** Common API of flash. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "flash.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define FLASH_END_ADDR (0x0000FFFFu) +#define FLASH_BYPASS() M0P_FLASH->BYPASS_f.BYSEQ = 0x5A5A;\ + M0P_FLASH->BYPASS_f.BYSEQ = 0xA5A5; +#define FLASH_IE_TRUE (0x03) +#define FLASH_IE_FALSE (0x00) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief FLASH OP + ** + ** Flash æ“作控制数æ®ç±»åž‹é‡å®šä¹‰ + ******************************************************************************/ +typedef enum en_flash_op +{ + Read = 0u, ///<读é…置值 + Program = 1u, ///<编程é…置值 + SectorErase = 2u, ///<扇区擦除é…置值 + ChipErase = 3u, ///<全片擦除é…置值 +} en_flash_op_t; + +/** + ****************************************************************************** + ** \brief FLASH LOCK + ** + ** Flash 加解é”æ•°æ®ç±»åž‹é‡å®šä¹‰ + ******************************************************************************/ +typedef enum en_flash_lock +{ + LockAll = 0x00000000u, ///<å…¨ç‰‡åŠ é” + UnlockAll = (int)0xFFFFFFFFu, ///<å…¨ç‰‡è§£é” +} en_flash_lock_t; + +/** + ****************************************************************************** + ** \brief FLASH 编程时间å‚æ•°é…ç½® + ** + ** FLASH编程时间å‚æ•°é…置数æ®ç±»åž‹é‡å®šä¹‰ (4MHz) + ******************************************************************************/ +typedef enum en_flash_prgtimer +{ + Tnvs = 0x20u, + Tpgs = 0x17u, + Tprog = 0x1Bu, + Tserase = 0x4650u, + Tmerase = 0x222E0u, + Tprcv = 0x18u, + Tsrcv = 0xF0u, + Tmrcv = 0x3E8u, +} en_flash_prgtimer_t; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnFlashCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Flash中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param == 0 + ** + *****************************************************************************/ +void EfRam_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnFlashCallback) + { + pfnFlashCallback(); + } +} + +/** + ***************************************************************************** + ** \brief Flashä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Flash_GetIntFlag(en_flash_int_type_t enFlashIntType) +{ + boolean_t bRetVal = FALSE; + + switch (enFlashIntType) + { + case FlashPCInt: + bRetVal = M0P_FLASH->IFR_f.IF0 ? TRUE : FALSE; + break; + case FlashSlockInt: + bRetVal = M0P_FLASH->IFR_f.IF1 ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Flash中断标志清除 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_ClearIntFlag(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + switch (enFlashIntType) + { + case FlashPCInt: + FLASH_BYPASS(); + M0P_FLASH->ICLR_f.ICLR0 = FALSE; + enResult = Ok; + break; + case FlashSlockInt: + FLASH_BYPASS(); + M0P_FLASH->ICLR_f.ICLR1 = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash中断使能 + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_EnableIrq (en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + switch (enFlashIntType) + { + case FlashPCInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE |= 0x01; + enResult = Ok; + break; + case FlashSlockInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE |= 0x02; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Flash中断ç¦æ­¢ + ** + ** + ** \param [in] enFlashIntType Flash中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Flash_DisableIrq(en_flash_int_type_t enFlashIntType) +{ + en_result_t enResult = Error; + + switch (enFlashIntType) + { + case FlashSlockInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE &= ~0x02u; + enResult = Ok; + break; + case FlashPCInt: + FLASH_BYPASS(); + M0P_FLASH->CR_f.IE &= ~0x01u; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH åˆå§‹åŒ–函数——中断æœåŠ¡ç¨‹åºã€ç¼–程时间é…ç½®åŠä½ŽåŠŸè€—æ¨¡å¼ + ** + ** 该函数用于é…置中断æœåŠ¡å‡½æ•°ã€ä½ŽåŠŸè€—模å¼ã€æ ¹æ®ç³»ç»Ÿæ—¶é’Ÿé…ç½®FLASH编程时间相关寄存器. + ** + ** \param [in] pfnFlashCb Flash中断æœåŠ¡å›žè°ƒå‡½æ•°[void function(void)] + ** \param [in] u8FreqCfg FLASH编程时钟频率é…ç½®(æ ¹æ®HCLK的频率选择é…置值)： + ** 1 - (0,4]MHz; + ** 2 - (4,8]MHz; + ** 4 - (8,16]MHz; + ** 6 - (16,24]MHz; + ** 8 - (24,32]MHz（该é…置会设置æ’å…¥1个FLASH等待周期）; + ** 12 - (32,48]MHz（该é…置会设置æ’å…¥1个FLASH等待周期）; + ** other - 无效值 + ** \param [in] bDpstbEn TRUE - 当系统进入DeepSleep模å¼ï¼ŒFLASH进入低功耗模å¼; + ** FALSE - 当系统进入DeepSleep模å¼ï¼ŒFLASHä¸è¿›å…¥ä½ŽåŠŸè€—模å¼; + ** + ** \retval Ok æ“作æˆåŠŸ. + ** \retval ErrorInvalidParameter å‚数无效. + ** + *****************************************************************************/ +en_result_t Flash_Init(func_ptr_t pfnFlashCb, uint8_t u8FreqCfg, boolean_t bDpstbEn) +{ + en_result_t enResult = Ok; + + if ((1 != u8FreqCfg) && + (2 != u8FreqCfg) && + (4 != u8FreqCfg) && + (6 != u8FreqCfg) && + (8 != u8FreqCfg) && + (12 != u8FreqCfg)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //当系统进入DeepSleep模å¼æ—¶ï¼ŒFLASH模å¼é…ç½® + FLASH_BYPASS(); + M0P_FLASH->CR_f.DPSTB_EN = bDpstbEn; + + //flash时间å‚数寄存器é…ç½® + FLASH_BYPASS(); + M0P_FLASH->TNVS_f.TNVS = Tnvs * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TPGS_f.TPGS = Tpgs * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TPROG_f.TPROG = Tprog * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TSERASE_f.TSERASE = Tserase * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TMERASE_f.TMERASE = Tmerase * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TPRCV_f.TPRCV = Tprcv * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TSRCV_f.TSRCV = Tsrcv * u8FreqCfg; + FLASH_BYPASS(); + M0P_FLASH->TMRCV_f.TMRCV = Tmrcv * u8FreqCfg; + + //å¼€å¯è¯»FLASH等待周期 + if (8 == u8FreqCfg) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = 0x01; + } + else if(12 == u8FreqCfg) + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = 0x01; + } + else + { + FLASH_BYPASS(); + M0P_FLASH->CR_f.WAIT = 0x00; + } + + pfnFlashCallback = pfnFlashCb; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 字节写 + ** + ** 用于å‘FLASH写入1字节数æ®. + ** + ** \param [in] u32Addr Flashåœ°å€ + ** \param [in] u8Data 1å­—èŠ‚æ•°æ® + ** + ** \retval Ok 写入æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_WriteByte(uint32_t u32Addr, uint8_t u8Data) +{ + en_result_t enResult = Ok; + + if (FLASH_END_ADDR < u32Addr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + + //write data + *((volatile uint8_t*)u32Addr) = u8Data; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH åŠå­—写 + ** + ** 用于å‘FLASH写入åŠå­—（2字节）数æ®. + ** + ** \param [in] u32Addr Flashåœ°å€ + ** \param [in] u16Data åŠå­—（2å­—èŠ‚ï¼‰æ•°æ® + ** + ** \retval Ok 写入æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_WriteHalfWord(uint32_t u32Addr, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if ((FLASH_END_ADDR < u32Addr) || (u32Addr % 2)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + + //write data + *((volatile uint16_t*)u32Addr) = u16Data; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 字写 + ** + ** 用于å‘FLASH写入1个字的数æ®. + ** + ** \param [in] u32Addr Flashåœ°å€ + ** \param [in] u32Data 1ä¸ªå­—æ•°æ® + ** + ** \retval Ok 写入æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_WriteWord(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enResult = Ok; + + if ((FLASH_END_ADDR < u32Addr) || (u32Addr % 4)) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = Program; + + //write data + *((volatile uint32_t*)u32Addr) = u32Data; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 扇区擦除 + ** + ** FLASH 扇区擦除. + ** + ** \param [in] u32SectorAddr æ‰€æ“¦é™¤æ‰‡åŒºå†…çš„åœ°å€ + ** + ** \retval Ok 擦除æˆåŠŸ. + ** \retval ErrorInvalidParameter FLASH地å€æ— æ•ˆ + *****************************************************************************/ +en_result_t Flash_SectorErase(uint32_t u32SectorAddr) +{ + + en_result_t enResult = Ok; + + if (FLASH_END_ADDR < u32SectorAddr) + { + enResult = ErrorInvalidParameter; + return (enResult); + } + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = SectorErase; + + //write data + *((volatile uint8_t*)u32SectorAddr) = 0; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 全片擦除 + ** + ** FLASH 全片擦除. + ** + ** + ** \retval Ok 擦除æˆåŠŸ. + ** + *****************************************************************************/ +en_result_t Flash_ChipErase(void) +{ + + en_result_t enResult = Ok; + + //unlock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = (uint32_t)UnlockAll; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //set OP + FLASH_BYPASS(); + M0P_FLASH->CR_f.OP = ChipErase; + + //write data + *((volatile uint8_t*)0) = 0; + + //busy? + while (TRUE == M0P_FLASH->CR_f.BUSY) + { + ; + } + + //lock flash + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK = LockAll; + + return (enResult); +} + +/** + ***************************************************************************** + ** \brief FLASH 编程ä¿æŠ¤åŠ é” + ** + ** \param [in] enFlashSector 加é”范围选择枚举 + ** + ** \retval Ok 加é”æˆåŠŸ + ** \retval ErrorInvalidParameter å‚数错误 + *****************************************************************************/ +en_result_t Flash_Lock(en_flash_sector_lock_t enFlashSector) +{ + en_result_t enResult = Ok; + + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK |= (uint32_t)enFlashSector; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH 编程ä¿æŠ¤è§£é” + ** + ** \param [in] enFlashSector 解é”范围选择枚举 + ** + ** \retval Ok 解é”æˆåŠŸ + ** \retval ErrorInvalidParameter å‚数错误 + *****************************************************************************/ +en_result_t Flash_Unlock(en_flash_sector_lock_t enFlashSector) +{ + en_result_t enResult = Ok; + + FLASH_BYPASS(); + M0P_FLASH->SLOCK_f.SLOCK &= ~(uint32_t)enFlashSector; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief FLASH 读等待周期设置 + ** + ** \param [in] enWaitCycle æ’å…¥FLASH读等待周期数枚举类型 + ** + ** \retval Ok 解é”æˆåŠŸ + ** \retval ErrorInvalidParameter å‚数错误 + *****************************************************************************/ +en_result_t Flash_WaitCycle(en_flash_waitcycle_t enWaitCycle) +{ + en_result_t enResult = Ok; + + //æ’å…¥FLASH读等待周期 + M0P_SYSCTRL->PERI_CLKEN_f.FLASH = 1; + M0P_FLASH->BYPASS_f.BYSEQ = 0x5A5A; + M0P_FLASH->BYPASS_f.BYSEQ = 0xA5A5; + if (0 == enWaitCycle) + { + M0P_FLASH->CR_f.WAIT = 0; + } + else if(1 == enWaitCycle) + { + M0P_FLASH->CR_f.WAIT = 1; + } + else + { + M0P_FLASH->CR_f.WAIT = 2; + } + + return enResult; +} + + +//@} // FlashGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/gpio.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/gpio.c new file mode 100644 index 0000000000..9e8c3690f9 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/gpio.c @@ -0,0 +1,613 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file Gpio.c + ** + ** GPIO driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-22 1.0 Lux First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "gpio.h" + +/** + ******************************************************************************* + ** \addtogroup GpioGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_PIN(port,pin) ( ) +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief GPIO åˆå§‹åŒ– + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] pstcGpioCfg IO é…置结构体指针 + ** + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_Init(en_gpio_port_t enPort, en_gpio_pin_t enPin, stc_gpio_config_t *pstcGpioCfg) +{ + //é…置为默认值,GPIO功能 + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = GpioAf0; + + //æ–¹å‘é…ç½® + if(GpioDirIn == pstcGpioCfg->enDir) + { + setBit(((uint32_t)&M0P_GPIO->PADIR + enPort), enPin, TRUE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PADIR + enPort), enPin, FALSE); + } + + //驱动能力é…ç½® + if(GpioDrvH == pstcGpioCfg->enDrv) + { + setBit(((uint32_t)&M0P_GPIO->PADR + enPort), enPin, FALSE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PADR + enPort), enPin, TRUE); + } + + //上拉下拉é…ç½® + if(GpioPu == pstcGpioCfg->enPuPd) + { + setBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, TRUE); + setBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, FALSE); + } + else if(GpioPd == pstcGpioCfg->enPuPd) + { + setBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, FALSE); + setBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, TRUE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PAPU + enPort), enPin, FALSE); + setBit(((uint32_t)&M0P_GPIO->PAPD + enPort), enPin, FALSE); + } + + //å¼€æ¼è¾“出功能 + if(GpioOdDisable == pstcGpioCfg->enOD) + { + setBit(((uint32_t)&M0P_GPIO->PAOD + enPort), enPin, FALSE); + } + else + { + setBit(((uint32_t)&M0P_GPIO->PAOD + enPort), enPin, TRUE); + } + + M0P_GPIO->CTRL2_f.AHB_SEL = pstcGpioCfg->enCtrlMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IOè¾“å…¥å€¼èŽ·å– + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval boolean_t IO电平高低 + ******************************************************************************/ +boolean_t Gpio_GetInputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return getBit(((uint32_t)&M0P_GPIO->PAIN + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port输入数æ®èŽ·å– + ** + ** \param [in] enPort IO Port + ** + ** \retval boolean_t IO Portæ•°æ® + ******************************************************************************/ +uint16_t Gpio_GetInputData(en_gpio_port_t enPort) +{ + return (uint16_t)(*((uint32_t *)((uint32_t)&M0P_GPIO->PAIN + enPort))); +} + +/** + ******************************************************************************* + ** \brief GPIO IO输出值写入 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [out] bVal 输出值 + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_WriteOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin, boolean_t bVal) +{ + setBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin, bVal); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IOè¾“å‡ºå€¼èŽ·å– + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval boolean_t IO电平高低 + ******************************************************************************/ +boolean_t Gpio_ReadOutputIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return getBit(((uint32_t)&M0P_GPIO->PAOUT + enPort), enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port设置，å¯åŒæ—¶è®¾ç½®ä¸€ç»„Port中的多个PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 该Portçš„16个PIN掩ç å€¼,将需è¦è®¾ç½®çš„PIN对应的bit写1有效 + ** + ** \retval boolean_t IO Portæ•°æ® + ******************************************************************************/ +en_result_t Gpio_SetPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABSET)) + enPort)) = u16ValMsk; + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO设置 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit(((uint32_t)&M0P_GPIO->PABSET + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Port清零，å¯åŒæ—¶æ¸…零一组Port中的多个PIN + ** + ** \param [in] enPort IO Port + ** \param [in] u16ValMsk 该Portçš„16个PIN掩ç å€¼,将需è¦æ¸…零的PIN对应的bit写1有效 + ** + ** \retval boolean_t IO Portæ•°æ® + ******************************************************************************/ +en_result_t Gpio_ClrPort(en_gpio_port_t enPort, uint16_t u16ValMsk) +{ + *((uint16_t*)(((uint32_t)&(M0P_GPIO->PABCLR)) + enPort)) = u16ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO清零 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_ClrIO(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit(((uint32_t)&M0P_GPIO->PABCLR + enPort), enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO Portç½®ä½/清零，å¯åŒæ—¶ç½®ä½/清零一组Port中的多个PIN + ** + ** \param [in] enPort IO Port +** \param [in] u32ValMsk 高16bits表示该Portçš„16个PINç½®ä½æŽ©ç å€¼, + ** 低16bits表示该Portçš„16个PIN清零掩ç å€¼, +** 将需è¦è®¾ç½®çš„PIN对应的bit写1,åŒä¸€ä¸ªPIN的掩ç åŒæ—¶ä¸º1,则该PIN清零。 + ** + ** \retval en_result_t Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetClrPort(en_gpio_port_t enPort, uint32_t u32ValMsk) +{ + *((uint32_t*)(((uint32_t)&(M0P_GPIO->PABSETCLR)) + enPort)) = u32ValMsk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IOé…ç½®ä¸ºæ¨¡æ‹ŸåŠŸèƒ½æ¨¡å¼ + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetAnalogMode(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit((uint32_t)&M0P_GPIO->PAADS + enPort, enPin, TRUE); + + return Ok; +} + +/** + ******************************************************************************* +** \brief GPIO IOå¤ç”¨åŠŸèƒ½è®¾ç½® + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] enAf å¤ç”¨åŠŸèƒ½æžšä¸¾ç±»åž‹é€‰æ‹© + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +en_result_t Gpio_SetAfMode(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_af_t enAf) +{ + *((uint32_t*)(((uint32_t)(&(M0P_GPIO->PA00_SEL)) + enPort) + (((uint32_t)enPin)<<2))) = enAf; + + return Ok; +} + + +static en_result_t _GpioEnableIrq(en_gpio_port_t enPort, + en_gpio_pin_t enPin, + en_gpio_irqtype_t enType, + boolean_t bEnable) +{ + //high level + if (enType & GpioIrqHigh) + { + setBit((uint32_t)&M0P_GPIO->PAHIE + enPort, enPin, bEnable); + } + //low level + if (enType & GpioIrqLow) + { + setBit((uint32_t)&M0P_GPIO->PALIE + enPort, enPin, bEnable); + } + //rising + if (enType & GpioIrqRising) + { + setBit((uint32_t)&M0P_GPIO->PARIE + enPort, enPin, bEnable); + } + //falling + if (enType & GpioIrqFalling) + { + setBit((uint32_t)&M0P_GPIO->PAFIE + enPort, enPin, bEnable); + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO中断使能 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] enType 中断使能类型 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_EnableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + _GpioEnableIrq(enPort, enPin, enType, TRUE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO IO中断关闭 + ** + ** \param [in] enPort IO Portå£ + ** \param [in] enPin IO Pinè„š + ** \param [in] enType 中断使能类型 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_DisableIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin, en_gpio_irqtype_t enType) +{ + _GpioEnableIrq(enPort, enPin, enType, FALSE); + + return Ok; +} + + +/** + ******************************************************************************* + ** \brief GPIO 获得IOä¸­æ–­çŠ¶æ€ + ** + ** \param [in] u8Port IO Portå£ + ** \param [in] u8Pin IO Pinè„š + ** + ** \retval IO中断状æ€å¼€å…³ + ******************************************************************************/ +boolean_t Gpio_GetIrqStatus(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + return getBit((uint32_t)&M0P_GPIO->PA_STAT + enPort, enPin); +} + +/** + ******************************************************************************* + ** \brief GPIO 清除IOä¸­æ–­çŠ¶æ€ + ** + ** \param [in] u8Port IO Portå£ + ** \param [in] u8Pin IO Pinè„š + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_ClearIrq(en_gpio_port_t enPort, en_gpio_pin_t enPin) +{ + setBit((uint32_t)&M0P_GPIO->PA_ICLR + enPort, enPin, FALSE); + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——中断模å¼é…ç½® + ** + ** \param [in] enIrqMode 端å£ä¸­æ–­æ¨¡å¼ï¼ˆæ·±åº¦ä¼‘眠是å¦å“应中断） + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfIrqModeConfig(en_gpio_sf_irqmode_t enIrqMode) +{ + M0P_GPIO->CTRL0_f.IESEL = enIrqMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——IR输出æžæ€§é…ç½® + ** + ** \param [in] enIrPolMode IR输出æžæ€§é…置枚举 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfIrPolConfig(en_gpio_sf_irpol_t enIrPolMode) +{ + M0P_GPIO->CTRL1_f.IR_POL = enIrPolMode; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——HCLK输出é…ç½® + ** + ** \param [in] enGate HCLK输出使能 + ** \param [in] enDiv 输出分频枚举值 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfHClkOutputConfig(en_gpio_sf_hclkout_g_t enGate, en_gpio_sf_hclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.HCLK_EN = enGate; + M0P_GPIO->CTRL1_f.HCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——PCLK输出é…ç½® + ** + ** \param [in] enGate PCLK输出使能 + ** \param [in] enDiv 输出分频枚举值 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfPClkOutputConfig(en_gpio_sf_pclkout_g_t enGate, en_gpio_sf_pclkout_div_t enDiv) +{ + M0P_GPIO->CTRL1_f.PCLK_EN = enGate; + M0P_GPIO->CTRL1_f.PCLK_SEL = enDiv; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——外部时钟输入æ¥æºé…ç½® + ** + ** \param [in] enExtClk 外部时钟信å·æ¥æºé€‰æ‹©æžšä¸¾ + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfExtClkConfig(en_gpio_sf_ssn_extclk_t enExtClk) +{ + M0P_GPIO->CTRL1_f.EXT_CLK_SEL = enExtClk; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——SSN 通é“ä¿¡å·æ¥æºé…ç½® + ** + ** \param [in] enSpi SSN SPI通é“选择枚举 + ** \param [in] enSsn SSN ä¿¡å·æ¥æºé€‰æ‹©æžšä¸¾ + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfSsnConfig(en_gpio_sf_ssnspi_t enSpi, en_gpio_sf_ssn_extclk_t enSsn) +{ + //SPI0 + if(enSpi == GpioSpi0) + { + M0P_GPIO->CTRL1_f.SSN0_SEL = enSsn; + } + //SPI1 + if(enSpi == GpioSpi1) + { + M0P_GPIO->CTRL2_f.SSN1_SEL = enSsn; + } + + return Ok; +} + +/** + ******************************************************************************* + ** \brief GPIO 端å£è¾…助功能é…置——Timer 门控输入é…ç½® + ** + ** \param [in] enTimG Timer类型选择枚举 + ** \param [in] enSf Timer互è”功能选择枚举 + ** + ** \retval Ok 设置æˆåŠŸ + ******************************************************************************/ +en_result_t Gpio_SfTimGConfig(en_gpio_sf_tim_g_t enTimG, en_gpio_sf_t enSf) +{ + M0P_GPIO->TIMGS &= (uint32_t)(~(0x07U<TIMGS |= (uint32_t)(enSf<TIMES &= (uint32_t)(~(0x07U<TIMES |= (uint32_t)(enSf<TIMCPS &= (uint32_t)(~(0x07u<TIMCPS |= (uint32_t)(enSf<PCAS_f.PCA_CH0 = enSf; + } + + if(GpioSfPcaECI == enPca) + { + M0P_GPIO->PCAS_f.PCA_ECI = enSf; + } + + return Ok; +} + + +//@} // GpioGroup + + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/hdiv.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/hdiv.c new file mode 100644 index 0000000000..825058189d --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/hdiv.c @@ -0,0 +1,176 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file crc.c +** +** Common API of crc. +** @link crcGroup Some description @endlink +** +** - 2017-05-16 +** +******************************************************************************/ + +/******************************************************************************* +* Include files +******************************************************************************/ +#include "ddl.h" +#include "hdiv.h" +/** +******************************************************************************* +** \addtogroup CrcGroup +******************************************************************************/ +//@{ + +/******************************************************************************* +* Local pre-processor symbols/macros ('#define') +******************************************************************************/ + +/******************************************************************************* +* Global variable definitions (declared in header file with 'extern') +******************************************************************************/ + +/******************************************************************************* +* Local type definitions ('typedef') +******************************************************************************/ + +/******************************************************************************* +* Local variable definitions ('static') +******************************************************************************/ + +/******************************************************************************* +* Local function prototypes ('static') +******************************************************************************/ + + +/******************************************************************************* +* Function implementation - global ('extern') and local ('static') +******************************************************************************/ +/** +* \brief +* HDIV 有符å·é™¤æ³• +* +* \param [in] Dividend 被除数 +* \param [in] Dividsor 除数 +* \param [out] stcDivResult 商和余数 +* +* \retval en_result_t Ok: é…ç½®æˆåŠŸ +* \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° +*/ +en_result_t Hdiv_Unsigned(uint32_t Dividend,uint16_t Divisor,stc_div_unsigned_result_t* stcDivResult) +{ + M0P_HDIV->SIGN_f.SIGN = 0; + if(NULL == stcDivResult) + { + return ErrorInvalidParameter; + } + (M0P_HDIV ->DIVIDEND) = Dividend; + (M0P_HDIV ->DIVISOR) = Divisor; + + if(Hdiv_GetZeroState() == TRUE) + { + return ErrorInvalidParameter; + } + + while(Hdiv_GetEndState() != TRUE) + { + ; + } + + stcDivResult->Quotient = M0P_HDIV->QUOTIENT_f.QUOTIENT; + stcDivResult->Remainder = M0P_HDIV ->REMAINDER_f.REMAINDER; + return Ok; +} + + +/** +* \brief +* HDIV 无符å·é™¤æ³• +* +* \param [in] Dividend 被除数 +* \param [in] Dividsor 除数 +* \param [out] stcDivResult 商和余数 +* +* \retval en_result_t Ok: é…ç½®æˆåŠŸ +* \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° +*/ +en_result_t Hdiv_Signed(int32_t Dividend,int16_t Divisor,stc_div_signed_result_t* stcDivResult) +{ + + __IO uint32_t * pDivdend = &(M0P_HDIV ->DIVIDEND); + __IO uint32_t * pDivsor = &(M0P_HDIV ->DIVISOR); + if(NULL == stcDivResult) + { + return ErrorInvalidParameter; + } + M0P_HDIV->SIGN_f.SIGN = 1; + *(__IO int32_t *)pDivdend = Dividend; + *(__IO int16_t *)pDivsor = Divisor; + + if(Hdiv_GetZeroState() == TRUE) + { + return ErrorInvalidParameter; + } + + while(Hdiv_GetEndState() != TRUE) + { + ; + } + + stcDivResult->Quotient = M0P_HDIV->QUOTIENT_f.QUOTIENT; + stcDivResult->Remainder = M0P_HDIV ->REMAINDER_f.REMAINDER; + return Ok; +} + +boolean_t Hdiv_GetEndState(void) +{ + return M0P_HDIV->STAT_f.END; +} + +boolean_t Hdiv_GetZeroState(void) +{ + return M0P_HDIV->STAT_f.ZERO; +} +//@} // CrcGroup + +/******************************************************************************* +* EOF (not truncated) +******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/i2c.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/i2c.c new file mode 100644 index 0000000000..85a13463b6 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/i2c.c @@ -0,0 +1,666 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file I2C.c + ** + ** WDT function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-03-13 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "i2c.h" + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static func_ptr_t pfnI2c0tCallback = NULL; +static func_ptr_t pfnI2c1tCallback = NULL; +/** + ****************************************************************************** + ** \brief I2C设置波特率é…置寄存器 + ** + ** \param [in] u8Tm 波特率é…置值 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t I2C_SetBaud(en_i2c_channel_t enCh,uint8_t u8Tm) + { + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->TM = u8Tm; + } + else + { + M0P_I2C1->TM = u8Tm; + } + + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C功能设置相关函数 + ** + ** \param [in] enFunc功能å‚æ•° + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t I2C_SetFunc(en_i2c_channel_t enCh,en_i2c_func_t enFunc) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C0->CR_f.ENS = 1; + break; + case I2cStart_En: + M0P_I2C0->CR_f.STA = 1; + break; + case I2cStop_En: + M0P_I2C0->CR_f.STO = 1; + break; + case I2cAck_En: + M0P_I2C0->CR_f.AA = 1; + break; + case I2cHlm_En: + M0P_I2C0->CR_f.H1M = 1; + break; + case I2cBaud_En: + M0P_I2C0->TMRUN = 0x01; + break; + default: + return ErrorInvalidParameter; + } + } + else + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C1->CR_f.ENS = 1; + break; + case I2cStart_En: + M0P_I2C1->CR_f.STA = 1; + break; + case I2cStop_En: + M0P_I2C1->CR_f.STO = 1; + break; + case I2cAck_En: + M0P_I2C1->CR_f.AA = 1; + break; + case I2cHlm_En: + M0P_I2C1->CR_f.H1M = 1; + break; + case I2cBaud_En: + M0P_I2C1->TMRUN = 0x01; + break; + default: + return ErrorInvalidParameter; + } + } + + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C功能清除相关函数 + ** + ** \param [in] enFunc功能å‚æ•° + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t I2C_ClearFunc(en_i2c_channel_t enCh,en_i2c_func_t enFunc) + { + en_result_t enRet = Error; + if(I2C0 == enCh) + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C0->CR_f.ENS = 0; + break; + case I2cStart_En: + M0P_I2C0->CR_f.STA = 0; + break; + case I2cStop_En: + M0P_I2C0->CR_f.STO = 0; + break; + case I2cAck_En: + M0P_I2C0->CR_f.AA = 0; + break; + case I2cHlm_En: + M0P_I2C0->CR_f.H1M = 0; + break; + case I2cBaud_En: + M0P_I2C0->TMRUN = 0x00; + break; + default: + return ErrorInvalidParameter; + } + } + else + { + switch(enFunc) + { + case I2cMode_En: + M0P_I2C1->CR_f.ENS = 0; + break; + case I2cStart_En: + M0P_I2C1->CR_f.STA = 0; + break; + case I2cStop_En: + M0P_I2C1->CR_f.STO = 0; + break; + case I2cAck_En: + M0P_I2C1->CR_f.AA = 0; + break; + case I2cHlm_En: + M0P_I2C1->CR_f.H1M = 0; + break; + case I2cBaud_En: + M0P_I2C1->TMRUN = 0x00; + break; + default: + return ErrorInvalidParameter; + } + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C获å–中断标记函数 + ** + ** \param æ—  + ** + ** \retval bIrq中断标记 + ** + ******************************************************************************/ +boolean_t I2C_GetIrq(en_i2c_channel_t enCh) +{ + boolean_t bIrq = FALSE; + if(I2C0 == enCh) + { + bIrq = M0P_I2C0->CR_f.SI; + } + else + { + bIrq = M0P_I2C1->CR_f.SI; + } + + return bIrq; +} +/** + ****************************************************************************** + ** \brief I2C清除中断标记函数 + ** + ** \param æ—  + ** + ** \retval bIrq中断标记 + ** + ******************************************************************************/ +en_result_t I2C_ClearIrq(en_i2c_channel_t enCh) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->CR_f.SI = 0; + } + else + { + M0P_I2C1->CR_f.SI = 0; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief I2C获å–ç›¸å…³çŠ¶æ€ + ** + ** \param æ—  + ** + ** \retval I2CçŠ¶æ€ + ** + ******************************************************************************/ +uint8_t I2C_GetState(en_i2c_channel_t enCh) +{ + uint8_t u8State = 0; + if(I2C0 == enCh) + { + u8State = M0P_I2C0->STAT; + } + else + { + u8State = M0P_I2C1->STAT; + } + return u8State; +} +/** + ****************************************************************************** + ** \brief I2C写从机地å€å‡½æ•° + ** + ** \param u8SlaveAddrä»Žæœºåœ°å€ + ** + ** \retval I2C写æˆåŠŸä¸Žå¦çŠ¶æ€ + ** + ******************************************************************************/ + en_result_t I2C_WriteSlaveAddr(en_i2c_channel_t enCh,stc_i2c_addr_t *pstcSlaveAddr) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->ADDR_f.ADR = pstcSlaveAddr->Addr; + M0P_I2C0->ADDR_f.GC = pstcSlaveAddr->Gc; + } + else + { + M0P_I2C1->ADDR_f.ADR = pstcSlaveAddr->Addr; + M0P_I2C1->ADDR_f.GC = pstcSlaveAddr->Gc; + } + + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief 字节写从机函数 + ** + ** \param u8Dataå†™æ•°æ® + ** + ** \retval 写数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_WriteByte(en_i2c_channel_t enCh,uint8_t u8Data) +{ + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->DATA = u8Data; + } + else + { + M0P_I2C1->DATA = u8Data; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief 字节读从机函数 + ** + ** \param æ—  + ** + ** \retval 读å–æ•°æ® + ** + ******************************************************************************/ +uint8_t I2C_ReadByte(en_i2c_channel_t enCh) +{ + uint8_t u8Data = 0; + if(I2C0 == enCh) + { + u8Data = M0P_I2C0->DATA; + } + else + { + u8Data = M0P_I2C1->DATA; + } + return u8Data; +} + /** + ****************************************************************************** + ** \brief 主机å‘é€å‡½æ•° + ** + ** \param u8Addr从机内存地å€ï¼Œpu8Data写数æ®ï¼Œu32Len写数æ®é•¿åº¦ + ** + ** \retval 写数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_MasterWriteData(en_i2c_channel_t enCh,uint8_t u8DevAddr,uint8_t u8Addr,uint8_t *pu8Data,uint32_t u32Len) +{ + en_result_t enRet = Error; + uint8_t u8i=0,u8State; + + I2C_SetFunc(enCh,I2cStart_En); + while(1) + { + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0x08: + I2C_ClearFunc(enCh,I2cStart_En); + I2C_WriteByte(enCh,u8DevAddr);//从设备地å€å‘é€ + break; + case 0x18: + I2C_WriteByte(enCh,u8Addr);//从设备内存地å€å‘é€ + break; + case 0x28: + I2C_WriteByte(enCh,pu8Data[u8i++]); + break; + case 0x20: + case 0x38: + I2C_SetFunc(enCh,I2cStart_En); + break; + case 0x30: + I2C_SetFunc(enCh,I2cStop_En); + break; + default: + break; + } + if(u8i>u32Len) + { + I2C_SetFunc(enCh,I2cStop_En);//此顺åºä¸èƒ½è°ƒæ¢ï¼Œå‡ºåœæ­¢æ¡ä»¶ + I2C_ClearIrq(enCh); + break; + } + I2C_ClearIrq(enCh); + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief 从机å‘é€å‡½æ•° + ** + ** \param pu8Dataå‘é€æ•°æ®ç¼“存，u32Lenå‘é€æ•°æ®é•¿åº¦ + ** + ** \retval å‘é€æ•°æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ + en_result_t I2C_SlaveWriteData(en_i2c_channel_t enCh,uint8_t *pu8Data,uint32_t *u32Len) + { + uint8_t u8i=0,u8State; + // + while(1) + { + + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0xA8: + case 0xB0: + I2C_WriteByte(enCh,pu8Data[u8i++]); + break; + case 0xB8: + case 0xC8: + I2C_WriteByte(enCh,pu8Data[u8i++]); + break; + case 0xF8: + *u32Len = u8i; + break; + default: + + return ErrorInvalidParameter; + } + I2C_ClearIrq(enCh); + } + } + /** + ****************************************************************************** + ** \brief 从机接收函数 + ** + ** \param pu8Data接收数æ®å­˜æ”¾ç¼“存，u32Len接收数æ®æŒ‡é’ˆ + ** + ** \retval 接收数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_SlaveReadData(en_i2c_channel_t enCh,uint8_t *pu8Data,uint32_t *pu32Len) +{ + uint8_t u8i=0,u8State; + while(0 == I2C_GetIrq(enCh)) + {} + while(1) + { + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0x60: + case 0x68: + case 0x70: + case 0x78: + break; + case 0x80: + case 0x90: + pu8Data[u8i++] = I2C_ReadByte(enCh); + break; + case 0xA0: + *pu32Len = u8i; + break; + default: + return ErrorInvalidParameter; + } + I2C_ClearIrq(enCh); + if(0xA0 == u8State) + { + return Ok; + } + } +} + +/** + ****************************************************************************** + ** \brief 主机接收函数 + ** + ** \param u8Addr从机内存地å€ï¼Œpu8Data读数æ®å­˜æ”¾ç¼“存，u32Len读数æ®é•¿åº¦ + ** + ** \retval 读数æ®æ˜¯å¦æˆåŠŸ + ** + ******************************************************************************/ + en_result_t I2C_MasterReadData(en_i2c_channel_t enCh,uint8_t u8DevAddr,uint8_t *pu8Data,uint8_t u8Addr,uint32_t u32Len) +{ + en_result_t enRet = Error; + uint8_t u8i=0,u8State; + + I2C_SetFunc(enCh,I2cStart_En); + + while(1) + { + while(0 == I2C_GetIrq(enCh)) + {} + u8State = I2C_GetState(enCh); + switch(u8State) + { + case 0x08: + I2C_ClearFunc(enCh,I2cStart_En); + I2C_WriteByte(enCh,u8DevAddr); + break; + case 0x18: + I2C_WriteByte(enCh,u8Addr); + break; + case 0x28: + I2C_SetFunc(enCh,I2cStart_En); + break; + case 0x10: + I2C_ClearFunc(enCh,I2cStart_En); + I2C_WriteByte(enCh,u8DevAddr|0x01);//从机地å€å‘é€OK + break; + case 0x40: + if(u32Len>1) + { + I2C_SetFunc(enCh,I2cAck_En); + } + break; + case 0x50: + pu8Data[u8i++] = I2C_ReadByte(enCh); + if(u8i==u32Len-1) + { + I2C_ClearFunc(enCh,I2cAck_En); + } + break; + case 0x58: + pu8Data[u8i++] = I2C_ReadByte(enCh); + I2C_SetFunc(enCh,I2cStop_En); + break; + case 0x38: + I2C_SetFunc(enCh,I2cStart_En); + break; + case 0x48: + I2C_SetFunc(enCh,I2cStop_En); + I2C_SetFunc(enCh,I2cStart_En); + break; + default: + I2C_SetFunc(enCh,I2cStart_En);//其他错误状æ€ï¼Œé‡æ–°å‘é€èµ·å§‹æ¡ä»¶ + break; + } + I2C_ClearIrq(enCh); + if(u8i==u32Len) + { + break; + } + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief I2C模å—åˆå§‹åŒ– + ** + ** \param pstcI2CCfgåˆå§‹åŒ–é…置结构体 + ** + ** \retval åˆå§‹åŒ–是å¦æˆåŠŸ + ** + ******************************************************************************/ +en_result_t I2C_Init(en_i2c_channel_t enCh,stc_i2c_config_t *pstcI2CCfg) +{ + en_result_t enRet = Error; + enRet = I2C_SetFunc(enCh,pstcI2CCfg->enFunc); + enRet = I2C_SetBaud(enCh,pstcI2CCfg->u8Tm); + enRet = I2C_WriteSlaveAddr(enCh,&pstcI2CCfg->stcSlaveAddr); + if(pstcI2CCfg->u8Tm<9) + { + I2C_SetFunc(enCh,I2cHlm_En); + } + if(NULL!=pstcI2CCfg->pfnI2c0Cb) + { + pfnI2c0tCallback = pstcI2CCfg->pfnI2c0Cb; + } + if(NULL!=pstcI2CCfg->pfnI2c1Cb) + { + pfnI2c1tCallback = pstcI2CCfg->pfnI2c1Cb; + } + if(TRUE == pstcI2CCfg->bTouchNvic) + { + if(I2C0 == enCh) + { + EnableNvic(I2C0_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(I2C1_IRQn,IrqLevel3,TRUE); + } + } + return enRet; +} +/** + ****************************************************************************** + ** \brief I2C模å—关闭åˆå§‹åŒ– + ** + ** \param æ—  + ** + ** \retval 设置是å¦æˆåŠŸ + ** + ******************************************************************************/ + en_result_t I2C_DeInit(en_i2c_channel_t enCh) + { + en_result_t enRet = Error; + if(I2C0 == enCh) + { + M0P_I2C0->CR = 0x00; + } + else + { + M0P_I2C1->CR = 0x00; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief I2C模å—中断处ç†å‡½æ•° + ** + ** \param u8Param æ— æ„义 + ** + ** \retval æ—  + ** + ******************************************************************************/ +void I2c_IRQHandler(uint8_t u8Param) +{ + if(I2C0 == u8Param) + { + if(NULL != pfnI2c0tCallback) + { + pfnI2c0tCallback(); + } + } + else + { + if(NULL != pfnI2c1tCallback) + { + pfnI2c1tCallback(); + } + } +} + +//@} // I2cGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/interrupts_hc32l136.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/interrupts_hc32l136.c new file mode 100644 index 0000000000..eb95c48ee1 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/interrupts_hc32l136.c @@ -0,0 +1,477 @@ +/****************************************************************************** +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file interrupts_hc32l136.c + ** + ** Interrupt management + ** @link Driver Group Some description @endlink + ** + ** - 2018-04-15 1.0 Lux First version. + ** + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ddl.h" +#include "interrupts_hc32l136.h" +__WEAKDEF void Gpio_IRQHandler(uint8_t u8Param); +__WEAKDEF void Dma_IRQHandler(uint8_t u8Param); +__WEAKDEF void Uart_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpUart_IRQHandler(uint8_t u8Param); +__WEAKDEF void Spi_IRQHandler(uint8_t u8Param); +__WEAKDEF void I2c_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Tim3_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adt_IRQHandler(uint8_t u8Param); +__WEAKDEF void LpTim_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pca_IRQHandler(uint8_t u8Param); +__WEAKDEF void Wdt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Vc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Rtc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Adc_IRQHandler(uint8_t u8Param); +__WEAKDEF void Pcnt_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lvd_IRQHandler(uint8_t u8Param); +__WEAKDEF void Lcd_IRQHandler(uint8_t u8Param); +__WEAKDEF void EfRam_IRQHandler(uint8_t u8Param); +__WEAKDEF void ClkTrim_IRQHandler(uint8_t u8Param); + +/** + ******************************************************************************* + ** \brief NVIC 中断使能 + ** + ** \param [in] enIrq 中断å·æžšä¸¾ç±»åž‹ + ** \param [in] enLevel 中断优先级枚举类型 + ** \param [in] bEn 中断开关 + ** \retval Ok 设置æˆåŠŸ + ** 其他值 设置失败 + ******************************************************************************/ +void EnableNvic(IRQn_Type enIrq, en_irq_level_t enLevel, boolean_t bEn) +{ + NVIC_ClearPendingIRQ(enIrq); + NVIC_SetPriority(enIrq, enLevel); + if (TRUE == bEn) + { + NVIC_EnableIRQ(enIrq); + } + else + { + NVIC_DisableIRQ(enIrq); + } +} + +/** + ******************************************************************************* + ** \brief NVIC hardware fault 中断实现 + ** 用于å•æ­¥è°ƒè¯•åŠŸèƒ½ + ** + ** \retval + ******************************************************************************/ +void HardFault_Handler(void) +{ + volatile int a = 0; + + while( 0 == a) + { + ; + } +} + +/** + ******************************************************************************* + ** \brief GPIO PortA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTA_IRQHandler(void) +{ + Gpio_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief GPIO PortB 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTB_IRQHandler(void) +{ + Gpio_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief GPIO PortC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTC_IRQHandler(void) +{ + Gpio_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief GPIO PortD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PORTD_IRQHandler(void) +{ + Gpio_IRQHandler(3); +} + +/** + ******************************************************************************* + ** \brief DMAC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void DMAC_IRQHandler(void) +{ + Dma_IRQHandler(0); +} + + +/** + ******************************************************************************* + ** \brief UART0 串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART0_IRQHandler(void) +{ + Uart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief UART1 串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void UART1_IRQHandler(void) +{ + Uart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief LPUART0 低功耗串å£0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART0_IRQHandler(void) +{ + LpUart_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPUART1 低功耗串å£1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPUART1_IRQHandler(void) +{ + LpUart_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief SPI0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI0_IRQHandler(void) +{ + Spi_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief SPI1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void SPI1_IRQHandler(void) +{ + Spi_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief I2C0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C0_IRQHandler(void) +{ + I2c_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief I2C1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void I2C1_IRQHandler(void) +{ + I2c_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM0 基础时钟0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM0_IRQHandler(void) +{ + Tim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM1 基础时钟1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM1_IRQHandler(void) +{ + Tim_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief TIM2 基础时钟2 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM2_IRQHandler(void) +{ + Tim_IRQHandler(2); +} + +/** + ******************************************************************************* + ** \brief TIM3 基础时钟3 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM3_IRQHandler(void) +{ + Tim3_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LPTIM 低功耗时钟 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LPTIM_IRQHandler(void) +{ + LpTim_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief TIM4 高级时钟4 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM4_IRQHandler(void) +{ + Adt_IRQHandler(4); +} + +/** + ******************************************************************************* + ** \brief TIM5 高级时钟5 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM5_IRQHandler(void) +{ + Adt_IRQHandler(5); +} + +/** + ******************************************************************************* + ** \brief TIM6 高级时钟6 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void TIM6_IRQHandler(void) +{ + Adt_IRQHandler(6); +} + +/** + ******************************************************************************* + ** \brief PCA 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCA_IRQHandler(void) +{ + Pca_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief WDT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void WDT_IRQHandler(void) +{ + Wdt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RTC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void RTC_IRQHandler(void) +{ + Rtc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief ADC 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void ADC_IRQHandler(void) +{ + Adc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief PCNT 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void PCNT_IRQHandler(void) +{ + Pcnt_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较0 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC0_IRQHandler(void) +{ + Vc_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 电压比较1 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void VC1_IRQHandler(void) +{ + Vc_IRQHandler(1); +} + +/** + ******************************************************************************* + ** \brief 低电压检测 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LVD_IRQHandler(void) +{ + Lvd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief LCD 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void LCD_IRQHandler(void) +{ + Lcd_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief RAM 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void EF_RAM_IRQHandler(void) +{ + EfRam_IRQHandler(0); +} + +/** + ******************************************************************************* + ** \brief 时钟校准 中断处ç†å‡½æ•° + ** + ** \retval + ******************************************************************************/ +void CLKTRIM_IRQHandler(void) +{ + ClkTrim_IRQHandler(0); +} + + + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lcd.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lcd.c new file mode 100644 index 0000000000..65206068d2 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lcd.c @@ -0,0 +1,579 @@ +/************************************************************************************* +* Copyright (C) 2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lcd.c + ** + ** WDT function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2018-5-3 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lcd.h" + +/** + ******************************************************************************* + ** \addtogroup I2cGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + en_result_t LCD_SetClkSrc(en_lcd_clk_t enLcdClk) + { + en_result_t enRet = Error; + M0P_LCD->CR1_f.CLKSRC = enLcdClk; + enRet = Ok; + return enRet; + } +/** + ****************************************************************************** + ** \brief LCD Biasæºé€‰æ‹©å‡½æ•° + ** + ** \param [in] enBiasSrcåç½®æºé€‰æ‹© + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SelBiasSrc(en_lcd_biassrc_t enBiasSrc) + { + en_result_t enRet = Error; + switch(enBiasSrc) + { + case LcdInRes_High: + case LcdInRes_Low: + case LcdInRes_Mid: + case LcdExtCap: + case LcdExtRes: + M0P_LCD->CR0_f.BSEL = enBiasSrc; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } +/** + ****************************************************************************** + ** \brief LCD å ç©ºæ¯”选择函数 + ** + ** \param [in] enDutyå ç©ºæ¯” + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_SetDuty(en_lcd_duty_t enDuty) +{ + en_result_t enRet = Error; + switch(enDuty) + { + case LcdStatic: + case LcdDuty2: + case LcdDuty3: + case LcdDuty4: + case LcdDuty6: + case LcdDuty8: + M0P_LCD->CR0_f.DUTY = enDuty; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LCD bias设置函数 + ** + ** \param [in] enBias　åç½® + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetBias(en_lcd_bias_t enBias) + { + en_result_t enRet = Error; + switch(enBias) + { + case LcdBias3: + case LcdBias2: + M0P_LCD->CR0_f.BIAS = enBias; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 电压泵时钟频率选择函数 + ** + ** \param [in] enCpClk 电压泵频率 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_SelCpClk(en_lcd_cpclk_t enCpClk) +{ + en_result_t enRet = Error; + switch(enCpClk) + { + case LcdClk2k: + case LcdClk4k: + case LcdClk8k: + case LcdClk16k: + M0P_LCD->CR0_f.CPCLK = enCpClk; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD 扫æ时钟频率选择函数 + ** + ** \param [in] enScanClk 扫æ时钟频率 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_SelScanClk(en_lcd_scanclk_t enScanClk) +{ + en_result_t enRet = Error; + switch(enScanClk) + { + case LcdClk64hz: + case LcdClk128hz: + case LcdClk256hz: + case LcdClk512hz: + M0P_LCD->CR0_f.LCDCLK = enScanClk; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD 模å—使能或闪å±ä½¿èƒ½ç¦æ­¢å‡½æ•° + ** + ** \param [in] enFunc功能，bFlag使能或ç¦æ­¢ + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_EnFunc(en_lcd_func_t enFunc,boolean_t bFlag) + { + en_result_t enRet = Error; + switch(enFunc) + { + case LcdEn: + M0P_LCD->CR0_f.EN = bFlag; + break; + case LcdBlinkEn: + M0P_LCD->CR1_f.BLINKEN = bFlag; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 显示模å¼0/1设置 + ** + ** \param [in] enDispModeæ¨¡å¼ + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetDispMode(en_lcd_dispmode_t enDispMode) + { + en_result_t enRet = Error; + switch(enDispMode) + { + case LcdMode0: + case LcdMode1: + M0P_LCD->CR1_f.MODE = enDispMode; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 对比度设置 + ** + ** \param [in] u8Contrast对比度 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetContrast(uint8_t u8Contrast) + { + en_result_t enRet = Error; + M0P_LCD->CR0_f.CONTRAST = u8Contrast; + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD é—ªå±è®¡æ•°å™¨è®¾ç½® + ** + ** \param [in] u8BlinkCnt计数器 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetBlinkCnt(uint8_t u8BlinkCnt) + { + en_result_t enRet = Error; + M0P_LCD->CR1_f.BLINKCNT = u8BlinkCnt; + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief LCD 中断标记清除 + ** + ** \param [in] æ—  + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_ClrIntState(void) +{ + en_result_t enRet = Error; + M0P_LCD->INTCLR_f.INTF = 0; + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief æ ¹æ®LCD显示模å¼èŽ·å–端å£é…ç½® + ** + ** \param [in]enLcdRunMode：显示方å¼ï¼Œ stcSegCom获å–端å£å‚æ•° + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_GetSegCom(stc_lcd_segcompara_t *pstcSegComPara,stc_lcd_segcom_t *pstcSegCom) +{ + en_result_t enRet = Error; + if(pstcSegComPara->u8MaxSeg>40) + { + return ErrorInvalidParameter; + } + switch(pstcSegComPara->enBiasSrc)//seg32_35 + { + case LcdInRes_High: + case LcdInRes_Low: + case LcdInRes_Mid: + pstcSegCom->bMux = 1; + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom = 0xff; + break; + case LcdExtCap: + case LcdExtRes: + //VLCD模拟端å£é…ç½® + if(pstcSegComPara->u8MaxSeg>36) + { + return ErrorInvalidParameter; + } + pstcSegCom->bMux = 0; + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom = 0x0f;//seg32_35ç½®0 + break; + default: + return ErrorInvalidParameter; + } + switch(pstcSegComPara->enDuty)//COM0_7 + { + case LcdStatic: + pstcSegCom->u8Com0_3 = 0xfe; + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty2: + pstcSegCom->u8Com0_3 = 0xfc;//COMå£é…置，默认按顺åºè¿›è¡Œé…ç½®com0/com1 + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty3: + pstcSegCom->u8Com0_3 = 0xf8;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty4: + pstcSegCom->u8Com0_3 = 0xf0;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xff; + break; + case LcdDuty6: + if(pstcSegComPara->u8MaxSeg>38) + { + return ErrorInvalidParameter; + } + pstcSegCom->u8Com0_3 = 0xf0;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xfc; + break; + case LcdDuty8: + if(pstcSegComPara->u8MaxSeg>36) + { + return ErrorInvalidParameter; + } + pstcSegCom->u8Com0_3 = 0xf0;//åªå–低4bit + pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom &= 0xf0; + break; + default: + return ErrorInvalidParameter; + } + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD COMSEG端å£é…ç½® + ** + ** \param [in] pstcSegCom端å£é…置结构体 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_SetSegCom(stc_lcd_segcom_t *pstcSegCom) + { + en_result_t enRet = Error; + M0P_LCD->POEN0 = pstcSegCom->u32Seg0_31; + M0P_LCD->POEN1 = (uint32_t)(pstcSegCom->Seg32_39VLcdCom7_4_t.SegVLcdCom); + M0P_LCD->POEN1_f.MUX = pstcSegCom->bMux; + M0P_LCD->POEN1_f.C0 = pstcSegCom->u8Com0_3&0x01; + M0P_LCD->POEN1_f.C1 = pstcSegCom->u8Com0_3&0x02; + M0P_LCD->POEN1_f.C2 = pstcSegCom->u8Com0_3&0x04; + M0P_LCD->POEN1_f.C3 = pstcSegCom->u8Com0_3&0x08; + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief 液晶全显 + ** + ** \param [in] æ—  + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_FullDisp(void) + { + en_result_t enRet=Error; + uint8_t i; + uint32_t volatile *p = NULL; + p = &M0P_LCD->RAM0; + for(i=0;i<8;i++) + { + *p = 0xffffffffu; + p++; + } + for(i=0;i<8;i++) + { + *p = 0xffu; + p++; + } + enRet = Ok; + return enRet; + } + /** + ****************************************************************************** + ** \brief 液晶全清 + ** + ** \param [in] æ—  + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_ClearDisp(void) +{ + en_result_t enRet=Error; + uint8_t i; + uint32_t volatile *p = NULL; + p = &M0P_LCD->RAM0; + for(i=0;i<16;i++) + { + *p = 0x00; + p++; + } + enRet = Ok; + return enRet; +} + /** + ****************************************************************************** + ** \brief LCD RAM bit设置函数 + ** + ** \param [in] u16Row RAM地å€ç´¢å¼•ï¼Œu32List bitä½ç´¢å¼•ï¼ŒbData写入0或1 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_WriteRam(uint16_t u16Row, uint32_t u32List, boolean_t bData) + { + en_result_t enRet = Error; + uint8_t RamListSize = 0; + volatile uint32_t *ptemp = NULL; + ptemp = (volatile uint32_t*)&M0P_LCD->RAM0; + if(u16Row>=8) + { + RamListSize = LCDRAM8_FSIZE; + } + else + { + RamListSize = LCDRAM0_7SIZE; + } + if ((u16Row > LCDRAMSIZE) || (u32List > RamListSize)) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ptemp += u16Row; + + if (bData == TRUE) + { + *ptemp |= (uint32_t)(1 << u32List); + } + else + { + *ptemp &= (uint32_t)(0 << u32List); + } + enRet = Ok; + return enRet; + } +/** + ****************************************************************************** + ** \brief LCD RAM 0-7寄存器设置函数 + ** + ** \param [in] u8Row RAM地å€ç´¢å¼•ï¼Œu32Data写入寄存器数值 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_WriteRam0_7Int32(uint8_t u8Row,uint32_t u32Data) +{ + en_result_t enRet = Error; + volatile uint32_t *ptemp = NULL; + ptemp = (volatile uint32_t*)&M0P_LCD->RAM0; + + if (u8Row > LCDRAMSIZE) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ptemp += u8Row; + *ptemp = u32Data; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LCD RAM 8-f寄存器设置函数 + ** + ** \param [in] u8Row RAM地å€ç´¢å¼•ï¼Œu8Data写入寄存器数值 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ +en_result_t LCD_WriteRam8_FInt8(uint8_t u8Row,uint8_t u8Data) +{ + en_result_t enRet = Error; + volatile uint32_t *ptemp = NULL; + ptemp = (volatile uint32_t*)&M0P_LCD->RAM0; + + if (u8Row > LCDRAMSIZE) + { + enRet = ErrorInvalidParameter; + return enRet; + } + + ptemp += u8Row; + *ptemp = u8Data; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LCD模å—åˆå§‹åŒ–函数 + ** + ** \param [in] stcLcdCfgé…置结构体 + ** + ** \retval enRet æˆåŠŸæˆ–失败 + ** + ******************************************************************************/ + en_result_t LCD_Init(stc_lcd_config_t *pstcLcdCfg) + { + en_result_t enRet = Error; + enRet = LCD_SelBiasSrc(pstcLcdCfg->enBiasSrc); + enRet = LCD_SetDuty(pstcLcdCfg->enDuty); + enRet = LCD_SetBias(pstcLcdCfg->enBias); + enRet = LCD_SelCpClk(pstcLcdCfg->enCpClk); + enRet = LCD_SelScanClk(pstcLcdCfg->enScanClk); + enRet = LCD_SetDispMode(pstcLcdCfg->enDispMode); + enRet = LCD_SetClkSrc(pstcLcdCfg->enClk); + if(Ok!=enRet) + { + return ErrorInvalidParameter; + } + if(pstcLcdCfg->bTouchNvic) + { + M0P_LCD->CR1_f.IE = 1; + EnableNvic(LCD_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(LCD_IRQn,IrqLevel3,FALSE); + } + return Ok; + } +//@} // LCDGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpm.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpm.c new file mode 100644 index 0000000000..dbba75a8e3 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpm.c @@ -0,0 +1,134 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file lpm.c + ** + ** Common API of lpm. + ** @link LpmGroup Some description @endlink + ** + ** - 2017-06-06 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "lpm.h" +/** + ******************************************************************************* + ** \addtogroup LpmGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#define IS_VALID_SEVONPEND(x) (SevPndDisable == (x) ||\ + SevPndEnable == (x)) +#define IS_VALID_SLEEPDEEP(x) (SlpDpDisable == (x) ||\ + SlpDpEnable == (x)) +#define IS_VALID_SLEEPONEXIT(x) (SlpExtDisable == (x) ||\ + SlpExtEnable == (x)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief 低功耗模å¼é…ç½® + ** + ** + ** \param [in] pstcConfig 低功耗模å¼é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpm_Config(stc_lpm_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_SEVONPEND(pstcConfig->enSEVONPEND)); + ASSERT(IS_VALID_SLEEPDEEP(pstcConfig->enSLEEPDEEP)); + ASSERT(IS_VALID_SLEEPONEXIT(pstcConfig->enSLEEPONEXIT)); + + SCB->SCR = pstcConfig->enSEVONPEND ? (SCB->SCR | SCB_SCR_SEVONPEND_Msk) : (SCB->SCR & ~SCB_SCR_SEVONPEND_Msk); + SCB->SCR = pstcConfig->enSLEEPDEEP ? (SCB->SCR | SCB_SCR_SLEEPDEEP_Msk) : (SCB->SCR & ~SCB_SCR_SLEEPDEEP_Msk); + SCB->SCR = pstcConfig->enSLEEPONEXIT ? (SCB->SCR | SCB_SCR_SLEEPONEXIT_Msk) : (SCB->SCR & ~SCB_SCR_SLEEPONEXIT_Msk); + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief 进入ç¡çœ æ¨¡å¼ + ** + ** + ** + ** \retval NULL + *****************************************************************************/ +void Lpm_GotoLpmMode(void) +{ + __WFI(); +} + +//@} // LpmGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpt.c new file mode 100644 index 0000000000..dcefd2e5e3 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpt.c @@ -0,0 +1,289 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file lpt.c + ** + ** Common API of Low Power timer. + ** @link lptGroup Some description @endlink + ** + ** - 2018-04-16 Husj First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "lpt.h" +/** + ******************************************************************************* + ** \addtogroup LptGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnLpTimCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Low Power Timer ä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Lpt_GetIntFlag(void) +{ + boolean_t bRetVal = FALSE; + + bRetVal = M0P_LPTIMER->IFR_f.TF ? TRUE : FALSE; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断标志清除 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_ClearIntFlag(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->ICLR_f.TFC = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param == 0 + ** + *****************************************************************************/ +void LpTim_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnLpTimCallback) + { + pfnLpTimCallback(); + } +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断使能 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_EnableIrq (void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.IE = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 中断ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_DisableIrq(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.IE = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer åˆå§‹åŒ–é…ç½® + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_Init(stc_lpt_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.GATE_P = pstcConfig->enGateP; + M0P_LPTIMER->CR_f.GATE = pstcConfig->enGate; + M0P_LPTIMER->CR_f.TCK_SEL = pstcConfig->enTckSel; + M0P_LPTIMER->CR_f.TOG_EN = pstcConfig->enTog; + M0P_LPTIMER->CR_f.CT = pstcConfig->enCT; + M0P_LPTIMER->CR_f.MD = pstcConfig->enMD; + + pfnLpTimCallback = pstcConfig->pfnLpTimCb; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer å¯åŠ¨è¿è¡Œ + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_Run(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.TR = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer åœæ­¢è¿è¡Œ + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_Stop(void) +{ + en_result_t enResult = Error; + + M0P_LPTIMER->CR_f.TR = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer é‡è½½å€¼è®¾ç½® + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Lpt_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Error; + boolean_t bRetVal = FALSE; + + bRetVal = M0P_LPTIMER->CR_f.WT_FLAG ? TRUE : FALSE; + if(TRUE == bRetVal) + { + M0P_LPTIMER->ARR_f.ARR = u16Data; + enResult = Ok; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Low Power Timer 16ä½è®¡æ•°å€¼èŽ·å– + ** + ** + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Lpt_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_LPTIMER->CNT_f.CNT; + + return u16CntData; +} + +//@} // LptGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpuart.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpuart.c new file mode 100644 index 0000000000..986b7377b4 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lpuart.c @@ -0,0 +1,966 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lpuart.c + ** + ** LPUART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lpuart.h" +/** + ****************************************************************************** + ** \addtogroup LPUartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +#define IS_VALID_CH(x) ((LPUART0 == (x)) ||\ + (LPUART1 == (x))) + +#define IS_VALID_CLK(x) ((LPUart_Pclk==(x))||\ + (LPUart_Pclk_1==(x))||\ + (LPUart_Xtl==(x))||\ + (LPUart_Rcl==(x))) + +#define IS_VALID_IRQSEL(x) ((LPUartTxIrq == (x)) ||\ + (LPUartRxIrq == (x)) ||\ + (LPUartFEIrq == (x)) ||\ + (LPUartCtsIrq == (x))||\ + (LPUartPEIrq == (x)) ||\ + (LPUartTxEIrq == (x))) + +#define IS_VALID_MODE(x) ((LPUartMode0==(x))||\ + (LPUartMode1==(x))||\ + (LPUartMode2==(x))||\ + (LPUartMode3==(x))) + +#define IS_VALID_STATUS(x) ((LPUartCts == (x))||\ + (LPUartRC == (x))||\ + (LPUartTC == (x))||\ + (LPUartPE == (x))||\ + (LPUartCtsIf == (x))||\ + (LPUartTxe == (x))||\ + (LPUartFE == (x))) +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_lpuart_instance_data_t* LPUartGetInternDataPtr(uint8_t u8Idx); +static void LPUartInitNvic(uint8_t u8Idx); +static void LPUartDeInitNvic(uint8_t u8Idx); +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +static stc_lpuart_instance_data_t m_astcLPUartInstanceDataLut[] = +{ + { + LPUART0, + M0P_LPUART0, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, + { + LPUART1, + M0P_LPUART1, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, +}; +/** + ****************************************************************************** + ** \brief LPUART0/1é€šé“ ç›¸å…³åœ°å€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 通é“对应的地å€ç»“æž„ + ** + ******************************************************************************/ +static stc_lpuart_instance_data_t* LPUartGetInternDataPtr(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t* pstcData = NULL; + uint8_t u8i = 0; + for (u8i = 0; u8i < ARRAY_SZ(m_astcLPUartInstanceDataLut); u8i++) + { + if (u8Idx == m_astcLPUartInstanceDataLut[u8i].u32Idx) + { + pstcData = &m_astcLPUartInstanceDataLut[u8i]; + break; + } + } + + return (pstcData); +} +/** + ****************************************************************************** + ** \brief LPUART通信中断使能函数设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断使能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_EnableIrq(uint8_t u8Idx, + en_lpuart_irq_sel_t enIrqSel) +{ + stc_lpuart_instance_data_t* pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case LPUartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 1u; + break; + case LPUartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 1u; + break; + case LPUartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 1u; + break; + case LPUartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 1u; + break; + case LPUartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 1u; + break; + case LPUartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通信中断ç¦æ­¢å‡½æ•°è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断ç¦æ­¢ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_DisableIrq(uint8_t u8Idx, + en_lpuart_irq_sel_t enIrqSel) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case LPUartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 0u; + break; + case LPUartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 0u; + break; + case LPUartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 0u; + break; + case LPUartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 0u; + break; + case LPUartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 0u; + break; + case LPUartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief lpuart通信时钟æºé€‰æ‹© + ** + ** \param [in] u8Idx通é“å·ï¼ŒenClk 时钟æºé€‰é¡¹ + ** + ** \retval Ok 设置æˆåŠŸ + **\retval ErrorInvalidParameter设置失败 + ******************************************************************************/ +en_result_t LPUart_SelSclk(uint8_t u8Idx,en_lpuart_sclksel_t enClk) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_CLK(enClk)); + switch(enClk) + { + case LPUart_Pclk: + case LPUart_Pclk_1: + case LPUart_Xtl: + case LPUart_Rcl: + pstcData->pstcInstance->SCON_f.SCLKSEL = enClk; + break; + default: + return (ErrorInvalidParameter); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief lpuart通信时钟æºé€‰æ‹© + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval Ok 设置æˆåŠŸ + **\retval + ******************************************************************************/ +uint32_t LPUart_GetSclk(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + uint8_t u8Sclksrc; + uint32_t u32Sclk; + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + ASSERT(IS_VALID_CH(u8Idx)); + u8Sclksrc = pstcData->pstcInstance->SCON_f.SCLKSEL; + switch(u8Sclksrc) + { + case 0x00: + case 0x01: + u32Sclk = Sysctrl_GetPClkFreq(); + break; + case 0x02: + u32Sclk = 32768; + break; + case 0x03: + u32Sclk = 38400;//此处必须使能内部38.4k + break; + default: + return 0; + } + return u32Sclk; +} +/** + ****************************************************************************** + ** \brief LPUART通é“4ç§æ¨¡å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œmode哪ç§æ¨¡å¼ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetMode(uint8_t u8Idx,en_lpuart_mode_t enMode) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_MODE(enMode)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.SM = enMode; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒstcMultiConfig多主机模å¼ç»“æž„ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetMultiMode(uint8_t u8Idx,stc_lpuart_multimode_t* pstcMultiConfig) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL != pstcMultiConfig) + { + pstcData->pstcInstance->SCON_f.ADRDET = pstcMultiConfig->enMulti_mode; + if(pstcMultiConfig->enMulti_mode == LPUartMulti) + { + pstcData->pstcInstance->SADDR = pstcMultiConfig->u8SlaveAddr; + pstcData->pstcInstance->SADEN = pstcMultiConfig->u8SaddEn; + } + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼å‘é€æ•°æ®/地å€å¸§æˆ–者奇å¶æ ¡éªŒé…ç½®TB8 + ** + ** \param [in] u8Idx通é“å·ï¼Œtb8æ•°æ®or地å€å¸§æˆ–者奇å¶æ ¡éªŒ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetMMDOrCk(uint8_t u8Idx,en_lpuart_mmdorck_t enTb8) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.B8CONT = enTb8; + return Ok; +} +/** + ****************************************************************************** + ** \brief 获å–RB8数值 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval RB8 + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +boolean_t LPUart_GetRb8(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + return ((pstcData->pstcInstance->SBUF>>8)&0x01); +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼ä»Žæœºåœ°å€é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddråœ°å€ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetSaddr(uint8_t u8Idx,uint8_t u8Addr) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADDR = u8Addr; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“多主机模å¼ä»ŽæœºæŽ©ç é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddren地å€æŽ©ç  + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetSaddrEn(uint8_t u8Idx,uint8_t u8Addren) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADEN = u8Addren; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“åœæ­¢ä½é•¿åº¦è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Lenåœæ­¢ä½é•¿åº¦ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_SetStopBit(uint8_t u8Idx,uint8_t u8Len) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + switch(u8Len) + { + case LPUart1bit: + case LPUart15bit: + case LPUart2bit: + pstcData->pstcInstance->SCON_f.STOPBIT = u8Len; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART采样频率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Div采样频率 + ** + ** \retval OKé…ç½®æˆåŠŸ + ******************************************************************************/ +en_result_t LPUart_SetClkDiv(uint8_t u8Idx,en_lpuart_clkdiv_t enClkDiv) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCON_f.OVER = enClkDiv; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART波特率计算值 + ** + ** \param [in] u8Idx通é“å·ï¼ŒstcBaud计算波特率值å‚æ•° + ** + ** \retval SCNT计算值 + ******************************************************************************/ +uint16_t LPUart_CalScnt(uint8_t u8Idx,stc_lpuart_baud_t *pstcBaud) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + uint16_t u16Scnt = 0; + uint8_t u8Over = 0; + ASSERT(IS_VALID_CH(u8Idx)); + + pstcData = LPUartGetInternDataPtr(u8Idx); + u8Over = pstcData->pstcInstance->SCON_f.OVER; + if(u8Over == 3) + { + return 0;//test + } + if(LPUartMode0 == pstcBaud->enRunMode) + { + return 0;//test + } + if((LPUartMode1 == pstcBaud->enRunMode)||(LPUartMode3 == pstcBaud->enRunMode)) + { + u8Over = 1<<(4-u8Over); + u16Scnt = pstcBaud->u32Sclk/(pstcBaud->u32Baud*u8Over); + } + else + { + u8Over = 1<<(5-u8Over); + u16Scnt = pstcBaud->u32Sclk/u8Over; + } + return u16Scnt; +} +/** + ****************************************************************************** + ** \brief LPUART通é“波特率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu32pclk时钟æºï¼ŒstcBaud波特率é…置结构 + ** + ** \retval 定时器é…置值 + ** \retval 0,获å–值失败 + ******************************************************************************/ +en_result_t LPUart_SetBaud(uint8_t u8Idx,uint16_t u16Scnt) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCNT = u16Scnt; + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“æ³¢ç‰¹çŽ‡èŽ·å– + ** + ** \param [in] u8Idx通é“å·,u8Modeå·¥ä½œæ¨¡å¼ + ** + ** \retval 波特率 + ******************************************************************************/ +uint32_t LPUart_GetBaud(uint8_t u8Idx,uint8_t u8Mode,uint32_t u32Pclk) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + uint32_t u32Baud = 0; + uint8_t u8Over = 0; + uint16_t u16Scnt = 0; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + u8Over = pstcData->pstcInstance->SCON_f.OVER; + switch(u8Mode) + { + case LPUartMode0: + u32Baud = u32Pclk/12; + break; + case LPUartMode1: + case LPUartMode3: + u16Scnt = pstcData->pstcInstance->SCNT; + u8Over = 1<<(4-u8Over); + u32Baud = u32Pclk/(u8Over*u16Scnt); + break; + case LPUartMode2: + u8Over = 1<<(5-u8Over); + u32Baud = u32Pclk/u8Over; + break; + default: + return 0;//test + } + return u32Baud; +} +/** + ****************************************************************************** + ** \brief LPUART通é“å‘é€æˆ–接收等功能使能设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_EnableFunc(uint8_t u8Idx, en_lpuart_func_t enFunc) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case LPUartTx: + case LPUartRx: + pstcData->pstcInstance->SCON_f.REN = 1u; + break; + case LPUartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 1u; + break; + case LPUartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 1u; + break; + case LPUartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 1u; + pstcData->pstcInstance->SCON_f.RTSEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“å‘é€æˆ–接收等功能ç¦æ­¢è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_DisableFunc(uint8_t u8Idx, en_lpuart_func_t enFunc) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case LPUartTx: + case LPUartRx: + pstcData->pstcInstance->SCON_f.REN = 0u; + break; + case LPUartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 0u; + break; + case LPUartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 0u; + break; + case LPUartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 0u; + pstcData->pstcInstance->SCON_f.RTSEN = 0u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 状æ€å€¼isr + ******************************************************************************/ +uint8_t LPUart_GetIsr(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + return(pstcData->pstcInstance->ISR); +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€å…¨éƒ¨æ¸…除 + ** + ** \param [in] u8Idx通é“å· + ** + **\retval Ok + ******************************************************************************/ +en_result_t LPUart_ClrIsr(uint8_t u8Idx) +{ + en_result_t enRet = Error; + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->ICR = 0; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatus获å–å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter获å–失败 + ******************************************************************************/ +boolean_t LPUart_GetStatus(uint8_t u8Idx,en_lpuart_status_t enStatus) +{ + boolean_t bStatus=FALSE; + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter;//4，用户åªéœ€åˆ¤æ–­0或1 + } + switch(enStatus) + { + case LPUartCts: + bStatus = (pstcData->pstcInstance->ISR_f.CTS == 1) ? TRUE : FALSE; + break; + case LPUartRC: + bStatus = (pstcData->pstcInstance->ISR_f.RC == 1) ? TRUE : FALSE; + break; + case LPUartTC: + bStatus = (pstcData->pstcInstance->ISR_f.TC == 1) ? TRUE : FALSE; + break; + case LPUartPE: + bStatus = (pstcData->pstcInstance->ISR_f.PE == 1) ? TRUE : FALSE; + break; + case LPUartFE: + bStatus = (pstcData->pstcInstance->ISR_f.FE == 1) ? TRUE : FALSE; + break; + case LPUartCtsIf: + bStatus = (pstcData->pstcInstance->ISR_f.CTSIF == 1) ? TRUE : FALSE; + break; + case LPUartTxe: + bStatus = (pstcData->pstcInstance->ISR_f.TXE == 1) ? TRUE : FALSE; + break; + default: + break; + } + return bStatus; +} +/** + ****************************************************************************** + ** \brief LPUART通é“通信状æ€æ¸…除 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatusæ¸…é™¤å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter清除失败 + ******************************************************************************/ +en_result_t LPUart_ClrStatus(uint8_t u8Idx,en_lpuart_status_t enStatus) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enStatus) + { + case LPUartCts: + pstcData->pstcInstance->ICR_f.CTSIFCF = 0; + break; + case LPUartRC: + pstcData->pstcInstance->ICR_f.RCCF = 0; + break; + case LPUartTC: + pstcData->pstcInstance->ICR_f.TCCF = 0; + break; + case LPUartPE: + pstcData->pstcInstance->ICR_f.PECF = 0; + break; + case LPUartFE: + pstcData->pstcInstance->ICR_f.FECF = 0; + break; + default: + break; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“å‘é€æ•°æ®å‡½æ•°,查询方å¼è°ƒç”¨æ­¤å‡½æ•°ï¼Œä¸­æ–­æ–¹å¼å‘é€ä¸é€‚用 + ** + ** \param [in] u8Idx通é“å·ï¼ŒDataå‘é€æ•°æ® + ** + ** \retval Okå‘é€æˆåŠŸ + **\retval ErrorInvalidParameterå‘é€å¤±è´¥ + ******************************************************************************/ +en_result_t LPUart_SendData(uint8_t u8Idx, uint8_t u8Data) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + LPUart_ClrStatus(u8Idx,LPUartTC); + pstcData->pstcInstance->SBUF_f.DATA = u8Data; + while(FALSE == LPUart_GetStatus(u8Idx,LPUartTC)) + {} + LPUart_ClrStatus(u8Idx,LPUartTC); + return Ok; +} +/** + ****************************************************************************** + ** \brief LPUART通é“接收数æ®å‡½æ•° + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æŽ¥æ”¶æ•°æ® + **\retval ErrorInvalidParameter接收失败 + ******************************************************************************/ +uint8_t LPUart_ReceiveData(uint8_t u8Idx) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + return (pstcData->pstcInstance->SBUF_f.DATA); +} +/** + ****************************************************************************** + ** \brief LPUART通é“中断处ç†å‡½æ•° + ** + ** \param [in] u8Param通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +void LpUart_IRQHandler(uint8_t u8Param) +{ + stc_lpuart_instance_data_t *pstcData = NULL; + pstcData = LPUartGetInternDataPtr(u8Param); + if (NULL == pstcData) + { + return; + } + if(1 == pstcData->pstcInstance->ISR_f.FE) + { + LPUart_ClrStatus(u8Param,LPUartFE); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnRxFEIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnRxFEIrqCb(); + } + return;//帧出错则ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.PE) + { + LPUart_ClrStatus(u8Param,LPUartPE); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnPEIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnPEIrqCb(); + } + return;//若奇å¶æ ¡éªŒå‡ºé”™åˆ™ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.CTSIF) + { + LPUart_ClrStatus(u8Param,LPUartCts); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnCtsIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnCtsIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.RC) + { + LPUart_ClrStatus(u8Param,LPUartRC); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnRxIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnRxIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.TC) + { + LPUart_ClrStatus(u8Param,LPUartTC); + if(NULL != pstcData->stcLPUartInternIrqCb.pfnTxIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnTxIrqCb(); + } + } +} +/** + ****************************************************************************** + ** \brief LPUART通é“使能内核NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void LPUartInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx));; + enIrqIndex = (IRQn_Type)(LPUART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_EnableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief LPUART通é“ç¦æ­¢å†…æ ¸NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void LPUartDeInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx)); + enIrqIndex = (IRQn_Type)(LPUART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_DisableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief LPUART通é“åˆå§‹åŒ–函数 + ** + ** \param [in] u8Idx通é“å·ï¼ŒpstcConfigåˆå§‹åŒ–结构体 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t LPUart_Init(uint8_t u8Idx,stc_lpuart_config_t* pstcConfig) +{ + en_result_t enRet = Error; + stc_lpuart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = LPUartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL == pstcConfig) + { + return ErrorInvalidParameter; + } + if(NULL != pstcConfig->pstcLpuart_clk) + { + LPUart_SelSclk(u8Idx,pstcConfig->pstcLpuart_clk->enSclk_sel); + LPUart_SetClkDiv(u8Idx,pstcConfig->pstcLpuart_clk->enSclk_Prs); + } + enRet = LPUart_SetMode(u8Idx,pstcConfig->enRunMode); + enRet = LPUart_SetStopBit(u8Idx,pstcConfig->enStopBit); + if(NULL != pstcConfig->pstcMultiMode) + { + enRet = LPUart_SetMultiMode(u8Idx,pstcConfig->pstcMultiMode); + } + if(NULL != pstcConfig->pstcIrqCb) + { + pstcData->stcLPUartInternIrqCb.pfnRxFEIrqCb = pstcConfig->pstcIrqCb->pfnRxFEIrqCb; + pstcData->stcLPUartInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcData->stcLPUartInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcData->stcLPUartInternIrqCb.pfnCtsIrqCb = pstcConfig->pstcIrqCb->pfnCtsIrqCb; + pstcData->stcLPUartInternIrqCb.pfnPEIrqCb = pstcConfig->pstcIrqCb->pfnPEIrqCb; + } + if(pstcConfig->bTouchNvic == TRUE) + { + LPUartInitNvic(u8Idx); + } + else + { + LPUartDeInitNvic(u8Idx); + } + enRet = Ok; + return enRet; +} +//@} // LPUartGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lvd.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lvd.c new file mode 100644 index 0000000000..d8e669fbaf --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/lvd.c @@ -0,0 +1,327 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file lvd.c + ** + ** Low Voltage Detect driver API. + ** @link Lvd Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "lvd.h" + +/** + ****************************************************************************** + ** \addtogroup LvdGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_INPUT(x) ( (x) <= LvdInputPB07 ) + +#define IS_VALID_THRESHOLD(x) ( (x) <= LvdTH3p3V ) + +#define IS_VALID_FILTER(x) ( (x) <= LvdFilter29ms ) + +#define IS_VALID_IRQTYPE(x) ( (x) <= LvdIrqFall ) + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') * + ******************************************************************************/ + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +// static void LvdEnableNvic(void); +// static void LvdDisableNvic(void); +// static en_result_t LvdEnable(en_lvd_type_t enType, boolean_t bFlag); + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnLvdIrqCbk = NULL; + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + + /** + * \brief + * LVD中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param 未使用 + * + * \retval æ—  + */ +void Lvd_IRQHandler(uint8_t u8Param) +{ + M0P_LVD->IFR_f.INTF = 0u; + if (NULL != pfnLvdIrqCbk) + { + pfnLvdIrqCbk(); + } +} + +/** + * \brief + * 使能NVIC中LVD中断 + * + * \param æ—  + * + * \retval æ—  + */ +static void LvdEnableNvic(void) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, IrqLevel3); + NVIC_EnableIRQ(LVD_IRQn); +} + +/** + * \brief + * 除能NVIC中LVD中断 + * + * \param æ—  + * + * \retval æ—  + */ +static void LvdDisableNvic(void) +{ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_DisableIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, IrqLevel3); +} + +/** + * \brief + * 使能LVD中断 + * + * \param [in] enType LVD中断类型 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效类型 + */ +en_result_t Lvd_EnableIrq(en_lvd_irq_type_t enType) +{ + en_result_t enRet = Ok; + + if (enType > LvdIrqFall) + { + return ErrorInvalidParameter; + } + else + { switch (enType) + { + case LvdIrqHigh: + M0P_LVD->CR_f.HTEN = 1u; + M0P_LVD->CR_f.RTEN = 0u; + M0P_LVD->CR_f.FTEN = 0u; + break; + case LvdIrqRise: + M0P_LVD->CR_f.HTEN = 0u; + M0P_LVD->CR_f.RTEN = 1u; + M0P_LVD->CR_f.FTEN = 0u; + break; + case LvdIrqFall: + M0P_LVD->CR_f.HTEN = 0u; + M0P_LVD->CR_f.RTEN = 0u; + M0P_LVD->CR_f.FTEN = 1u; + break; + default: + break; + } + + M0P_LVD->CR_f.IE = 1u; + LvdEnableNvic(); + } + return enRet; +} + +/** + * \brief + * 除能LVD中断 + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_DisableIrq(void) +{ + LvdDisableNvic(); + M0P_LVD->CR_f.IE = 0u; + M0P_LVD->CR_f.HTEN = 0u; + M0P_LVD->CR_f.RTEN = 0u; + M0P_LVD->CR_f.FTEN = 0u; +} + +/** + * \brief + * LVDåˆå§‹åŒ– + * + * \param [in] pstcConfig LVDé…置指针 + * + * \retval æ—  + */ +void Lvd_Init(stc_lvd_config_t *pstcConfig) +{ + ASSERT(pstcConfig); + ASSERT(IS_VALID_INPUT(pstcConfig->enInput)); + ASSERT(IS_VALID_THRESHOLD(pstcConfig->enThreshold)); + ASSERT(IS_VALID_FILTER(pstcConfig->enFilterTime)); + ASSERT(IS_VALID_IRQTYPE(pstcConfig->enIrqType)); + + //NEED to DISABLE first. + Lvd_Disable(); + Lvd_DisableIrq(); + LvdDisableNvic(); + + M0P_LVD->CR_f.DEBOUNCE_TIME = pstcConfig->enFilterTime; + M0P_LVD->CR_f.FLTEN = pstcConfig->bFilter; + M0P_LVD->CR_f.VTDS = pstcConfig->enThreshold; + M0P_LVD->CR_f.SOURCE_SEL = pstcConfig->enInput; + M0P_LVD->CR_f.ACT = pstcConfig->bLvdReset; + + pfnLvdIrqCbk = pstcConfig->pfnIrqCbk; +} + +/** + * \brief + * LVD deinit + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_DeInit(void) +{ + Lvd_DisableIrq(); + LvdDisableNvic(); + + pfnLvdIrqCbk = NULL; + Lvd_Disable(); +} + +/** + * \brief + * 使能LVD + * + * \param æ—  + * + * \retval æ—  + * + */ +void Lvd_Enable(void) +{ + M0P_LVD->CR_f.LVDEN = 1u; +} + +/** + * \brief + * 除能LVD + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_Disable(void) +{ + M0P_LVD->CR_f.LVDEN = 0u; +} + +/** + * \brief + * 获å–LVD中断标志 + * + * \param æ—  + * + * \retval boolean_t 中断标志 + */ +boolean_t Lvd_GetIrqStat(void) +{ + return M0P_LVD->IFR_f.INTF; + +} + +/** + * \brief + * 清除LVD中断标志 + * + * \param æ—  + * + * \retval æ—  + */ +void Lvd_ClearIrq(void) +{ + M0P_LVD->IFR_f.INTF = 0u; +} + +/** + * \brief + * 获å–Filter结果 + * + * \param æ—  + * + * \retval boolean_t Fliter结果 + */ +boolean_t Lvd_GetFilterResult(void) +{ + return (boolean_t)M0P_LVD->IFR_f.FILTER; +} +//@} // LvdGroup + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/opa.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/opa.c new file mode 100644 index 0000000000..38acfce544 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/opa.c @@ -0,0 +1,438 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file opa.c + ** + ** opa driver API. + ** @link opa Group Some description @endlink + ** + ** - 2018-04-15 Devi First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "opa.h" + +/** + ****************************************************************************** + ** \addtogroup OPAGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_pagagain(x) ( (x) <= 7 ) + +#define IS_VALID_channel(x) ( (OPA0 == (x)) ||\ + (OPA1 == (x)) ||\ + (OPA2 == (x)) ) + +#define IS_VALID_Mode(x) ( (OpaUintMode == (x)) ||\ + (OpaForWardMode == (x)) ||\ + (OpaOppositeMode == (x)) ||\ + (OpaThreeOppMode == (x)) ||\ + (OpaThreeForMode == (x)) ||\ + (OpaDiffMode == (x)) ||\ + (OpaMeterMode == (x)) ||\ + (OpaGpMode == (x)) ) + +#define IS_VALID_metergain(x) ( (OpaMeterGain3 == (x)) ||\ + (OpaMeterGain1_3 == (x)) ||\ + (OpaMeterGain1 == (x)) ) + +#define IS_VALID_calsel(x) ( (OpaSoftMode == (x)) ||\ + (OpaSoftTriggerMode == (x)) ||\ + (OpaADCTriggerMode == (x)) ) + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * \brief + * OPA åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +en_result_t OPA_Init(void) +{ + uint16_t i; + + M0P_SYSCTRL->PERI_CLKEN_f.ADC = 1; + M0P_BGR->CR_f.BGR_EN = 1; + for(i=0;i<2000;i++) + { + ; + } + + M0P_OPA->CR0 = 0x120; + M0P_OPA->CR1 = 0x120; + M0P_OPA->CR2 = 0x120; + M0P_OPA->CR = 0x00; + return Ok; +} + +/** + * \brief + * OPA 去åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +en_result_t OPA_DeInit(void) +{ + + M0P_OPA->CR0 = 0x120; + M0P_OPA->CR1 = 0x120; + M0P_OPA->CR2 = 0x120; + M0P_OPA->CR = 0x00; + M0P_BGR->CR_f.BGR_EN = 0; + M0P_SYSCTRL->PERI_CLKEN_f.ADC = 0; + return Ok; +} + +/** + * \brief + * OPA 基本功能设置 + * + * \param [in] en_opa_channel_t 使用那个通é“çš„OPA + * \param [in] en_opa_modesel_t OPA模å¼é€‰æ‹© + * \param [in] stc_opa_gain_config_t OPA增益选择 + * + * \retval æ—  + */ +en_result_t OPA_Operate(en_opa_channel_t enchannel ,en_opa_modesel_t enMode,stc_opa_gain_config_t *pstrGain) +{ + stc_opa_cr0_field_t *stcOpacr; + + ASSERT( IS_VALID_Mode(enMode) ); + ASSERT( IS_VALID_channel(enchannel) ); + + if (OPA0 == enchannel) + { + stcOpacr = (stc_opa_cr0_field_t*)&M0P_OPA->CR0_f; + } + if (OPA1 == enchannel) + { + stcOpacr = (stc_opa_cr0_field_t*)&M0P_OPA->CR1_f; + } + if (OPA2 == enchannel) + { + stcOpacr = (stc_opa_cr0_field_t*)&M0P_OPA->CR2_f; + } + + if(enMode == OpaUintMode) + { + stcOpacr->NEGSEL = 0; + stcOpacr->POSSEL = 3; + stcOpacr->UBUFSEL = 1; + stcOpacr->POEN = 1; + } + else if(enMode == OpaForWardMode) + { + stcOpacr->NEGSEL = 1; + stcOpacr->POEN = 1; + stcOpacr->PGAGAIN = pstrGain->enNoInGain; + stcOpacr->POSSEL = 3; + stcOpacr->RESINMUX = 0; + stcOpacr->RESSEL = 1; + } + else if(enMode == OpaOppositeMode) + { + stcOpacr->NEGSEL = 1; + stcOpacr->POEN = 1; + stcOpacr->PGAGAIN = pstrGain->enInGain; + stcOpacr->POSSEL = 3; + stcOpacr->RESINMUX = 2; + stcOpacr->RESSEL = 1; + } + else if(enMode == OpaDiffMode) + { + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 3; + M0P_OPA->CR2_f.POSSEL = 0; + + M0P_OPA->CR0_f.NEGSEL = 0; + M0P_OPA->CR1_f.NEGSEL = 1; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 0; + M0P_OPA->CR1_f.RESINMUX = 1; + M0P_OPA->CR2_f.RESINMUX = 0; + + M0P_OPA->CR0_f.UBUFSEL = 1; + M0P_OPA->CR1_f.UBUFSEL = 0; + M0P_OPA->CR2_f.UBUFSEL = 0; + + M0P_OPA->CR0_f.RESSEL = 0; + M0P_OPA->CR1_f.RESSEL = 1; + M0P_OPA->CR2_f.RESSEL = 0; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 1; + M0P_OPA->CR2_f.POEN = 0; + + M0P_OPA->CR0_f.PGAGAIN = 0; + M0P_OPA->CR1_f.PGAGAIN = pstrGain->enNoInGain; + M0P_OPA->CR2_f.PGAGAIN = 0; + } + else if(enMode == OpaGpMode) + { + stcOpacr->BIASSEL = 1; + stcOpacr->MODE = 1; + stcOpacr->NEGSEL = 3; + stcOpacr->POEN = 0; + stcOpacr->PGAGAIN = 5; + stcOpacr->POSSEL = 3; + stcOpacr->RESINMUX = 0; + stcOpacr->RESSEL = 0; + stcOpacr->UBUFSEL = 0; + } + else + { + return ErrorInvalidParameter; + } + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} + +/** + * \brief + * OPA 基本功能设置 (级è”æ­£å‘å’Œåå‘模å¼ä»¥åŠä»ªè¡¨æ¨¡å¼) + * \param [in] en_opa_modesel_t OPA模å¼é€‰æ‹© + * \param [in] stc_opa_gain_config_t OPA增益选择 + * + * \retval æ—  + */ +en_result_t OPA_ThreeOperate(en_opa_modesel_t enMode,stc_opa_gain_config_t *pstrGain0,stc_opa_gain_config_t *pstrGain1,stc_opa_gain_config_t *pstrGain2) +{ + + ASSERT( IS_VALID_Mode(enMode) ); + + if(enMode == OpaThreeOppMode) + { + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 3; + M0P_OPA->CR2_f.POSSEL = 3; + + M0P_OPA->CR0_f.NEGSEL = 1; + M0P_OPA->CR1_f.NEGSEL = 1; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 2; + M0P_OPA->CR1_f.RESINMUX = 1; + M0P_OPA->CR2_f.RESINMUX = 1; + + M0P_OPA->CR0_f.RESSEL = 1; + M0P_OPA->CR1_f.RESSEL = 1; + M0P_OPA->CR2_f.RESSEL = 1; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 0; + M0P_OPA->CR2_f.POEN = 1; + + M0P_OPA->CR0_f.PGAGAIN = pstrGain0->enInGain; + M0P_OPA->CR1_f.PGAGAIN = pstrGain1->enInGain; + M0P_OPA->CR2_f.PGAGAIN = pstrGain2->enInGain; + } + else if(enMode == OpaThreeForMode) + { + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 2; + M0P_OPA->CR2_f.POSSEL = 2; + + M0P_OPA->CR0_f.NEGSEL = 1; + M0P_OPA->CR1_f.NEGSEL = 1; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 0; + M0P_OPA->CR1_f.RESINMUX = 0; + M0P_OPA->CR2_f.RESINMUX = 0; + + M0P_OPA->CR0_f.UBUFSEL = 0; + M0P_OPA->CR1_f.UBUFSEL = 0; + M0P_OPA->CR2_f.UBUFSEL = 0; + + M0P_OPA->CR0_f.RESSEL = 1; + M0P_OPA->CR1_f.RESSEL = 1; + M0P_OPA->CR2_f.RESSEL = 1; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 0; + M0P_OPA->CR2_f.POEN = 1; + + M0P_OPA->CR0_f.PGAGAIN = pstrGain0->enNoInGain; + M0P_OPA->CR1_f.PGAGAIN = pstrGain1->enNoInGain; + M0P_OPA->CR2_f.PGAGAIN = pstrGain2->enNoInGain; + } + else + { + return ErrorInvalidParameter; + } + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} + +/** + * \brief + * OPA ä»ªè¡¨æ¨¡å¼ + * \param [in] en_opa_metergain_t OPA增益选择 + * + * \retval æ—  + */ +en_result_t OPA_MeterOperate(en_opa_metergain_t enGainMode) +{ + ASSERT( IS_VALID_metergain(enGainMode) ); + + M0P_OPA->CR0_f.POSSEL = 3; + M0P_OPA->CR1_f.POSSEL = 3; + M0P_OPA->CR2_f.POSSEL = 1; + + M0P_OPA->CR0_f.NEGSEL = 0; + M0P_OPA->CR1_f.NEGSEL = 0; + M0P_OPA->CR2_f.NEGSEL = 1; + + M0P_OPA->CR0_f.RESINMUX = 0; + M0P_OPA->CR1_f.RESINMUX = 0; + M0P_OPA->CR2_f.RESINMUX = 1; + + M0P_OPA->CR0_f.UBUFSEL = 1; + M0P_OPA->CR1_f.UBUFSEL = 1; + M0P_OPA->CR2_f.UBUFSEL = 0; + + M0P_OPA->CR0_f.RESSEL = 1; + M0P_OPA->CR1_f.RESSEL = 0; + M0P_OPA->CR2_f.RESSEL = 1; + + M0P_OPA->CR0_f.POEN = 0; + M0P_OPA->CR1_f.POEN = 0; + M0P_OPA->CR2_f.POEN = 1; + + if(enGainMode == OpaMeterGain3) + { + M0P_OPA->CR0_f.PGAGAIN = 6; + M0P_OPA->CR2_f.PGAGAIN = 3; + } + if(enGainMode == OpaMeterGain1_3) + { + M0P_OPA->CR0_f.PGAGAIN = 3; + M0P_OPA->CR2_f.PGAGAIN = 6; + } + if(enGainMode == OpaMeterGain1) + { + M0P_OPA->CR0_f.PGAGAIN = 5; + M0P_OPA->CR2_f.PGAGAIN = 5; + } + + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} +/** + * \brief + * OPA æ ¡æ­£æ¨¡å¼ + * \param [in] en_opa_calsel_t OPA校正模å¼é€‰æ‹© + * + * \retval æ—  + */ +en_result_t OPA_Cal(en_opa_calsel_t enCalMode) +{ + ASSERT( IS_VALID_calsel(enCalMode) ); + + if(enCalMode == OpaSoftMode) + { + + } + if(enCalMode == OpaSoftTriggerMode) + { + + } + if (enCalMode == OpaADCTriggerMode) + { + + } + + M0P_OPA->CR0_f.EN = 1; + M0P_OPA->CR1_f.EN = 1; + M0P_OPA->CR2_f.EN = 1; + return Ok; +} +//@} // OPAGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pca.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pca.c new file mode 100644 index 0000000000..774e91c265 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pca.c @@ -0,0 +1,834 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file pca.c + ** + ** Common API of PCA. + ** @link pcaGroup Some description @endlink + ** + ** - 2018-04-16 Husj First version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "pca.h" +/** + ******************************************************************************* + ** \addtogroup PcaGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_MODULE(x) (Module0 == (x) ||\ + Module1 == (x) ||\ + Module2 == (x) ||\ + Module3 == (x) ||\ + Module4 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnPcaCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief PCAä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Pca_GetIntFlag(en_pca_module_t enModule) +{ + boolean_t bRetVal = FALSE; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + bRetVal = M0P_PCA->CCON_f.CCF0 ? TRUE : FALSE; + break; + case Module1: + bRetVal = M0P_PCA->CCON_f.CCF1 ? TRUE : FALSE; + break; + case Module2: + bRetVal = M0P_PCA->CCON_f.CCF2 ? TRUE : FALSE; + break; + case Module3: + bRetVal = M0P_PCA->CCON_f.CCF3 ? TRUE : FALSE; + break; + case Module4: + bRetVal = M0P_PCA->CCON_f.CCF4 ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief PCAè®¡æ•°ä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Pca_GetCntIntFlag(void) +{ + boolean_t bRetVal = FALSE; + + bRetVal = M0P_PCA->CCON_f.CF ? TRUE : FALSE; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief PCA中断标志清除 + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_ClearIntFlag(en_pca_module_t enModule) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->ICLR_f.CCF0 = FALSE; + enResult = Ok; + break; + case Module1: + M0P_PCA->ICLR_f.CCF1 = FALSE; + enResult = Ok; + break; + case Module2: + M0P_PCA->ICLR_f.CCF2 = FALSE; + enResult = Ok; + break; + case Module3: + M0P_PCA->ICLR_f.CCF3 = FALSE; + enResult = Ok; + break; + case Module4: + M0P_PCA->ICLR_f.CCF4 = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数中断标志清除 + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_ClearCntIntFlag(void) +{ + en_result_t enResult = Error; + + M0P_PCA->ICLR_f.CF = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA中断æœåŠ¡ç¨‹åº + ** + ** + ** \param [in] u8Param == 0 + ** + *****************************************************************************/ +void Pca_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnPcaCallback) + { + pfnPcaCallback(); + } +} + +/** + ***************************************************************************** + ** \brief PCA中断使能 + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_EnableIrq(en_pca_module_t enModule) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAPM0_f.CCIE = TRUE; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAPM1_f.CCIE = TRUE; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAPM2_f.CCIE = TRUE; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAPM3_f.CCIE = TRUE; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAPM4_f.CCIE = TRUE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数中断使能 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_EnableCntIrq (void) +{ + en_result_t enResult = Error; + + M0P_PCA->CMOD_f.CFIE = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA中断ç¦æ­¢ + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_DisableIrq(en_pca_module_t enModule) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAPM0_f.CCIE = FALSE; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAPM1_f.CCIE = FALSE; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAPM2_f.CCIE = FALSE; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAPM3_f.CCIE = FALSE; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAPM4_f.CCIE = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数中断ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_DisableCntIrq(void) +{ + en_result_t enResult = Error; + + M0P_PCA->CMOD_f.CFIE = FALSE; + enResult = Ok; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief PCAåˆå§‹åŒ–é…ç½® + ** + ** + ** \param [in] pstcConfig PCA模å—é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Init(stc_pca_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + M0P_PCA->CMOD_f.CIDL = pstcConfig->enCIDL; + M0P_PCA->CMOD_f.WDTE = pstcConfig->enWDTE; + M0P_PCA->CMOD_f.CPS = pstcConfig->enCPS; + + pfnPcaCallback = pstcConfig->pfnPcaCb; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA模å¼é…ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] pstcCapMod PCA模å¼é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CapModConfig(en_pca_module_t enModule, stc_pca_capmodconfig_t* pstcCapMod) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + { + M0P_PCA->CCAPM0_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM0_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM0_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM0_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM0_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM0_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module1: + { + M0P_PCA->CCAPM1_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM1_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM1_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM1_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM1_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM1_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module2: + { + M0P_PCA->CCAPM2_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM2_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM2_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM2_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM2_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM2_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module3: + { + M0P_PCA->CCAPM3_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM3_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM3_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM3_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM3_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM3_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + case Module4: + { + M0P_PCA->CCAPM4_f.ECOM = pstcCapMod->enECOM; + M0P_PCA->CCAPM4_f.CAPP = pstcCapMod->enCAPP; + M0P_PCA->CCAPM4_f.CAPN = pstcCapMod->enCAPN; + M0P_PCA->CCAPM4_f.MAT = pstcCapMod->enMAT; + M0P_PCA->CCAPM4_f.TOG = pstcCapMod->enTOG; + M0P_PCA->CCAPM4_f.PWM = pstcCapMod->en8bitPWM; + enResult = Ok; + } + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCAå¯åŠ¨è¿è¡Œ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Run(void) +{ + en_result_t enResult = Error; + + M0P_PCA->CCON_f.CR = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCAåœæ­¢è¿è¡Œ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Stop(void) +{ + en_result_t enResult = Error; + + M0P_PCA->CCON_f.CR = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA16ä½æ¯”较数æ®è®¾ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] u16Data PCAæ•èŽ·æ•°æ® + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CmpData16Set(en_pca_module_t enModule, uint16_t u16Data) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAP0_f.CCAP0 = u16Data; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAP1_f.CCAP1 = u16Data; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAP2_f.CCAP2 = u16Data; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAP3_f.CCAP3 = u16Data; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAP4_f.CCAP4 = u16Data; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief PCA16ä½æ•èŽ·æ•°æ®èŽ·å– + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval u16Data + *****************************************************************************/ +uint16_t Pca_CapData16Get(en_pca_module_t enModule) +{ + uint16_t u16Data = 0; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + u16Data = M0P_PCA->CCAP0_f.CCAP0; + break; + case Module1: + u16Data = M0P_PCA->CCAP1_f.CCAP1; + break; + case Module2: + u16Data = M0P_PCA->CCAP2_f.CCAP2; + break; + case Module3: + u16Data = M0P_PCA->CCAP3_f.CCAP3; + break; + case Module4: + u16Data = M0P_PCA->CCAP4_f.CCAP4; + break; + default: + u16Data = 0; + break; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief PCA高8ä½æ¯”较数æ®è®¾ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] u8Data PCA高8ä½æ•èŽ·æ•°æ® + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CmpDataHSet(en_pca_module_t enModule, uint8_t u8Data) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAP0H_f.CCAP0 = u8Data; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAP1H_f.CCAP1 = u8Data; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAP2H_f.CCAP2 = u8Data; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAP3H_f.CCAP3 = u8Data; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAP4H_f.CCAP4 = u8Data; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA低8ä½æ¯”较数æ®è®¾ç½® + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** \param [in] u8Data PCA低8ä½æ•èŽ·æ•°æ® + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CmpDataLSet(en_pca_module_t enModule, uint8_t u8Data) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + M0P_PCA->CCAP0L_f.CCAP0 = u8Data; + enResult = Ok; + break; + case Module1: + M0P_PCA->CCAP1L_f.CCAP1 = u8Data; + enResult = Ok; + break; + case Module2: + M0P_PCA->CCAP2L_f.CCAP2 = u8Data; + enResult = Ok; + break; + case Module3: + M0P_PCA->CCAP3L_f.CCAP3 = u8Data; + enResult = Ok; + break; + case Module4: + M0P_PCA->CCAP4L_f.CCAP4 = u8Data; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA计数器åˆå€¼è®¾ç½® + ** + ** + ** + ** \param [in] u16Data PCA计数器åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Error; + + M0P_PCA->CNT_f.CNT = u16Data; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA16ä½è®¡æ•°å™¨å€¼èŽ·å– + ** + ** + ** + ** \retval 16ä½è®¡æ•°å™¨å€¼ + *****************************************************************************/ +uint16_t Pca_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_PCA->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief PCA周期é‡è½½å€¼è®¾ç½® + ** + ** + ** + ** \param [in] u16Data PCA周期é‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_CARRSet(uint16_t u16Data) +{ + en_result_t enResult = Error; + + M0P_PCA->CARR_f.CARR = u16Data; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA周期é‡è½½å€¼èŽ·å– + ** + ** + ** + ** \retval PCA周期é‡è½½å€¼ + *****************************************************************************/ +uint16_t Pca_CARRGet(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_PCA->CARR_f.CARR; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief PCA增强PWM 使能 + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Enable16bitPWM(void) +{ + en_result_t enResult = Error; + + M0P_PCA->EPWM_f.EPWM = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCA增强PWM ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Pca_Disable16bitPWM(void) +{ + en_result_t enResult = Error; + + M0P_PCA->EPWM_f.EPWM = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief PCAæ¯”è¾ƒé«˜é€Ÿè¾“å‡ºæ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enModule PCA模å—选择（Module0ã€Module1ã€Module2ã€Module3ã€Module4） + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Pca_GetCmpHighFlag(en_pca_module_t enModule) +{ + boolean_t bRetVal = FALSE; + + ASSERT(IS_VALID_MODULE(enModule)); + + switch (enModule) + { + case Module0: + bRetVal = M0P_PCA->CCAPO_f.CCAPO0 ? TRUE : FALSE; + break; + case Module1: + bRetVal = M0P_PCA->CCAPO_f.CCAPO1 ? TRUE : FALSE; + break; + case Module2: + bRetVal = M0P_PCA->CCAPO_f.CCAPO2 ? TRUE : FALSE; + break; + case Module3: + bRetVal = M0P_PCA->CCAPO_f.CCAPO3 ? TRUE : FALSE; + break; + case Module4: + bRetVal = M0P_PCA->CCAPO_f.CCAPO4 ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +//@} // PcaGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pcnt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pcnt.c new file mode 100644 index 0000000000..bdf0561aeb --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/pcnt.c @@ -0,0 +1,417 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file pcnt.c + ** + ** pcnt driver API. + ** @link pcnt Group Some description @endlink + ** + ** - 2018-04-15 Devi First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "pcnt.h" + +/** + ****************************************************************************** + ** \addtogroup PCNTGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define IS_VALID_pagagain(x) ( (x) <= 7 ) + +#define IS_VALID_channel(x) ( (OPA0 == (x)) ||\ + (OPA1 == (x)) ||\ + (OPA2 == (x)) ) + +#define IS_VALID_STAT(x) ( (PCNT_S1E == (x)) ||\ + (PCNT_S0E == (x)) ||\ + (PCNT_BB == (x)) ||\ + (PCNT_FE == (x)) ||\ + (PCNT_DIR == (x)) ||\ + (PCNT_TO == (x)) ||\ + (PCNT_OV == (x)) ||\ + (PCNT_UF == (x)) ) + + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnPcntCallback = NULL; ///< callback function pointer for PCNT Irq +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +void Pcnt_IRQHandler(void) +{ + if(NULL != pfnPcntCallback) + { + pfnPcntCallback(); + } +} + +/** + * \brief + * PCNT åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +en_result_t PCNT_Init(stc_pcnt_config_t* pstcPcntConfig) +{ + + + M0P_SYSCTRL->PERI_CLKEN_f.PCNT = 1; + + M0P_PCNT->CR_f.S1P = pstcPcntConfig->bS1Sel; + M0P_PCNT->CR_f.S0P = pstcPcntConfig->bS0Sel; + M0P_PCNT->CR_f.DIR = pstcPcntConfig->u8Direc; //è®¡æ•°æ–¹å¼ + M0P_PCNT->CR_f.CLKSEL = pstcPcntConfig->u8Clk; + M0P_PCNT->CR_f.MODE = pstcPcntConfig->u8Mode; + + M0P_PCNT->FLT_f.CLKDIV = pstcPcntConfig->u8FLTClk; + + if(pstcPcntConfig->bFLTEn) + { + if(pstcPcntConfig->u8FLTDep == 0) + { + M0P_PCNT->FLT_f.DEBTOP = 2; + } + else + { + M0P_PCNT->FLT_f.DEBTOP = pstcPcntConfig->u8FLTDep; + } + } + M0P_PCNT->FLT_f.EN = pstcPcntConfig->bFLTEn; + + M0P_PCNT->TOCR_f.TH = pstcPcntConfig->u16TODep; + M0P_PCNT->TOCR_f.EN = pstcPcntConfig->bTOEn; + + if (TRUE == pstcPcntConfig->bIrqEn) + { + M0P_PCNT->IEN = pstcPcntConfig->u8IrqStatus; + EnableNvic(PCNT_IRQn,IrqLevel3,TRUE); + } + else + { + M0P_PCNT->IEN = 0x00; + EnableNvic(PCNT_IRQn,IrqLevel3,FALSE); + } + if(NULL != pstcPcntConfig->pfnIrqCb) + { + pfnPcntCallback = pstcPcntConfig->pfnIrqCb; + } + return Ok; +} + +/** + * \brief + * PCNT 去åˆå§‹åŒ– + * + * \param æ—  + * \param æ—  + * + * \retval æ—  + * \retval æ—  + */ +void PCNT_DeInit(void) +{ + M0P_PCNT->CR = 0; + M0P_PCNT->RUN = 0; + M0P_SYSCTRL->PERI_CLKEN_f.PCNT = 0; + +} + +/** + * \brief + * PCNT 脉冲计数设置 + * + * \param [in] start 开始计数设置 + * \param [in] end 结æŸè®¡æ•°è®¾ç½® + * + * \retval æ—  + */ +en_result_t PCNT_Parameter(uint8_t start,uint8_t end) +{ + uint32_t u32TimeOut; + + u32TimeOut = 1000; + M0P_PCNT->BUF = end; //加载结æŸæº¢å‡ºå€¼ + M0P_PCNT->CMD_f.B2T = 1; + + while(u32TimeOut--) + { + if(FALSE == M0P_PCNT->SR2_f.B2T) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + + u32TimeOut = 1000; + M0P_PCNT->BUF = start; //加载åˆå§‹å€¼ + M0P_PCNT->CMD_f.B2C = 1; + + while(u32TimeOut--) + { + if(FALSE == M0P_PCNT->SR2_f.B2C) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + return Ok; +} + +/** + * \brief + * 获å–PCNTè®¡æ•°æ–¹å‘ + * \param [in] + * + * \retval æ—  + */ +en_pcnt_direcsel_t PCNT_Direction(void) +{ + return (en_pcnt_direcsel_t)M0P_PCNT->SR1_f.DIR; +} + +/** + * \brief + * 获å–PCNT计数值 + * \param [in] + * + * \retval æ—  + */ +uint16_t PCNT_Count(void) +{ + return M0P_PCNT->CNT; +} + +/** + * \brief + * 获å–PCNT溢出值 + * \param [in] + * + * \retval æ—  + */ +uint16_t PCNT_TopCount(void) +{ + return M0P_PCNT->TOP; +} + +/** + * \brief + * PCNT使能 + * \param [in] + * + * \retval æ—  + */ +void PCNT_Run(boolean_t work) +{ + M0P_PCNT->RUN_f.RUN = work; +} + +/** + * \brief + * PCNT 读å–çŠ¶æ€ + * \param [in] en_pcnt_status_t PCNTçŠ¶æ€ + * + * \retval æ—  + */ +boolean_t PCNT_GetStatus(en_pcnt_status_t enStatus) +{ + boolean_t bFlag = FALSE; + + ASSERT(IS_VALID_STAT(enStatus)); + + switch (enStatus) + { + case PCNT_S1E: + bFlag = M0P_PCNT->IFR_f.S1E; + break; + case PCNT_S0E: + bFlag = M0P_PCNT->IFR_f.S0E; + break; + case PCNT_BB: + bFlag = M0P_PCNT->IFR_f.BB; + break; + case PCNT_FE: + bFlag = M0P_PCNT->IFR_f.FE; + break; + case PCNT_DIR: + bFlag = M0P_PCNT->IFR_f.DIR; + break; + case PCNT_TO: + bFlag = M0P_PCNT->IFR_f.TO; + break; + case PCNT_OV: + bFlag = M0P_PCNT->IFR_f.OV; + break; + case PCNT_UF: + bFlag = M0P_PCNT->IFR_f.UF; + break; + default: + break; + } + return bFlag; +} +/** + * \brief + * PCNT æ¸…é™¤çŠ¶æ€ + * \param [in] en_pcnt_status_t PCNTçŠ¶æ€ + * + * \retval æ—  + */ +void PCNT_ClrStatus(en_pcnt_status_t enStatus) +{ + + ASSERT(IS_VALID_STAT(enStatus)); + + switch (enStatus) + { + case PCNT_S1E: + M0P_PCNT->ICR_f.S1E = 0; + break; + case PCNT_S0E: + M0P_PCNT->ICR_f.S0E = 0; + break; + case PCNT_BB: + M0P_PCNT->ICR_f.BB = 0; + break; + case PCNT_FE: + M0P_PCNT->ICR_f.FE = 0; + break; + case PCNT_DIR: + M0P_PCNT->ICR_f.DIR = 0; + break; + case PCNT_TO: + M0P_PCNT->ICR_f.TO = 0; + break; + case PCNT_OV: + M0P_PCNT->ICR_f.OV = 0; + break; + case PCNT_UF: + M0P_PCNT->ICR_f.UF = 0; + break; + default: + break; + } +} +/** + * \brief + * PCNT 中断设置 + * \param [in] en_pcnt_status_t PCNTçŠ¶æ€ + * + * \retval æ—  + */ +void PCNT_SetIrqStatus(en_pcnt_status_t enStatus) +{ + + ASSERT(IS_VALID_STAT(enStatus)); + + switch (enStatus) + { + case PCNT_S1E: + M0P_PCNT->IEN_f.S1E = 1; + break; + case PCNT_S0E: + M0P_PCNT->IEN_f.S0E = 1; + break; + case PCNT_BB: + M0P_PCNT->IEN_f.BB = 1; + break; + case PCNT_FE: + M0P_PCNT->IEN_f.FE = 1; + break; + case PCNT_DIR: + M0P_PCNT->IEN_f.DIR = 1; + break; + case PCNT_TO: + M0P_PCNT->IEN_f.TO = 1; + break; + case PCNT_OV: + M0P_PCNT->IEN_f.OV = 1; + break; + case PCNT_UF: + M0P_PCNT->IEN_f.UF = 1; + break; + default: + break; + } +} +//@} // OPAGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/reset.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/reset.c new file mode 100644 index 0000000000..8dd5ca06d7 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/reset.c @@ -0,0 +1,163 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file reset.c + ** + ** Common API of reset. + ** @link resetGroup Some description @endlink + ** + ** - 2017-05-04 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "reset.h" + +/** + ******************************************************************************* + ** \addtogroup ResetGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief 获å–å¤ä½æºç±»åž‹. + ** + ** \param [out] pstcOut å¤ä½æºç±»åž‹åˆ—表 + ** + ** \retval Ok æ“作æˆåŠŸ + ** 其他 æ“作失败 + ******************************************************************************/ +en_result_t Reset_GetCause(stc_reset_cause_t *pstcOut) +{ + uint8_t u8val = 0; + if (NULL == pstcOut) + { + return ErrorInvalidParameter; + } + + u8val = M0P_RESET->RESET_FLAG; + + *pstcOut = *((stc_reset_cause_t*)&u8val); + return Ok; +} + +/** + ******************************************************************************* + ** \brief 清除å¤ä½æºç±»åž‹. + ** + ** \param [in] stcval å¤ä½æºç±»åž‹åˆ—表,æ¯ç§ç±»åž‹å¯¹åº”的比特ä½å†™â€œ0â€æ¸…除，写“1â€æ— æ•ˆ + ** + ** \retval Ok æ“作æˆåŠŸ + ** 其他 æ“作失败 + ******************************************************************************/ +en_result_t Reset_Clear(stc_reset_cause_t stcval) +{ + uint8_t u8val = *((uint8_t*)&stcval); + + M0P_RESET->RESET_FLAG = u8val; + + return Ok; +} + +/** + ******************************************************************************* + ** \brief 设置外设å¤ä½æºå¼€å…³. + ** + ** \param [in] enPeri å¤ä½æºç±»åž‹åˆ—表 + ** \param [in] bFlag å¤ä½å¼€å…³ + ** + ** \retval Ok æ“作æˆåŠŸ + ** 其他 æ“作失败 + ******************************************************************************/ +en_result_t Reset_SetPeripheralReset(en_reset_peripheral_t enPeri, boolean_t bFlag) +{ + + bFlag = !!bFlag; + + if(TRUE == bFlag) + { + M0P_RESET->PREI_RESET |= (uint32_t)enPeri; + } + else + { + M0P_RESET->PREI_RESET &= ~(uint32_t)enPeri; + } + + return Ok; +} + +//@} // ResetGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rng.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rng.c new file mode 100644 index 0000000000..8ec6c08531 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rng.c @@ -0,0 +1,191 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file rng.c + ** + ** Common API of rng. + ** @link flashGroup Some description @endlink + ** + ** - 2018-05-08 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "rng.h" +/** + ******************************************************************************* + ** \addtogroup FlashGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief éšæœºæ•°åˆå§‹åŒ–(上电第一次生æˆéšæœºæ•°ï¼‰ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Rng_Init(void) +{ + //==>>生æˆ64bitséšæœºæ•°ï¼ˆä¸Šç”µç¬¬ä¸€æ¬¡ï¼‰ + M0P_RNG->CR_f.RNGCIR_EN = 1; + //模å¼é…ç½®0 + M0P_RNG->MODE_f.LOAD = 1; + M0P_RNG->MODE_f.FDBK = 1; + M0P_RNG->MODE_f.CNT = 6; + //生æˆéšæœºæ•°0 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //模å¼é…ç½®1 + M0P_RNG->MODE_f.LOAD = 0; + M0P_RNG->MODE_f.FDBK = 0; + M0P_RNG->MODE_f.CNT = 4; + //生æˆéšæœºæ•°1 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //关闭éšæœºæºç”µè·¯ï¼ŒèŠ‚çœåŠŸè€— + M0P_RNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief 生æˆéšæœºæ•°ï¼ˆéžä¸Šç”µç¬¬ä¸€æ¬¡ç”Ÿæˆéšæœºæ•°ï¼‰ + ** + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +en_result_t Rng_Generate(void) +{ + //==>>生æˆ64bitséšæœºæ•°ï¼ˆéžä¸Šç”µç¬¬ä¸€æ¬¡ç”Ÿæˆï¼‰ + M0P_RNG->CR_f.RNGCIR_EN = 1; + + //模å¼é…ç½®0 + M0P_RNG->MODE_f.LOAD = 0; + M0P_RNG->MODE_f.FDBK = 1; + M0P_RNG->MODE_f.CNT = 6; + //生æˆéšæœºæ•°0 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //模å¼é…ç½®1 + M0P_RNG->MODE_f.FDBK = 0; + M0P_RNG->MODE_f.CNT = 4; + M0P_RNG->MODE_f.CNT = 4; + //生æˆéšæœºæ•°1 + M0P_RNG->CR_f.RNG_RUN = 1; + while(M0P_RNG->CR_f.RNG_RUN) + { + ; + } + + //关闭éšæœºæºç”µè·¯ï¼ŒèŠ‚çœåŠŸè€— + M0P_RNG->CR_f.RNGCIR_EN = 0; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief éšæœºæ•°èŽ·å– + ** + ** \retval data0 + *****************************************************************************/ +uint32_t Rng_GetData0(void) +{ + return M0P_RNG->DATA0; +} + +/** + ***************************************************************************** + ** \brief éšæœºæ•°èŽ·å– + ** + ** \retval data1 + *****************************************************************************/ +uint32_t Rng_GetData1(void) +{ + return M0P_RNG->DATA1; +} + +//@} // RngGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rtc.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rtc.c new file mode 100644 index 0000000000..f6e1025edd --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/rtc.c @@ -0,0 +1,875 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file rtc.c + ** + ** RTC function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "rtc.h" +/** + ****************************************************************************** + ** \addtogroup RtcGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define IS_VALID_CLK(x) (RtcClk32768 == (x)||\ + RtcClk32768_1== (x)||\ + RtcClk32 == (x)||\ + RtcClk32_1 == (x)||\ + RtcClkHxt128 == (x)||\ + RtcClkHxt256 == (x)||\ + RtcClkHxt512 == (x)||\ + RtcClkHxt1024 == (x)) + +#define IS_VALID_CYCSEL(x) (RtcPrads == (x)||\ + RtcPradx==(x)) + +#define IS_VALID_PRDS(x) (Rtc_None == (x)||\ + Rtc_05S == (x)||\ + Rtc_1S == (x)||\ + Rtc_1Min == (x)||\ + Rtc_1H == (x)||\ + Rtc_1Day == (x)||\ + Rtc_1Mon == (x)||\ + Rtc_1Mon_1 == (x)) + +#define IS_VALID_IRQ_SEL(x) (RtcPrdf == (x) ||\ + RtcAlmf == (x)) + +#define IS_VALID_FUNC(x) ((RtcCount==(x))||\ + (RtcAlarmEn==(x))||\ + (Rtc_ComenEn==(x))||\ + (Rtc1HzOutEn==(x))) +#define CkDateTime 0x7F +#define CkDate 0x78 +#define CkTime 0x07 + +//#define DecToBcd(x) ((((x)/10)<<4) + ((x)%10)) +//#define BcdToDec(x) ((((x)>>4)*10) + ((x)&0x0F)) + +#define RTC_TIMEOUT 1000//test 1s + +/******************************************************************************/ +/* Local function prototypes ('const') */ +/******************************************************************************/ +const uint8_t Leap_Month_Base[] = {3,6,0,3,5,1,3,6,2,4,0,2}; +const uint8_t NonLeap_Month_Base[] = {4,0,0,3,5,1,3,6,2,4,0,2}; +const uint8_t Cnst_Month_Tbl[12]={0x31,0x28,0x31,0x30,0x31,0x30,0x31,0x31,0x30,0x31,0x30,0x31}; +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_rtc_intern_cb_t* RtcGetInternDataCb(void); +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ +static stc_rtc_intern_cb_t stcRtcIrqCb = {NULL, NULL}; +/** + ****************************************************************************** + ** \brief RTC计数时钟选择 + ** + ** \param [in] enClkæ—¶é’Ÿæº + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Rtc_SelClk(en_rtc_clk_t enClk) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CLK(enClk)); + M0P_RTC->CR1_f.CKSEL = enClk; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC周期中断方å¼é€‰æ‹© + ** + ** \param [in] pstccCyc周期中断方å¼åŠå‘¨æœŸé—´éš”选择 + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Rtc_SetCyc(stc_rtc_cyc_sel_t* pstcCyc) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CYCSEL(pstcCyc->enCyc_sel)); + ASSERT(IS_VALID_PRDS(pstcCyc->enPrds_sel)); + M0P_RTC->CR0_f.PRDSEL = pstcCyc->enCyc_sel; + if(pstcCyc->enCyc_sel) + { + M0P_RTC->CR0_f.PRDX = pstcCyc->u8Prdx; + } + else + { + M0P_RTC->CR0_f.PRDS = pstcCyc->enPrds_sel; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC时制选择 + ** + ** \param [in] bmode是12时制or24时制 + ** + ** \retval Ok 设置正常 + ** \retval ErrorInvalidParameter 设置异常 + ******************************************************************************/ +en_result_t Rtc_SetAmPm(en_rtc_ampm_t enMode) +{ + en_result_t enRet = Error; + switch(enMode) + { + case 0: + case 1: + M0P_RTC->CR0_f.AMPM = enMode; + break; + default: + return ErrorInvalidParameter; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTCæ—¶åˆ¶èŽ·å– + ** + ** \param [in] æ—  + ** + ** \retval 时制 + ******************************************************************************/ +boolean_t Rtc_GetHourMode(void) +{ + return(M0P_RTC->CR0_f.AMPM); +} +/** + ****************************************************************************** + ** \brief RTC闹钟中断设置 + ** + ** \param [in] pstcAlarmTime闹钟时间时ã€åˆ†ã€å‘¨ + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_SetAlarmTime(stc_rtc_alarmset_t* pstcAlarmTime) +{ + en_result_t enRet = Ok; + ASSERT(NULL != pstcAlarmTime); + if(Rtc12h == M0P_RTC->CR0_f.AMPM) + { + enRet = Check_BCD_Format(pstcAlarmTime->u8Hour,0x00,0x12); + } + else + { + enRet = Check_BCD_Format(pstcAlarmTime->u8Hour,0x00,0x24); + } + if(enRet != Ok) + { + return enRet; + } + enRet = Check_BCD_Format(pstcAlarmTime->u8Minute,0x00,0x59); + if(enRet != Ok) + { + return enRet; + } + // enRet = Check_BCD_Format(pstcAlarmTime->u8Week,0x00,0x06); + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->ALMHOUR = pstcAlarmTime->u8Hour; + M0P_RTC->ALMMIN = pstcAlarmTime->u8Minute; + M0P_RTC->ALMWEEK = pstcAlarmTime->u8Week; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTCé—¹é’Ÿä¸­æ–­æ—¶é—´èŽ·å– + ** + ** \param [in] pstcAlarmTime闹钟时间时ã€åˆ†ã€å‘¨ + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_GetAlarmTime(stc_rtc_alarmset_t* pstcAlarmTime) +{ + en_result_t enRet = Error; + ASSERT(NULL != pstcAlarmTime); + pstcAlarmTime->u8Minute = M0P_RTC->ALMMIN; + pstcAlarmTime->u8Hour = M0P_RTC->ALMHOUR; + pstcAlarmTime->u8Week = M0P_RTC->ALMWEEK; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC 1hz模å¼é€‰æ‹© + ** + ** \param [in] bmode 高精度和普通精度 + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_Set1HzMode(boolean_t bMode) +{ + en_result_t enRet = Error; + M0P_RTC->CR0_f.HZ1SEL = bMode; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC 1hzè¡¥å¿å€¼è®¾ç½® + ** + ** \param [in] u16Cr è¡¥å¿å€¼ + ** + ** \retval Ok 设置正常 + ** + ******************************************************************************/ +en_result_t Rtc_SetCompCr(uint16_t u16Cr) +{ + en_result_t enRet = Error; + M0P_RTC->COMPEN_f.CR = u16Cr; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC 功能使能设置 + ** + ** \param [in] enFunc 功能选择 + ** + ** \retval Ok 设置正常 + ** \retval ErrorInvalidParameter 设置异常 + ******************************************************************************/ +en_result_t Rtc_EnableFunc(en_rtc_func_t enFunc) +{ + ASSERT(IS_VALID_FUNC(enFunc)); + switch(enFunc) + { + case RtcCount: + M0P_RTC->CR0_f.START = 1u; + break; + case RtcAlarmEn: + M0P_RTC->CR1_f.ALMEN = 1u; + break; + case Rtc_ComenEn: + M0P_RTC->COMPEN_f.EN = 1u; + break; + case Rtc1HzOutEn: + M0P_RTC->CR0_f.HZ1OE = 1u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC 功能ç¦æ­¢è®¾ç½® + ** + ** \param [in] enFunc 功能选择 + ** + ** \retval Ok 设置正常 + ** \retval ErrorInvalidParameter 设置异常 + ******************************************************************************/ +en_result_t Rtc_DisableFunc(en_rtc_func_t enFunc) +{ + ASSERT(IS_VALID_FUNC(enFunc)); + switch(enFunc) + { + case RtcCount: + M0P_RTC->CR0_f.START = 0u; + break; + case RtcAlarmEn: + M0P_RTC->CR1_f.ALMEN = 0u; + break; + case Rtc_ComenEn: + M0P_RTC->COMPEN_f.EN = 0u; + break; + case Rtc1HzOutEn: + M0P_RTC->CR0_f.HZ1OE = 0u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +uint8_t Change_DateTimeFormat(uint8_t u8sr) +{ + uint8_t u8de=0; + while(u8sr>=0x10) + { + u8de +=10; + u8sr -=0x10; + } + u8de += u8sr; + return(u8de); +} +/** + ****************************************************************************** + ** \brief RTC å¹³ã€é—°å¹´æ£€æµ‹ + ** + ** \param [in] u8year å¹´åè¿›åˆ¶ä½Žä¸¤ä½ + ** + ** \retval 1 é—°å¹´ + ** \retval 0 平年 + ******************************************************************************/ +uint8_t Rtc_CheckLeapYear(uint8_t u8year) +{ + uint8_t u8year_shl,u8year_shr; + u8year_shl = u8year>>2; + u8year_shr = u8year_shl<<2; + if(u8year== u8year_shr) + { + return 1; + } + else + { + return 0; + } +} +/** + ****************************************************************************** + ** \brief RTCæ ¹æ®æ—¥æœŸè®¡ç®—周数 + ** + ** \param [in] pu8Date日期 + ** + ** \retval week 周数 + ** + ******************************************************************************/ +uint8_t Rtc_CalWeek(uint8_t* pu8Date) +{ + uint8_t u8week; + if((Rtc_CheckLeapYear(Change_DateTimeFormat(*(pu8Date+2)))==1)) + { + u8week = (Change_DateTimeFormat(*(pu8Date+2))+Change_DateTimeFormat(*(pu8Date+2))/4+Leap_Month_Base[Change_DateTimeFormat(*(pu8Date+1))-1]+Change_DateTimeFormat(*(pu8Date))+2)%7; + } + else + { + u8week = (Change_DateTimeFormat(*(pu8Date+2))+Change_DateTimeFormat(*(pu8Date+2))/4+NonLeap_Month_Base[Change_DateTimeFormat(*(pu8Date+1))-1]+Change_DateTimeFormat(*(pu8Date))+2)%7; + } + return u8week; +} +/** + ****************************************************************************** + ** \brief RTCæ ¹æ®å¹´æœˆèŽ·å–天数 + ** + ** \param [in] u8month月份，u8year年份 + ** + ** \retval u8day天数 + ** + ******************************************************************************/ +uint8_t Get_Month_Max_Day(uint8_t u8month, uint8_t u8year) +{ + uint8_t u8day = 0; + + u8day = Cnst_Month_Tbl[u8month - 1]; + if((u8month == 2) && ((u8year % 4) == 0)) + { + u8day++; + } + return(u8day);//dayçš„æ ¼å¼æ˜¯bcdç ï¼Œä¾‹å¦‚；日为31天，day=0x31 +} +/** + ****************************************************************************** + ** \brief RTCæ ¹æ®æ—¥æœŸè®¡ç®—周数 + ** + ** \param [in] pu8buf日期时间数æ®ï¼Œu8len检查数æ®é•¿åº¦ï¼Œu8limit_min最å°å€¼ï¼Œu8limit_max最大值 + ** + ** \retval Error 错误，Ok校验正确 + ** + ******************************************************************************/ +en_result_t Check_BCD_Format(uint8_t u8data,uint8_t u8limit_min, uint8_t u8limit_max) +{ + + if (((u8data & 0x0F) > 0x09) || ((u8data & 0xF0) > 0x90) + ||(u8data > u8limit_max) || (u8data < u8limit_min)) + { + return Error; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC时间格å¼æ£€æµ‹ + ** + ** \param [in] pu8TimeDate日期时间数æ®ï¼Œu8Modeæ£€æµ‹æ¨¡å¼ + ** + ** \retval enRet校验结果 + ** + ******************************************************************************/ +en_result_t Rtc_CheckDateTimeFormat(uint8_t* pu8TimeDate,uint8_t u8Mode) +{ + uint8_t u8i=0; + uint8_t u8mon_max_day = 0x28; + uint8_t u8date[3]; + uint8_t u8Hour = 0; + en_result_t enRet=Error; + while(u8i<7) + { + if(u8Mode&&(1<CR0_f.AMPM) + { + u8Hour = *pu8TimeDate&0x1f; + enRet = Check_BCD_Format(u8Hour,0x00,0x12);//æ—¶ + } + else + { + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x24); + } + break; + case 3: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x06); + break; + case 4: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x31); + u8date[0] = *pu8TimeDate; + break; + case 5: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x12); + u8date[1] = *pu8TimeDate; + break; + case 6: + enRet = Check_BCD_Format(*pu8TimeDate,0x00,0x99); + u8date[2] = *pu8TimeDate; + break; + default: + break; + } + pu8TimeDate++; + } + if(enRet!=Ok) + { + return enRet; + } + u8i++; + } + if((u8Mode&0x10)&&(u8Mode&0x20)) + { + if(u8Mode&0x40) + { + u8mon_max_day = Get_Month_Max_Day(Change_DateTimeFormat(u8date[1]), Change_DateTimeFormat(u8date[2])); + } + else + { + u8mon_max_day = Get_Month_Max_Day(Change_DateTimeFormat(u8date[1]), 1); + } + if(u8date[0]>u8mon_max_day) + { + return Error; + } + } + if((u8Mode&0x10)&&(!(u8Mode&0x20))) + { + if(u8date[0]>0x28) + { + return Error; + } + } + enRet = Ok; + return(enRet); +} +/** + ****************************************************************************** + ** \brief RTC设置时间函数 + ** + ** \param [in] pstcTimeDate日期时间数æ®ã€bUpdateTime是å¦æ›´æ”¹æ—¶é—´ã€bUpdateDate是å¦æ›´æ”¹æ—¥æœŸ + ** + ** \retval Ok 设置正常 + ** \retval ErrorTimeout 时间溢出错误 + ******************************************************************************/ +en_result_t Rtc_WriteDateTime(stc_rtc_time_t* pstcTimeDate,boolean_t bUpdateTime, + boolean_t bUpdateDate) +{ + int32_t u32TimeOut; + uint8_t* pu8TimeDate; + en_result_t enRet = Ok; + u32TimeOut = RTC_TIMEOUT; + pu8TimeDate = &pstcTimeDate->u8Second; + ASSERT(NULL != pstcTimeDate); + if(1 == M0P_RTC->CR0_f.START) + { + M0P_RTC->CR1_f.WAIT = 1; + while(--u32TimeOut) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u32TimeOut==0) + { + return ErrorTimeout; + } + } + if(TRUE == bUpdateTime) + { + enRet = Rtc_CheckDateTimeFormat(pu8TimeDate,CkTime); + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->SEC = pstcTimeDate->u8Second; + M0P_RTC->MIN = pstcTimeDate->u8Minute; + M0P_RTC->HOUR = pstcTimeDate->u8Hour; + } + if(TRUE == bUpdateDate) + { + enRet = Rtc_CheckDateTimeFormat(pu8TimeDate,CkDate); + if(enRet != Ok) + { + return enRet; + } + M0P_RTC->DAY = pstcTimeDate->u8Day; + M0P_RTC->MON = pstcTimeDate->u8Month; + M0P_RTC->YEAR = pstcTimeDate->u8Year; + M0P_RTC->WEEK = pstcTimeDate->u8DayOfWeek; + } + M0P_RTC->CR1_f.WAIT = 0; + if(1 == M0P_RTC->CR0_f.START) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + return enRet; +} +/** + ****************************************************************************** +** \brief RTC 12å°æ—¶ä¸Šåˆæˆ–下åˆèŽ·å– + ** + ** \param [in] æ—  + ** +** \retval 上åˆæˆ–ä¸‹åˆ + ******************************************************************************/ +boolean_t Rtc_RDAmPm(void) +{ + boolean_t bRet; + + bRet = M0P_RTC->HOUR&0x20; + bRet>>=5; + return bRet; +} +/** + ****************************************************************************** + ** \brief RTC获å–时间函数 + ** + ** \param [in] pstcTimeDateæ—¥æœŸæ—¶é—´æ•°æ® + ** + ** \retval Ok 获å–正常 + ** \retval ErrorTimeout 时间溢出错误 + ******************************************************************************/ +en_result_t Rtc_ReadDateTime(stc_rtc_time_t* pstcTimeDate) +{ + uint32_t u32TimeOut; + uint8_t u8DayOfWeek, u8BcdSec, u8BcdMin, u8BcdHour, u8Day, u8Month, u8Year; + + ASSERT(NULL != pstcTimeDate); + u32TimeOut = RTC_TIMEOUT; + if(1 == M0P_RTC->CR0_f.START) + { + M0P_RTC->CR1_f.WAIT = 1; + while(u32TimeOut--) + { + if(M0P_RTC->CR1_f.WAITF) + { + break; + } + } + if(u32TimeOut==0) + { + return ErrorTimeout; + } + } + u8BcdSec = M0P_RTC->SEC; + u8BcdMin = M0P_RTC->MIN; + u8BcdHour = M0P_RTC->HOUR; + u8Day = M0P_RTC->DAY; + u8Month = M0P_RTC->MON; + u8Year = M0P_RTC->YEAR; + u8DayOfWeek = M0P_RTC->WEEK; + + pstcTimeDate->u8Second = u8BcdSec; + pstcTimeDate->u8Minute = u8BcdMin; + if(1 == M0P_RTC->CR0_f.AMPM) + { + pstcTimeDate->u8Hour = u8BcdHour; + } + else + { + pstcTimeDate->u8Hour = u8BcdHour&0x1f; + } + pstcTimeDate->u8Day = u8Day; + pstcTimeDate->u8Month = u8Month; + pstcTimeDate->u8Year = u8Year; + pstcTimeDate->u8DayOfWeek = u8DayOfWeek; + + M0P_RTC->CR1_f.WAIT = 0; + if(1 == M0P_RTC->CR0_f.START) + { + while(M0P_RTC->CR1_f.WAITF) + {} + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC计数or读写状æ€èŽ·å– + ** + ** \param [in] æ—  + ** + ** \retval 计数orè¯»å†™çŠ¶æ€ + ** + ******************************************************************************/ +boolean_t Rtc_RDStatus(void) +{ + boolean_t bRet; + bRet = M0P_RTC->CR1_f.WAITF; + return bRet; +} +/** + ****************************************************************************** + ** \brief RTC闹钟中断使能 + ** + ** \param [in] enordis中断使能orç¦æ­¢ + ** + ** \retval Ok设置æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Rtc_EnAlarmIrq(en_rtc_alarmirq_t enIrqEn) +{ + en_result_t enRet = Error; + M0P_RTC->CR1_f.ALMIE = enIrqEn; + Rtc_ClrIrqStatus(RtcAlmf);//使能中断åŽæ¸…除中断请求标记 + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC中断请求状æ€èŽ·å– + ** + ** \param [in] enIrqSel获å–哪ç§ä¸­æ–­è¯·æ±‚ + ** + ** \retval ä¸­æ–­è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +boolean_t Rtc_GetIrqStatus(en_rtc_status_irq_t enIrqSel) +{ + boolean_t bRet = FALSE; + ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + switch(enIrqSel) + { + case RtcPrdf: + (M0P_RTC->CR1_f.PRDF == 1)?(bRet = TRUE) : (bRet = FALSE); + break; + case RtcAlmf : + (M0P_RTC->CR1_f.ALMF == 1)?(bRet = TRUE) : (bRet = FALSE); + break; + default: + break; + } + return bRet; +} +/** + ****************************************************************************** + ** \brief RTC中断请求清除 + ** + ** \param [in] enIrqSel清除哪ç§ä¸­æ–­è¯·æ±‚ + ** + ** \retval Ok 清除æˆåŠŸ + ** \retval ErrorInvalidParameter 清除失败 + ******************************************************************************/ +en_result_t Rtc_ClrIrqStatus(en_rtc_status_irq_t enIrqSel) +{ + ASSERT(IS_VALID_IRQ_SEL(enIrqSel)); + switch(enIrqSel) + { + case RtcPrdf: + M0P_RTC->CR1_f.PRDF = 0; + break; + case RtcAlmf: + M0P_RTC->CR1_f.ALMF = 0; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief RTC中断处ç†å‡½æ•°æŽ¥å£èŽ·å– + ** + ** \param [in] æ—  + ** + ** \retval 接å£å‡½æ•°åœ°å€ + ** + ******************************************************************************/ +static stc_rtc_intern_cb_t* RtcGetInternDataCb(void) +{ + return &stcRtcIrqCb; +} +/** + ****************************************************************************** + ** \brief RTC总体åˆå§‹åŒ–函数 + ** + ** \param [in] pstcRtcConfigåˆå§‹åŒ–结构 + ** + ** \retval Okåˆå§‹åŒ–æˆåŠŸ + ** \retval ErrorInvalidParameter åˆå§‹åŒ–错误 + ******************************************************************************/ +en_result_t Rtc_Init(stc_rtc_config_t* pstcRtcConfig) +{ + en_result_t enRet = Error; + stc_rtc_intern_cb_t* pstcRtcInternCb; + if(NULL == pstcRtcConfig) + { + return Error; + } + pstcRtcInternCb = RtcGetInternDataCb(); + enRet = Rtc_SelClk(pstcRtcConfig->enClkSel); + enRet = Rtc_SetAmPm(pstcRtcConfig->enAmpmSel); + if(enRet != Ok) + { + return enRet; + } + if(NULL != pstcRtcConfig->pstcCycSel) + { + if(Ok != Rtc_SetCyc(pstcRtcConfig->pstcCycSel)) + { + return Error; + } + } + if(NULL != pstcRtcConfig->pstcTimeDate) + { + if(Ok != Rtc_WriteDateTime(pstcRtcConfig->pstcTimeDate,TRUE,TRUE)) + { + return Error; + } + } + if(NULL != pstcRtcConfig->pstcIrqCb) + { + pstcRtcInternCb->pfnAlarmIrqCb = pstcRtcConfig->pstcIrqCb->pfnAlarmIrqCb; + pstcRtcInternCb->pfnTimerIrqCb = pstcRtcConfig->pstcIrqCb->pfnTimerIrqCb; + } + if(TRUE == pstcRtcConfig->bTouchNvic) + { + EnableNvic(RTC_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(RTC_IRQn,IrqLevel3,FALSE); + } + return enRet; +} +/** + ****************************************************************************** + ** \brief RTC计数ç¦æ­¢å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval Okç¦æ­¢è®¾ç½®æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Rtc_DeInit(void) +{ + EnableNvic(RTC_IRQn,IrqLevel3,FALSE); + Rtc_DisableFunc(RtcCount); + Rtc_DisableFunc(RtcAlarmEn); + Rtc_DisableFunc(Rtc_ComenEn); + Rtc_DisableFunc(Rtc1HzOutEn); + return Ok; +} +/** + ****************************************************************************** + ** \brief RTC中断处ç†å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Rtc_IRQHandler(void) +{ + stc_rtc_intern_cb_t* pstcRtcInternCb; + pstcRtcInternCb = RtcGetInternDataCb() ; + if(TRUE == M0P_RTC->CR1_f.ALMF) + { + M0P_RTC->CR1_f.ALMF = 0u; + if(NULL != pstcRtcInternCb->pfnAlarmIrqCb) + { + pstcRtcInternCb->pfnAlarmIrqCb(); + } + } + if(TRUE == M0P_RTC->CR1_f.PRDF) + { + M0P_RTC->CR1_f.PRDF = 0; + if(NULL != pstcRtcInternCb->pfnTimerIrqCb) + { + pstcRtcInternCb->pfnTimerIrqCb(); + } + } +} +//@} // RtcGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/spi.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/spi.c new file mode 100644 index 0000000000..8b9e8e6626 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/spi.c @@ -0,0 +1,526 @@ +/****************************************************************************** +* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with eaenCh copy of this software, whether used in part or whole, +* at all times. +*/ +/*****************************************************************************/ +/** \file spi.c + ** + ** SPI driver API. + ** @link Driver Group Some description @endlink + ** + ** - 2018-05-17 1.0 Devi First version for Device Driver Library of + ** Module. + ** + *****************************************************************************/ + +/****************************************************************************** + * Include files + *****************************************************************************/ +#include "spi.h" + +/** + ****************************************************************************** + ** \addtogroup SpiGroup + *****************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + *****************************************************************************/ + +#define IS_VALID_STAT(x) ( SpiIf == (x)||\ + SpiSserr == (x)||\ + SpiBusy == (x)||\ + SpiMdf == (x)||\ + SpiTxe == (x)||\ + SpiRxne == (x)) +#define IS_VALID_CH(x) ( Spi0 == (x)||\ + Spi1 == (x)) + + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable prototypes ('static') */ +/******************************************************************************/ +static func_ptr_t pfnSpi0Callback = NULL; ///< callback function pointer for SPI Irq +static func_ptr_t pfnSpi1Callback = NULL; ///< callback function pointer for SPI Irq +/** + ****************************************************************************** + ** \brief SPI 中断处ç†å‡½æ•° + ** + ** \param [in] enChé€šé“ + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Spi_IRQHandler(en_spi_channel_t enCh) +{ + if(Spi0 == enCh) + { + if(NULL != pfnSpi0Callback) + { + pfnSpi0Callback(); + } + } + else + { + if(NULL != pfnSpi1Callback) + { + pfnSpi1Callback(); + } + + } +} +/** + ****************************************************************************** + ** \brief SPI 请求状æ€èŽ·å– + ** + ** \param [in]enCh é€šé“ + ** + ** \retval è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +uint8_t Spi_GetState(en_spi_channel_t enCh) +{ + uint8_t u8State = 0; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + u8State = M0P_SPI0->STAT; + } + else + { + u8State = M0P_SPI1->STAT; + } + return u8State; +} +/** + ****************************************************************************** + ** \brief SPI 请求状æ€èŽ·å– + ** + ** \param [in]enCh 通é“， enStatus 获å–请求 + ** + ** \retval è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +boolean_t Spi_GetStatus(en_spi_channel_t enCh,en_spi_status_t enStatus) +{ + boolean_t bFlag = FALSE; + ASSERT(IS_VALID_CH(enCh)); + ASSERT(IS_VALID_STAT(enStatus)); + if(Spi0 == enCh) + { + switch (enStatus) + { + case SpiIf: + bFlag = M0P_SPI0->STAT_f.SPIF; + break; + case SpiSserr: + bFlag = M0P_SPI0->STAT_f.SSERR; + break; + case SpiMdf: + bFlag = M0P_SPI0->STAT_f.MDF; + break; + case SpiBusy: + bFlag = M0P_SPI0->STAT_f.BUSY; + break; + case SpiTxe: + bFlag = M0P_SPI0->STAT_f.TXE; + break; + case SpiRxne: + bFlag = M0P_SPI0->STAT_f.RXNE; + break; + default: + break; + } + } + else + { + switch (enStatus) + { + case SpiIf: + bFlag = M0P_SPI1->STAT_f.SPIF; + break; + case SpiSserr: + bFlag = M0P_SPI1->STAT_f.SSERR; + break; + case SpiMdf: + bFlag = M0P_SPI1->STAT_f.MDF; + break; + case SpiBusy: + bFlag = M0P_SPI1->STAT_f.BUSY; + break; + case SpiTxe: + bFlag = M0P_SPI1->STAT_f.TXE; + break; + case SpiRxne: + bFlag = M0P_SPI1->STAT_f.RXNE; + break; + default: + break; + } + } + return bFlag; +} +/** + ****************************************************************************** + ** \brief SPI中断清除 + ** + ** \param [in]enCh 通é“， enStatus 获å–请求 + ** + ** \retval è¯·æ±‚çŠ¶æ€ + ** + ******************************************************************************/ +en_result_t Spi_ClearStatus(en_spi_channel_t enCh) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->ICLR_f.INT_CLR = 0; + } + else + { + M0P_SPI1->ICLR_f.INT_CLR = 0; + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief SPI 功能使能ç¦æ­¢å‡½æ•° + ** + ** \param [in] enCh通é“，enFunc功能，bFlag 0/1使能或ç¦æ­¢ + ** + ** \retval Okåˆå§‹åŒ–æˆåŠŸ + ** \retval ErrorInvalidParameter åˆå§‹åŒ–错误 + ******************************************************************************/ +en_result_t Spi_FuncEn(en_spi_channel_t enCh,en_spi_func_t enFunc,boolean_t bFlag) +{ + en_result_t enRet = Error; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + switch(enFunc) + { + case SpiRxNeIe: + M0P_SPI0->CR2_f.RXNEIE = bFlag; + break; + case SpiTxEIe: + M0P_SPI0->CR2_f.TXEIE = bFlag; + break; + case SpiDmaTxEn: + M0P_SPI0->CR2_f.HDMA_TX = bFlag; + break; + case SpiDmaRxEn: + M0P_SPI0->CR2_f.HDMA_RX = bFlag; + break; + default: + return ErrorInvalidParameter; + } + } + else + { + switch(enFunc) + { + case SpiRxNeIe: + M0P_SPI1->CR2_f.RXNEIE = bFlag; + break; + case SpiTxEIe: + M0P_SPI1->CR2_f.TXEIE = bFlag; + break; + case SpiDmaTxEn: + M0P_SPI1->CR2_f.HDMA_TX = bFlag; + break; + case SpiDmaRxEn: + M0P_SPI1->CR2_f.HDMA_RX = bFlag; + break; + default: + return ErrorInvalidParameter; + } + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief SPI 总体åˆå§‹åŒ–函数 + ** + ** \param [in] + enChé€šé“ + pstcSpiConfigåˆå§‹åŒ–结构 + ** + ** \retval Okåˆå§‹åŒ–æˆåŠŸ + ** \retval ErrorInvalidParameter åˆå§‹åŒ–错误 + ******************************************************************************/ +en_result_t Spi_Init(en_spi_channel_t enCh,stc_spi_config_t *pstcSpiConfig) +{ + ASSERT(NULL != pstcSpiConfig); + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->CR = 0x00; + + M0P_SPI0->CR_f.MSTR = pstcSpiConfig->bMasterMode; + M0P_SPI0->CR_f.CPOL = pstcSpiConfig->bCPOL; + M0P_SPI0->CR_f.CPHA = pstcSpiConfig->bCPHA; + if(pstcSpiConfig->u8BaudRate > SpiClkDiv16) + { + M0P_SPI0->CR_f.SPR2 = 1; + } + M0P_SPI0->CR |= (pstcSpiConfig->u8BaudRate&0x03u); + + M0P_SPI0->STAT = 0x00; + + M0P_SPI0->CR_f.SPEN = TRUE; + if (TRUE == pstcSpiConfig->bIrqEn) + { + M0P_SPI0->CR2_f.INT_EN = 1; + EnableNvic(SPI0_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(SPI0_IRQn,IrqLevel3,FALSE); + } + if(NULL != pstcSpiConfig->pfnSpi0IrqCb) + { + pfnSpi0Callback = pstcSpiConfig->pfnSpi0IrqCb; + } + } + else + { + M0P_SPI1->CR = 0x00; + + M0P_SPI1->CR_f.MSTR = pstcSpiConfig->bMasterMode; + M0P_SPI1->CR_f.CPOL = pstcSpiConfig->bCPOL; + M0P_SPI1->CR_f.CPHA = pstcSpiConfig->bCPHA; + if(pstcSpiConfig->u8BaudRate > SpiClkDiv16) + { + M0P_SPI1->CR_f.SPR2 = 1; + } + M0P_SPI1->CR |= (pstcSpiConfig->u8BaudRate&0x03u); + + M0P_SPI1->STAT = 0x00; + + M0P_SPI1->CR_f.SPEN = TRUE; + if (TRUE == pstcSpiConfig->bIrqEn) + { + M0P_SPI1->CR2_f.INT_EN = 1; + EnableNvic(SPI1_IRQn,IrqLevel3,TRUE); + } + else + { + EnableNvic(SPI1_IRQn,IrqLevel3,FALSE); + } + if(NULL != pstcSpiConfig->pfnSpi1IrqCb) + { + pfnSpi1Callback = pstcSpiConfig->pfnSpi1IrqCb; + } + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI ç¦æ­¢å‡½æ•° + ** + ** \param [in] enChé€šé“ + ** + ** \retval Okç¦æ­¢è®¾ç½®æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Spi_DeInit(en_spi_channel_t enCh) +{ + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->DATA = 0x00; + M0P_SPI0->STAT = 0x00; + M0P_SPI0->CR = 0x00; + pfnSpi0Callback = NULL; + EnableNvic(SPI0_IRQn,IrqLevel3,FALSE); + } + else + { + M0P_SPI1->DATA = 0x00; + M0P_SPI1->STAT = 0x00; + M0P_SPI1->CR = 0x00; + pfnSpi1Callback = NULL; + EnableNvic(SPI1_IRQn,IrqLevel3,FALSE); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief SPI é…置主å‘é€çš„电平 + ** + ** \param [in] 高低电平 + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Spi_SetCS(en_spi_channel_t enCh,boolean_t bFlag) +{ + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + M0P_SPI0->SSN = bFlag; + } + else + { + M0P_SPI1->SSN = bFlag; + } +} +/** + ****************************************************************************** + ** \brief SPI å‘é€ä¸€å­—节函数 + ** + ** \param [in] enCh通é“，u8Dataå‘é€å­—节 + ** + ** \retval Okå‘é€æˆåŠŸ + ** + ******************************************************************************/ +en_result_t Spi_SendData(en_spi_channel_t enCh,uint8_t u8Data) +{ + uint32_t u32TimeOut; + ASSERT(IS_VALID_CH(enCh)); + u32TimeOut = 1000; + if(Spi0 == enCh) + { + while(--u32TimeOut) + { + if(TRUE == M0P_SPI0->STAT_f.TXE) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + M0P_SPI0->DATA = u8Data; + u32TimeOut = 1000; + while(--u32TimeOut) + { + if(TRUE == M0P_SPI0->STAT_f.RXNE) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + u8Data = M0P_SPI0->DATA; + } + else + { + while(--u32TimeOut) + { + if(TRUE == M0P_SPI1->STAT_f.TXE) + + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + M0P_SPI1->DATA = u8Data; + u32TimeOut = 1000; + while(--u32TimeOut) + { + if(TRUE == M0P_SPI1->STAT_f.RXNE) + { + break; + } + } + if(u32TimeOut == 0) + { + return ErrorTimeout; + } + u8Data = M0P_SPI1->DATA; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief SPI 接收一字节函数 + ** + ** \param [in] enChæŽ¥æ”¶é€šé“ + ** + ** \retval æŽ¥æ”¶ä¸€å­—èŠ‚æ•°æ® + ** + ******************************************************************************/ +uint8_t Spi_ReceiveData(en_spi_channel_t enCh,boolean_t bMasterOrSlave) +{ + uint8_t temp; + ASSERT(IS_VALID_CH(enCh)); + if(Spi0 == enCh) + { + if(1 == bMasterOrSlave) + { + M0P_SPI0->DATA = 0x00; + } + while(0 == M0P_SPI0->STAT_f.RXNE){;} + temp = M0P_SPI0->DATA; + } + else + { + if(1 == bMasterOrSlave) + { + M0P_SPI1->DATA = 0x00; + } + while(0 == M0P_SPI1->STAT_f.RXNE){;} + temp = M0P_SPI1->DATA; + } + return temp; +} + +//@} // SpiGroup +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/sysctrl.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/sysctrl.c new file mode 100644 index 0000000000..c6f02cce9d --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/sysctrl.c @@ -0,0 +1,776 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file sysctrl.c + ** + ** Common API of sysctrl. + ** @link SysctrlGroup Some description @endlink + ** + ** - 2018-04-22 Lux + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "sysctrl.h" + +/** + ******************************************************************************* + ** \addtogroup SysctrlGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CLK_TIMEOUT (1000000u) + +#define IS_VALID_SRC(x) ( ClkRCH == (x)||\ + ClkXTH == (x)||\ + ClkRCL == (x)||\ + ClkXTL == (x) ) + + +#define IS_VALID_FUNC(x) ( ClkFuncWkupRCH == (x)||\ + ClkFuncXTHEn == (x)||\ + ClkFuncXTLEn == (x)||\ + ClkFuncXTLAWSON == (x)||\ + ClkFuncFaultEn == (x)||\ + ClkFuncRtcLPWEn == (x)||\ + ClkFuncLockUpEn == (x)||\ + ClkFuncRstPinIOEn == (x)||\ + ClkFuncSwdPinIOEn == (x) ) + +#define RCH_CR_TRIM_24M_VAL (*((volatile uint16_t*) (0x00100C00ul))) +#define RCH_CR_TRIM_22_12M_VAL (*((volatile uint16_t*) (0x00100C02ul))) +#define RCH_CR_TRIM_16M_VAL (*((volatile uint16_t*) (0x00100C04ul))) +#define RCH_CR_TRIM_8M_VAL (*((volatile uint16_t*) (0x00100C06ul))) +#define RCH_CR_TRIM_4M_VAL (*((volatile uint16_t*) (0x00100C08ul))) + +#define RCL_CR_TRIM_38400_VAL (*((volatile uint16_t*) (0x00100C20ul))) +#define RCL_CR_TRIM_32768_VAL (*((volatile uint16_t*) (0x00100C22ul))) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern uint32_t SystemCoreClock; +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief SYSCTRL0\SYSCTRL1寄存器æ“ä½œè§£é” + ** + ** \retval None + ******************************************************************************/ +static void _SysctrlUnlock(void) +{ + M0P_SYSCTRL->SYSCTRL2 = 0x5A5A; + M0P_SYSCTRL->SYSCTRL2 = 0xA5A5; +} + +/** + ******************************************************************************* + ** \brief 系统时钟æºä½¿èƒ½ + ** \param [in] enSource ç›®æ ‡æ—¶é’Ÿæº + ** \param [in] bFlag 使能1-å¼€/0-å…³ + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkSourceEnable(en_sysctrl_clk_source_t enSource, boolean_t bFlag) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + bFlag = !!bFlag; + + switch (enSource) + { + case SysctrlClkRCH: + M0P_SYSCTRL->SYSCTRL0_f.RCH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTH: + M0P_GPIO->PDADS_f.PD00 = 1; + M0P_GPIO->PDADS_f.PD01 = 1; + M0P_SYSCTRL->SYSCTRL0_f.XTH_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTH_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkRCL: + M0P_SYSCTRL->SYSCTRL0_f.RCL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->RCL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkXTL: + M0P_GPIO->PCADS_f.PC14 = 1; + M0P_GPIO->PCADS_f.PC15 = 1; + M0P_SYSCTRL->SYSCTRL0_f.XTL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->XTL_CR_f.STABLE)) + { + ; + } + break; + + case SysctrlClkPLL: + M0P_SYSCTRL->SYSCTRL0_f.PLL_EN = bFlag; + while(bFlag && (1 != M0P_SYSCTRL->PLL_CR_f.STABLE)) + { + ; + } + break; + + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速晶振驱动é…ç½® + ** \param [in] enFreq 外部高速晶振频率范围选择 + ** \param [in] enDriver 外部高速晶振驱动能力选择 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_XTHDriverConfig(en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部低速晶振驱动é…ç½® + ** \param [in] enFreq 外部低速晶振频率范围选择 + ** \param [in] enDriver 外部低速晶振驱动能力选择 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_XTLDriverConfig(en_sysctrl_xtl_amp_t enAmp, en_sysctrl_xtal_driver_t enDriver) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTL_CR_f.AMP_SEL = enAmp; + M0P_SYSCTRL->XTL_CR_f.DRIVER = enDriver; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速时钟稳定周期é…ç½® + ** \param [in] enCycle 外部高速时钟稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHStableTime(en_sysctrl_xth_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTH_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部低速时钟稳定周期é…ç½® + ** \param [in] enCycle 内部低速时钟稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLStableTime(en_sysctrl_rcl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->RCL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部低速时钟稳定周期é…ç½® + ** \param [in] enCycle 外部低速时钟稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetXTLStableTime(en_sysctrl_xtl_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->XTL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL稳定周期é…ç½® + ** \param [in] enCycle PLL稳定周期设置 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPLLStableTime(en_sysctrl_pll_cycle_t enCycle) +{ + en_result_t enRet = Ok; + M0P_SYSCTRL->PLL_CR_f.STARTUP = enCycle; + return enRet; +} + +/** + ******************************************************************************* + ** \brief 时钟æºåˆ‡æ¢ï¼Œè¯¥å‡½æ•°æ‰§è¡ŒåŽä¼šå¼€å¯æ–°æ—¶é’Ÿæº + ** \note 选择时钟æºä¹‹å‰ï¼Œéœ€æ ¹æ®éœ€è¦é…置目标时钟æºçš„频率/驱动å‚æ•°/使能时钟æºç­‰ + ** \param [in] enSource æ–°æ—¶é’Ÿæº + ** + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SysClkSwitch(en_sysctrl_clk_source_t enSource) +{ + en_result_t enRet = Ok; + + en_sysctrl_clk_source_t ClkNew = enSource; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.CLK_SW5_SEL = ClkNew; + + //æ›´æ–°Core时钟（HCLK） + SystemCoreClockUpdate(); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 获得系统时钟（HCLK）频率值 + ** \retval uint32_t HCLK频率值 + ** + ******************************************************************************/ +uint32_t Sysctrl_GetHClkFreq(void) +{ + uint32_t u32Val = 0; + const uint32_t u32hcr_tbl[] = { 4000000, 8000000, 16000000, 22120000, 24000000}; + const uint16_t u32lcr_tbl[] = { 32768, 38400}; + en_sysctrl_clk_source_t enSrc; + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + u16Trim[0] = RCL_CR_TRIM_38400_VAL; + + //获å–当å‰ç³»ç»Ÿæ—¶é’Ÿ + enSrc = (en_sysctrl_clk_source_t)(M0P_SYSCTRL->SYSCTRL0_f.CLK_SW5_SEL); + + switch (enSrc) + { + case SysctrlClkRCH: + { + + if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[4])) + { + u32Val = u32hcr_tbl[4]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[3])) + { + u32Val = u32hcr_tbl[3]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[2])) + { + u32Val = u32hcr_tbl[2]; + } + else if((M0P_SYSCTRL->RCH_CR_f.TRIM) == (u16Trim[1])) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + break; + case SysctrlClkXTH: + u32Val = SYSTEM_XTH; + break; + case SysctrlClkRCL: + { + if(u16Trim[0] == (M0P_SYSCTRL->RCL_CR_f.TRIM)) + { + u32Val = u32lcr_tbl[1]; + } + else + { + u32Val = u32lcr_tbl[0]; + } + } + break; + case SysctrlClkXTL: + u32Val = SYSTEM_XTL; + break; + case SysctrlClkPLL: + { + if (SysctrlPllRch == M0P_SYSCTRL->PLL_CR_f.REFSEL) + { + if(u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[4]; + } + else if(u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[3]; + } + else if(u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[2]; + } + else if(u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) + { + u32Val = u32hcr_tbl[1]; + } + else + { + u32Val = u32hcr_tbl[0]; + } + } + else + { + u32Val = SYSTEM_XTH; + } + + u32Val = (u32Val * M0P_SYSCTRL->PLL_CR_f.DIVN); + } + break; + default: + u32Val = 0u; + break; + } + + u32Val = (u32Val >> M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS); + + return u32Val; +} + +/** + ******************************************************************************* + ** \brief 获得外设时钟（PCLK）频率值 + ** \retval uint32_t PCLK频率值(Hz) + ** + ******************************************************************************/ +uint32_t Sysctrl_GetPClkFreq(void) +{ + uint32_t u32Val = 0; + + u32Val = Sysctrl_GetHClkFreq(); + u32Val = (u32Val >> (M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS)); + + return u32Val; +} + + +/** + ******************************************************************************* + ** \brief 时钟åˆå§‹åŒ–函数 + ** \param [in] pstcCfg åˆå§‹åŒ–é…ç½®å‚æ•° + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkInit(stc_sysctrl_clk_config_t *pstcCfg) +{ + en_result_t enRet = Ok; + + //系统时钟å‚æ•°é…ç½® + switch(pstcCfg->enClkSrc) + { + case SysctrlClkRCH: + + break; + case SysctrlClkXTH: + Sysctrl_XTHDriverConfig(SysctrlXtalDriver3); + Sysctrl_SetXTHStableTime(SysctrlXthStableCycle16384); + break; + case SysctrlClkRCL: + Sysctrl_SetRCLStableTime(SysctrlRclStableCycle256); + break; + case SysctrlClkXTL: + Sysctrl_XTLDriverConfig(SysctrlXtlAmp3, SysctrlXtalDriver3); + Sysctrl_SetXTLStableTime(SysctrlXtlStableCycle16384); + break; + case SysctrlClkPLL: + Sysctrl_SetPLLStableTime(SysctrlPllStableCycle16384); + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + //时钟æºä½¿èƒ½ + Sysctrl_ClkSourceEnable(pstcCfg->enClkSrc, TRUE); + + //时钟æºåˆ‡æ¢ + Sysctrl_SysClkSwitch(pstcCfg->enClkSrc); + + //时钟分频设置 + Sysctrl_SetHCLKDiv(pstcCfg->enHClkDiv); + Sysctrl_SetPCLKDiv(pstcCfg->enPClkDiv); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 时钟去åˆå§‹åŒ–函数 + ** \param [in] + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_ClkDeInit(void) +{ + en_result_t enRet = Ok; + + //é…ç½®RCH为内部4Hz + Sysctrl_SetRCHTrim(SysctrlRchFreq4MHz); + + //时钟æºä½¿èƒ½ + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); + + //时钟æºåˆ‡æ¢ + Sysctrl_SysClkSwitch(SysctrlClkRCH); + + //其它时钟æºä½¿èƒ½å…³é—­ + Sysctrl_ClkSourceEnable(SysctrlClkXTH, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkRCL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkXTL, FALSE); + Sysctrl_ClkSourceEnable(SysctrlClkPLL, FALSE); + + //时钟分频设置 + Sysctrl_SetHCLKDiv(SysctrlHclkDiv1); + Sysctrl_SetPCLKDiv(SysctrlPclkDiv1); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部高速时钟频率TRIM值加载 + ** \param [in] enRCHFreq 设定的RCH目标频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败或时钟未稳定 + ******************************************************************************/ +en_result_t Sysctrl_SetRCHTrim(en_sysctrl_rch_freq_t enRCHFreq) +{ + en_result_t enRet = Ok; + + //加载RCH Trim值 + switch (enRCHFreq) + { + case SysctrlRchFreq4MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_4M_VAL; + break; + case SysctrlRchFreq8MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_8M_VAL; + break; + case SysctrlRchFreq16MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_16M_VAL; + break; + case SysctrlRchFreq22_12MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_22_12M_VAL; + break; + case SysctrlRchFreq24MHz: + M0P_SYSCTRL->RCH_CR_f.TRIM = RCH_CR_TRIM_24M_VAL; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外部高速时钟频率范围设定 + ** \param [in] enXTHFreq 设定的频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败或时钟未稳定 + ******************************************************************************/ +en_result_t Sysctrl_SetXTHFreq(en_sysctrl_xth_freq_t enXTHFreq) +{ + en_result_t enRet = Ok; + + M0P_SYSCTRL->XTH_CR_f.XTH_FSEL = enXTHFreq; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief PLL时钟é…ç½® + ** \param [in] pstcPLLCfg PLLé…置结构体指针 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败或å‚数值ä¸åŒ¹é… + ******************************************************************************/ +en_result_t Sysctrl_SetPLLFreq(stc_sysctrl_pll_config_t *pstcPLLCfg) +{ + en_result_t enRet = Ok; + + uint16_t u16Trim[5] = {0}; + u16Trim[4] = RCH_CR_TRIM_24M_VAL; + u16Trim[3] = RCH_CR_TRIM_22_12M_VAL; + u16Trim[2] = RCH_CR_TRIM_16M_VAL; + u16Trim[1] = RCH_CR_TRIM_8M_VAL; + + ////PLL最高时钟ä¸èƒ½è¶…过48MHz + //RCH作为PLL输入 + if (SysctrlPllRch == pstcPLLCfg->enPllClkSrc) + { + if( ((u16Trim[4] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[3] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 2)) || + ((u16Trim[2] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 3)) || + ((u16Trim[1] == M0P_SYSCTRL->RCH_CR_f.TRIM) && (pstcPLLCfg->enPllMul > 6))) + { + return ErrorInvalidMode; + } + } + else //XTH作为PLL输入 + { + if ((SYSTEM_XTH * pstcPLLCfg->enPllMul) > 48*1000*1000) + { + return ErrorInvalidMode; + } + } + + M0P_SYSCTRL->PLL_CR_f.FRSEL = pstcPLLCfg->enInFreq; + M0P_SYSCTRL->PLL_CR_f.FOSC = pstcPLLCfg->enOutFreq; + M0P_SYSCTRL->PLL_CR_f.DIVN = pstcPLLCfg->enPllMul; + M0P_SYSCTRL->PLL_CR_f.REFSEL = pstcPLLCfg->enPllClkSrc; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 内部低速时钟频率TRIM值加载 + ** \param [in] enRCLFreq 设定的RCL目标频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRCLTrim(en_sysctrl_rcl_freq_t enRCLFreq) +{ + en_result_t enRet = Ok; + + switch (enRCLFreq) + { + case SysctrlRclFreq32768: + M0P_SYSCTRL->RCL_CR_f.TRIM = RCL_CR_TRIM_32768_VAL; + break; + case SysctrlRclFreq38400: + M0P_SYSCTRL->RCL_CR_f.TRIM = RCL_CR_TRIM_38400_VAL; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 系统时钟（HCLK）分频设定 + ** \param [in] enHCLKDiv 分频设定值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetHCLKDiv(en_sysctrl_hclk_div_t enHCLKDiv) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.HCLK_PRS = enHCLKDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 外设时钟（PCLK）分频设定 + ** \param [in] enPCLKDiv 分频设定值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPCLKDiv(en_sysctrl_pclk_div_t enPCLKDiv) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL0_f.PCLK_PRS = enPCLKDiv; + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 设置外设时钟门控开关 + ** \param [in] enPeripheral 目标外设 + ** \param [in] bFlag 使能开关 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral, boolean_t bFlag) +{ + en_result_t enRet = Ok; + + bFlag = !!bFlag; + + setBit(&(M0P_SYSCTRL->PERI_CLKEN), enPeripheral, bFlag); + + return enRet; +} + +/** + ******************************************************************************* + ** \brief èŽ·å¾—å¤–è®¾æ—¶é’Ÿé—¨æŽ§å¼€å…³çŠ¶æ€ + ** \param [in] enPeripheral 目标外设 + ** \retval TRUE å¼€ + ** FALSE å…³ + ******************************************************************************/ +boolean_t Sysctrl_GetPeripheralGate(en_sysctrl_peripheral_gate_t enPeripheral) +{ + return getBit(&(M0P_SYSCTRL->PERI_CLKEN), enPeripheral); +} + +/** + ******************************************************************************* + ** \brief 系统功能设定 + ** \param [in] enFunc 系统功能枚举类型 + ** \param [in] bFlag 1-å¼€/0-å…³ + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetFunc(en_sysctrl_func_t enFunc, boolean_t bFlag) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + bFlag = !!bFlag; + + switch (enFunc) + { + case SysctrlWkupByRCHEn: + M0P_SYSCTRL->SYSCTRL0_f.WAKEUP_BYRCH = bFlag; + break; + case SysctrlEXTHEn: + M0P_SYSCTRL->SYSCTRL1_f.EXTH_EN = bFlag; + break; + case SysctrlEXTLEn: + M0P_SYSCTRL->SYSCTRL1_f.EXTL_EN = bFlag; + break; + case SysctrlXTLAlwaysOnEn: + M0P_SYSCTRL->SYSCTRL1_f.XTL_ALWAYS_ON = bFlag; + break; + case SysctrlClkFuncRTCLpmEn: + M0P_SYSCTRL->SYSCTRL1_f.RTC_LPW = bFlag; + break; + case SysctrlCMLockUpEn: + M0P_SYSCTRL->SYSCTRL1_f.LOCKUP_EN = bFlag; + break; + case SysctrlSWDUseIOEn: + M0P_SYSCTRL->SYSCTRL1_f.SWD_USE_IO = bFlag; + break; + default: + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + ******************************************************************************* + ** \brief 设定RTC校准时钟频率 + ** \param [in] enRtcAdj 校准频率值 + ** \retval Ok 设定æˆåŠŸ + ** 其他 设定失败 + ******************************************************************************/ +en_result_t Sysctrl_SetRTCAdjustClkFreq(en_sysctrl_rtc_adjust_t enRtcAdj) +{ + en_result_t enRet = Ok; + + _SysctrlUnlock(); + M0P_SYSCTRL->SYSCTRL1_f.RTC_FREQ_ADJUST = enRtcAdj; + + return enRet; +} + +//@} // SysctrlGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer0.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer0.c new file mode 100644 index 0000000000..7210d18116 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer0.c @@ -0,0 +1,1390 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file timer3.c + ** + ** Common API of base timer. + ** @link BT Tiemr3 Group Some description @endlink + ** + ** - 2018-04-18 First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "timer0.h" +/** + ******************************************************************************* + ** \addtogroup Tim0Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define IS_VALID_TIM(x) (TIM0 == (x) || TIM1 == (x) || TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnTim0Callback = NULL; + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志获å–(模å¼0/1/23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Tim0_GetIntFlag(en_tim0_irq_type_t enTim0Irq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + + u32Val = M0P_TIM0_MODE23->IFR; + bRetVal = (u32Val>>enTim0Irq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志清除(模å¼0/1/23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_ClearIntFlag(en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->ICLR = ~(1u<ICLR_f.BIF = 0; + M0P_TIM0_MODE23->ICLR_f.CA0E = 0; + M0P_TIM0_MODE23->ICLR_f.CA0F = 0; + M0P_TIM0_MODE23->ICLR_f.CB0E = 0; + M0P_TIM0_MODE23->ICLR_f.CB0F = 0; + M0P_TIM0_MODE23->ICLR_f.TIF = 0; + M0P_TIM0_MODE23->ICLR_f.UIF = 0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode0_EnableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode0_DisableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼1) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode1_EnableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE1->M1CR_f.UIE = TRUE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE1->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼1) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode1_DisableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE1->M1CR_f.UIE = FALSE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE1->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode23_EnableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE23->M23CR_f.UIE = TRUE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEA = TRUE; + break; + case Tim0CB0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEB = TRUE; + break; +// case Tim0CA1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEA = TRUE; +// break; +// case Tim0CB1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEB = TRUE; +// break; +// case Tim0CA2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEA = TRUE; +// break; +// case Tim0CB2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEB = TRUE; +// break; + case Tim0BkIrq: + M0P_TIM0_MODE23->M23CR_f.BIE = TRUE; + break; + case Tim0TrigIrq: + M0P_TIM0_MODE23->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enTim0Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode23_DisableIrq (en_tim0_irq_type_t enTim0Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim0Irq) + { + case Tim0UevIrq: + M0P_TIM0_MODE23->M23CR_f.UIE = FALSE; + break; + case Tim0CA0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEA = FALSE; + break; + case Tim0CB0Irq: + M0P_TIM0_MODE23->CRCH0_f.CIEB = FALSE; + break; +// case Tim0CA1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEA = FALSE; +// break; +// case Tim0CB1Irq: +// M0P_TIM0_MODE23->CRCH1_f.CIEB = FALSE; +// break; +// case Tim0CA2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEA = FALSE; +// break; +// case Tim0CB2Irq: +// M0P_TIM0_MODE23->CRCH2_f.CIEB = FALSE; +// break; + case Tim0BkIrq: + M0P_TIM0_MODE23->M23CR_f.BIE = FALSE; + break; + case Tim0TrigIrq: + M0P_TIM0_MODE23->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param Timer0通é“选择(0 - TIM0) + ** + ** \retval NULL + *****************************************************************************/ +void Tim0_IRQHandler(uint8_t u8Param) +{ + switch (u8Param) + { + case 0: + if(NULL != pfnTim0Callback) + { + pfnTim0Callback(); + } + break; + default: + ; + break; + } +} + + + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼0) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode0_Init(stc_tim0_mode0_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM0_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM0_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM0_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM0_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 翻转输出使能/ç¦æ­¢è®¾å®š(模å¼0) + ** + ** + ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:ç¦æ­¢ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_EnTOG_Output(boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data CNT 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim0_M0_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM0_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u32Data 32ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M0_Cnt32Set(uint32_t u32Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Tim0_M0_Cnt32Get(void) +{ + uint32_t u32CntData = 0; + + u32CntData = M0P_TIM0_MODE0->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer0 åˆå§‹åŒ–é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode1_Init(stc_tim0_mode1_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->M1CR_f.MODE = pstcConfig->enWorkMode; +// M0P_TIM0_MODE0->M1CR_f.PRS = pstcConfig->enPRS; +// M0P_TIM0_MODE0->M1CR_f.CT = pstcConfig->enCT; +// M0P_TIM0_MODE0->M1CR_f.ONESHOT = pstcConfig->enOneShot; +// +// pfnTim0Callback = pstcConfig->pfnTim0Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC 输入é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Input_Config(stc_tim0_pwc_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->MSCR_f.TS = pstcConfig->enTsSel; +// M0P_TIM0_MODE0->MSCR_f.IA0S = pstcConfig->enIA0Sel; +// M0P_TIM0_MODE0->MSCR_f.IB0S = pstcConfig->enIB0Sel; +// M0P_TIM0_MODE0->FLTR_f.ETP = pstcConfig->enETRPhase; +// M0P_TIM0_MODE0->FLTR_f.FLTET = pstcConfig->enFltETR; +// M0P_TIM0_MODE0->FLTR_f.FLTA0 = pstcConfig->enFltIA0; +// M0P_TIM0_MODE0->FLTR_f.FLTB0 = pstcConfig->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹©(模å¼1) + ** + ** + ** \param [in] enEdgeSel pwc测é‡èµ·å§‹ç»ˆæ­¢ç”µå¹³ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_PWC_Edge_Sel(en_tim0_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + +// switch (enEdgeSel) +// { +// case 0: ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 0; //上å‡æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 0; //上å‡æ²¿ +// break; +// case 1: ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 1; //下é™æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 0; //上å‡æ²¿ +// break; +// case 2: ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 0; //上å‡æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 1; //下é™æ²¿ +// break; +// case 3: ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) +// M0P_TIM0_MODE0->M1CR_f.EDG1ST = 1; //下é™æ²¿ +// M0P_TIM0_MODE0->M1CR_f.EDG2ND = 1; //下é™æ²¿ +// break; +// default: +// ; +// break; +// } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Run(void) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Stop(void) +{ + en_result_t enResult = Ok; + +// M0P_TIM0_MODE0->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼1) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M1_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim0_M1_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM0_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 脉冲宽度测é‡ç»“果数值获å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits脉冲宽度测é‡ç»“æžœ + *****************************************************************************/ +uint16_t Tim0_M1_PWC_CapValueGet(void) +{ + uint16_t u16CapData = 0; + +// u16CapData = M0P_TIM0_MODE0->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_Mode23_Init(stc_tim0_mode23_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM0_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM0_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM0_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM0_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM0_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM0_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM0_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim0Callback = pstcConfig->pfnTim0Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM输出使能(模å¼23) + ** + ** + ** \param [in] bEnOutput PWM输出使能/ç¦æ­¢è®¾å®š + ** \param [in] bEnAutoOutput PWM自动输出使能/ç¦æ­¢è®¾å®š + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->DTR_f.MOE = bEnOutput; + M0P_TIM0_MODE23->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** \param [in] bArrBufEn ARRé‡è½½ç¼“存使能TRUE/ç¦æ­¢FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->ARR_f.ARR = u16Data; + M0P_TIM0_MODE23->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim0_M23_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM0_MODE23->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB设置(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** \param [in] u16Data CCRxA/CCRxB 16ä½åˆå§‹å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_CCR_Set(en_tim0_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if(Tim0CCR0A == enCCRSel) + { + M0P_TIM0_MODE23->CCR0A_f.CCR0A = u16Data; + } + else if(Tim0CCR0B == enCCRSel) + { + M0P_TIM0_MODE23->CCR0B_f.CCR0B = u16Data; + } +// else if(Tim0CCR1A == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR1A_f.CCR1A = u16Data; +// } +// else if(Tim0CCR1B == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR1B_f.CCR1B = u16Data; +// } +// else if(Tim0CCR2A == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR2A_f.CCR2A = u16Data; +// } +// else if(Tim0CCR2B == enCCRSel) +// { +// M0P_TIM0_MODE23->CCR2B_f.CCR2B = u16Data; +// } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB读å–(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** + ** \retval 16bitsCCRxA/CCRxBæ•èŽ·å€¼ + *****************************************************************************/ +uint16_t Tim0_M23_CCR_Get(en_tim0_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + + if(Tim0CCR0A == enCCRSel) + { + u16Data = M0P_TIM0_MODE23->CCR0A_f.CCR0A; + } + else if(Tim0CCR0B == enCCRSel) + { + u16Data = M0P_TIM0_MODE23->CCR0B_f.CCR0B; + } +// else if(Tim0CCR1A == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR1A_f.CCR1A; +// } +// else if(Tim0CCR1B == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR1B_f.CCR1B; +// } +// else if(Tim0CCR2A == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR2A_f.CCR2A; +// } +// else if(Tim0CCR2B == enCCRSel) +// { +// u16Data = M0P_TIM0_MODE23->CCR2B_f.CCR2B; +// } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_GateFuncSel(stc_tim0_m23_gate_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.CSG = pstcConfig->enGateFuncSel; + M0P_TIM0_MODE23->M23CR_f.CRG = pstcConfig->bGateRiseCap; + M0P_TIM0_MODE23->M23CR_f.CFG = pstcConfig->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 主从模å¼é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_MasterSlave_Set(stc_tim0_m23_master_slave_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->MSCR_f.MSM = pstcConfig->enMasterSlaveSel; + M0P_TIM0_MODE23->MSCR_f.MMS = pstcConfig->enMasterSrc; + M0P_TIM0_MODE23->MSCR_f.SMS = pstcConfig->enSlaveModeSel; + M0P_TIM0_MODE23->MSCR_f.TS = pstcConfig->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB比较通é“控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_PortOutput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_compare_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim0Chx) + { + case Tim0CH0: + M0P_TIM0_MODE23->CRCH0_f.CSA = 0; + M0P_TIM0_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxACmpCtrl; + M0P_TIM0_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + M0P_TIM0_MODE23->CRCH0_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM0_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM0_MODE23->CRCH0_f.CSB = 0; + M0P_TIM0_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM0_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + M0P_TIM0_MODE23->CRCH0_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM0_MODE23->CRCH0_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; +// case Tim0CH1: +// M0P_TIM0_MODE23->CRCH1_f.CSA = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxACmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; +// M0P_TIM0_MODE23->CRCH1_f.BUFEA = pstcConfig->bCHxACmpBufEn; +// M0P_TIM0_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; +// +// M0P_TIM0_MODE23->CRCH1_f.CSB = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBCmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; +// M0P_TIM0_MODE23->CRCH1_f.BUFEB = pstcConfig->bCHxBCmpBufEn; +// M0P_TIM0_MODE23->CRCH1_f.CISB = pstcConfig->enCHxBCmpIntSel; +// break; +// case Tim0CH2: +// M0P_TIM0_MODE23->CRCH2_f.CSA = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxACmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; +// M0P_TIM0_MODE23->CRCH2_f.BUFEA = pstcConfig->bCHxACmpBufEn; +// M0P_TIM0_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; +// +// M0P_TIM0_MODE23->CRCH2_f.CSB = 0; +// M0P_TIM0_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBCmpCtrl; +// M0P_TIM0_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; +// M0P_TIM0_MODE23->CRCH2_f.BUFEB = pstcConfig->bCHxBCmpBufEn; +// M0P_TIM0_MODE23->CRCH2_f.CISB = pstcConfig->enCHxBCmpIntSel; +// break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_PortInput_Config(en_tim0_channel_t enTim0Chx, stc_tim0_m23_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim0Chx) + { + case Tim0CH0: + M0P_TIM0_MODE23->CRCH0_f.CSA = 1; + M0P_TIM0_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM0_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxAInFlt; + M0P_TIM0_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + + M0P_TIM0_MODE23->CRCH0_f.CSB = 1; + M0P_TIM0_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM0_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBInFlt; + M0P_TIM0_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + break; +// case Tim0CH1: +// M0P_TIM0_MODE23->CRCH1_f.CSA = 1; +// M0P_TIM0_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxAInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; +// +// M0P_TIM0_MODE23->CRCH1_f.CSB = 1; +// M0P_TIM0_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; +// break; +// case Tim0CH2: +// M0P_TIM0_MODE23->CRCH2_f.CSA = 1; +// M0P_TIM0_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxAInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; +// +// M0P_TIM0_MODE23->CRCH2_f.CSB = 1; +// M0P_TIM0_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; +// M0P_TIM0_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBInFlt; +// M0P_TIM0_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; +// break; + default: + enResult = Error; + break; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 ERT输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_ETRInput_Config(stc_tim0_m23_etr_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->FLTR_f.ETP = pstcConfig->enETRPolarity; + M0P_TIM0_MODE23->FLTR_f.FLTET = pstcConfig->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 刹车BK输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_BrakeInput_Config(stc_tim0_m23_bk_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->DTR_f.BKE = pstcConfig->bEnBrake; + M0P_TIM0_MODE23->DTR_f.VC0E = pstcConfig->bEnVC0Brake; + M0P_TIM0_MODE23->DTR_f.VC1E = pstcConfig->bEnVC1Brake; + M0P_TIM0_MODE23->DTR_f.SAFEEN = pstcConfig->bEnSafetyBk; + M0P_TIM0_MODE23->DTR_f.BKSEL = pstcConfig->bEnBKSync; + M0P_TIM0_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enBkCH0AStat; + M0P_TIM0_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enBkCH0BStat; +// M0P_TIM0_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enBkCH1AStat; +// M0P_TIM0_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enBkCH1BStat; +// M0P_TIM0_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enBkCH2AStat; +// M0P_TIM0_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enBkCH2BStat; + M0P_TIM0_MODE23->FLTR_f.BKP = pstcConfig->enBrakePolarity; + M0P_TIM0_MODE23->FLTR_f.FLTBK = pstcConfig->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 触å‘ADC控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_TrigADC_Config(stc_tim0_m23_adc_trig_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->ADTR_f.ADTE = pstcConfig->bEnTrigADC; + M0P_TIM0_MODE23->ADTR_f.UEVE = pstcConfig->bEnUevTrigADC; + M0P_TIM0_MODE23->ADTR_f.CMA0E = pstcConfig->bEnCH0ACmpTrigADC; + M0P_TIM0_MODE23->ADTR_f.CMB0E = pstcConfig->bEnCH0BCmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMA1E = pstcConfig->bEnCH1ACmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMB1E = pstcConfig->bEnCH1BCmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMA2E = pstcConfig->bEnCH2ACmpTrigADC; +// M0P_TIM0_MODE23->ADTR_f.CMB2E = pstcConfig->bEnCH2BCmpTrigADC; + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 死区功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_DT_Config(stc_tim0_m23_dt_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->DTR_f.DTEN = pstcConfig->bEnDeadTime; + M0P_TIM0_MODE23->DTR_f.DTR = pstcConfig->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 é‡å¤å‘¨æœŸè®¾ç½®(模å¼23) + ** + ** + ** \param [in] u8ValidPeriod é‡å¤å‘¨æœŸå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_SetValidPeriod(uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 OCREF清除功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_OCRefClr(stc_tim0_m23_OCREF_Clr_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.OCCS = pstcConfig->enOCRefClrSrcSel; + M0P_TIM0_MODE23->M23CR_f.OCCE = pstcConfig->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 使能DMA传输(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnDMA(stc_tim0_m23_trig_dma_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.UDE = pstcConfig->bUevTrigDMA; + M0P_TIM0_MODE23->M23CR_f.TDE = pstcConfig->bTITrigDMA; + M0P_TIM0_MODE23->CRCH0_f.CDEA = pstcConfig->bCmpA0TrigDMA; + M0P_TIM0_MODE23->CRCH0_f.CDEB = pstcConfig->bCmpB0TrigDMA; +// M0P_TIM0_MODE23->CRCH1_f.CDEA = pstcConfig->bCmpA1TrigDMA; +// M0P_TIM0_MODE23->CRCH1_f.CDEB = pstcConfig->bCmpB1TrigDMA; +// M0P_TIM0_MODE23->CRCH2_f.CDEA = pstcConfig->bCmpA2TrigDMA; +// M0P_TIM0_MODE23->CRCH2_f.CDEB = pstcConfig->bCmpB2TrigDMA; + M0P_TIM0_MODE23->MSCR_f.CCDS = pstcConfig->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较A软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwTrigCapCmpA(en_tim0_channel_t enTim0Chx) +{ + en_result_t enResult = Ok; + if(Tim0CH0 == enTim0Chx) + { + M0P_TIM0_MODE23->CRCH0_f.CCGA = TRUE; + } +// else if(Tim0CH1 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH1_f.CCGA = TRUE; +// } +// else if(Tim0CH2 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH2_f.CCGA = TRUE; +// } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较B软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim0Chx Timer3通é“(Tim0CH0, Tim0CH1, Tim0CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwTrigCapCmpB(en_tim0_channel_t enTim0Chx) +{ + en_result_t enResult = Ok; + if(Tim0CH0 == enTim0Chx) + { + M0P_TIM0_MODE23->CRCH0_f.CCGB = TRUE; + } +// else if(Tim0CH1 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH1_f.CCGB = TRUE; +// } +// else if(Tim0CH2 == enTim0Chx) +// { +// M0P_TIM0_MODE23->CRCH2_f.CCGB = TRUE; +// } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件更新使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwUev(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件触å‘使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwTrig(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件刹车使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim0_M23_EnSwBk(void) +{ + en_result_t enResult = Ok; + + M0P_TIM0_MODE23->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // Tim0Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer3.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer3.c new file mode 100644 index 0000000000..983062704c --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/timer3.c @@ -0,0 +1,1399 @@ +/****************************************************************************** +*Copyright(C)2018, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file timer3.c + ** + ** Common API of base timer. + ** @link BT Tiemr3 Group Some description @endlink + ** + ** - 2018-04-18 First Version + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "timer3.h" +/** + ******************************************************************************* + ** \addtogroup Tim3Group + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +//#define IS_VALID_TIM(x) (TIM0 == (x) || TIM1 == (x) || TIM2 == (x)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnTim3Callback = NULL; + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志获å–(模å¼0/1/23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Tim3_GetIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + boolean_t bRetVal = FALSE; + uint32_t u32Val; + + u32Val = M0P_TIM3_MODE23->IFR; + bRetVal = (u32Val>>enTim3Irq) & 0x1; + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断标志清除(模å¼0/1/23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_ClearIntFlag(en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ICLR = ~(1u<ICLR_f.UIF = 0; + M0P_TIM3_MODE23->ICLR_f.CA0F = 0; + M0P_TIM3_MODE23->ICLR_f.CA1F = 0; + M0P_TIM3_MODE23->ICLR_f.CA2F = 0; + M0P_TIM3_MODE23->ICLR_f.CB0F = 0; + M0P_TIM3_MODE23->ICLR_f.CB1F = 0; + M0P_TIM3_MODE23->ICLR_f.CB2F = 0; + M0P_TIM3_MODE23->ICLR_f.BIF = 0; + M0P_TIM3_MODE23->ICLR_f.TIF = 0; + M0P_TIM3_MODE23->ICLR_f.CA0E = 0; + M0P_TIM3_MODE23->ICLR_f.CA1E = 0; + M0P_TIM3_MODE23->ICLR_f.CA2E = 0; + M0P_TIM3_MODE23->ICLR_f.CB0E = 0; + M0P_TIM3_MODE23->ICLR_f.CB1E = 0; + M0P_TIM3_MODE23->ICLR_f.CB2E = 0; + + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_EnableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_DisableIrq(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.UIE = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼1) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼1) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE1->M1CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE1->CR0_f.CIEA = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断使能(模å¼23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_EnableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = TRUE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = TRUE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = TRUE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = TRUE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = TRUE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = TRUE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = TRUE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = TRUE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = TRUE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断ç¦æ­¢(模å¼23) + ** + ** + ** \param [in] enTim3Irq 中断类型 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_DisableIrq (en_tim3_irq_type_t enTim3Irq) +{ + en_result_t enResult = Ok; + + + switch (enTim3Irq) + { + case Tim3UevIrq: + M0P_TIM3_MODE23->M23CR_f.UIE = FALSE; + break; + case Tim3CA0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEA = FALSE; + break; + case Tim3CB0Irq: + M0P_TIM3_MODE23->CRCH0_f.CIEB = FALSE; + break; + case Tim3CA1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEA = FALSE; + break; + case Tim3CB1Irq: + M0P_TIM3_MODE23->CRCH1_f.CIEB = FALSE; + break; + case Tim3CA2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEA = FALSE; + break; + case Tim3CB2Irq: + M0P_TIM3_MODE23->CRCH2_f.CIEB = FALSE; + break; + case Tim3BkIrq: + M0P_TIM3_MODE23->M23CR_f.BIE = FALSE; + break; + case Tim3TrigIrq: + M0P_TIM3_MODE23->M23CR_f.TIE = FALSE; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param Timer3通é“选择(3 - TIM3) + ** + ** \retval NULL + *****************************************************************************/ +void Tim3_IRQHandler(uint8_t u8Param) +{ + switch (u8Param) + { + case 0: + if(NULL != pfnTim3Callback) + { + pfnTim3Callback(); + } + break; + default: + ; + break; + } +} + + + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼0) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode0_Init(stc_tim3_mode0_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM3_MODE0->M0CR_f.GATEP = pstcConfig->enGateP; + M0P_TIM3_MODE0->M0CR_f.GATE = pstcConfig->bEnGate; + M0P_TIM3_MODE0->M0CR_f.PRS = pstcConfig->enPRS; + M0P_TIM3_MODE0->M0CR_f.TOGEN = pstcConfig->bEnTog; + M0P_TIM3_MODE0->M0CR_f.CT = pstcConfig->enCT; + M0P_TIM3_MODE0->M0CR_f.MD = pstcConfig->enCntMode; + + pfnTim3Callback = pstcConfig->pfnTim3Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->M0CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 翻转输出使能/ç¦æ­¢è®¾å®š(模å¼0) + ** + ** + ** \param [in] bEnOutput 翻转输出设定 TRUE:使能, FALSE:ç¦æ­¢ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_EnTOG_Output(boolean_t bEnOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->DTR_f.MOE = bEnOutput; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data CNT 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M0_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE0->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_ARRSet(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->ARR_f.ARR = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼0) + ** + ** + ** \param [in] u32Data 32ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M0_Cnt32Set(uint32_t u32Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE0->CNT32_f.CNT32 = u32Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 32ä½è®¡æ•°å€¼èŽ·å–(模å¼0) + ** + ** + ** \param [in] none + ** + ** \retval 32bits计数值 + *****************************************************************************/ +uint32_t Tim3_M0_Cnt32Get(void) +{ + uint32_t u32CntData = 0; + + u32CntData = M0P_TIM3_MODE0->CNT32_f.CNT32; + + return u32CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode1_Init(stc_tim3_mode1_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.MODE = pstcConfig->enWorkMode; + M0P_TIM3_MODE1->M1CR_f.PRS = pstcConfig->enPRS; + M0P_TIM3_MODE1->M1CR_f.CT = pstcConfig->enCT; + M0P_TIM3_MODE1->M1CR_f.ONESHOT = pstcConfig->enOneShot; + + pfnTim3Callback = pstcConfig->pfnTim3Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC 输入é…ç½®(模å¼1) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Input_Config(stc_tim3_pwc_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->MSCR_f.TS = pstcConfig->enTsSel; + M0P_TIM3_MODE1->MSCR_f.IA0S = pstcConfig->enIA0Sel; + M0P_TIM3_MODE1->MSCR_f.IB0S = pstcConfig->enIB0Sel; + M0P_TIM3_MODE1->FLTR_f.ETP = pstcConfig->enETRPhase; + M0P_TIM3_MODE1->FLTR_f.FLTET = pstcConfig->enFltETR; + M0P_TIM3_MODE1->FLTR_f.FLTA0 = pstcConfig->enFltIA0; + M0P_TIM3_MODE1->FLTR_f.FLTB0 = pstcConfig->enFltIB0; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWC测é‡è¾¹æ²¿èµ·å§‹ç»“æŸé€‰æ‹©(模å¼1) + ** + ** + ** \param [in] enEdgeSel pwc测é‡èµ·å§‹ç»ˆæ­¢ç”µå¹³ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_PWC_Edge_Sel(en_tim3_m1cr_Edge_t enEdgeSel) +{ + en_result_t enResult = Ok; + + switch (enEdgeSel) + { + case 0: ///< 上å‡æ²¿åˆ°ä¸Šå‡æ²¿(周期) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 1: ///< 下é™æ²¿åˆ°ä¸Šå‡æ²¿(低电平) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下é™æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 0; //上å‡æ²¿ + break; + case 2: ///< 上å‡æ²¿åˆ°ä¸‹é™æ²¿(高电平) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 0; //上å‡æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + case 3: ///< 下é™æ²¿åˆ°ä¸‹é™æ²¿(周期) + M0P_TIM3_MODE1->M1CR_f.EDG1ST = 1; //下é™æ²¿ + M0P_TIM3_MODE1->M1CR_f.EDG2ND = 1; //下é™æ²¿ + break; + default: + ; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->M1CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼1) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M1_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE1->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M1_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE1->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 脉冲宽度测é‡ç»“果数值获å–(模å¼1) + ** + ** + ** \param [in] none + ** + ** \retval 16bits脉冲宽度测é‡ç»“æžœ + *****************************************************************************/ +uint16_t Tim3_M1_PWC_CapValueGet(void) +{ + uint16_t u16CapData = 0; + + u16CapData = M0P_TIM3_MODE1->CCR0A_f.CCR0A; + + return u16CapData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åˆå§‹åŒ–é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_Mode23_Init(stc_tim3_mode23_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.MODE = pstcConfig->enWorkMode; + + M0P_TIM3_MODE23->M23CR_f.PRS = pstcConfig->enPRS; + M0P_TIM3_MODE23->M23CR_f.CT = pstcConfig->enCT; + M0P_TIM3_MODE23->M23CR_f.COMP = pstcConfig->enPWMTypeSel; + M0P_TIM3_MODE23->M23CR_f.PWM2S = pstcConfig->enPWM2sSel; + M0P_TIM3_MODE23->M23CR_f.ONESHOT = pstcConfig->bOneShot; + M0P_TIM3_MODE23->M23CR_f.URS = pstcConfig->bURSSel; + M0P_TIM3_MODE23->M23CR_f.DIR = pstcConfig->enCntDir; + + pfnTim3Callback = pstcConfig->pfnTim3Cb; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM输出使能(模å¼23) + ** + ** + ** \param [in] bEnOutput PWM输出使能/ç¦æ­¢è®¾å®š + ** \param [in] bEnAutoOutput PWM自动输出使能/ç¦æ­¢è®¾å®š + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnPWM_Output(boolean_t bEnOutput, boolean_t bEnAutoOutput) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.MOE = bEnOutput; + M0P_TIM3_MODE23->DTR_f.AOE = bEnAutoOutput; + + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Base Timer3 å¯åŠ¨è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Run(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 åœæ­¢è¿è¡Œ(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Stop(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CTEN = FALSE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 é‡è½½å€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16bitsé‡è½½å€¼ + ** \param [in] bArrBufEn ARRé‡è½½ç¼“存使能TRUE/ç¦æ­¢FALSE + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ARRSet(uint16_t u16Data, boolean_t bArrBufEn) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ARR_f.ARR = u16Data; + M0P_TIM3_MODE23->M23CR_f.BUFPEN = bArrBufEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å™¨åˆå€¼è®¾ç½®(模å¼23) + ** + ** + ** \param [in] u16Data 16ä½åˆå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_Cnt16Set(uint16_t u16Data) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->CNT_f.CNT = u16Data; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 16ä½è®¡æ•°å€¼èŽ·å–(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval 16bits计数值 + *****************************************************************************/ +uint16_t Tim3_M23_Cnt16Get(void) +{ + uint16_t u16CntData = 0; + + u16CntData = M0P_TIM3_MODE23->CNT_f.CNT; + + return u16CntData; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB设置(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** \param [in] u16Data CCRxA/CCRxB 16ä½åˆå§‹å€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_CCR_Set(en_tim3_m23_ccrx_t enCCRSel, uint16_t u16Data) +{ + en_result_t enResult = Ok; + + if(Tim3CCR0A == enCCRSel) + { + M0P_TIM3_MODE23->CCR0A_f.CCR0A = u16Data; + } + else if(Tim3CCR0B == enCCRSel) + { + M0P_TIM3_MODE23->CCR0B_f.CCR0B = u16Data; + } + else if(Tim3CCR1A == enCCRSel) + { + M0P_TIM3_MODE23->CCR1A_f.CCR1A = u16Data; + } + else if(Tim3CCR1B == enCCRSel) + { + M0P_TIM3_MODE23->CCR1B_f.CCR1B = u16Data; + } + else if(Tim3CCR2A == enCCRSel) + { + M0P_TIM3_MODE23->CCR2A_f.CCR2A = u16Data; + } + else if(Tim3CCR2B == enCCRSel) + { + M0P_TIM3_MODE23->CCR2B_f.CCR2B = u16Data; + } + else + { + enResult = Error; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 比较æ•èŽ·å¯„存器CCRxA/CCRxB读å–(模å¼23) + ** + ** + ** \param [in] enCCRSel CCRxA/CCRxB设定 + ** + ** \retval 16bitsCCRxA/CCRxBæ•èŽ·å€¼ + *****************************************************************************/ +uint16_t Tim3_M23_CCR_Get(en_tim3_m23_ccrx_t enCCRSel) +{ + uint16_t u16Data = 0; + + if(Tim3CCR0A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0A_f.CCR0A; + } + else if(Tim3CCR0B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR0B_f.CCR0B; + } + else if(Tim3CCR1A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1A_f.CCR1A; + } + else if(Tim3CCR1B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR1B_f.CCR1B; + } + else if(Tim3CCR2A == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2A_f.CCR2A; + } + else if(Tim3CCR2B == enCCRSel) + { + u16Data = M0P_TIM3_MODE23->CCR2B_f.CCR2B; + } + else + { + u16Data = 0; + } + + return u16Data; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 PWM互补输出模å¼ä¸‹ï¼ŒGATE功能选择(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_GateFuncSel(stc_tim3_m23_gate_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.CSG = pstcConfig->enGateFuncSel; + M0P_TIM3_MODE23->M23CR_f.CRG = pstcConfig->bGateRiseCap; + M0P_TIM3_MODE23->M23CR_f.CFG = pstcConfig->bGateFallCap; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 主从模å¼é…ç½®(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_MasterSlave_Set(stc_tim3_m23_master_slave_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->MSCR_f.MSM = pstcConfig->enMasterSlaveSel; + M0P_TIM3_MODE23->MSCR_f.MMS = pstcConfig->enMasterSrc; + M0P_TIM3_MODE23->MSCR_f.SMS = pstcConfig->enSlaveModeSel; + M0P_TIM3_MODE23->MSCR_f.TS = pstcConfig->enTsSel; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB比较通é“控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortOutput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_compare_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH0_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH0_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH1_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH1_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 0; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxACmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEA = pstcConfig->bCHxACmpBufEn; + M0P_TIM3_MODE23->M23CR_f.CIS = pstcConfig->enCHxACmpIntSel; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 0; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBCmpCtrl; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; + M0P_TIM3_MODE23->CRCH2_f.BUFEB = pstcConfig->bCHxBCmpBufEn; + M0P_TIM3_MODE23->CRCH2_f.CISB = pstcConfig->enCHxBCmpIntSel; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 CHxA/CHxB输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_PortInput_Config(en_tim3_channel_t enTim3Chx, stc_tim3_m23_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + switch (enTim3Chx) + { + case Tim3CH0: + M0P_TIM3_MODE23->CRCH0_f.CSA = 1; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA0_FLTA0 = pstcConfig->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA0 = pstcConfig->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH0_f.CSB = 1; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB0_FLTB0 = pstcConfig->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB0 = pstcConfig->enCHxBPolarity; + break; + case Tim3CH1: + M0P_TIM3_MODE23->CRCH1_f.CSA = 1; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA1_FLTA1 = pstcConfig->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA1 = pstcConfig->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH1_f.CSB = 1; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB1_FLTB1 = pstcConfig->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB1 = pstcConfig->enCHxBPolarity; + break; + case Tim3CH2: + M0P_TIM3_MODE23->CRCH2_f.CSA = 1; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enCHxACapSel; + M0P_TIM3_MODE23->FLTR_f.OCMA2_FLTA2 = pstcConfig->enCHxAInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPA2 = pstcConfig->enCHxAPolarity; + + M0P_TIM3_MODE23->CRCH2_f.CSB = 1; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enCHxBCapSel; + M0P_TIM3_MODE23->FLTR_f.OCMB2_FLTB2 = pstcConfig->enCHxBInFlt; + M0P_TIM3_MODE23->FLTR_f.CCPB2 = pstcConfig->enCHxBPolarity; + break; + default: + enResult = Error; + break; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 ERT输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_ETRInput_Config(stc_tim3_m23_etr_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->FLTR_f.ETP = pstcConfig->enETRPolarity; + M0P_TIM3_MODE23->FLTR_f.FLTET = pstcConfig->enETRFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 刹车BK输入控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_BrakeInput_Config(stc_tim3_m23_bk_input_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.BKE = pstcConfig->bEnBrake; + M0P_TIM3_MODE23->DTR_f.VC0E = pstcConfig->bEnVC0Brake; + M0P_TIM3_MODE23->DTR_f.VC1E = pstcConfig->bEnVC1Brake; + M0P_TIM3_MODE23->DTR_f.SAFEEN = pstcConfig->bEnSafetyBk; + M0P_TIM3_MODE23->DTR_f.BKSEL = pstcConfig->bEnBKSync; + M0P_TIM3_MODE23->CRCH0_f.CFA_CRA_BKSA = pstcConfig->enBkCH0AStat; + M0P_TIM3_MODE23->CRCH0_f.CFB_CRB_BKSB = pstcConfig->enBkCH0BStat; + M0P_TIM3_MODE23->CRCH1_f.CFA_CRA_BKSA = pstcConfig->enBkCH1AStat; + M0P_TIM3_MODE23->CRCH1_f.CFB_CRB_BKSB = pstcConfig->enBkCH1BStat; + M0P_TIM3_MODE23->CRCH2_f.CFA_CRA_BKSA = pstcConfig->enBkCH2AStat; + M0P_TIM3_MODE23->CRCH2_f.CFB_CRB_BKSB = pstcConfig->enBkCH2BStat; + M0P_TIM3_MODE23->FLTR_f.BKP = pstcConfig->enBrakePolarity; + M0P_TIM3_MODE23->FLTR_f.FLTBK = pstcConfig->enBrakeFlt; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 触å‘ADC控制(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_TrigADC_Config(stc_tim3_m23_adc_trig_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->ADTR_f.ADTE = pstcConfig->bEnTrigADC; + M0P_TIM3_MODE23->ADTR_f.UEVE = pstcConfig->bEnUevTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA0E = pstcConfig->bEnCH0ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB0E = pstcConfig->bEnCH0BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA1E = pstcConfig->bEnCH1ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB1E = pstcConfig->bEnCH1BCmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMA2E = pstcConfig->bEnCH2ACmpTrigADC; + M0P_TIM3_MODE23->ADTR_f.CMB2E = pstcConfig->bEnCH2BCmpTrigADC; + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 死区功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_DT_Config(stc_tim3_m23_dt_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->DTR_f.DTEN = pstcConfig->bEnDeadTime; + M0P_TIM3_MODE23->DTR_f.DTR = pstcConfig->u8DeadTimeValue; + + return enResult; +} + +/** + ***************************************************************************** +** \brief Base Timer3 é‡å¤å‘¨æœŸè®¾ç½®(模å¼23) + ** + ** + ** \param [in] u8ValidPeriod é‡å¤å‘¨æœŸå€¼ + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_SetValidPeriod(uint8_t u8ValidPeriod) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->RCR_f.RCR = u8ValidPeriod; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 OCREF清除功能(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_OCRefClr(stc_tim3_m23_OCREF_Clr_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.OCCS = pstcConfig->enOCRefClrSrcSel; + M0P_TIM3_MODE23->M23CR_f.OCCE = pstcConfig->bVCClrEn; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 使能DMA传输(模å¼23) + ** + ** + ** \param [in] pstcConfig åˆå§‹åŒ–é…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnDMA(stc_tim3_m23_trig_dma_config_t* pstcConfig) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UDE = pstcConfig->bUevTrigDMA; + M0P_TIM3_MODE23->M23CR_f.TDE = pstcConfig->bTITrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEA = pstcConfig->bCmpA0TrigDMA; + M0P_TIM3_MODE23->CRCH0_f.CDEB = pstcConfig->bCmpB0TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEA = pstcConfig->bCmpA1TrigDMA; + M0P_TIM3_MODE23->CRCH1_f.CDEB = pstcConfig->bCmpB1TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEA = pstcConfig->bCmpA2TrigDMA; + M0P_TIM3_MODE23->CRCH2_f.CDEB = pstcConfig->bCmpB2TrigDMA; + M0P_TIM3_MODE23->MSCR_f.CCDS = pstcConfig->enCmpUevTrigDMA; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较A软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpA(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGA = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGA = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGA = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 æ•èŽ·æ¯”较B软件触å‘(模å¼23) + ** + ** + ** \param [in] enTim3Chx Timer3通é“(Tim3CH0, Tim3CH1, Tim3CH2) + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrigCapCmpB(en_tim3_channel_t enTim3Chx) +{ + en_result_t enResult = Ok; + if(Tim3CH0 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH0_f.CCGB = TRUE; + } + else if(Tim3CH1 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH1_f.CCGB = TRUE; + } + else if(Tim3CH2 == enTim3Chx) + { + M0P_TIM3_MODE23->CRCH2_f.CCGB = TRUE; + } + else + { + enResult = Error; + } + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件更新使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwUev(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.UG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件触å‘使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwTrig(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.TG = TRUE; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Base Timer3 软件刹车使能(模å¼23) + ** + ** + ** \param [in] none + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Tim3_M23_EnSwBk(void) +{ + en_result_t enResult = Ok; + + M0P_TIM3_MODE23->M23CR_f.BG = TRUE; + + return enResult; +} + +//@} // Tim3Group + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/trim.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/trim.c new file mode 100644 index 0000000000..413a8fc248 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/trim.c @@ -0,0 +1,348 @@ +/****************************************************************************** +*Copyright(C)2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/** \file trim.c + ** + ** Common API of trim. + ** @link trimGroup Some description @endlink + ** + ** - 2017-05-16 + ** + ******************************************************************************/ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "trim.h" +/** + ******************************************************************************* + ** \addtogroup TrimGroup + ******************************************************************************/ +//@{ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#define IS_VALID_TRIMINT(x) (TrimStop == (x) ||\ + TrimCalCntOf == (x) ||\ + TrimXTLFault == (x) ||\ + TrimXTHFault == (x) ||\ + TrimPLLFault == (x)) + + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static func_ptr_t pfnTrimCallback = NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + ***************************************************************************** + ** \brief Trimä¸­æ–­æ ‡å¿—èŽ·å– + ** + ** + ** \param [in] enIntType 中断类型（RefStopã€CalCntOfã€XTAL32KFaultã€XTAL32MFault） + ** + ** \retval TRUE or FALSE + *****************************************************************************/ +boolean_t Trim_GetIntFlag(en_trim_inttype_t enIntType) +{ + boolean_t bRetVal = FALSE; + + ASSERT(IS_VALID_TRIMINT(enIntType)); + + switch (enIntType) + { + case TrimStop: + bRetVal = M0P_CLK_TRIM->IFR_f.STOP ? TRUE : FALSE; + break; + case TrimCalCntOf: + bRetVal = M0P_CLK_TRIM->IFR_f.CALCNT_OF ? TRUE : FALSE; + break; + case TrimXTLFault: + bRetVal = M0P_CLK_TRIM->IFR_f.XTL_FAULT ? TRUE : FALSE; + break; + case TrimXTHFault: + bRetVal = M0P_CLK_TRIM->IFR_f.XTH_FAULT ? TRUE : FALSE; + break; + case TrimPLLFault: + bRetVal = M0P_CLK_TRIM->IFR_f.PLL_FAULT ? TRUE : FALSE; + break; + default: + bRetVal = FALSE; + break; + } + + return bRetVal; +} + +/** + ***************************************************************************** + ** \brief Trim中断标志清除 + ** + ** + ** \param [in] enIntType 中断类型（RefStopã€CalCntOfã€XTAL32KFaultã€XTAL32MFault） + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_ClearIntFlag(en_trim_inttype_t enIntType) +{ + en_result_t enResult = Error; + + ASSERT(IS_VALID_TRIMINT(enIntType)); + + switch (enIntType) + { + case TrimStop: + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; + enResult = Ok; + break; + case TrimCalCntOf: + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; + enResult = Ok; + break; + case TrimXTLFault: + M0P_CLK_TRIM->ICLR_f.XTL_FAULT_CLR = FALSE; + enResult = Ok; + break; + case TrimXTHFault: + M0P_CLK_TRIM->ICLR_f.XTH_FAULT_CLR = FALSE; + enResult = Ok; + break; + case TrimPLLFault: + M0P_CLK_TRIM->ICLR_f.PLL_FAULT_CLR = FALSE; + enResult = Ok; + break; + default: + enResult = Error; + break; + } + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim中断æœåŠ¡å‡½æ•° + ** + ** + ** \param [in] u8Param == 0 + ** + ** \retval NULL + *****************************************************************************/ +void ClkTrim_IRQHandler(uint8_t u8Param) +{ + if(NULL != pfnTrimCallback) + { + pfnTrimCallback(); + } +} + +/** + ***************************************************************************** + ** \brief Trim中断使能 + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_EnableIrq (void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.IE = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim中断ç¦æ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_DisableIrq(void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.IE = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trimåˆå§‹åŒ–é…ç½® + ** + ** + ** \param [in] pstcConfig Trimé…置结构体指针 + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Init(stc_trim_config_t* pstcConfig) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.MON_EN = pstcConfig->enMON; + + if (TrimCalPLL == pstcConfig->enCALCLK) + { + M0P_CLK_TRIM->CR_f.CALCLK_SEL2 = TRUE; + M0P_CLK_TRIM->CR_f.CALCLK_SEL = pstcConfig->enCALCLK; + } + else + { + M0P_CLK_TRIM->CR_f.CALCLK_SEL2 = FALSE; + M0P_CLK_TRIM->CR_f.CALCLK_SEL = pstcConfig->enCALCLK; + } + + M0P_CLK_TRIM->CR_f.REFCLK_SEL = pstcConfig->enREFCLK; + + M0P_CLK_TRIM->REFCON_f.RCNTVAL = pstcConfig->u32RefCon; + if(TrimMonEnable == pstcConfig->enMON) + { + M0P_CLK_TRIM->CALCON_f.CCNTVAL = pstcConfig->u32CalCon; + } + + + pfnTrimCallback = pstcConfig->pfnTrimCb; + + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim校准/监测å¯åŠ¨è¿è¡Œ + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Run(void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.TRIM_START = TRUE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trim校准/监测åœæ­¢ + ** + ** + ** + ** + ** \retval Ok or Error + *****************************************************************************/ +en_result_t Trim_Stop(void) +{ + en_result_t enResult = Error; + + M0P_CLK_TRIM->CR_f.TRIM_START = FALSE; + enResult = Ok; + + return enResult; +} + +/** + ***************************************************************************** + ** \brief Trimå‚è€ƒè®¡æ•°å™¨è®¡æ•°å€¼èŽ·å– + ** + ** + ** \retval u32Data å‚考计数器计数值 + *****************************************************************************/ +uint32_t Trim_RefCntGet(void) +{ + uint32_t u32Data = 0; + + u32Data = M0P_CLK_TRIM->REFCNT_f.REFCNT; + + return u32Data; +} + +/** + ***************************************************************************** + ** \brief Trimæ ¡å‡†è®¡æ•°å™¨è®¡æ•°å€¼èŽ·å– + ** + ** + ** + ** + ** \retval u32Data 校准计数器计数值 + *****************************************************************************/ +uint32_t Trim_CalCntGet(void) +{ + uint32_t u32Data = 0; + + u32Data = M0P_CLK_TRIM->CALCNT_f.CALCNT; + + return u32Data; +} + +//@} // TrimGroup + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/uart.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/uart.c new file mode 100644 index 0000000000..f17a7ccc61 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/uart.c @@ -0,0 +1,910 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file uart.c + ** + ** UART function driver API. + ** @link SampleGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "uart.h" +/** + ****************************************************************************** + ** \addtogroup UartGroup + ******************************************************************************/ +//@{ +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +#define IS_VALID_CH(x) ((UARTCH0 == (x)) ||\ + (UARTCH1 == (x))) + +#define IS_VALID_IRQSEL(x) ((UartTxIrq == (x)) ||\ + (UartRxIrq == (x)) ||\ + (UartFEIrq == (x)) ||\ + (UartCtsIrq == (x))||\ + (UartPEIrq == (x)) ||\ + (UartTxEIrq == (x))) + +#define IS_VALID_MODE(x) ((UartMode0==(x))||\ + (UartMode1==(x))||\ + (UartMode2==(x))||\ + (UartMode3==(x))) + +#define IS_VALID_STATUS(x) ((UartCts == (x))||\ + (UartRC == (x))||\ + (UartTC == (x))||\ + (UartPE == (x))||\ + (UartCtsIf == (x))||\ + (UartTxe == (x))||\ + (UartFE == (x))) +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_uart_instance_data_t* UartGetInternDataPtr(uint8_t u8Idx); +static void UartInitNvic(uint8_t u8Idx); +static void UartDeInitNvic(uint8_t u8Idx); +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +static stc_uart_instance_data_t m_astcUartInstanceDataLut[] = +{ + { + UARTCH0, + M0P_UART0, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, + { + UARTCH1, + M0P_UART1, /* pstcInstance */ + {NULL,NULL,NULL,NULL,NULL}, + }, +}; +/** + ****************************************************************************** + ** \brief UART0/1é€šé“ ç›¸å…³åœ°å€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 通é“对应的地å€ç»“æž„ + ** + ******************************************************************************/ +static stc_uart_instance_data_t* UartGetInternDataPtr(uint8_t u8Idx) +{ + stc_uart_instance_data_t* pstcData = NULL; + uint8_t u8i = 0; + for (u8i = 0; u8i < ARRAY_SZ(m_astcUartInstanceDataLut); u8i++) + { + if (u8Idx == m_astcUartInstanceDataLut[u8i].u32Idx) + { + pstcData = &m_astcUartInstanceDataLut[u8i]; + break; + } + } + + return (pstcData); +} +/** + ****************************************************************************** + ** \brief UART通信中断使能函数设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断使能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_EnableIrq(uint8_t u8Idx, + en_uart_irq_sel_t enIrqSel) +{ + stc_uart_instance_data_t* pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case UartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 1u; + break; + case UartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 1u; + break; + case UartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 1u; + break; + case UartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 1u; + break; + case UartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 1u; + break; + case UartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通信中断ç¦æ­¢å‡½æ•°è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenIrqSelå‘é€or接收中断ç¦æ­¢ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_DisableIrq(uint8_t u8Idx, + en_uart_irq_sel_t enIrqSel) +{ + stc_uart_instance_data_t *pstcData = NULL; + + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_IRQSEL(enIrqSel)); + + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enIrqSel) + { + case UartTxIrq: + pstcData->pstcInstance->SCON_f.TCIE = 0u; + break; + case UartRxIrq: + pstcData->pstcInstance->SCON_f.RCIE = 0u; + break; + case UartFEIrq: + pstcData->pstcInstance->SCON_f.FEIE = 0u; + break; + case UartCtsIrq: + pstcData->pstcInstance->SCON_f.CTSIE = 0u; + break; + case UartPEIrq: + pstcData->pstcInstance->SCON_f.PEIE = 0u; + break; + case UartTxEIrq: + pstcData->pstcInstance->SCON_f.TXEIE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“4ç§æ¨¡å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œmode哪ç§æ¨¡å¼ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetMode(uint8_t u8Idx,en_uart_mode_t enMode) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_MODE(enMode)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.SM = enMode; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒstcMultiConfig多主机模å¼ç»“æž„ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetMultiMode(uint8_t u8Idx,stc_uart_multimode_t* pstcMultiConfig) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL != pstcMultiConfig) + { + pstcData->pstcInstance->SCON_f.ADRDET = pstcMultiConfig->enMulti_mode; + if(pstcMultiConfig->enMulti_mode == UartMulti) + { + pstcData->pstcInstance->SADDR = pstcMultiConfig->u8SlaveAddr; + pstcData->pstcInstance->SADEN = pstcMultiConfig->u8SaddEn; + } + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼å‘é€æ•°æ®/地å€å¸§æˆ–者奇å¶æ ¡éªŒé…ç½®TB8 + ** + ** \param [in] u8Idx通é“å·ï¼Œtb8æ•°æ®or地å€å¸§æˆ–者奇å¶æ ¡éªŒ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetMMDOrCk(uint8_t u8Idx,en_uart_mmdorck_t enTb8) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SCON_f.B8CONT = enTb8; + return Ok; +} +/** + ****************************************************************************** + ** \brief 获å–RB8数值 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval RB8 + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +boolean_t Uart_GetRb8(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + return (pstcData->pstcInstance->SBUF_f.DATA8); +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼ä»Žæœºåœ°å€é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddråœ°å€ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetSaddr(uint8_t u8Idx,uint8_t u8Addr) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADDR = u8Addr; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“多主机模å¼ä»ŽæœºæŽ©ç é…置函数 + ** + ** \param [in] u8Idx通é“å·ï¼Œaddren地å€æŽ©ç  + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetSaddrEn(uint8_t u8Idx,uint8_t u8Addren) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + pstcData->pstcInstance->SADEN = u8Addren; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“åœæ­¢ä½é•¿åº¦è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Lenåœæ­¢ä½é•¿åº¦ + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_SetStopBit(uint8_t u8Idx,uint8_t u8Len) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + switch(u8Len) + { + case Uart1bit: + case Uart15bit: + case Uart2bit: + pstcData->pstcInstance->SCON_f.STOPBIT = u8Len; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART采样频率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu8Div采样频率 + ** + ** \retval OKé…ç½®æˆåŠŸ + ******************************************************************************/ +en_result_t Uart_SetClkDiv(uint8_t u8Idx,en_uart_clkdiv_t enClkDiv) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCON_f.OVER = enClkDiv; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“波特率é…置值计算 + ** + ** \param [in] u8Idx通é“å·ï¼ŒpstcBaud波特率， + ** + ** \retval 定时器é…置值 + ** \retval 0,获å–值失败,u16Scnt波特率设置值 + ******************************************************************************/ +uint16_t Uart_CalScnt(uint8_t u8Idx,stc_uart_baud_t *pstcBaud) +{ + stc_uart_instance_data_t *pstcData = NULL; + uint16_t u16Scnt = 0; + uint8_t u8Over = 0; + ASSERT(IS_VALID_CH(u8Idx)); + + pstcData = UartGetInternDataPtr(u8Idx); + u8Over = pstcData->pstcInstance->SCON_f.OVER; + if(UartMode0 == pstcBaud->enRunMode) + { + return 0;//test + } + if((UartMode1 == pstcBaud->enRunMode)||(UartMode3 == pstcBaud->enRunMode)) + { + if(0 == u8Over) + { + u8Over = 16; + } + else + { + u8Over = 8; + } + + u16Scnt = pstcBaud->u32Pclk/(pstcBaud->u32Baud*u8Over); + } + else + { + if(0 == u8Over) + { + u8Over = 32; + } + else + { + u8Over = 16; + } + u16Scnt = pstcBaud->u32Pclk/u8Over; + } + return u16Scnt; +} +/** + ****************************************************************************** + ** \brief UART通é“波特率é…ç½® + ** + ** \param [in] u8Idx通é“å·ï¼Œu16Scnt波特率设置 + ** + ** \retval 定时器é…置值 + ** \retval 0,获å–值失败 + ******************************************************************************/ +en_result_t Uart_SetBaud(uint8_t u8Idx,uint16_t u16Scnt) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->SCNT = u16Scnt; + return Ok; +} + +/** + ****************************************************************************** + ** \brief UART通é“æ³¢ç‰¹çŽ‡èŽ·å– + ** + ** \param [in] u8Idx通é“å·,u8Modeå·¥ä½œæ¨¡å¼ + ** + ** \retval 波特率 + ******************************************************************************/ +uint32_t Uart_GetBaud(uint8_t u8Idx,uint8_t u8Mode,uint32_t u32Pclk) +{ + stc_uart_instance_data_t *pstcData = NULL; + uint32_t u32Baud = 0; + uint8_t u8Over = 0; + uint16_t u16Scnt = 0; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + u16Scnt = pstcData->pstcInstance->SCNT; + + switch(u8Mode) + { + case UartMode0: + u32Baud = u32Pclk/12; + break; + case UartMode1: + case UartMode3: + if(0 == pstcData->pstcInstance->SCON_f.OVER) + { + u8Over = 16; + } + else + { + u8Over = 8; + } + u32Baud = u32Pclk/(u8Over*u16Scnt); + break; + case UartMode2: + if(0 == pstcData->pstcInstance->SCON_f.OVER) + { + u8Over = 32; + } + else + { + u8Over = 16; + } + u32Baud = u32Pclk/u8Over; + break; + default : + return 0;//test + } + return u32Baud; +} +/** + ****************************************************************************** + ** \brief UART通é“å‘é€æˆ–接收等功能使能设置 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_EnableFunc(uint8_t u8Idx, en_uart_func_t enFunc) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case UartTx: + case UartRx: + pstcData->pstcInstance->SCON_f.REN = 1u; + break; + case UartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 1u; + break; + case UartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 1u; + break; + case UartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 1u; + pstcData->pstcInstance->SCON_f.RTSEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“å‘é€æˆ–接收等功能ç¦æ­¢è®¾ç½® + ** + ** \param [in] u8Idx通é“å·ï¼ŒenFunc功能 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_DisableFunc(uint8_t u8Idx, en_uart_func_t enFunc) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enFunc) + { + case UartTx: + case UartRx: + pstcData->pstcInstance->SCON_f.REN = 0u; + break; + case UartDmaTx: + pstcData->pstcInstance->SCON_f.DMATXEN = 0u; + break; + case UartDmaRx: + pstcData->pstcInstance->SCON_f.DMARXEN = 0u; + break; + case UartCtsRts: + pstcData->pstcInstance->SCON_f.CTSEN = 0u; + pstcData->pstcInstance->SCON_f.RTSEN = 0u; + break; + default: + return ErrorInvalidParameter; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval 状æ€å€¼ + ******************************************************************************/ +uint8_t Uart_GetIsr(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + return (pstcData->pstcInstance->ISR); +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€èŽ·å– + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatus获å–å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter获å–失败 + ******************************************************************************/ +boolean_t Uart_GetStatus(uint8_t u8Idx,en_uart_status_t enStatus) +{ + boolean_t bStatus=FALSE; + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter;//4，用户åªéœ€åˆ¤æ–­0或1 + } + switch(enStatus) + { + case UartCts: + bStatus = (pstcData->pstcInstance->ISR_f.CTS == 1) ? TRUE : FALSE; + break; + case UartRC: + bStatus = (pstcData->pstcInstance->ISR_f.RC == 1) ? TRUE : FALSE; + break; + case UartTC: + bStatus = (pstcData->pstcInstance->ISR_f.TC == 1) ? TRUE : FALSE; + break; + case UartPE: + bStatus = (pstcData->pstcInstance->ISR_f.PE == 1) ? TRUE : FALSE; + break; + case UartFE: + bStatus = (pstcData->pstcInstance->ISR_f.FE == 1) ? TRUE : FALSE; + break; + case UartCtsIf: + bStatus = (pstcData->pstcInstance->ISR_f.CTSIF == 1) ? TRUE : FALSE; + break; + case UartTxe: + bStatus = (pstcData->pstcInstance->ISR_f.TXE == 1) ? TRUE : FALSE; + break; + default: + break; + } + return bStatus; +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€æ¸…除 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval OK + ******************************************************************************/ +en_result_t Uart_ClrIsr(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + pstcData->pstcInstance->ICR = 0u; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“通信状æ€æ¸…除 + ** + ** \param [in] u8Idx通é“å·ï¼ŒenStatusæ¸…é™¤å“ªä¸ªçŠ¶æ€ + ** + ** \retval 状æ€å€¼ + **\retval ErrorInvalidParameter清除失败 + ******************************************************************************/ +en_result_t Uart_ClrStatus(uint8_t u8Idx,en_uart_status_t enStatus) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + ASSERT(IS_VALID_STATUS(enStatus)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + switch(enStatus) + { + case UartCts: + pstcData->pstcInstance->ICR_f.CTSIFCF = 0; + break; + case UartRC: + pstcData->pstcInstance->ICR_f.RCCF = 0; + break; + case UartTC: + pstcData->pstcInstance->ICR_f.TCCF = 0; + break; + case UartPE: + pstcData->pstcInstance->ICR_f.PECF = 0; + break; + case UartFE: + pstcData->pstcInstance->ICR_f.FECF = 0; + break; + default: + break; + } + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“å‘é€æ•°æ®å‡½æ•°,查询方å¼è°ƒç”¨æ­¤å‡½æ•°ï¼Œä¸­æ–­æ–¹å¼å‘é€ä¸é€‚用 + ** + ** \param [in] u8Idx通é“å·ï¼ŒDataå‘é€æ•°æ® + ** + ** \retval Okå‘é€æˆåŠŸ + **\retval ErrorInvalidParameterå‘é€å¤±è´¥ + ******************************************************************************/ +en_result_t Uart_SendData(uint8_t u8Idx, uint8_t u8Data) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + while(FALSE == Uart_GetStatus(u8Idx, UartTxe)) + {} + pstcData->pstcInstance->SBUF_f.DATA = u8Data; + return Ok; +} +/** + ****************************************************************************** + ** \brief UART通é“接收数æ®å‡½æ•° + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æŽ¥æ”¶æ•°æ® + **\retval ErrorInvalidParameter接收失败 + ******************************************************************************/ +int Uart_ReceiveData(uint8_t u8Idx) +{ + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return -1; + } + return (pstcData->pstcInstance->SBUF_f.DATA); +} +/** + ****************************************************************************** + ** \brief UART通é“中断处ç†å‡½æ•° + ** + ** \param [in] u8Param通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Uart_IRQHandler(uint8_t u8Param) +{ + stc_uart_instance_data_t *pstcData = NULL; + pstcData = UartGetInternDataPtr(u8Param); + if (NULL == pstcData) + { + return; + } + if(1 == pstcData->pstcInstance->ISR_f.FE) + { + Uart_ClrStatus(u8Param,UartFE); + if(NULL != pstcData->stcUartInternIrqCb.pfnRxFEIrqCb) + { + pstcData->stcUartInternIrqCb.pfnRxFEIrqCb(); + } + return;//帧出错则ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.PE) + { + Uart_ClrStatus(u8Param,UartPE); + if(NULL != pstcData->stcUartInternIrqCb.pfnPEIrqCb) + { + pstcData->stcUartInternIrqCb.pfnPEIrqCb(); + } + return;//若奇å¶æ ¡éªŒå‡ºé”™åˆ™ä¸è¿›è¡ŒåŽç»­æ•°æ®å¤„ç† + } + if(1 == pstcData->pstcInstance->ISR_f.CTSIF) + { + Uart_ClrStatus(u8Param,UartCts); + if(NULL != pstcData->stcUartInternIrqCb.pfnCtsIrqCb) + { + pstcData->stcUartInternIrqCb.pfnCtsIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.RC) + { + Uart_ClrStatus(u8Param,UartRC); + if(NULL != pstcData->stcUartInternIrqCb.pfnRxIrqCb) + { + pstcData->stcUartInternIrqCb.pfnRxIrqCb(); + } + } + if(1 == pstcData->pstcInstance->ISR_f.TC) + { + Uart_ClrStatus(u8Param,UartTC); + if(NULL != pstcData->stcUartInternIrqCb.pfnTxIrqCb) + { + pstcData->stcUartInternIrqCb.pfnTxIrqCb(); + } + } +} +/** + ****************************************************************************** + ** \brief UART通é“使能内核NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void UartInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx));; + enIrqIndex = (IRQn_Type)(UART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_EnableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief UART通é“ç¦æ­¢å†…æ ¸NVIC中断 + ** + ** \param [in] u8Idx通é“å· + ** + ** \retval æ—  + ** + ******************************************************************************/ +static void UartDeInitNvic(uint8_t u8Idx) +{ + IRQn_Type enIrqIndex; + + ASSERT(IS_VALID_CH(u8Idx)); + enIrqIndex = (IRQn_Type)(UART0_IRQn + u8Idx); + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex,IrqLevel3); + NVIC_DisableIRQ(enIrqIndex); + +} +/** + ****************************************************************************** + ** \brief UART通é“åˆå§‹åŒ–函数 + ** + ** \param [in] u8Idx通é“å·ï¼ŒpstcConfigåˆå§‹åŒ–结构体 + ** + ** \retval OKé…ç½®æˆåŠŸ + **\retval ErrorInvalidParameteré…置失败 + ******************************************************************************/ +en_result_t Uart_Init(uint8_t u8Idx, + stc_uart_config_t* pstcConfig) +{ + en_result_t enRet = Error; + stc_uart_instance_data_t *pstcData = NULL; + ASSERT(IS_VALID_CH(u8Idx)); + pstcData = UartGetInternDataPtr(u8Idx); + if (NULL == pstcData) + { + return ErrorInvalidParameter; + } + if(NULL == pstcConfig) + { + return ErrorInvalidParameter; + } + enRet = Uart_SetMode(u8Idx,pstcConfig->enRunMode); + enRet = Uart_SetStopBit(u8Idx,pstcConfig->enStopBit); + if(NULL != pstcConfig->pstcMultiMode) + { + enRet = Uart_SetMultiMode(u8Idx,pstcConfig->pstcMultiMode); + } + if(NULL != pstcConfig->pstcIrqCb) + { + pstcData->stcUartInternIrqCb.pfnRxFEIrqCb = pstcConfig->pstcIrqCb->pfnRxFEIrqCb; + pstcData->stcUartInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcData->stcUartInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcData->stcUartInternIrqCb.pfnCtsIrqCb = pstcConfig->pstcIrqCb->pfnCtsIrqCb; + pstcData->stcUartInternIrqCb.pfnPEIrqCb = pstcConfig->pstcIrqCb->pfnPEIrqCb; + } + if(pstcConfig->bTouchNvic == TRUE) + { + UartInitNvic(u8Idx); + } + else + { + UartDeInitNvic(u8Idx); + } + enRet = Ok; + return enRet; +} +//@} // UartGroup diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/vc.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/vc.c new file mode 100644 index 0000000000..fbb14ed4a6 --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/vc.c @@ -0,0 +1,674 @@ +/****************************************************************************** +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file vc.c + ** + ** voltage comparator driver API. + ** @link VC Group Some description @endlink + ** + ** - 2017-06-28 Alex First Version + ** + ******************************************************************************/ + +/****************************************************************************** + * Include files + ******************************************************************************/ +#include "vc.h" + +/** + ****************************************************************************** + ** \addtogroup VcGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define IS_VALID_CHANNEL(x) ( VcChannel0==(x) || VcChannel1 == (x)) +#define IS_VALID_STAT(x) ( VcCmpResult==(x) || VcIntrResult == (x)) +#define IS_VALID_DIV(x) ( (x) <= 64u ) + +#define IS_VALID_INPUT_P(x) ( (x) <= VcInPCh15 ) + +#define IS_VALID_INPUT_N(x) ( (x) <= AiLdo ) + +#define IS_VALID_DLY(x) ( (VcDelay30mv == (x)) ||\ + (VcDelay20mv == (x)) ||\ + (VcDelay10mv == (x)) ||\ + (VcDelayoff == (x)) ) + +#define IS_VALID_BIAS(x) ( (VcBias300na == (x)) ||\ + (VcBias1200na == (x)) ||\ + (VcBias10ua == (x)) ||\ + (VcBias20ua == (x)) ) + +#define IS_VALID_FILTER(x) ( (x) <= VcFilter28800us ) + + + +/****************************************************************************** + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + + +/****************************************************************************** + * Local type definitions ('typedef') + ******************************************************************************/ + +/****************************************************************************** + * Local function prototypes ('static') + ******************************************************************************/ +static en_result_t VcEnableIrq(en_vc_channel_t enChannel, boolean_t bFlag); +static void VcEnableNvic(IRQn_Type enIrqn); +static void VcDisableNvic(IRQn_Type enIrqn); + +/****************************************************************************** + * Local variable definitions ('static') + ******************************************************************************/ +static func_ptr_t pfnVc0IrqCb = NULL; +static func_ptr_t pfnVc1IrqCb = NULL; + +/***************************************************************************** + * Function implementation - global ('extern') and local ('static') + *****************************************************************************/ + +/** + * \brief + * 指定VC通é“中断使能/除能 + * + * \param [in] enChannel VC通é“å· + * \param [in] bFlag 使能/除能标志 + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +static en_result_t VcEnableIrq(en_vc_channel_t enChannel, boolean_t bFlag) +{ + if (VcChannel0 == enChannel) + { + if (bFlag) + { + VcEnableNvic(VC0_IRQn); + M0P_VC->VC0_CR_f.IE = 1u; + } + else + { + M0P_VC->VC0_CR_f.IE = 0u; + VcDisableNvic(VC0_IRQn); + } + } + else if (VcChannel1 == enChannel) + { + if (bFlag) + { + VcEnableNvic(VC1_IRQn); + M0P_VC->VC1_CR_f.IE = 1u; + } + else + { + M0P_VC->VC1_CR_f.IE = 0u; + VcDisableNvic(VC1_IRQn); + } + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * 使能NVIC中VC中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + */ +static void VcEnableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_EnableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, IrqLevel3); +} + +/** + * \brief + * 除能NVIC中VC中断 + * + * \param [in] enIrqn ä¸­æ–­å· + * + * \retval æ—  + */ +static void VcDisableNvic(IRQn_Type enIrqn) +{ + NVIC_ClearPendingIRQ(enIrqn); + NVIC_DisableIRQ(enIrqn); + NVIC_SetPriority(enIrqn, IrqLevel3); +} + +/** + * \brief + * VC中断æœåŠ¡ç¨‹åº + * + * \param [in] u8Param VC通é“å· + * + * \retval æ—  + */ +void Vc_IRQHandler(uint8_t u8Param) +{ + if (0 == u8Param) + { + if (TRUE == M0P_VC->IFR_f.VC0_INTF) + { + if (NULL != pfnVc0IrqCb) + { + pfnVc0IrqCb(); + } + M0P_VC->IFR_f.VC0_INTF = 0; + } + } + else if (1 == u8Param) + { + if (TRUE == M0P_VC->IFR_f.VC1_INTF) + { + if (NULL != pfnVc1IrqCb) + { + pfnVc1IrqCb(); + } + M0P_VC->IFR_f.VC1_INTF = 0; + } + } + else + { + ; // just return + } +} + +/** + * \brief + * é…ç½®VC中断触å‘æ–¹å¼ + * + * \param [in] enChannel VC通é“å· + * \param [in] enSel 中断触å‘æ–¹å¼é€‰æ‹© + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_ConfigIrq(en_vc_channel_t enChannel, en_vc_irq_sel_t enSel) +{ + stc_vc_vc0_cr_field_t *stcVcnCr; + en_result_t enRet = Ok; + + if (VcChannel0 == enChannel) + { + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC0_CR_f; + } + else if (VcChannel1 == enChannel) + { + stcVcnCr = (stc_vc_vc0_cr_field_t*)&M0P_VC->VC1_CR_f; + } + else + { + return ErrorInvalidParameter; + } + + switch (enSel) + { + case VcIrqRise: + stcVcnCr->RISING = 1u; + break; + case VcIrqFall: + stcVcnCr->FALLING = 1u; + break; + case VcIrqHigh: + stcVcnCr->LEVEL = 1u; + break; + + default: + enRet= ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + * \brief + * 获å–VCçŠ¶æ€ + * + * \param [in] enChannel VC通é“å· + * \param [in] enStat VC状æ€ç±»åž‹ + * + * \retval boolean_t TRUE: 状æ€ä¸ºé«˜ + * \retval boolean_t FALSE: 状æ€ä¸ºä½Ž + */ +boolean_t Vc_GetStat(en_vc_channel_t enChannel, en_vc_stat_t enStat) +{ + boolean_t bFlag = FALSE; + + ASSERT( IS_VALID_CHANNEL(enChannel) ); + ASSERT( IS_VALID_STAT(enStat) ); + + if (VcChannel0 == enChannel) + { + switch (enStat) + { + case VcCmpResult: + bFlag = M0P_VC->IFR_f.VC0_FILTER; + break; + case VcIntrResult: + bFlag = M0P_VC->IFR_f.VC0_INTF; + break; + default: + break; + } + } + else + { + switch (enStat) + { + case VcCmpResult: + bFlag = M0P_VC->IFR_f.VC1_FILTER; + break; + case VcIntrResult: + bFlag = M0P_VC->IFR_f.VC1_INTF; + break; + default: + break; + } + } + + return bFlag; +} + +/** + * \brief + * 清除VC中断标志 + * + * \param [in] enChannel VC通é“å· + * + * \retval æ—  + */ +void Vc_ClearIrq(en_vc_channel_t enChannel) +{ + ASSERT( IS_VALID_CHANNEL(enChannel) ); + + if (VcChannel0 == enChannel) + { + M0P_VC->IFR_f.VC0_INTF = 0u; + } + else + { + M0P_VC->IFR_f.VC1_INTF = 0u; + } +} + +/** + * \brief + * 指定VC通é“中断使能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_EnableIrq(en_vc_channel_t enChannel) +{ + return VcEnableIrq(enChannel, TRUE); +} + +/** + * \brief + * 指定VC通é“中断除能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: 设置æˆåŠŸ + * ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DisableIrq(en_vc_channel_t enChannel) +{ + return VcEnableIrq(enChannel, FALSE); +} + +/** + * \brief + * VC模å—åˆå§‹åŒ– + * + * \param [in] pstcGeneralConfig VC模å—é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DACInit(stc_vc_dac_config_t *pstcDacConfig) +{ + if (NULL == pstcDacConfig) + { + return ErrorInvalidParameter; + } + + M0P_VC->CR_f.DIV_EN = pstcDacConfig->bDivEn; + M0P_VC->CR_f.REF2P5_SEL = pstcDacConfig->enDivVref; + + if (pstcDacConfig->u8DivVal < 0x40) + { + M0P_VC->CR_f.DIV = pstcDacConfig->u8DivVal; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC模å—deinit + * + * \param æ—  + * + * \retval æ—  + */ +void Vc_DACDeInit(void) +{ + M0P_VC->CR_f.DIV_EN = 0u; + M0P_VC->CR_f.DIV = 0x20u; + M0P_VC->CR_f.REF2P5_SEL = 0u; +} + +/** + * \brief + * VC通é“åˆå§‹åŒ– + * + * \param [in] enChannel VC通é“å· + * \param [in] pstcChannelConfig VC通é“é…置指针 + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_ChannelInit(en_vc_channel_t enChannel, + stc_vc_channel_config_t *pstcChannelConfig) +{ + //en_result_t enRet = Ok; + + ASSERT(NULL != pstcChannelConfig); + ASSERT(IS_VALID_INPUT_P(pstcChannelConfig->enVcInPin_P)); + ASSERT(IS_VALID_INPUT_N(pstcChannelConfig->enVcInPin_N)); + ASSERT(IS_VALID_DLY(pstcChannelConfig->enVcCmpDly)); + ASSERT(IS_VALID_BIAS(pstcChannelConfig->enVcBiasCurrent)); + ASSERT(IS_VALID_FILTER(pstcChannelConfig->enVcFilterTime)); + + if (VcChannel0 == enChannel) + { + M0P_VC->CR_f.VC0_HYS_SEL = pstcChannelConfig->enVcCmpDly; + M0P_VC->CR_f.VC0_BIAS_SEL = pstcChannelConfig->enVcBiasCurrent; + M0P_VC->VC0_CR_f.DEBOUNCE_TIME = pstcChannelConfig->enVcFilterTime; + M0P_VC->VC0_CR_f.P_SEL = pstcChannelConfig->enVcInPin_P; + M0P_VC->VC0_CR_f.N_SEL = pstcChannelConfig->enVcInPin_N; + M0P_VC->VC0_OUT_CFG = 1<enVcOutConfig; + + switch(pstcChannelConfig->enVcIrqSel) + { + case VcIrqRise: + M0P_VC->VC0_CR_f.RISING = 1u; + break; + case VcIrqFall: + M0P_VC->VC0_CR_f.FALLING = 1u; + break; + case VcIrqHigh: + M0P_VC->VC0_CR_f.LEVEL = 1u; + break; + default: + M0P_VC->VC0_CR_f.LEVEL = 0u; + M0P_VC->VC0_CR_f.RISING = 0u; + M0P_VC->VC0_CR_f.FALLING = 0u; + break; + } + + pfnVc0IrqCb = pstcChannelConfig->pfnAnalogCmpCb; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->CR_f.VC1_HYS_SEL = pstcChannelConfig->enVcCmpDly; + M0P_VC->CR_f.VC1_BIAS_SEL = pstcChannelConfig->enVcBiasCurrent; + M0P_VC->VC1_CR_f.DEBOUNCE_TIME = pstcChannelConfig->enVcFilterTime; + M0P_VC->VC1_CR_f.P_SEL = pstcChannelConfig->enVcInPin_P; + M0P_VC->VC1_CR_f.N_SEL = pstcChannelConfig->enVcInPin_N; + M0P_VC->VC1_OUT_CFG = 1<enVcOutConfig; + + switch(pstcChannelConfig->enVcIrqSel) + { + case VcIrqRise: + M0P_VC->VC1_CR_f.RISING = 1u; + break; + case VcIrqFall: + M0P_VC->VC1_CR_f.FALLING = 1u; + break; + case VcIrqHigh: + M0P_VC->VC1_CR_f.LEVEL = 1u; + break; + default: + M0P_VC->VC1_CR_f.LEVEL = 0u; + M0P_VC->VC1_CR_f.RISING = 0u; + M0P_VC->VC1_CR_f.FALLING = 0u; + break; + } + + pfnVc1IrqCb = pstcChannelConfig->pfnAnalogCmpCb; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC通é“Deinit + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_ChannelDeInit(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.EN = 0u; + M0P_VC->CR_f.VC0_HYS_SEL = 0; + M0P_VC->CR_f.VC0_BIAS_SEL = 0; + M0P_VC->VC0_CR_f.DEBOUNCE_TIME = 0; + M0P_VC->VC0_CR_f.P_SEL = 0; + M0P_VC->VC0_CR_f.N_SEL = 0; + M0P_VC->VC0_OUT_CFG = 0; + M0P_VC->VC0_CR_f.LEVEL = 0u; + M0P_VC->VC0_CR_f.RISING = 0u; + M0P_VC->VC0_CR_f.FALLING = 0u; + pfnVc0IrqCb = NULL; + M0P_VC->VC0_CR_f.IE = 0u; + VcDisableNvic(VC0_IRQn); + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.EN = 0u; + M0P_VC->CR_f.VC1_HYS_SEL = 0; + M0P_VC->CR_f.VC1_BIAS_SEL = 0; + M0P_VC->VC1_CR_f.DEBOUNCE_TIME = 0; + M0P_VC->VC1_CR_f.P_SEL = 0; + M0P_VC->VC1_CR_f.N_SEL = 0; + M0P_VC->VC1_OUT_CFG = 0; + M0P_VC->VC1_CR_f.LEVEL = 0u; + M0P_VC->VC1_CR_f.RISING = 0u; + M0P_VC->VC1_CR_f.FALLING = 0u; + pfnVc1IrqCb = NULL; + M0P_VC->VC1_CR_f.IE = 0u; + VcDisableNvic(VC1_IRQn); + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC通é“使能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_EnableChannel(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.EN = 1u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.EN = 1u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC通é“除能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DisableChannel(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.EN = 0u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.EN = 0u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC输出滤波使能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_EnableFilter(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.FLTEN = 1u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.FLTEN = 1u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + * \brief + * VC输出滤波除能 + * + * \param [in] enChannel VC通é“å· + * + * \retval en_result_t Ok: é…ç½®æˆåŠŸ + * \retval en_result_t ErrorInvalidParameter: 无效å‚æ•° + */ +en_result_t Vc_DisableFilter(en_vc_channel_t enChannel) +{ + if (VcChannel0 == enChannel) + { + M0P_VC->VC0_CR_f.FLTEN = 0u; + } + else if (VcChannel1 == enChannel) + { + M0P_VC->VC1_CR_f.FLTEN = 0u; + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +//@} // VcGroup + + +/****************************************************************************** + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/wdt.c b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/wdt.c new file mode 100644 index 0000000000..0a3ea826dc --- /dev/null +++ b/bsp/hc32l136/Libraries/HC32L136_StdPeriph_Driver/src/wdt.c @@ -0,0 +1,184 @@ +/************************************************************************************* +* Copyright (C) 2017, Huada Semiconductor Co.,Ltd All rights reserved. +* +* This software is owned and published by: +* Huada Semiconductor Co.,Ltd ("HDSC"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with HDSC +* components. This software is licensed by HDSC to be adapted only +* for use in systems utilizing HDSC components. HDSC shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. HDSC is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* Disclaimer: +* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file wdt.c + ** + ** WDT function driver API. + ** @link WdtGroup Some description @endlink + ** + ** - 2017-05-17 1.0 CJ First version for Device Driver Library of Module. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "wdt.h" + +/** + ****************************************************************************** + ** \defgroup WdtGroup + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static func_ptr_t pfnWdtCallback = NULL; +/** + ****************************************************************************** + ** \brief WDT溢出时间设置函数 + ** + ** \param [in] u8LoadValue 溢出时间 + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Wdt_WriteWdtLoad(uint8_t u8LoadValue) +{ + M0P_WDT->CON_f.WOV = u8LoadValue; +} +/** + ****************************************************************************** + ** \brief WDTåˆå§‹åŒ–函数 + ** + ** \param [in] stcConfig åˆå§‹åŒ–结构 + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Wdt_Init(stc_wdt_config_t* pstcConfig) +{ + en_result_t enRet = Error; + ASSERT(NULL != pstcConfig); + Wdt_WriteWdtLoad(pstcConfig->u8LoadValue); + pfnWdtCallback = pstcConfig->pfnWdtIrqCb; + M0P_WDT->CON_f.WINT_EN = pstcConfig->enResetEnable; + if(pstcConfig->enResetEnable) + { + EnableNvic(WDT_IRQn,IrqLevel3,TRUE); + } + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief WDTå¤ä½åŠå¯åŠ¨å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Wdt_Start(void) +{ + en_result_t enRet = Error; + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; + enRet = Ok; + return enRet; +} +/** + ****************************************************************************** + ** \brief WDTå¤ä½åŠå¯åŠ¨å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval Ok + ** + ******************************************************************************/ +void Wdt_Feed(void) +{ + M0P_WDT->RST = 0x1E; + M0P_WDT->RST = 0xE1; +} +/** + ****************************************************************************** + ** \brief WDT读å–当å‰è®¡æ•°å€¼å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval 计数值 + ** + ******************************************************************************/ +uint8_t Wdt_ReadWdtValue(void) +{ + uint8_t u8Count; + u8Count = M0P_WDT->CON_f.WCNTL; + return u8Count; +} +/** + ****************************************************************************** + ** \brief WDT读å–当å‰è¿è¡ŒçŠ¶æ€ + ** + ** \param [in] æ—  + ** + ** \retval 状æ€å€¼ + ** + ******************************************************************************/ +uint8_t Wdt_ReadwdtStatus(void) +{ + return M0P_WDT->CON_f.WDTR; +} +/** + ****************************************************************************** + ** \brief WDT中断处ç†å‡½æ•° + ** + ** \param [in] æ—  + ** + ** \retval æ—  + ** + ******************************************************************************/ +void Wdt_IRQHandler(void) +{ + if(M0P_WDT->CON_f.WDINT) + { + Wdt_Start();//clr wdt 标记 + if(NULL != pfnWdtCallback) + { + pfnWdtCallback(); + } + } +} + +//@} // WdtGroup diff --git a/bsp/hc32l136/Libraries/LICENSE b/bsp/hc32l136/Libraries/LICENSE new file mode 100644 index 0000000000..72823826b8 --- /dev/null +++ b/bsp/hc32l136/Libraries/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2020, Huada Semiconductor Co., Ltd ("HDSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32l136/Libraries/SConscript b/bsp/hc32l136/Libraries/SConscript new file mode 100644 index 0000000000..f8e856e883 --- /dev/null +++ b/bsp/hc32l136/Libraries/SConscript @@ -0,0 +1,48 @@ +# RT-Thread building script for bridge + +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +HC32L136_StdPeriph_Driver/src/adc.c +HC32L136_StdPeriph_Driver/src/gpio.c +HC32L136_StdPeriph_Driver/src/uart.c +HC32L136_StdPeriph_Driver/src/lpuart.c +HC32L136_StdPeriph_Driver/src/rtc.c +HC32L136_StdPeriph_Driver/src/sysctrl.c +HC32L136_StdPeriph_Driver/src/timer3.c +HC32L136_StdPeriph_Driver/src/trim.c +HC32L136_StdPeriph_Driver/src/flash.c +HC32L136_StdPeriph_Driver/src/ddl.c +CMSIS/Device/HDSC/HC32L136/Source/system_hc32l13x.c +CMSIS/Device/HDSC/HC32L136/Source/interrupts_hc32l136.c +""") + +#src += Glob('HC32F4A0_StdPeriph_Driver/src/*.c') + +if GetDepend(['RT_USING_WDT']): + src += ['HC32L136_StdPeriph_Driver/src/wdt.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/HDSC/HC32L136/Source/GCC/startup_hc32l136.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/HDSC/HC32L136/Source/ARM/startup_hc32l136.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/HDSC/HC32L136/Source/IAR/startup_hc32l136.s'] + +#add headfile script +path = [cwd + '/CMSIS/Include', + cwd + '/CMSIS/Device/HDSC/HC32L136/Include', + cwd + '/HC32L136_StdPeriph_Driver/inc'] + +CPPDEFINES = ['USE_DDL_DRIVER', rtconfig.MCU_TYPE, '__DEBUG'] + +group = DefineGroup('HC32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32l136/README.md b/bsp/hc32l136/README.md new file mode 100644 index 0000000000..5367aacbad --- /dev/null +++ b/bsp/hc32l136/README.md @@ -0,0 +1,100 @@ +# HDSC HC32LFx3x-STK-V2.0 å¼€å‘æ¿ BSP 说明 + +## 简介 + +本文档为åŽå¤§åŠå¯¼ä½“为 HC32LFx3x-STK-V2.0 å¼€å‘æ¿æ供的 BSP (æ¿çº§æ”¯æŒåŒ…) 说明。 + +主è¦å†…容如下： + +- å¼€å‘æ¿èµ„æºä»‹ç» +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开å‘者å¯ä»¥å¿«é€Ÿåœ°ä¸Šæ‰‹è¯¥ BSP，将 RT-Thread è¿è¡Œåœ¨å¼€å‘æ¿ä¸Šã€‚在进阶使用指å—章节，将会介ç»æ›´å¤šé«˜çº§åŠŸèƒ½ï¼Œå¸®åŠ©å¼€å‘者利用 RT-Thread 驱动更多æ¿è½½èµ„æºã€‚ + +## å¼€å‘æ¿ä»‹ç» + +HC32LFx3x-STK-V2.0 是 HDSC 官方推出的开å‘æ¿ï¼Œæ­è½½ HC32L136 芯片，基于 ARM Cortex-M0 内核，最高主频 48 MHz，具有丰富的æ¿è½½èµ„æºã€‚ + +å¼€å‘æ¿å¤–观如下图所示： + +![board](figures/board.png) + +HC32LFx3x-STK-V2.0 å¼€å‘æ¿å¸¸ç”¨ **æ¿è½½èµ„æº** 如下： + +- MCU：HC32L136，主频 48MHz，64KB FLASH ，8KB RAM +- 常用外设 +- 常用接å£ï¼š +- 调试接å£ï¼šæ¿è½½DAP调试器ã€æ ‡å‡† JTAG/SWD。 + +## å¤–è®¾æ”¯æŒ + +本 BSP ç›®å‰å¯¹å¤–设的支æŒæƒ…况如下： + +| **片上外设** | **支æŒæƒ…况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| GPIO | æ”¯æŒ | PA0, PA1... PI15 ---> PIN: 0, 1...63 | +| UART | æ”¯æŒ | UART0~1 | +| LED | æ”¯æŒ | LED | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，éµå¾ªç®€å•çš„步骤å³å¯å°† RT-Thread æ“作系统è¿è¡Œåœ¨è¯¥å¼€å‘æ¿ä¸Šï¼Œçœ‹åˆ°å®žéªŒæ•ˆæžœ 。 + +- 进阶使用 + + 本章节是为需è¦åœ¨ RT-Thread æ“作系统上使用更多开å‘æ¿èµ„æºçš„å¼€å‘者准备的。通过使用 ENV 工具对 BSP 进行é…置，å¯ä»¥å¼€å¯æ›´å¤šæ¿è½½èµ„æºï¼Œå®žçŽ°æ›´å¤šé«˜çº§åŠŸèƒ½ã€‚ + + +### 快速上手 + +本 BSP 为开å‘者æä¾› MDK4ã€MDK5ã€IAR工程，暂ä¸æ”¯æŒGCCå¼€å‘环境。下é¢ä»¥ MDK5 å¼€å‘环境为例，介ç»å¦‚何将系统è¿è¡Œèµ·æ¥ã€‚ + +#### 硬件连接 + + + +#### 编译下载 + +åŒå‡» project.uvprojx 文件，打开 MDK5 工程，编译并下载程åºåˆ°å¼€å‘æ¿ã€‚ + +> 工程默认é…置使用 J-LINK 下载程åºï¼Œç‚¹å‡»ä¸‹è½½æŒ‰é’®å³å¯ä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿ã€‚ + +#### è¿è¡Œç»“æžœ + +下载程åºæˆåŠŸä¹‹åŽï¼Œç³»ç»Ÿä¼šè‡ªåŠ¨è¿è¡Œï¼Œè§‚察开å‘æ¿ä¸Š LED çš„è¿è¡Œæ•ˆæžœï¼Œç»¿è‰²ä¼šå‘¨æœŸæ€§é—ªçƒã€‚ + +连接PA2ã€PA3串å£ï¼Œåœ¨ç»ˆç«¯å·¥å…·é‡Œæ‰“开相应的串å£ï¼Œå¤ä½è®¾å¤‡åŽï¼Œå¯ä»¥çœ‹åˆ° RT-Thread 的输出信æ¯: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Aug 20 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +æ­¤ BSP 默认åªå¼€å¯äº† GPIO å’Œ ä¸²å£ 1 的功能，更多高级功能需è¦åˆ©ç”¨ env 工具对 BSP 进行é…置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令é…置工程，é…置好之åŽä¿å­˜é€€å‡ºã€‚ + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令é‡æ–°ç”Ÿæˆå·¥ç¨‹ã€‚ + +## 注æ„事项 + +## è”ç³»äººä¿¡æ¯ + +维护人: + +- [Ching], 邮箱：<515892376@qq.com> \ No newline at end of file diff --git a/bsp/hc32l136/SConscript b/bsp/hc32l136/SConscript new file mode 100644 index 0000000000..24bb4646ab --- /dev/null +++ b/bsp/hc32l136/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32l136/SConstruct b/bsp/hc32l136/SConstruct new file mode 100644 index 0000000000..ae37ec6a48 --- /dev/null +++ b/bsp/hc32l136/SConstruct @@ -0,0 +1,45 @@ +import os +import sys +import rtconfig + +print "############sconstruct##############" +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +print "RTT_ROOT: " + RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'hc32L136.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +print "######################env:" +print env +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32l136/applications/SConscript b/bsp/hc32l136/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/hc32l136/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l136/applications/main.c b/bsp/hc32l136/applications/main.c new file mode 100644 index 0000000000..699e24a524 --- /dev/null +++ b/bsp/hc32l136/applications/main.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2021, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-07 PJQ first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "board.h" + +#include +#include + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* defined the LED pin: PC9 */ +#define LED_PIN GET_PIN(D, 5) +#define KEY_PIN GET_PIN(B, 9) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + uint8_t flag; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +void key_handler(void *param) +{ + flag = ~flag; +} + +/** + ******************************************************************************* + ** \brief Main function of GPIO output + ** + ** \param None + ** + ** \retval int32_t Return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_attach_irq(KEY_PIN, PIN_IRQ_MODE_FALLING, key_handler, RT_NULL); + rt_pin_irq_enable(KEY_PIN, PIN_IRQ_ENABLE); + + while(1) + { + if (flag == 0) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_delay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_delay(500); + } + else + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_delay(2000); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_delay(2000); + } + } +} + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/board/Kconfig b/bsp/hc32l136/board/Kconfig new file mode 100644 index 0000000000..35ecfe181b --- /dev/null +++ b/bsp/hc32l136/board/Kconfig @@ -0,0 +1,57 @@ +menu "Hardware Drivers Config" + +config MCU_HC32L136 + bool + select ARCH_ARM_CORTEX_M0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default y + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default y + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 51 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 90 + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32l136/board/SConscript b/bsp/hc32l136/board/SConscript new file mode 100644 index 0000000000..589332a741 --- /dev/null +++ b/bsp/hc32l136/board/SConscript @@ -0,0 +1,14 @@ +from building import * + +cwd = GetCurrentDir() + +CPPPATH = [cwd] + +# add general drivers +src = Split(''' +board.c +''') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l136/board/board.c b/bsp/hc32l136/board/board.c new file mode 100644 index 0000000000..d39b09be9a --- /dev/null +++ b/bsp/hc32l136/board/board.c @@ -0,0 +1,101 @@ + /* + * Copyright (C) 2021, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 pjq first version + */ + + + +#include +#include + +#include "board.h" + +/** + * @addtogroup HC32 + */ + +/*@{*/ + +/** + * @brief BSP clock initialize. + * Set board system clock 24Mhz + * @param None + * @retval None + */ +void rt_hw_board_clock_init(void) +{ + Sysctrl_SetRCHTrim(SysctrlRchFreq24MHz); + Sysctrl_ClkSourceEnable(SysctrlClkRCH, TRUE); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + SystemCoreClockUpdate(); + SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initialize HC32 board. + */ +void rt_hw_board_init() +{ + /* Configure the System clock */ + rt_hw_board_clock_init(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do{ + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while(delta < us_tick * us); +} +/*@}*/ diff --git a/bsp/hc32l136/board/board.h b/bsp/hc32l136/board/board.h new file mode 100644 index 0000000000..6d256c3d2c --- /dev/null +++ b/bsp/hc32l136/board/board.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2021, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 pjq first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ddl.h" +#include "gpio.h" +#include "drv_gpio.h" + +/* board configuration */ +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE 0x2000 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) + +/* High speed sram. */ +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#ifdef __ICCARM__ +#define HEAP_END SRAM_END +#else +#define HEAP_END SRAM_END +#endif + +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); + +#endif + +// <<< Use Configuration Wizard in Context Menu >>> diff --git a/bsp/hc32l136/board/linker_scripts/link.icf b/bsp/hc32l136/board/linker_scripts/link.icf new file mode 100644 index 0000000000..719e8b673c --- /dev/null +++ b/bsp/hc32l136/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0100; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/hc32l136/board/linker_scripts/link.lds b/bsp/hc32l136/board/linker_scripts/link.lds new file mode 100644 index 0000000000..af109a6da6 --- /dev/null +++ b/bsp/hc32l136/board/linker_scripts/link.lds @@ -0,0 +1,203 @@ + /** + ******************************************************************************* + * @file hc32f4a0_flash.lds + * @brief Linker script for HC32F4A0 Device with 2MByte FLASH, 512KByte RAM. + @verbatim + Change Logs: + Date Author Notes + 2020-09-15 Chengy First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP (rx): ORIGIN = 0x03000000, LENGTH = 6876 + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_sec : + { + KEEP(*(.otp_sec)) + } >OTP + + .otp_lock_sec 0x03001800 : + { + KEEP(*(.otp_lock_sec)) + } >OTP + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32l136/board/linker_scripts/link.sct b/bsp/hc32l136/board/linker_scripts/link.sct new file mode 100644 index 0000000000..7cc97595b0 --- /dev/null +++ b/bsp/hc32l136/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x10000 { ; load region size_region + ER_IROM1 0x00000000 0x10000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x2000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32l136/drivers/SConscript b/bsp/hc32l136/drivers/SConscript new file mode 100644 index 0000000000..f37a9f6386 --- /dev/null +++ b/bsp/hc32l136/drivers/SConscript @@ -0,0 +1,22 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" + +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + src += ['drv_soft_i2c.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32l136/drivers/drv_gpio.c b/bsp/hc32l136/drivers/drv_gpio.c new file mode 100644 index 0000000000..0d1798dd03 --- /dev/null +++ b/bsp/hc32l136/drivers/drv_gpio.c @@ -0,0 +1,381 @@ +/* + * Copyright (C) 2021, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 pjq first version + */ + +#include +#include "rthw.h" + +#ifdef RT_USING_PIN +#include "gpio.h" +#include "drv_gpio.h" +#include "interrupts_hc32l136.h" + +#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F)) +#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) * 0x40u)) +#define GPIO_PIN(pin) ((uint16_t)(GPIO_PIN_INDEX(pin))) + +#define PIN_NUM(port, pin) (((((port) / 0x40u) << 4) | ((pin) & 0x0F))) +#define PIN_MAX_NUM ((GpioPortD / 0x40u * 16) + (GpioPin15 + 1)) + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + +}; + +static void pin_irq_handler(en_gpio_port_t port, en_gpio_pin_t pin) +{ + rt_int32_t irqindex = -1; + + irqindex = PIN_NUM(port, pin); + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } +} + +void Gpio_IRQHandler(uint8_t u8Param) +{ + en_gpio_pin_t i; + en_gpio_port_t enPort; + + enPort = (en_gpio_port_t)(GpioPortA + (GpioPortB - GpioPortA) * u8Param); + rt_interrupt_enter(); + for (i=GpioPin0; i<=GpioPin15; i++) + { + if(TRUE == Gpio_GetIrqStatus(enPort, i)) + { + Gpio_ClearIrq(enPort, i); + pin_irq_handler(enPort, i); + } + + } + rt_interrupt_leave(); +} + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (PIN_LOW == value) + { + Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, FALSE); + } + else + { + Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, TRUE); + } + } +} + +static int _pin_read(rt_device_t dev, rt_base_t pin) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (FALSE == Gpio_GetInputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin)) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + } + + return value; +} + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + stc_gpio_config_t pstcGpioCfg; + + memset(&pstcGpioCfg, 0, sizeof(pstcGpioCfg)); + if (pin >= PIN_MAX_NUM) + { + return; + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + pstcGpioCfg.enDir = GpioDirOut; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_INPUT: + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPu; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_INPUT_PULLUP: + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPu; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_INPUT_PULLDOWN: + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPd; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + case PIN_MODE_OUTPUT_OD: + pstcGpioCfg.enDir = GpioDirOut; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enOD = GpioOdEnable; + pstcGpioCfg.enCtrlMode = GpioAHB; + break; + default: + break; + } + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg); +} + +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = pin; + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = pin; + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + rt_base_t level; + en_gpio_port_t gpio_port; + en_gpio_pin_t gpio_pin; + rt_int32_t irqindex; + stc_gpio_config_t pstcGpioCfg; + + if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled))) + { + return -RT_ENOSYS; + } + + irqindex = pin; + gpio_port = (en_gpio_port_t)GPIO_PORT(pin); + gpio_pin = (en_gpio_pin_t)GPIO_PIN(pin); + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Exint config */ + pstcGpioCfg.enDir = GpioDirIn; + pstcGpioCfg.enDrv = GpioDrvL; + pstcGpioCfg.enPuPd = GpioPu; + pstcGpioCfg.enOD = GpioOdDisable; + pstcGpioCfg.enCtrlMode = GpioAHB; + Gpio_Init(gpio_port, gpio_pin, &pstcGpioCfg); + Gpio_ClearIrq(gpio_port, gpio_pin); + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqRising); + break; + case PIN_IRQ_MODE_FALLING: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqHigh); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqLow); + break; + } + EnableNvic((IRQn_Type)(pin / 16), IrqLevel3, TRUE); + + rt_hw_interrupt_enable(level); + } + else + { + level = rt_hw_interrupt_disable(); + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqRising); + break; + case PIN_IRQ_MODE_FALLING: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling); + break; + case PIN_IRQ_MODE_RISING_FALLING: + + break; + case PIN_IRQ_MODE_LOW_LEVEL: + Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqLow); + break; + } + rt_hw_interrupt_enable(level); + } + + return RT_EOK; +} + +static const struct rt_pin_ops _pin_ops = +{ + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_detach_irq, + _pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE); + + return rt_device_pin_register("pin", &_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/hc32l136/drivers/drv_gpio.h b/bsp/hc32l136/drivers/drv_gpio.h new file mode 100644 index 0000000000..bc07777b90 --- /dev/null +++ b/bsp/hc32l136/drivers/drv_gpio.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2021, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 pjq first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include + +#ifdef RT_USING_PIN + +#define __HC_PORT(port) GpioPort##port +#define GET_PIN(PORT, PIN) (((rt_uint16_t)__HC_PORT(PORT) / 0x40 * 16) + PIN) + +#ifndef EXINT0_IRQ_CONFIG +#define EXINT0_IRQ_CONFIG \ + { \ + .irq = EXINT0_INT_IRQn, \ + .irq_prio = EXINT0_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT1_IRQ_CONFIG +#define EXINT1_IRQ_CONFIG \ + { \ + .irq = EXINT1_INT_IRQn, \ + .irq_prio = EXINT1_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT2_IRQ_CONFIG +#define EXINT2_IRQ_CONFIG \ + { \ + .irq = EXINT2_INT_IRQn, \ + .irq_prio = EXINT2_INT_PRIO, \ + } +#endif /* EXINT2_IRQ_CONFIG */ + +#ifndef EXINT3_IRQ_CONFIG +#define EXINT3_IRQ_CONFIG \ + { \ + .irq = EXINT3_INT_IRQn, \ + .irq_prio = EXINT3_INT_PRIO, \ + } +#endif /* EXINT3_IRQ_CONFIG */ + +#ifndef EXINT4_IRQ_CONFIG +#define EXINT4_IRQ_CONFIG \ + { \ + .irq = EXINT4_INT_IRQn, \ + .irq_prio = EXINT4_INT_PRIO, \ + } +#endif /* EXINT4_IRQ_CONFIG */ + +#ifndef EXINT5_IRQ_CONFIG +#define EXINT5_IRQ_CONFIG \ + { \ + .irq = EXINT5_INT_IRQn, \ + .irq_prio = EXINT5_INT_PRIO, \ + } +#endif /* EXINT5_IRQ_CONFIG */ + +#ifndef EXINT6_IRQ_CONFIG +#define EXINT6_IRQ_CONFIG \ + { \ + .irq = EXINT6_INT_IRQn, \ + .irq_prio = EXINT6_INT_PRIO, \ + } +#endif /* EXINT6_IRQ_CONFIG */ + +#ifndef EXINT7_IRQ_CONFIG +#define EXINT7_IRQ_CONFIG \ + { \ + .irq = EXINT7_INT_IRQn, \ + .irq_prio = EXINT7_INT_PRIO, \ + } +#endif /* EXINT7_IRQ_CONFIG */ + +#ifndef EXINT8_IRQ_CONFIG +#define EXINT8_IRQ_CONFIG \ + { \ + .irq = EXINT8_INT_IRQn, \ + .irq_prio = EXINT8_INT_PRIO, \ + } +#endif /* EXINT8_IRQ_CONFIG */ + +#ifndef EXINT9_IRQ_CONFIG +#define EXINT9_IRQ_CONFIG \ + { \ + .irq = EXINT9_INT_IRQn, \ + .irq_prio = EXINT9_INT_PRIO, \ + } +#endif /* EXINT9_IRQ_CONFIG */ + +#ifndef EXINT10_IRQ_CONFIG +#define EXINT10_IRQ_CONFIG \ + { \ + .irq = EXINT10_INT_IRQn, \ + .irq_prio = EXINT10_INT_PRIO, \ + } +#endif /* EXINT10_IRQ_CONFIG */ + +#ifndef EXINT11_IRQ_CONFIG +#define EXINT11_IRQ_CONFIG \ + { \ + .irq = EXINT11_INT_IRQn, \ + .irq_prio = EXINT11_INT_PRIO, \ + } +#endif /* EXINT11_IRQ_CONFIG */ + +#ifndef EXINT12_IRQ_CONFIG +#define EXINT12_IRQ_CONFIG \ + { \ + .irq = EXINT12_INT_IRQn, \ + .irq_prio = EXINT12_INT_PRIO, \ + } +#endif /* EXINT12_IRQ_CONFIG */ + +#ifndef EXINT13_IRQ_CONFIG +#define EXINT13_IRQ_CONFIG \ + { \ + .irq = EXINT13_INT_IRQn, \ + .irq_prio = EXINT13_INT_PRIO, \ + } +#endif /* EXINT13_IRQ_CONFIG */ + +#ifndef EXINT14_IRQ_CONFIG +#define EXINT14_IRQ_CONFIG \ + { \ + .irq = EXINT14_INT_IRQn, \ + .irq_prio = EXINT14_INT_PRIO, \ + } +#endif /* EXINT14_IRQ_CONFIG */ + +#ifndef EXINT15_IRQ_CONFIG +#define EXINT15_IRQ_CONFIG \ + { \ + .irq = EXINT15_INT_IRQn, \ + .irq_prio = EXINT15_INT_PRIO, \ + } +#endif /* EXINT15_IRQ_CONFIG */ + +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/hc32l136/drivers/drv_usart.c b/bsp/hc32l136/drivers/drv_usart.c new file mode 100644 index 0000000000..7f81374dbb --- /dev/null +++ b/bsp/hc32l136/drivers/drv_usart.c @@ -0,0 +1,622 @@ +/* + * Copyright (C) 2021, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 pjq first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include +#include "gpio.h" +#include "uart.h" +#include "drv_usart.h" + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) +#error "Please define at least one BSP_USING_UARTx" +/* UART instance can be selected at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */ +#endif + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/* HC32 config Rx timeout */ +struct hc32_uart_rxto +{ + rt_uint32_t channel; + rt_size_t timeout_bits; +}; + +/* HC32 UART index */ +struct uart_index +{ + rt_uint8_t index; + rt_uint8_t idx; +}; + +/* HC32 UART irq handler */ +struct uart_irq_handler +{ + void (*tx_irq_handler)(void); + void (*rxerr_irq_handler)(void); + void (*rx_irq_handler)(void); + void (*cts_irq_handler)(void); + void (*pei_irq_handler)(void); +}; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +#ifdef RT_SERIAL_USING_DMA +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +enum +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif + UART_INDEX_MAX, +}; + +static const struct uart_index uart_map[] = +{ +#ifdef BSP_USING_UART0 + {UART0_INDEX, UARTCH0}, +#endif +#ifdef BSP_USING_UART1 + {UART1_INDEX, UARTCH1}, +#endif +}; + +static struct hc32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART0 + { \ + .name = "uart0", \ + .idx = UARTCH0, \ + }, +#endif +#ifdef BSP_USING_UART1 + { \ + .name = "uart1", \ + .idx = UARTCH1, \ + } +#endif +}; + +#ifdef BSP_USING_UART0 +static int uart0_rx_flag; +#endif +#ifdef BSP_USING_UART1 +static int uart1_rx_flag; +#endif +static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +static const struct uart_irq_handler uart_irq_handlers[sizeof(uart_obj) / sizeof(uart_obj[0])]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +//static uint32_t hc32_get_uart_index(M0P_UART_TypeDef *Instance) +static uint32_t hc32_get_uart_index(uint8_t idx) +{ + uint32_t index = UART_INDEX_MAX; + + for (uint8_t i = 0U; i < ARRAY_SZ(uart_map); i++) + { + if (uart_map[i].idx == idx) + { + index = uart_map[i].index; + RT_ASSERT(index < UART_INDEX_MAX) + break; + } + } + + return index; +} + +#if defined(BSP_USING_UART0) +void uart0_gpioinit(void) +{ + stc_gpio_config_t stcGpioCfg; + DDL_ZERO_STRUCT(stcGpioCfg); + stcGpioCfg.enDir = GpioDirOut; + Gpio_Init(GpioPortA,GpioPin9,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin9,GpioAf1);//TX + stcGpioCfg.enDir = GpioDirIn; + Gpio_Init(GpioPortA,GpioPin10,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin10,GpioAf1);//RX +} +#endif + +#if defined(BSP_USING_UART1) +void uart1_gpioinit(void) +{ + stc_gpio_config_t stcGpioCfg; + + DDL_ZERO_STRUCT(stcGpioCfg); + stcGpioCfg.enDir = GpioDirOut; + Gpio_Init(GpioPortA,GpioPin2,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin2,GpioAf1);//TX + stcGpioCfg.enDir = GpioDirIn; + Gpio_Init(GpioPortA,GpioPin3,&stcGpioCfg); + Gpio_SetAfMode(GpioPortA,GpioPin3,GpioAf1);//RX +} +#endif + +static rt_err_t hc32_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct hc32_uart *uart; + uint16_t u16Scnt = 0; + stc_uart_config_t stcConfig; + stc_uart_irq_cb_t stcUartIrqCb; + stc_uart_multimode_t stcMulti; + stc_uart_baud_t stcBaud; + uint8_t index; + en_uart_mmdorck_t enTb8; + + DDL_ZERO_STRUCT(stcConfig); + DDL_ZERO_STRUCT(stcUartIrqCb); + DDL_ZERO_STRUCT(stcMulti); + DDL_ZERO_STRUCT(stcBaud); + + RT_ASSERT(RT_NULL != cfg); + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); +#if defined(BSP_USING_UART0) + if (uart->config->idx == UARTCH0) + { + uart0_gpioinit(); + } +#endif + +#if defined(BSP_USING_UART1) + if (uart->config->idx == UARTCH1) + { + uart1_gpioinit(); + } +#endif + + /* Configure USART initialization structure */ + index = hc32_get_uart_index(uart->config->idx); + stcUartIrqCb.pfnRxIrqCb = uart_irq_handlers[index].rx_irq_handler; + stcUartIrqCb.pfnTxIrqCb = uart_irq_handlers[index].tx_irq_handler; + stcUartIrqCb.pfnRxFEIrqCb = uart_irq_handlers[index].rxerr_irq_handler; + stcUartIrqCb.pfnPEIrqCb = uart_irq_handlers[index].pei_irq_handler; + stcUartIrqCb.pfnCtsIrqCb = uart_irq_handlers[index].cts_irq_handler; + stcConfig.pstcIrqCb = &stcUartIrqCb; + stcConfig.bTouchNvic = TRUE; + + stcConfig.enRunMode = UartMode3; + stcMulti.enMulti_mode = UartNormal; + + if(BIT_ORDER_LSB == cfg->bit_order) + { + + } + else + { + + } + + switch(cfg->stop_bits) + { + case STOP_BITS_1: + stcConfig.enStopBit = Uart1bit; + break; + case STOP_BITS_2: + stcConfig.enStopBit = Uart2bit; + break; + default: + break; + } + + switch(cfg->parity) + { + case PARITY_NONE: + enTb8 = UartDataOrAddr; + break; + case PARITY_EVEN: + enTb8 = UartEven; + break; + case PARITY_ODD: + enTb8 = UartOdd; + break; + default: + enTb8 = UartDataOrAddr; + break; + } + + switch(cfg->data_bits) + { + case DATA_BITS_8: + break; + default: + return -RT_ERROR; + } + + Uart_SetMMDOrCk(uart->config->idx, enTb8); + stcConfig.pstcMultiMode = &stcMulti; + Uart_Init(uart->config->idx, &stcConfig); + + Uart_SetClkDiv(uart->config->idx, Uart8Or16Div); + stcBaud.u32Pclk = Sysctrl_GetPClkFreq(); + stcBaud.enRunMode = UartMode3; + stcBaud.u32Baud = cfg->baud_rate; + u16Scnt = Uart_CalScnt(uart->config->idx, &stcBaud); + Uart_SetBaud(uart->config->idx, u16Scnt); + + Uart_ClrStatus(uart->config->idx, UartTC); + Uart_ClrStatus(uart->config->idx, UartRC); + Uart_DisableIrq(uart->config->idx, UartTxIrq); + Uart_DisableIrq(uart->config->idx, UartRxIrq); + Uart_EnableFunc(uart->config->idx, UartRx); + + return RT_EOK; +} + +static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hc32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct hc32_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + Uart_DisableIrq(uart->config->idx, UartRxIrq); + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + Uart_ClrStatus(uart->config->idx, UartRC); + Uart_EnableIrq(uart->config->idx, UartRxIrq); + break; + + case RT_DEVICE_CTRL_CLOSE: + break; + } + + return RT_EOK; +} + +static int hc32_putc(struct rt_serial_device *serial, char c) +{ + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + + if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + if (Uart_GetStatus(uart->config->idx, UartTC) == FALSE) + { + return -1; + } + } + Uart_SendData(uart->config->idx, c); + + return 1; +} + +static int hc32_getc(struct rt_serial_device *serial) +{ + int ch= -1; + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + +#if defined(BSP_USING_UART0) + if (uart->config->idx == UARTCH0) + { + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX) + { + if (uart0_rx_flag) + { + ch = Uart_ReceiveData(uart->config->idx); + uart0_rx_flag = 0; + } + } + else + { + if(Uart_GetStatus(uart->config->idx, UartRC)) + { + Uart_ClrStatus(uart->config->idx, UartRC); + ch = Uart_ReceiveData(uart->config->idx); + } + } + } +#endif +#if defined(BSP_USING_UART1) + if (uart->config->idx == UARTCH1) + { + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX) + { + if (uart1_rx_flag) + { + ch = Uart_ReceiveData(uart->config->idx); + uart1_rx_flag = 0; + } + } + else + { + if(Uart_GetStatus(uart->config->idx, UartRC)) + { + Uart_ClrStatus(uart->config->idx, UartRC); + ch = Uart_ReceiveData(uart->config->idx); + } + } + } +#endif + + return ch; +} + +static rt_size_t hc32_dma_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + int direction) +{ + + return 0; +} + +static void hc32_uart_rx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +} + +static void hc32_uart_tx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); + } +} + +static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); +} + +static void hc32_uart_cts_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); +} + +static void hc32_uart_pei_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); +} + +#ifdef RT_SERIAL_USING_DMA +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + +} +#endif + +#if defined(BSP_USING_UART0) +static void hc32_uart0_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart0_rx_flag = 1; + hc32_uart_rx_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_cts_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_cts_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart0_pei_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_pei_irq_handler(&uart_obj[UART0_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +static void hc32_uart1_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart1_rx_flag = 1; + hc32_uart_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_cts_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_cts_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_pei_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_pei_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +static const struct uart_irq_handler uart_irq_handlers[] = +{ +#ifdef BSP_USING_UART0 + { hc32_uart0_tx_irq_handler, hc32_uart0_rxerr_irq_handler, hc32_uart0_rx_irq_handler, + hc32_uart0_cts_irq_handler, hc32_uart0_pei_irq_handler + }, +#endif +#ifdef BSP_USING_UART1 + { hc32_uart1_tx_irq_handler, hc32_uart1_rxerr_irq_handler, hc32_uart1_rx_irq_handler, + hc32_uart1_cts_irq_handler, hc32_uart1_pei_irq_handler + }, +#endif +}; + +static void hc32_uart_get_dma_config(void) +{ + +} + +static const struct rt_uart_ops hc32_uart_ops = +{ + .configure = hc32_configure, + .control = hc32_control, + .putc = hc32_putc, + .getc = hc32_getc, + .dma_transmit = hc32_dma_transmit +}; + +int hc32_hw_uart_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + hc32_uart_get_dma_config(); + + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio,TRUE); +#ifdef BSP_USING_UART0 + Sysctrl_SetPeripheralGate(SysctrlPeripheralUart0,TRUE); +#endif +#ifdef BSP_USING_UART1 + Sysctrl_SetPeripheralGate(SysctrlPeripheralUart1,TRUE); +#endif + + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].serial.config = config; + uart_obj[i].config = &uart_config[i]; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].config->name, + (RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX | + uart_obj[i].uart_dma_flag), + &uart_obj[i]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +INIT_BOARD_EXPORT(hc32_hw_uart_init); + +#endif /* RT_USING_SERIAL */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/drivers/drv_usart.h b/bsp/hc32l136/drivers/drv_usart.h new file mode 100644 index 0000000000..a948bde5d3 --- /dev/null +++ b/bsp/hc32l136/drivers/drv_usart.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2021, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 pjq first version + */ + + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "rtdevice.h" + +#include "ddl.h" +#include "uart.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* HC32 config uart class */ +struct hc32_uart_config +{ + const char *name; + rt_uint8_t idx; + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +/* stm32 uart dirver class */ +struct hc32_uart +{ + struct hc32_uart_config *config; +#ifdef RT_SERIAL_USING_DMA + +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +int rt_hw_uart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32l136/figures/board.png b/bsp/hc32l136/figures/board.png new file mode 100644 index 0000000000..b5b5b368d1 Binary files /dev/null and b/bsp/hc32l136/figures/board.png differ diff --git a/bsp/hc32l136/project.ewp b/bsp/hc32l136/project.ewp new file mode 100644 index 0000000000..1ed9cb8f20 --- /dev/null +++ b/bsp/hc32l136/project.ewp @@ -0,0 +1,2157 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + CPU + + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m0\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m0\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\drivers\drv_gpio.c + + + $PROJ_DIR$\drivers\drv_usart.c + + + + finsh + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + + HC32_StdPeriph + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\adc.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\ddl.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\flash.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\gpio.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32L136\Source\interrupts_hc32l136.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\lpuart.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\rtc.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32L136\Source\IAR\startup_hc32l136.s + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\sysctrl.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32L136\Source\system_hc32l13x.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\timer3.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\trim.c + + + $PROJ_DIR$\Libraries\HC32L136_StdPeriph_Driver\src\uart.c + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\components.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + + diff --git a/bsp/hc32l136/project.eww b/bsp/hc32l136/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/hc32l136/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/hc32l136/project.uvoptx b/bsp/hc32l136/project.uvoptx new file mode 100644 index 0000000000..27cc1f022c --- /dev/null +++ b/bsp/hc32l136/project.uvoptx @@ -0,0 +1,924 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + -U -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K.FLM -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM) + + + 0 + JL2CM3 + -U4294967295 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC2000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + 2 + 6 + 2 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 16 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 22 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 5 + 23 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 24 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_compiler.c + finsh_compiler.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_error.c + finsh_error.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_init.c + finsh_init.c + 0 + 0 + + + + + HC32_StdPeriph + 0 + 0 + 0 + 0 + + 6 + 32 + 2 + 0 + 0 + 0 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\ARM\startup_hc32l136.s + startup_hc32l136.s + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\trim.c + trim.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\system_hc32l13x.c + system_hc32l13x.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\interrupts_hc32l136.c + interrupts_hc32l136.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\uart.c + uart.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\sysctrl.c + sysctrl.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\gpio.c + gpio.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\ddl.c + ddl.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\timer3.c + timer3.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\flash.c + flash.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\lpuart.c + lpuart.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\rtc.c + rtc.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + Libraries\HC32L136_StdPeriph_Driver\src\adc.c + adc.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + ..\..\src\components.c + components.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\..\src\object.c + object.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + 0 + 0 + + + + diff --git a/bsp/hc32l136/project.uvprojx b/bsp/hc32l136/project.uvprojx new file mode 100644 index 0000000000..c6f27013bd --- /dev/null +++ b/bsp/hc32l136/project.uvprojx @@ -0,0 +1,713 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + HC32L136K8TA + HDSC + HDSC.HC32L136.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x20000000,0x2000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM)) + 0 + $$Device:HC32L136K8TA$Device\Include\HC32L136K8TA.h + + + + + + + + + + $$Device:HC32L136K8TA$SVD\HC32L136K8TA.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + USE_DDL_DRIVER, __DEBUG, __RTTHREAD__, HC32L136, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;board;drivers;..\..\components\finsh;Libraries\CMSIS\Include;Libraries\CMSIS\Device\HDSC\HC32L136\Include;Libraries\HC32L136_StdPeriph_Driver\inc;.;..\..\include;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_usart.c + 1 + drivers\drv_usart.c + + + + + finsh + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + HC32_StdPeriph + + + startup_hc32l136.s + 2 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\ARM\startup_hc32l136.s + + + trim.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\trim.c + + + system_hc32l13x.c + 1 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\system_hc32l13x.c + + + interrupts_hc32l136.c + 1 + Libraries\CMSIS\Device\HDSC\HC32L136\Source\interrupts_hc32l136.c + + + uart.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\uart.c + + + sysctrl.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\sysctrl.c + + + gpio.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\gpio.c + + + ddl.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\ddl.c + + + timer3.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\timer3.c + + + flash.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\flash.c + + + lpuart.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\lpuart.c + + + rtc.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\rtc.c + + + adc.c + 1 + Libraries\HC32L136_StdPeriph_Driver\src\adc.c + + + + + Kernel + + + mem.c + 1 + ..\..\src\mem.c + + + clock.c + 1 + ..\..\src\clock.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + idle.c + 1 + ..\..\src\idle.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + irq.c + 1 + ..\..\src\irq.c + + + timer.c + 1 + ..\..\src\timer.c + + + components.c + 1 + ..\..\src\components.c + + + object.c + 1 + ..\..\src\object.c + + + device.c + 1 + ..\..\src\device.c + + + thread.c + 1 + ..\..\src\thread.c + + + + + + + + + + + + + + diff --git a/bsp/hc32l136/rtconfig.h b/bsp/hc32l136/rtconfig.h new file mode 100644 index 0000000000..68c2c571d6 --- /dev/null +++ b/bsp/hc32l136/rtconfig.h @@ -0,0 +1,180 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +//#define RT_USING_TIMER_SOFT +//#define RT_TIMER_THREAD_PRIO 4 +//#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 512 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 512 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define MCU_HC32L136 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/hc32l136/rtconfig.py b/bsp/hc32l136/rtconfig.py new file mode 100644 index 0000000000..4556c8a87e --- /dev/null +++ b/bsp/hc32l136/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='iar' + +print "############rtconfig##############" + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +print "CROSS_TOOL: " + CROSS_TOOL + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:\03_software\Program Files\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:\03_software\Program Files\IAR Systems\Embedded Workbench 7.5' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +MCU_TYPE = 'HC32L136' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall -DHC32F4A0 -D__DEBUG -DUSE_DDL_DRIVER -D__ASSEMBLY__ -D__FPU_USED' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m0.fp' + CFLAGS = DEVICE + ' --apcs=interwork -DUSE_DDL_DRIVER -DHC32F4A0 -D__DEBUG' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/link.sct"' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D __DEBUG' + ' -D USE_DDL_DRIVER' + ' -D HC32F4A0' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/hc32l136/template.ewp b/bsp/hc32l136/template.ewp new file mode 100644 index 0000000000..4e56df1965 --- /dev/null +++ b/bsp/hc32l136/template.ewp @@ -0,0 +1,1933 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 18 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32l136/template.eww b/bsp/hc32l136/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/hc32l136/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32l136/template.uvoptx b/bsp/hc32l136/template.uvoptx new file mode 100644 index 0000000000..53cd00988b --- /dev/null +++ b/bsp/hc32l136/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + -U -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K.FLM -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM) + + + 0 + JL2CM3 + -U4294967295 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC2000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32l136/template.uvprojx b/bsp/hc32l136/template.uvprojx new file mode 100644 index 0000000000..c40f7d0bf7 --- /dev/null +++ b/bsp/hc32l136/template.uvprojx @@ -0,0 +1,391 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + 0 + + + HC32L136K8TA + HDSC + HDSC.HC32L136.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x20000000,0x2000) IROM(0x00000000,0x10000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FlashHC32L136_64K -FS00 -FL010000 -FP0($$Device:HC32L136K8TA$Flash\FlashHC32L136_64K.FLM)) + 0 + $$Device:HC32L136K8TA$Device\Include\HC32L136K8TA.h + + + + + + + + + + $$Device:HC32L136K8TA$SVD\HC32L136K8TA.sfr + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + __DEBUG,HC32F4A0,USE_DDL_DRIVER + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + --keep=*Handler + + + + + + + + + + + + + + +