mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-08-18 11:53:05 +08:00
[BSP] move libcpu/mips/x1000 to bsp/x1000/cpu
This commit is contained in:
Bernard Xiong
@@ -1,14 +0,0 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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ASFLAGS = ''
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group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
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Return('group')
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@@ -1,217 +0,0 @@
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/*
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* File : cache.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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||||
*
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* Change Logs:
|
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* Date Author Notes
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* 2016/11/02 Urey the first version
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*/
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#include <rtthread.h>
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#include <board.h>
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#include <rthw.h>
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#include "../common/mips.h"
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#define CONFIG_SYS_DCACHE_SIZE 16384
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#define CONFIG_SYS_ICACHE_SIZE 16384
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define K0_TO_K1() \
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do { \
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unsigned long __k0_addr; \
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\
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__asm__ __volatile__( \
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"la %0, 1f\n\t" \
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"or %0, %0, %1\n\t" \
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"jr %0\n\t" \
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"nop\n\t" \
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"1: nop\n" \
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: "=&r"(__k0_addr) \
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: "r" (0x20000000) ); \
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} while(0)
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#define K1_TO_K0() \
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do { \
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unsigned long __k0_addr; \
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__asm__ __volatile__( \
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"nop;nop;nop;nop;nop;nop;nop\n\t" \
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"la %0, 1f\n\t" \
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"jr %0\n\t" \
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"nop\n\t" \
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"1: nop\n" \
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: "=&r" (__k0_addr)); \
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} while (0)
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#define INVALIDATE_BTB() \
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do { \
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unsigned long tmp; \
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__asm__ __volatile__( \
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".set mips32\n\t" \
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"mfc0 %0, $16, 7\n\t" \
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"nop\n\t" \
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"ori %0, 2\n\t" \
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"mtc0 %0, $16, 7\n\t" \
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"nop\n\t" \
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".set mips2\n\t" \
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: "=&r" (tmp)); \
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} while (0)
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#define __sync() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips2\n\t" \
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"sync\n\t" \
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".set pop" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#if defined(JZ4775) || defined(X1000)
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#define SYNC_WB() \
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do { \
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__asm__ __volatile__ ( \
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"sync\n\t" \
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"lw $0, %0\n\t" \
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: \
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:"m"(*(int *)0xa0000000) \
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:"memory"); \
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} while (0)
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#else
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#error "not define sync wb"
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#define SYNC_WB() __asm__ __volatile__ ("sync")
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#endif
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#undef cache_op
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#define cache_op(op, addr) \
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__asm__ __volatile__( \
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".set push\n" \
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".set noreorder\n" \
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".set mips3\n" \
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"cache %0, %1\n" \
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".set pop\n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void rt_hw_dcache_flush_line(rt_uint32_t addr)
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{
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cache_op(HIT_WRITEBACK_INV_D, addr);
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SYNC_WB();
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}
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void rt_hw_dcache_flush_range(rt_uint32_t start_addr, rt_uint32_t size)
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{
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rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
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rt_uint32_t addr = start_addr & ~(lsize - 1);
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rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
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rt_uint32_t writebuffer;
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for (; addr <= aend; addr += lsize)
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{
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cache_op(HIT_WRITEBACK_INV_D, addr);
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}
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SYNC_WB();
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}
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void rt_hw_dcache_flush_all(void)
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{
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rt_uint32_t addr;
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
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{
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cache_op(INDEX_WRITEBACK_INV_D, addr);
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}
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SYNC_WB();
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}
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void rt_hw_dcache_invalidate_range(rt_uint32_t start_addr,rt_uint32_t size)
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{
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rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE;
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rt_uint32_t addr = start_addr & ~(lsize - 1);
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rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize)
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cache_op(HIT_INVALIDATE_D, addr);
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}
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void rt_hw_dcache_invalidate_all(void)
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{
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rt_uint32_t addr;
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
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{
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cache_op(INDEX_STORE_TAG_D, addr);
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}
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SYNC_WB();
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}
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void rt_hw_icache_flush_line(rt_uint32_t addr)
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{
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cache_op(HIT_INVALIDATE_I, addr);
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}
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void rt_hw_icache_flush_all(void)
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{
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rt_uint32_t addr;
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asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
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asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
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{
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cache_op(INDEX_STORE_TAG_I, addr);
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}
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INVALIDATE_BTB();
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}
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void rt_hw_icache_invalidate_all(void)
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{
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rt_uint32_t i;
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K0_TO_K1();
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asm volatile (".set noreorder\n"
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".set mips32\n\t"
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"mtc0\t$0,$28\n\t"
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"mtc0\t$0,$29\n"
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".set mips0\n"
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".set reorder\n");
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for (i = CKSEG0; i < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
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cache_op(INDEX_STORE_TAG_I, i);
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K1_TO_K0();
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INVALIDATE_BTB();
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}
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void rt_hw_flush_cache_all(void)
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{
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rt_hw_dcache_flush_all();
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rt_hw_icache_flush_all();
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}
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@@ -1,41 +0,0 @@
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/*
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* File : cache.h
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||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ19ÈÕ Urey the first version
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*/
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#ifndef _X1000_CACHE_H_
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#define _X1000_CACHE_H_
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#include "../common/mips.h"
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#include "../common/mips_cache.h"
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void rt_hw_icache_invalidate_all(void);
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void rt_hw_icache_flush_all(void);
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void rt_hw_dcache_flush_all(void);
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void rt_hw_dcache_flush_range(rt_uint32_t addr, rt_uint32_t size);
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void rt_hw_dcache_invalidate_all(void);
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void rt_hw_dcache_invalidate_range(rt_uint32_t addr,rt_uint32_t size);
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void rt_hw_flush_cache_all(void);
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#endif /* _X1000_CACHE_H_ */
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@@ -1,131 +0,0 @@
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/*
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||||
* File : cpu.c
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||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ8ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
|
||||
#include <rtthread.h>
|
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#include <board.h>
|
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#include <rthw.h>
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
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mips32_core_cfg_t g_mips_core =
|
||||
{
|
||||
.icache_line_size = 32,
|
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.icache_size = 16384,
|
||||
|
||||
.dcache_line_size = 32,
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.dcache_size = 16384,
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||||
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.max_tlb_entries = 16, /* max_tlb_entries */
|
||||
};
|
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|
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void rt_hw_tlb_init(void)
|
||||
{
|
||||
//----------------------------------------------------------------------------------
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||||
//cchappy tlb 0x30000000 to 0xC0000000
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//----------------------------------------------------------------------------------
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unsigned int pagemask = 0x007fe000;//0x01ffe000; /* 4MB */
|
||||
/* cached D:allow-W V:valid G */
|
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unsigned int entrylo0 = (0x30000000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
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unsigned int entrylo1 = (0x30400000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
|
||||
unsigned int entryhi = 0xc0000000; /* kseg2 base */
|
||||
int i;
|
||||
__write_32bit_c0_register($5, 4, 0xa9000000);
|
||||
write_c0_pagemask(pagemask);
|
||||
write_c0_wired(0);
|
||||
/* indexed write 32 tlb entry */
|
||||
for(i = 0; i < 32; i++)
|
||||
{
|
||||
asm (
|
||||
".macro _ssnop; sll $0, $0, 1; .endm\n\t"
|
||||
".macro _ehb; sll $0, $0, 3; .endm\n\t"
|
||||
".macro mtc0_tlbw_hazard; _ssnop; _ssnop; _ehb; .endm\n\t"
|
||||
".macro tlbw_use_hazard; _ssnop; _ssnop; _ssnop; _ehb; .endm\n\t"
|
||||
"\n\t"
|
||||
"mtc0 %0, $0\n\t" /* write Index */
|
||||
"tlbw_use_hazard\n\t"
|
||||
"mtc0 %1, $5\n\t" /* write PageMask */
|
||||
"mtc0 %2, $10\n\t" /* write EntryHi */
|
||||
"mtc0 %3, $2\n\t" /* write EntryLo0 */
|
||||
"mtc0 %4, $3\n\t" /* write EntryLo1 */
|
||||
"mtc0_tlbw_hazard\n\t"
|
||||
"tlbwi \n\t" /* TLB indexed write */
|
||||
"tlbw_use_hazard\n\t"
|
||||
: : "Jr" (i), "r" (pagemask), "r" (entryhi),
|
||||
"r" (entrylo0), "r" (entrylo1)
|
||||
);
|
||||
entryhi += 0x0800000; /* 32MB */
|
||||
entrylo0 += (0x0800000 >> 6);
|
||||
entrylo1 += (0x0800000 >> 6);
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_cache_init(void)
|
||||
{
|
||||
r4k_cache_flush_all();
|
||||
}
|
||||
|
||||
/**
|
||||
* this function will reset CPU
|
||||
*
|
||||
*/
|
||||
RT_WEAK void rt_hw_cpu_reset()
|
||||
{
|
||||
/* open the watch-dog */
|
||||
REG_WDT_TCSR = WDT_TCSR_EXT_EN;
|
||||
REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
|
||||
REG_WDT_TDR = 0x03;
|
||||
REG_WDT_TCNT = 0x00;
|
||||
REG_WDT_TCER |= WDT_TCER_TCEN;
|
||||
|
||||
rt_kprintf("reboot system...\n");
|
||||
rt_hw_interrupt_disable();
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* this function will shutdown CPU
|
||||
*
|
||||
*/
|
||||
RT_WEAK void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_kprintf("shutdown...\n");
|
||||
rt_hw_interrupt_disable();
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function finds the first bit set (beginning with the least significant bit)
|
||||
* in value and return the index of that bit.
|
||||
*
|
||||
* Bits are numbered starting at 1 (the least significant bit). A return value of
|
||||
* zero from any of these functions means that the argument was zero.
|
||||
*
|
||||
* @return return the index of the first bit set. If value is 0, then this function
|
||||
* shall return 0.
|
||||
*/
|
||||
RT_WEAK int __rt_ffs(int value)
|
||||
{
|
||||
return __builtin_ffs(value);
|
||||
}
|
||||
@@ -1,215 +0,0 @@
|
||||
/*
|
||||
* File : cpu_intc.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016/09/07 Urey the first version
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
||||
#define INTERRUPTS_MAX 64
|
||||
|
||||
extern rt_uint32_t rt_interrupt_nest;
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
static struct rt_irq_desc isr_table[INTERRUPTS_MAX];
|
||||
|
||||
static void rt_hw_interrupt_handler(int vector, void *param)
|
||||
{
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
rt_int32_t idx;
|
||||
|
||||
clear_c0_status(0xff04); /* clear ERL */
|
||||
set_c0_status(0x0400); /* set IP2 */
|
||||
|
||||
|
||||
rt_memset(isr_table, 0x00, sizeof(isr_table));
|
||||
for (idx = 0; idx < INTERRUPTS_MAX; idx ++)
|
||||
{
|
||||
isr_table[idx].handler = rt_hw_interrupt_handler;
|
||||
}
|
||||
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrupt_flag = 0;
|
||||
|
||||
/* enable cpu interrupt mask */
|
||||
set_c0_status(IE_IRQ0 | IE_IRQ1);
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
/* mask interrupt */
|
||||
__intc_mask_irq(vector);
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
__intc_unmask_irq(vector);
|
||||
}
|
||||
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if(vector < INTERRUPTS_MAX)
|
||||
{
|
||||
old_handler = isr_table[vector].handler;
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
isr_table[vector].handler = handler;
|
||||
isr_table[vector].param = param;
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
rt_inline int fls(int x)
|
||||
{
|
||||
__asm__("clz %0, %1" : "=r" (x) : "r" (x));
|
||||
|
||||
return 32 - x;
|
||||
}
|
||||
|
||||
void rt_interrupt_dispatch(void *ptreg)
|
||||
{
|
||||
void *param;
|
||||
rt_isr_handler_t irq_func;
|
||||
|
||||
int irq = 0, group;
|
||||
rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0;
|
||||
|
||||
rt_uint32_t c0_status, c0_cause;
|
||||
rt_uint32_t pending_im;
|
||||
|
||||
/* check os timer */
|
||||
c0_status = read_c0_status();
|
||||
c0_cause = read_c0_cause();
|
||||
|
||||
pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM);
|
||||
|
||||
if (pending_im & CAUSEF_IP3)
|
||||
{
|
||||
extern void rt_hw_ost_handler(void);
|
||||
rt_hw_ost_handler();
|
||||
return;
|
||||
}
|
||||
if (pending_im & CAUSEF_IP2)
|
||||
{
|
||||
intc_ipr0 = REG_INTC_IPR(0);
|
||||
intc_ipr1 = REG_INTC_IPR(1);
|
||||
|
||||
if (intc_ipr0)
|
||||
{
|
||||
irq = fls(intc_ipr0) - 1;
|
||||
intc_ipr0 &= ~(1<<irq);
|
||||
}
|
||||
else if(intc_ipr1)
|
||||
{
|
||||
irq = fls(intc_ipr1) - 1;
|
||||
intc_ipr1 &= ~(1<<irq);
|
||||
irq += 32;
|
||||
}
|
||||
else
|
||||
{
|
||||
//VPU
|
||||
}
|
||||
|
||||
if (irq >= INTERRUPTS_MAX)
|
||||
rt_kprintf("max interrupt, irq=%d\n", irq);
|
||||
|
||||
/* do interrupt */
|
||||
irq_func = isr_table[irq].handler;
|
||||
param = isr_table[irq].param;
|
||||
(*irq_func)(irq, param);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[irq].counter++;
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
|
||||
/* ack interrupt */
|
||||
__intc_ack_irq(irq);
|
||||
}
|
||||
|
||||
if (pending_im & CAUSEF_IP0)
|
||||
rt_kprintf("CAUSEF_IP0\n");
|
||||
if (pending_im & CAUSEF_IP1)
|
||||
rt_kprintf("CAUSEF_IP1\n");
|
||||
if (pending_im & CAUSEF_IP4)
|
||||
rt_kprintf("CAUSEF_IP4\n");
|
||||
if (pending_im & CAUSEF_IP5)
|
||||
rt_kprintf("CAUSEF_IP5\n");
|
||||
if (pending_im & CAUSEF_IP6)
|
||||
rt_kprintf("CAUSEF_IP6\n");
|
||||
if (pending_im & CAUSEF_IP7)
|
||||
rt_kprintf("CAUSEF_IP7\n");
|
||||
}
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
#include <finsh.h>
|
||||
int list_irqs(void)
|
||||
{
|
||||
int index;
|
||||
|
||||
rt_kprintf("interrupt list:\n");
|
||||
rt_kprintf("----------------\n");
|
||||
rt_kprintf("name counter\n");
|
||||
for (index = 0; index < INTERRUPTS_MAX; index ++)
|
||||
{
|
||||
if (isr_table[index].handler != rt_hw_interrupt_handler)
|
||||
{
|
||||
rt_kprintf("%-*.*s %d\n", RT_NAME_MAX, RT_NAME_MAX, isr_table[index].name, isr_table[index].counter);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
MSH_CMD_EXPORT(list_irqs, list interrupt counter);
|
||||
#endif
|
||||
|
||||
unsigned int spin_lock_irqsave(void)
|
||||
{
|
||||
register unsigned int t;
|
||||
t = read_c0_status();
|
||||
write_c0_status((t & (~1)));
|
||||
return (t);
|
||||
}
|
||||
|
||||
void spin_unlock_irqrestore(unsigned int val)
|
||||
{
|
||||
write_c0_status(val);
|
||||
}
|
||||
@@ -1,208 +0,0 @@
|
||||
/*
|
||||
* File : mips_backtrace.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ11ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "mips.h"
|
||||
|
||||
/*********************************************************************************************************
|
||||
Ö¸ÁÒå
|
||||
*********************************************************************************************************/
|
||||
#define ADDUI_SP_INST 0x27bd0000
|
||||
#define SW_RA_INST 0xafbf0000
|
||||
#define JR_RA_INST 0x03e00008
|
||||
|
||||
#define INST_OP_MASK 0xffff0000
|
||||
#define INST_OFFSET_MASK 0x0000ffff
|
||||
|
||||
#define abs(s) ((s) < 0 ? -(s):(s))
|
||||
|
||||
int backtrace_ctx(mips_reg_ctx *ctx)
|
||||
{
|
||||
unsigned long *addr;
|
||||
unsigned long *pc, *ra, *sp;
|
||||
size_t ra_offset;
|
||||
size_t stack_size;
|
||||
int depth;
|
||||
int size = 8;
|
||||
|
||||
pc = (unsigned long *)(unsigned long)ctx->CP0EPC;
|
||||
ra = (unsigned long *)(unsigned long)ctx->regs[REG_RA];
|
||||
sp = (unsigned long *)(unsigned long)ctx->regs[REG_SP];
|
||||
|
||||
rt_kprintf("[0x%08x]\n", pc);
|
||||
|
||||
if (size == 1) return 1;
|
||||
|
||||
ra_offset = stack_size = 0;
|
||||
|
||||
for (addr = ra; !ra_offset || !stack_size; --addr)
|
||||
{
|
||||
switch (*addr & INST_OP_MASK) {
|
||||
case ADDUI_SP_INST:
|
||||
stack_size = abs((short)(*addr&INST_OFFSET_MASK));
|
||||
break;
|
||||
|
||||
case SW_RA_INST:
|
||||
ra_offset = (short)(*addr&INST_OFFSET_MASK);
|
||||
break;
|
||||
|
||||
case 0x3c1c0000:
|
||||
goto out_of_loop;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
out_of_loop:
|
||||
if (ra_offset) ra = *(unsigned long **)((unsigned long)sp + ra_offset);
|
||||
if (stack_size) sp = (unsigned long *)((unsigned long)sp + stack_size);
|
||||
|
||||
// repeat backwar scanning
|
||||
for (depth = 1; depth < size && ra && ra != (unsigned long *)0xffffffff; ++depth)
|
||||
{
|
||||
rt_kprintf("RA[%2d] : [0x%08x]\n", depth ,ra);
|
||||
|
||||
ra_offset = 0;
|
||||
stack_size = 0;
|
||||
|
||||
for ( addr = ra; !ra_offset || !stack_size; -- addr )
|
||||
{
|
||||
switch( *addr & INST_OP_MASK)
|
||||
{
|
||||
case ADDUI_SP_INST:
|
||||
stack_size = abs((short)(*addr&INST_OFFSET_MASK));
|
||||
break;
|
||||
|
||||
case SW_RA_INST:
|
||||
ra_offset = abs((short)(*addr&INST_OFFSET_MASK));
|
||||
break;
|
||||
|
||||
case 0x3c1c0000:
|
||||
return depth +1;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ra = *(unsigned long **)((unsigned long)sp + ra_offset);
|
||||
sp = (unsigned long *)((unsigned long)sp + stack_size);
|
||||
}
|
||||
|
||||
return depth;
|
||||
}
|
||||
|
||||
int backtrace(void)
|
||||
{
|
||||
unsigned long *addr;
|
||||
unsigned long *ra;
|
||||
unsigned long *sp;
|
||||
int size = 8, depth;
|
||||
|
||||
size_t ra_offset;
|
||||
size_t stack_size;
|
||||
|
||||
// get current $a and $sp
|
||||
__asm__ __volatile__ (
|
||||
" move %0, $ra\n"
|
||||
" move %1, $sp\n"
|
||||
: "=r"(ra), "=r"(sp)
|
||||
);
|
||||
|
||||
// scanning to find the size of hte current stack frame
|
||||
stack_size = 0;
|
||||
|
||||
for ( addr = (unsigned long *)backtrace; !stack_size; ++addr)
|
||||
{
|
||||
if ((*addr & INST_OP_MASK ) == ADDUI_SP_INST )
|
||||
stack_size = abs((short)(*addr&INST_OFFSET_MASK));
|
||||
else if ( *addr == JR_RA_INST )
|
||||
break;
|
||||
}
|
||||
|
||||
sp = (unsigned long *) (( unsigned long )sp + stack_size);
|
||||
|
||||
// repeat backwar scanning
|
||||
for ( depth = 0; depth < size && ((( unsigned long )ra > KSEG0BASE) && (( unsigned long )ra < KSEG1BASE)); ++ depth )
|
||||
{
|
||||
rt_kprintf("RA[%2d] : [0x%08x]\n", depth, ra);
|
||||
{
|
||||
extern void rt_thread_exit(void);
|
||||
if ((uint32_t)ra == (uint32_t)(rt_thread_exit))
|
||||
return depth;
|
||||
}
|
||||
|
||||
ra_offset = 0;
|
||||
stack_size = 0;
|
||||
|
||||
for ( addr = ra; !ra_offset || !stack_size; -- addr )
|
||||
{
|
||||
switch( *addr & INST_OP_MASK)
|
||||
{
|
||||
case ADDUI_SP_INST:
|
||||
stack_size = abs((short)(*addr&INST_OFFSET_MASK));
|
||||
break;
|
||||
|
||||
case SW_RA_INST:
|
||||
ra_offset = (short)(*addr&INST_OFFSET_MASK);
|
||||
break;
|
||||
|
||||
case 0x3c1c0000:
|
||||
return depth +1;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ra = *(unsigned long **)((unsigned long)sp + ra_offset);
|
||||
sp = (unsigned long*) ((unsigned long)sp+stack_size );
|
||||
}
|
||||
|
||||
return depth;
|
||||
}
|
||||
|
||||
#include <rtthread.h>
|
||||
extern long list_thread(void);
|
||||
void assert_hook(const char* ex, const char* func, rt_size_t line)
|
||||
{
|
||||
backtrace();
|
||||
|
||||
list_thread();
|
||||
rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex, func, line);
|
||||
}
|
||||
|
||||
int backtrace_init(void)
|
||||
{
|
||||
#ifdef RT_DEBUG
|
||||
rt_assert_set_hook(assert_hook);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(backtrace_init);
|
||||
@@ -1,48 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016-09-19 Urey first version
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
|
||||
.globl cache_init
|
||||
.ent cache_init
|
||||
cache_init:
|
||||
.set noreorder
|
||||
mtc0 zero, CP0_TAGLO
|
||||
move t0, a0 // cache total size
|
||||
move t1, a1 // cache line size
|
||||
li t2, 0x80000000
|
||||
addu t3, t0, t2
|
||||
|
||||
_cache_init_loop:
|
||||
cache 8, 0(t2) // icache_index_store_tag
|
||||
cache 9, 0(t2) // dcache_index_store_tag
|
||||
addu t2, t1
|
||||
bne t2, t3, _cache_init_loop
|
||||
nop
|
||||
|
||||
mfc0 t0, CP0_CONFIG
|
||||
li t1, 0x7
|
||||
not t1
|
||||
and t0, t0, t1
|
||||
or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
|
||||
mtc0 t0, CP0_CONFIG
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.set reorder
|
||||
.end cache_init
|
||||
@@ -1,81 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016-09-07 Urey first version
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
||||
.global rt_thread_switch_interrupt_flag
|
||||
.global rt_interrupt_from_thread
|
||||
.global rt_interrupt_to_thread
|
||||
|
||||
.section .text,"ax",@progbits
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.globl rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
mfc0 v0,CP0_STATUS
|
||||
srl v1,v0,1
|
||||
sll v1,v1,1
|
||||
# and v1,v0,0xfffffffe
|
||||
mtc0 v1,CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
|
||||
LEAF(rt_hw_interrupt_enable)
|
||||
mtc0 a0,CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
END(rt_hw_interrupt_enable)
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to)/*
|
||||
* a0 --> to
|
||||
*/
|
||||
LEAF(rt_hw_context_switch_to)
|
||||
lw sp , 0(a0) /* switch to the new stack */
|
||||
RESTORE_CONTEXT
|
||||
END(rt_hw_context_switch_to)
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
|
||||
* a0 --> from
|
||||
* a1 --> to
|
||||
*/
|
||||
LEAF(rt_hw_context_switch)
|
||||
mtc0 ra, CP0_EPC
|
||||
SAVE_CONTEXT
|
||||
|
||||
sw sp, 0(a0) /* store sp in preempted tasks TCB */
|
||||
lw sp, 0(a1) /* get new task stack pointer */
|
||||
|
||||
RESTORE_CONTEXT
|
||||
END(rt_hw_context_switch)
|
||||
|
||||
LEAF(rt_hw_context_switch_interrupt)
|
||||
la t0, rt_thread_switch_interrupt_flag
|
||||
lw t1, 0(t0)
|
||||
nop
|
||||
bnez t1, _reswitch
|
||||
nop
|
||||
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
|
||||
sw t1, 0(t0)
|
||||
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
|
||||
sw a0, 0(t0)
|
||||
_reswitch:
|
||||
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
|
||||
sw a1, 0(t0)
|
||||
jr ra
|
||||
nop
|
||||
END(rt_hw_context_switch_interrupt)
|
||||
|
||||
@@ -1,382 +0,0 @@
|
||||
/*
|
||||
* File : mips_excpt.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016年9月7日 Urey the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "mips.h"
|
||||
#include "mips_excpt.h"
|
||||
|
||||
extern int backtrace(void);
|
||||
int backtrace_ctx(mips_reg_ctx *ctx);
|
||||
|
||||
extern long list_thread(void);
|
||||
|
||||
const static char *regstr[] = {
|
||||
"$0 zero", "$1 at", "$2 v0", "$3 v1", "$4 a0", "$5 a1", "$6 a2", "$7 a3",
|
||||
"$8 t0", "$9 t1", "$10 t2", "$11 t3", "$12 t4", "$13 t5", "$14 t6", "$15 t7",
|
||||
"$16 s0", "$17 s1", "$18 s2", "$19 s3", "$20 s4", "$21 s5", "$22 s6", "$23 s7",
|
||||
"$24 t8", "$25 t9", "$26 k0", "$27 k1", "$28 gp", "$29 sp", "$30 fp", "$31 ra"
|
||||
};
|
||||
|
||||
static const char *cause_strings[32] =
|
||||
{
|
||||
/* 0 */ "Int",
|
||||
/* 1 */ "TLB Mods",
|
||||
/* 2 */ "TLB Load",
|
||||
/* 3 */ "TLB Store",
|
||||
/* 4 */ "Address Load",
|
||||
/* 5 */ "Address Store",
|
||||
/* 6 */ "Instruction Bus Error",
|
||||
/* 7 */ "Data Bus Error",
|
||||
/* 8 */ "Syscall",
|
||||
/* 9 */ "Breakpoint",
|
||||
/* 10 */ "Reserved Instruction",
|
||||
/* 11 */ "Coprocessor Unuseable",
|
||||
/* 12 */ "Overflow",
|
||||
/* 13 */ "Trap",
|
||||
/* 14 */ "Instruction Virtual Coherency Error",
|
||||
/* 15 */ "FP Exception",
|
||||
/* 16 */ "Reserved 16",
|
||||
/* 17 */ "Reserved 17",
|
||||
/* 18 */ "Reserved 18",
|
||||
/* 19 */ "Reserved 19",
|
||||
/* 20 */ "Reserved 20",
|
||||
/* 21 */ "Reserved 21",
|
||||
/* 22 */ "Reserved 22",
|
||||
/* 23 */ "Watch",
|
||||
/* 24 */ "Reserved 24",
|
||||
/* 25 */ "Reserved 25",
|
||||
/* 26 */ "Reserved 26",
|
||||
/* 27 */ "Reserved 27",
|
||||
/* 28 */ "Reserved 28",
|
||||
/* 29 */ "Reserved 29",
|
||||
/* 30 */ "Reserved 30",
|
||||
/* 31 */ "Data Virtual Coherency Error"
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* exception handle table
|
||||
*/
|
||||
exception_func_t sys_exception_handlers[32];
|
||||
|
||||
static void mod_handler(mips_reg_ctx *regs)
|
||||
{
|
||||
rt_kprintf("tlb modification exception\n");
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_kprintf(" cause: 0x%08x\n", read_c0_cause());
|
||||
|
||||
list_thread();
|
||||
|
||||
printf("-----------------------------------------------------\n");
|
||||
printf("BACKTRACE:\n");
|
||||
backtrace();
|
||||
printf("-----------------------------------------------------\n");
|
||||
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void tlbl_handler(mips_reg_ctx *regs)
|
||||
{
|
||||
rt_kprintf("tlb exception: load\n");
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_kprintf(" cause: 0x%08x\n", read_c0_cause());
|
||||
|
||||
list_thread();
|
||||
|
||||
printf("-----------------------------------------------------\n");
|
||||
printf("BACKTRACE:\n");
|
||||
backtrace();
|
||||
printf("-----------------------------------------------------\n");
|
||||
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void tlbs_handler(mips_reg_ctx *regs)
|
||||
{
|
||||
rt_kprintf("tlb exception: store\n");
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_kprintf(" cause: 0x%08x\n", read_c0_cause());
|
||||
|
||||
list_thread();
|
||||
|
||||
printf("-----------------------------------------------------\n");
|
||||
printf("BACKTRACE:\n");
|
||||
backtrace();
|
||||
printf("-----------------------------------------------------\n");
|
||||
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void adel_handler(mips_reg_ctx *regs)
|
||||
{
|
||||
rt_kprintf("address error exception: load\n");
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_kprintf(" cause: 0x%08x\n", read_c0_cause());
|
||||
|
||||
list_thread();
|
||||
rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, rt_thread_self()->name);
|
||||
|
||||
printf("-----------------------------------------------------\n");
|
||||
printf("BACKTRACE:\n");
|
||||
backtrace();
|
||||
printf("-----------------------------------------------------\n");
|
||||
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void ades_handler(mips_reg_ctx *regs)
|
||||
{
|
||||
rt_kprintf("address error exception: store\n");
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_kprintf(" cause: 0x%08x\n", read_c0_cause());
|
||||
|
||||
list_thread();
|
||||
|
||||
printf("-----------------------------------------------------\n");
|
||||
printf("BACKTRACE:\n");
|
||||
backtrace();
|
||||
printf("-----------------------------------------------------\n");
|
||||
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void fpe_handler(mips_reg_ctx *regs)
|
||||
{
|
||||
rt_kprintf("floating point exception\n");
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_kprintf(" cause: 0x%08x\n", read_c0_cause());
|
||||
|
||||
list_thread();
|
||||
|
||||
printf("-----------------------------------------------------\n");
|
||||
printf("BACKTRACE:\n");
|
||||
backtrace();
|
||||
printf("-----------------------------------------------------\n");
|
||||
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
|
||||
static void unhandled_exception_handle(mips_reg_ctx *regs)
|
||||
{
|
||||
int i;
|
||||
unsigned int cause = read_c0_cause();
|
||||
unsigned int exc = (cause >> 2) & 0x1f;
|
||||
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", regs->CP0EPC);
|
||||
rt_kprintf(" cause: 0x%08x\n", regs->CP0Cause);
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
{
|
||||
if (i % 4 == 0)
|
||||
printf("\n");
|
||||
printf("%8s %08x ", regstr[i], regs->regs[i]);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
list_thread();
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void install_default_exception_handler(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<sizeof(sys_exception_handlers)/sizeof(sys_exception_handlers[0]); i++)
|
||||
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
|
||||
|
||||
sys_exception_handlers[EX_MOD] = mod_handler;
|
||||
sys_exception_handlers[EX_TLBL] = tlbl_handler;
|
||||
sys_exception_handlers[EX_TLBS] = tlbs_handler;
|
||||
sys_exception_handlers[EX_ADEL] = adel_handler;
|
||||
sys_exception_handlers[EX_ADES] = ades_handler;
|
||||
sys_exception_handlers[EX_FPE] = fpe_handler;
|
||||
}
|
||||
|
||||
int rt_hw_exception_init(void)
|
||||
{
|
||||
/* install the default exception handler */
|
||||
install_default_exception_handler();
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* setup the exception handle
|
||||
*/
|
||||
exception_func_t rt_set_except_vector(int n, exception_func_t func)
|
||||
{
|
||||
exception_func_t old_handler = sys_exception_handlers[n];
|
||||
|
||||
if ((n == 0) || (n > 32) || (!func))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
sys_exception_handlers[n] = func;
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
void mips_exception_handler(mips_reg_ctx *ctx)
|
||||
{
|
||||
static int read_epc_count = 0;
|
||||
static int epc_save = 0;
|
||||
int i;
|
||||
unsigned int epc;
|
||||
|
||||
//如果 read_epc_count>0 说明 c_except_handler 在读 epc 时重入了，即读 epc 导致了一个新的异常
|
||||
if (read_epc_count > 0)
|
||||
{
|
||||
printf("ERROR: read epc fail when except handle\n");
|
||||
epc = epc_save;
|
||||
read_epc_count = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
read_epc_count++;
|
||||
epc_save = 0;
|
||||
epc = read_c0_epc();
|
||||
epc_save = epc;
|
||||
|
||||
if (epc != 0)
|
||||
{
|
||||
printf("-----------------------------------------------------\n");
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
printf("%08x:\t%08x\n",
|
||||
(epc - 4 * 4 + i * 4),
|
||||
*(unsigned int *) ((epc - 4 * 4 + i * 4) | 0xa0000000));
|
||||
}
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
printf("%08x:\t%08x\n",
|
||||
(epc + i * 4),
|
||||
*(unsigned int *) ((epc + i * 4) | 0xa0000000));
|
||||
}
|
||||
printf("-----------------------------------------------------\n");
|
||||
}
|
||||
|
||||
read_epc_count--;
|
||||
}
|
||||
|
||||
printf("-----------------------------------------------------\n");
|
||||
unsigned int cause = read_c0_cause();
|
||||
unsigned int exc = (cause >> 2) & 0x1f;
|
||||
printf("CAUSE=%08x --> %s\n", cause, cause_strings[exc]);
|
||||
printf("EPC=%08x\n", epc);
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
{
|
||||
if ((i != 0) && (i % 4 == 0))
|
||||
printf("\n");
|
||||
printf("%8s %08x ", regstr[i], ctx->regs[i]);
|
||||
}
|
||||
printf("\n-----------------------------------------------------\n");
|
||||
printf("%s: \t %8x\n","CP0Status ", ctx->CP0Status);
|
||||
printf("%s: \t %8x\n","CP0DataHI ", ctx->CP0DataHI);
|
||||
printf("%s: \t %8x\n","CP0DataLO ", ctx->CP0DataLO);
|
||||
printf("%s: \t %8x\n","CP0BadVAddr", ctx->CP0BadVAddr);
|
||||
printf("%s: \t %8x\n","CP0Cause ", ctx->CP0Cause);
|
||||
printf("%s: \t %8x\n","CP0EPC ", ctx->CP0EPC);
|
||||
printf("-----------------------------------------------------\n");
|
||||
|
||||
#if 0
|
||||
switch (exc)
|
||||
{
|
||||
case EX_MOD:
|
||||
/* TLB modified */
|
||||
break;
|
||||
|
||||
case EX_TLBL: /* TLB exc(load or ifetch) */
|
||||
case EX_TLBS: /* TLB exception (store) */
|
||||
|
||||
break;
|
||||
|
||||
case EX_ADEL: /* Address err(load or ifetch) */
|
||||
case EX_ADES: /* Address error (store) */
|
||||
|
||||
break;
|
||||
|
||||
case EX_IBE: /* Instruction Bus Error */
|
||||
case EX_DBE: /* Data Bus Error */
|
||||
|
||||
break;
|
||||
|
||||
case EX_SYS: /* Syscall */
|
||||
|
||||
break;
|
||||
|
||||
case EX_BP: /* Breakpoint */
|
||||
case EX_TR: /* Trap instruction */
|
||||
|
||||
break;
|
||||
case EX_RI: /* Reserved instruction */
|
||||
|
||||
break;
|
||||
case EX_FPE: /* floating point exception */
|
||||
break;
|
||||
|
||||
case EX_CPU: /* CoProcessor Unusable */
|
||||
|
||||
break;
|
||||
case EX_OV: /* OVerflow */
|
||||
case EX_C2E: /* COP2 exception */
|
||||
case EX_MDMX: /* MDMX exception */
|
||||
case EX_WATCH: /* Watch exception */
|
||||
case EX_MCHECK: /* Machine check exception */
|
||||
case EX_CacheErr: /* Cache error caused re-entry */
|
||||
/* to Debug Mode */
|
||||
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("Unknow exception: %d\r\n", exc);
|
||||
break;
|
||||
}
|
||||
#else
|
||||
sys_exception_handlers[exc](ctx);
|
||||
#endif
|
||||
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
|
||||
void mips_cache_error_handler (unsigned int Addr)
|
||||
{
|
||||
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
list_thread();
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
void mips_tlb_refill_handler(void)
|
||||
{
|
||||
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_kprintf(" cause: 0x%08x\n", read_c0_cause());
|
||||
list_thread();
|
||||
rt_kprintf("current thread: %s\n", rt_thread_self()->name);
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
@@ -1,88 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016-09-07 Urey first version
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
||||
#define _EXC_STKSIZE 20*1024
|
||||
|
||||
;/*********************************************************************************************************
|
||||
; PTE BASE 相关定义
|
||||
;*********************************************************************************************************/
|
||||
|
||||
#define PTE_BASE_OFFSET 23
|
||||
#define PTE_BASE_SIZE 9
|
||||
#define MIPS32_BADVPN2_SHIFT 2
|
||||
|
||||
|
||||
.section ".text", "ax"
|
||||
.set noreorder
|
||||
|
||||
LEAF(mips_tlb_refill_handlerx)
|
||||
.set push
|
||||
.set noat
|
||||
.set noreorder
|
||||
.set volatile
|
||||
|
||||
;/*
|
||||
; * K1 = CP0_CTXT
|
||||
; * K0 = K1
|
||||
; */
|
||||
mfc0 k1 , CP0_CONTEXT ;/* K1 等于 Context 寄存器 */
|
||||
ehb
|
||||
move k0 , k1 ;/* K0 等于 Context 寄存器 */
|
||||
|
||||
;/*
|
||||
; * K1 <<= PTE_BASE_SIZE
|
||||
; * K1 >>= PTE_BASE_SIZE
|
||||
; * K1 >>= 4
|
||||
; * K1 >>= MIPS32_BADVPN2_SHIFT
|
||||
; * K1 <<= 3
|
||||
; */
|
||||
sll k1 , PTE_BASE_SIZE
|
||||
srl k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT) ;/* K1 为 BAD VPN2 */
|
||||
sll k1 , (4 - 1)
|
||||
|
||||
;/*
|
||||
; * K0 >>= PTE_BASE_OFFSET
|
||||
; * K0 <<= PTE_BASE_OFFSET
|
||||
; */
|
||||
srl k0 , PTE_BASE_OFFSET
|
||||
sll k0 , PTE_BASE_OFFSET ;/* K0 为 PTE BASE */
|
||||
|
||||
;/*
|
||||
; * K1 = K1 | K0
|
||||
; */
|
||||
or k1 , k1 , k0 ;/* 合成 */
|
||||
|
||||
;/*
|
||||
; * K0 = *K1
|
||||
; * K1 = *(K1 + 4)
|
||||
; */
|
||||
lw k0 , 0(k1)
|
||||
lw k1 , 4(k1)
|
||||
|
||||
;/*
|
||||
; * CP0_TLBLO0 = K0
|
||||
; * CP0_TLBLO1 = K1
|
||||
; */
|
||||
mtc0 k0 , CP0_ENTRYLO0 ;/* EntryLo0 */
|
||||
mtc0 k1 , CP0_ENTRYLO1 ;/* EntryLo1 */
|
||||
ehb
|
||||
|
||||
tlbwr ;/* TLB 随机替换 */
|
||||
|
||||
eret ;/* 异常返回 */
|
||||
|
||||
.set pop
|
||||
END(mips_tlb_refill_handlerx)
|
||||
@@ -1,183 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016-09-09 Urey first version
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#ifdef __mips_hard_float
|
||||
|
||||
.module hardfloat
|
||||
.module doublefloat
|
||||
.set nomips16
|
||||
|
||||
#include "../common/mips.h"
|
||||
#undef fp
|
||||
|
||||
.global mips_vfp32_init
|
||||
LEAF(mips_vfp32_init)
|
||||
mfc0 t0, CP0_STATUS
|
||||
or t0 , M_StatusCU1
|
||||
mtc0 t0, CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
END(mips_vfp32_init)
|
||||
|
||||
#
|
||||
# FUNCTION: _fpctx_save
|
||||
#
|
||||
# DESCRIPTION: save floating point registers to memory starting at a0
|
||||
#
|
||||
# RETURNS: int
|
||||
# 0: No context saved
|
||||
# CTX_*: Type of context stored
|
||||
#
|
||||
.global _fpctx_save
|
||||
LEAF(_fpctx_save)
|
||||
sw zero, LINKCTX_NEXT(a0)
|
||||
mfc0 t0, CP0_STATUS
|
||||
li t1, M_StatusCU1
|
||||
and t1, t0, t1
|
||||
bnez t1, 1f
|
||||
# FP not enabled, bail out
|
||||
move v0, zero
|
||||
jr ra
|
||||
|
||||
1: # Save FP32 base
|
||||
li t1, ST0_FR
|
||||
and t0, t0, t1
|
||||
cfc1 t2, $31
|
||||
sw t2, FP32CTX_CSR(a0)
|
||||
sdc1 $f0, FP32CTX_0(a0)
|
||||
sdc1 $f2, FP32CTX_2(a0)
|
||||
sdc1 $f4, FP32CTX_4(a0)
|
||||
sdc1 $f6, FP32CTX_6(a0)
|
||||
sdc1 $f8, FP32CTX_8(a0)
|
||||
sdc1 $f10, FP32CTX_10(a0)
|
||||
sdc1 $f12, FP32CTX_12(a0)
|
||||
sdc1 $f14, FP32CTX_14(a0)
|
||||
sdc1 $f16, FP32CTX_16(a0)
|
||||
sdc1 $f18, FP32CTX_18(a0)
|
||||
sdc1 $f20, FP32CTX_20(a0)
|
||||
sdc1 $f22, FP32CTX_22(a0)
|
||||
sdc1 $f24, FP32CTX_24(a0)
|
||||
sdc1 $f26, FP32CTX_26(a0)
|
||||
sdc1 $f28, FP32CTX_28(a0)
|
||||
sdc1 $f30, FP32CTX_30(a0)
|
||||
bnez t0, 2f
|
||||
li v0, LINKCTX_TYPE_FP32
|
||||
sw v0, LINKCTX_ID(a0)
|
||||
jr ra
|
||||
|
||||
2: # Save FP64 extra
|
||||
.set push
|
||||
.set fp=64
|
||||
sdc1 $f1, FP64CTX_1(a0)
|
||||
sdc1 $f3, FP64CTX_3(a0)
|
||||
sdc1 $f5, FP64CTX_5(a0)
|
||||
sdc1 $f7, FP64CTX_7(a0)
|
||||
sdc1 $f9, FP64CTX_9(a0)
|
||||
sdc1 $f11, FP64CTX_11(a0)
|
||||
sdc1 $f13, FP64CTX_13(a0)
|
||||
sdc1 $f15, FP64CTX_15(a0)
|
||||
sdc1 $f17, FP64CTX_17(a0)
|
||||
sdc1 $f19, FP64CTX_19(a0)
|
||||
sdc1 $f21, FP64CTX_21(a0)
|
||||
sdc1 $f23, FP64CTX_23(a0)
|
||||
sdc1 $f25, FP64CTX_25(a0)
|
||||
sdc1 $f27, FP64CTX_27(a0)
|
||||
sdc1 $f29, FP64CTX_29(a0)
|
||||
sdc1 $f31, FP64CTX_31(a0)
|
||||
.set pop
|
||||
li v0, LINKCTX_TYPE_FP64
|
||||
sw v0, LINKCTX_ID(a0)
|
||||
jr ra
|
||||
END(_fpctx_save)
|
||||
|
||||
#
|
||||
# FUNCTION: _fpctx_load
|
||||
#
|
||||
# DESCRIPTION: load floating point registers from context chain starting at a0
|
||||
#
|
||||
# RETURNS: int
|
||||
# 0: Unrecognised context
|
||||
# CTX_*: Type of context restored
|
||||
#
|
||||
.global _fpctx_load
|
||||
LEAF(_fpctx_load)
|
||||
lw v0, LINKCTX_ID(a0)
|
||||
# Detect type
|
||||
li t0, LINKCTX_TYPE_FP64
|
||||
li t1, LINKCTX_TYPE_FP32
|
||||
li t2, M_StatusCU1
|
||||
beq v0, t0, 0f
|
||||
beq v0, t1, 1f
|
||||
# Don't recognise this context, fail
|
||||
move v0, zero
|
||||
jr ra
|
||||
|
||||
0: # FP64 context
|
||||
# Enable CU1
|
||||
di t3
|
||||
ehb
|
||||
or t3, t3, t2
|
||||
mtc0 t3, CP0_STATUS
|
||||
ehb
|
||||
# Load FP64 extra
|
||||
.set push
|
||||
.set fp=64
|
||||
ldc1 $f1, FP64CTX_1(a0)
|
||||
ldc1 $f3, FP64CTX_3(a0)
|
||||
ldc1 $f5, FP64CTX_5(a0)
|
||||
ldc1 $f7, FP64CTX_7(a0)
|
||||
ldc1 $f9, FP64CTX_9(a0)
|
||||
ldc1 $f11, FP64CTX_11(a0)
|
||||
ldc1 $f13, FP64CTX_13(a0)
|
||||
ldc1 $f15, FP64CTX_15(a0)
|
||||
ldc1 $f17, FP64CTX_17(a0)
|
||||
ldc1 $f19, FP64CTX_19(a0)
|
||||
ldc1 $f21, FP64CTX_21(a0)
|
||||
ldc1 $f23, FP64CTX_23(a0)
|
||||
ldc1 $f25, FP64CTX_25(a0)
|
||||
ldc1 $f27, FP64CTX_27(a0)
|
||||
ldc1 $f29, FP64CTX_29(a0)
|
||||
ldc1 $f31, FP64CTX_31(a0)
|
||||
.set pop
|
||||
1: # FP32 context
|
||||
# Enable CU1
|
||||
di t3
|
||||
ehb
|
||||
or t3, t3, t2
|
||||
mtc0 t3, CP0_STATUS
|
||||
ehb
|
||||
# Load FP32 base
|
||||
lw t1, FP32CTX_CSR(a0)
|
||||
ctc1 t1, $31
|
||||
ldc1 $f0, FP32CTX_0(a0)
|
||||
ldc1 $f2, FP32CTX_2(a0)
|
||||
ldc1 $f4, FP32CTX_4(a0)
|
||||
ldc1 $f6, FP32CTX_6(a0)
|
||||
ldc1 $f8, FP32CTX_8(a0)
|
||||
ldc1 $f10, FP32CTX_10(a0)
|
||||
ldc1 $f12, FP32CTX_12(a0)
|
||||
ldc1 $f14, FP32CTX_14(a0)
|
||||
ldc1 $f16, FP32CTX_16(a0)
|
||||
ldc1 $f18, FP32CTX_18(a0)
|
||||
ldc1 $f20, FP32CTX_20(a0)
|
||||
ldc1 $f22, FP32CTX_22(a0)
|
||||
ldc1 $f24, FP32CTX_24(a0)
|
||||
ldc1 $f26, FP32CTX_26(a0)
|
||||
ldc1 $f28, FP32CTX_28(a0)
|
||||
ldc1 $f30, FP32CTX_30(a0)
|
||||
# Return CTX_FP32/64
|
||||
jr ra
|
||||
END(_fpctx_load)
|
||||
|
||||
#endif
|
||||
@@ -1,82 +0,0 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016Äê9ÔÂ8ÈÕ Urey the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
||||
register U32 $GP __asm__ ("$28");
|
||||
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
static rt_uint32_t wSR=0;
|
||||
static rt_uint32_t wGP;
|
||||
|
||||
mips_reg_ctx *regCtx;
|
||||
mips_arg_ctx *argCtx;
|
||||
rt_uint32_t i;
|
||||
|
||||
if (wSR == 0)
|
||||
{
|
||||
wSR = read_c0_status();
|
||||
wSR &= 0xfffffffe;
|
||||
wSR |= 0x0403;
|
||||
|
||||
wGP = $GP;
|
||||
}
|
||||
|
||||
if ((rt_uint32_t) stack_addr & 0x7)
|
||||
{
|
||||
stack_addr = (rt_uint8_t *)((rt_uint32_t)stack_addr - 4);
|
||||
}
|
||||
|
||||
argCtx = (mips_arg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx));
|
||||
regCtx = (mips_reg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx) - sizeof(mips_reg_ctx));
|
||||
|
||||
for (i = 0; i < 4; ++i)
|
||||
{
|
||||
argCtx->args[i] = i;
|
||||
}
|
||||
|
||||
//±£´æͨÓüĴæÆ÷
|
||||
for (i = 0; i < 32; ++i)
|
||||
{
|
||||
regCtx->regs[i] = i;
|
||||
}
|
||||
|
||||
regCtx->regs[REG_SP] = (rt_uint32_t)stack_addr;
|
||||
regCtx->regs[REG_A0] = (rt_uint32_t)parameter;
|
||||
regCtx->regs[REG_GP] = (rt_uint32_t)wGP;
|
||||
regCtx->regs[REG_FP] = (rt_uint32_t)0x0;
|
||||
regCtx->regs[REG_RA] = (rt_uint32_t)texit;
|
||||
|
||||
regCtx->CP0DataLO = 0x00;
|
||||
regCtx->CP0DataHI = 0x00;
|
||||
regCtx->CP0Cause = read_c0_cause();
|
||||
regCtx->CP0Status = wSR;
|
||||
regCtx->CP0EPC = (rt_uint32_t)tentry;
|
||||
regCtx->CP0BadVAddr= 0x00;
|
||||
|
||||
return (rt_uint8_t *)(regCtx);
|
||||
}
|
||||
@@ -1,314 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2016-09-07 Urey first version
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
||||
#define IRQ_STACK_SIZE 0x2000
|
||||
#define EXC_STACK_SIZE 0x2000
|
||||
|
||||
|
||||
.section ".bss"
|
||||
ALIGN(4)
|
||||
irq_stack_low:
|
||||
.space IRQ_STACK_SIZE
|
||||
irq_stack_top:
|
||||
.space 8
|
||||
|
||||
ALIGN(4)
|
||||
exc_stack_low:
|
||||
.space EXC_STACK_SIZE
|
||||
exc_stack_top:
|
||||
.space 8
|
||||
|
||||
#define SYSTEM_STACK 0x80003fe8
|
||||
|
||||
;/*********************************************************************************************************
|
||||
; Èë¿Ú
|
||||
;*********************************************************************************************************/
|
||||
.global rtthread_startup
|
||||
.global mips_vfp32_init
|
||||
|
||||
.global _start
|
||||
.section ".start", "ax"
|
||||
.set noreorder
|
||||
_start:
|
||||
.set noreorder
|
||||
la ra, _start
|
||||
|
||||
li t1, 0x00800000
|
||||
mtc0 t1, CP0_CAUSE
|
||||
|
||||
/* init cp0 registers. */
|
||||
li t0, 0x1000FC00 /* BEV = 0 and mask all interrupt */
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
#ifdef __mips_hard_float
|
||||
jal mips_vfp32_init
|
||||
nop
|
||||
#endif
|
||||
|
||||
/* setup stack pointer */
|
||||
li sp, SYSTEM_STACK
|
||||
la gp, _gp
|
||||
|
||||
_cache_init:
|
||||
/* init caches, assumes a 4way * 128set * 32byte I/D cache */
|
||||
mtc0 zero, CP0_TAGLO /* TAGLO reg */
|
||||
mtc0 zero, CP0_TAGHI /* TAGHI reg */
|
||||
li t0, 3 /* enable cache for kseg0 accesses */
|
||||
mtc0 t0, CP0_CONFIG /* CONFIG reg */
|
||||
la t0, 0x80000000 /* an idx op should use an unmappable address */
|
||||
ori t1, t0, 0x4000 /* 16kB cache */
|
||||
|
||||
_cache_loop:
|
||||
cache 0x8, 0(t0) /* index store icache tag */
|
||||
cache 0x9, 0(t0) /* index store dcache tag */
|
||||
bne t0, t1, _cache_loop
|
||||
addiu t0, t0, 0x20 /* 32 bytes per cache line */
|
||||
nop
|
||||
|
||||
/* invalidate BTB */
|
||||
mfc0 t0, CP0_CONFIG
|
||||
nop
|
||||
ori t0, 2
|
||||
mtc0 t0, CP0_CONFIG
|
||||
nop
|
||||
|
||||
|
||||
/* jump to RT-Thread RTOS */
|
||||
jal rtthread_startup
|
||||
nop
|
||||
|
||||
/* restart, never die */
|
||||
j _start
|
||||
nop
|
||||
.set reorder
|
||||
|
||||
|
||||
;/*********************************************************************************************************
|
||||
; Òì³£ÏòÁ¿±í
|
||||
;*********************************************************************************************************/
|
||||
/* 0x0 - TLB refill handler */
|
||||
.section .vectors.1, "ax", %progbits
|
||||
j mips_tlb_refill_entry
|
||||
nop
|
||||
|
||||
/* 0x100 - Cache error handler */
|
||||
.section .vectors.2, "ax", %progbits
|
||||
j mips_cache_error_entry
|
||||
nop
|
||||
|
||||
/* 0x180 - Exception/Interrupt handler */
|
||||
.section .vectors.3, "ax", %progbits
|
||||
j mips_exception_entry
|
||||
nop
|
||||
|
||||
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
|
||||
.section .vectors.4, "ax", %progbits
|
||||
j mips_interrupt_entry
|
||||
nop
|
||||
.section .vectors, "ax", %progbits
|
||||
|
||||
.global mips_exception_handler
|
||||
// .global mips_syscall
|
||||
LEAF(mips_exception_entry)
|
||||
.set push
|
||||
.set noat
|
||||
.set noreorder
|
||||
.set volatile
|
||||
|
||||
mfc0 k0, C0_CAUSE
|
||||
andi k0, k0, 0x7c
|
||||
beq zero, k0, except_do_intr
|
||||
nop
|
||||
|
||||
andi k0,(0x08 << 2)
|
||||
beq zero,k0,except_do
|
||||
nop
|
||||
except_do_intr:
|
||||
la k0,mips_interrupt_entry
|
||||
jr k0
|
||||
nop
|
||||
except_do_syscall:
|
||||
// la k0,mips_syscall
|
||||
// jr k0
|
||||
nop
|
||||
except_do:
|
||||
//save sp
|
||||
move k0,sp
|
||||
//la sp, exc_stack_top
|
||||
subu sp, sp, CONTEXT_SIZE
|
||||
//save context
|
||||
sw $0, (4*0)(sp);
|
||||
sw $1, (4*1)(sp);
|
||||
sw $2, (4*2)(sp);
|
||||
sw $3, (4*3)(sp);
|
||||
sw $4, (4*4)(sp);
|
||||
sw $5, (4*5)(sp);
|
||||
sw $6, (4*6)(sp);
|
||||
sw $7, (4*7)(sp);
|
||||
sw $8, (4*8)(sp);
|
||||
sw $9, (4*9)(sp);
|
||||
sw $10, (4*10)(sp);
|
||||
sw $11, (4*11)(sp);
|
||||
sw $12, (4*12)(sp);
|
||||
sw $13, (4*13)(sp);
|
||||
sw $14, (4*14)(sp);
|
||||
sw $15, (4*15)(sp);
|
||||
sw $16, (4*16)(sp);
|
||||
sw $17, (4*17)(sp);
|
||||
sw $18, (4*18)(sp);
|
||||
sw $19, (4*19)(sp);
|
||||
sw $20, (4*20)(sp);
|
||||
sw $21, (4*21)(sp);
|
||||
sw $22, (4*22)(sp);
|
||||
sw $23, (4*23)(sp);
|
||||
sw $24, (4*24)(sp);
|
||||
sw $25, (4*25)(sp);
|
||||
sw $26, (4*26)(sp);
|
||||
sw $27, (4*27)(sp);
|
||||
sw $28, (4*28)(sp);
|
||||
sw k0, (4*29)(sp); //old sp
|
||||
sw $30, (4*30)(sp);
|
||||
sw $31, (4*31)(sp);
|
||||
|
||||
/* STATUS CAUSE EPC.... */
|
||||
mfc0 $2, CP0_STATUS
|
||||
sw $2, STK_OFFSET_SR(sp)
|
||||
|
||||
mfc0 $2, CP0_CAUSE
|
||||
sw $2, STK_OFFSET_CAUSE(sp)
|
||||
|
||||
mfc0 $2, CP0_BADVADDR
|
||||
sw $2, STK_OFFSET_BADVADDR(sp)
|
||||
|
||||
MFC0 $2, CP0_EPC
|
||||
sw $2, STK_OFFSET_EPC(sp)
|
||||
|
||||
mfhi $2
|
||||
sw $2, STK_OFFSET_HI(sp)
|
||||
|
||||
mflo $2
|
||||
sw $2, STK_OFFSET_LO(sp)
|
||||
|
||||
move a0, sp
|
||||
la k0, mips_exception_handler
|
||||
j k0
|
||||
nop
|
||||
|
||||
//
|
||||
|
||||
.set pop
|
||||
END(mips_exception_entry)
|
||||
|
||||
.global mips_tlb_refill_handler
|
||||
LEAF(mips_tlb_refill_entry)
|
||||
.set push
|
||||
.set noat
|
||||
.set noreorder
|
||||
.set volatile
|
||||
|
||||
la k0,mips_tlb_refill_handler
|
||||
jr k0
|
||||
|
||||
nop
|
||||
eret
|
||||
nop
|
||||
|
||||
.set pop
|
||||
END(mips_tlb_refill_entry)
|
||||
|
||||
.global mips_cache_error_handler
|
||||
LEAF(mips_cache_error_entry)
|
||||
.set push
|
||||
.set noat
|
||||
.set noreorder
|
||||
.set volatile
|
||||
|
||||
la k0,mips_cache_error_handler
|
||||
jr k0
|
||||
nop
|
||||
eret
|
||||
nop
|
||||
|
||||
.set pop
|
||||
END(mips_cache_error_entry)
|
||||
|
||||
|
||||
|
||||
.global rt_interrupt_dispatch
|
||||
.global rt_interrupt_enter
|
||||
.global rt_interrupt_leave
|
||||
LEAF(mips_interrupt_entry)
|
||||
.set push
|
||||
.set noat
|
||||
.set noreorder
|
||||
.set volatile
|
||||
|
||||
//mfc0 k0,CP0_EPC
|
||||
SAVE_CONTEXT
|
||||
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t1, CP0_STATUS
|
||||
and t0, t1
|
||||
|
||||
andi t0, 0xff00
|
||||
beqz t0, spurious_interrupt
|
||||
nop
|
||||
|
||||
/* let k0 keep the current context sp */
|
||||
move k0, sp
|
||||
|
||||
/* switch to kernel stack */
|
||||
la sp, irq_stack_top
|
||||
jal rt_interrupt_enter
|
||||
nop
|
||||
jal rt_interrupt_dispatch
|
||||
nop
|
||||
jal rt_interrupt_leave
|
||||
nop
|
||||
|
||||
/* switch sp back to thread's context */
|
||||
move sp, k0
|
||||
|
||||
/*
|
||||
* if rt_thread_switch_interrupt_flag set, jump to
|
||||
* rt_hw_context_switch_interrupt_do and don't return
|
||||
*/
|
||||
la k0, rt_thread_switch_interrupt_flag
|
||||
lw k1, 0(k0)
|
||||
beqz k1, spurious_interrupt
|
||||
nop
|
||||
sw zero, 0(k0) /* clear flag */
|
||||
nop
|
||||
|
||||
/*
|
||||
* switch to the new thread
|
||||
*/
|
||||
la k0, rt_interrupt_from_thread
|
||||
lw k1, 0(k0)
|
||||
nop
|
||||
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
|
||||
|
||||
la k0, rt_interrupt_to_thread
|
||||
lw k1, 0(k0)
|
||||
nop
|
||||
lw sp, 0(k1) /* get new task's stack pointer */
|
||||
j spurious_interrupt
|
||||
nop
|
||||
spurious_interrupt:
|
||||
RESTORE_CONTEXT
|
||||
|
||||
.set pop
|
||||
END(mips_interrupt_entry)
|
||||
@@ -1,284 +0,0 @@
|
||||
/*
|
||||
* File : x1000.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2015-11-19 Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef __X1000_H__
|
||||
#define __X1000_H__
|
||||
|
||||
#include "../common/mips.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define cache_unroll(base,op) \
|
||||
__asm__ __volatile__(" \
|
||||
.set noreorder; \
|
||||
.set mips3; \
|
||||
cache %1, (%0); \
|
||||
.set mips0; \
|
||||
.set reorder" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
/* cpu pipeline flush */
|
||||
static inline void jz_sync(void)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
static inline void writeb(u8 value, u32 address)
|
||||
{
|
||||
*((volatile u8 *) address) = value;
|
||||
}
|
||||
static inline void writew( u16 value, u32 address)
|
||||
{
|
||||
*((volatile u16 *) address) = value;
|
||||
}
|
||||
static inline void writel(u32 value, u32 address)
|
||||
{
|
||||
*((volatile u32 *) address) = value;
|
||||
}
|
||||
|
||||
static inline u8 readb(u32 address)
|
||||
{
|
||||
return *((volatile u8 *)address);
|
||||
}
|
||||
|
||||
static inline u16 readw(u32 address)
|
||||
{
|
||||
return *((volatile u16 *)address);
|
||||
}
|
||||
|
||||
static inline u32 readl(u32 address)
|
||||
{
|
||||
return *((volatile u32 *)address);
|
||||
}
|
||||
|
||||
static inline void jz_writeb(u32 address, u8 value)
|
||||
{
|
||||
*((volatile u8 *)address) = value;
|
||||
}
|
||||
|
||||
static inline void jz_writew(u32 address, u16 value)
|
||||
{
|
||||
*((volatile u16 *)address) = value;
|
||||
}
|
||||
|
||||
static inline void jz_writel(u32 address, u32 value)
|
||||
{
|
||||
*((volatile u32 *)address) = value;
|
||||
}
|
||||
|
||||
static inline u8 jz_readb(u32 address)
|
||||
{
|
||||
return *((volatile u8 *)address);
|
||||
}
|
||||
|
||||
static inline u16 jz_readw(u32 address)
|
||||
{
|
||||
return *((volatile u16 *)address);
|
||||
}
|
||||
|
||||
static inline u32 jz_readl(u32 address)
|
||||
{
|
||||
return *((volatile u32 *)address);
|
||||
}
|
||||
|
||||
#define BIT(n) (0x01u << (n))
|
||||
#define BIT0 (0x01u << 0)
|
||||
#define BIT1 (0x01u << 1)
|
||||
#define BIT2 (0x01u << 2)
|
||||
#define BIT3 (0x01u << 3)
|
||||
#define BIT4 (0x01u << 4)
|
||||
#define BIT5 (0x01u << 5)
|
||||
#define BIT6 (0x01u << 6)
|
||||
#define BIT7 (0x01u << 7)
|
||||
#define BIT8 (0x01u << 8)
|
||||
#define BIT9 (0x01u << 9)
|
||||
#define BIT10 (0x01u << 10)
|
||||
#define BIT11 (0x01u << 11)
|
||||
#define BIT12 (0x01u << 12)
|
||||
#define BIT13 (0x01u << 13)
|
||||
#define BIT14 (0x01u << 14)
|
||||
#define BIT15 (0x01u << 15)
|
||||
#define BIT16 (0x01u << 16)
|
||||
#define BIT17 (0x01u << 17)
|
||||
#define BIT18 (0x01u << 18)
|
||||
#define BIT19 (0x01u << 19)
|
||||
#define BIT20 (0x01u << 20)
|
||||
#define BIT21 (0x01u << 21)
|
||||
#define BIT22 (0x01u << 22)
|
||||
#define BIT23 (0x01u << 23)
|
||||
#define BIT24 (0x01u << 24)
|
||||
#define BIT25 (0x01u << 25)
|
||||
#define BIT26 (0x01u << 26)
|
||||
#define BIT27 (0x01u << 27)
|
||||
#define BIT28 (0x01u << 28)
|
||||
#define BIT29 (0x01u << 29)
|
||||
#define BIT30 (0x01u << 30)
|
||||
#define BIT31 (0x01u << 31)
|
||||
|
||||
/* Generate the bit field mask from msb to lsb */
|
||||
#define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
|
||||
|
||||
|
||||
/* Get the bit field value from the data which is read from the register */
|
||||
#define get_bf_value(data, lsb, mask) (((data) & (mask)) >> (lsb))
|
||||
|
||||
#endif /* !ASSEMBLY */
|
||||
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Register Definitions
|
||||
//
|
||||
/* AHB0 BUS Devices Base */
|
||||
#define HARB0_BASE 0xB3000000
|
||||
#define EMC_BASE 0xB3010000
|
||||
#define DDRC_BASE 0xB3020000
|
||||
#define MDMAC_BASE 0xB3030000
|
||||
#define LCD_BASE 0xB3050000
|
||||
#define TVE_BASE 0xB3050000
|
||||
#define SLCD_BASE 0xB3050000
|
||||
#define CIM_BASE 0xB3060000
|
||||
#define IPU_BASE 0xB3080000
|
||||
/* AHB1 BUS Devices Base */
|
||||
#define HARB1_BASE 0xB3200000
|
||||
#define DMAGP0_BASE 0xB3210000
|
||||
#define DMAGP1_BASE 0xB3220000
|
||||
#define DMAGP2_BASE 0xB3230000
|
||||
#define MC_BASE 0xB3250000
|
||||
#define ME_BASE 0xB3260000
|
||||
#define DEBLK_BASE 0xB3270000
|
||||
#define IDCT_BASE 0xB3280000
|
||||
#define CABAC_BASE 0xB3290000
|
||||
#define TCSM0_BASE 0xB32B0000
|
||||
#define TCSM1_BASE 0xB32C0000
|
||||
#define SRAM_BASE 0xB32D0000
|
||||
/* AHB2 BUS Devices Base */
|
||||
#define HARB2_BASE 0xB3400000
|
||||
#define NEMC_BASE 0xB3410000
|
||||
#define DMAC_BASE 0xB3420000
|
||||
#define UHC_BASE 0xB3430000
|
||||
//#define UDC_BASE 0xB3440000
|
||||
#define SFC_BASE 0xB3440000
|
||||
#define GPS_BASE 0xB3480000
|
||||
#define ETHC_BASE 0xB34B0000
|
||||
#define BCH_BASE 0xB34D0000
|
||||
#define MSC0_BASE 0xB3450000
|
||||
#define MSC1_BASE 0xB3460000
|
||||
#define MSC2_BASE 0xB3470000
|
||||
#define OTG_BASE 0xb3500000
|
||||
|
||||
/* APB BUS Devices Base */
|
||||
#define CPM_BASE 0xB0000000
|
||||
#define INTC_BASE 0xB0001000
|
||||
#define TCU_BASE 0xB0002000
|
||||
#define WDT_BASE 0xB0002000
|
||||
#define OST_BASE 0xB2000000 /* OS Timer */
|
||||
#define RTC_BASE 0xB0003000
|
||||
#define GPIO_BASE 0xB0010000
|
||||
#define AIC_BASE 0xB0020000
|
||||
#define DMIC_BASE 0xB0021000
|
||||
#define ICDC_BASE 0xB0020000
|
||||
#define UART0_BASE 0xB0030000
|
||||
#define UART1_BASE 0xB0031000
|
||||
#define UART2_BASE 0xB0032000
|
||||
#define SCC_BASE 0xB0040000
|
||||
#define SSI0_BASE 0xB0043000
|
||||
#define SSI1_BASE 0xB0044000
|
||||
#define SSI2_BASE 0xB0045000
|
||||
#define I2C0_BASE 0xB0050000
|
||||
#define I2C1_BASE 0xB0051000
|
||||
#define I2C2_BASE 0xB0052000
|
||||
#define PS2_BASE 0xB0060000
|
||||
#define SADC_BASE 0xB0070000
|
||||
#define OWI_BASE 0xB0072000
|
||||
#define TSSI_BASE 0xB0073000
|
||||
|
||||
/* NAND CHIP Base Address*/
|
||||
#define NEMC_CS1_IOBASE 0Xbb000000
|
||||
#define NEMC_CS2_IOBASE 0Xba000000
|
||||
#define NEMC_CS3_IOBASE 0Xb9000000
|
||||
#define NEMC_CS4_IOBASE 0Xb8000000
|
||||
#define NEMC_CS5_IOBASE 0Xb7000000
|
||||
#define NEMC_CS6_IOBASE 0Xb6000000
|
||||
|
||||
/*********************************************************************************************************
|
||||
** WDT
|
||||
*********************************************************************************************************/
|
||||
#define WDT_TDR (0x00)
|
||||
#define WDT_TCER (0x04)
|
||||
#define WDT_TCNT (0x08)
|
||||
#define WDT_TCSR (0x0C)
|
||||
|
||||
#define REG_WDT_TDR REG16(WDT_BASE + WDT_TDR)
|
||||
#define REG_WDT_TCER REG8(WDT_BASE + WDT_TCER)
|
||||
#define REG_WDT_TCNT REG16(WDT_BASE + WDT_TCNT)
|
||||
#define REG_WDT_TCSR REG16(WDT_BASE + WDT_TCSR)
|
||||
|
||||
#define WDT_TSCR_WDTSC (1 << 16)
|
||||
|
||||
#define WDT_TCSR_PRESCALE_1 (0 << 3)
|
||||
#define WDT_TCSR_PRESCALE_4 (1 << 3)
|
||||
#define WDT_TCSR_PRESCALE_16 (2 << 3)
|
||||
#define WDT_TCSR_PRESCALE_64 (3 << 3)
|
||||
#define WDT_TCSR_PRESCALE_256 (4 << 3)
|
||||
#define WDT_TCSR_PRESCALE_1024 (5 << 3)
|
||||
|
||||
#define WDT_TCSR_EXT_EN (1 << 2)
|
||||
#define WDT_TCSR_RTC_EN (1 << 1)
|
||||
#define WDT_TCSR_PCK_EN (1 << 0)
|
||||
|
||||
#define WDT_TCER_TCEN (1 << 0)
|
||||
|
||||
/* RTC Reg */
|
||||
#define RTC_RTCCR (0x00) /* rw, 32, 0x00000081 */
|
||||
#define RTC_RTCSR (0x04) /* rw, 32, 0x???????? */
|
||||
#define RTC_RTCSAR (0x08) /* rw, 32, 0x???????? */
|
||||
#define RTC_RTCGR (0x0c) /* rw, 32, 0x0??????? */
|
||||
#define RTC_HCR (0x20) /* rw, 32, 0x00000000 */
|
||||
#define RTC_HWFCR (0x24) /* rw, 32, 0x0000???0 */
|
||||
#define RTC_HRCR (0x28) /* rw, 32, 0x00000??0 */
|
||||
#define RTC_HWCR (0x2c) /* rw, 32, 0x00000008 */
|
||||
#define RTC_HWRSR (0x30) /* rw, 32, 0x00000000 */
|
||||
#define RTC_HSPR (0x34) /* rw, 32, 0x???????? */
|
||||
#define RTC_WENR (0x3c) /* rw, 32, 0x00000000 */
|
||||
#define RTC_CKPCR (0x40) /* rw, 32, 0x00000010 */
|
||||
#define RTC_OWIPCR (0x44) /* rw, 32, 0x00000010 */
|
||||
#define RTC_PWRONCR (0x48) /* rw, 32, 0x???????? */
|
||||
|
||||
#define RTCCR_WRDY BIT(7)
|
||||
#define WENR_WEN BIT(31)
|
||||
|
||||
#define RECOVERY_SIGNATURE (0x001a1a)
|
||||
#define REBOOT_SIGNATURE (0x003535)
|
||||
#define UNMSAK_SIGNATURE (0x7c0000)//do not use these bits
|
||||
|
||||
|
||||
#include "x1000_cpm.h"
|
||||
#include "x1000_intc.h"
|
||||
#include "x1000_otg_dwc.h"
|
||||
#include "x1000_aic.h"
|
||||
#include "x1000_slcdc.h"
|
||||
|
||||
#endif /* _JZ_M150_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,120 +0,0 @@
|
||||
/*
|
||||
* File : x1000_intc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-02-03 Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _X1000_INTC_H_
|
||||
#define _X1000_INTC_H_
|
||||
|
||||
|
||||
/*
|
||||
* INTC (Interrupt Controller)
|
||||
*/
|
||||
#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20)
|
||||
#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20)
|
||||
#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20)
|
||||
#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20)
|
||||
#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20)
|
||||
|
||||
#define REG_INTC_ISR(n) REG32(INTC_ISR((n)))
|
||||
#define REG_INTC_IMR(n) REG32(INTC_IMR((n)))
|
||||
#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n)))
|
||||
#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n)))
|
||||
#define REG_INTC_IPR(n) REG32(INTC_IPR((n)))
|
||||
|
||||
// interrupt controller interrupts
|
||||
#define IRQ_DMIC 0
|
||||
#define IRQ_AIC0 1
|
||||
#define IRQ_RESERVED2 2
|
||||
#define IRQ_RESERVED3 3
|
||||
#define IRQ_RESERVED4 4
|
||||
#define IRQ_RESERVED5 5
|
||||
#define IRQ_RESERVED6 6
|
||||
#define IRQ_SFC 7
|
||||
#define IRQ_SSI0 8
|
||||
#define IRQ_RESERVED9 9
|
||||
#define IRQ_PDMA 10
|
||||
#define IRQ_PDMAD 11
|
||||
#define IRQ_RESERVED12 12
|
||||
#define IRQ_RESERVED13 13
|
||||
#define IRQ_GPIO3 14
|
||||
#define IRQ_GPIO2 15
|
||||
#define IRQ_GPIO1 16
|
||||
#define IRQ_GPIO0 17
|
||||
#define IRQ_RESERVED18 18
|
||||
#define IRQ_RESERVED19 19
|
||||
#define IRQ_RESERVED20 20
|
||||
#define IRQ_OTG 21
|
||||
#define IRQ_RESERVED22 22
|
||||
#define IRQ_AES 23
|
||||
#define IRQ_RESERVED24 24
|
||||
#define IRQ_TCU2 25
|
||||
#define IRQ_TCU1 26
|
||||
#define IRQ_TCU0 27
|
||||
#define IRQ_RESERVED28 28
|
||||
#define IRQ_RESERVED29 29
|
||||
#define IRQ_CIM 30
|
||||
#define IRQ_LCD 31
|
||||
#define IRQ_RTC 32
|
||||
#define IRQ_RESERVED33 33
|
||||
#define IRQ_RESERVED34 34
|
||||
#define IRQ_RESERVED35 35
|
||||
#define IRQ_MSC1 36
|
||||
#define IRQ_MSC0 37
|
||||
#define IRQ_SCC 38
|
||||
#define IRQ_RESERVED39 39
|
||||
#define IRQ_PCM0 40
|
||||
#define IRQ_RESERVED41 41
|
||||
#define IRQ_RESERVED42 42
|
||||
#define IRQ_RESERVED43 43
|
||||
#define IRQ_HARB2 44
|
||||
#define IRQ_RESERVED45 45
|
||||
#define IRQ_HARB0 46
|
||||
#define IRQ_CPM 47
|
||||
#define IRQ_RESERVED48 48
|
||||
#define IRQ_UART2 49
|
||||
#define IRQ_UART1 50
|
||||
#define IRQ_UART0 51
|
||||
#define IRQ_DDR 52
|
||||
#define IRQ_RESERVED53 53
|
||||
#define IRQ_EFUSE 54
|
||||
#define IRQ_MAC 55
|
||||
#define IRQ_RESERVED56 56
|
||||
#define IRQ_RESERVED57 57
|
||||
#define IRQ_I2C2 58
|
||||
#define IRQ_I2C1 59
|
||||
#define IRQ_I2C0 60
|
||||
#define IRQ_PDMAM 61
|
||||
#define IRQ_JPEG 62
|
||||
#define IRQ_RESERVED63 63
|
||||
|
||||
#define IRQ_INTC_MAX 63
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
|
||||
#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
|
||||
#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _X1000_INTC_H_ */
|
||||
@@ -1,306 +0,0 @@
|
||||
/*
|
||||
* File : x1000_otg_dwc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-02-03 Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef _X1000_OTG_DWC_H_
|
||||
#define _X1000_OTG_DWC_H_
|
||||
|
||||
/* Globle Regs define */
|
||||
#define GOTG_CTL (OTG_BASE + 0x00)
|
||||
#define GOTG_INTR (OTG_BASE + 0x04)
|
||||
#define GAHB_CFG (OTG_BASE + 0x08)
|
||||
#define GUSB_CFG (OTG_BASE + 0x0c)
|
||||
#define GRST_CTL (OTG_BASE + 0x10)
|
||||
#define GINT_STS (OTG_BASE + 0x14)
|
||||
#define GINT_MASK (OTG_BASE + 0x18)
|
||||
#define GRXSTS_READ (OTG_BASE + 0x1c)
|
||||
#define GRXSTS_POP (OTG_BASE + 0x20)
|
||||
#define GRXFIFO_SIZE (OTG_BASE + 0x24)
|
||||
#define GNPTXFIFO_SIZE (OTG_BASE + 0x28)
|
||||
#define GDTXFIFO_SIZE (OTG_BASE + 0x104)
|
||||
#define GHW_CFG1 (OTG_BASE + 0x44)
|
||||
#define GHW_CFG2 (OTG_BASE + 0x48)
|
||||
#define GHW_CFG3 (OTG_BASE + 0x4c)
|
||||
#define GHW_CFG4 (OTG_BASE + 0x50)
|
||||
#define GDFIFO_CFG (OTG_BASE + 0x5c)
|
||||
#define PCGC_CTL (OTG_BASE + 0xe00)
|
||||
|
||||
/* Fifo number 1 ~ 15 */
|
||||
#define GDEIP_TXF(n) (OTG_BASE + (0x104 + ((n-1) * 0x4)))
|
||||
|
||||
#define REG_GOTG_CTL REG32(GOTG_CTL)
|
||||
#define REG_GOTG_INTR REG32(GOTG_INTR)
|
||||
#define REG_GAHB_CFG REG32(GAHB_CFG)
|
||||
#define REG_GUSB_CFG REG32(GUSB_CFG)
|
||||
#define REG_GRST_CTL REG32(GRST_CTL)
|
||||
#define REG_GINT_STS REG32(GINT_STS)
|
||||
#define REG_GINT_MASK REG32(GINT_MASK)
|
||||
#define REG_GRXSTS_READ REG32(GRXSTS_READ)
|
||||
#define REG_GRXSTS_POP REG32(GRXSTS_POP)
|
||||
#define REG_GRXFIFO_SIZE REG32(GRXFIFO_SIZE)
|
||||
#define REG_GNPTXFIFO_SIZE REG32(GNPTXFIFO_SIZE)
|
||||
#define REG_GDTXFIFO_SIZE REG32(GDTXFIFO_SIZE)
|
||||
#define REG_GHW_CFG1 REG32(GHW_CFG1)
|
||||
#define REG_GHW_CFG2 REG32(GHW_CFG2)
|
||||
#define REG_GHW_CFG3 REG32(GHW_CFG3)
|
||||
#define REG_GHW_CFG4 REG32(GHW_CFG4)
|
||||
#define REG_GDFIFO_CFG REG32(GDFIFO_CFG)
|
||||
#define REG_GDIEP_TXF(n) REG32(GDEIP_TXF(n))
|
||||
#define REG_PCGC_CTL REG32(PCGC_CTL)
|
||||
/* Device Regs define */
|
||||
#define EP_FIFO(n) (OTG_BASE + (n+1)*0x1000) // FiX ME
|
||||
#define REG_EP_FIFO(n) REG32(EP_FIFO(n))
|
||||
|
||||
|
||||
#define OTG_DCFG (OTG_BASE + 0x800)
|
||||
#define OTG_DCTL (OTG_BASE + 0x804)
|
||||
#define OTG_DSTS (OTG_BASE + 0x808)
|
||||
#define DIEP_MASK (OTG_BASE + 0x810)
|
||||
#define DOEP_MASK (OTG_BASE + 0x814)
|
||||
#define OTG_DAINT (OTG_BASE + 0x818)
|
||||
#define DAINT_MASK (OTG_BASE + 0x81c)
|
||||
|
||||
#define DIEP_EMPMSK (OTG_BASE + 0x834)
|
||||
|
||||
|
||||
/* It's used in OTG_MULT_PROC_INTRPT = 1
|
||||
#define DEACH_INT (OTG_BASE + 0x838)
|
||||
#define DEACH_INTMASK (OTG_BASE + 0x83c)
|
||||
#define DIEP0_INTMASK (OTG_BASE + 0x840)
|
||||
#define DIEP1_INTMASK (OTG_BASE + 0x844)
|
||||
#define DOEP0_INTMASK (OTG_BASE + 0x880)
|
||||
#define DOEP1_INTMASK (OTG_BASE + 0x884)
|
||||
*/
|
||||
|
||||
#define DIEP_CTL(n) (OTG_BASE + (0x900 + (n)*0x20))
|
||||
#define DOEP_CTL(n) (OTG_BASE + (0xb00 + (n)*0x20))
|
||||
|
||||
#define DIEP_INT(n) (OTG_BASE + (0x908 + (n)*0x20))
|
||||
#define DOEP_INT(n) (OTG_BASE + (0xb08 + (n)*0x20))
|
||||
|
||||
#define DIEP_SIZE(n) (OTG_BASE + (0x910 + (n)*0x20))
|
||||
#define DOEP_SIZE(n) (OTG_BASE + (0xb10 + (n)*0x20))
|
||||
|
||||
#define DIEP_TXFSTS(n) (OTG_BASE + (0x918 + (n)*0x20))
|
||||
|
||||
#define DIEP_DMA(n) (OTG_BASE + (0x914 + (n)*0x20))
|
||||
#define DOEP_DMA(n) (OTG_BASE + (0xb14 + (n)*0x20))
|
||||
|
||||
#define REG_OTG_DCFG REG32(OTG_DCFG)
|
||||
#define REG_OTG_DCTL REG32(OTG_DCTL)
|
||||
#define REG_OTG_DSTS REG32(OTG_DSTS)
|
||||
#define REG_DIEP_MASK REG32(DIEP_MASK)
|
||||
#define REG_DOEP_MASK REG32(DOEP_MASK)
|
||||
#define REG_OTG_DAINT REG32(OTG_DAINT)
|
||||
#define REG_DAINT_MASK REG32(DAINT_MASK)
|
||||
#define REG_DIEP_EMPMSK REG32(DIEP_EMPMSK)
|
||||
|
||||
#define REG_DIEP_CTL(n) REG32(DIEP_CTL(n))
|
||||
#define REG_DOEP_CTL(n) REG32(DOEP_CTL(n))
|
||||
|
||||
#define REG_DIEP_INT(n) REG32(DIEP_INT(n))
|
||||
#define REG_DOEP_INT(n) REG32(DOEP_INT(n))
|
||||
|
||||
#define REG_DIEP_SIZE(n) REG32(DIEP_SIZE(n))
|
||||
#define REG_DOEP_SIZE(n) REG32(DOEP_SIZE(n))
|
||||
|
||||
#define REG_DIEP_TXFSTS(n) REG32(DIEP_TXFSTS(n))
|
||||
|
||||
#define REG_DIEP_DMA(n) REG32(DIEP_DMA(n))
|
||||
#define REG_DOEP_DMA(n) REG32(DOEP_DMA(n))
|
||||
|
||||
/* Regs macro define */
|
||||
/*************************************************/
|
||||
#define AHBCFG_TXFE_LVL BIT7
|
||||
#define AHBCFG_DMA_ENA BIT5
|
||||
#define AHBCFG_GLOBLE_INTRMASK BIT0
|
||||
#define USBCFG_FORCE_DEVICE BIT30
|
||||
#define USBCFG_TRDTIME_MASK (0xf << 10)
|
||||
#define USBCFG_TRDTIME_9 (9 << 10)
|
||||
#define USBCFG_TRDTIME_6 (6 << 10)
|
||||
|
||||
/* GRSTCTL */
|
||||
#define RSTCTL_AHB_IDLE BIT31
|
||||
#define RSTCTL_TXFNUM_ALL (0x10 << 6)
|
||||
#define RSTCTL_TXFIFO_FLUSH BIT5
|
||||
#define RSTCTL_RXFIFO_FLUSH BIT4
|
||||
#define RSTCTL_INTK_FLUSH BIT3
|
||||
#define RSTCTL_FRMCNT_RST BIT2
|
||||
#define RSTCTL_CORE_RST BIT0
|
||||
|
||||
/* GINTMSK */
|
||||
#define GINTMSK_RSUME_DETE BIT31
|
||||
#define GINTMSK_CONID_STSCHG BIT28
|
||||
#define GINTMSK_RESET_DETE BIT23
|
||||
#define GINTMSK_FETCH_SUSPEND BIT22
|
||||
#define GINTMSK_OEP_INTR BIT19
|
||||
#define GINTMSK_IEP_INTR BIT18
|
||||
#define GINTMSK_EP_MISMATCH BIT17
|
||||
#define GINTMSK_ENUM_DONE BIT13
|
||||
#define GINTMSK_USB_RESET BIT12
|
||||
#define GINTMSK_USB_SUSPEND BIT11
|
||||
#define GINTMSK_USB_EARLYSUSPEND BIT10
|
||||
#define GINTMSK_I2C_INT BIT9
|
||||
#define GINTMSK_ULPK_CKINT BIT8
|
||||
#define GINTMSK_GOUTNAK_EFF BIT7
|
||||
#define GINTMSK_GINNAK_EFF BIT6
|
||||
#define GINTMSK_NPTXFIFO_EMPTY BIT5
|
||||
#define GINTMSK_RXFIFO_NEMPTY BIT4
|
||||
#define GINTMSK_START_FRAM BIT3
|
||||
#define GINTMSK_OTG_INTR BIT2
|
||||
#define GINTMSK_MODE_MISMATCH BIT1
|
||||
|
||||
/* GINTSTS */
|
||||
#define GINTSTS_RSUME_DETE BIT31
|
||||
#define GINTSTS_CONID_STSCHG BIT28
|
||||
#define GINTSTS_RESET_DETE BIT23
|
||||
#define GINTSTS_FETCH_SUSPEND BIT22
|
||||
#define GINTSTS_OEP_INTR BIT19
|
||||
#define GINTSTS_IEP_INTR BIT18
|
||||
#define GINTSTS_EP_MISMATCH BIT17
|
||||
#define GINTSTS_ENUM_DONE BIT13
|
||||
#define GINTSTS_USB_RESET BIT12
|
||||
#define GINTSTS_USB_SUSPEND BIT11
|
||||
#define GINTSTS_USB_EARLYSUSPEND BIT10
|
||||
#define GINTSTS_I2C_INT BIT9
|
||||
#define GINTSTS_ULPK_CKINT BIT8
|
||||
#define GINTSTS_GOUTNAK_EFF BIT7
|
||||
#define GINTSTS_GINNAK_EFF BIT6
|
||||
#define GINTSTS_NPTXFIFO_EMPTY BIT5
|
||||
#define GINTSTS_RXFIFO_NEMPTY BIT4
|
||||
#define GINTSTS_START_FRAM BIT3
|
||||
#define GINTSTS_OTG_INTR BIT2
|
||||
#define GINTSTS_MODE_MISMATCH BIT1
|
||||
|
||||
/* DCTL */
|
||||
#define DCTL_CGOUTNAK BIT10
|
||||
#define DCTL_CLR_GNPINNAK BIT8
|
||||
#define DCTL_SGNPINNAK BIT7
|
||||
#define DCTL_SOFT_DISCONN BIT1
|
||||
#define DCTL_SGOUTNAK BIT9
|
||||
/* DCFG */
|
||||
#define DCFG_DEV_ADDR_MASK (0x7f << 4)
|
||||
#define DCFG_DEV_ADDR_BIT 4
|
||||
#define DCFG_DEV_DESC_DMA (1 << 23)
|
||||
/* DSTS */
|
||||
#define DSTS_ERRATIC_ERROR BIT3
|
||||
#define DSTS_ENUM_SPEED_MASK (0x3 << 1)
|
||||
#define DSTS_ENUM_SPEED_BIT BIT1
|
||||
#define DSTS_ENUM_SPEED_HIGH (0x0 << 1)
|
||||
#define DSTS_ENUM_SPEED_FULL_30OR60 (0x1 << 1)
|
||||
#define DSTS_ENUM_SPEED_LOW (0x2 << 1)
|
||||
#define DSTS_ENUM_SPEED_FULL_48 (0x3 << 1)
|
||||
|
||||
/* GRXSTSR/GRXSTSP */
|
||||
#define GRXSTSP_PKSTS_MASK (0xf << 17)
|
||||
#define GRXSTSP_PKSTS_GOUT_NAK (0x1 << 17)
|
||||
#define GRXSTSP_PKSTS_GOUT_RECV (0x2 << 17)
|
||||
#define GRXSTSP_PKSTS_TX_COMP (0x3 << 17)
|
||||
#define GRXSTSP_PKSTS_SETUP_COMP (0x4 << 17)
|
||||
#define GRXSTSP_PKSTS_SETUP_RECV (0x6 << 17)
|
||||
#define GRXSTSP_BYTE_CNT_MASK (0x7ff << 4)
|
||||
#define GRXSTSP_BYTE_CNT_BIT 4
|
||||
#define GRXSTSP_EPNUM_MASK (0xf)
|
||||
#define GRXSTSP_EPNUM_BIT BIT0
|
||||
|
||||
|
||||
/* DIOEPCTL */
|
||||
// ep0
|
||||
#define DEP_EP0_MAXPKET_SIZE 64
|
||||
#define DEP_EP0_MPS_64 (0x0)
|
||||
#define DEP_EP0_MPS_32 (0x1)
|
||||
#define DEP_EP0_MPS_16 (0x2)
|
||||
#define DEP_EP0_MPS_8 (0x3)
|
||||
|
||||
#define DEP_ENA_BIT BIT31
|
||||
#define DEP_DISENA_BIT BIT30
|
||||
#define DEP_SET_NAK BIT27
|
||||
#define DEP_CLEAR_NAK BIT26
|
||||
#define DEP_SET_STALL BIT21
|
||||
#define DEP_TYPE_MASK (0x3 << 18)
|
||||
#define DEP_TYPE_CNTL (0x0 << 18)
|
||||
#define DEP_TYPE_ISO (0x1 << 18)
|
||||
#define DEP_TYPE_BULK (0x2 << 18)
|
||||
#define DEP_TYPE_INTR (0x3 << 18)
|
||||
#define USB_ACTIVE_EP BIT15
|
||||
#define DEP_PKTSIZE_MASK 0x7ff
|
||||
#define DEP_FS_PKTSIZE 64
|
||||
#define DEP_HS_PKTSIZE 512
|
||||
|
||||
/* DIOEPINT */
|
||||
#define DEP_NYET_INT BIT14
|
||||
#define DEP_NAK_INT BIT13
|
||||
#define DEP_BABBLE_ERR_INT BIT12
|
||||
#define DEP_PKT_DROP_STATUS BIT11
|
||||
#define DEP_BNA_INT BIT9
|
||||
#define DEP_TXFIFO_UNDRN BIT8 // Only for INEP
|
||||
#define DEP_OUTPKT_ERR BIT8 // Only for OUTEP
|
||||
#define DEP_TXFIFO_EMPTY BIT7
|
||||
#define DEP_INEP_NAKEFF BIT6 // Only for INEP
|
||||
#define DEP_B2B_SETUP_RECV BIT6 // Only for OUTEP0
|
||||
#define DEP_INTOKEN_EPMISATCH BIT5 // Only for INEP
|
||||
#define DEP_STATUS_PHASE_RECV BIT5 // Only for OUTEP0
|
||||
#define DEP_INTOKEN_RECV_TXFIFO_EMPTY BIT4 // Only for INEP
|
||||
#define DEP_OUTTOKEN_RECV_EPDIS BIT4 // Only for OUTEP
|
||||
#define DEP_TIME_OUT BIT3 // Only for INEP
|
||||
#define DEP_SETUP_PHASE_DONE BIT3 // Only for OUTEP0
|
||||
#define DEP_AHB_ERR BIT2
|
||||
#define DEP_EPDIS_INT BIT1
|
||||
#define DEP_XFER_COMP BIT0 // Used by INEP and OUTEP
|
||||
|
||||
/* DOEPSIZ0 */
|
||||
#define DOEPSIZE0_SUPCNT_1 (0x1 << 29)
|
||||
#define DOEPSIZE0_SUPCNT_2 (0x2 << 29)
|
||||
#define DOEPSIZE0_SUPCNT_3 (0x3 << 29)
|
||||
#define DOEPSIZE0_PKTCNT_BIT BIT19
|
||||
|
||||
|
||||
#define DEP_RXFIFO_SIZE 1064
|
||||
#define DEP_NPTXFIFO_SIZE 1024
|
||||
#define DEP_DTXFIFO_SIZE 768
|
||||
|
||||
|
||||
#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
|
||||
#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
|
||||
#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
|
||||
#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
|
||||
#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
|
||||
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_1word 0x0
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_4word 0x1
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_8word 0x2
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_16word 0x3
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_32word 0x4
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_64word 0x5
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_128word 0x6
|
||||
#define DWC_GAHBCFG_EXT_DMA_BURST_256word 0x7
|
||||
|
||||
#define DEP_NUM 2
|
||||
|
||||
#if 0
|
||||
#define UTMI_PHY_WIDTH 8
|
||||
#else
|
||||
#define UTMI_PHY_WIDTH 16
|
||||
#endif
|
||||
|
||||
#endif /* _X1000_OTG_DWC_H_ */
|
||||
@@ -1,463 +0,0 @@
|
||||
/*
|
||||
* File : x1000_slcdc.h
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017Äê3ÔÂ20ÈÕ Urey the first version
|
||||
*/
|
||||
#ifndef _X1000_SLCDC_H_
|
||||
#define _X1000_SLCDC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*************************************************************************
|
||||
* SLCD (Smart LCD Controller)
|
||||
*************************************************************************/
|
||||
#define LCDC0_BASE LCD_BASE
|
||||
|
||||
#define SLCDC_CFG (LCDC0_BASE + 0xA0) /* SLCDC Configure Register */
|
||||
#define SLCDC_CTRL (LCDC0_BASE + 0xA4) /* SLCDC Control Register */
|
||||
#define SLCDC_STATE (LCDC0_BASE + 0xA8) /* SLCDC Status Register */
|
||||
#define SLCDC_DATA (LCDC0_BASE + 0xAC) /* SLCDC Data Register */
|
||||
|
||||
#define SLCDC_CFG_NEW (LCDC0_BASE + 0xB8)
|
||||
#define SLCDC_WTIME (LCDC0_BASE + 0xB0)
|
||||
#define SLCDC_TAS (LCDC0_BASE + 0xB4)
|
||||
#define SLCDC_SLOW_TIME (LCDC0_BASE + 0xBC)
|
||||
|
||||
/* SLCDC Configure Register */
|
||||
#define SLCDC_CFG_DWIDTH_BIT 10
|
||||
#define SLCDC_CFG_DWIDTH_MASK (0x7 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_DWIDTH_18BIT (0 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_DWIDTH_16BIT (1 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_DWIDTH_8BIT_x3 (2 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_DWIDTH_8BIT_x2 (3 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_DWIDTH_8BIT_x1 (4 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_DWIDTH_24BIT (5 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_DWIDTH_9BIT_x2 (7 << SLCDC_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_CFG_CWIDTH_BIT (8)
|
||||
#define SLCDC_CFG_CWIDTH_MASK (0x3 << SLCDC_CFG_CWIDTH_BIT)
|
||||
#define SLCDC_CFG_CWIDTH_16BIT (0 << SLCDC_CFG_CWIDTH_BIT)
|
||||
#define SLCDC_CFG_CWIDTH_8BIT (1 << SLCDC_CFG_CWIDTH_BIT)
|
||||
#define SLCDC_CFG_CWIDTH_18BIT (2 << SLCDC_CFG_CWIDTH_BIT)
|
||||
#define SLCDC_CFG_CWIDTH_24BIT (3 << SLCDC_CFG_CWIDTH_BIT)
|
||||
#define SLCDC_CFG_CS_ACTIVE_LOW (0 << 4)
|
||||
#define SLCDC_CFG_CS_ACTIVE_HIGH (1 << 4)
|
||||
#define SLCDC_CFG_RS_CMD_LOW (0 << 3)
|
||||
#define SLCDC_CFG_RS_CMD_HIGH (1 << 3)
|
||||
#define SLCDC_CFG_CLK_ACTIVE_FALLING (0 << 1)
|
||||
#define SLCDC_CFG_CLK_ACTIVE_RISING (1 << 1)
|
||||
#define SLCDC_CFG_TYPE_PARALLEL (0 << 0)
|
||||
#define SLCDC_CFG_TYPE_SERIAL (1 << 0)
|
||||
|
||||
/* SLCD New Configure Register */
|
||||
#define SLCDC_NEW_CFG_DWIDTH_BIT 13
|
||||
#define SLCDC_NEW_CFG_DWIDTH_MASK (0x7 << SLCDC_NEW_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_NEW_CFG_DWIDTH_8BIT (0 << SLCDC_NEW_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_NEW_CFG_DWIDTH_9BIT (1 << SLCDC_NEW_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_NEW_CFG_DWIDTH_16BIT (2 << SLCDC_NEW_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_NEW_CFG_DWIDTH_18BIT (3 << SLCDC_NEW_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_NEW_CFG_DWIDTH_24BIT (4 << SLCDC_NEW_CFG_DWIDTH_BIT)
|
||||
#define SLCDC_NEW_CFG_6800_MD (1 << 11)
|
||||
#define SLCDC_NEW_CFG_CMD_9BIT (1 << 10) /* only use in old slcd */
|
||||
#define SLCDC_NEW_CFG_CMD_16BIT (0 << 10) /* only use in old slcd */
|
||||
#define SLCDC_NEW_CFG_DTIME_BIT 8
|
||||
#define SLCDC_NEW_CFG_DTIME_MASK (0x3 << SLCDC_NEW_CFG_DTIME_BIT)
|
||||
#define SLCDC_NEW_CFG_DTIME_ONCE (0 << SLCDC_NEW_CFG_DTIME_BIT)
|
||||
#define SLCDC_NEW_CFG_DTIME_TWICE (1 << SLCDC_NEW_CFG_DTIME_BIT)
|
||||
#define SLCDC_NEW_CFG_DTIME_THREE (2 << SLCDC_NEW_CFG_DTIME_BIT)
|
||||
#define SLCDC_NEW_CFG_CS_HIGH_IDLE (0 << 5)
|
||||
#define SLCDC_NEW_CFG_CS_LOW_IDLE (1 << 5)
|
||||
#define SLCDC_NEW_CFG_RS_CMD_LOW (0 << 4)
|
||||
#define SLCDC_NEW_CFG_RS_CMD_HIGH (1 << 4)
|
||||
#define SLCDC_NEW_CFG_CLK_ACTIVE_FALLING (0 << 3)
|
||||
#define SLCDC_NEW_CFG_CLK_ACTIVE_RISING (1 << 3)
|
||||
#define SLCDC_NEW_CFG_DTYPE_PARALLEL (0 << 2)
|
||||
#define SLCDC_NEW_CFG_DTYPE_SERIAL (1 << 2)
|
||||
#define SLCDC_NEW_CFG_CTYPE_PARALLEL (0 << 1)
|
||||
#define SLCDC_NEW_CFG_CTYPE_SERIAL (1 << 1)
|
||||
#define SLCDC_NEW_CFG_FMT_CONV_EN (1 << 0)
|
||||
|
||||
/* SLCD Control Register */
|
||||
#define SLCDC_CTRL_TE_INV (1 << 9)
|
||||
#define SLCDC_CTRL_NOT_USE_TE (1 << 8)
|
||||
#define SLCDC_CTRL_DCSI_SEL (1 << 7)
|
||||
#define SLCDC_CTRL_MIPI_MODE (1 << 6)
|
||||
#define SLCDC_CTRL_NEW_MODE (1 << 5)
|
||||
#define SLCDC_CTRL_FAST_MODE (1 << 4)
|
||||
#define SLCDC_CTRL_GATE_MASK (1 << 3)
|
||||
#define SLCDC_CTRL_DMA_MODE (1 << 2)
|
||||
#define SLCDC_CTRL_DMA_START (1 << 1)
|
||||
#define SLCDC_CTRL_DMA_EN (1 << 0)
|
||||
|
||||
/* SLCD Status Register */
|
||||
#define SLCDC_STATE_BUSY (1 << 0)
|
||||
|
||||
/* SLCD Data Register */
|
||||
#define SLCDC_DATA_RS_DATA (0 << 30)
|
||||
#define SLCDC_DATA_RS_COMMAND (1 << 30)
|
||||
|
||||
/*************************************************************************
|
||||
* LCDC (LCD Controller)
|
||||
*************************************************************************/
|
||||
|
||||
#define LCDC_CFG (LCDC0_BASE + 0x00)
|
||||
#define LCDC_CTRL (LCDC0_BASE + 0x30)
|
||||
#define LCDC_STATE (LCDC0_BASE + 0x34)
|
||||
#define LCDC_OSDC (LCDC0_BASE + 0x100)
|
||||
#define LCDC_OSDCTRL (LCDC0_BASE + 0x104)
|
||||
#define LCDC_OSDS (LCDC0_BASE + 0x108)
|
||||
#define LCDC_BGC0 (LCDC0_BASE + 0x10C)
|
||||
#define LCDC_BGC1 (LCDC0_BASE + 0x2C4)
|
||||
#define LCDC_KEY0 (LCDC0_BASE + 0x110)
|
||||
#define LCDC_KEY1 (LCDC0_BASE + 0x114)
|
||||
#define LCDC_ALPHA (LCDC0_BASE + 0x118)
|
||||
#define LCDC_RGBC (LCDC0_BASE + 0x90)
|
||||
#define LCDC_VAT (LCDC0_BASE + 0x0c)
|
||||
#define LCDC_DAH (LCDC0_BASE + 0x10)
|
||||
#define LCDC_DAV (LCDC0_BASE + 0x14)
|
||||
#define LCDC_XYP0 (LCDC0_BASE + 0x120)
|
||||
#define LCDC_XYP1 (LCDC0_BASE + 0x124)
|
||||
#define LCDC_SIZE0 (LCDC0_BASE + 0x128)
|
||||
#define LCDC_SIZE1 (LCDC0_BASE + 0x12C)
|
||||
#define LCDC_VSYNC (LCDC0_BASE + 0x04)
|
||||
#define LCDC_HSYNC (LCDC0_BASE + 0x08)
|
||||
#define LCDC_PS (LCDC0_BASE + 0x18)
|
||||
#define LCDC_CLS (LCDC0_BASE + 0x1c)
|
||||
#define LCDC_SPL (LCDC0_BASE + 0x20)
|
||||
#define LCDC_REV (LCDC0_BASE + 0x24)
|
||||
#define LCDC_IID (LCDC0_BASE + 0x38)
|
||||
#define LCDC_DA0 (LCDC0_BASE + 0x40)
|
||||
#define LCDC_SA0 (LCDC0_BASE + 0x44)
|
||||
#define LCDC_FID0 (LCDC0_BASE + 0x48)
|
||||
#define LCDC_CMD0 (LCDC0_BASE + 0x4c)
|
||||
#define LCDC_DA1 (LCDC0_BASE + 0x50)
|
||||
#define LCDC_SA1 (LCDC0_BASE + 0x54)
|
||||
#define LCDC_FID1 (LCDC0_BASE + 0x58)
|
||||
#define LCDC_CMD1 (LCDC0_BASE + 0x5c)
|
||||
#define LCDC_OFFS0 (LCDC0_BASE + 0x60)
|
||||
#define LCDC_PW0 (LCDC0_BASE + 0x64)
|
||||
#define LCDC_CNUM0 (LCDC0_BASE + 0x68)
|
||||
#define LCDC_DESSIZE0 (LCDC0_BASE + 0x6C)
|
||||
#define LCDC_OFFS1 (LCDC0_BASE + 0x70)
|
||||
#define LCDC_PW1 (LCDC0_BASE + 0x74)
|
||||
#define LCDC_CNUM1 (LCDC0_BASE + 0x78)
|
||||
#define LCDC_DESSIZE1 (LCDC0_BASE + 0x7C)
|
||||
#define LCDC_PCFG (LCDC0_BASE + 0x2C0)
|
||||
#define LCDC_CPOS1 (0x78)
|
||||
#define LCDC_DUAL_CTRL (0x2c8)
|
||||
#define LCDC_ENH_CFG (0x400)
|
||||
#define LCDC_ENH_CSCCFG (0x404)
|
||||
#define LCDC_ENH_LUMACFG (0x408)
|
||||
#define LCDC_ENH_CHROCFG0 (0x40c)
|
||||
#define LCDC_ENH_CHROCFG1 (0x410)
|
||||
#define LCDC_ENH_DITHERCFG (0x414)
|
||||
#define LCDC_ENH_STATUS (0x418)
|
||||
#define LCDC_ENH_GAMMA (0x800)
|
||||
#define LCDC_ENH_VEE (0x1000)
|
||||
|
||||
/* LCD Configure Register */
|
||||
#define LCDC_CFG_LCDPIN_BIT 31
|
||||
#define LCDC_CFG_LCDPIN_MASK (0x1 << LCDC_CFG_LCDPIN_BIT)
|
||||
#define LCDC_CFG_LCDPIN_LCD (0x0 << LCDC_CFG_LCDPIN_BIT)
|
||||
#define LCDC_CFG_LCDPIN_SLCD (0x1 << LCDC_CFG_LCDPIN_BIT)
|
||||
#define LCDC_CFG_TVEPEH (1 << 30)
|
||||
#define LCDC_CFG_NEWDES (1 << 28)
|
||||
#define LCDC_CFG_PALBP (1 << 27)
|
||||
#define LCDC_CFG_TVEN (1 << 26)
|
||||
#define LCDC_CFG_RECOVER (1 << 25)
|
||||
#define LCDC_CFG_PSM (1 << 23)
|
||||
#define LCDC_CFG_CLSM (1 << 22)
|
||||
#define LCDC_CFG_SPLM (1 << 21)
|
||||
#define LCDC_CFG_REVM (1 << 20)
|
||||
#define LCDC_CFG_HSYNM (1 << 19)
|
||||
#define LCDC_CFG_PCLKM (1 << 18)
|
||||
#define LCDC_CFG_INVDAT (1 << 17)
|
||||
#define LCDC_CFG_SYNDIR_IN (1 << 16)
|
||||
#define LCDC_CFG_PSP (1 << 15)
|
||||
#define LCDC_CFG_CLSP (1 << 14)
|
||||
#define LCDC_CFG_SPLP (1 << 13)
|
||||
#define LCDC_CFG_REVP (1 << 12)
|
||||
#define LCDC_CFG_HSP (1 << 11)
|
||||
#define LCDC_CFG_PCP (1 << 10)
|
||||
#define LCDC_CFG_DEP (1 << 9)
|
||||
#define LCDC_CFG_VSP (1 << 8)
|
||||
#define LCDC_CFG_MODE_TFT_18BIT (1 << 7)
|
||||
#define LCDC_CFG_MODE_TFT_16BIT (0 << 7)
|
||||
#define LCDC_CFG_MODE_TFT_24BIT (1 << 6)
|
||||
#define LCDC_CFG_MODE_BIT 0
|
||||
#define LCDC_CFG_MODE_MASK (0x0f << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_GENERIC_TFT (0 << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_SPECIAL_TFT_1 (1 << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_SPECIAL_TFT_2 (2 << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_SPECIAL_TFT_3 (3 << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_NONINTER_CCIR656 (4 << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_INTER_CCIR656 (6 << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_SERIAL_TFT (12 << LCDC_CFG_MODE_BIT)
|
||||
#define LCDC_CFG_MODE_LCM (13 << LCDC_CFG_MODE_BIT)
|
||||
/* LCD Control Register */
|
||||
#define LCDC_CTRL_PINMD (1 << 31)
|
||||
#define LCDC_CTRL_BST_BIT 28
|
||||
#define LCDC_CTRL_BST_MASK (0x7 << LCDC_CTRL_BST_BIT)
|
||||
#define LCDC_CTRL_BST_4 (0 << LCDC_CTRL_BST_BIT)
|
||||
#define LCDC_CTRL_BST_8 (1 << LCDC_CTRL_BST_BIT)
|
||||
#define LCDC_CTRL_BST_16 (2 << LCDC_CTRL_BST_BIT)
|
||||
#define LCDC_CTRL_BST_32 (3 << LCDC_CTRL_BST_BIT)
|
||||
#define LCDC_CTRL_BST_64 (4 << LCDC_CTRL_BST_BIT)
|
||||
#define LCDC_CTRL_RGB565 (0 << 27)
|
||||
#define LCDC_CTRL_RGB555 (1 << 27)
|
||||
#define LCDC_CTRL_OFUP (1 << 26)
|
||||
#define LCDC_CTRL_PDD_BIT 16
|
||||
#define LCDC_CTRL_PDD_MASK (0xff << LCDC_CTRL_PDD_BIT)
|
||||
#define LCDC_CTRL_DACTE (1 << 14)
|
||||
#define LCDC_CTRL_EOFM (1 << 13)
|
||||
#define LCDC_CTRL_SOFM (1 << 12)
|
||||
#define LCDC_CTRL_OFUM (1 << 11)
|
||||
#define LCDC_CTRL_IFUM0 (1 << 10)
|
||||
#define LCDC_CTRL_IFUM1 (1 << 9)
|
||||
#define LCDC_CTRL_LDDM (1 << 8)
|
||||
#define LCDC_CTRL_QDM (1 << 7)
|
||||
#define LCDC_CTRL_BEDN (1 << 6)
|
||||
#define LCDC_CTRL_PEDN (1 << 5)
|
||||
#define LCDC_CTRL_DIS (1 << 4)
|
||||
#define LCDC_CTRL_ENA (1 << 3)
|
||||
#define LCDC_CTRL_BPP_BIT 0
|
||||
#define LCDC_CTRL_BPP_MASK (0x07 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_1 (0 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_2 (1 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_4 (2 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_8 (3 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_16 (4 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_18_24 (5 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_CMPS_24 (6 << LCDC_CTRL_BPP_BIT)
|
||||
#define LCDC_CTRL_BPP_30 (7 << LCDC_CTRL_BPP_BIT)
|
||||
/* LCD Status Register */
|
||||
#define LCDC_STATE_QD (1 << 7)
|
||||
#define LCDC_STATE_EOF (1 << 5)
|
||||
#define LCDC_STATE_SOF (1 << 4)
|
||||
#define LCDC_STATE_OFU (1 << 3)
|
||||
#define LCDC_STATE_IFU0 (1 << 2)
|
||||
#define LCDC_STATE_IFU1 (1 << 1)
|
||||
#define LCDC_STATE_LDD (1 << 0)
|
||||
/* OSD Configure Register */
|
||||
#define LCDC_OSDC_PREMULTI1 (1 << 23)
|
||||
#define LCDC_OSDC_COEF_SLE1_BIT 21
|
||||
#define LCDC_OSDC_COEF_SLE1_MASK (0x03 << LCDC_OSDC_COEF_SLE1_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE1_0 (0 << LCDC_OSDC_COEF_SLE1_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE1_1 (1 << LCDC_OSDC_COEF_SLE1_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE1_2 (2 << LCDC_OSDC_COEF_SLE1_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE1_3 (3 << LCDC_OSDC_COEF_SLE1_BIT)
|
||||
#define LCDC_OSDC_PREMULTI0 (1 << 20)
|
||||
#define LCDC_OSDC_COEF_SLE0_BIT 18
|
||||
#define LCDC_OSDC_COEF_SLE0_MASK (0x03 << LCDC_OSDC_COEF_SLE0_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE0_0 (0 << LCDC_OSDC_COEF_SLE0_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE0_1 (1 << LCDC_OSDC_COEF_SLE0_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE0_2 (2 << LCDC_OSDC_COEF_SLE0_BIT)
|
||||
#define LCDC_OSDC_COEF_SLE0_3 (3 << LCDC_OSDC_COEF_SLE0_BIT)
|
||||
#define LCDC_OSDC_ALPHAMD1 (1 << 17)
|
||||
#define LCDC_OSDC_SOFM1 (1 << 15)
|
||||
#define LCDC_OSDC_EOFM1 (1 << 14)
|
||||
#define LCDC_OSDC_SOFM0 (1 << 11)
|
||||
#define LCDC_OSDC_EOFM0 (1 << 10)
|
||||
#define LCDC_OSDC_DENDM (1 << 9)
|
||||
#define LCDC_OSDC_F1EN (1 << 4)
|
||||
#define LCDC_OSDC_F0EN (1 << 3)
|
||||
#define LCDC_OSDC_ALPHAEN (1 << 2)
|
||||
#define LCDC_OSDC_ALPHAMD0 (1 << 1)
|
||||
#define LCDC_OSDC_OSDEN (1 << 0)
|
||||
/* OSD Controll Register */
|
||||
#define LCDC_OSDCTRL_IPU_CLKEN (1 << 15)
|
||||
#define LCDC_OSDCTRL_RGB0_RGB565 (0 << 5)
|
||||
#define LCDC_OSDCTRL_RGB0_RGB555 (1 << 5)
|
||||
#define LCDC_OSDCTRL_RGB1_RGB565 (0 << 4)
|
||||
#define LCDC_OSDCTRL_RGB1_RGB555 (1 << 4)
|
||||
#define LCDC_OSDCTRL_BPP_BIT 0
|
||||
#define LCDC_OSDCTRL_BPP_MASK (0x7<<LCDC_OSDCTRL_BPP_BIT)
|
||||
#define LCDC_OSDCTRL_BPP_15_16 (4 << LCDC_OSDCTRL_BPP_BIT)
|
||||
#define LCDC_OSDCTRL_BPP_18_24 (5 << LCDC_OSDCTRL_BPP_BIT)
|
||||
#define LCDC_OSDCTRL_BPP_CMPS_24 (6 << LCDC_OSDCTRL_BPP_BIT)
|
||||
#define LCDC_OSDCTRL_BPP_30 (7 << LCDC_OSDCTRL_BPP_BIT)
|
||||
/* OSD State Register */
|
||||
#define LCDC_OSDS_SOF1 (1 << 15)
|
||||
#define LCDC_OSDS_EOF1 (1 << 14)
|
||||
#define LCDC_OSDS_SOF0 (1 << 11)
|
||||
#define LCDC_OSDS_EOF0 (1 << 10)
|
||||
#define LCDC_OSDS_DEND (1 << 8)
|
||||
/* Background 0 or Background 1 Color Register */
|
||||
#define LCDC_BGC_RED_OFFSET 16
|
||||
#define LCDC_BGC_RED_MASK (0xFF << LCDC_BGC_RED_OFFSET)
|
||||
#define LCDC_BGC_GREEN_OFFSET 8
|
||||
#define LCDC_BGC_GREEN_MASK (0xFF << LCDC_BGC_GREEN_OFFSET)
|
||||
#define LCDC_BGC_BLUE_OFFSET 0
|
||||
#define LCDC_BGC_BLUE_MASK (0xFF << LCDC_BGC_BLUE_OFFSET)
|
||||
/* Foreground 0 or Foreground 1 Color Key Register */
|
||||
#define LCDC_KEY_KEYEN (1 << 31)
|
||||
#define LCDC_KEY_KEYMD (1 << 30)
|
||||
#define LCDC_KEY_RED_OFFSET 16
|
||||
#define LCDC_KEY_RED_MASK (0xFF << LCDC_KEY_RED_OFFSET)
|
||||
#define LCDC_KEY_GREEN_OFFSET 8
|
||||
#define LCDC_KEY_GREEN_MASK (0xFF << LCDC_KEY_GREEN_OFFSET)
|
||||
#define LCDC_KEY_BLUE_OFFSET 0
|
||||
#define LCDC_KEY_BLUE_MASK (0xFF << LCDC_KEY_BLUE_OFFSET)
|
||||
#define LCDC_KEY_MASK (LCDC_KEY_RED_MASK | LCDC_KEY_GREEN_MASK\
|
||||
/* ALPHA Register */
|
||||
#define LCDC_ALPHA1_OFFSET 8
|
||||
#define LCDC_ALPHA1_MASK (0xFF << LCDC_ALPHA1_OFFSET)
|
||||
#define LCDC_ALPHA0_OFFSET 0
|
||||
#define LCDC_ALPHA0_MASK (0xFF << LCDC_ALPHA0_OFFSET)
|
||||
/* IPU Restart Register */
|
||||
#define LCDC_IPUR_IPUREN (1 << 31)
|
||||
#define LCDC_IPUR_IPURMASK (0xFFFFFF)
|
||||
/* RGB Control Register */
|
||||
#define LCDC_RGBC_RGBDM (1 << 15)
|
||||
#define LCDC_RGBC_DMM (1 << 14)
|
||||
#define LCDC_RGBC_RGBFMT (1 << 7)
|
||||
#define LCDC_RGBC_ODDRGB_BIT 4
|
||||
#define LCDC_RGBC_ODDRGB_MASK (0x7 << LCDC_RGBC_ODDRGB_BIT)
|
||||
#define LCDC_RGBC_ODD_RGB (0 << LCDC_RGBC_ODDRGB_BIT)
|
||||
#define LCDC_RGBC_ODD_RBG (1 << LCDC_RGBC_ODDRGB_BIT)
|
||||
#define LCDC_RGBC_ODD_GRB (2 << LCDC_RGBC_ODDRGB_BIT)
|
||||
#define LCDC_RGBC_ODD_GBR (3 << LCDC_RGBC_ODDRGB_BIT)
|
||||
#define LCDC_RGBC_ODD_BRG (4 << LCDC_RGBC_ODDRGB_BIT)
|
||||
#define LCDC_RGBC_ODD_BGR (5 << LCDC_RGBC_ODDRGB_BIT)
|
||||
#define LCDC_RGBC_EVENRGB_BIT 0
|
||||
#define LCDC_RGBC_EVENRGB_MASK (0x7<<LCDC_RGBC_EVENRGB_BIT)
|
||||
#define LCDC_RGBC_EVEN_RGB 0
|
||||
#define LCDC_RGBC_EVEN_RBG 1
|
||||
#define LCDC_RGBC_EVEN_GRB 2
|
||||
#define LCDC_RGBC_EVEN_GBR 3
|
||||
#define LCDC_RGBC_EVEN_BRG 4
|
||||
#define LCDC_RGBC_EVEN_BGR 5
|
||||
/* Vertical Synchronize Register */
|
||||
#define LCDC_VSYNC_VPS_BIT 16
|
||||
#define LCDC_VSYNC_VPS_MASK (0xfff << LCDC_VSYNC_VPS_BIT)
|
||||
#define LCDC_VSYNC_VPE_BIT 0
|
||||
#define LCDC_VSYNC_VPE_MASK (0xfff << LCDC_VSYNC_VPE_BIT)
|
||||
/* Horizontal Synchronize Register */
|
||||
#define LCDC_HSYNC_HPS_BIT 16
|
||||
#define LCDC_HSYNC_HPS_MASK (0xfff << LCDC_HSYNC_HPS_BIT)
|
||||
#define LCDC_HSYNC_HPE_BIT 0
|
||||
#define LCDC_HSYNC_HPE_MASK (0xfff << LCDC_HSYNC_HPE_BIT)
|
||||
/* Virtual Area Setting Register */
|
||||
#define LCDC_VAT_HT_BIT 16
|
||||
#define LCDC_VAT_HT_MASK (0xfff << LCDC_VAT_HT_BIT)
|
||||
#define LCDC_VAT_VT_BIT 0
|
||||
#define LCDC_VAT_VT_MASK (0xfff << LCDC_VAT_VT_BIT)
|
||||
/* Display Area Horizontal Start/End Point Register */
|
||||
#define LCDC_DAH_HDS_BIT 16
|
||||
#define LCDC_DAH_HDS_MASK (0xfff << LCDC_DAH_HDS_BIT)
|
||||
#define LCDC_DAH_HDE_BIT 0
|
||||
#define LCDC_DAH_HDE_MASK (0xfff << LCDC_DAH_HDE_BIT)
|
||||
/* Display Area Vertical Start/End Point Register */
|
||||
#define LCDC_DAV_VDS_BIT 16
|
||||
#define LCDC_DAV_VDS_MASK (0xfff << LCDC_DAV_VDS_BIT)
|
||||
#define LCDC_DAV_VDE_BIT 0
|
||||
#define LCDC_DAV_VDE_MASK (0xfff << LCDC_DAV_VDE_BIT)
|
||||
/* Foreground 0 or Foreground 1 XY Position Register */
|
||||
#define LCDC_XYP_YPOS_BIT 16
|
||||
#define LCDC_XYP_YPOS_MASK (0xfff << LCDC_XYP_YPOS_BIT)
|
||||
#define LCDC_XYP_XPOS_BIT 0
|
||||
#define LCDC_XYP_XPOS_MASK (0xfff << LCDC_XYP_XPOS_BIT)
|
||||
/* Foreground 0 or Foreground 1 Size Register */
|
||||
#define LCDC_SIZE_HEIGHT_BIT 16
|
||||
#define LCDC_SIZE_HEIGHT_MASK (0xfff << LCDC_SIZE_HEIGHT_BIT)
|
||||
#define LCDC_SIZE_WIDTH_BIT 0
|
||||
#define LCDC_SIZE_WIDTH_MASK (0xfff << LCDC_SIZE_WIDTH_BIT)
|
||||
/* PS Signal Setting */
|
||||
#define LCDC_PS_PSS_BIT 16
|
||||
#define LCDC_PS_PSS_MASK (0xfff << LCDC_PS_PSS_BIT)
|
||||
#define LCDC_PS_PSE_BIT 0
|
||||
#define LCDC_PS_PSE_MASK (0xfff << LCDC_PS_PSE_BIT)
|
||||
/* CLS Signal Setting */
|
||||
#define LCDC_CLS_CLSS_BIT 16
|
||||
#define LCDC_CLS_CLSS_MASK (0xfff << LCDC_CLS_CLSS_BIT)
|
||||
#define LCDC_CLS_CLSE_BIT 0
|
||||
#define LCDC_CLS_CLSE_MASK (0xfff << LCDC_CLS_CLSE_BIT)
|
||||
/* SPL Signal Setting */
|
||||
#define LCDC_SPL_SPLS_BIT 16
|
||||
#define LCDC_SPL_SPLS_MASK (0xfff << LCDC_SPL_SPLS_BIT)
|
||||
#define LCDC_SPL_SPLE_BIT 0
|
||||
#define LCDC_SPL_SPLE_MASK (0xfff << LCDC_SPL_SPLE_BIT)
|
||||
/* REV Signal Setting */
|
||||
#define LCDC_REV_REVS_BIT 16
|
||||
#define LCDC_REV_REVS_MASK (0xfff << LCDC_REV_REVS_BIT)
|
||||
/* DMA Command 0 or 1 Register */
|
||||
#define LCDC_CMD_SOFINT (1 << 31)
|
||||
#define LCDC_CMD_EOFINT (1 << 30)
|
||||
#define LCDC_CMD_CMD (1 << 29)
|
||||
#define LCDC_CMD_PAL (1 << 28)
|
||||
#define LCDC_CMD_COMPEN (1 << 27)
|
||||
#define LCDC_CMD_FRM_EN (1 << 26)
|
||||
#define LCDC_CMD_FIELD_SEL (1 << 25)
|
||||
#define LCDC_CMD_16X16BLOCK (1 << 24)
|
||||
#define LCDC_CMD_LEN_BIT 0
|
||||
#define LCDC_CMD_LEN_MASK (0xffffff << LCDC_CMD_LEN_BIT)
|
||||
/* DMA Offsize Register 0,1 */
|
||||
#define LCDC_OFFS_BIT 0
|
||||
#define LCDC_OFFS_OFFSIZE_MASK (0xffffff << LCDC_OFFS_BIT)
|
||||
/* DMA Page Width Register 0,1 */
|
||||
#define LCDC_PW_BIT 0
|
||||
#define LCDC_PW_PAGEWIDTH_MASK (0xffffff << LCDC_PW_BIT)
|
||||
/* DMA Command Counter Register 0,1 */
|
||||
#define LCDC_CNUM_BIT 0
|
||||
#define LCDC_CNUM_CNUM_MASK (0xff << LCDC_CNUM_BIT)
|
||||
#define LCDC_CPOS_ALPHAMD1 (1 << 31)
|
||||
#define LCDC_CPOS_RGB_RGB565 (0 << 30)
|
||||
#define LCDC_CPOS_RGB_RGB555 (1 << 30)
|
||||
#define LCDC_CPOS_BPP_BIT 27
|
||||
#define LCDC_CPOS_BPP_MASK (0x07 << LCDC_CPOS_BPP_BIT)
|
||||
#define LCDC_CPOS_BPP_16 (4 << LCDC_CPOS_BPP_BIT)
|
||||
#define LCDC_CPOS_BPP_18_24 (5 << LCDC_CPOS_BPP_BIT)
|
||||
#define LCDC_CPOS_BPP_CMPS_24 (6 << LCDC_CPOS_BPP_BIT)
|
||||
#define LCDC_CPOS_BPP_30 (7 << LCDC_CPOS_BPP_BIT)
|
||||
#define LCDC_CPOS_PREMULTI (1 << 26)
|
||||
#define LCDC_CPOS_COEF_SLE_BIT 24
|
||||
#define LCDC_CPOS_COEF_SLE_MASK (0x3 << LCDC_CPOS_COEF_SLE_BIT)
|
||||
#define LCDC_CPOS_COEF_SLE_0 (0 << LCDC_CPOS_COEF_SLE_BIT)
|
||||
#define LCDC_CPOS_COEF_SLE_1 (1 << LCDC_CPOS_COEF_SLE_BIT)
|
||||
#define LCDC_CPOS_COEF_SLE_2 (2 << LCDC_CPOS_COEF_SLE_BIT)
|
||||
#define LCDC_CPOS_COEF_SLE_3 (3 << LCDC_CPOS_COEF_SLE_BIT)
|
||||
#define LCDC_CPOS_YPOS_BIT 12
|
||||
#define LCDC_CPOS_YPOS_MASK (0xfff << LCDC_CPOS_YPOS_BIT)
|
||||
#define LCDC_CPOS_XPOS_BIT 0
|
||||
#define LCDC_CPOS_XPOS_MASK (0xfff << LCDC_CPOS_XPOS_BIT)
|
||||
/* Foreground 0,1 Size Register */
|
||||
#define LCDC_DESSIZE_ALPHA_BIT 24
|
||||
#define LCDC_DESSIZE_ALPHA_MASK (0xff << LCDC_DESSIZE_ALPHA_BIT)
|
||||
#define LCDC_DESSIZE_HEIGHT_BIT 12
|
||||
#define LCDC_DESSIZE_HEIGHT_MASK (0xfff << LCDC_DESSIZE_HEIGHT_BIT)
|
||||
#define LCDC_DESSIZE_WIDTH_BIT 0
|
||||
#define LCDC_DESSIZE_WIDTH_MASK (0xfff << LCDC_DESSIZE_WIDTH_BIT)
|
||||
/* Priority level threshold configure Register */
|
||||
#define LCDC_PCFG_LCDC_PRI_MD (1 << 31)
|
||||
#define LCDC_PCFG_HP_BST_BIT 28
|
||||
#define LCDC_PCFG_HP_BST_MASK (0x7 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_HP_BST_4 (0 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_HP_BST_8 (1 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_HP_BST_16 (2 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_HP_BST_32 (3 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_HP_BST_C16 (5 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_HP_BST_64 (4 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_HP_BST_DIS (7 << LCDC_PCFG_HP_BST_BIT)
|
||||
#define LCDC_PCFG_PCFG2_BIT 18
|
||||
#define LCDC_PCFG_PCFG2_MASK (0x1ff << LCDC_PCFG_PCFG2_BIT)
|
||||
#define LCDC_PCFG_PCFG1_BIT 9
|
||||
#define LCDC_PCFG_PCFG1_MASK (0x1ff << LCDC_PCFG_PCFG1_BIT)
|
||||
#define LCDC_PCFG_PCFG0_BIT 0
|
||||
#define LCDC_PCFG_PCFG0_MASK (0x1ff << LCDC_PCFG_PCFG0_BIT)
|
||||
/* Dual LCDC Channel Control register */
|
||||
#define LCDC_DUAL_CTRL_IPU_WR_SEL (1 << 8)
|
||||
#define LCDC_DUAL_CTRL_TFT_SEL (1 << 6)
|
||||
#define LCDC_DUAL_CTRL_PRI_IPU_EN (1 << 5)
|
||||
#define LCDC_DUAL_CTRL_PRI_IPU_BIT 3
|
||||
#define LCDC_DUAL_CTRL_PRI_IPU_MASK (0x3 << LCDC_DUAL_CTRL_PRI_IPU_BIT)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _X1000_SLCDC_H_ */
|
||||
@@ -1,11 +0,0 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -1,118 +0,0 @@
|
||||
/*
|
||||
* File : cache.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#include "../xburst/cache.h"
|
||||
|
||||
#include <board.h>
|
||||
|
||||
#define CACHE_SIZE 16*1024
|
||||
#define CACHE_LINE_SIZE 32
|
||||
#define KSEG0 0x80000000
|
||||
|
||||
#define K0_TO_K1() \
|
||||
do { \
|
||||
unsigned long __k0_addr; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
"la %0, 1f\n\t" \
|
||||
"or %0, %0, %1\n\t" \
|
||||
"jr %0\n\t" \
|
||||
"nop\n\t" \
|
||||
"1: nop\n" \
|
||||
: "=&r"(__k0_addr) \
|
||||
: "r" (0x20000000) ); \
|
||||
} while(0)
|
||||
|
||||
#define K1_TO_K0() \
|
||||
do { \
|
||||
unsigned long __k0_addr; \
|
||||
__asm__ __volatile__( \
|
||||
"nop;nop;nop;nop;nop;nop;nop\n\t" \
|
||||
"la %0, 1f\n\t" \
|
||||
"jr %0\n\t" \
|
||||
"nop\n\t" \
|
||||
"1: nop\n" \
|
||||
: "=&r" (__k0_addr)); \
|
||||
} while (0)
|
||||
|
||||
#define INVALIDATE_BTB() \
|
||||
do { \
|
||||
unsigned long tmp; \
|
||||
__asm__ __volatile__( \
|
||||
".set mips32\n\t" \
|
||||
"mfc0 %0, $16, 7\n\t" \
|
||||
"nop\n\t" \
|
||||
"ori %0, 2\n\t" \
|
||||
"mtc0 %0, $16, 7\n\t" \
|
||||
"nop\n\t" \
|
||||
".set mips2\n\t" \
|
||||
: "=&r" (tmp)); \
|
||||
} while (0)
|
||||
|
||||
#define SYNC_WB() __asm__ __volatile__ ("sync")
|
||||
|
||||
#define cache_op(op,addr) \
|
||||
__asm__ __volatile__( \
|
||||
" .set noreorder \n" \
|
||||
" .set mips32\n\t \n" \
|
||||
" cache %0, %1 \n" \
|
||||
" .set mips0 \n" \
|
||||
" .set reorder" \
|
||||
: \
|
||||
: "i" (op), "m" (*(unsigned char *)(addr)))
|
||||
|
||||
void __icache_invalidate_all(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
K0_TO_K1();
|
||||
|
||||
asm volatile (".set noreorder\n"
|
||||
".set mips32\n\t"
|
||||
"mtc0\t$0,$28\n\t"
|
||||
"mtc0\t$0,$29\n"
|
||||
".set mips0\n"
|
||||
".set reorder\n");
|
||||
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
|
||||
cache_op(Index_Store_Tag_I, i);
|
||||
|
||||
K1_TO_K0();
|
||||
|
||||
INVALIDATE_BTB();
|
||||
}
|
||||
|
||||
void __dcache_writeback_all(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
|
||||
cache_op(Index_Writeback_Inv_D, i);
|
||||
|
||||
SYNC_WB();
|
||||
}
|
||||
|
||||
void rt_hw_cache_init(void)
|
||||
{
|
||||
__dcache_writeback_all();
|
||||
__icache_invalidate_all();
|
||||
}
|
||||
|
||||
@@ -1,62 +0,0 @@
|
||||
/*
|
||||
* File : cache.h
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#ifndef __CACHE_H__
|
||||
#define __CACHE_H__
|
||||
|
||||
/*
|
||||
* Cache Operations
|
||||
*/
|
||||
#define Index_Invalidate_I 0x00
|
||||
#define Index_Writeback_Inv_D 0x01
|
||||
#define Index_Invalidate_SI 0x02
|
||||
#define Index_Writeback_Inv_SD 0x03
|
||||
#define Index_Load_Tag_I 0x04
|
||||
#define Index_Load_Tag_D 0x05
|
||||
#define Index_Load_Tag_SI 0x06
|
||||
#define Index_Load_Tag_SD 0x07
|
||||
#define Index_Store_Tag_I 0x08
|
||||
#define Index_Store_Tag_D 0x09
|
||||
#define Index_Store_Tag_SI 0x0A
|
||||
#define Index_Store_Tag_SD 0x0B
|
||||
#define Create_Dirty_Excl_D 0x0d
|
||||
#define Create_Dirty_Excl_SD 0x0f
|
||||
#define Hit_Invalidate_I 0x10
|
||||
#define Hit_Invalidate_D 0x11
|
||||
#define Hit_Invalidate_SI 0x12
|
||||
#define Hit_Invalidate_SD 0x13
|
||||
#define Fill 0x14
|
||||
#define Hit_Writeback_Inv_D 0x15
|
||||
/* 0x16 is unused */
|
||||
#define Hit_Writeback_Inv_SD 0x17
|
||||
#define Hit_Writeback_I 0x18
|
||||
#define Hit_Writeback_D 0x19
|
||||
/* 0x1a is unused */
|
||||
#define Hit_Writeback_SD 0x1b
|
||||
/* 0x1c is unused */
|
||||
/* 0x1e is unused */
|
||||
#define Hit_Set_Virtual_SI 0x1e
|
||||
#define Hit_Set_Virtual_SD 0x1f
|
||||
|
||||
void rt_hw_cache_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,51 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2019-07-19 Zhou Yanjie clean up code
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips_def.h"
|
||||
#include "../common/mipsregs.h"
|
||||
#include "../common/stackframe.h"
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
|
||||
.globl cache_init
|
||||
.ent cache_init
|
||||
cache_init:
|
||||
.set noreorder
|
||||
mtc0 zero, CP0_TAGLO
|
||||
move t0, a0 // cache total size
|
||||
move t1, a1 // cache line size
|
||||
li t2, 0x80000000
|
||||
addu t3, t0, t2
|
||||
|
||||
_cache_init_loop:
|
||||
cache 8, 0(t2) // icache_index_store_tag
|
||||
cache 9, 0(t2) // dcache_index_store_tag
|
||||
addu t2, t1
|
||||
bne t2, t3, _cache_init_loop
|
||||
nop
|
||||
|
||||
mfc0 t0, CP0_CONFIG
|
||||
li t1, 0x7
|
||||
not t1
|
||||
and t0, t0, t1
|
||||
or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
|
||||
mtc0 t0, CP0_CONFIG
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.set reorder
|
||||
.end cache_init
|
||||
@@ -1,155 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2010-09-11 bernard port to JZ4755
|
||||
* 2019-07-19 Zhou Yanjie clean up code
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips_def.h"
|
||||
#include "../common/stackframe.h"
|
||||
#include "stack.h"
|
||||
|
||||
.section ".text", "ax"
|
||||
.set noreorder
|
||||
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable()
|
||||
*/
|
||||
.globl rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
mfc0 v0, CP0_STATUS
|
||||
and v1, v0, 0xfffffffe
|
||||
mtc0 v1, CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t level)
|
||||
*/
|
||||
.globl rt_hw_interrupt_enable
|
||||
rt_hw_interrupt_enable:
|
||||
mtc0 a0, CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
|
||||
* a0 --> from
|
||||
* a1 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
mtc0 ra, CP0_EPC
|
||||
SAVE_ALL
|
||||
|
||||
sw sp, 0(a0) /* store sp in preempted tasks TCB */
|
||||
lw sp, 0(a1) /* get new task stack pointer */
|
||||
|
||||
RESTORE_ALL_AND_RET
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to)/*
|
||||
* a0 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
lw sp, 0(a0) /* get new task stack pointer */
|
||||
|
||||
RESTORE_ALL_AND_RET
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
|
||||
*/
|
||||
.globl rt_thread_switch_interrupt_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
la t0, rt_thread_switch_interrupt_flag
|
||||
lw t1, 0(t0)
|
||||
nop
|
||||
bnez t1, _reswitch
|
||||
nop
|
||||
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
|
||||
sw t1, 0(t0)
|
||||
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
|
||||
sw a0, 0(t0)
|
||||
_reswitch:
|
||||
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
|
||||
sw a1, 0(t0)
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl system_dump
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
|
||||
*/
|
||||
.globl rt_interrupt_enter
|
||||
.globl rt_interrupt_leave
|
||||
.globl mips_irq_handle
|
||||
mips_irq_handle:
|
||||
SAVE_ALL
|
||||
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t1, CP0_STATUS
|
||||
and t0, t1
|
||||
|
||||
andi t0, 0xff00
|
||||
beqz t0, spurious_interrupt
|
||||
nop
|
||||
|
||||
/* let k0 keep the current context sp */
|
||||
move k0, sp
|
||||
/* switch to kernel stack */
|
||||
li sp, SYSTEM_STACK
|
||||
|
||||
jal rt_interrupt_enter
|
||||
nop
|
||||
jal rt_interrupt_dispatch
|
||||
nop
|
||||
jal rt_interrupt_leave
|
||||
nop
|
||||
|
||||
/* switch sp back to thread's context */
|
||||
move sp, k0
|
||||
|
||||
/*
|
||||
* if rt_thread_switch_interrupt_flag set, jump to
|
||||
* rt_hw_context_switch_interrupt_do and don't return
|
||||
*/
|
||||
la k0, rt_thread_switch_interrupt_flag
|
||||
lw k1, 0(k0)
|
||||
beqz k1, spurious_interrupt
|
||||
nop
|
||||
sw zero, 0(k0) /* clear flag */
|
||||
nop
|
||||
|
||||
/*
|
||||
* switch to the new thread
|
||||
*/
|
||||
la k0, rt_interrupt_from_thread
|
||||
lw k1, 0(k0)
|
||||
nop
|
||||
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
|
||||
|
||||
la k0, rt_interrupt_to_thread
|
||||
lw k1, 0(k0)
|
||||
nop
|
||||
lw sp, 0(k1) /* get new task's stack pointer */
|
||||
j spurious_interrupt
|
||||
nop
|
||||
|
||||
spurious_interrupt:
|
||||
RESTORE_ALL_AND_RET
|
||||
|
||||
.set reorder
|
||||
@@ -1,75 +0,0 @@
|
||||
/*
|
||||
* File : cpu.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-07-09 Bernard first version
|
||||
* 2010-09-11 Bernard add CPU reset implementation
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* this function will reset CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_reset()
|
||||
{
|
||||
/* open the watch-dog */
|
||||
REG_WDT_TCSR = WDT_TCSR_EXT_EN;
|
||||
REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
|
||||
REG_WDT_TDR = 0x03;
|
||||
REG_WDT_TCNT = 0x00;
|
||||
REG_WDT_TCER |= WDT_TCER_TCEN;
|
||||
|
||||
rt_kprintf("reboot system...\n");
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* this function will shutdown CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function finds the first bit set (beginning with the least significant bit)
|
||||
* in value and return the index of that bit.
|
||||
*
|
||||
* Bits are numbered starting at 1 (the least significant bit). A return value of
|
||||
* zero from any of these functions means that the argument was zero.
|
||||
*
|
||||
* @return return the index of the first bit set. If value is 0, then this function
|
||||
* shall return 0.
|
||||
*/
|
||||
int __rt_ffs(int value)
|
||||
{
|
||||
return __builtin_ffs(value);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -1,81 +0,0 @@
|
||||
/*
|
||||
* File : exception.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include "../common/exception.h"
|
||||
#include "../common/mipsregs.h"
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* exception handle table
|
||||
*/
|
||||
exception_func_t sys_exception_handlers[33];
|
||||
|
||||
/**
|
||||
* setup the exception handle
|
||||
*/
|
||||
exception_func_t rt_set_except_vector(int n, exception_func_t func)
|
||||
{
|
||||
exception_func_t old_handler = sys_exception_handlers[n];
|
||||
|
||||
if ((n == 0) || (n > 32) || (!func))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
sys_exception_handlers[n] = func;
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
void tlb_refill_handler(void)
|
||||
{
|
||||
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
void cache_error_handler(void)
|
||||
{
|
||||
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
static void unhandled_exception_handle(pt_regs_t *regs)
|
||||
{
|
||||
rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
|
||||
}
|
||||
|
||||
void install_default_execpt_handle(void)
|
||||
{
|
||||
rt_int32_t i;
|
||||
|
||||
for (i=0; i<33; i++)
|
||||
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
@@ -1,249 +0,0 @@
|
||||
/*
|
||||
* File : interrupt.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* 2010-07-09 Bernard first version
|
||||
* 2013-03-29 aozima Modify the interrupt interface implementations.
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
|
||||
#define INTERRUPTS_MAX 64
|
||||
#else
|
||||
#define INTERRUPTS_MAX 32
|
||||
#endif
|
||||
|
||||
extern rt_uint32_t rt_interrupt_nest;
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
static struct rt_irq_desc isr_table[INTERRUPTS_MAX];
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
static void rt_hw_interrupt_handler(int vector, void *param)
|
||||
{
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
rt_int32_t idx;
|
||||
|
||||
rt_memset(isr_table, 0x00, sizeof(isr_table));
|
||||
for (idx = 0; idx < INTERRUPTS_MAX; idx ++)
|
||||
{
|
||||
isr_table[idx].handler = rt_hw_interrupt_handler;
|
||||
}
|
||||
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrupt_flag = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
/* mask interrupt */
|
||||
__intc_mask_irq(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
__intc_unmask_irq(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param handler the interrupt service routine to be installed
|
||||
* @param param the interrupt service function parameter
|
||||
* @param name the interrupt name
|
||||
* @return old handler
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if(vector < INTERRUPTS_MAX)
|
||||
{
|
||||
old_handler = isr_table[vector].handler;
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
isr_table[vector].handler = handler;
|
||||
isr_table[vector].param = param;
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
|
||||
/*
|
||||
* fls - find last bit set.
|
||||
* @word: The word to search
|
||||
*
|
||||
* This is defined the same way as ffs.
|
||||
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
|
||||
*/
|
||||
rt_inline int fls(int x)
|
||||
{
|
||||
__asm__("clz %0, %1" : "=r" (x) : "r" (x));
|
||||
|
||||
return 32 - x;
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <mipsregs.h>
|
||||
|
||||
void rt_interrupt_dispatch(void *ptreg)
|
||||
{
|
||||
int i;
|
||||
void *param;
|
||||
rt_isr_handler_t irq_func;
|
||||
|
||||
#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000)
|
||||
int irq = 0, group;
|
||||
rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0;
|
||||
|
||||
rt_uint32_t c0_status, c0_cause;
|
||||
rt_uint32_t pending_im;
|
||||
|
||||
/* check os timer */
|
||||
c0_status = read_c0_status();
|
||||
c0_cause = read_c0_cause();
|
||||
|
||||
pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM);
|
||||
|
||||
if (pending_im & CAUSEF_IP3)
|
||||
{
|
||||
extern void rt_hw_ost_handler(void);
|
||||
rt_hw_ost_handler();
|
||||
return;
|
||||
}
|
||||
|
||||
if (pending_im & CAUSEF_IP2)
|
||||
{
|
||||
intc_ipr0 = REG_INTC_IPR(0);
|
||||
intc_ipr1 = REG_INTC_IPR(1);
|
||||
|
||||
if (intc_ipr0)
|
||||
{
|
||||
irq = fls(intc_ipr0) - 1;
|
||||
intc_ipr0 &= ~(1<<irq);
|
||||
}
|
||||
else if(intc_ipr1)
|
||||
{
|
||||
irq = fls(intc_ipr1) - 1;
|
||||
intc_ipr1 &= ~(1<<irq);
|
||||
irq += 32;
|
||||
}
|
||||
#ifndef RT_USING_JZ_X1000 /* X1000 has no VPU */
|
||||
else
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"mfc0 %0, $13, 0 \n\t"
|
||||
"nop \n\t"
|
||||
:"=r"(vpu_pending)
|
||||
:);
|
||||
|
||||
if(vpu_pending & 0x800)
|
||||
irq = IRQ_VPU;
|
||||
else
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (irq >= INTERRUPTS_MAX)
|
||||
rt_kprintf("max interrupt, irq=%d\n", irq);
|
||||
|
||||
/* do interrupt */
|
||||
irq_func = isr_table[irq].handler;
|
||||
param = isr_table[irq].param;
|
||||
(*irq_func)(irq, param);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[i].counter++;
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
|
||||
/* ack interrupt */
|
||||
__intc_ack_irq(irq);
|
||||
}
|
||||
|
||||
if (pending_im & CAUSEF_IP0)
|
||||
rt_kprintf("CAUSEF_IP0\n");
|
||||
if (pending_im & CAUSEF_IP1)
|
||||
rt_kprintf("CAUSEF_IP1\n");
|
||||
if (pending_im & CAUSEF_IP4)
|
||||
rt_kprintf("CAUSEF_IP4\n");
|
||||
if (pending_im & CAUSEF_IP5)
|
||||
rt_kprintf("CAUSEF_IP5\n");
|
||||
if (pending_im & CAUSEF_IP6)
|
||||
rt_kprintf("CAUSEF_IP6\n");
|
||||
if (pending_im & CAUSEF_IP7)
|
||||
rt_kprintf("CAUSEF_IP7\n");
|
||||
#else
|
||||
static rt_uint32_t pending = 0;
|
||||
|
||||
/* the hardware interrupt */
|
||||
pending |= REG_INTC_IPR;
|
||||
if (!pending) return;
|
||||
|
||||
for (i = INTERRUPTS_MAX; i > 0; --i)
|
||||
{
|
||||
if ((pending & (1<<i)))
|
||||
{
|
||||
pending &= ~(1<<i);
|
||||
|
||||
/* do interrupt */
|
||||
irq_func = isr_table[i].handler;
|
||||
param = isr_table[i].param;
|
||||
(*irq_func)(i, param);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[i].counter++;
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
|
||||
/* ack interrupt */
|
||||
__intc_ack_irq(i);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -1,358 +0,0 @@
|
||||
/*
|
||||
* File : mipscfg.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-27 swkyer first version
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include "../common/mipsregs.h"
|
||||
#include "../common/mipscfg.h"
|
||||
|
||||
mips32_core_cfg_t g_mips_core =
|
||||
{
|
||||
16, /* icache_line_size */
|
||||
256, /* icache_lines_per_way */
|
||||
4, /* icache_ways */
|
||||
16, /* dcache_line_size */
|
||||
256, /* dcache_lines_per_way */
|
||||
4, /* dcache_ways */
|
||||
16, /* max_tlb_entries */
|
||||
};
|
||||
|
||||
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
|
||||
{
|
||||
rt_uint16_t rets = 1;
|
||||
|
||||
while (n--)
|
||||
rets *= b;
|
||||
|
||||
return rets;
|
||||
}
|
||||
|
||||
/**
|
||||
* read core attribute
|
||||
*/
|
||||
void mips32_cfg_init(void)
|
||||
{
|
||||
rt_uint16_t val;
|
||||
rt_uint32_t cp0_config1;
|
||||
|
||||
cp0_config1 = read_c0_config();
|
||||
if (cp0_config1 & 0x80000000)
|
||||
{
|
||||
cp0_config1 = read_c0_config1();
|
||||
|
||||
val = (cp0_config1 & (7<<22))>>22;
|
||||
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<19))>>19;
|
||||
g_mips_core.icache_line_size = 2 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<16))>>16;
|
||||
g_mips_core.icache_ways = val + 1;
|
||||
|
||||
val = (cp0_config1 & (7<<13))>>13;
|
||||
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<10))>>10;
|
||||
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
|
||||
val = (cp0_config1 & (7<<7))>>7;
|
||||
g_mips_core.dcache_ways = val + 1;
|
||||
|
||||
val = (cp0_config1 & (0x3F<<25))>>25;
|
||||
g_mips_core.max_tlb_entries = val + 1;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
static void CP0_status_analyze(unsigned long value)
|
||||
{
|
||||
if(value & (1<<26))
|
||||
rt_kprintf(" FR");
|
||||
if(value & (1<<23))
|
||||
rt_kprintf(" PX");
|
||||
if(value & (1<<22))
|
||||
rt_kprintf(" BEV");
|
||||
if(value & (1<<20))
|
||||
rt_kprintf(" SR");
|
||||
if(value & (1<<19))
|
||||
rt_kprintf(" NMI");
|
||||
if(value & (1<<20))
|
||||
rt_kprintf(" SR");
|
||||
if(value & (0xFF<<8))
|
||||
rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF);
|
||||
if(value & (1<<7))
|
||||
rt_kprintf(" KX");
|
||||
if(value & (1<<6))
|
||||
rt_kprintf(" SX");
|
||||
if(value & (1<<5))
|
||||
rt_kprintf(" UX");
|
||||
if(value & (0x03<<3))
|
||||
rt_kprintf(" KSU:0x%02X", (value >> 3) & 0x03);
|
||||
if(value & (1<<2))
|
||||
rt_kprintf(" ERL");
|
||||
if(value & (1<<1))
|
||||
rt_kprintf(" EXL");
|
||||
if(value & (1<<0))
|
||||
rt_kprintf(" IE");
|
||||
}
|
||||
|
||||
static void CP0_config0_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
|
||||
/* [15] BE */
|
||||
if(value & (1<<15))
|
||||
rt_kprintf(" big-endian");
|
||||
else
|
||||
rt_kprintf(" little-endian");
|
||||
|
||||
/* [14:13] AT */
|
||||
{
|
||||
int AT = (value >> 13) & 0x03;
|
||||
|
||||
if(AT == 0)
|
||||
{
|
||||
rt_kprintf(" MIPS32");
|
||||
}
|
||||
else if(AT == 1)
|
||||
{
|
||||
rt_kprintf(" MIPS64/A32");
|
||||
}
|
||||
else if(AT == 2)
|
||||
{
|
||||
rt_kprintf(" MIPS64/A64");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf(" unkown");
|
||||
}
|
||||
}
|
||||
|
||||
/* [12:10] AR */
|
||||
{
|
||||
int AR = (value >> 10) & 0x07;
|
||||
|
||||
if(AR == 0)
|
||||
{
|
||||
rt_kprintf(" R1");
|
||||
}
|
||||
else if(AR == 1)
|
||||
{
|
||||
rt_kprintf(" R2");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf(" reserve");
|
||||
}
|
||||
}
|
||||
|
||||
/* [3] VI */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" VI");
|
||||
|
||||
/* [2:0] K0 */
|
||||
{
|
||||
int K0 = value & 0x07;
|
||||
|
||||
if(K0 == 2)
|
||||
{
|
||||
rt_kprintf(" uncached");
|
||||
}
|
||||
else if(K0 == 3)
|
||||
{
|
||||
rt_kprintf(" cacheable");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf(" K0:reserve");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CP0_config1_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
|
||||
/* [30:25] MMU size */
|
||||
{
|
||||
int MMU_size = (value >> 25) & 0x3F;
|
||||
rt_kprintf(" TLB:%d", MMU_size + 1);
|
||||
}
|
||||
|
||||
/* [24:22] IS, [21:19] IL, [18:16] IA */
|
||||
{
|
||||
int IS = (value >> 22) & 0x07;
|
||||
int IL = (value >> 19) & 0x07;
|
||||
int IA = (value >> 16) & 0x07;
|
||||
|
||||
IA = IA + 1;
|
||||
IS = 64 << IS;
|
||||
IL = 2 << IL;
|
||||
rt_kprintf(" Icache-%dKB:%dway*%dset*%dbyte",
|
||||
(IA*IS*IL) >> 10, IA, IS, IL);
|
||||
}
|
||||
|
||||
/* [15:13] DS, [12:10] DL, [9:7] DA */
|
||||
{
|
||||
int DS = (value >> 13) & 0x07;
|
||||
int DL = (value >> 10) & 0x07;
|
||||
int DA = (value >> 7) & 0x07;
|
||||
|
||||
DA = DA + 1;
|
||||
DS = 64 << DS;
|
||||
DL = 2 << DL;
|
||||
rt_kprintf(" Dcache-%dKB:%dway*%dset*%dbyte",
|
||||
(DA*DS*DL) >> 10, DA, DS, DL);
|
||||
}
|
||||
|
||||
/* [6] C2 */
|
||||
if(value & (1UL<<6))
|
||||
rt_kprintf(" CP2");
|
||||
|
||||
/* [5] MD */
|
||||
if(value & (1UL<<5))
|
||||
rt_kprintf(" MDMX-ASE");
|
||||
|
||||
/* [4] PC */
|
||||
if(value & (1UL<<4))
|
||||
rt_kprintf(" performa-count");
|
||||
|
||||
/* [3] WR */
|
||||
if(value & (1UL<<3))
|
||||
rt_kprintf(" Watch");
|
||||
|
||||
/* [2] CA */
|
||||
if(value & (1UL<<2))
|
||||
rt_kprintf(" MIPS16e");
|
||||
|
||||
/* [1] EP */
|
||||
if(value & (1UL<<1))
|
||||
rt_kprintf(" EJTAG");
|
||||
|
||||
/* [0] FP */
|
||||
if(value & (1UL<<0))
|
||||
rt_kprintf(" FPU");
|
||||
}
|
||||
|
||||
static void CP0_config2_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
}
|
||||
|
||||
static void CP0_config3_analyze(unsigned long value)
|
||||
{
|
||||
/* [31] M */
|
||||
if(value & (1UL<<31))
|
||||
rt_kprintf(" M");
|
||||
}
|
||||
|
||||
static void list_mips(void)
|
||||
{
|
||||
unsigned long value;
|
||||
unsigned long num = 0;
|
||||
|
||||
rt_kprintf("MIPS coprocessor register:\r\n");
|
||||
|
||||
rt_kprintf("( 0,0) INDEX : 0x%08X\r\n", read_c0_index());
|
||||
rt_kprintf("( 1,0) RANDOM : 0x%08X\r\n", read_c0_random());
|
||||
rt_kprintf("( 2,0) ENTRYLO0 : 0x%08X\r\n", read_c0_entrylo0());
|
||||
rt_kprintf("( 3,0) ENTRYLO1 : 0x%08X\r\n", read_c0_entrylo1());
|
||||
rt_kprintf("( 4,0) CONTEXT : 0x%08X\r\n", read_c0_context());
|
||||
rt_kprintf("( 5,0) PAGEMASK : 0x%08X\r\n", read_c0_pagemask());
|
||||
rt_kprintf("( 6,0) WIRED : 0x%08X\r\n", read_c0_wired());
|
||||
rt_kprintf("( 7,0) INFO : 0x%08X\r\n", read_c0_info());
|
||||
rt_kprintf("( 8,0) BADVADDR : 0x%08X\r\n", read_c0_badvaddr());
|
||||
rt_kprintf("( 9,0) COUNT : 0x%08X\r\n", read_c0_count());
|
||||
rt_kprintf("(10,0) ENTRYHI : 0x%08X\r\n", read_c0_entryhi());
|
||||
rt_kprintf("(11,0) COMPARE : 0x%08X\r\n", read_c0_compare());
|
||||
|
||||
value = read_c0_status();
|
||||
rt_kprintf("(12,0) STATUS : 0x%08X", value);
|
||||
CP0_status_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
/*
|
||||
rt_kprintf("(12,1) INTCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 1));
|
||||
rt_kprintf("(12,2) SRSCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 2));
|
||||
*/
|
||||
|
||||
rt_kprintf("(13,0) CAUSE : 0x%08X\r\n", read_c0_cause());
|
||||
rt_kprintf("(14,0) EPC : 0x%08X\r\n", read_c0_epc());
|
||||
rt_kprintf("(15,0) PRID : 0x%08X\r\n", read_c0_prid());
|
||||
rt_kprintf("(15,1) EBASE : 0x%08X\r\n", read_c0_ebase());
|
||||
|
||||
value = read_c0_config();
|
||||
rt_kprintf("(16,0) CONFIG : 0x%08X", value);
|
||||
CP0_config0_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
if(value & (1UL << 31))
|
||||
{
|
||||
value = read_c0_config1();
|
||||
rt_kprintf("(16,1) CONFIG1 : 0x%08X", value);
|
||||
CP0_config1_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
if(value & (1UL << 31))
|
||||
{
|
||||
value = read_c0_config2();
|
||||
rt_kprintf("(16,2) CONFIG2 : 0x%08X\r\n", value);
|
||||
CP0_config2_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
if(value & (1UL << 31))
|
||||
{
|
||||
value = read_c0_config3();
|
||||
rt_kprintf("(16,3) CONFIG3 : 0x%08X\r\n", value);
|
||||
CP0_config3_analyze(value);
|
||||
rt_kprintf("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rt_kprintf("(17,0) LLADDR : 0x%08X\r\n", __read_32bit_c0_register($17, 0));
|
||||
rt_kprintf("(18,0) WATCHLO : 0x%08X\r\n", __read_32bit_c0_register($18, 0));
|
||||
rt_kprintf("(19,0) WATCHHI : 0x%08X\r\n", __read_32bit_c0_register($19, 0));
|
||||
rt_kprintf("(20,0) XCONTEXT : 0x%08X\r\n", __read_32bit_c0_register($20, 0));
|
||||
rt_kprintf("(21,0) FRAMEMASK : 0x%08X\r\n", __read_32bit_c0_register($21, 0));
|
||||
rt_kprintf("(22,0) DIAGNOSTIC: 0x%08X\r\n", __read_32bit_c0_register($22, 0));
|
||||
rt_kprintf("(23,0) DEBUG : 0x%08X\r\n", __read_32bit_c0_register($23, 0));
|
||||
rt_kprintf("(24,0) DEPC : 0x%08X\r\n", __read_32bit_c0_register($24, 0));
|
||||
|
||||
rt_kprintf("(25,0) PERFCTL0 : 0x%08X\r\n", __read_32bit_c0_register($25, 0));
|
||||
rt_kprintf("(26,0) ECC : 0x%08X\r\n", __read_32bit_c0_register($26, 0));
|
||||
rt_kprintf("(27,0) CACHEERR : 0x%08X\r\n", __read_32bit_c0_register($27, 0));
|
||||
rt_kprintf("(28,0) TAGLO : 0x%08X\r\n", __read_32bit_c0_register($28, 0));
|
||||
rt_kprintf("(29,0) TAGHI : 0x%08X\r\n", __read_32bit_c0_register($29, 0));
|
||||
|
||||
/*
|
||||
rt_kprintf("(30,0) ERROREPC : 0x%08X\r\n", __read_32bit_c0_register($30, 0));
|
||||
rt_kprintf("(31,0) DESAVE : 0x%08X\r\n", __read_32bit_c0_register($31, 0));
|
||||
*/
|
||||
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
}
|
||||
FINSH_FUNCTION_EXPORT(list_mips, list CPU info)
|
||||
#endif /* RT_USING_FINSH */
|
||||
|
||||
@@ -1,103 +0,0 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2010-07-07 Bernard porting to Ingenic CPU
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @addtogroup Ingenic
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
extern rt_uint32_t cp0_get_cause(void);
|
||||
extern rt_uint32_t cp0_get_status(void);
|
||||
extern rt_uint32_t cp0_get_hi(void);
|
||||
extern rt_uint32_t cp0_get_lo(void);
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk;
|
||||
static rt_uint32_t g_sr = 0;
|
||||
|
||||
if (g_sr == 0)
|
||||
{
|
||||
g_sr = cp0_get_status();
|
||||
g_sr &= 0xfffffffe;
|
||||
g_sr |= 0x0403;
|
||||
}
|
||||
|
||||
/** Start at stack top */
|
||||
stk = (rt_uint32_t *)stack_addr;
|
||||
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
|
||||
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
|
||||
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
|
||||
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
|
||||
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
|
||||
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
|
||||
*(--stk) = (rt_uint32_t) texit; /* ra */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
|
||||
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
|
||||
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
|
||||
*(--stk) = (rt_uint32_t) parameter; /* a0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
|
||||
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
|
||||
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -1,28 +0,0 @@
|
||||
/*
|
||||
* File : stack.h
|
||||
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#ifndef __STACK_H__
|
||||
#define __STACK_H__
|
||||
|
||||
#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
|
||||
|
||||
#endif
|
||||
@@ -1,158 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2010-09-04 bernard porting to JZ47xx
|
||||
* 2019-07-19 Zhou Yanjie clean up code
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include "../common/mips_def.h"
|
||||
#include "../common/stackframe.h"
|
||||
#include "stack.h"
|
||||
|
||||
.section ".start", "ax"
|
||||
.set noreorder
|
||||
|
||||
/* the program entry */
|
||||
.globl _start
|
||||
_start:
|
||||
.set noreorder
|
||||
la ra, _start
|
||||
|
||||
li t1, 0x00800000
|
||||
mtc0 t1, CP0_CAUSE
|
||||
|
||||
/* init cp0 registers. */
|
||||
li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
/* setup stack pointer */
|
||||
li sp, SYSTEM_STACK
|
||||
la gp, _gp
|
||||
|
||||
/* init caches, assumes a 4way * 128set * 32byte I/D cache */
|
||||
mtc0 zero, CP0_TAGLO /* TAGLO reg */
|
||||
mtc0 zero, CP0_TAGHI /* TAGHI reg */
|
||||
li t0, 3 /* enable cache for kseg0 accesses */
|
||||
mtc0 t0, CP0_CONFIG /* CONFIG reg */
|
||||
la t0, 0x80000000 /* an idx op should use an unmappable address */
|
||||
ori t1, t0, 0x4000 /* 16kB cache */
|
||||
|
||||
_cache_loop:
|
||||
cache 0x8, 0(t0) /* index store icache tag */
|
||||
cache 0x9, 0(t0) /* index store dcache tag */
|
||||
bne t0, t1, _cache_loop
|
||||
addiu t0, t0, 0x20 /* 32 bytes per cache line */
|
||||
nop
|
||||
|
||||
/* invalidate BTB */
|
||||
mfc0 t0, CP0_CONFIG
|
||||
nop
|
||||
ori t0, 2
|
||||
mtc0 t0, CP0_CONFIG
|
||||
nop
|
||||
|
||||
/* copy IRAM section */
|
||||
la t0, _iramcopy
|
||||
la t1, _iramstart
|
||||
la t2, _iramend
|
||||
_iram_loop:
|
||||
lw t3, 0(t0)
|
||||
sw t3, 0(t1)
|
||||
addiu t1, 4
|
||||
bne t1, t2, _iram_loop
|
||||
addiu t0, 4
|
||||
/* clear bss */
|
||||
la t0, __bss_start
|
||||
la t1, __bss_end
|
||||
_clr_bss_loop:
|
||||
sw zero, 0(t0)
|
||||
bne t0, t1, _clr_bss_loop
|
||||
addiu t0, t0, 4
|
||||
|
||||
/* jump to RT-Thread RTOS */
|
||||
jal rtthread_startup
|
||||
nop
|
||||
|
||||
/* restart, never die */
|
||||
j _start
|
||||
nop
|
||||
.set reorder
|
||||
|
||||
.globl cp0_get_cause
|
||||
cp0_get_cause:
|
||||
mfc0 v0, CP0_CAUSE
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl cp0_get_status
|
||||
cp0_get_status:
|
||||
mfc0 v0, CP0_STATUS
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl cp0_get_hi
|
||||
cp0_get_hi:
|
||||
mfhi v0
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.globl cp0_get_lo
|
||||
cp0_get_lo:
|
||||
mflo v0
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.extern tlb_refill_handler
|
||||
.extern cache_error_handler
|
||||
|
||||
/* Exception Handler */
|
||||
/* 0x0 - TLB refill handler */
|
||||
.section .vectors.1, "ax", %progbits
|
||||
j tlb_refill_handler
|
||||
nop
|
||||
|
||||
/* 0x100 - Cache error handler */
|
||||
.section .vectors.2, "ax", %progbits
|
||||
j cache_error_handler
|
||||
nop
|
||||
|
||||
/* 0x180 - Exception/Interrupt handler */
|
||||
.section .vectors.3, "ax", %progbits
|
||||
j _general_exception_handler
|
||||
nop
|
||||
|
||||
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
|
||||
.section .vectors.4, "ax", %progbits
|
||||
j _irq_handler
|
||||
nop
|
||||
|
||||
.section .vectors, "ax", %progbits
|
||||
.extern mips_irq_handle
|
||||
|
||||
/* general exception handler */
|
||||
_general_exception_handler:
|
||||
.set noreorder
|
||||
mfc0 k1, CP0_CAUSE
|
||||
andi k1, k1, 0x7c
|
||||
srl k1, k1, 2
|
||||
lw k0, sys_exception_handlers(k1)
|
||||
jr k0
|
||||
nop
|
||||
.set reorder
|
||||
|
||||
/* interrupt handler */
|
||||
_irq_handler:
|
||||
.set noreorder
|
||||
la k0, mips_irq_handle
|
||||
jr k0
|
||||
nop
|
||||
.set reorder
|
||||
@@ -1,329 +0,0 @@
|
||||
/*
|
||||
* File : x1000.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2015-11-19 Urey the first version
|
||||
*/
|
||||
|
||||
#ifndef X1000_H__
|
||||
#define X1000_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
// typedef unsigned int size_t;
|
||||
#define u64 unsigned long long
|
||||
#define u32 unsigned int
|
||||
#define u16 unsigned short
|
||||
#define u8 unsigned char
|
||||
|
||||
#define U64 unsigned long long
|
||||
#define U32 unsigned int
|
||||
#define U16 unsigned short
|
||||
#define U8 unsigned char
|
||||
|
||||
#define S64 signed long long
|
||||
#define S32 int
|
||||
#define S16 short int
|
||||
#define S8 signed char
|
||||
|
||||
#define cache_unroll(base,op) \
|
||||
__asm__ __volatile__(" \
|
||||
.set noreorder; \
|
||||
.set mips3; \
|
||||
cache %1, (%0); \
|
||||
.set mips0; \
|
||||
.set reorder" \
|
||||
: \
|
||||
: "r" (base), \
|
||||
"i" (op));
|
||||
|
||||
/* cpu pipeline flush */
|
||||
static inline void jz_sync(void)
|
||||
{
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
static inline void writeb(u8 value, u32 address)
|
||||
{
|
||||
*((volatile u8 *) address) = value;
|
||||
}
|
||||
static inline void writew( u16 value, u32 address)
|
||||
{
|
||||
*((volatile u16 *) address) = value;
|
||||
}
|
||||
static inline void writel(u32 value, u32 address)
|
||||
{
|
||||
*((volatile u32 *) address) = value;
|
||||
}
|
||||
|
||||
static inline u8 readb(u32 address)
|
||||
{
|
||||
return *((volatile u8 *)address);
|
||||
}
|
||||
|
||||
static inline u16 readw(u32 address)
|
||||
{
|
||||
return *((volatile u16 *)address);
|
||||
}
|
||||
|
||||
static inline u32 readl(u32 address)
|
||||
{
|
||||
return *((volatile u32 *)address);
|
||||
}
|
||||
|
||||
static inline void jz_writeb(u32 address, u8 value)
|
||||
{
|
||||
*((volatile u8 *)address) = value;
|
||||
}
|
||||
|
||||
static inline void jz_writew(u32 address, u16 value)
|
||||
{
|
||||
*((volatile u16 *)address) = value;
|
||||
}
|
||||
|
||||
static inline void jz_writel(u32 address, u32 value)
|
||||
{
|
||||
*((volatile u32 *)address) = value;
|
||||
}
|
||||
|
||||
static inline u8 jz_readb(u32 address)
|
||||
{
|
||||
return *((volatile u8 *)address);
|
||||
}
|
||||
|
||||
static inline u16 jz_readw(u32 address)
|
||||
{
|
||||
return *((volatile u16 *)address);
|
||||
}
|
||||
|
||||
static inline u32 jz_readl(u32 address)
|
||||
{
|
||||
return *((volatile u32 *)address);
|
||||
}
|
||||
|
||||
#define REG8(addr) *((volatile u8 *)(addr))
|
||||
#define REG16(addr) *((volatile u16 *)(addr))
|
||||
#define REG32(addr) *((volatile u32 *)(addr))
|
||||
|
||||
#define BIT(n) (0x01u << (n))
|
||||
|
||||
#else
|
||||
|
||||
#define REG8(addr) (addr)
|
||||
#define REG16(addr) (addr)
|
||||
#define REG32(addr) (addr)
|
||||
|
||||
#endif /* !ASSEMBLY */
|
||||
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Register Definitions
|
||||
//
|
||||
/* AHB0 BUS Devices Base */
|
||||
#define HARB0_BASE 0xB3000000
|
||||
#define EMC_BASE 0xB3010000
|
||||
#define DDRC_BASE 0xB3020000
|
||||
#define MDMAC_BASE 0xB3030000
|
||||
#define LCD_BASE 0xB3050000
|
||||
#define TVE_BASE 0xB3050000
|
||||
#define SLCD_BASE 0xB3050000
|
||||
#define CIM_BASE 0xB3060000
|
||||
#define IPU_BASE 0xB3080000
|
||||
/* AHB1 BUS Devices Base */
|
||||
#define HARB1_BASE 0xB3200000
|
||||
#define DMAGP0_BASE 0xB3210000
|
||||
#define DMAGP1_BASE 0xB3220000
|
||||
#define DMAGP2_BASE 0xB3230000
|
||||
#define MC_BASE 0xB3250000
|
||||
#define ME_BASE 0xB3260000
|
||||
#define DEBLK_BASE 0xB3270000
|
||||
#define IDCT_BASE 0xB3280000
|
||||
#define CABAC_BASE 0xB3290000
|
||||
#define TCSM0_BASE 0xB32B0000
|
||||
#define TCSM1_BASE 0xB32C0000
|
||||
#define SRAM_BASE 0xB32D0000
|
||||
/* AHB2 BUS Devices Base */
|
||||
#define HARB2_BASE 0xB3400000
|
||||
#define NEMC_BASE 0xB3410000
|
||||
#define DMAC_BASE 0xB3420000
|
||||
#define UHC_BASE 0xB3430000
|
||||
#define UDC_BASE 0xB3440000
|
||||
#define GPS_BASE 0xB3480000
|
||||
#define ETHC_BASE 0xB34B0000
|
||||
#define BCH_BASE 0xB34D0000
|
||||
#define MSC0_BASE 0xB3450000
|
||||
#define MSC1_BASE 0xB3460000
|
||||
#define MSC2_BASE 0xB3470000
|
||||
|
||||
/* APB BUS Devices Base */
|
||||
#define CPM_BASE 0xB0000000
|
||||
#define INTC_BASE 0xB0001000
|
||||
#define TCU_BASE 0xB0002000
|
||||
#define WDT_BASE 0xB0002000
|
||||
#define OST_BASE 0xB2000000 /* OS Timer */
|
||||
#define RTC_BASE 0xB0003000
|
||||
#define GPIO_BASE 0xB0010000
|
||||
#define AIC_BASE 0xB0020000
|
||||
#define DMIC_BASE 0xB0021000
|
||||
#define ICDC_BASE 0xB0020000
|
||||
#define UART0_BASE 0xB0030000
|
||||
#define UART1_BASE 0xB0031000
|
||||
#define UART2_BASE 0xB0032000
|
||||
#define UART3_BASE 0xB0033000
|
||||
#define SCC_BASE 0xB0040000
|
||||
#define SSI0_BASE 0xB0043000
|
||||
#define SSI1_BASE 0xB0044000
|
||||
#define SSI2_BASE 0xB0045000
|
||||
#define I2C0_BASE 0xB0050000
|
||||
#define I2C1_BASE 0xB0051000
|
||||
#define PS2_BASE 0xB0060000
|
||||
#define SADC_BASE 0xB0070000
|
||||
#define OWI_BASE 0xB0072000
|
||||
#define TSSI_BASE 0xB0073000
|
||||
|
||||
/* NAND CHIP Base Address*/
|
||||
#define NEMC_CS1_IOBASE 0Xbb000000
|
||||
#define NEMC_CS2_IOBASE 0Xba000000
|
||||
#define NEMC_CS3_IOBASE 0Xb9000000
|
||||
#define NEMC_CS4_IOBASE 0Xb8000000
|
||||
#define NEMC_CS5_IOBASE 0Xb7000000
|
||||
#define NEMC_CS6_IOBASE 0Xb6000000
|
||||
|
||||
/*********************************************************************************************************
|
||||
** WDT
|
||||
*********************************************************************************************************/
|
||||
#define WDT_TDR (WDT_BASE + 0x00)
|
||||
#define WDT_TCER (WDT_BASE + 0x04)
|
||||
#define WDT_TCNT (WDT_BASE + 0x08)
|
||||
#define WDT_TCSR (WDT_BASE + 0x0C)
|
||||
|
||||
#define REG_WDT_TDR REG16(WDT_TDR)
|
||||
#define REG_WDT_TCER REG8(WDT_TCER)
|
||||
#define REG_WDT_TCNT REG16(WDT_TCNT)
|
||||
#define REG_WDT_TCSR REG16(WDT_TCSR)
|
||||
|
||||
#define WDT_TSCR_WDTSC (1 << 16)
|
||||
|
||||
#define WDT_TCSR_PRESCALE_1 (0 << 3)
|
||||
#define WDT_TCSR_PRESCALE_4 (1 << 3)
|
||||
#define WDT_TCSR_PRESCALE_16 (2 << 3)
|
||||
#define WDT_TCSR_PRESCALE_64 (3 << 3)
|
||||
#define WDT_TCSR_PRESCALE_256 (4 << 3)
|
||||
#define WDT_TCSR_PRESCALE_1024 (5 << 3)
|
||||
|
||||
#define WDT_TCSR_EXT_EN (1 << 2)
|
||||
#define WDT_TCSR_RTC_EN (1 << 1)
|
||||
#define WDT_TCSR_PCK_EN (1 << 0)
|
||||
|
||||
#define WDT_TCER_TCEN (1 << 0)
|
||||
|
||||
/*********************************************************************************************************
|
||||
** ÖжÏÔ´
|
||||
*********************************************************************************************************/
|
||||
/* INTC (Interrupt Controller) */
|
||||
#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20)
|
||||
#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20)
|
||||
#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20)
|
||||
#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20)
|
||||
#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20)
|
||||
|
||||
#define REG_INTC_ISR(n) REG32(INTC_ISR((n)))
|
||||
#define REG_INTC_IMR(n) REG32(INTC_IMR((n)))
|
||||
#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n)))
|
||||
#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n)))
|
||||
#define REG_INTC_IPR(n) REG32(INTC_IPR((n)))
|
||||
|
||||
// interrupt controller interrupts
|
||||
#define IRQ_DMIC 0
|
||||
#define IRQ_AIC0 1
|
||||
#define IRQ_RESERVED2 2
|
||||
#define IRQ_RESERVED3 3
|
||||
#define IRQ_RESERVED4 4
|
||||
#define IRQ_RESERVED5 5
|
||||
#define IRQ_RESERVED6 6
|
||||
#define IRQ_SFC 7
|
||||
#define IRQ_SSI0 8
|
||||
#define IRQ_RESERVED9 9
|
||||
#define IRQ_PDMA 10
|
||||
#define IRQ_PDMAD 11
|
||||
#define IRQ_RESERVED12 12
|
||||
#define IRQ_RESERVED13 13
|
||||
#define IRQ_GPIO3 14
|
||||
#define IRQ_GPIO2 15
|
||||
#define IRQ_GPIO1 16
|
||||
#define IRQ_GPIO0 17
|
||||
#define IRQ_RESERVED18 18
|
||||
#define IRQ_RESERVED19 19
|
||||
#define IRQ_RESERVED20 20
|
||||
#define IRQ_OTG 21
|
||||
#define IRQ_RESERVED22 22
|
||||
#define IRQ_AES 23
|
||||
#define IRQ_RESERVED24 24
|
||||
#define IRQ_TCU2 25
|
||||
#define IRQ_TCU1 26
|
||||
#define IRQ_TCU0 27
|
||||
#define IRQ_RESERVED28 28
|
||||
#define IRQ_RESERVED29 29
|
||||
#define IRQ_CIM 30
|
||||
#define IRQ_LCD 31
|
||||
#define IRQ_RTC 32
|
||||
#define IRQ_RESERVED33 33
|
||||
#define IRQ_RESERVED34 34
|
||||
#define IRQ_RESERVED35 35
|
||||
#define IRQ_MSC1 36
|
||||
#define IRQ_MSC0 37
|
||||
#define IRQ_SCC 38
|
||||
#define IRQ_RESERVED39 39
|
||||
#define IRQ_PCM0 40
|
||||
#define IRQ_RESERVED41 41
|
||||
#define IRQ_RESERVED42 42
|
||||
#define IRQ_RESERVED43 43
|
||||
#define IRQ_HARB2 44
|
||||
#define IRQ_RESERVED45 45
|
||||
#define IRQ_HARB0 46
|
||||
#define IRQ_CPM 47
|
||||
#define IRQ_RESERVED48 48
|
||||
#define IRQ_UART2 49
|
||||
#define IRQ_UART1 50
|
||||
#define IRQ_UART0 51
|
||||
#define IRQ_DDR 52
|
||||
#define IRQ_RESERVED53 53
|
||||
#define IRQ_EFUSE 54
|
||||
#define IRQ_MAC 55
|
||||
#define IRQ_RESERVED56 56
|
||||
#define IRQ_RESERVED57 57
|
||||
#define IRQ_I2C2 58
|
||||
#define IRQ_I2C1 59
|
||||
#define IRQ_I2C0 60
|
||||
#define IRQ_PDMAM 61
|
||||
#define IRQ_JPEG 62
|
||||
#define IRQ_RESERVED63 63
|
||||
|
||||
#define IRQ_INTC_MAX 63
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
|
||||
#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
|
||||
#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _JZ_M150_H_ */
|
||||
Reference in New Issue
Block a user