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Merge pull request #181 from grissiom/rm48x50-next

Browse Source 
Rm48x50 next
This commit is contained in:
Bernard Xiong
2013-10-22 16:22:02 -07:00
parent ac5da68db7 377c6e6cc9
commit a3bf5e2d9b
38 changed files with 1381 additions and 6753 deletions
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bsp/rm48x50/HALCoGen/SConscript
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import copy
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('source/*.c')
src += Glob('source/*.S')
CPPPATH = [cwd + '/include/']
group = DefineGroup('HALCoGen', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/rm48x50/HALCoGen/source/dabort.asm
-98
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@@ -1,98 +0,0 @@
;-------------------------------------------------------------------------------
; dabort.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Run Memory Test
.ref custom_dabort
.def _dabort
.asmfunc
_dabort
stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack
ldr r12, esmsr3 ; ESM Group3 status register
ldr r0, [r12]
tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
bne ramErrorFound
tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
bne ramErrorFound
noRAMerror
tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
bne flashErrorFound
bl custom_dabort ; custom data abort handler required
; If this custom handler is written in assembly, all registers used in the routine
; and the link register must be saved on to the stack upon entry, and restored before
; return from the routine.
ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack
subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted
ramErrorFound
ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW
ldr r2, [r1]
tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
beq ramErrorReal
mov r2, #0x20
str r2, [r1, #0x10] ; clear RAM error status register
ldr r1, ram2ctrl
str r2, [r1, #0x10] ; clear RAM error status register
mov r2, #0x28
str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors
mov r2, #5
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
ldmfd r13!, {r0 - r12, lr}
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
; this is the case because the data abort was caused intentionally
; and we do not want to cause the same data abort again.
ramErrorReal
b ramErrorReal ; branch here forever as continuing operation is not recommended
flashErrorFound
ldr r1, flashbase
ldr r2, [r1, #0x6C] ; read FDIAGCTRL register
mov r2, r2, lsr #16
tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
beq flashErrorReal
mov r2, #1
mov r2, r2, lsl #8
str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag
mov r2, #0x80
str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error
mov r2, #5
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
ldmfd r13!, {r0 - r12, lr}
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
; this is the case because the data abort was caused intentionally
; and we do not want to cause the same data abort again.
flashErrorReal
b flashErrorReal ; branch here forever as continuing operation is not recommended
esmsr3 .word 0xFFFFF520
ramctrl .word 0xFFFFF800
ram2ctrl .word 0xFFFFF900
ram1errstat .word 0xFFFFF810
ram2errstat .word 0xFFFFF910
flashbase .word 0xFFF87000
.endasmfunc
bsp/rm48x50/HALCoGen/source/esm.c
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bsp/rm48x50/HALCoGen/source/notification.c
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/** @file notification.c
* @brief User Notification Definition File
* @date 29.May.2013
* @version 03.05.02
*
* This file defines empty notification routines to avoid
* linker errors, Driver expects user to define the notification.
* The user needs to either remove this file and use their custom
* notification function or place their code sequence in this file
* between the provided USER CODE BEGIN and USER CODE END.
*
*/
/* Include Files */
#include "esm.h"
#include "sys_selftest.h"
#include "gio.h"
#include "sci.h"
#include "rti.h"
#include "sys_dma.h"
/* USER CODE BEGIN (0) */
#include <stdint.h>
/* USER CODE END */
void esmGroup1Notification(uint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (1) */
/* USER CODE END */
}
/* USER CODE BEGIN (2) */
/* USER CODE END */
void esmGroup2Notification(uint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (3) */
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (5) */
/* USER CODE END */
}
/* USER CODE BEGIN (6) */
/* USER CODE END */
void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (7) */
/* USER CODE END */
}
/* USER CODE BEGIN (8) */
/* USER CODE END */
void rtiNotification(uint32 notification)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (9) */
sciSendByte(scilinREG, 'I');
/* USER CODE END */
}
/* USER CODE BEGIN (10) */
/* USER CODE END */
void gioNotification(gioPORT_t *port, sint32 bit)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
/* USER CODE BEGIN (20) */
/* USER CODE END */
void sciNotification(sciBASE_t *sci, uint32 flags)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (29) */
if (sci == scilinREG && flags == SCI_RX_INT)
{
}
/* USER CODE END */
}
/* USER CODE BEGIN (30) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* USER CODE BEGIN (47) */
/* USER CODE END */
/* USER CODE BEGIN (50) */
/* USER CODE END */
/* USER CODE BEGIN (53) */
/* USER CODE END */
void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (54) */
/* USER CODE END */
}
/* USER CODE BEGIN (55) */
/* USER CODE END */
/* USER CODE BEGIN (56) */
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/pinmux.c
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/** @file pinmux.c
* @brief PINMUX Driver Inmplmentation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* Include Files */
#include "pinmux.h"
#define PINMUX_SET(REG, BALLID, MUX) \
pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)
#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)
#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
#define PINMUX_ETHERNET_SELECT(interface) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
/* USER CODE BEGIN (0) */
/* USER CODE END */
void muxInit(void){
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Enable Pin Muxing */
kickerReg->KICKER0 = 0x83E70B13U;
kickerReg->KICKER1 = 0x95A4F1E0U;
/* USER CODE BEGIN (2) */
/* USER CODE END */
pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;
pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
pinMuxReg->PINMMR3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
pinMuxReg->PINMMR7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30;
pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;
pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
pinMuxReg->PINMMR16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
pinMuxReg->PINMMR19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;
pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8;
pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U;
pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U;
pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA;
PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
PINMUX_ALT_ADC_TRIGGER_SELECT(1);
PINMUX_ETHERNET_SELECT(RMII);
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* Disable Pin Muxing */
kickerReg->KICKER0 = 0x00000000U;
kickerReg->KICKER1 = 0x00000000U;
/* USER CODE BEGIN (4) */
/* USER CODE END */
}
/* USER CODE BEGIN (5) */
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/rti.c
-28
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@@ -764,31 +764,3 @@ void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
}
}
/* USER CODE BEGIN (82) */
/* USER CODE END */
/** @fn void rtiCompare3Interrupt(void)
* @brief RTI1 Compare 3 Interrupt Handler
*
* RTI1 Compare 3 interrupt handler
*
*/
void rtiCompare3Interrupt(void)
{
/* USER CODE BEGIN (83) */
/* USER CODE END */
rtiREG1->INTFLAG = 8U;
rtiNotification(rtiNOTIFICATION_COMPARE3);
/* USER CODE BEGIN (84) */
/* USER CODE END */
}
bsp/rm48x50/HALCoGen/source/sci.c
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bsp/rm48x50/HALCoGen/source/sys_core.asm
-660
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bsp/rm48x50/HALCoGen/source/sys_dma.c
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/** @file dma.c
* @brief DMA Driver Inmplmentation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_dma.h"
/** @fn void dmaEnable(void)
* @brief enables DMA module
*
* This function brings DMA out of reset
*/
void dmaEnable(void)
{
dmaREG->GCTRL = 0x00000001U; /* reset dma */
dmaREG->GCTRL |= 0x00010000U; /* enable dma */
dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */
}
/** @fn void dmaDisable(void)
* @brief disables DMA module
*
* This function disables DMA module
*/
void dmaDisable(void)
{
/* Wait until DMA's external bus has completed data transfer */
while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U)
{
} /* Wait */
/* Disable DMA module */
dmaREG->GCTRL = 0U;
}
/** @fn void dmaReqAssign(uint32 channel,uint32 reqline)
* @brief Initializes the DMA Driver
* @param[in] channel DMA channel
* @param[in] reqline DMA request line
*
* This function assigns dma request lines to channels
*/
void dmaReqAssign(uint32 channel,uint32 reqline)
{
register uint32 i=0U,j=0U;
i = channel >> 2U; /* Find the register to configure */
j = channel -(i<<2U); /* Find the offset of the type */
j = 3U-j; /* reverse the byte order */
j = j<<3U; /* find the bit location */
/* mapping channel 'i' to request line 'j' */
dmaREG->DREQASI[i] &= ~(0xffU<<j);
dmaREG->DREQASI[i] |= (reqline<<j);
}
/** @fn uint32 dmaGetReq(uint32 channel)
* @brief Gets the request line number mapped to the selected channel
* @param[in] channel DMA channel
*
* This function returns the request line number mapped to the selected channel
*/
uint32 dmaGetReq(uint32 channel)
{
register uint32 i=0U,j=0U;
i = channel >> 2U; /* Find the register to configure */
j = channel -(i<<2U); /* Find the offset of the type */
j = 3U-j; /* reverse the byte order */
j = j<<3U; /* find the bit location */
return ((dmaREG->DREQASI[i] >> j) &0xffU);
}
/** @fn void dmaSetCtrlPacket(uint32 channel)
* @brief Initializes the DMA Driver
*
* This function sets control packet
*/
void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT)
{
register uint32 i=0U,j=0U;
dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD;
dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD;
dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT;
dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14U) | (g_dmaCTRLPKT.WRSIZE << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \
(g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT);
dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U);
dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET);
dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET);
i = channel >> 3U; /* Find the register to write */
j = channel -(i << 3U); /* Find the offset of the 4th bit */
j = 7U -j; /* Reverse the order of the 4th bit offset */
j = j<<2U; /* Find the bit location of the 4th bit to write */
dmaREG->PAR[i] &= ~(0xfU<<j);
dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);
}
/** @fn void dmaSetChEnable(uint32 channel,uint32 type)
* @brief Enable channel
* @param[in] channel DMA channel
* @param[in] type Type of triggering
* - DMA_HW: Enables the selected DMA channel for hardware triggering
* - DMA_SW: Enables the selected DMA channel for software triggering
*
* This function enables the DMA channel for hardware or software triggering
*/
void dmaSetChEnable(uint32 channel,uint32 type)
{
if(type == DMA_HW)
{
dmaREG->HWCHENAS = (1U << channel);
}
else if(type == DMA_SW)
{
dmaREG->SWCHENAS = (1U << channel);
}
else
{
/** Empty */
}
}
/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
* @brief Assign Priority to the channel
* @param[in] channel DMA channel
* @param[in] priority Priority queue to which channel needs to be assigned
* - LOWPRIORITY : The selected channel will be assigned to low priority queue
* - HIGHPRIORITY: The selected channel will be assigned to high priority queue
*
* This function assigns the selected priority to the selected channel
*/
void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
{
if (priority == LOWPRIORITY)
{
dmaREG->CHPRIOR |= 1U << channel;
}
else
{
dmaREG->CHPRIOS |= 1U << channel;
}
}
/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
* @brief Enable selected interrupt
* @param[in] channel DMA channel
* @param[in] inttype Interrupt to be enabled
* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
* - BER: Bus Error Interrupt will be disabled for the selected channel
*
* This function enables the selected interrupt for the selected channel
*/
void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
{
dmaREG->GCHIENAS = 1 << channel;
switch (inttype)
{
case FTC: dmaREG->FTCINTENAS |= 1U << channel;
break;
case LFS: dmaREG->LFSINTENAS |= 1U << channel;
break;
case HBC: dmaREG->HBCINTENAS |= 1U << channel;
break;
case BTC: dmaREG->BTCINTENAS |= 1U << channel;
break;
default :
break;
}
}
/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
* @brief Disable selected interrupt
* @param[in] channel DMA channel
* @param[in] inttype Interrupt to be disabled
* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
* - BER: Bus Error Interrupt will be disabled for the selected channel
*
* This function disables the selected interrupt for the selected channel
*/
void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
{
switch (inttype)
{
case FTC: dmaREG->FTCINTENAR |= 1U << channel;
break;
case LFS: dmaREG->LFSINTENAR |= 1U << channel;
break;
case HBC: dmaREG->HBCINTENAR |= 1U << channel;
break;
case BTC: dmaREG->BTCINTENAR |= 1U << channel;
break;
default :
break;
}
}
/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
* @brief Configure start and end address of the region
* @param[in] region Memory Region
* - DMA_REGION0
* - DMA_REGION1
* - DMA_REGION2
* - DMA_REGION3
* @param[in] start_add Start address of the the region
* @param[in] end_add End address of the region
*
* This function configure start and end address of the selected region
*/
void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
{
dmaREG->DMAMPR[region].STARTADD = start_add;
dmaREG->DMAMPR[region].ENDADD = end_add;
}
/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
* @brief Enable the selected region
* @param[in] region Memory Region
* - DMA_REGION0
* - DMA_REGION1
* - DMA_REGION2
* - DMA_REGION3
* @param[in] access Access permission of the selected region
* - FULLACCESS
* - READONLY
* - WRITEONLY
* - NOACCESS
* @param[in] intenable Interrupt to be enabled or not
* - INTERRUPT_ENABLE : Enable interrupt for the selected region
* - INTERRUPT_DISABLE: Disable interrupt for the selected region
*
* This function enables the selected region with selected access permission with or without interrupt enable
*/
void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
{
/* Enable the region */
dmaREG->DMAMPCTRL |= 1U << (region*8U);
/* Set access permission for the region */
dmaREG->DMAMPCTRL |= access << ((region*8U) + 1U);
/* Enable or Disable interrupt */
dmaREG->DMAMPCTRL |= intenable << ((region*8U) + 3U);
}
/** @fn void dmaDisableRegion(dmaREGION_t region)
* @brief Disable the selected region
* @param[in] region Memory Region
* - DMA_REGION0
* - DMA_REGION1
* - DMA_REGION2
* - DMA_REGION3
*
* This function disables the selected region(no address checking done).
*/
void dmaDisableRegion(dmaREGION_t region)
{
dmaREG->DMAMPCTRL &= ~(1U << (region*8U));
}
/** @fn void dmaEnableParityCheck(void)
* @brief Enable Parity Check
*
* This function enables parit check
*/
void dmaEnableParityCheck(void)
{
dmaREG->DMAPCR = 0x5U;
}
/** @fn void dmaDisableParityCheck(void)
* @brief Disable Parity Check
*
* This function disables parity check
*/
void dmaDisableParityCheck(void)
{
dmaREG->DMAPCR = 0xAU;
}
bsp/rm48x50/HALCoGen/source/sys_intvecs.asm
-44
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@@ -1,44 +0,0 @@
;-------------------------------------------------------------------------------
; sys_intvecs.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.sect ".intvecs"
.arm
;-------------------------------------------------------------------------------
; import reference for interrupt routines
.ref _c_int00
.ref _dabort
.ref IRQ_Handler
.def resetEntry
;-------------------------------------------------------------------------------
; interrupt vectors
resetEntry
b _c_int00
b turnon_VFP
svcEntry
b svcEntry
prefetchEntry
b prefetchEntry
b _dabort
reservedEntry
b reservedEntry
b IRQ_Handler
ldr pc,[pc,#-0x1b0]
.sect ".text"
turnon_VFP
; Enable FPV
STMDB sp!, {r0}
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
LDMIA sp!, {r0}
subs pc, lr, #4
;-------------------------------------------------------------------------------
bsp/rm48x50/HALCoGen/source/sys_main.c
-82
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@@ -1,82 +0,0 @@
/** @file sys_main.c
* @brief Application main file
* @date 29.May.2013
* @version 03.05.02
*
* This file contains an empty main function,
* which can be used for the application.
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* USER CODE BEGIN (0) */
/* we will use our own main and get rid off everything from HALCoGen here */
#if 0
#include <stdint.h>
/* USER CODE END */
/* Include Files */
#include "sys_common.h"
#include "system.h"
/* USER CODE BEGIN (1) */
/* Include HET header file - types, definitions and function declarations for system driver */
#include "het.h"
#include "esm.h"
#include "sci.h"
#include "rti.h"
/* Task1 */
void vTaskDelay(int t)
{
for (; t; t--)
{
int i;
for(i = 100000;i ; i--)
{
}
}
}
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
uint8_t sci_buf;
/* USER CODE END */
void main(void)
{
/* USER CODE BEGIN (3) */
/* Set high end timer GIO port hetPort pin direction to all output */
gioSetDirection(hetPORT1, 0xFFFFFFFF);
sciInit();
rtiInit();
rtiStartCounter(rtiCOUNTER_BLOCK1);
rtiEnableNotification(rtiNOTIFICATION_COMPARE3);
_enable_IRQ();
sciReceive(scilinREG, 1, &sci_buf);
for(;;)
{
gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1);
/* Taggle HET[1] with timer tick */
/*sciSendByte(scilinREG, 'b');*/
vTaskDelay(100);
/*sciSendByte(scilinREG, 'a');*/
}
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
#endif
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/sys_mpu.asm
-403
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@@ -1,403 +0,0 @@
;-------------------------------------------------------------------------------
; sys_mpu.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Initalize Mpu
.def _mpuInit_
.asmfunc
_mpuInit_
stmfd sp!, {r0}
; Disable mpu
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
; Disable background region
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
; Setup region 1
mov r0, #0
mcr p15, #0, r0, c6, c2, #0
ldr r0, r1Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1000
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 2
mov r0, #1
mcr p15, #0, r0, c6, c2, #0
ldr r0, r2Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x0600
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region
mov r0, #2
mcr p15, #0, r0, c6, c2, #0
ldr r0, r3Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 4
mov r0, #3
mcr p15, #0, r0, c6, c2, #0
ldr r0, r4Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 5
mov r0, #4
mcr p15, #0, r0, c6, c2, #0
ldr r0, r5Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0000
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x19 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 6
mov r0, #5
mcr p15, #0, r0, c6, c2, #0
ldr r0, r6Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0000
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 7
mov r0, #6
mcr p15, #0, r0, c6, c2, #0
ldr r0, r7Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1200
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 8
mov r0, #7
mcr p15, #0, r0, c6, c2, #0
ldr r0, r8Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0010
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 9
mov r0, #8
mcr p15, #0, r0, c6, c2, #0
ldr r0, r9Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0010
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x08 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 10
mov r0, #9
mcr p15, #0, r0, c6, c2, #0
ldr r0, r10Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0010
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 11
mov r0, #10
mcr p15, #0, r0, c6, c2, #0
ldr r0, r11Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1100
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0A << 1) + (0))
mcr p15, #0, r0, c6, c1, #2
; Setup region 12
mov r0, #11
mcr p15, #0, r0, c6, c2, #0
ldr r0, r12Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (0))
mcr p15, #0, r0, c6, c1, #2
; Enable mpu background region
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
; Enable mpu
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
ldmfd sp!, {r0}
bx lr
r1Base .word 0x00000000
r2Base .word 0x00000000
r3Base .word 0x08000000
r4Base .word 0x08400000
r5Base .word 0x60000000
r6Base .word 0x80000000
r7Base .word 0xF0000000
r8Base .word 0xFC000000
r9Base .word 0xFE000000
r10Base .word 0xFF000000
r11Base .word 0x08001000
r12Base .word 0x20000000
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Mpu
.def _mpuEnable_
.asmfunc
_mpuEnable_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Mpu
.def _mpuDisable_
.asmfunc
_mpuDisable_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Mpu background region
.def _mpuEnableBackgroundRegion_
.asmfunc
_mpuEnableBackgroundRegion_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Mpu background region
.def _mpuDisableBackgroundRegion_
.asmfunc
_mpuDisableBackgroundRegion_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Returns number of implemented Mpu regions
.def _mpuGetNumberOfRegions_
.asmfunc
_mpuGetNumberOfRegions_
mrc p15, #0, r0, c0, c0, #4
uxtb r0, r0, ROR #8
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Returns the type of the implemented mpu regions
.def _mpuAreRegionsSeparate_
.asmfunc
_mpuAreRegionsSeparate_
mrc p15, #0, r0, c0, c0, #4
uxtb r0, r0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set mpu region number
.def _mpuSetRegion_
.asmfunc
_mpuSetRegion_
mcr p15, #0, r0, c6, c2, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get mpu region number
.def _mpuGetRegion_
.asmfunc
_mpuGetRegion_
mrc p15, #0, r0, c6, c2, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set base address
.def _mpuSetRegionBaseAddress_
.asmfunc
_mpuSetRegionBaseAddress_
mcr p15, #0, r0, c6, c1, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get base address
.def _mpuGetRegionBaseAddress_
.asmfunc
_mpuGetRegionBaseAddress_
mrc p15, #0, r0, c6, c1, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set type and permission
.def _mpuSetRegionTypeAndPermission_
.asmfunc
_mpuSetRegionTypeAndPermission_
orr r0, r0, r1
mcr p15, #0, r0, c6, c1, #4
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get type
.def _mpuGetRegionType_
.asmfunc
_mpuGetRegionType_
mrc p15, #0, r0, c6, c1, #4
bic r0, r0, #0xFF00
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get permission
.def _mpuGetRegionPermission_
.asmfunc
_mpuGetRegionPermission_
mrc p15, #0, r0, c6, c1, #4
bic r0, r0, #0xFF
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set region size register value
.def _mpuSetRegionSizeRegister_
.asmfunc
_mpuSetRegionSizeRegister_
mcr p15, #0, r0, c6, c1, #2
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
bsp/rm48x50/HALCoGen/source/sys_pcr.c
-602
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File diff suppressed because it is too large Load Diff
bsp/rm48x50/HALCoGen/source/sys_phantom.c
-32
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@@ -1,32 +0,0 @@
/** @file sys_phantom.c
* @brief Phantom Interrupt Source File
* @date 29.May.2013
* @version 03.05.02
*
* This file contains:
* - Phantom Interrupt Handler
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Phantom Interrupt Handler */
/* USER CODE BEGIN (1) */
/* USER CODE END */
#pragma CODE_STATE(phantomInterrupt, 32)
#pragma INTERRUPT(phantomInterrupt, IRQ)
void phantomInterrupt(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
}
/* USER CODE BEGIN (3) */
/* USER CODE END */
bsp/rm48x50/HALCoGen/source/sys_pmm.c
-348
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@@ -1,348 +0,0 @@
/** @file sys_pmm.c
* @brief PCR Driver Implementation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_pmm.h"
/** @fn void pmmInit(void)
* @brief Initializes the PMM Driver
*
* This function initializes the PMM module.
*/
void pmmInit(void)
{
/*Disable clocks to all logic domains*/
pmmREG->PDCLKDISREG = 0xFU;
/*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/
pmmREG->GLOBALCTRL1 = (0U << 8U) | (0U << 0U); /*from GUI*/
/*Power on the logic power domains*/
pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
/*Power on the memory-only power domains*/
pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
/*wait till Logic Power Domain PD2 turns ON*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD2] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Logic Power Domain PD3 turns ON*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD3] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Logic Power Domain PD4 turns OFF*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD4] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
{
}/* Wait */
/*wait till Logic Power Domain PD5 turns ON*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD5] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Memory Only Power Domain RAM_PD1 turns ON*/
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD1] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Memory Only Power Domain RAM_PD2 turns ON*/
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD2] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Memory Only Power Domain RAM_PD3 turns ON*/
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD3] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
{
/* Enable clocks for the selected logic domain */
pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
}
}
/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
* @brief Turns on Logic Power Domain
* @param[in] logicPD - Power Domain to be turned on
* - PMM_LOGICPD2: Power domain PD2 will be turned on
* - PMM_LOGICPD3: Power domain PD3 will be turned on
* - PMM_LOGICPD4: Power domain PD4 will be turned on
* - PMM_LOGICPD5: Power domain PD5 will be turned on
*
* This function turns on the selected Logic Power Domain
*
*/
void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
{
if (logicPD != PMM_LOGICPD1)
{
/* Power on the domain */
if (logicPD == PMM_LOGICPD2)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
}
else if (logicPD == PMM_LOGICPD3)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
}
else if (logicPD == PMM_LOGICPD4)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
}
else
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0x5U << 0U);
}
/* Wait until the power domain turns on */
while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
{
/* Enable clocks to the power domain */
pmmREG->PDCLKDISCLRREG = 1U << (uint32)logicPD;
}
}
}
/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
* @brief Turns on Memory Power Domain
* @param[in] memPD - Power Domain to be tured on
* - PMM_MEMPD1: Power domain RAM_PD1 will be turned on
* - PMM_MEMPD2: Power domain RAM_PD2 will be turned on
* - PMM_MEMPD3: Power domain RAM_PD3 will be turned on
*
* This function turns on the selected Memory Power Domain
*
*/
void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
{
/* Power on the domain */
if (memPD == PMM_MEMPD1)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
}
else if (memPD == PMM_MEMPD2)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
}
else
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
}
/*Wait until the power domain turns on*/
while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
}
/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
* @brief Turns off Logic Power Domain
* @param[in] logicPD - Power Domain to be tured off
* - PMM_LOGICPD2: Power domain PD2 will be turned off
* - PMM_LOGICPD3: Power domain PD3 will be turned off
* - PMM_LOGICPD4: Power domain PD4 will be turned off
* - PMM_LOGICPD5: Power doamin PD5 will be turned off
*
* This function turns off the selected Logic Power Domain
*
*/
void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
{
if (logicPD != PMM_LOGICPD1)
{
/* Disable all clocks to the power domain */
pmmREG->PDCLKDISSETREG = 1U << (uint32)logicPD;
/* Power down the domain */
if (logicPD == PMM_LOGICPD2)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
}
else if (logicPD == PMM_LOGICPD3)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
}
else if (logicPD == PMM_LOGICPD4)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
}
else
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0xAU << 0U);
}
/* Wait until the power domain turns off */
while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
{
}/* Wait */
}
}
/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
* @brief Turns off Memory Power Domain
* @param[in] memPD - Power Domain to be tured off
* - PMM_MEMPD1: Power domain RAM_PD1 will be turned off
* - PMM_MEMPD2: Power domain RAM_PD2 will be turned off
* - PMM_MEMPD3: Power domain RAM_PD3 will be turned off
*
* This function turns off the selected Memory Power Domain
*
*/
void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
{
/* Power down the domain */
if (memPD == PMM_MEMPD1)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
}
else if (memPD == PMM_MEMPD2)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
}
else
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
}
/*Wait until the power domain turns off*/
while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT) != 0U)
{
}/* Wait */
}
/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
* @brief Check if the power domain is active or not
* @param[in] logicPD - Power Domain to be be checked
* - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not
* - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not
* - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not
* - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not
* @return The function will return:
* - TRUE : When the selected power domain is in Active state.
* - FALSE: When the selected power domain is in OFF state.
*
* This function checks whether the selected power domain is active or not.
*
*/
boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
{
boolean status;
if ((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
status = FALSE;
}
else
{
status = TRUE;
}
return status;
}
/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
* @brief Check if the power domain is active or not
* @param[in] memPD - Power Domain to be tured off
* - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not
* - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not
* - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not
* @return The function will return:
* - TRUE : When the selected power domain is in Active state.
* - FALSE: When the selected power domain is in OFF state.
*
* This function checks whether the selected power domain is active or not.
*
*/
boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
{
boolean status;
if ((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
status = FALSE;
}
else
{
status = TRUE;
}
return status;
}
/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
* @brief Get the initial or current values of the configuration register
* @param[in] *config_reg - pointer to the struct to which the initial or current value of the configuration registers need to be stored
* @param[in] type - whether initial or current value of the configuration registers need to be stored
* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
*/
void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
{
if (type == InitialValue)
{
config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE;
}
else
{
config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0;
config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0;
config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG;
config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1;
}
}
/** @fn void pmmSetMode(pmm_Mode_t mode)
* @brief Set PSCON Compare Block Mode
* @param[in] mode - PSCON Compare Block mode
* - LockStep : PSCON compare block is set to Lock-Step mode
* - SelfTest : PSCON compare block is set to Self-Test mode
* - ErrorForcing : PSCON compare block is set to Error-Forcing mode
* - SelfTestErrorForcing : PSCON compare block is set to Self-Test-Error-Forcing mode
*
* This function sets the PSCON Compare block to the selected mode
*
*/
void pmmSetMode(pmm_Mode_t mode)
{
/* Set PSCON Compare Block Mode */
pmmREG->PRCKEYREG = mode;
}
/** @fn boolean pmmPerformSelfTest(void)
* @brief Perform self test and return the result
*
* @return The function will return
* - TRUE if PSCON compare block passed self-test
* - FALSE if PSCON compare block failed in self-test
*
* This function checks whether PSCON compare block passed the self-test or not.
*
*/
boolean pmmPerformSelfTest(void)
{
boolean status = TRUE;
/*Enter self-test mode*/
pmmREG->PRCKEYREG = SelfTest;
/*Wait till self test is completed*/
while ((pmmREG->LPDDCSTAT1 & 0xFU) != 0xFU)
{
}/* Wait */
while ((pmmREG->MPDDCSTAT1 & 0x7U) != 0x7U)
{
}/* Wait */
/*Check whether self-test passed or not*/
if ((pmmREG->LPDDCSTAT2 & 0xFU) != 0U)
{
status = FALSE;
}
if ((pmmREG->MPDDCSTAT2 & 0x7U) != 0U)
{
status = FALSE;
}
/*Enter lock-step mode*/
pmmREG->PRCKEYREG = LockStep;
return status;
}
bsp/rm48x50/HALCoGen/source/sys_pmu.asm
-223
View File
@@ -1,223 +0,0 @@
;-------------------------------------------------------------------------------
; sys_pmu.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Initialize Pmu
; Note: It will reset all counters
.def _pmuInit_
.asmfunc
_pmuInit_
stmfd sp!, {r0}
; set control register
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #(1 << 4) + 6 + 1
mcr p15, #0, r0, c9, c12, #0
; clear flags
mov r0, #0
sub r1, r1, #1
mcr p15, #0, r0, c9, c12, #3
; select counter 0 event
mcr p15, #0, r0, c9, c12, #5 ; select counter
mov r0, #0x11
mcr p15, #0, r0, c9, c13, #1 ; select event
; select counter 1 event
mov r0, #1
mcr p15, #0, r0, c9, c12, #5 ; select counter
mov r0, #0x11
mcr p15, #0, r0, c9, c13, #1 ; select event
; select counter 2 event
mov r0, #2
mcr p15, #0, r0, c9, c12, #5 ; select counter
mov r0, #0x11
mcr p15, #0, r0, c9, c13, #1 ; select event
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Counters Global [Cycle, Event [0..2]]
; Note: It will reset all counters
.def _pmuEnableCountersGlobal_
.asmfunc
_pmuEnableCountersGlobal_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #7
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Counters Global [Cycle, Event [0..2]]
.def _pmuDisableCountersGlobal_
.asmfunc
_pmuDisableCountersGlobal_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
bic r0, r0, #1
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Reset Cycle Counter
.def _pmuResetCycleCounter_
.asmfunc
_pmuResetCycleCounter_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #4
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Reset Event Counters [0..2]
.def _pmuResetEventCounters_
.asmfunc
_pmuResetEventCounters_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #2
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Reset Cycle Counter abd Event Counters [0..2]
.def _pmuResetCounters_
.asmfunc
_pmuResetCounters_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #6
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Start Counters [Cycle, 0..2]
.def _pmuStartCounters_
.asmfunc
_pmuStartCounters_
mcr p15, #0, r0, c9, c12, #1
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Stop Counters [Cycle, 0..2]
.def _pmuStopCounters_
.asmfunc
_pmuStopCounters_
mcr p15, #0, r0, c9, c12, #2
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set Count event
.def _pmuSetCountEvent_
.asmfunc
_pmuSetCountEvent_
lsr r0, r0, #1
mcr p15, #0, r0, c9, c12, #5 ; select counter
mcr p15, #0, r1, c9, c13, #1 ; select event
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get Cycle Count
.def _pmuGetCycleCount_
.asmfunc
_pmuGetCycleCount_
mrc p15, #0, r0, c9, c13, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get Event Counter Count Value
.def _pmuGetEventCount_
.asmfunc
_pmuGetEventCount_
lsr r0, r0, #1
mcr p15, #0, r0, c9, c12, #5 ; select counter
mrc p15, #0, r0, c9, c13, #2 ; read event counter
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get Overflow Flags
.def _pmuGetOverflow_
.asmfunc
_pmuGetOverflow_
mrc p15, #0, r0, c9, c12, #3 ; read overflow
mov r1, #0
sub r1, r1, #1
mcr p15, #0, r1, c9, c12, #3 ; clear flags
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
bsp/rm48x50/HALCoGen/source/sys_selftest.c
-2178
View File
File diff suppressed because it is too large Load Diff
bsp/rm48x50/HALCoGen/source/sys_startup.c
+56 -459
View File
File diff suppressed because it is too large Load Diff
bsp/rm48x50/HALCoGen/source/sys_vim.c
+3 -145
View File
@@ -30,140 +30,6 @@ typedef volatile struct vimRam
#define vimRAM ((vimRAM_t *)0xFFF82000U)
static const t_isrFuncPTR s_vim_init[129] =
{
&phantomInterrupt,
&esmHighInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&rtiCompare3Interrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&linHighLevelInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
};
void vimParityErrorHandler(void);
/** @fn void vimInit(void)
* @brief Initializes VIM module
*
@@ -172,18 +38,8 @@ void vimParityErrorHandler(void);
void vimInit(void)
{
/* Initialize VIM table */
{
uint32 i;
for (i = 0U; i < (VIM_CHANNELS + 1U); i++)
{
vimRAM->ISR[i] = s_vim_init[i];
}
}
/* Set Fall-Back Address Parity Error Register */
VIM_FBPARERR = (uint32)&vimParityErrorHandler;
/*VIM_FBPARERR = (uint32)&vimParityErrorHandler;*/
/* set IRQ/FIQ priorities */
vimREG->FIRQPR0 = SYS_FIQ
@@ -627,6 +483,7 @@ void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
}
#if 0
#pragma CODE_STATE(vimParityErrorHandler, 32)
#pragma INTERRUPT(vimParityErrorHandler, IRQ)
@@ -674,3 +531,4 @@ void vimParityErrorHandler(void)
}
}
}
#endif
bsp/rm48x50/HALCoGen/source/system.c
+4 -3
View File
@@ -282,7 +282,7 @@ void systemInit(void)
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
*/
efcCheck();
//efcCheck();
/* USER CODE BEGIN (17) */
/* USER CODE END */
@@ -294,17 +294,18 @@ void systemInit(void)
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
//muxInit();
/* USER CODE BEGIN (19) */
/* USER CODE END */
#if 0
/* Wait for eFuse controller self-test to complete and check results */
if ((!checkefcSelfTest()) !=0U) /* eFuse controller ECC logic self-test failed */
{
efcClass2Error(); /* device operation is not reliable */
}
#endif
/* USER CODE BEGIN (20) */
/* USER CODE END */
bsp/rm48x50/SConscript
+12
View File
@@ -0,0 +1,12 @@
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/rm48x50/SConstruct
+31
View File
@@ -0,0 +1,31 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-rm48x50.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
if env['PLATFORM'] == 'win32':
env['ASCOM'] = '$AS $ASFLAGS $CCFLAGS $_CCCOMCOM -o $TARGET $SOURCES'
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
Depends(TARGET, 'rm48x50.ld')
# make a building
DoBuilding(TARGET, objs)
bsp/rm48x50/application/SConscript
+9
View File
@@ -0,0 +1,9 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/rm48x50/application/startup.c
+23 -1
View File
@@ -19,7 +19,7 @@
#ifdef RT_USING_FINSH
#include <finsh.h>
extern void finsh_system_init(void);
extern int finsh_system_init(void);
#endif
#include <board.h>
@@ -43,6 +43,28 @@ extern unsigned char * const system_data_end;
#endif
#define MEMEND 0x08040000
void rt_hw_pmu_enable_cnt(void)
{
unsigned long tmp;
__asm (" MRC p15, #0, r0, c9, c12, #0");
__asm (" ORR r0, r0, #0x09\n");
__asm (" MCR p15, #0, r0, c9, c12, #0\n");
__asm (" MOV r0, #1\n");
__asm (" RBIT r0, r0\n");
__asm (" MCR p15, #0, r0, c9, c12, #1\n");
}
void rt_hw_pmu_setcnt(unsigned long val)
{
__asm (" MCR p15, #0, r0, c9, c13, #0");
}
unsigned long rt_hw_pmu_getcnt(void)
{
__asm (" MRC p15, #0, r0, c9, c13, #0");
}
/**
* This function will startup RT-Thread RTOS.
*/
bsp/rm48x50/drivers/SConscript
-9
View File
@@ -6,15 +6,6 @@ from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
# remove no need file.
if GetDepend('RT_USING_LWIP') == False:
src_need_remove = ['dm9000.c'] # need remove file list.
SrcRemove(src, src_need_remove)
if GetDepend('RT_USING_DFS') == False:
src_need_remove = ['sd.c'] # need remove file list.
SrcRemove(src, src_need_remove)
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
bsp/rm48x50/drivers/board.h
+1 -1
View File
@@ -20,7 +20,7 @@
#define RT_USING_UART2
#define RT_UART_RX_BUFFER_SIZE 64
void rt_hw_board_init(void);
void rt_hw_led_set(rt_uint32_t led);
void rt_hw_led_set(int led);
void rt_hw_led_flash(void);
#ifdef RT_USING_FINSH
bsp/rm48x50/rm48x50.ld
+144
View File
@@ -0,0 +1,144 @@
/*
* linker script for RM48x50 with GNU ld
* Grissiom 2013-10-20
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x00000000, LENGTH = 3M
DATA (rw) : ORIGIN = 0x08000000, LENGTH = 256k
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(system_vectors)
SECTIONS
{
.text :
{
__text_start = .;
*(.vectors)
*(.text)
*(.text.*)
__rodata_start = .;
*(.rodata)
*(.rodata.*)
__rodata_end = .;
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.v4_bx)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for initialization */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
__text_end = .;
} > CODE = 0
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
} > CODE
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
__data_end = .;
__noinit_start = .;
.noinit :
{
. = ALIGN(4);
*(.bss.noinit)
} > DATA
__noinit_stop = .;
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
} > DATA
__bss_end = .;
/* Stabs debugging sections.
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
*/
_end = .;
}
bsp/rm48x50/rtconfig.h
+3 -3
View File
@@ -19,7 +19,7 @@
// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
#define IDLE_THREAD_STACK_SIZE 512
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
//#define RT_DEBUG
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
@@ -27,7 +27,7 @@
// </section>
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
#define RT_USING_HOOK
//#define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
@@ -131,7 +131,7 @@
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
#define RT_USING_LWIP
//#define RT_USING_LWIP
// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
#define RT_USING_LWIP141
// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
bsp/rm48x50/rtconfig.py
+103
View File
@@ -0,0 +1,103 @@
import os
# toolchains options
ARCH='arm'
CPU='cortex-r4'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Program Files\GNU Tools ARM Embedded\4.7 2013q3\bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil'
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support IAR yet!'
print '================================================='
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -Wall -march=armv7-r -mfloat-abi=hard'+\
' -ftree-vectorize -ffast-math -mfpu=vfpv3-d16 '+\
' -ffunction-sections -fdata-sections '
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-rm48x50.map,-cref,-u,system_vectors -T rm48x50.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 '
AFLAGS += ' -g -gdwarf-2'
else:
CFLAGS += ' -O3 -g -gdwarf-2'
AFLAGS += ' -g -gdwarf-2'
POST_ACTION = SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMP'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-beaglebone.map --scatter beaglebone_ram.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' --cpu DARMP'
CFLAGS = ''
AFLAGS = ''
LFLAGS = ' --config beaglebone_ram.icf'
EXEC_PATH += '/arm/bin/'
RT_USING_MINILIBC = False
POST_ACTION = ''