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[libcpu] mips: Merge loongson_1 into gs232

Browse Source 
Previously Loongson 1B and Loongson 1C have their own libcpu
implemention, but they're almost identical. So we merge them
into gs232 and adapt to new common code.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang
2019-12-07 00:55:46 +08:00
parent 7c66501861
commit 9ef986929c
33 changed files with 920 additions and 3359 deletions
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0
libcpu/mips/loongson_1b/SConscript → libcpu/mips/gs232/SConscript
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231
libcpu/mips/gs232/cache.c Normal file
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@@ -0,0 +1,231 @@
/*
* Cache Ops For Loongson GS232
*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
* 2015-07-08 chinesebear modified for loongson 1c
*/
#include <rtthread.h>
#include <mips.h>
#define K0BASE 0x80000000
#define PRID_LS1C 0x4220
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Ls1c(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
extern void enable_cpu_cache(void);
typedef struct cacheinfo_t
{
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t
{
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu(void)
{
unsigned int cpu_id;
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_LS1C:
rt_kprintf("CPU:Loongson 1C\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
break;
default:
rt_kprintf("Unknown CPU type, system halted!\n");
while (1)
{
;
}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config1 = read_c0_config1();
unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
if ((icache_line_size = ((config1 >> 19) & 7)))
icache_line_size = 2 << icache_line_size;
else
icache_line_size = icache_line_size;
icache_sets = 64 << ((config1 >> 22) & 7);
icache_ways = 1 + ((config1 >> 16) & 7);
icache_size = icache_sets * icache_ways * icache_line_size;
if ((dcache_line_size = ((config1 >> 10) & 7)))
dcache_line_size = 2 << dcache_line_size;
else
dcache_line_size = dcache_line_size;
dcache_sets = 64 << ((config1 >> 13) & 7);
dcache_ways = 1 + ((config1 >> 7) & 7);
dcache_size = dcache_sets * dcache_ways * dcache_line_size;
rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = icache_line_size;
pcacheinfo->dcacheline_size = dcache_line_size;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
Invalidate_Dcache_Fill_Ls1c(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}

13
libcpu/mips/loongson_1c/cache.h → libcpu/mips/gs232/cache.h
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@@ -1,20 +1,19 @@
/* /*
* File : cache.h * Cache Ops For Loongson GS232
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
* *
* The license and distribution terms for this file may be * Copyright (c) 2006-2019, RT-Thread Development Team
* found in the file LICENSE in this distribution or at *
* http://www.rt-thread.org/license/LICENSE * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2010-07-09 Bernard first version * 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B * 2011-08-08 lgnq modified for LS1B
* 2015-07-08 chinesebear modified for loongson 1c
*/ */
#ifndef __CACHE_H__ #ifndef __CACHE_H__
#define __CACHE_H__ #define __CACHE_H__
/* /*
* Cache Operations * Cache Operations
*/ */

4
libcpu/mips/loongson_1c/cache_gcc.S → libcpu/mips/gs232/cache_gcc.S
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@@ -16,9 +16,7 @@
#define __ASSEMBLY__ #define __ASSEMBLY__
#endif #endif
#include "../common/mipsregs.h" #include <mips.h>
#include "../common/mips_def.h"
#include "../common/asm.h"
#include "cache.h" #include "cache.h"
.ent cache_init .ent cache_init

23
libcpu/mips/gs232/cpuinit_gcc.S Normal file
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@@ -0,0 +1,23 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
.section ".start", "ax"
.set noreorder
.globl rt_cpu_early_init
rt_cpu_early_init:
jr ra
nop

72
libcpu/mips/gs232/cpuport.c Normal file
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@@ -0,0 +1,72 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
* 2015-07-06 chinesebear modified for loongson 1c
*/
#include <rtthread.h>
#include "gs232.h"
/**
* @addtogroup Loongson GS232
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WDT_SET = 0x01; /* watch dog start */
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define CONFIG_SYS_CACHELINE_SIZE 32
#define Hit_Writeback_Inv_D 0x15
void flush_cache(unsigned long start_addr, unsigned long size)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
/*@}*/

67
libcpu/mips/gs232/gs232.h Normal file
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@@ -0,0 +1,67 @@
/*
* Misc define for GS232
*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __GS232_H__
#define __GS232_H__
#include <mips.h>
#define INTC_BASE 0xBFD01040
#define GS232_INTC_CELLS 5
#define GS232_NR_IRQS (32 * GS232_INTC_CELLS)
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
#ifndef __ASSEMBLY__
#include <rthw.h>
/* Watch Dog registers */
#define WDT_EN HWREG32(WDT_BASE + 0x00)
#define WDT_SET HWREG32(WDT_BASE + 0x04)
#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
#define PLL_FREQ HWREG32(0xbfe78030)
#define PLL_DIV_PARAM HWREG32(0xbfe78034)
struct gs232_intc_regs
{
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
};
extern void rt_hw_timer_init(void);
#endif
#endif

162
libcpu/mips/gs232/interrupt.c Normal file
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@@ -0,0 +1,162 @@
/*
* Interrupt handle for GS232
*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
* 2013-03-29 aozima Modify the interrupt interface implementations.
* 2015-07-06 chinesebear modified for loongson 1c
* 2019-12-04 Jiaxun Yang Generialize
*/
#include <rtthread.h>
#include <rthw.h>
#include "gs232.h"
#define MAX_INTR (GS232_NR_IRQS)
static struct rt_irq_desc irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
static struct gs232_intc_regs volatile *gs232_hw0_icregs
= (struct gs232_intc_regs volatile *)(INTC_BASE);
/**
* @addtogroup Loongson GS232
*/
/*@{*/
static void rt_hw_interrupt_handler(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t idx;
rt_int32_t i;
rt_uint32_t c0_status = 0;
for (i=0; i < GS232_INTC_CELLS; i++)
{
/* Disable */
(gs232_hw0_icregs+i)->int_en = 0x0;
/* Trigger active low */
(gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */
/* Make all interrupts level triggered */
(gs232_hw0_icregs+i)->int_edge = 0x00000000;
/* Mask all interrupts */
(gs232_hw0_icregs+i)->int_clr = 0xffffffff;
mips_unmask_cpu_irq(i + 2);
}
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
for (idx = 0; idx < MAX_INTR; idx ++)
{
irq_handle_table[idx].handler = rt_hw_interrupt_handler;
}
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
(gs232_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
(gs232_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector >= 0 && vector < MAX_INTR)
{
old_handler = irq_handle_table[vector].handler;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
irq_handle_table[vector].handler = handler;
irq_handle_table[vector].param = param;
}
return old_handler;
}
/**
* ִ Call ISR
* @IRQn ID of IRQ
*/
void gs232_do_IRQ(int IRQn)
{
rt_isr_handler_t irq_func;
void *param;
irq_func = irq_handle_table[IRQn].handler;
param = irq_handle_table[IRQn].param;
irq_func(IRQn, param);
#ifdef RT_USING_INTERRUPT_INFO
irq_handle_table[IRQn].counter++;
#endif
return ;
}
void rt_do_mips_cpu_irq(rt_uint32_t ip)
{
rt_uint32_t intstatus, irq, n;
if (ip == 7) {
rt_hw_timer_handler();
} else {
n = ip - 2;
/* Receive interrupt signal, compute the irq */
intstatus = (gs232_hw0_icregs+n)->int_isr & (gs232_hw0_icregs+n)->int_en;
if (0 == intstatus)
return ;
irq = __rt_ffs(intstatus) - 1;
gs232_do_IRQ((n<<5) + irq);
/* ack interrupt */
(gs232_hw0_icregs+n)->int_clr |= (1 << irq);
}
}
/*@}*/

67
libcpu/mips/gs232/ls1b.h Normal file
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@@ -0,0 +1,67 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
*/
#ifndef __LS1B_H__
#define __LS1B_H__
#include <gs232.h>
#define LS1B_ACPI_IRQ 0
#define LS1B_HPET_IRQ 1
#define LS1B_UART0_IRQ 2
#define LS1B_UART1_IRQ 3
#define LS1B_UART2_IRQ 4
#define LS1B_UART3_IRQ 5
#define LS1B_CAN0_IRQ 6
#define LS1B_CAN1_IRQ 7
#define LS1B_SPI0_IRQ 8
#define LS1B_SPI1_IRQ 9
#define LS1B_AC97_IRQ 10
#define LS1B_MS_IRQ 11
#define LS1B_KB_IRQ 12
#define LS1B_DMA0_IRQ 13
#define LS1B_DMA1_IRQ 14
#define LS1B_NAND_IRQ 15
#define LS1B_I2C0_IRQ 16
#define LS1B_I2C1_IRQ 17
#define LS1B_PWM0_IRQ 18
#define LS1B_PWM1_IRQ 19
#define LS1B_PWM2_IRQ 20
#define LS1B_PWM3_IRQ 21
#define LS1B_LPC_IRQ 22
#define LS1B_EHCI_IRQ 32
#define LS1B_OHCI_IRQ 33
#define LS1B_GMAC1_IRQ 34
#define LS1B_GMAC2_IRQ 35
#define LS1B_SATA_IRQ 36
#define LS1B_GPU_IRQ 37
#define LS1B_PCI_INTA_IRQ 38
#define LS1B_PCI_INTB_IRQ 39
#define LS1B_PCI_INTC_IRQ 40
#define LS1B_PCI_INTD_IRQ 41
#define LS1B_GPIO_IRQ 64
#define LS1B_GPIO_FIRST_IRQ 64
#define LS1B_GPIO_IRQ_COUNT 96
#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
#define INT_PCI_INTA (1<<6)
#define INT_PCI_INTB (1<<7)
#define INT_PCI_INTC (1<<8)
#define INT_PCI_INTD (1<<9)
#define LS1B_LAST_IRQ 159
#define MIPS_CPU_TIMER_IRQ 167
#define LS1B_INTREG_BASE 0xbfd01040
#define LS1B_DMA_IRQ_BASE 168
#define LS1B_DMA_IRQ_COUNT 16
#endif

81
libcpu/mips/gs232/ls1c.h Normal file
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@@ -0,0 +1,81 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
* 2015-07-06 chinesebear modified for loongson 1c
*/
#ifndef __LS1C_H__
#define __LS1C_H__
#include <gs232.h>
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
//#define LS1C_UART0_IRQ 3 // linux<75><78><EFBFBD><EFBFBD>3<EFBFBD><33>v1.4<EFBFBD>汾<EFBFBD><EFBFBD>1c<EFBFBD>ֲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Σ<EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD>
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
#define LS1C_CAN1_IRQ 7
#define LS1C_SPI0_IRQ 8
#define LS1C_SPI1_IRQ 9
#define LS1C_AC97_IRQ 10
#define LS1C_MS_IRQ 11
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
#define LS1C_DMA2_IRQ 15
#define LS1C_NAND_IRQ 16
#define LS1C_PWM0_IRQ 17
#define LS1C_PWM1_IRQ 18
#define LS1C_PWM2_IRQ 19
#define LS1C_PWM3_IRQ 20
#define LS1C_RTC_INT0_IRQ 21
#define LS1C_RTC_INT1_IRQ 22
#define LS1C_RTC_INT2_IRQ 23
#define LS1C_UART3_IRQ 29
#define LS1C_ADC_IRQ 30
#define LS1C_SDIO_IRQ 31
#define LS1C_EHCI_IRQ (32+0)
#define LS1C_OHCI_IRQ (32+1)
#define LS1C_OTG_IRQ (32+2)
#define LS1C_MAC_IRQ (32+3)
#define LS1C_CAM_IRQ (32+4)
#define LS1C_UART4_IRQ (32+5)
#define LS1C_UART5_IRQ (32+6)
#define LS1C_UART6_IRQ (32+7)
#define LS1C_UART7_IRQ (32+8)
#define LS1C_UART8_IRQ (32+9)
#define LS1C_UART9_IRQ (32+13)
#define LS1C_UART10_IRQ (32+14)
#define LS1C_UART11_IRQ (32+15)
#define LS1C_I2C2_IRQ (32+17)
#define LS1C_I2C1_IRQ (32+18)
#define LS1C_I2C0_IRQ (32+19)
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_FIRST_IRQ 64
#define LS1C_GPIO_IRQ_COUNT 96
#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
#define LS1C_LAST_IRQ 159
#define LS1C_INTREG_BASE 0xbfd01040
// <20><>о1c<31><63><EFBFBD>жϷ<D0B6>Ϊ<EFBFBD><CEAA><EFBFBD>飬ÿ<E9A3AC><C3BF>32<33><32>
#define LS1C_NR_IRQS (32*5)
// GPIO<49><4F>ź<EFBFBD><C5BA>жϺ<D0B6>֮<EFBFBD><D6AE>Ļ<EFBFBD><C4BB><EFBFBD>ת<EFBFBD><D7AA>
#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn))
#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ)
#endif

77
libcpu/mips/gs232/mipscfg.c Normal file
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@@ -0,0 +1,77 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include <mips.h>
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}

41
libcpu/mips/gs232/timer.c Normal file
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@@ -0,0 +1,41 @@
/*
* Assembly Macros For MIPS
*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#include <rtthread.h>
#include <rthw.h>
#include <mips.h>
#include <board.h>
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(void)
{
unsigned int count;
count = read_c0_compare();
write_c0_compare(count);
write_c0_count(0);
/* increase a OS tick */
rt_tick_increase();
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
write_c0_count(0);
mips_unmask_cpu_irq(7);
}

230
libcpu/mips/loongson_1b/cache.c
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@@ -1,230 +0,0 @@
/*
* File : cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
#define PRID_LS1B 0x4220
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Ls1b(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
extern void enable_cpu_cache(void);
typedef struct cacheinfo_t
{
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t
{
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu(void)
{
unsigned int cpu_id;
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_LS1B:
rt_kprintf("CPU:LS1B\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
break;
default:
rt_kprintf("Unknown CPU type, system halted!\n");
while (1)
{
;
}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config1 = read_c0_config1();
unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
if ((icache_line_size = ((config1 >> 19) & 7)))
icache_line_size = 2 << icache_line_size;
else
icache_line_size = icache_line_size;
icache_sets = 64 << ((config1 >> 22) & 7);
icache_ways = 1 + ((config1 >> 16) & 7);
icache_size = icache_sets * icache_ways * icache_line_size;
if ((dcache_line_size = ((config1 >> 10) & 7)))
dcache_line_size = 2 << dcache_line_size;
else
dcache_line_size = dcache_line_size;
dcache_sets = 64 << ((config1 >> 13) & 7);
dcache_ways = 1 + ((config1 >> 7) & 7);
dcache_size = dcache_sets * dcache_ways * dcache_line_size;
rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = icache_line_size;
pcacheinfo->dcacheline_size = dcache_line_size;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
Invalidate_Dcache_Fill_Ls1b(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}

52
libcpu/mips/loongson_1b/cache.h
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@@ -1,52 +0,0 @@
/*
* File : cache.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#endif

219
libcpu/mips/loongson_1b/cache_gcc.S
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@@ -1,219 +0,0 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
* 2019-07-19 Zhou Yanjie clean up code
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include "../common/mipsregs.h"
#include "../common/mips_def.h"
#include "../common/asm.h"
#include "cache.h"
.ent cache_init
.global cache_init
.set noreorder
cache_init:
move t1,ra
####part 2####
cache_detect_4way:
mfc0 t4, CP0_CONFIG
andi t5, t4, 0x0e00
srl t5, t5, 9 #ic
andi t6, t4, 0x01c0
srl t6, t6, 6 #dc
addiu t8, $0, 1
addiu t9, $0, 2
#set dcache way
beq t6, $0, cache_d1way
addiu t7, $0, 1 #1 way
beq t6, t8, cache_d2way
addiu t7, $0, 2 #2 way
beq $0, $0, cache_d4way
addiu t7, $0, 4 #4 way
cache_d1way:
beq $0, $0, 1f
addiu t6, t6, 12 #1 way
cache_d2way:
beq $0, $0, 1f
addiu t6, t6, 11 #2 way
cache_d4way:
addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12)
1: #set icache way
beq t5, $0, cache_i1way
addiu t3, $0, 1 #1 way
beq t5, t8, cache_i2way
addiu t3, $0, 2 #2 way
beq $0, $0, cache_i4way
addiu t3, $0, 4 #4 way
cache_i1way:
beq $0, $0, 1f
addiu t5, t5, 12
cache_i2way:
beq $0, $0, 1f
addiu t5, t5, 11
cache_i4way:
addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12)
1: addiu t4, $0, 1
sllv t6, t4, t6
sllv t5, t4, t5
#if 0
la t0, memvar
sw t7, 0x0(t0) #ways
sw t5, 0x4(t0) #icache size
sw t6, 0x8(t0) #dcache size
#endif
####part 3####
.set mips3
lui a0, 0x8000
addu a1, $0, t5
addu a2, $0, t6
cache_init_d2way:
#a0=0x80000000, a1=icache_size, a2=dcache_size
#a3, v0 and v1 used as local registers
mtc0 $0, CP0_TAGHI
addu v0, $0, a0
addu v1, a0, a2
1: slt a3, v0, v1
beq a3, $0, 1f
nop
mtc0 $0, CP0_TAGLO
beq t7, 1, 4f
cache Index_Store_Tag_D, 0x0(v0) # 1 way
beq t7, 2 ,4f
cache Index_Store_Tag_D, 0x1(v0) # 2 way
cache Index_Store_Tag_D, 0x2(v0) # 4 way
cache Index_Store_Tag_D, 0x3(v0)
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_i2way:
addu v0, $0, a0
addu v1, a0, a1
1: slt a3, v0, v1
beq a3, $0, 1f
nop
beq t3, 1, 4f
cache Index_Invalidate_I, 0x0(v0) # 1 way
beq t3, 2, 4f
cache Index_Invalidate_I, 0x1(v0) # 2 way
cache Index_Invalidate_I, 0x2(v0)
cache Index_Invalidate_I, 0x3(v0) # 4 way
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_d2way:
addu v0, $0, a0
addu v1, a0, a2
1: slt a3, v0, v1
beq a3, $0, 1f
nop
beq t7, 1, 4f
cache Index_Writeback_Inv_D, 0x0(v0) #1 way
beq t7, 2, 4f
cache Index_Writeback_Inv_D, 0x1(v0) # 2 way
cache Index_Writeback_Inv_D, 0x2(v0)
cache Index_Writeback_Inv_D, 0x3(v0) # 4 way
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_init_finish:
jr t1
nop
.set reorder
.end cache_init
###########################
# Enable CPU cache #
###########################
LEAF(enable_cpu_cache)
.set noreorder
mfc0 t0, CP0_CONFIG
nop
and t0, ~0x03
or t0, 0x03
mtc0 t0, CP0_CONFIG
nop
.set reorder
j ra
END (enable_cpu_cache)
###########################
# disable CPU cache #
###########################
LEAF(disable_cpu_cache)
.set noreorder
mfc0 t0, CP0_CONFIG
nop
and t0, ~0x03
or t0, 0x2
mtc0 t0, CP0_CONFIG
nop
.set reorder
j ra
END (disable_cpu_cache)
/**********************************/
/* Invalidate Instruction Cache */
/**********************************/
LEAF(Clear_TagLo)
.set noreorder
mtc0 zero, CP0_TAGLO
nop
.set reorder
j ra
END(Clear_TagLo)
.set mips3
/**********************************/
/* Invalidate Instruction Cache */
/**********************************/
LEAF(Invalidate_Icache_Ls1b)
.set noreorder
cache Index_Invalidate_I,0(a0)
cache Index_Invalidate_I,1(a0)
cache Index_Invalidate_I,2(a0)
cache Index_Invalidate_I,3(a0)
.set reorder
j ra
END(Invalidate_Icache_Ls1b)
/**********************************/
/* Invalidate Data Cache */
/**********************************/
LEAF(Invalidate_Dcache_ClearTag_Ls1b)
.set noreorder
cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag
cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag
.set reorder
j ra
END(Invalidate_Dcache_ClearTag_Ls1b)
LEAF(Invalidate_Dcache_Fill_Ls1b)
.set noreorder
cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag
cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag
.set reorder
j ra
END(Invalidate_Dcache_Fill_Ls1b)
LEAF(Writeback_Invalidate_Dcache)
.set noreorder
cache Hit_Writeback_Inv_D, (a0)
.set reorder
j ra
END(Writeback_Invalidate_Dcache)
.set mips0

150
libcpu/mips/loongson_1b/context_gcc.S
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@@ -1,150 +0,0 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
* 2019-07-19 Zhou Yanjie clean up code
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include "../common/mips_def.h"
#include "../common/stackframe.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder

124
libcpu/mips/loongson_1b/cpuport.c
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@@ -1,124 +0,0 @@
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include "ls1b.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WDT_SET = 0x01; /* watch dog start */
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

91
libcpu/mips/loongson_1b/exception.c
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@@ -1,91 +0,0 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Loongson
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/

188
libcpu/mips/loongson_1b/interrupt.c
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@@ -1,188 +0,0 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
* 2013-03-29 aozima Modify the interrupt interface implementations.
*/
#include <rtthread.h>
#include <rthw.h>
#include "ls1b.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static struct rt_irq_desc irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
static void rt_hw_interrupt_handler(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t idx;
/* pci active low */
ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq
/* make all interrupts level triggered */
(ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
/* mask all interrupts */
(ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
for (idx = 0; idx < MAX_INTR; idx ++)
{
irq_handle_table[idx].handler = rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
(ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
(ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector >= 0 && vector < MAX_INTR)
{
old_handler = irq_handle_table[vector].handler;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
irq_handle_table[vector].handler = handler;
irq_handle_table[vector].param = param;
}
return old_handler;
}
void rt_interrupt_dispatch(void *ptreg)
{
int irq;
void *param;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
rt_uint32_t c0_cause;
volatile rt_uint32_t cause_im;
volatile rt_uint32_t status_im;
rt_uint32_t pending_im;
/* check os timer */
c0_status = read_c0_status();
c0_cause = read_c0_cause();
cause_im = c0_cause & ST0_IM;
status_im = c0_status & ST0_IM;
pending_im = cause_im & status_im;
if (pending_im & CAUSEF_IP7)
{
rt_hw_timer_handler();
}
if (pending_im & CAUSEF_IP2)
{
/* the hardware interrupt */
status = ls1b_hw0_icregs->int_isr;
if (!status)
return;
for (irq = MAX_INTR; irq > 0; --irq)
{
if ((status & (1 << irq)))
{
status &= ~(1 << irq);
irq_func = irq_handle_table[irq].handler;
param = irq_handle_table[irq].param;
/* do interrupt */
irq_func(irq, param);
#ifdef RT_USING_INTERRUPT_INFO
irq_handle_table[irq].counter++;
#endif /* RT_USING_INTERRUPT_INFO */
/* ack interrupt */
ls1b_hw0_icregs->int_clr |= (1 << irq);
}
}
}
else if (pending_im & CAUSEF_IP3)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP4)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP5)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP6)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
}
/*@}*/

140
libcpu/mips/loongson_1b/ls1b.h
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@@ -1,140 +0,0 @@
/*
* File : ls1b.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
*/
#ifndef __LS1B_H__
#define __LS1B_H__
#include "../common/mipsregs.h"
#define LS1B_ACPI_IRQ 0
#define LS1B_HPET_IRQ 1
#define LS1B_UART0_IRQ 2
#define LS1B_UART1_IRQ 3
#define LS1B_UART2_IRQ 4
#define LS1B_UART3_IRQ 5
#define LS1B_CAN0_IRQ 6
#define LS1B_CAN1_IRQ 7
#define LS1B_SPI0_IRQ 8
#define LS1B_SPI1_IRQ 9
#define LS1B_AC97_IRQ 10
#define LS1B_MS_IRQ 11
#define LS1B_KB_IRQ 12
#define LS1B_DMA0_IRQ 13
#define LS1B_DMA1_IRQ 14
#define LS1B_NAND_IRQ 15
#define LS1B_I2C0_IRQ 16
#define LS1B_I2C1_IRQ 17
#define LS1B_PWM0_IRQ 18
#define LS1B_PWM1_IRQ 19
#define LS1B_PWM2_IRQ 20
#define LS1B_PWM3_IRQ 21
#define LS1B_LPC_IRQ 22
#define LS1B_EHCI_IRQ 32
#define LS1B_OHCI_IRQ 33
#define LS1B_GMAC1_IRQ 34
#define LS1B_GMAC2_IRQ 35
#define LS1B_SATA_IRQ 36
#define LS1B_GPU_IRQ 37
#define LS1B_PCI_INTA_IRQ 38
#define LS1B_PCI_INTB_IRQ 39
#define LS1B_PCI_INTC_IRQ 40
#define LS1B_PCI_INTD_IRQ 41
#define LS1B_GPIO_IRQ 64
#define LS1B_GPIO_FIRST_IRQ 64
#define LS1B_GPIO_IRQ_COUNT 96
#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
#define INT_PCI_INTA (1<<6)
#define INT_PCI_INTB (1<<7)
#define INT_PCI_INTC (1<<8)
#define INT_PCI_INTD (1<<9)
#define LS1B_LAST_IRQ 159
#define MIPS_CPU_TIMER_IRQ 167
#define LS1B_INTREG_BASE 0xbfd01040
#define LS1B_DMA_IRQ_BASE 168
#define LS1B_DMA_IRQ_COUNT 16
struct ls1b_intc_regs
{
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
};
struct ls1b_cop_global_regs
{
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
} ;
struct ls1b_cop_channel_regs
{
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
} ;
struct ls1b_cop_regs
{
struct ls1b_cop_global_regs global;
struct ls1b_cop_channel_regs chan[8][2];
} ;
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
/* Watch Dog registers */
#define WDT_EN __REG32(WDT_BASE + 0x00)
#define WDT_SET __REG32(WDT_BASE + 0x04)
#define WDT_TIMER __REG32(WDT_BASE + 0x08)
#define PLL_FREQ __REG32(0xbfe78030)
#define PLL_DIV_PARAM __REG32(0xbfe78034)
#endif

82
libcpu/mips/loongson_1b/mipscfg.c
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@@ -1,82 +0,0 @@
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}

138
libcpu/mips/loongson_1b/start_gcc.S
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@@ -1,138 +0,0 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
* 2019-07-19 Zhou Yanjie clean up code
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include "../common/mips_def.h"
#include "../common/stackframe.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
and t0, 0xfffffffe # By default it will be disabled.
mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
nop
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder

14
libcpu/mips/loongson_1c/SConscript
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@@ -1,14 +0,0 @@
# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
ASFLAGS = ''
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
Return('group')

233
libcpu/mips/loongson_1c/cache.c
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@@ -1,233 +0,0 @@
/*
* File : cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
* 2015-07-08 chinesebear modified for loongson 1c
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
#define PRID_LS1C 0x4220
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Ls1c(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
extern void enable_cpu_cache(void);
typedef struct cacheinfo_t
{
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t
{
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu(void)
{
unsigned int cpu_id;
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_LS1C:
rt_kprintf("CPU:Loongson 1C\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
break;
default:
rt_kprintf("Unknown CPU type, system halted!\n");
while (1)
{
;
}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config1 = read_c0_config1();
unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
if ((icache_line_size = ((config1 >> 19) & 7)))
icache_line_size = 2 << icache_line_size;
else
icache_line_size = icache_line_size;
icache_sets = 64 << ((config1 >> 22) & 7);
icache_ways = 1 + ((config1 >> 16) & 7);
icache_size = icache_sets * icache_ways * icache_line_size;
if ((dcache_line_size = ((config1 >> 10) & 7)))
dcache_line_size = 2 << dcache_line_size;
else
dcache_line_size = dcache_line_size;
dcache_sets = 64 << ((config1 >> 13) & 7);
dcache_ways = 1 + ((config1 >> 7) & 7);
dcache_size = dcache_sets * dcache_ways * dcache_line_size;
rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = icache_line_size;
pcacheinfo->dcacheline_size = dcache_line_size;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
Invalidate_Dcache_Fill_Ls1c(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}

163
libcpu/mips/loongson_1c/context_gcc.S
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@@ -1,163 +0,0 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
* 2019-07-19 Zhou Yanjie clean up code
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include "../common/mips_def.h"
#include "../common/stackframe.h"
#include "stackframe_fpu.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
ori a0, 0x00000800
mtc0 a0, CP0_STATUS
ehb
mfc0 v0, CP0_CAUSE
ehb
or v1, v0, 0x800000 //EBASE + 0x200
mtc0 v1, CP0_CAUSE
ehb
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
SAVE_FPU
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_FPU
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_FPU
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
SAVE_FPU
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_FPU
RESTORE_ALL_AND_RET
.set reorder

166
libcpu/mips/loongson_1c/cpuport.c
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@@ -1,166 +0,0 @@
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
* 2015-07-06 chinesebear modified for loongson 1c
*/
#include <rtthread.h>
#include "ls1c.h"
register rt_uint32_t $GP __asm__ ("$28");
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WDT_SET = 0x01; /* watch dog start */
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
static rt_uint32_t g_gp = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
g_gp = $GP;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) g_gp; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set push \n" \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set pop \n" \
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
#if defined(CONFIG_CPU_LOONGSON2)
#define Hit_Invalidate_I 0x00
#else
#define Hit_Invalidate_I 0x10
#endif
#define Hit_Invalidate_D 0x11
#define CONFIG_SYS_CACHELINE_SIZE 32
#define Hit_Writeback_Inv_D 0x15
void flush_cache(unsigned long start_addr, unsigned long size)
{
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
unsigned long addr = start_addr & ~(lsize - 1);
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
while (1) {
cache_op(Hit_Writeback_Inv_D, addr);
cache_op(Hit_Invalidate_I, addr);
if (addr == aend)
break;
addr += lsize;
}
}
/*@}*/

91
libcpu/mips/loongson_1c/exception.c
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@@ -1,91 +0,0 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Loongson
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/

226
libcpu/mips/loongson_1c/interrupt.c
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@@ -1,226 +0,0 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
* 2013-03-29 aozima Modify the interrupt interface implementations.
* 2015-07-06 chinesebear modified for loongson 1c
*/
#include <rtthread.h>
#include <rthw.h>
#include "ls1c.h"
#include "ls1c_public.h"
#define MAX_INTR (LS1C_NR_IRQS)
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static struct rt_irq_desc irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
static struct ls1c_intc_regs volatile *ls1c_hw0_icregs
= (struct ls1c_intc_regs volatile *)(LS1C_INTREG_BASE);
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
static void rt_hw_interrupt_handler(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t idx;
rt_int32_t i;
rt_uint32_t c0_status = 0;
// 设置协处理器0的状态寄存器SR的IM7-2，允许中断
c0_status = read_c0_status();
c0_status |= 0xFC00;
write_c0_status(c0_status);
// 龙芯1c的中断分为五组
for (i=0; i<5; i++)
{
/* disable */
(ls1c_hw0_icregs+i)->int_en = 0x0;
/* pci active low */
(ls1c_hw0_icregs+i)->int_pol = -1; //must be done here 20110802 lgnq
/* make all interrupts level triggered */
(ls1c_hw0_icregs+i)->int_edge = 0x00000000;
/* mask all interrupts */
(ls1c_hw0_icregs+i)->int_clr = 0xffffffff;
}
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
for (idx = 0; idx < MAX_INTR; idx ++)
{
irq_handle_table[idx].handler = rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
(ls1c_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
(ls1c_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector >= 0 && vector < MAX_INTR)
{
old_handler = irq_handle_table[vector].handler;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
irq_handle_table[vector].handler = handler;
irq_handle_table[vector].param = param;
}
return old_handler;
}
/**
* 执行中断处理函数
* @IRQn 中断号
*/
void ls1c_do_IRQ(int IRQn)
{
rt_isr_handler_t irq_func;
void *param;
// 找到中断处理函数
irq_func = irq_handle_table[IRQn].handler;
param = irq_handle_table[IRQn].param;
// 执行中断处理函数
irq_func(IRQn, param);
#ifdef RT_USING_INTERRUPT_INFO
irq_handle_table[IRQn].counter++;
#endif
return ;
}
void ls1c_irq_dispatch(int n)
{
rt_uint32_t intstatus, irq;
/* Receive interrupt signal, compute the irq */
intstatus = (ls1c_hw0_icregs+n)->int_isr & (ls1c_hw0_icregs+n)->int_en;
if (0 == intstatus)
return ;
// 执行中断处理函数
irq = ls1c_ffs(intstatus) - 1;
ls1c_do_IRQ((n<<5) + irq);
/* ack interrupt */
(ls1c_hw0_icregs+n)->int_clr |= (1 << irq);
return ;
}
void rt_interrupt_dispatch(void *ptreg)
{
int irq;
void *param;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
rt_uint32_t c0_cause;
volatile rt_uint32_t cause_im;
volatile rt_uint32_t status_im;
rt_uint32_t pending_im;
/* check os timer */
c0_status = read_c0_status();
c0_cause = read_c0_cause();
cause_im = c0_cause & ST0_IM;
status_im = c0_status & ST0_IM;
pending_im = cause_im & status_im;
if (pending_im & CAUSEF_IP7)
{
rt_hw_timer_handler();
}
else if (pending_im & CAUSEF_IP2)
{
ls1c_irq_dispatch(0);
}
else if (pending_im & CAUSEF_IP3)
{
ls1c_irq_dispatch(1);
}
else if (pending_im & CAUSEF_IP4)
{
ls1c_irq_dispatch(2);
}
else if (pending_im & CAUSEF_IP5)
{
ls1c_irq_dispatch(3);
}
else if (pending_im & CAUSEF_IP6)
{
ls1c_irq_dispatch(4);
}
}
/*@}*/

155
libcpu/mips/loongson_1c/ls1c.h
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@@ -1,155 +0,0 @@
/*
* File : ls1c.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
* 2015-07-06 chinesebear modified for loongson 1c
*/
#ifndef __LS1C_H__
#define __LS1C_H__
#include "../common/mipsregs.h"
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
//#define LS1C_UART0_IRQ 3 // linux中是3，v1.4版本的1c手册中是2，暂屏蔽，待确认
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
#define LS1C_CAN1_IRQ 7
#define LS1C_SPI0_IRQ 8
#define LS1C_SPI1_IRQ 9
#define LS1C_AC97_IRQ 10
#define LS1C_MS_IRQ 11
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
#define LS1C_DMA2_IRQ 15
#define LS1C_NAND_IRQ 16
#define LS1C_PWM0_IRQ 17
#define LS1C_PWM1_IRQ 18
#define LS1C_PWM2_IRQ 19
#define LS1C_PWM3_IRQ 20
#define LS1C_RTC_INT0_IRQ 21
#define LS1C_RTC_INT1_IRQ 22
#define LS1C_RTC_INT2_IRQ 23
#define LS1C_UART3_IRQ 29
#define LS1C_ADC_IRQ 30
#define LS1C_SDIO_IRQ 31
#define LS1C_EHCI_IRQ (32+0)
#define LS1C_OHCI_IRQ (32+1)
#define LS1C_OTG_IRQ (32+2)
#define LS1C_MAC_IRQ (32+3)
#define LS1C_CAM_IRQ (32+4)
#define LS1C_UART4_IRQ (32+5)
#define LS1C_UART5_IRQ (32+6)
#define LS1C_UART6_IRQ (32+7)
#define LS1C_UART7_IRQ (32+8)
#define LS1C_UART8_IRQ (32+9)
#define LS1C_UART9_IRQ (32+13)
#define LS1C_UART10_IRQ (32+14)
#define LS1C_UART11_IRQ (32+15)
#define LS1C_I2C2_IRQ (32+17)
#define LS1C_I2C1_IRQ (32+18)
#define LS1C_I2C0_IRQ (32+19)
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_FIRST_IRQ 64
#define LS1C_GPIO_IRQ_COUNT 96
#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
#define LS1C_LAST_IRQ 159
#define LS1C_INTREG_BASE 0xbfd01040
// 龙芯1c的中断分为五组，每组32个
#define LS1C_NR_IRQS (32*5)
// GPIO编号和中断号之间的互相转换
#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn))
#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ)
struct ls1c_intc_regs
{
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
};
struct ls1c_cop_global_regs
{
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
} ;
struct ls1c_cop_channel_regs
{
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
} ;
struct ls1c_cop_regs
{
struct ls1c_cop_global_regs global;
struct ls1c_cop_channel_regs chan[8][2];
} ;
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
/* Watch Dog registers */
#define WDT_EN __REG32(WDT_BASE + 0x00)
#define WDT_SET __REG32(WDT_BASE + 0x08)
#define WDT_TIMER __REG32(WDT_BASE + 0x04)
#define PLL_FREQ __REG32(0xbfe78030)
#define PLL_DIV_PARAM __REG32(0xbfe78034)
#endif

82
libcpu/mips/loongson_1c/mipscfg.c
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@@ -1,82 +0,0 @@
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}

85
libcpu/mips/loongson_1c/sdram_cfg.h
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@@ -1,85 +0,0 @@
#ifndef __OPENLOONGSON_SDRAM_CFG_H
#define __OPENLOONGSON_SDRAM_CFG_H
//#define SD_FREQ (6 * PLL_M) / (2 * SDRAM_PARAM_DIV_NUM)
#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
/* 颗粒行数 */
#define ROW_1K 0x7
#define ROW_2K 0x0
#define ROW_4K 0x1
#define ROW_8K 0x2
#define ROW_16K 0x3
/* 颗粒列数 */
#define COL_256 0x7
#define COL_512 0x0
#define COL_1K 0x1
#define COL_2K 0x2
#define COL_4K 0x3
/* 颗粒位宽 */
#define WIDTH_8 0x0
#define WIDTH_16 0x1
#define WIDTH_32 0x2
#define TRCD 3
#define TCL 3
#define TRP 3
#define TRFC 8
#define TRAS 6
#define TREF 0x818
#define TWR 2
#define DEF_SEL 0x1
#define DEF_SEL_N 0x0
#define HANG_UP 0x1
#define HANG_UP_N 0x0
#define CFG_VALID 0x1
#if 0
// 白菜板8MB
/*
以型号为IS42S16400的SDRAM为例，
物理参数为，
容量：8MB
位宽：16位
列宽：8位，即2的8次方，即256
行宽：12位，即2的12次方，即4K
所以，
颗粒的位宽=WIDTH_16
颗粒的列数=COL_256
颗粒的行数=ROW_4K
再结合宏SD_PARA0和芯片手册中寄存器SD_CONFIG，相信一看就能明白
替换宏SD_PARA0中的行宽、列宽和位宽
*/
#define SDRAM_WIDTH (WIDTH_16)
#define SDRAM_COL (COL_256)
#define SDRAM_ROW (ROW_4K)
#else
// 智龙32MByte
#define SDRAM_WIDTH (WIDTH_16)
#define SDRAM_COL (COL_512)
#define SDRAM_ROW (ROW_8K)
#endif
#define SD_PARA0 (0x7f<<25 | \
(TRAS << 21) | \
(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
SDRAM_ROW)
#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#endif

98
libcpu/mips/loongson_1c/stackframe_fpu.h
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@@ -1,98 +0,0 @@
/*
* ls1c FPU's stackframe
* 最开始本想，将代码加入到stackframe.h中的SAVE_ALL, RESTORE_ALL和RESTORE_ALL_AND_RET中，
* 但考虑到源文件"stackframe.h"位于目录"libcpu\mips\common"内，怕影响到其它mips cpu
* 所以，另外新建本源文件
*/
#ifndef __OPENLOONGSON_STACKFRAME_FPU_H
#define __OPENLOONGSON_STACKFRAME_FPU_H
#include "../common/asm.h"
#include "../common/mipsregs.h"
#include "../common/stackframe.h"
#define PT_FPU_R0 (0)
#define PT_FPU_R2 ((PT_FPU_R0) + 2*LONGSIZE)
#define PT_FPU_R4 ((PT_FPU_R2) + 2*LONGSIZE)
#define PT_FPU_R6 ((PT_FPU_R4) + 2*LONGSIZE)
#define PT_FPU_R8 ((PT_FPU_R6) + 2*LONGSIZE)
#define PT_FPU_R10 ((PT_FPU_R8) + 2*LONGSIZE)
#define PT_FPU_R12 ((PT_FPU_R10) + 2*LONGSIZE)
#define PT_FPU_R14 ((PT_FPU_R12) + 2*LONGSIZE)
#define PT_FPU_R16 ((PT_FPU_R14) + 2*LONGSIZE)
#define PT_FPU_R18 ((PT_FPU_R16) + 2*LONGSIZE)
#define PT_FPU_R20 ((PT_FPU_R18) + 2*LONGSIZE)
#define PT_FPU_R22 ((PT_FPU_R20) + 2*LONGSIZE)
#define PT_FPU_R24 ((PT_FPU_R22) + 2*LONGSIZE)
#define PT_FPU_R26 ((PT_FPU_R24) + 2*LONGSIZE)
#define PT_FPU_R28 ((PT_FPU_R26) + 2*LONGSIZE)
#define PT_FPU_R30 ((PT_FPU_R28) + 2*LONGSIZE)
#define PT_FPU_SIZE ((((PT_FPU_R30) + 2*LONGSIZE) + (2*PTRSIZE-1)) & ~(2*PTRSIZE-1))
.macro SAVE_FPU
.set push
.set noreorder
#ifdef RT_USING_FPU
move k1, sp /* 保存现场 */
and k0, k1, 0xFFFFFFF8 /* 8字节对齐 */
PTR_SUBU sp, k0, PT_FPU_SIZE /* 计算栈底 */
s.d $f0, PT_FPU_R0(sp)
s.d $f2, PT_FPU_R2(sp)
s.d $f4, PT_FPU_R4(sp)
s.d $f6, PT_FPU_R6(sp)
s.d $f8, PT_FPU_R8(sp)
s.d $f10, PT_FPU_R10(sp)
s.d $f12, PT_FPU_R12(sp)
s.d $f14, PT_FPU_R14(sp)
s.d $f16, PT_FPU_R16(sp)
s.d $f18, PT_FPU_R18(sp)
s.d $f20, PT_FPU_R20(sp)
s.d $f22, PT_FPU_R22(sp)
s.d $f24, PT_FPU_R24(sp)
s.d $f26, PT_FPU_R26(sp)
s.d $f28, PT_FPU_R28(sp)
s.d $f30, PT_FPU_R30(sp)
move sp, k1 /* 恢复现场 */
#endif
.set reorder
.set pop
.endm
.macro RESTORE_FPU
.set push
.set noreorder
#ifdef RT_USING_FPU
move k1, sp /* 保存现场 */
and k0, k1, 0xFFFFFFF8 /* 8字节对齐 */
PTR_SUBU sp, k0, PT_FPU_SIZE /* 计算栈底*/
l.d $f0, PT_FPU_R0(sp)
l.d $f2, PT_FPU_R2(sp)
l.d $f4, PT_FPU_R4(sp)
l.d $f6, PT_FPU_R6(sp)
l.d $f8, PT_FPU_R8(sp)
l.d $f10, PT_FPU_R10(sp)
l.d $f12, PT_FPU_R12(sp)
l.d $f14, PT_FPU_R14(sp)
l.d $f16, PT_FPU_R16(sp)
l.d $f18, PT_FPU_R18(sp)
l.d $f20, PT_FPU_R20(sp)
l.d $f22, PT_FPU_R22(sp)
l.d $f24, PT_FPU_R24(sp)
l.d $f26, PT_FPU_R26(sp)
l.d $f28, PT_FPU_R28(sp)
l.d $f30, PT_FPU_R30(sp)
move sp, k1 /* 恢复现场 */
#endif
.set reorder
.set pop
.endm
#endif

530
libcpu/mips/loongson_1c/start_gcc.S
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