mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-23 12:15:32 +08:00
Import beaglebone porting
This commit is contained in:
bernard
@@ -0,0 +1,14 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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cwd = str(Dir('#'))
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,29 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-beaglebone.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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# make a building
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DoBuilding(TARGET, objs)
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@@ -0,0 +1,11 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'applications')
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,28 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2012-11-20 Bernard the first version
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*/
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#include <stdlib.h>
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#include <rtthread.h>
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#include <components.h>
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int rt_application_init()
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{
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/* do component initialization */
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rt_components_init();
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#ifdef RT_USING_NEWLIB
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libc_system_init(RT_CONSOLE_DEVICE_NAME);
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#endif
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return 0;
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}
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@@ -0,0 +1,171 @@
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2012-11-20 Bernard the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <components.h>
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#include "board.h"
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#include <interrupt.h>
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#ifdef RT_USING_VMM
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#include <vmm.h>
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static rt_uint32_t DMTIMER = 0;
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#define TIMER_HW_BASE (DMTIMER)
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#else
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#define TIMER_HW_BASE AM33XX_DMTIMER_7_REGS
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#endif
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#define DMTIMER_TCLR_AR (0x00000002u)
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#define DMTIMER_TCLR_CE (0x00000040u)
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#define DMTIMER_TCLR_PRE (0x00000020u)
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#define DMTIMER_TCLR_ST (0x00000001u)
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#define DMTIMER_IRQENABLE_SET_OVF_EN_FLAG (0x00000002u)
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#define DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG (0x00000002u)
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#define CM_DPLL_CLKSEL_CLK_CLKSEL (0x00000003u)
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#define CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3 (0x2u)
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#define CM_PER_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define CM_PER_CLKCTRL_MODULEMODE (0x00000003u)
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#define CM_PER_CLKCTRL_IDLEST (0x00030000u)
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#define CM_PER_CLKCTRL_IDLEST_FUNC (0x0u)
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#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
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#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x00004000u)
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#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (1<<13)
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static void rt_hw_timer_isr(int vector, void* param)
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{
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rt_tick_increase();
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DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
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}
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static void timer_clk_init(void)
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{
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unsigned long prcm_base;
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#ifdef RT_USING_VMM
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prcm_base = vmm_find_iomap("PRCM");
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#else
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prcm_base = AM33XX_PRCM_REGS;
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#endif
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/* software forced wakeup */
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CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
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/* Waiting for the L4LS clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
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;
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/* Select the clock source for the Timer2 instance. */
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CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
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/* 32k clock source */
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CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
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while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
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CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
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/* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
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CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
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/* Waiting for MODULEMODE field to reflect the written value. */
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while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
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CM_PER_CLKCTRL_MODULEMODE_ENABLE);
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/*
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* Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register
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* for the module is fully functional.
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*/
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while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
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CM_PER_CLKCTRL_IDLEST_FUNC);
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/* Waiting for the L4LS clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
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/* Waiting for the TIMER7 clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
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}
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int rt_hw_timer_init(void)
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{
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rt_uint32_t counter;
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#ifdef RT_USING_VMM
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DMTIMER = vmm_find_iomap("TIMER7");
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#endif
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timer_clk_init();
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/* soft reset the timer */
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DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
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while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1)
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;
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/* calculate count */
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counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
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/* set initial count */
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DMTIMER_TCRR(TIMER_HW_BASE) = counter;
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/* set reload count */
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DMTIMER_TLDR(TIMER_HW_BASE) = counter;
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/* set mode: auto reload */
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DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
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/* interrupt enable for match */
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DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
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DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
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rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_control(TINT7, 0, 0);
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rt_hw_interrupt_umask(TINT7);
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while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
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;
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/* start timer */
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DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
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while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
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;
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_timer_init);
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/**
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* This function will initialize beaglebone board
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*/
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void rt_hw_board_init(void)
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{
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rt_components_board_init();
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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}
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void rt_hw_cpu_reset(void)
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{
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unsigned long prcm_base;
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#ifdef RT_USING_VMM
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prcm_base = vmm_find_iomap("PRCM");
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#else
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prcm_base = AM33XX_PRCM_REGS;
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#endif
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REG32(PRM_DEVICE(prcm_base)) = 0x1;
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RT_ASSERT(0);
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}
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FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);
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FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, __cmd_reboot, reboot the cpu);
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@@ -0,0 +1,32 @@
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/*
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* File : board.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2013, RT-Thread Development Team
|
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*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-06 Bernard the first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <am33xx.h>
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#if defined(__CC_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
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||||
#elif defined(__GNUC__)
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||||
extern int __bss_end;
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#define HEAP_BEGIN ((void*)&__bss_end)
|
||||
#endif
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||||
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#define HEAP_END (void*)0x90000000
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||||
void rt_hw_board_init(void);
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#endif
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@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* File : startup.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-12-05 Bernard the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <board.h>
|
||||
|
||||
extern int rt_application_init(void);
|
||||
|
||||
/**
|
||||
* This function will startup RT-Thread RTOS.
|
||||
*/
|
||||
void rtthread_startup(void)
|
||||
{
|
||||
/* initialzie hardware interrupt */
|
||||
rt_hw_interrupt_init();
|
||||
|
||||
/* initialize board */
|
||||
rt_hw_board_init();
|
||||
/* show RT-Thread version */
|
||||
rt_show_version();
|
||||
|
||||
/* initialize memory system */
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init(HEAP_BEGIN, HEAP_END);
|
||||
#endif
|
||||
|
||||
/* initialize scheduler system */
|
||||
rt_system_scheduler_init();
|
||||
|
||||
/* initialize soft timer thread */
|
||||
rt_system_timer_thread_init();
|
||||
|
||||
/* initialize application */
|
||||
rt_application_init();
|
||||
|
||||
/* initialize idle thread */
|
||||
rt_thread_idle_init();
|
||||
|
||||
/* start scheduler */
|
||||
rt_system_scheduler_start();
|
||||
|
||||
/* never reach here */
|
||||
return ;
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* disable interrupt first */
|
||||
rt_hw_interrupt_disable();
|
||||
|
||||
/* invoke rtthread_startup */
|
||||
rtthread_startup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,91 @@
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80200000;
|
||||
|
||||
__text_start = .;
|
||||
.text :
|
||||
{
|
||||
*(.vectors)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for modules */
|
||||
. = ALIGN(4);
|
||||
__rtmsymtab_start = .;
|
||||
KEEP(*(RTMSymTab))
|
||||
__rtmsymtab_end = .;
|
||||
|
||||
/* section information for initialization */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
} =0
|
||||
__text_end = .;
|
||||
|
||||
__rodata_start = .;
|
||||
.rodata : { *(.rodata) *(.rodata.*) }
|
||||
__rodata_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.ctors :
|
||||
{
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*(.ctors))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
}
|
||||
|
||||
.dtors :
|
||||
{
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
}
|
||||
|
||||
__data_start = .;
|
||||
. = ALIGN(4);
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
}
|
||||
__data_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = __data_end;
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
_end = .;
|
||||
}
|
||||
@@ -0,0 +1,22 @@
|
||||
import copy
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
|
||||
# remove no need file.
|
||||
if GetDepend('RT_USING_LWIP') == False:
|
||||
src_need_remove = ['dm9000.c'] # need remove file list.
|
||||
SrcRemove(src, src_need_remove)
|
||||
|
||||
if GetDepend('RT_USING_DFS') == False:
|
||||
src_need_remove = ['sd.c'] # need remove file list.
|
||||
SrcRemove(src, src_need_remove)
|
||||
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,281 @@
|
||||
/*
|
||||
* File : serial.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-06 Bernard the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <am33xx.h>
|
||||
#include <interrupt.h>
|
||||
#include "serial.h"
|
||||
#include "serial_reg.h"
|
||||
|
||||
struct am33xx_uart
|
||||
{
|
||||
unsigned long base;
|
||||
int irq;
|
||||
};
|
||||
|
||||
static void am33xx_uart_isr(int irqno, void* param)
|
||||
{
|
||||
rt_uint32_t iir;
|
||||
struct am33xx_uart* uart;
|
||||
struct rt_serial_device *serial;
|
||||
|
||||
serial = (struct rt_serial_device*)param;
|
||||
uart = (struct am33xx_uart *)serial->parent.user_data;
|
||||
|
||||
iir = UART_IIR_REG(uart->base);
|
||||
|
||||
if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
|
||||
{
|
||||
rt_hw_serial_isr(serial);
|
||||
}
|
||||
}
|
||||
|
||||
#define NOT_IMPLEMENTED() RT_ASSERT(0)
|
||||
|
||||
static rt_err_t am33xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct am33xx_uart* uart;
|
||||
unsigned long base;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct am33xx_uart *)serial->parent.user_data;
|
||||
RT_ASSERT(uart);
|
||||
base = uart->base;
|
||||
|
||||
#define __LCR UART_LCR_REG(base)
|
||||
|
||||
if (cfg->data_bits == DATA_BITS_8)
|
||||
__LCR |= 3;
|
||||
else
|
||||
NOT_IMPLEMENTED();
|
||||
|
||||
if (cfg->stop_bits == STOP_BITS_1)
|
||||
__LCR &= ~(1<<2);
|
||||
else
|
||||
__LCR |= (1<<2);
|
||||
|
||||
if (cfg->parity == PARITY_NONE)
|
||||
__LCR &= ~(1<<3);
|
||||
else
|
||||
__LCR |= (1<<3);
|
||||
|
||||
__LCR |= (1<<7);
|
||||
if (cfg->baud_rate == BAUD_RATE_115200)
|
||||
{
|
||||
UART_DLL_REG(base) = 26;
|
||||
UART_DLH_REG(base) = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
NOT_IMPLEMENTED();
|
||||
}
|
||||
__LCR &= ~(1<<7);
|
||||
|
||||
UART_MDR1_REG(base) = 0;
|
||||
UART_MDR2_REG(base) = 0;
|
||||
|
||||
#undef __LCR
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t am33xx_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct am33xx_uart* uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct am33xx_uart *)serial->parent.user_data;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
rt_hw_interrupt_mask(uart->irq);
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
rt_hw_interrupt_umask(uart->irq);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int printkc(char c)
|
||||
{
|
||||
int base = 0xf9e09000;
|
||||
|
||||
while (!(UART_LSR_REG(base) & 0x20));
|
||||
UART_THR_REG(base) = c;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int am33xx_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct am33xx_uart* uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct am33xx_uart *)serial->parent.user_data;
|
||||
|
||||
while (!(UART_LSR_REG(uart->base) & 0x20));
|
||||
UART_THR_REG(uart->base) = c;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int am33xx_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch;
|
||||
struct am33xx_uart* uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct am33xx_uart *)serial->parent.user_data;
|
||||
|
||||
ch = -1;
|
||||
if (UART_LSR_REG(uart->base) & 0x01)
|
||||
{
|
||||
ch = UART_RHR_REG(uart->base) & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops am33xx_uart_ops =
|
||||
{
|
||||
am33xx_configure,
|
||||
am33xx_control,
|
||||
am33xx_putc,
|
||||
am33xx_getc,
|
||||
};
|
||||
|
||||
/* UART1 device driver structure */
|
||||
struct serial_ringbuffer uart1_int_rx;
|
||||
struct am33xx_uart uart1 =
|
||||
{
|
||||
UART1_BASE,
|
||||
UART1_INT,
|
||||
};
|
||||
struct rt_serial_device serial1;
|
||||
|
||||
#define write_reg(base, value) *(int*)(base) = value
|
||||
#define read_reg(base) *(int*)(base)
|
||||
|
||||
#define PRM_PER_INTRANSLATION (1 << 20)
|
||||
#define PRM_PER_POWSTATEOFF (0)
|
||||
#define PRM_PER_PERMEMSTATEOFF (0)
|
||||
|
||||
static void poweron_per_domain(void)
|
||||
{
|
||||
unsigned long prcm_base;
|
||||
unsigned long prm_state;
|
||||
|
||||
prcm_base = AM33XX_PRCM_REGS;
|
||||
|
||||
/* wait for ongoing translations */
|
||||
for (prm_state = PRM_PER_PWRSTST_REG(prcm_base);
|
||||
prm_state & PRM_PER_INTRANSLATION;
|
||||
prm_state = PRM_PER_PWRSTST_REG(prcm_base))
|
||||
;
|
||||
|
||||
/* check power state */
|
||||
if ((prm_state & 0x03) == PRM_PER_POWSTATEOFF)
|
||||
/* power on PER domain */
|
||||
PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3;
|
||||
|
||||
/* check per mem state */
|
||||
if ((prm_state & 0x03) == PRM_PER_PERMEMSTATEOFF)
|
||||
/* power on PER domain */
|
||||
PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3 << 25;
|
||||
|
||||
while (PRM_PER_PWRSTST_REG(prcm_base) & PRM_PER_INTRANSLATION)
|
||||
;
|
||||
}
|
||||
|
||||
static void start_uart_clk(void)
|
||||
{
|
||||
unsigned long prcm_base;
|
||||
|
||||
prcm_base = AM33XX_PRCM_REGS;
|
||||
|
||||
/* software forced wakeup */
|
||||
CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
|
||||
|
||||
/* Waiting for the L4LS clock */
|
||||
while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
|
||||
;
|
||||
|
||||
/* enable uart1 */
|
||||
CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2;
|
||||
|
||||
/* wait for uart1 clk */
|
||||
while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
|
||||
;
|
||||
/* Waiting for the L4LS UART clock */
|
||||
while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10)))
|
||||
;
|
||||
}
|
||||
|
||||
static void config_pinmux(void)
|
||||
{
|
||||
unsigned long ctlm_base;
|
||||
|
||||
ctlm_base = AM33XX_CTLM_REGS;
|
||||
|
||||
/* make sure the pin mux is OK for uart */
|
||||
REG32(ctlm_base + 0x800 + 0x180) = 0x20;
|
||||
REG32(ctlm_base + 0x800 + 0x184) = 0x00;
|
||||
}
|
||||
|
||||
int rt_hw_serial_init(void)
|
||||
{
|
||||
struct am33xx_uart* uart;
|
||||
struct serial_configure config;
|
||||
|
||||
uart = &uart1;
|
||||
uart->base = UART1_BASE;
|
||||
|
||||
poweron_per_domain();
|
||||
start_uart_clk();
|
||||
config_pinmux();
|
||||
|
||||
config.baud_rate = BAUD_RATE_115200;
|
||||
config.bit_order = BIT_ORDER_LSB;
|
||||
config.data_bits = DATA_BITS_8;
|
||||
config.parity = PARITY_NONE;
|
||||
config.stop_bits = STOP_BITS_1;
|
||||
config.invert = NRZ_NORMAL;
|
||||
|
||||
serial1.ops = &am33xx_uart_ops;
|
||||
serial1.int_rx = &uart1_int_rx;
|
||||
serial1.config = config;
|
||||
|
||||
/* enable RX interrupt */
|
||||
UART_IER_REG(uart->base) = 0x01;
|
||||
/* install ISR */
|
||||
rt_hw_interrupt_install(uart->irq, am33xx_uart_isr, &serial1, "uart1");
|
||||
rt_hw_interrupt_control(uart->irq, 0, 0);
|
||||
rt_hw_interrupt_mask(uart->irq);
|
||||
|
||||
/* register UART1 device */
|
||||
rt_hw_serial_register(&serial1, "uart1",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
uart);
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_serial_init);
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* File : serial.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-06 Bernard the first version
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_H__
|
||||
#define __SERIAL_H__
|
||||
|
||||
int rt_hw_serial_init(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,109 @@
|
||||
#ifndef SERIAL_REG_H
|
||||
#define SERIAL_REG_H
|
||||
|
||||
/** @brief Base addresses of UART memory mapped registers */
|
||||
#define UART0_BASE (0x44E09000)
|
||||
#define UART1_BASE (0x48022000)
|
||||
#define UART2_BASE (0x48024000)
|
||||
#define UART3_BASE (0x481A6000)
|
||||
#define UART4_BASE (0x481A8000)
|
||||
#define UART5_BASE (0x481AA000)
|
||||
|
||||
/* UART registers */
|
||||
#define UART_DLL(base) (base + 0x0)
|
||||
#define UART_RHR(base) (base + 0x0)
|
||||
#define UART_THR(base) (base + 0x0)
|
||||
#define UART_DLH(base) (base + 0x4)
|
||||
#define UART_IER(base) (base + 0x4)
|
||||
#define UART_EFR(base) (base + 0x8)
|
||||
#define UART_FCR(base) (base + 0x8)
|
||||
#define UART_IIR(base) (base + 0x8)
|
||||
#define UART_LCR(base) (base + 0xC)
|
||||
#define UART_MCR(base) (base + 0x10)
|
||||
#define UART_XON1_ADDR1(base) (base + 0x10)
|
||||
#define UART_LSR(base) (base + 0x14)
|
||||
#define UART_XON2_ADDR2(base) (base + 0x14)
|
||||
#define UART_MSR(base) (base + 0x18)
|
||||
#define UART_TCR(base) (base + 0x18)
|
||||
#define UART_XOFF1(base) (base + 0x18)
|
||||
#define UART_SPR(base) (base + 0x1C)
|
||||
#define UART_TLR(base) (base + 0x1C)
|
||||
#define UART_XOFF2(base) (base + 0x1C)
|
||||
#define UART_MDR1(base) (base + 0x20)
|
||||
#define UART_MDR2(base) (base + 0x24)
|
||||
#define UART_SFLSR(base) (base + 0x28)
|
||||
#define UART_TXFLL(base) (base + 0x28)
|
||||
#define UART_RESUME(base) (base + 0x2C)
|
||||
#define UART_TXFLH(base) (base + 0x2C)
|
||||
#define UART_RXFLL(base) (base + 0x30)
|
||||
#define UART_SFREGL(base) (base + 0x30)
|
||||
#define UART_RXFLH(base) (base + 0x34)
|
||||
#define UART_SFREGH(base) (base + 0x34)
|
||||
#define UART_BLR(base) (base + 0x38)
|
||||
#define UART_UASR(base) (base + 0x38)
|
||||
#define UART_ACREG(base) (base + 0x3C)
|
||||
#define UART_SCR(base) (base + 0x40)
|
||||
#define UART_SSR(base) (base + 0x44)
|
||||
#define UART_EBLR(base) (base + 0x48)
|
||||
#define UART_MVR(base) (base + 0x50)
|
||||
#define UART_SYSC(base) (base + 0x54)
|
||||
#define UART_SYSS(base) (base + 0x58)
|
||||
#define UART_WER(base) (base + 0x5C)
|
||||
#define UART_CFPS(base) (base + 0x60)
|
||||
#define UART_RXFIFO_LVL(base) (base + 0x64)
|
||||
#define UART_TXFIFO_LVL(base) (base + 0x68)
|
||||
#define UART_IER2(base) (base + 0x6C)
|
||||
#define UART_ISR2(base) (base + 0x70)
|
||||
#define UART_FREQ_SEL(base) (base + 0x74)
|
||||
#define UART_MDR3(base) (base + 0x80)
|
||||
#define UART_TX_DMA_THRESHOLD(base) (base + 0x84)
|
||||
|
||||
#define UART_DLL_REG(base) REG16(UART_DLL(base))
|
||||
#define UART_RHR_REG(base) REG16(UART_RHR(base))
|
||||
#define UART_THR_REG(base) REG16(UART_THR(base))
|
||||
#define UART_DLH_REG(base) REG16(UART_DLH(base))
|
||||
#define UART_IER_REG(base) REG16(UART_IER(base))
|
||||
#define UART_EFR_REG(base) REG16(UART_EFR(base))
|
||||
#define UART_FCR_REG(base) REG16(UART_FCR(base))
|
||||
#define UART_IIR_REG(base) REG16(UART_IIR(base))
|
||||
#define UART_LCR_REG(base) REG16(UART_LCR(base))
|
||||
#define UART_MCR_REG(base) REG16(UART_MCR(base))
|
||||
#define UART_XON1_ADDR1_REG(base) REG16(UART_XON1_ADDR1(base))
|
||||
#define UART_LSR_REG(base) REG16(UART_LSR(base))
|
||||
#define UART_XON2_ADDR2_REG(base) REG16(UART_XON2_ADDR2(base))
|
||||
#define UART_MSR_REG(base) REG16(UART_MSR(base))
|
||||
#define UART_TCR_REG(base) REG16(UART_TCR(base))
|
||||
#define UART_XOFF1_REG(base) REG16(UART_XOFF1(base))
|
||||
#define UART_SPR_REG(base) REG16(UART_SPR(base))
|
||||
#define UART_TLR_REG(base) REG16(UART_TLR(base))
|
||||
#define UART_XOFF2_REG(base) REG16(UART_XOFF2(base))
|
||||
#define UART_MDR1_REG(base) REG16(UART_MDR1(base))
|
||||
#define UART_MDR2_REG(base) REG16(UART_MDR2(base))
|
||||
#define UART_SFLSR_REG(base) REG16(UART_SFLSR(base))
|
||||
#define UART_TXFLL_REG(base) REG16(UART_TXFLL(base))
|
||||
#define UART_RESUME_REG(base) REG16(UART_RESUME(base))
|
||||
#define UART_TXFLH_REG(base) REG16(UART_TXFLH(base))
|
||||
#define UART_RXFLL_REG(base) REG16(UART_RXFLL(base))
|
||||
#define UART_SFREGL_REG(base) REG16(UART_SFREGL(base))
|
||||
#define UART_RXFLH_REG(base) REG16(UART_RXFLH(base))
|
||||
#define UART_SFREGH_REG(base) REG16(UART_SFREGH(base))
|
||||
#define UART_BLR_REG(base) REG16(UART_BLR(base))
|
||||
#define UART_UASR_REG(base) REG16(UART_UASR(base))
|
||||
#define UART_ACREG_REG(base) REG16(UART_ACREG(base))
|
||||
#define UART_SCR_REG(base) REG16(UART_SCR(base))
|
||||
#define UART_SSR_REG(base) REG16(UART_SSR(base))
|
||||
#define UART_EBLR_REG(base) REG16(UART_EBLR(base))
|
||||
#define UART_MVR_REG(base) REG16(UART_MVR(base))
|
||||
#define UART_SYSC_REG(base) REG16(UART_SYSC(base))
|
||||
#define UART_SYSS_REG(base) REG16(UART_SYSS(base))
|
||||
#define UART_WER_REG(base) REG16(UART_WER(base))
|
||||
#define UART_CFPS_REG(base) REG16(UART_CFPS(base))
|
||||
#define UART_RXFIFO_LVL_REG(base) REG16(UART_RXFIFO_LVL(base))
|
||||
#define UART_TXFIFO_LVL_REG(base) REG16(UART_TXFIFO_LVL(base))
|
||||
#define UART_IER2_REG(base) REG16(UART_IER2(base))
|
||||
#define UART_ISR2_REG(base) REG16(UART_ISR2(base))
|
||||
#define UART_FREQ_SEL_REG(base) REG16(UART_FREQ_SEL(base))
|
||||
#define UART_MDR3_REG(base) REG16(UART_MDR3(base))
|
||||
#define UART_TX_DMA_THRESHOLD_REG(base) REG16(UART_TX_DMA_THRESHOLD(base))
|
||||
|
||||
#endif /* end of include guard: SERIAL_REG_H */
|
||||
@@ -0,0 +1,147 @@
|
||||
/* RT-Thread config file */
|
||||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
|
||||
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
|
||||
|
||||
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
|
||||
#define RT_NAME_MAX 6
|
||||
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
|
||||
#define RT_ALIGN_SIZE 4
|
||||
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
|
||||
// <item description="8">8</item>
|
||||
// <item description="32">32</item>
|
||||
// <item description="256">256</item>
|
||||
// </integer>
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
|
||||
#define IDLE_THREAD_STACK_SIZE 512
|
||||
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
|
||||
#define RT_DEBUG
|
||||
//#define RT_DEBUG_SCHEDULER 1
|
||||
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
|
||||
// #define RT_THREAD_DEBUG
|
||||
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
|
||||
//#define RT_USING_OVERFLOW_CHECK
|
||||
// </section>
|
||||
|
||||
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
|
||||
#define RT_USING_HOOK
|
||||
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
|
||||
// #define RT_USING_TIMER_SOFT
|
||||
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
|
||||
#define RT_TIMER_TICK_PER_SECOND 10
|
||||
// </section>
|
||||
|
||||
// <section name="IPC" description="Inter-Thread communication" default="always" >
|
||||
// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
|
||||
#define RT_USING_SEMAPHORE
|
||||
// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
|
||||
#define RT_USING_MUTEX
|
||||
// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
|
||||
#define RT_USING_EVENT
|
||||
// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
|
||||
#define RT_USING_MAILBOX
|
||||
// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
// </section>
|
||||
|
||||
// <section name="MM" description="Memory Management" default="always" >
|
||||
// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
|
||||
#define RT_USING_MEMPOOL
|
||||
// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
|
||||
// #define RT_USING_MEMHEAP
|
||||
// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
|
||||
#define RT_USING_HEAP
|
||||
// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
|
||||
// #define RT_USING_MEMHEAP_AS_HEAP
|
||||
// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
|
||||
#define RT_USING_SMALL_MEM
|
||||
// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
|
||||
// #define RT_USING_SLAB
|
||||
// </section>
|
||||
|
||||
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
|
||||
#define RT_USING_DEVICE
|
||||
// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
|
||||
#define RT_USING_DEVICE_IPC
|
||||
// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
|
||||
#define RT_USING_SERIAL
|
||||
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
|
||||
#define RT_UART_RX_BUFFER_SIZE 64
|
||||
// <bool name=RT_USING_INTERRUPT_INFO description="Using interrupt information description" default="true" />
|
||||
#define RT_USING_INTERRUPT_INFO
|
||||
// </section>
|
||||
|
||||
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
|
||||
#define RT_USING_CONSOLE
|
||||
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
// </section>
|
||||
|
||||
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
|
||||
#define RT_USING_FINSH
|
||||
// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
|
||||
#define FINSH_USING_MSH
|
||||
// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
|
||||
//#define FINSH_USING_MSH_DEFAULT
|
||||
// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
|
||||
#define FINSH_USING_SYMTAB
|
||||
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
// </section>
|
||||
|
||||
// <section name="LIBC" description="C Runtime library setting" default="always" >
|
||||
// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
|
||||
//#define RT_USING_NEWLIB
|
||||
// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
|
||||
#define RT_USING_PTHREADS
|
||||
// </section>
|
||||
|
||||
// <section name="RT_USING_DFS" description="Device file system" default="true" >
|
||||
// #define RT_USING_DFS
|
||||
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
|
||||
// #define DFS_USING_WORKDIR
|
||||
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
|
||||
#define DFS_FILESYSTEMS_MAX 2
|
||||
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
|
||||
#define DFS_FD_MAX 4
|
||||
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
|
||||
#define RT_USING_DFS_ELMFAT
|
||||
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
|
||||
// <item description="LFN1">1</item>
|
||||
// <item description="LFN1">2</item>
|
||||
// </integer>
|
||||
#define RT_DFS_ELM_USE_LFN 1
|
||||
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
|
||||
#define RT_DFS_ELM_MAX_LFN 64
|
||||
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
|
||||
// #define RT_USING_DFS_YAFFS2
|
||||
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
|
||||
// #define RT_USING_DFS_UFFS
|
||||
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
|
||||
// #define RT_USING_DFS_DEVFS
|
||||
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
|
||||
// #define RT_USING_DFS_NFS
|
||||
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
|
||||
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
|
||||
// </section>
|
||||
|
||||
// </RDTConfigurator>
|
||||
|
||||
#define __rt_ffs __builtin_ffs
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,103 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='am335x'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Program Files (x86)\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI\bin'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'C:/Keil'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
print '================ERROR============================'
|
||||
print 'Not support IAR yet!'
|
||||
print '================================================='
|
||||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -Wall -march=armv7-a -mtune=cortex-a8'+\
|
||||
' -ftree-vectorize -ffast-math -mfpu=vfpv3-d16 -mfloat-abi=softfp'
|
||||
#DEVICE = ' '
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-beaglebone.map,-cref,-u,Reset_Handler -T beaglebone_ram.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -Wall'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2 -Wall'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
|
||||
SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --device DARMP'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-beaglebone.map --scatter beaglebone_ram.sct'
|
||||
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = ' --cpu DARMP'
|
||||
|
||||
CFLAGS = ''
|
||||
AFLAGS = ''
|
||||
LFLAGS = ' --config beaglebone_ram.icf'
|
||||
|
||||
EXEC_PATH += '/arm/bin/'
|
||||
RT_USING_MINILIBC = False
|
||||
POST_ACTION = ''
|
||||
@@ -0,0 +1,3 @@
|
||||
mmcinfo
|
||||
fatload mmc 0 0x80200000 rtthread.bin
|
||||
go 0x80200000
|
||||
Reference in New Issue
Block a user