mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-22 03:09:16 +08:00
Merge pull request #3468 from bigmagic123/aarch64_cache_api
Aarch64 cache api
This commit is contained in:
Bernard Xiong
@@ -148,7 +148,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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CONFIG_RT_USING_HWTIMER=y
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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CONFIG_RT_USING_I2C=y
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CONFIG_RT_I2C_DEBUG=y
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CONFIG_RT_USING_I2C_BITOPS=y
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# CONFIG_RT_I2C_BITOPS_DEBUG is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_PWM is not set
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@@ -163,7 +166,12 @@ CONFIG_RT_MMCSD_STACK_SIZE=4096
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CONFIG_RT_MMCSD_THREAD_PREORITY=22
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CONFIG_RT_MMCSD_MAX_PARTITION=16
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CONFIG_RT_SDIO_DEBUG=y
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# CONFIG_RT_USING_SPI is not set
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CONFIG_RT_USING_SPI=y
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# CONFIG_RT_USING_QSPI is not set
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# CONFIG_RT_USING_SPI_MSD is not set
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# CONFIG_RT_USING_SFUD is not set
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# CONFIG_RT_USING_ENC28J60 is not set
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# CONFIG_RT_USING_SPI_WIFI is not set
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CONFIG_RT_USING_WDT=y
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# CONFIG_RT_USING_AUDIO is not set
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# CONFIG_RT_USING_SENSOR is not set
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@@ -420,36 +428,6 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_VT100 is not set
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# CONFIG_PKG_USING_ULAPACK is not set
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# CONFIG_PKG_USING_UKAL is not set
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#
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# Privated Packages of RealThread
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#
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# CONFIG_PKG_USING_CODEC is not set
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# CONFIG_PKG_USING_PLAYER is not set
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# CONFIG_PKG_USING_MPLAYER is not set
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# CONFIG_PKG_USING_PERSIMMON_SRC is not set
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# CONFIG_PKG_USING_JS_PERSIMMON is not set
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# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
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#
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# Network Utilities
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#
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# CONFIG_PKG_USING_WICED is not set
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# CONFIG_PKG_USING_CLOUDSDK is not set
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# CONFIG_PKG_USING_POWER_MANAGER is not set
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# CONFIG_PKG_USING_RT_OTA is not set
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# CONFIG_PKG_USING_RDBD_SRC is not set
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# CONFIG_PKG_USING_RTINSIGHT is not set
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# CONFIG_PKG_USING_SMARTCONFIG is not set
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# CONFIG_PKG_USING_RTX is not set
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# CONFIG_RT_USING_TESTCASE is not set
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# CONFIG_PKG_USING_NGHTTP2 is not set
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# CONFIG_PKG_USING_AVS is not set
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# CONFIG_PKG_USING_JOYLINK is not set
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# CONFIG_PKG_USING_STS is not set
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# CONFIG_PKG_USING_DLMS is not set
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# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
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# CONFIG_PKG_USING_ZBAR is not set
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CONFIG_BCM2836_SOC=y
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# CONFIG_BSP_SUPPORT_FPU is not set
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@@ -468,8 +446,13 @@ CONFIG_BSP_USING_CORETIMER=y
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CONFIG_BSP_USING_SYSTIMER=y
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CONFIG_RT_USING_SYSTIMER1=y
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CONFIG_RT_USING_SYSTIMER3=y
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# CONFIG_BSP_USING_I2C is not set
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# CONFIG_BSP_USING_SPI is not set
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CONFIG_BSP_USING_I2C=y
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# CONFIG_BSP_USING_I2C0 is not set
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CONFIG_BSP_USING_I2C1=y
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CONFIG_BSP_USING_SPI=y
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CONFIG_BSP_USING_SPI0_BUS=y
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CONFIG_BSP_USING_SPI0_DEVICE0=y
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# CONFIG_BSP_USING_SPI0_DEVICE1 is not set
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CONFIG_BSP_USING_WDT=y
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# CONFIG_BSP_USING_RTC is not set
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CONFIG_BSP_USING_SDIO=y
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@@ -63,12 +63,17 @@ menu "Hardware Drivers Config"
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select RT_USING_SPI
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default n
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if BSP_USING_SPI
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config BSP_USING_SPI0
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bool "Enable SPI0"
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if BSP_USING_SPI
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config BSP_USING_SPI0_BUS
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bool "Enable SPI0 BUS"
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default n
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config BSP_USING_SPI1
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bool "Enable SPI1"
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config BSP_USING_SPI0_DEVICE0
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bool "Enable SPI0 DEVICE0"
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select BSP_USING_SPI0_BUS
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default n
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config BSP_USING_SPI0_DEVICE1
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bool "Enable SPI0 DEVICE1"
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select BSP_USING_SPI0_BUS
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default n
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endif
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@@ -100,6 +100,8 @@ void rt_hw_board_init(void)
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armv8_map(0x40000000, 0x40000000, 0x1000, MEM_ATTR_IO);//core timer
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armv8_map(0x3F300000, 0x3F300000, 0x1000, MEM_ATTR_IO);//sdio
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armv8_map(0xc00000, 0xc00000, 0x1000, MEM_ATTR_IO);//mbox
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armv8_map(0x3f804000, 0x3f804000, 0x1000, MEM_ATTR_IO);//i2c0
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armv8_map(0x3f205000, 0x3f205000, 0x1000, MEM_ATTR_IO);//i2c1
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mmu_enable();
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/* initialize hardware interrupt */
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@@ -8,56 +8,104 @@
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* 2019-07-29 zdzn first version
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*/
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#include "raspi.h"
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#include "drv_i2c.h"
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#if defined (BSP_USING_I2C0)
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#define I2C1BUS_NAME "i2c0"
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#endif /*BSP_USING_I2C0*/
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//Maybe redefined
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typedef unsigned long rt_ubase_t;
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typedef rt_ubase_t rt_size_t;
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#if defined (BSP_USING_I2C1)
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#define I2C2BUS_NAME "i2c1"
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#endif /*BSP_USING_I2C1*/
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static int i2c_byte_wait_us = 0;
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#ifdef BSP_USING_I2C0
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static struct raspi_i2c_bus raspi_i2c0 =
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rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag)
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{
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.device_name = I2C1BUS_NAME,
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};
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rt_uint32_t status;
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rt_uint32_t remaining = len;
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rt_uint32_t i = 0;
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rt_uint8_t reason = BCM283X_I2C_REASON_OK;
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static struct raspi_master_config_t raspi_i2c0_cfg =
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/* Clear FIFO */
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BCM283X_BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1);
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/* Clear Status */
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BCM283X_BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
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/* Set Data Length */
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BCM283X_BSC_DLEN(base) = len;
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if (flag)
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{
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/* Start read */
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BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ;
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/* wait for transfer to complete */
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while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
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{
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/* we must empty the FIFO as it is populated and not use any delay */
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while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
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{
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/* Read from FIFO, no barrier */
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buf[i] = BCM283X_BSC_FIFO(base);
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i++;
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remaining--;
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}
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}
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/* transfer has finished - grab any remaining stuff in FIFO */
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while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD))
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{
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/* Read from FIFO, no barrier */
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buf[i] = BCM283X_BSC_FIFO(base);
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i++;
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remaining--;
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}
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}
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else
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{
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/* pre populate FIFO with max buffer */
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while (remaining && (i < BSC_FIFO_SIZE))
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{
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BCM283X_BSC_FIFO(base) = buf[i];
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i++;
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remaining--;
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}
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/* Enable device and start transfer */
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BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST;
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/* Transfer is over when BCM2835_BSC_S_DONE */
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while (!(BCM283X_BSC_S(base) & BSC_S_DONE))
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{
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while (remaining && (BCM283X_BSC_S(base) & BSC_S_TXD))
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{
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/* Write to FIFO */
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BCM283X_BSC_FIFO(base) = buf[i];
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i++;
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remaining--;
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}
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}
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}
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status = BCM283X_BSC_S(base);
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if (status & BSC_S_ERR)
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{
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reason = BCM283X_I2C_REASON_ERROR_NACK;
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}
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else if (status & BSC_S_CLKT)
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{
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reason = BCM283X_I2C_REASON_ERROR_CLKT;
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}
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else if (remaining)
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{
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reason = BCM283X_I2C_REASON_ERROR_DATA;
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}
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BCM283X_BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE);
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return reason;
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}
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struct raspi_i2c_hw_config
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{
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.sdl_pin = BCM_GPIO_PIN_0,
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.scl_pin = BCM_GPIO_PIN_1,
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.sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
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.scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
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.slave_address = 8,
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.bsc_base = (PER_BASE + BCM283X_BSC0_BASE),
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.clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
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rt_uint8_t bsc_num;
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rt_uint8_t sdl_pin;
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rt_uint8_t scl_pin;
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rt_uint8_t sdl_mode;
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rt_uint8_t scl_mode;
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};
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#endif /* RT_USING_HW_I2C1 */
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#ifdef BSP_USING_I2C1
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static struct raspi_i2c_bus raspi_i2c1 =
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{
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.device_name = I2C2BUS_NAME,
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};
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static struct raspi_master_config_t raspi_i2c1_cfg =
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{
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.sdl_pin = BCM_GPIO_PIN_2,
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.scl_pin = BCM_GPIO_PIN_3,
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.sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
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.scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
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.slave_address = 9,
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.bsc_base = (PER_BASE + BCM283X_BSC1_BASE),
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.clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
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};
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#endif /* RT_USING_HW_I2C2 */
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#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
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static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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@@ -70,58 +118,32 @@ static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
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rt_uint32_t,
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rt_uint32_t);
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void i2c_master_init(struct raspi_master_config_t *cfg)
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{
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volatile rt_uint32_t addr;
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rt_uint32_t data;
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bcm283x_gpio_fsel(cfg->sdl_pin, cfg->sdl_pin_mode); /* SDA */
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bcm283x_gpio_fsel(cfg->scl_pin, cfg->scl_pin_mode); /* SCL */
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addr = cfg->bsc_base + BCM283X_BSC_DIV;
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data = bcm283x_peri_read(addr);
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i2c_byte_wait_us = ( data * 1000000 / BCM283X_CORE_CLK_HZ) * 9;
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addr = cfg->bsc_base + BCM283X_BSC_DIV;
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bcm283x_peri_write(addr, cfg->clk_div);
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//update
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i2c_byte_wait_us = (cfg->clk_div * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
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}
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static rt_uint32_t i2c_byte_wait_us = 0;
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static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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volatile rt_uint32_t addr;
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struct raspi_i2c_bus *raspi_i2c;
|
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rt_size_t i;
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rt_uint8_t reason;
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RT_ASSERT(bus != RT_NULL);
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raspi_i2c = (struct raspi_i2c_bus *) bus;
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raspi_i2c->msg = msgs;
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raspi_i2c->msg_ptr = 0;
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raspi_i2c->msg_cnt = num;
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raspi_i2c->dptr = 0;
|
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addr = raspi_i2c->cfg->bsc_base + BCM283X_BSC_A;
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bcm283x_peri_write(addr, msgs->addr);
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volatile rt_base_t base = (volatile rt_base_t)(bus->parent.user_data);
|
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if (bus->addr == 0)
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base = BCM283X_BSC0_BASE;
|
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else
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base = BCM283X_BSC1_BASE;
|
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|
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BCM283X_BSC_A(base) = msgs->addr;
|
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|
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for (i = 0; i < num; i++)
|
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{
|
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if ( raspi_i2c->msg[i].flags & RT_I2C_RD )
|
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{
|
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bcm283x_i2c_read(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
|
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}
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if (msgs[i].flags & RT_I2C_RD)
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reason = i2c_read_or_write(base, msgs->buf, msgs->len, 1);
|
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else
|
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{
|
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bcm283x_i2c_write(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
|
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}
|
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reason = i2c_read_or_write(base, msgs->buf, msgs->len, 0);
|
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}
|
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raspi_i2c->msg = RT_NULL;
|
||||
raspi_i2c->msg_ptr = 0;
|
||||
raspi_i2c->msg_cnt = 0;
|
||||
raspi_i2c->dptr = 0;
|
||||
return i;
|
||||
return (reason == 0)? i : 0;
|
||||
}
|
||||
|
||||
static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
|
||||
@@ -134,7 +156,7 @@ static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
|
||||
rt_uint32_t cmd,
|
||||
rt_uint32_t arg)
|
||||
{
|
||||
return RT_ERROR;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
|
||||
@@ -144,33 +166,72 @@ static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
|
||||
.i2c_bus_control = raspi_i2c_bus_control,
|
||||
};
|
||||
|
||||
static rt_err_t raspi_i2c_configure(struct raspi_i2c_bus *bus, struct raspi_master_config_t *cfg)
|
||||
|
||||
static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg)
|
||||
{
|
||||
RT_ASSERT(bus != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
bus->device.ops = &raspi_i2c_ops;
|
||||
bus->cfg = cfg;
|
||||
volatile rt_uint32_t base = cfg->scl_mode ? BCM283X_BSC1_BASE : BCM283X_BSC0_BASE;
|
||||
|
||||
GPIO_FSEL(cfg->sdl_pin, cfg->sdl_mode); /* SDA */
|
||||
GPIO_FSEL(cfg->scl_pin, cfg->scl_mode); /* SCL */
|
||||
/* use 0xFFFE mask to limit a max value and round down any odd number */
|
||||
rt_uint32_t divider = (BCM283X_CORE_CLK_HZ / 10000) & 0xFFFE;
|
||||
BCM283X_BSC_DIV(base) = (rt_uint16_t) divider;
|
||||
i2c_byte_wait_us = (divider * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
|
||||
|
||||
i2c_master_init(cfg);
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_I2C0)
|
||||
#define I2C0_BUS_NAME "i2c0"
|
||||
static struct raspi_i2c_hw_config hw_device0 =
|
||||
{
|
||||
.bsc_num = 0,
|
||||
.sdl_pin = RPI_GPIO_P1_27,
|
||||
.scl_pin = RPI_GPIO_P1_28,
|
||||
.sdl_mode = BCM283X_GPIO_FSEL_ALT0,
|
||||
.scl_mode = BCM283X_GPIO_FSEL_ALT0,
|
||||
};
|
||||
|
||||
struct rt_i2c_bus_device device0 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.addr = 0,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_I2C1)
|
||||
#define I2C1_BUS_NAME "i2c1"
|
||||
static struct raspi_i2c_hw_config hw_device1 =
|
||||
{
|
||||
.bsc_num = 1,
|
||||
.sdl_pin = RPI_GPIO_P1_03,
|
||||
.scl_pin = RPI_GPIO_P1_05,
|
||||
.sdl_mode = BCM283X_GPIO_FSEL_ALT0,
|
||||
.scl_mode = BCM283X_GPIO_FSEL_ALT0,
|
||||
};
|
||||
struct rt_i2c_bus_device device1 =
|
||||
{
|
||||
.ops = &raspi_i2c_ops,
|
||||
.addr = 1,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
int rt_hw_i2c_init(void)
|
||||
{
|
||||
|
||||
#if defined(BSP_USING_I2C0)
|
||||
raspi_i2c_configure(&raspi_i2c0 , &raspi_i2c0_cfg);
|
||||
rt_i2c_bus_device_register(&raspi_i2c0.device, raspi_i2c0.device_name);
|
||||
#endif /* BSP_USING_I2C1 */
|
||||
raspi_i2c_configure(&hw_device0);
|
||||
rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
|
||||
raspi_i2c_configure(&raspi_i2c1 , &raspi_i2c1_cfg);
|
||||
rt_i2c_bus_device_register(&raspi_i2c1.device, raspi_i2c1.device_name);
|
||||
|
||||
#endif /* BSP_USING_I2C2 */
|
||||
raspi_i2c_configure(&hw_device1);
|
||||
rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -11,10 +11,10 @@
|
||||
#ifndef __DRV_I2C_H__
|
||||
#define __DRV_I2C_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rtthread.h>
|
||||
#include "bcm283x.h"
|
||||
|
||||
#include "board.h"
|
||||
|
||||
struct raspi_master_config_t
|
||||
{
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -12,57 +12,91 @@
|
||||
#define __DRV_SPI_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#include "bcm283x.h"
|
||||
#include <rtdevice.h>
|
||||
#include <drivers/spi.h>
|
||||
#include "raspi.h"
|
||||
|
||||
//#include <drivers/spi.h>
|
||||
#include "board.h"
|
||||
|
||||
#define SPI0_BASE_ADDR (PER_BASE + BCM283X_SPI0_BASE)
|
||||
|
||||
#define SPI_CORE_CLK 250000000U
|
||||
#define SPI_CS 0x00
|
||||
#define SPI_CS_LEN_LONG (1 << 25)
|
||||
#define SPI_CS_DMA_LEN (1 << 24)
|
||||
#define SPI_CS_CSPOL2 (1 << 23)
|
||||
#define SPI_CS_CSPOL1 (1 << 22)
|
||||
#define SPI_CS_CSPOL0 (1 << 21)
|
||||
#define SPI_CS_RXF (1 << 20)
|
||||
#define SPI_CS_RXR (1 << 19)
|
||||
#define SPI_CS_TXD (1 << 18)
|
||||
#define SPI_CS_RXD (1 << 17)
|
||||
#define SPI_CS_DONE (1 << 16)
|
||||
#define SPI_CS_LEN (1 << 13)
|
||||
#define SPI_CS_REN (1 << 12)
|
||||
#define SPI_CS_ADCS (1 << 11)
|
||||
#define SPI_CS_INTR (1 << 10)
|
||||
#define SPI_CS_INTD (1 << 9)
|
||||
#define SPI_CS_DMAEN (1 << 8)
|
||||
#define SPI_CS_TA (1 << 7)
|
||||
#define SPI_CS_CSPOL (1 << 6)
|
||||
#define SPI_CS_CLEAR_RXFIFO (1 << 5)
|
||||
#define SPI_CS_CLEAR_TXFIFO (1 << 4)
|
||||
#define SPI_CS_CPOL (1 << 3)
|
||||
#define SPI_CS_CPHA (1 << 2)
|
||||
#define SPI_CS_MASK 0x3
|
||||
#define SPI_FIFO 0x04
|
||||
#define SPI_CLK 0x08
|
||||
#define SPI_CLK_MASK 0xffff
|
||||
#define SPI_DLEN 0x0c
|
||||
#define SPI_DLEN_MASK 0xffff
|
||||
#define SPI_LTOH 0x10
|
||||
#define SPI_LTOH_MASK 0xf
|
||||
#define SPI_DC 0x14
|
||||
#define SPI_DC_RPANIC_SHIFT 24
|
||||
#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT)
|
||||
#define SPI_DC_RDREQ_SHIFT 16
|
||||
#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT)
|
||||
#define SPI_DC_TPANIC_SHIFT 8
|
||||
#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT)
|
||||
#define SPI_DC_TDREQ_SHIFT 0
|
||||
#define SPI_DC_TDREQ_MASK 0xff
|
||||
static rt_uint8_t raspi_byte_reverse_table[] =
|
||||
{
|
||||
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
|
||||
0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
|
||||
0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
|
||||
0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
|
||||
0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
|
||||
0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
|
||||
0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
|
||||
0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
|
||||
0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
|
||||
0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
|
||||
0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
|
||||
0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
|
||||
0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
|
||||
0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
|
||||
0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
|
||||
0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
|
||||
0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
|
||||
0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
|
||||
0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
|
||||
0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
|
||||
0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
|
||||
0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
|
||||
0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
|
||||
0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
|
||||
0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
|
||||
0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
|
||||
0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
|
||||
0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
|
||||
0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
|
||||
0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
|
||||
0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
|
||||
0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
|
||||
};
|
||||
|
||||
int rt_hw_spi_bus_init(void);
|
||||
#define SPI_CORE_CLK 250000000U
|
||||
#define SPI_CS 0x00
|
||||
#define SPI_CS_LEN_LONG (1 << 25)
|
||||
#define SPI_CS_DMA_LEN (1 << 24)
|
||||
#define SPI_CS_CSPOL2 (1 << 23)
|
||||
#define SPI_CS_CSPOL1 (1 << 22)
|
||||
#define SPI_CS_CSPOL0 (1 << 21)
|
||||
#define SPI_CS_RXF (1 << 20)
|
||||
#define SPI_CS_RXR (1 << 19)
|
||||
#define SPI_CS_TXD (1 << 18)
|
||||
#define SPI_CS_RXD (1 << 17)
|
||||
#define SPI_CS_DONE (1 << 16)
|
||||
#define SPI_CS_LEN (1 << 13)
|
||||
#define SPI_CS_REN (1 << 12)
|
||||
#define SPI_CS_ADCS (1 << 11)
|
||||
#define SPI_CS_INTR (1 << 10)
|
||||
#define SPI_CS_INTD (1 << 9)
|
||||
#define SPI_CS_DMAEN (1 << 8)
|
||||
#define SPI_CS_TA (1 << 7)
|
||||
#define SPI_CS_CSPOL (1 << 6)
|
||||
#define SPI_CS_CLEAR_RXFIFO (1 << 5)
|
||||
#define SPI_CS_CLEAR_TXFIFO (1 << 4)
|
||||
#define SPI_CS_CPOL (1 << 3)
|
||||
#define SPI_CS_CPHA (1 << 2)
|
||||
#define SPI_CS_MASK 0x3
|
||||
#define SPI_FIFO 0x04
|
||||
#define SPI_CLK 0x08
|
||||
#define SPI_CLK_MASK 0xffff
|
||||
#define SPI_DLEN 0x0c
|
||||
#define SPI_DLEN_MASK 0xffff
|
||||
#define SPI_LTOH 0x10
|
||||
#define SPI_LTOH_MASK 0xf
|
||||
#define SPI_DC 0x14
|
||||
#define SPI_DC_RPANIC_SHIFT 24
|
||||
#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT)
|
||||
#define SPI_DC_RDREQ_SHIFT 16
|
||||
#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT)
|
||||
#define SPI_DC_TPANIC_SHIFT 8
|
||||
#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT)
|
||||
#define SPI_DC_TDREQ_SHIFT 0
|
||||
#define SPI_DC_TDREQ_MASK 0xff
|
||||
|
||||
int rt_hw_spi_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -102,6 +102,9 @@
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_HWTIMER
|
||||
#define RT_USING_I2C
|
||||
#define RT_I2C_DEBUG
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_SDIO
|
||||
#define RT_SDIO_STACK_SIZE 2048
|
||||
@@ -110,6 +113,7 @@
|
||||
#define RT_MMCSD_THREAD_PREORITY 22
|
||||
#define RT_MMCSD_MAX_PARTITION 16
|
||||
#define RT_SDIO_DEBUG
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_WDT
|
||||
|
||||
/* Using USB */
|
||||
@@ -179,12 +183,6 @@
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* Privated Packages of RealThread */
|
||||
|
||||
|
||||
/* Network Utilities */
|
||||
|
||||
#define BCM2836_SOC
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
@@ -198,6 +196,11 @@
|
||||
#define BSP_USING_SYSTIMER
|
||||
#define RT_USING_SYSTIMER1
|
||||
#define RT_USING_SYSTIMER3
|
||||
#define BSP_USING_I2C
|
||||
#define BSP_USING_I2C1
|
||||
#define BSP_USING_SPI
|
||||
#define BSP_USING_SPI0_BUS
|
||||
#define BSP_USING_SPI0_DEVICE0
|
||||
#define BSP_USING_WDT
|
||||
#define BSP_USING_SDIO
|
||||
#define BSP_USING_SDIO0
|
||||
|
||||
Reference in New Issue
Block a user