diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h index 80e111fbbe..41c10756a0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h @@ -37,8 +37,8 @@ { \ .Instance = SPI2, \ .bus_name = "spi2", \ - .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ - .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ + .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ + .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \ .dma_rx.Instance = DMA1_Stream3, \ .dma_rx.channel = DMA_CHANNEL_0, \ .dma_rx.dma_irq = DMA1_Stream3_IRQn, \ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c index 6f6aa52796..7e1d81fa07 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c @@ -6,11 +6,12 @@ * Change Logs: * Date Author Notes * 2018-12-05 zylx first version + * 2018-12-12 greedyhao Porting for stm32f7xx */ #include -#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) +// #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) #include "drv_config.h" //#define DRV_DEBUG @@ -126,7 +127,7 @@ static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel) case 17: stm32_channel = ADC_CHANNEL_17; break; -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4) +#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) case 18: stm32_channel = ADC_CHANNEL_18; break; @@ -148,7 +149,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch #if defined(SOC_SERIES_STM32F1) if (channel <= 17) -#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4) +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) if (channel <= 18) #endif { @@ -159,7 +160,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch { #if defined(SOC_SERIES_STM32F1) LOG_E("ADC channel must be between 0 and 17."); -#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4) +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) LOG_E("ADC channel must be between 0 and 18."); #endif return -RT_ERROR; @@ -167,12 +168,12 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch ADC_ChanConf.Rank = 1; #if defined(SOC_SERIES_STM32F1) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5; -#elif defined(SOC_SERIES_STM32F4) +#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES; #elif defined(SOC_SERIES_STM32L4) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; #endif -#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4) +#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) ADC_ChanConf.Offset = 0; #endif #ifdef SOC_SERIES_STM32L4 diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c index 5fa182899c..94ac8d8df3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-27 zylx change to new framework + * 2018-12-12 greedyhao Porting for stm32f7xx */ #include "board.h" @@ -20,6 +21,14 @@ #if defined(BSP_USING_QSPI) +#if defined (SOC_SERIES_STM32L4) +#define QUADSPI_DMA_IRQ DMA1_Channel5_IRQn +#define QUADSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler +#elif defined (SOC_SERIES_STM32F7) +#define QUADSPI_DMA_IRQ DMA2_Stream2_IRQn +#define QUADSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler +#endif /* SOC_SERIES_STM32L4 */ + struct stm32_hw_spi_cs { uint16_t Pin; @@ -97,14 +106,19 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu /* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */ HAL_NVIC_SetPriority(QUADSPI_IRQn, 0, 0); HAL_NVIC_EnableIRQ(QUADSPI_IRQn); - HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); + HAL_NVIC_SetPriority(QUADSPI_DMA_IRQ, 0, 0); + HAL_NVIC_EnableIRQ(QUADSPI_DMA_IRQ); - /* init QSPI DMA */ - __HAL_RCC_DMA1_CLK_ENABLE(); + /* init QSPI DMA */ + __HAL_RCC_DMA1_CLK_ENABLE(); HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma); +#if defined(SOC_SERIES_STM32F4) qspi_bus->hdma_quadspi.Instance = DMA1_Channel5; qspi_bus->hdma_quadspi.Init.Request = DMA_REQUEST_5; +#elif defined(SOC_SERIES_STM32F7) + qspi_bus->hdma_quadspi.Instance = DMA2_Stream2; + qspi_bus->hdma_quadspi.Init.channel = DMA_CHANNEL_11; +#endif qspi_bus->hdma_quadspi.Init.Direction = DMA_PERIPH_TO_MEMORY; qspi_bus->hdma_quadspi.Init.PeriphInc = DMA_PINC_DISABLE; qspi_bus->hdma_quadspi.Init.MemInc = DMA_MINC_ENABLE; @@ -377,7 +391,7 @@ void QUADSPI_IRQHandler(void) rt_interrupt_leave(); } -void DMA1_Channel5_IRQHandler(void) +void QUADSPI_DMA_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index 3e7abed609..7883fc1c02 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-5 SummerGift change to new framework + * 2018-12-11 greedyhao Porting for stm32f7xx */ #include "board.h" diff --git a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig index defcdcacd8..fd7bf67079 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig @@ -20,7 +20,14 @@ menu "Onboard Peripheral Drivers" config BSP_USING_SDRAM bool "Enable SDRAM" default n - + + config BSP_USING_QSPI_FLASH + bool "Enable QSPI FLASH (W25Q128 spi5)" + select BSP_USING_SPI5 + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + endmenu menu "On-chip Peripheral Drivers" diff --git a/bsp/stm32/stm32f767-fire-challenger/board/SConscript b/bsp/stm32/stm32f767-fire-challenger/board/SConscript index c0637137c2..d70c847cd5 100644 --- a/bsp/stm32/stm32f767-fire-challenger/board/SConscript +++ b/bsp/stm32/stm32f767-fire-challenger/board/SConscript @@ -10,8 +10,8 @@ src += Glob('CubeMX_Config/Src/stm32f7xx_hal_msp.c') if GetDepend(['BSP_USING_ETH']): src += Glob('ports/phy_reset.c') -if GetDepend(['BSP_USING_SPI_FLASH']): - src += Glob('ports/spi_flash_init.c') +if GetDepend(['BSP_USING_QSPI_FLASH']): + src += Glob('ports/qspi_flash_init.c') path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c new file mode 100644 index 0000000000..1b9120a5c5 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 zylx change to new framework + */ + +#include +#include +#include +#include +#include + +#ifdef BSP_USING_QSPI_FLASH + +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +char w25qxx_read_status_register2(struct rt_qspi_device *device) +{ + /* 0x35 read status register2 */ + char instruction = 0x35, status; + + rt_qspi_send_then_recv(device, &instruction, 1, &status, 1); + + return status; +} + +void w25qxx_write_enable(struct rt_qspi_device *device) +{ + /* 0x06 write enable */ + char instruction = 0x06; + + rt_qspi_send(device, &instruction, 1); +} + +void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) +{ + char status = 0; + /* 0x38 enter qspi mode */ + char instruction = 0x38; + char write_status2_buf[2] = {0}; + + /* 0x31 write status register2 */ + write_status2_buf[0] = 0x31; + + status = w25qxx_read_status_register2(device); + if (!(status & 0x02)) + { + status |= 1 << 1; + w25qxx_write_enable(device); + write_status2_buf[1] = status; + rt_qspi_send(device, &write_status2_buf, 2); + rt_qspi_send(device, &instruction, 1); + rt_kprintf("flash already enter qspi mode\n"); + rt_thread_mdelay(10); + } +} + +static int rt_hw_qspi_flash_with_sfud_init(void) +{ + stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); + + /* init w25q128 */ + if (RT_NULL == rt_sfud_flash_probe("w25q128", "qspi10")) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); + +#endif/* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h b/bsp/stm32/stm32f767-fire-challenger/rtconfig.h index b452bdc556..69261c5e1e 100644 --- a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h +++ b/bsp/stm32/stm32f767-fire-challenger/rtconfig.h @@ -78,6 +78,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using WiFi */