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[lpcxxx] auto formatted

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This commit is contained in:
Meco Man
2021-03-17 02:26:35 +08:00
parent c3ffe18688
commit 958d940575
171 changed files with 5365 additions and 5302 deletions
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36
bsp/lpc176x/applications/application.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -38,44 +38,44 @@ extern int lwip_system_init(void);
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
/* initialize platform */
platform_init();
/* initialize platform */
platform_init();
#ifdef RT_USING_LWIP
/* register Ethernet interface device */
lpc17xx_emac_hw_init();
/* initialize lwip stack */
/* register ethernetif device */
eth_system_device_init();
/* register ethernetif device */
eth_system_device_init();
/* initialize lwip system */
lwip_system_init();
rt_kprintf("TCP/IP initialized!\n");
/* initialize lwip system */
lwip_system_init();
rt_kprintf("TCP/IP initialized!\n");
#endif
/* Filesystem Initialization */
#ifdef RT_USING_DFS
rt_hw_sdcard_init();
/* initialize the device file system */
dfs_init();
/* initialize the device file system */
dfs_init();
#ifdef RT_USING_DFS_ELMFAT
/* initialize the elm chan FatFS file system*/
elm_init();
/* initialize the elm chan FatFS file system*/
elm_init();
#endif
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
rt_kprintf("File System initialized!\n");
else
rt_kprintf("File System init failed!\n");
rt_kprintf("File System init failed!\n");
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
/* initialize finsh */
finsh_system_init();
#endif
}
@@ -84,8 +84,8 @@ int rt_application_init()
rt_thread_t tid;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
return 0;

8
bsp/lpc176x/applications/platform.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -16,11 +16,11 @@ static struct rt_memheap _memheap;
void platform_init(void)
{
#ifdef RT_USING_MEMHEAP
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
#ifdef RT_USING_LWIP
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
#else
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
#endif
#endif
}

2
bsp/lpc176x/applications/platform.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

56
bsp/lpc176x/applications/startup.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -33,28 +33,28 @@ extern int __bss_end;
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
#endif
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize application */
rt_application_init();
/* initialize application */
rt_application_init();
/* initialize timer */
rt_system_timer_init();
@@ -62,25 +62,25 @@ void rtthread_startup(void)
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
return 0;
}
/*@}*/

34
bsp/lpc176x/drivers/board.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -29,13 +29,13 @@
*/
void rt_hw_timer_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
}
void SysTick_Handler(void)
@@ -48,24 +48,24 @@ void SysTick_Handler(void)
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
/* initialize systick */
SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
/* initialize systick */
SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
#ifdef RT_USING_UART0
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

2
bsp/lpc176x/drivers/board.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

714
bsp/lpc176x/drivers/emac.c
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File diff suppressed because it is too large Load Diff

11
bsp/lpc176x/drivers/emac.h
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@@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
@@ -11,7 +20,7 @@
#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE 0x20080000
#define RX_DESC_BASE 0x20080000
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)

2
bsp/lpc176x/drivers/led.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/lpc176x/drivers/sd.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
if (dev->user_data == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = ((SDCFG *)dev->user_data)->sectorsize;
geometry->block_size = ((SDCFG *)dev->user_data)->blocksize;
geometry->sector_count = ((SDCFG *)dev->user_data)->sectorcnt;

229
bsp/lpc176x/drivers/spi.c
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@@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include "LPC17xx.h" /* LPC17xx definitions */
#include "spi.h"
@@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s);
/* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */
void LPC17xx_SPI_Init (void)
{
uint32_t dummy;
uint32_t dummy;
dummy = dummy; // avoid warning
dummy = dummy; // avoid warning
#if 0
/* Initialize and enable the SSP0 Interface module. */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* Initialize and enable the SSP0 Interface module. */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */
/* SSEL is GPIO, output set to high. */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
#else
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */
LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/
LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */
/* SSEL is GPIO, output set to high. */
LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */
LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/
LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */
/* P3.26 is SD Card Power Supply Enable Pin */
LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */
LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */
/* P3.26 is SD Card Power Supply Enable Pin */
LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */
LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */
#endif
/* PCLK_SSP0=CCLK */
LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */
/* PCLK_SSP0=CCLK */
LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */
LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */
LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */
LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
/* wait for busy gone */
while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* wait for busy gone */
while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* drain SPI RX FIFO */
while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
{
dummy = LPC_SSP0->DR;
}
/* drain SPI RX FIFO */
while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
{
dummy = LPC_SSP0->DR;
}
}
/* Close SSP0 */
void LPC17xx_SPI_DeInit( void )
{
// disable SPI
LPC_SSP0->CR1 = 0;
// disable SPI
LPC_SSP0->CR1 = 0;
#if 0
// Pins to GPIO
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
// Pins to GPIO
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
#else
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
#endif
// disable SSP power
LPC_SC->PCONP &= ~(1 << 21);
// disable SSP power
LPC_SC->PCONP &= ~(1 << 21);
}
/* Set a SSP0 clock speed to desired value. */
void LPC17xx_SPI_SetSpeed (uint8_t speed)
{
speed &= 0xFE;
if ( speed < 2 ) {
speed = 2 ;
}
LPC_SSP0->CPSR = speed;
speed &= 0xFE;
if ( speed < 2 ) {
speed = 2 ;
}
LPC_SSP0->CPSR = speed;
}
/* SSEL: low */
void LPC17xx_SPI_Select ()
{
#if 0
LPC_GPIO0->FIOPIN &= ~(1<<16);
LPC_GPIO0->FIOPIN &= ~(1<<16);
#else
LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */
LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */
#endif
}
@@ -120,41 +129,41 @@ void LPC17xx_SPI_Select ()
void LPC17xx_SPI_DeSelect ()
{
#if 0
LPC_GPIO0->FIOPIN |= (1<<16);
LPC_GPIO0->FIOPIN |= (1<<16);
#else
LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */
LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */
#endif
}
/* Send one byte then recv one byte of response. */
static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s)
{
uint8_t byte_r;
uint8_t byte_r;
LPC_SSP0->DR = byte_s;
while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */
byte_r = LPC_SSP0->DR;
LPC_SSP0->DR = byte_s;
while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */
byte_r = LPC_SSP0->DR;
return byte_r; /* Return received value */
return byte_r; /* Return received value */
}
/* Send one byte */
void LPC17xx_SPI_SendByte (uint8_t data)
{
LPC17xx_SPI_SendRecvByte (data);
LPC17xx_SPI_SendRecvByte (data);
}
/* Recv one byte */
uint8_t LPC17xx_SPI_RecvByte ()
{
return LPC17xx_SPI_SendRecvByte (0xFF);
return LPC17xx_SPI_SendRecvByte (0xFF);
}
/* Release SSP0 */
void LPC17xx_SPI_Release (void)
{
LPC17xx_SPI_DeSelect ();
LPC17xx_SPI_RecvByte ();
LPC17xx_SPI_DeSelect ();
LPC17xx_SPI_RecvByte ();
}
@@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void)
#define FIFO_ELEM 8
/* Receive btr (must be multiple of 4) bytes of data and store in buff. */
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
{
uint32_t hwtr, startcnt, i, rec;
uint32_t hwtr, startcnt, i, rec;
hwtr = btr/2; /* byte number in unit of short */
if ( btr < FIFO_ELEM ) {
startcnt = hwtr;
} else {
startcnt = FIFO_ELEM;
}
hwtr = btr/2; /* byte number in unit of short */
if ( btr < FIFO_ELEM ) {
startcnt = hwtr;
} else {
startcnt = FIFO_ELEM;
}
LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */
LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */
for ( i = startcnt; i; i-- ) {
LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
for ( i = startcnt; i; i-- ) {
LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
do {
while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
// wait for data in RX FIFO (RNE set)
}
rec = LPC_SSP0->DR;
if ( i < ( hwtr - startcnt ) ) {
LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
*buff++ = (uint8_t)(rec>>8);
*buff++ = (uint8_t)(rec);
i++;
} while ( i < hwtr );
do {
while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
// wait for data in RX FIFO (RNE set)
}
rec = LPC_SSP0->DR;
if ( i < ( hwtr - startcnt ) ) {
LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
*buff++ = (uint8_t)(rec>>8);
*buff++ = (uint8_t)(rec);
i++;
} while ( i < hwtr );
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
}
/* Send 512 bytes of data block (stored in buff). */
void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff)
{
uint32_t cnt;
uint16_t data;
uint32_t cnt;
uint16_t data;
LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */
LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */
/* fill the FIFO unless it is full */
for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
{
/* wait for TX FIFO not full (TNF) */
while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
/* fill the FIFO unless it is full */
for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
{
/* wait for TX FIFO not full (TNF) */
while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
data = (*buff++) << 8;
data |= *buff++;
LPC_SSP0->DR = data;
}
data = (*buff++) << 8;
data |= *buff++;
LPC_SSP0->DR = data;
}
/* wait for BSY gone */
while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* wait for BSY gone */
while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* drain receive FIFO */
while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
data = LPC_SSP0->DR;
}
/* drain receive FIFO */
while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
data = LPC_SSP0->DR;
}
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
}
#endif /* USE_FIFO */

25
bsp/lpc176x/drivers/spi.h
View File

@@ -1,17 +1,26 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_SPI_H__
#define __LPC17XX_SPI_H__
#include <stdint.h>
#include <stdbool.h>
// if not use FIFO, R: 600kB/s, W: 500kB/s
// if use FIFO, R: 1.2MB/s, W: 800kB/s
// if not use FIFO, R: 600kB/s, W: 500kB/s
// if use FIFO, R: 1.2MB/s, W: 800kB/s
#define USE_FIFO 1
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
#define SPI_SPEED_20MHz 4 /* => 18MHz */
#define SPI_SPEED_25MHz 4 /* => 18MHz */
#define SPI_SPEED_400kHz 180 /* => 400kHz */
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
#define SPI_SPEED_20MHz 4 /* => 18MHz */
#define SPI_SPEED_25MHz 4 /* => 18MHz */
#define SPI_SPEED_400kHz 180 /* => 400kHz */
/* external functions */
void LPC17xx_SPI_Init (void);
@@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data);
uint8_t LPC17xx_SPI_RecvByte (void);
#if USE_FIFO
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff);
#endif
#endif // __LPC17XX_SPI_H__
#endif // __LPC17XX_SPI_H__

10
bsp/lpc176x/drivers/uart.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -56,8 +56,8 @@ void UART0_IRQHandler(void)
{
rt_ubase_t level, iir;
struct rt_uart_lpc *uart = &uart_device;
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
/* read IIR and clear it */
iir = LPC_UART->IIR;
@@ -91,8 +91,8 @@ void UART0_IRQHandler(void)
{
iir = LPC_UART->LSR; //oe pe fe oe read for clear interrupt
}
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
return;
}

52
bsp/lpc176x/rtconfig.h
View File

@@ -4,17 +4,17 @@
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 6
#define RT_NAME_MAX 6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
#define RT_DEBUG_COLOR
@@ -29,11 +29,11 @@
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
@@ -67,15 +67,15 @@
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
@@ -87,7 +87,7 @@
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
@@ -102,16 +102,16 @@
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
#define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_CODE_PAGE" description="specifies the OEM code page to be used on the target system" default="936">
// <item description="Japanese Shift-JIS (DBCS, OEM, Windows)">932</item>
// <item description="Simplified Chinese GBK (DBCS, OEM, Windows)">936</item>
@@ -142,7 +142,7 @@
// </integer>
#define RT_DFS_ELM_CODE_PAGE 437
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 64
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
@@ -152,7 +152,7 @@
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
@@ -168,29 +168,29 @@
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR "192.168.1.30"
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />