mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-23 12:15:32 +08:00
feat[ADC]: 新增 ADC V2 驱动支持 (#11440)
* feat[ADC V2]: add ADC V2 driver support add ADC V2 core APIs, session state management, and sequence read support add STM32 ADC V2 HAL backend with internal-channel and VREF handling add per-series STM32 ADC V2 default configuration headers wire ADC V2 Kconfig and SConscript integration for components and STM32 BSP drivers keep ADC V2 mutually exclusive with the legacy ADC driver path * feat[ADC V2]: add ADC V2 MSH special channel read support add generic ADC V2 MSH commands for probing, configuring, raw reads, voltage reads, and sequence reads add STM32 ADC V2 backend special commands for VREFINT, temperature sensor, and VBAT reads add STM32 helper APIs for special logical channels, sampling time, resolution, and temperature calculation wire ADC V2 MSH sources through Kconfig and SConscript * feat[ADC V2]: add ADC V2 stream DMA support add ADC V2 stream APIs with latest-frame and FIFO buffering policies wire STM32 ADC V2 to circular DMA stream mode with per-instance Kconfig options extend STM32 ADC config headers and DMA helpers for stream DMA configuration add FinSH stream commands for start, read, cancel, and stop operations handle Cortex-M7 cache-safe DMA buffers for STM32 stream sampling * feat[ADC V2]: add timer trigger support for ADC V2 streams add ADC V2 trigger configuration, validation, and lifecycle coordination add timer update trigger support through clock timer TRGO controls map STM32 ADC V2 timer update triggers to HAL external trigger selector fields add Kconfig, SConscript, and MSH entries for ADC trigger setup and inspection * feat[ADCV2]: add timer and comparator trigger selectors add ADC V2 timer compare and analog comparator trigger configuration support extend clock timer trigger config with compare event and channel fields wire STM32 ADC external trigger selector mappings for TIM update, TIM compare, and COMP output add FinSH trigger_set commands and Kconfig switches for timer and comparator trigger backends * fix[ADC V2]: resolve ADC V1 compatibility Kconfig loop * ci[ADC V2][stm32]: add ADC v2 peripheral config for stm32f407-rt-spark BSP
This commit is contained in:
wdfk-prog
@@ -24,6 +24,116 @@ if BSP_USING_USBD
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# "ULPI: UTMI+ Low Pin Interface"
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endif
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menuconfig BSP_USING_ADC_V2
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bool "Enable ADC V2"
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select RT_USING_ADC
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select RT_USING_ADC_V2
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default n
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if BSP_USING_ADC_V2
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config BSP_USING_ADC1
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bool "Enable ADC1"
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default n
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config BSP_USING_ADC2
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bool "Enable ADC2"
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depends on (SOC_SERIES_STM32F1 || SOC_SERIES_STM32F2 || SOC_SERIES_STM32F3 || \
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SOC_SERIES_STM32F4 || SOC_SERIES_STM32G4 || SOC_SERIES_STM32F7 || \
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SOC_SERIES_STM32H5 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32H7RS || \
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SOC_SERIES_STM32L4 || SOC_SERIES_STM32L5 || SOC_SERIES_STM32MP1 || \
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SOC_SERIES_STM32U5)
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default n
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config BSP_USING_ADC3
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bool "Enable ADC3"
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depends on (SOC_SERIES_STM32F1 || SOC_SERIES_STM32F2 || SOC_SERIES_STM32F3 || \
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SOC_SERIES_STM32F4 || SOC_SERIES_STM32G4 || SOC_SERIES_STM32F7 || \
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SOC_SERIES_STM32H7 || SOC_SERIES_STM32L4 || SOC_SERIES_STM32MP1)
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default n
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config BSP_USING_ADC4
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bool "Enable ADC4"
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depends on (SOC_SERIES_STM32F3 || SOC_SERIES_STM32G4 || SOC_SERIES_STM32U5)
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default n
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config BSP_ADC_USING_TRIGGER
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bool "Enable ADC V2 trigger backend"
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select RT_ADC_USING_TRIGGER
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default n
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help
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Enable STM32 ADC V2 trigger selector validation and backend
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encoding. The ADC backend maps the framework-cached trigger to STM32
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HAL ADC selector fields. Trigger-source frequency and lifecycle are
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owned by the ADC trigger framework and timer trigger backend.
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config BSP_ADC_USING_TIMER_TRIGGER
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bool "Enable ADC V2 timer trigger selector backend"
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depends on BSP_ADC_USING_TRIGGER
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depends on BSP_USING_TIM
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depends on RT_USING_CLOCK_TIME
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select RT_ADC_TRIGGER_USING_TIMER
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select RT_USING_CLOCK_TIMER_TRIGGER
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default n
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help
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Enable STM32 TIMx update/TRGO and compare event to ADC external
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trigger selector mapping for ADC V2 stream pacing. Timer frequency,
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TRGO/compare setup, and lifecycle are handled through the clock
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timer trigger backend during ADC stream start and stop.
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config BSP_ADC_USING_ANALOG_COMPARE_TRIGGER
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bool "Enable ADC V2 analog comparator trigger selector backend"
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depends on BSP_ADC_USING_TRIGGER
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select RT_ADC_TRIGGER_USING_COMPARE
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default n
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help
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Enable STM32 COMPx_OUT to ADC external trigger selector mapping for
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ADC V2. Comparator input, threshold, polarity, and enable state are
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owned by board code, application code, or a comparator driver.
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config BSP_ADC_USING_STREAM_DMA
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bool
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config BSP_ADC1_USING_DMA
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bool "Enable ADC1 stream DMA backend"
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depends on BSP_USING_ADC1
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select RT_ADC_USING_STREAM
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select BSP_ADC_USING_STREAM_DMA
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default n
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help
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Enable the STM32 ADC1 DMA backend for ADC V2 stream sessions.
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This option only enables the board-level DMA backend. The stream
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framework and buffering policies are controlled by RT_ADC_USING_STREAM,
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RT_ADC_STREAM_USING_LATEST, and RT_ADC_STREAM_USING_FIFO.
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config BSP_ADC2_USING_DMA
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bool "Enable ADC2 stream DMA backend"
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depends on BSP_USING_ADC2
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select RT_ADC_USING_STREAM
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select BSP_ADC_USING_STREAM_DMA
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default n
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help
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Enable the STM32 ADC2 DMA backend for ADC V2 stream sessions.
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config BSP_ADC3_USING_DMA
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bool "Enable ADC3 stream DMA backend"
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depends on BSP_USING_ADC3
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select RT_ADC_USING_STREAM
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select BSP_ADC_USING_STREAM_DMA
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default n
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help
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Enable the STM32 ADC3 DMA backend for ADC V2 stream sessions.
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config BSP_ADC4_USING_DMA
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bool "Enable ADC4 stream DMA backend"
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depends on BSP_USING_ADC4
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select RT_ADC_USING_STREAM
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select BSP_ADC_USING_STREAM_DMA
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default n
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help
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Enable the STM32 ADC4 DMA backend for ADC V2 stream sessions.
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endif
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config BSP_USING_CRC
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bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
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select RT_USING_HWCRYPTO
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@@ -59,4 +169,3 @@ config BSP_USING_UDID
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bool "Enable UDID (Unique Device Identifier)"
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select RT_USING_HWCRYPTO
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default n
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@@ -46,9 +46,18 @@ if GetDepend(['RT_USING_I2C']):
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if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']) and not GetDepend(['SOC_STM32H750_ARTPI']):
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src += ['drv_eth.c']
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if GetDepend(['RT_USING_ADC']):
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if GetDepend(['RT_USING_ADC']) and not GetDepend(['RT_USING_ADC_V2']):
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src += ['drv_adc.c']
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if GetDepend(['BSP_USING_ADC_V2']):
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src += ['drv_adc_v2.c']
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if GetDepend(['BSP_ADC_USING_TRIGGER']):
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src += ['drv_adc_v2_trigger.c']
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if GetDepend(['RT_USING_FINSH', 'RT_ADC_V2_USING_MSH']):
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src += ['drv_adc_v2_msh.c']
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if GetDepend(['RT_USING_DAC']):
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src += ['drv_dac.c']
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@@ -0,0 +1,372 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2026-04-21 wdfk-prog add stm32f0 adc v2 configuration
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*/
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/**
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* @file adc_config_v2.h
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* @brief STM32F0 ADC V2 configuration defaults.
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*/
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#ifndef __ADC_CONFIG_V2_H__
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#define __ADC_CONFIG_V2_H__
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#include <rtconfig.h>
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#if defined(RT_USING_ADC_V2)
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#include <rtthread.h>
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#include <drivers/adc_v2.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @brief Default ADC clock prescaler for STM32F0. */
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#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
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#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
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#elif defined(ADC_CLOCK_ASYNC_DIV1)
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#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
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#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
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/** @brief Default ADC data alignment for STM32F0. */
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#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
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/** @brief Default ADC resolution for STM32 ADC V2. */
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#ifdef ADC_RESOLUTION_12B
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#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
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#else
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#define ADC_DEFAULT_RESOLUTION 0U
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#endif /* ADC_RESOLUTION_12B */
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/** @brief Default ADC sampling time for STM32F0. */
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#if defined(ADC_SAMPLETIME_71CYCLES_5)
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#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_71CYCLES_5
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#else
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#define ADC_DEFAULT_SAMPLING_TIME 0U
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#endif /* defined(ADC_SAMPLETIME_71CYCLES_5) */
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/** @brief Maximum regular sequence length supported by the STM32F0 driver. */
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#define STM32_ADC_MAX_SEQUENCE 16
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/** @brief Whether sequence mode is compiled in. */
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#define STM32_ADC_USING_SEQUENCE 1
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/** @brief Whether any ADC instance requests a stream DMA backend. */
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#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
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defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
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#define STM32_ADC_HAS_STREAM_DMA_BSP 1
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#else
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#define STM32_ADC_HAS_STREAM_DMA_BSP 0
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#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
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/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
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#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
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#define STM32_ADC_USING_STREAM 1
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#else
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#define STM32_ADC_USING_STREAM 0
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#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
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/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
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#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
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#if STM32_ADC_USING_STREAM
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#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
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#if defined(ADC1_DMA_REQUEST)
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#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
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#else
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#define STM32_ADC1_DMA_REQUEST_VALUE 0U
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#endif /* defined(ADC1_DMA_REQUEST) */
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#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
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#define ADC1_V2_HAS_DMA_CONFIG 1
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static const struct stm32_dma_config ADC1_DMA_CONFIG =
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STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
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ADC1_DMA_RCC,
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ADC1_DMA_IRQ,
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ADC1_DMA_REQUEST,
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STM32_DMA_DEFAULT_PRIORITY,
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STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
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STM32_DMA_DEFAULT_SUB_PRIORITY);
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#elif defined(ADC1_DMA_CHANNEL)
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#define ADC1_V2_HAS_DMA_CONFIG 1
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static const struct stm32_dma_config ADC1_DMA_CONFIG =
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STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
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ADC1_DMA_RCC,
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ADC1_DMA_IRQ,
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ADC1_DMA_CHANNEL,
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STM32_ADC1_DMA_REQUEST_VALUE,
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STM32_DMA_DEFAULT_PRIORITY,
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STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
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STM32_DMA_DEFAULT_SUB_PRIORITY);
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#elif defined(ADC1_DMA_REQUEST)
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#define ADC1_V2_HAS_DMA_CONFIG 1
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static const struct stm32_dma_config ADC1_DMA_CONFIG =
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STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
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ADC1_DMA_RCC,
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ADC1_DMA_IRQ,
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0U,
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ADC1_DMA_REQUEST,
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STM32_DMA_DEFAULT_PRIORITY,
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STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
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STM32_DMA_DEFAULT_SUB_PRIORITY);
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#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
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#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
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#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
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#if defined(ADC2_DMA_REQUEST)
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#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
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#else
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#define STM32_ADC2_DMA_REQUEST_VALUE 0U
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#endif /* defined(ADC2_DMA_REQUEST) */
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#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
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#define ADC2_V2_HAS_DMA_CONFIG 1
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static const struct stm32_dma_config ADC2_DMA_CONFIG =
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STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
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ADC2_DMA_RCC,
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ADC2_DMA_IRQ,
|
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ADC2_DMA_REQUEST,
|
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STM32_DMA_DEFAULT_PRIORITY,
|
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STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
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STM32_DMA_DEFAULT_SUB_PRIORITY);
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#elif defined(ADC2_DMA_CHANNEL)
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#define ADC2_V2_HAS_DMA_CONFIG 1
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static const struct stm32_dma_config ADC2_DMA_CONFIG =
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STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
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ADC2_DMA_RCC,
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ADC2_DMA_IRQ,
|
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ADC2_DMA_CHANNEL,
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STM32_ADC2_DMA_REQUEST_VALUE,
|
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STM32_DMA_DEFAULT_PRIORITY,
|
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STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
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STM32_DMA_DEFAULT_SUB_PRIORITY);
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#elif defined(ADC2_DMA_REQUEST)
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#define ADC2_V2_HAS_DMA_CONFIG 1
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static const struct stm32_dma_config ADC2_DMA_CONFIG =
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STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
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ADC2_DMA_RCC,
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ADC2_DMA_IRQ,
|
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0U,
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ADC2_DMA_REQUEST,
|
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STM32_DMA_DEFAULT_PRIORITY,
|
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STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
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STM32_DMA_DEFAULT_SUB_PRIORITY);
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#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
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#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
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#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
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#if defined(ADC3_DMA_REQUEST)
|
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#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
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#else
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#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
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#endif /* defined(ADC3_DMA_REQUEST) */
|
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|
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#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
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#define ADC3_V2_HAS_DMA_CONFIG 1
|
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static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
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STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
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ADC3_DMA_RCC,
|
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ADC3_DMA_IRQ,
|
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ADC3_DMA_REQUEST,
|
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STM32_DMA_DEFAULT_PRIORITY,
|
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STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
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STM32_DMA_DEFAULT_SUB_PRIORITY);
|
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#elif defined(ADC3_DMA_CHANNEL)
|
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#define ADC3_V2_HAS_DMA_CONFIG 1
|
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static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
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STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
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ADC3_DMA_RCC,
|
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ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
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STM32_DMA_DEFAULT_SUB_PRIORITY);
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#elif defined(ADC3_DMA_REQUEST)
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#define ADC3_V2_HAS_DMA_CONFIG 1
|
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static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
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STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
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ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
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0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
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|
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#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
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#if defined(ADC4_DMA_REQUEST)
|
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#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
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#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
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#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
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#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32F0 legacy internal ADC source logical channel overrides. */
|
||||
#if !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB)
|
||||
#define STM32_ADC_TEMP_LOGICAL_OVERRIDE 16
|
||||
#define STM32_ADC_VREF_LOGICAL_OVERRIDE 17
|
||||
#define STM32_ADC_VBAT_LOGICAL_OVERRIDE 18
|
||||
#endif /* !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32F0 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32F0 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32F0 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,365 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32f1 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32F1 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32F1. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32F1. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32F1. */
|
||||
#if defined(ADC_SAMPLETIME_55CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_55CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_55CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32F1 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32F1 legacy internal ADC source logical channel overrides. */
|
||||
#if !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB)
|
||||
#define STM32_ADC_TEMP_LOGICAL_OVERRIDE 16
|
||||
#define STM32_ADC_VREF_LOGICAL_OVERRIDE 17
|
||||
#define STM32_ADC_VBAT_LOGICAL_OVERRIDE 18
|
||||
#endif /* !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32F1 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32F1 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32F1 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32f2 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32F2 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32F2. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32F2. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32F2. */
|
||||
#if defined(ADC_SAMPLETIME_112CYCLES)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_112CYCLES
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_112CYCLES) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32F2 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32F2 legacy internal ADC source logical channel overrides. */
|
||||
#if !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB)
|
||||
#define STM32_ADC_TEMP_LOGICAL_OVERRIDE 16
|
||||
#define STM32_ADC_VREF_LOGICAL_OVERRIDE 17
|
||||
#define STM32_ADC_VBAT_LOGICAL_OVERRIDE 18
|
||||
#endif /* !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_HAS_CONFIG_OFFSET 1
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32F2 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32F2 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32F2 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,405 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32f3 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32F3 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32F3. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32F3. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32F3. */
|
||||
#if defined(ADC_SAMPLETIME_181CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_181CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_181CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32F3 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32F3 legacy internal ADC source logical channel overrides. */
|
||||
#if !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB)
|
||||
#define STM32_ADC_TEMP_LOGICAL_OVERRIDE 16
|
||||
#define STM32_ADC_VREF_LOGICAL_OVERRIDE 17
|
||||
#define STM32_ADC_VBAT_LOGICAL_OVERRIDE 18
|
||||
#endif /* !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VREFINT)
|
||||
/** @brief STM32F3 VREFINT HAL ADC channel for the multi-instance route. */
|
||||
#define STM32_ADC_VREF_HAL_CHANNEL ADC_CHANNEL_VREFINT
|
||||
/** @brief STM32F3 ADC instances that can sample VREFINT. */
|
||||
#define STM32_ADC_VREF_INSTANCE_MASK ((1UL << 0) | (1UL << 1) | (1UL << 2) | (1UL << 3))
|
||||
#endif /* defined(ADC_CHANNEL_VREFINT) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32F3 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32F3 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32F3 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef BSP_USING_ADC4
|
||||
/** @brief Default STM32F3 ADC4 V2 object initializer. */
|
||||
#define ADC4_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc4", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC4, \
|
||||
}, \
|
||||
ADC4_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32f4 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32F4 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32F4. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32F4. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32F4. */
|
||||
#if defined(ADC_SAMPLETIME_112CYCLES)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_112CYCLES
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_112CYCLES) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32F4 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32F4 legacy internal ADC source logical channel overrides. */
|
||||
#if !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB)
|
||||
#define STM32_ADC_TEMP_LOGICAL_OVERRIDE 16
|
||||
#define STM32_ADC_VREF_LOGICAL_OVERRIDE 17
|
||||
#define STM32_ADC_VBAT_LOGICAL_OVERRIDE 18
|
||||
#endif /* !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_HAS_CONFIG_OFFSET 1
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32F4 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32F4 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32F4 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -211,7 +211,13 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA2 stream0 */
|
||||
#if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE)
|
||||
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE)
|
||||
#define ADC1_DMA_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define ADC1_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define ADC1_DMA_INSTANCE DMA2_Stream0
|
||||
@@ -223,12 +229,6 @@ extern "C" {
|
||||
#define ADC3_DMA_INSTANCE DMA2_Stream0
|
||||
#define ADC3_DMA_CHANNEL DMA_CHANNEL_2
|
||||
#define ADC3_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
|
||||
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
|
||||
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
@@ -283,18 +283,18 @@ extern "C" {
|
||||
#define MEMTOMEM2_DMA_INSTANCE DMA2_Stream2
|
||||
#define MEMTOMEM2_DMA_CHANNEL DMA_CHANNEL_2
|
||||
#define MEMTOMEM2_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define UART1_RX_DMA_INSTANCE DMA2_Stream2
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
|
||||
#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
|
||||
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
|
||||
#define UART6_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#define UART6_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||
|
||||
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32f7 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32F7 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32F7. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32F7. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32F7. */
|
||||
#if defined(ADC_SAMPLETIME_112CYCLES)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_112CYCLES
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_112CYCLES) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32F7 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32F7 legacy internal ADC source logical channel overrides. */
|
||||
#if !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB)
|
||||
#define STM32_ADC_TEMP_LOGICAL_OVERRIDE 16
|
||||
#define STM32_ADC_VREF_LOGICAL_OVERRIDE 17
|
||||
#define STM32_ADC_VBAT_LOGICAL_OVERRIDE 18
|
||||
#endif /* !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_HAS_CONFIG_OFFSET 1
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32F7 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32F7 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32F7 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,327 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-05-27 wdfk-prog add stm32g0 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32G0 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32G0. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32G0. */
|
||||
#if defined(ADC_DATAALIGN_RIGHT)
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
#else
|
||||
#define ADC_DEFAULT_DATA_ALIGN 0U
|
||||
#endif /* defined(ADC_DATAALIGN_RIGHT) */
|
||||
|
||||
/** @brief Default ADC resolution for STM32G0. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32G0. */
|
||||
#if defined(ADC_SAMPLETIME_160CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_160CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_79CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_79CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_39CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_39CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_160CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32G0 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32G0 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,412 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32g4 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32G4 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32G4. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32G4. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32G4. */
|
||||
#if defined(ADC_SAMPLETIME_247CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_247CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_247CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32G4 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
#if defined(ADC_CHANNEL_VBAT)
|
||||
/** @brief STM32G4 VBAT HAL ADC channel for the multi-instance route. */
|
||||
#define STM32_ADC_VBAT_HAL_CHANNEL ADC_CHANNEL_VBAT
|
||||
/** @brief STM32G4 ADC instances that can sample VBAT. */
|
||||
#define STM32_ADC_VBAT_INSTANCE_MASK ((1UL << 0) | (1UL << 2) | (1UL << 4))
|
||||
#endif /* defined(ADC_CHANNEL_VBAT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VREFINT)
|
||||
/** @brief STM32G4 VREFINT HAL ADC channel for the multi-instance route. */
|
||||
#define STM32_ADC_VREF_HAL_CHANNEL ADC_CHANNEL_VREFINT
|
||||
/** @brief STM32G4 ADC instances that can sample VREFINT. */
|
||||
#define STM32_ADC_VREF_INSTANCE_MASK ((1UL << 0) | (1UL << 2) | (1UL << 3) | (1UL << 4))
|
||||
#endif /* defined(ADC_CHANNEL_VREFINT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_TEMPSENSOR_ADC5)
|
||||
/** @brief STM32G4 alternate temperature sensor HAL ADC channel. */
|
||||
#define STM32_ADC_TEMP_ALT_HAL_CHANNEL ADC_CHANNEL_TEMPSENSOR_ADC5
|
||||
/** @brief STM32G4 ADC instances that can sample the alternate temperature sensor channel. */
|
||||
#define STM32_ADC_TEMP_ALT_INSTANCE_MASK (1UL << 4)
|
||||
#endif /* defined(ADC_CHANNEL_TEMPSENSOR_ADC5) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32G4 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32G4 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32G4 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef BSP_USING_ADC4
|
||||
/** @brief Default STM32G4 ADC4 V2 object initializer. */
|
||||
#define ADC4_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc4", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC4, \
|
||||
}, \
|
||||
ADC4_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,371 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-05-27 wdfk-prog add stm32h5 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32H5 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32H5. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32H5. */
|
||||
#if defined(ADC_DATAALIGN_RIGHT)
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
#else
|
||||
#define ADC_DEFAULT_DATA_ALIGN 0U
|
||||
#endif /* defined(ADC_DATAALIGN_RIGHT) */
|
||||
|
||||
/** @brief Default ADC resolution for STM32H5. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32H5. */
|
||||
#if defined(ADC_SAMPLETIME_814CYCLES)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_814CYCLES
|
||||
#elif defined(ADC_SAMPLETIME_810CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_810CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_247CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_247CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_814CYCLES) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32H5 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
#if defined(ADC_CHANNEL_VBAT)
|
||||
/** @brief STM32H5 VBAT HAL ADC channel for the series-specific route. */
|
||||
#define STM32_ADC_VBAT_HAL_CHANNEL ADC_CHANNEL_VBAT
|
||||
#if defined(ADC2)
|
||||
/** @brief STM32H5 ADC instances that can sample VBAT. */
|
||||
#define STM32_ADC_VBAT_INSTANCE_MASK (1UL << 1)
|
||||
#else
|
||||
/** @brief STM32H5 ADC instances that can sample VBAT. */
|
||||
#define STM32_ADC_VBAT_INSTANCE_MASK (1UL << 0)
|
||||
#endif /* defined(ADC2) */
|
||||
#endif /* defined(ADC_CHANNEL_VBAT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VBAT_ADC4)
|
||||
/** @brief STM32H5 alternate VBAT HAL ADC channel. */
|
||||
#define STM32_ADC_VBAT_ALT_HAL_CHANNEL ADC_CHANNEL_VBAT_ADC4
|
||||
/** @brief STM32H5 ADC instances that can sample the alternate VBAT channel. */
|
||||
#define STM32_ADC_VBAT_ALT_INSTANCE_MASK (1UL << 2)
|
||||
#endif /* defined(ADC_CHANNEL_VBAT_ADC4) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32H5 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32H5 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,386 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32h7 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32H7 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32H7. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32H7. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32H7. */
|
||||
#if defined(ADC_SAMPLETIME_810CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_810CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_810CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32H7 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
#if defined(ADC3)
|
||||
/** @brief STM32H7 default internal ADC source instance mask. */
|
||||
#define STM32_ADC_INTERNAL_DEFAULT_INSTANCE_MASK (1UL << 2)
|
||||
#else
|
||||
/** @brief STM32H7 default internal ADC source instance mask. */
|
||||
#define STM32_ADC_INTERNAL_DEFAULT_INSTANCE_MASK 0UL
|
||||
#endif /* defined(ADC3) */
|
||||
|
||||
#if defined(ADC_CHANNEL_TEMPSENSOR)
|
||||
/** @brief STM32H7 temperature sensor HAL ADC channel for the default internal route. */
|
||||
#define STM32_ADC_TEMP_HAL_CHANNEL ADC_CHANNEL_TEMPSENSOR
|
||||
#endif /* defined(ADC_CHANNEL_TEMPSENSOR) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VBAT)
|
||||
/** @brief STM32H7 VBAT HAL ADC channel for the default internal route. */
|
||||
#define STM32_ADC_VBAT_HAL_CHANNEL ADC_CHANNEL_VBAT
|
||||
#endif /* defined(ADC_CHANNEL_VBAT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VREFINT)
|
||||
/** @brief STM32H7 VREFINT HAL ADC channel for the default internal route. */
|
||||
#define STM32_ADC_VREF_HAL_CHANNEL ADC_CHANNEL_VREFINT
|
||||
#endif /* defined(ADC_CHANNEL_VREFINT) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32H7 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32H7 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32H7 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,366 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-05-27 wdfk-prog add stm32h7rs adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32H7RS ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32H7RS. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32H7RS. */
|
||||
#if defined(ADC_DATAALIGN_RIGHT)
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
#else
|
||||
#define ADC_DEFAULT_DATA_ALIGN 0U
|
||||
#endif /* defined(ADC_DATAALIGN_RIGHT) */
|
||||
|
||||
/** @brief Default ADC resolution for STM32H7RS. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32H7RS. */
|
||||
#if defined(ADC_SAMPLETIME_810CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_810CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_814CYCLES)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_814CYCLES
|
||||
#elif defined(ADC_SAMPLETIME_387CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_387CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_810CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32H7RS driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32H7RS ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32H7RS ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32H7RS ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,336 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-05-27 wdfk-prog add stm32l0 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32L0 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32L0. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32L0. */
|
||||
#if defined(ADC_DATAALIGN_RIGHT)
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
#else
|
||||
#define ADC_DEFAULT_DATA_ALIGN 0U
|
||||
#endif /* defined(ADC_DATAALIGN_RIGHT) */
|
||||
|
||||
/** @brief Default ADC resolution for STM32L0. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32L0. */
|
||||
#if defined(ADC_SAMPLETIME_160CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_160CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_79CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_79CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_39CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_39CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_160CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32L0 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32L0 legacy internal ADC source logical channel overrides. */
|
||||
#if !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB)
|
||||
#define STM32_ADC_TEMP_LOGICAL_OVERRIDE 16
|
||||
#define STM32_ADC_VREF_LOGICAL_OVERRIDE 17
|
||||
#define STM32_ADC_VBAT_LOGICAL_OVERRIDE 18
|
||||
#endif /* !defined(__HAL_ADC_CHANNEL_TO_DECIMAL_NB) && !defined(__LL_ADC_CHANNEL_TO_DECIMAL_NB) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32L0 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,392 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32l4 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32L4 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32L4. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32L4. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32L4. */
|
||||
#if defined(ADC_SAMPLETIME_247CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_247CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_247CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32L4 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
#if defined(ADC_CHANNEL_TEMPSENSOR)
|
||||
/** @brief STM32L4 temperature sensor HAL ADC channel for the multi-instance route. */
|
||||
#define STM32_ADC_TEMP_HAL_CHANNEL ADC_CHANNEL_TEMPSENSOR
|
||||
/** @brief STM32L4 ADC instances that can sample temperature sensor. */
|
||||
#define STM32_ADC_TEMP_INSTANCE_MASK ((1UL << 0) | (1UL << 2))
|
||||
#endif /* defined(ADC_CHANNEL_TEMPSENSOR) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VBAT)
|
||||
/** @brief STM32L4 VBAT HAL ADC channel for the multi-instance route. */
|
||||
#define STM32_ADC_VBAT_HAL_CHANNEL ADC_CHANNEL_VBAT
|
||||
/** @brief STM32L4 ADC instances that can sample VBAT. */
|
||||
#define STM32_ADC_VBAT_INSTANCE_MASK ((1UL << 0) | (1UL << 2))
|
||||
#endif /* defined(ADC_CHANNEL_VBAT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VREFINT)
|
||||
/** @brief STM32L4 VREFINT HAL ADC channel for the multi-instance route. */
|
||||
#define STM32_ADC_VREF_HAL_CHANNEL ADC_CHANNEL_VREFINT
|
||||
/** @brief STM32L4 ADC instances that can sample VREFINT. */
|
||||
#define STM32_ADC_VREF_INSTANCE_MASK ((1UL << 0) | (1UL << 1) | (1UL << 2))
|
||||
#endif /* defined(ADC_CHANNEL_VREFINT) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_HAS_SIMPLE_CALIBRATION 1
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32L4 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32L4 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32L4 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,353 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-05-27 wdfk-prog add stm32l5 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32L5 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32L5. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32L5. */
|
||||
#if defined(ADC_DATAALIGN_RIGHT)
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
#else
|
||||
#define ADC_DEFAULT_DATA_ALIGN 0U
|
||||
#endif /* defined(ADC_DATAALIGN_RIGHT) */
|
||||
|
||||
/** @brief Default ADC resolution for STM32L5. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32L5. */
|
||||
#if defined(ADC_SAMPLETIME_247CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_247CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_640CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_640CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_160CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_160CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_247CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32L5 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_HAS_SIMPLE_CALIBRATION 1
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32L5 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32L5 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32mp1 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32MP1 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32MP1. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32MP1. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32MP1. */
|
||||
#if defined(ADC_SAMPLETIME_810CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_810CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_810CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32MP1 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
#if defined(ADC_CHANNEL_VBAT)
|
||||
/** @brief STM32MP1 VBAT HAL ADC channel for the ADC2 route. */
|
||||
#define STM32_ADC_VBAT_HAL_CHANNEL ADC_CHANNEL_VBAT
|
||||
/** @brief STM32MP1 ADC instances that can sample VBAT. */
|
||||
#define STM32_ADC_VBAT_INSTANCE_MASK (1UL << 1)
|
||||
#endif /* defined(ADC_CHANNEL_VBAT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VREFINT)
|
||||
/** @brief STM32MP1 VREFINT HAL ADC channel for the ADC2 route. */
|
||||
#define STM32_ADC_VREF_HAL_CHANNEL ADC_CHANNEL_VREFINT
|
||||
/** @brief STM32MP1 ADC instances that can sample VREFINT. */
|
||||
#define STM32_ADC_VREF_INSTANCE_MASK (1UL << 1)
|
||||
#endif /* defined(ADC_CHANNEL_VREFINT) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32MP1 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32MP1 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32MP1 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,422 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32u5 adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32U5 ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32U5. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32U5. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32U5. */
|
||||
#if defined(ADC_SAMPLETIME_814CYCLES)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_814CYCLES
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_814CYCLES) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32U5 driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 internal-channel routing policy for this STM32 series. */
|
||||
/** @brief STM32U5 default internal ADC source instance mask. */
|
||||
#define STM32_ADC_INTERNAL_DEFAULT_INSTANCE_MASK ((1UL << 0) | (1UL << 1))
|
||||
|
||||
#if defined(ADC_CHANNEL_TEMPSENSOR)
|
||||
/** @brief STM32U5 temperature sensor HAL ADC channel for the default internal route. */
|
||||
#define STM32_ADC_TEMP_HAL_CHANNEL ADC_CHANNEL_TEMPSENSOR
|
||||
#endif /* defined(ADC_CHANNEL_TEMPSENSOR) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VBAT)
|
||||
/** @brief STM32U5 VBAT HAL ADC channel for the default internal route. */
|
||||
#define STM32_ADC_VBAT_HAL_CHANNEL ADC_CHANNEL_VBAT
|
||||
#endif /* defined(ADC_CHANNEL_VBAT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VREFINT)
|
||||
/** @brief STM32U5 VREFINT HAL ADC channel for the multi-instance route. */
|
||||
#define STM32_ADC_VREF_HAL_CHANNEL ADC_CHANNEL_VREFINT
|
||||
/** @brief STM32U5 ADC instances that can sample VREFINT. */
|
||||
#define STM32_ADC_VREF_INSTANCE_MASK ((1UL << 0) | (1UL << 1) | (1UL << 3))
|
||||
#endif /* defined(ADC_CHANNEL_VREFINT) */
|
||||
|
||||
#if defined(ADC_CHANNEL_TEMPSENSOR_ADC4)
|
||||
/** @brief STM32U5 alternate temperature sensor HAL ADC channel. */
|
||||
#define STM32_ADC_TEMP_ALT_HAL_CHANNEL ADC_CHANNEL_TEMPSENSOR_ADC4
|
||||
/** @brief STM32U5 ADC instances that can sample the alternate temperature sensor channel. */
|
||||
#define STM32_ADC_TEMP_ALT_INSTANCE_MASK (1UL << 3)
|
||||
#endif /* defined(ADC_CHANNEL_TEMPSENSOR_ADC4) */
|
||||
|
||||
#if defined(ADC_CHANNEL_VBAT_ADC4)
|
||||
/** @brief STM32U5 alternate VBAT HAL ADC channel. */
|
||||
#define STM32_ADC_VBAT_ALT_HAL_CHANNEL ADC_CHANNEL_VBAT_ADC4
|
||||
/** @brief STM32U5 ADC instances that can sample the alternate VBAT channel. */
|
||||
#define STM32_ADC_VBAT_ALT_INSTANCE_MASK (1UL << 3)
|
||||
#endif /* defined(ADC_CHANNEL_VBAT_ADC4) */
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_NEEDS_ANALOG_SUPPLY 1
|
||||
#define STM32_ADC_VREF_NEEDS_INSTANCE 1
|
||||
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32U5 ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32U5 ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32U5 ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef BSP_USING_ADC4
|
||||
/** @brief Default STM32U5 ADC4 V2 object initializer. */
|
||||
#define ADC4_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc4", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC4, \
|
||||
}, \
|
||||
ADC4_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,368 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32wb adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32WB ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32WB. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32WB. */
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
|
||||
/** @brief Default ADC resolution for STM32 ADC V2. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32WB. */
|
||||
#if defined(ADC_SAMPLETIME_2CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_2CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_2CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32WB driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_HAS_SIMPLE_CALIBRATION 1
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32WB ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
/** @brief Default STM32WB ADC2 V2 object initializer. */
|
||||
#define ADC2_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
}, \
|
||||
ADC2_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
/** @brief Default STM32WB ADC3 V2 object initializer. */
|
||||
#define ADC3_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
}, \
|
||||
ADC3_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
@@ -0,0 +1,332 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-05-27 wdfk-prog add stm32wl adc v2 configuration
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file adc_config_v2.h
|
||||
* @brief STM32WL ADC V2 configuration defaults.
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_V2_H__
|
||||
#define __ADC_CONFIG_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Default ADC clock prescaler for STM32WL. */
|
||||
#if defined(ADC_CLOCK_SYNC_PCLK_DIV4)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_SYNC_PCLK_DIV4
|
||||
#elif defined(ADC_CLOCK_ASYNC_DIV1)
|
||||
#define ADC_DEFAULT_CLOCK_PRESCALER ADC_CLOCK_ASYNC_DIV1
|
||||
#endif /* defined(ADC_CLOCK_SYNC_PCLK_DIV4) */
|
||||
|
||||
/** @brief Default ADC data alignment for STM32WL. */
|
||||
#if defined(ADC_DATAALIGN_RIGHT)
|
||||
#define ADC_DEFAULT_DATA_ALIGN ADC_DATAALIGN_RIGHT
|
||||
#else
|
||||
#define ADC_DEFAULT_DATA_ALIGN 0U
|
||||
#endif /* defined(ADC_DATAALIGN_RIGHT) */
|
||||
|
||||
/** @brief Default ADC resolution for STM32WL. */
|
||||
#ifdef ADC_RESOLUTION_12B
|
||||
#define ADC_DEFAULT_RESOLUTION ADC_RESOLUTION_12B
|
||||
#else
|
||||
#define ADC_DEFAULT_RESOLUTION 0U
|
||||
#endif /* ADC_RESOLUTION_12B */
|
||||
|
||||
/** @brief Default ADC sampling time for STM32WL. */
|
||||
#if defined(ADC_SAMPLETIME_160CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_160CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_247CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_247CYCLES_5
|
||||
#elif defined(ADC_SAMPLETIME_640CYCLES_5)
|
||||
#define ADC_DEFAULT_SAMPLING_TIME ADC_SAMPLETIME_640CYCLES_5
|
||||
#else
|
||||
#define ADC_DEFAULT_SAMPLING_TIME 0U
|
||||
#endif /* defined(ADC_SAMPLETIME_160CYCLES_5) */
|
||||
|
||||
|
||||
/** @brief Maximum regular sequence length supported by the STM32WL driver. */
|
||||
#define STM32_ADC_MAX_SEQUENCE 16
|
||||
|
||||
/** @brief Whether sequence mode is compiled in. */
|
||||
#define STM32_ADC_USING_SEQUENCE 1
|
||||
|
||||
/** @brief Whether any ADC instance requests a stream DMA backend. */
|
||||
#if defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || \
|
||||
defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA)
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 1
|
||||
#else
|
||||
#define STM32_ADC_HAS_STREAM_DMA_BSP 0
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) || defined(BSP_ADC2_USING_DMA) || defined(BSP_ADC3_USING_DMA) || defined(BSP_ADC4_USING_DMA) */
|
||||
|
||||
/** @brief Whether stream mode is compiled in through the STM32 DMA-backed backend. */
|
||||
#if defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP
|
||||
#define STM32_ADC_USING_STREAM 1
|
||||
#else
|
||||
#define STM32_ADC_USING_STREAM 0
|
||||
#endif /* defined(RT_ADC_USING_STREAM) && defined(HAL_DMA_MODULE_ENABLED) && STM32_ADC_HAS_STREAM_DMA_BSP */
|
||||
|
||||
/** @brief Whether the compiled STM32 ADC stream backend uses DMA transport. */
|
||||
#define STM32_ADC_USING_DMA_STREAM STM32_ADC_USING_STREAM
|
||||
|
||||
#if STM32_ADC_USING_STREAM
|
||||
#if defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ)
|
||||
#if defined(ADC1_DMA_REQUEST)
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE ADC1_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC1_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC1_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_CHANNEL)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
ADC1_DMA_CHANNEL,
|
||||
STM32_ADC1_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC1_DMA_REQUEST)
|
||||
#define ADC1_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC1_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC1_DMA_INSTANCE,
|
||||
ADC1_DMA_RCC,
|
||||
ADC1_DMA_IRQ,
|
||||
0U,
|
||||
ADC1_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC1_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC1_USING_DMA) && defined(ADC1_DMA_INSTANCE) && defined(ADC1_DMA_RCC) && defined(ADC1_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ)
|
||||
#if defined(ADC2_DMA_REQUEST)
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE ADC2_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC2_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC2_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_CHANNEL)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
ADC2_DMA_CHANNEL,
|
||||
STM32_ADC2_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC2_DMA_REQUEST)
|
||||
#define ADC2_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC2_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC2_DMA_INSTANCE,
|
||||
ADC2_DMA_RCC,
|
||||
ADC2_DMA_IRQ,
|
||||
0U,
|
||||
ADC2_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC2_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC2_USING_DMA) && defined(ADC2_DMA_INSTANCE) && defined(ADC2_DMA_RCC) && defined(ADC2_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ)
|
||||
#if defined(ADC3_DMA_REQUEST)
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE ADC3_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC3_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC3_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_CHANNEL)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
ADC3_DMA_CHANNEL,
|
||||
STM32_ADC3_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC3_DMA_REQUEST)
|
||||
#define ADC3_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC3_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC3_DMA_INSTANCE,
|
||||
ADC3_DMA_RCC,
|
||||
ADC3_DMA_IRQ,
|
||||
0U,
|
||||
ADC3_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC3_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC3_USING_DMA) && defined(ADC3_DMA_INSTANCE) && defined(ADC3_DMA_RCC) && defined(ADC3_DMA_IRQ) */
|
||||
|
||||
#if defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ)
|
||||
#if defined(ADC4_DMA_REQUEST)
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE ADC4_DMA_REQUEST
|
||||
#else
|
||||
#define STM32_ADC4_DMA_REQUEST_VALUE 0U
|
||||
#endif /* defined(ADC4_DMA_REQUEST) */
|
||||
|
||||
#if defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_CHANNEL)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
ADC4_DMA_CHANNEL,
|
||||
STM32_ADC4_DMA_REQUEST_VALUE,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#elif defined(ADC4_DMA_REQUEST)
|
||||
#define ADC4_V2_HAS_DMA_CONFIG 1
|
||||
static const struct stm32_dma_config ADC4_DMA_CONFIG =
|
||||
STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(ADC4_DMA_INSTANCE,
|
||||
ADC4_DMA_RCC,
|
||||
ADC4_DMA_IRQ,
|
||||
0U,
|
||||
ADC4_DMA_REQUEST,
|
||||
STM32_DMA_DEFAULT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_PREEMPT_PRIORITY,
|
||||
STM32_DMA_DEFAULT_SUB_PRIORITY);
|
||||
#endif /* defined(STM32_DMA_USES_GPDMA) && defined(ADC4_DMA_REQUEST) */
|
||||
#endif /* defined(BSP_ADC4_USING_DMA) && defined(ADC4_DMA_INSTANCE) && defined(ADC4_DMA_RCC) && defined(ADC4_DMA_IRQ) */
|
||||
|
||||
#endif /* STM32_ADC_USING_STREAM */
|
||||
|
||||
#if defined(ADC1_V2_HAS_DMA_CONFIG)
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD .dma_rx = &ADC1_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC1_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC1_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC2_V2_HAS_DMA_CONFIG)
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD .dma_rx = &ADC2_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC2_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC2_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC3_V2_HAS_DMA_CONFIG)
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD .dma_rx = &ADC3_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC3_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC3_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
#if defined(ADC4_V2_HAS_DMA_CONFIG)
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD .dma_rx = &ADC4_DMA_CONFIG,
|
||||
#else
|
||||
#define ADC4_V2_DMA_CONFIG_FIELD
|
||||
#endif /* defined(ADC4_V2_HAS_DMA_CONFIG) */
|
||||
|
||||
|
||||
|
||||
/* ADC V2 HAL feature policy for this STM32 series. */
|
||||
#if defined(ADC_DEFAULT_DATA_ALIGN)
|
||||
#define STM32_ADC_HAS_INIT_DATA_ALIGN 1
|
||||
#endif /* defined(ADC_DEFAULT_DATA_ALIGN) */
|
||||
|
||||
#if defined(ADC_EXTERNALTRIGCONVEDGE_NONE)
|
||||
#define STM32_ADC_HAS_INIT_EXT_TRIG_EDGE 1
|
||||
#endif /* defined(ADC_EXTERNALTRIGCONVEDGE_NONE) */
|
||||
|
||||
#define STM32_ADC_HAS_INIT_DMA_CONT_REQUESTS 1
|
||||
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_CONVERSION 1
|
||||
#define STM32_ADC_HAS_INIT_NBR_OF_DISC_CONVERSION 1
|
||||
|
||||
#if defined(ADC_EOC_SINGLE_CONV)
|
||||
#define STM32_ADC_HAS_INIT_EOC_SELECTION 1
|
||||
#endif /* defined(ADC_EOC_SINGLE_CONV) */
|
||||
|
||||
#define STM32_ADC_HAS_SIMPLE_CALIBRATION 1
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
/** @brief Default STM32WL ADC1 V2 object initializer. */
|
||||
#define ADC1_V2_CONFIG \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.config = \
|
||||
{ \
|
||||
.sampling_time = ADC_DEFAULT_SAMPLING_TIME, \
|
||||
.resolution = ADC_DEFAULT_RESOLUTION, \
|
||||
.data_align = ADC_DEFAULT_DATA_ALIGN, \
|
||||
.input_modes = RT_ADC_INPUT_MODE_SINGLE_ENDED, \
|
||||
.oversampling_ratio = 0U, \
|
||||
.oversampling_right_shift = 0U, \
|
||||
}, \
|
||||
.handle = \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
}, \
|
||||
ADC1_V2_DMA_CONFIG_FIELD \
|
||||
}
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __ADC_CONFIG_V2_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-21 wdfk-prog add stm32 adc v2 driver declarations
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file drv_adc_v2.h
|
||||
* @brief STM32 ADC V2 driver declarations.
|
||||
*/
|
||||
|
||||
#ifndef __DRV_ADC_V2_H__
|
||||
#define __DRV_ADC_V2_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#if defined(RT_USING_ADC_V2)
|
||||
#include <board.h>
|
||||
#include <rtdevice.h>
|
||||
#include <drivers/adc_v2.h>
|
||||
|
||||
/**
|
||||
* @brief STM32 ADC backend private device configuration.
|
||||
*
|
||||
* @note The fields map directly to STM32 HAL ADC initialization values. Use
|
||||
* ADC_RESOLUTION_xxx, ADC_OVERSAMPLING_RATIO_xxx, and
|
||||
* ADC_RIGHTBITSHIFT_xxx macros from the active STM32 HAL headers when
|
||||
* the corresponding feature exists. The configuration should be updated
|
||||
* before opening the ADC device.
|
||||
*/
|
||||
struct stm32_adc_private_cfg
|
||||
{
|
||||
rt_uint32_t sampling_time; /**< HAL ADC sampling-time value; 0 uses ADC_DEFAULT_SAMPLING_TIME. */
|
||||
rt_uint32_t resolution; /**< HAL ADC resolution value; 0 uses ADC_DEFAULT_RESOLUTION. */
|
||||
rt_uint32_t data_align; /**< HAL ADC data-alignment value; 0 uses ADC_DEFAULT_DATA_ALIGN. */
|
||||
rt_uint8_t input_modes; /**< Bit mask of enum rt_adc_input_mode values; 0 uses single-ended input. */
|
||||
rt_uint8_t reserved[3]; /**< Reserved for alignment and future STM32 backend options. */
|
||||
rt_uint32_t oversampling_ratio; /**< HAL ADC oversampling ratio; 0 disables hardware oversampling. */
|
||||
rt_uint32_t oversampling_right_shift; /**< HAL ADC oversampling right shift; 0 uses no right shift. */
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @brief Initialize and register STM32 ADC devices.
|
||||
* @return Operation status.
|
||||
*/
|
||||
int stm32_adc_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* defined(RT_USING_ADC_V2) */
|
||||
|
||||
#endif /* __DRV_ADC_V2_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -6,7 +6,7 @@
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 SummerGift first version
|
||||
* 2020-10-14 PeakRacing Porting for stm32wbxx
|
||||
* 2020-10-14 PeakRacing Porting for stm32wbxx
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
@@ -18,7 +18,7 @@
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#if defined(SOC_SERIES_STM32F0)
|
||||
#include "f0/dma_config.h"
|
||||
@@ -27,82 +27,92 @@ extern "C" {
|
||||
#include "f0/tim_config.h"
|
||||
#include "f0/pwm_config.h"
|
||||
#include "f0/adc_config.h"
|
||||
#include "f0/adc_config_v2.h"
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
#include "f1/dma_config.h"
|
||||
#include "f1/uart_config.h"
|
||||
#include "f1/spi_config.h"
|
||||
#include "f1/adc_config.h"
|
||||
#include "f1/adc_config_v2.h"
|
||||
#include "f1/tim_config.h"
|
||||
#include "f1/sdio_config.h"
|
||||
#include "f1/pwm_config.h"
|
||||
#include "f1/usbd_config.h"
|
||||
#include "f1/i2c_hard_config.h"
|
||||
#include "f1/pulse_encoder_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F2)
|
||||
#elif defined(SOC_SERIES_STM32F2)
|
||||
#include "f2/dma_config.h"
|
||||
#include "f2/uart_config.h"
|
||||
#include "f2/spi_config.h"
|
||||
#include "f2/adc_config.h"
|
||||
#include "f2/adc_config_v2.h"
|
||||
#include "f2/tim_config.h"
|
||||
#include "f2/sdio_config.h"
|
||||
#include "f2/pwm_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F3)
|
||||
#elif defined(SOC_SERIES_STM32F3)
|
||||
#include "f3/uart_config.h"
|
||||
#include "f3/tim_config.h"
|
||||
#include "f3/pwm_config.h"
|
||||
#include "f3/dma_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F4)
|
||||
#include "f3/adc_config_v2.h"
|
||||
#elif defined(SOC_SERIES_STM32F4)
|
||||
#include "f4/dma_config.h"
|
||||
#include "f4/uart_config.h"
|
||||
#include "f4/spi_config.h"
|
||||
#include "f4/qspi_config.h"
|
||||
#include "f4/usbd_config.h"
|
||||
#include "f4/adc_config.h"
|
||||
#include "f4/adc_config_v2.h"
|
||||
#include "f4/dac_config.h"
|
||||
#include "f4/tim_config.h"
|
||||
#include "f4/sdio_config.h"
|
||||
#include "f4/pwm_config.h"
|
||||
#include "f4/i2c_hard_config.h"
|
||||
#include "f4/pulse_encoder_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F7)
|
||||
#elif defined(SOC_SERIES_STM32F7)
|
||||
#include "f7/dma_config.h"
|
||||
#include "f7/uart_config.h"
|
||||
#include "f7/spi_config.h"
|
||||
#include "f7/qspi_config.h"
|
||||
#include "f7/adc_config.h"
|
||||
#include "f7/adc_config_v2.h"
|
||||
#include "f7/tim_config.h"
|
||||
#include "f7/sdio_config.h"
|
||||
#include "f7/pwm_config.h"
|
||||
#elif defined(SOC_SERIES_STM32L0)
|
||||
#elif defined(SOC_SERIES_STM32L0)
|
||||
#include "l0/dma_config.h"
|
||||
#include "l0/uart_config.h"
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
#include "l0/adc_config_v2.h"
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
#include "l4/dma_config.h"
|
||||
#include "l4/uart_config.h"
|
||||
#include "l4/spi_config.h"
|
||||
#include "l4/qspi_config.h"
|
||||
#include "l4/adc_config.h"
|
||||
#include "l4/adc_config_v2.h"
|
||||
#include "l4/dac_config.h"
|
||||
#include "l4/tim_config.h"
|
||||
#include "l4/sdio_config.h"
|
||||
#include "l4/pwm_config.h"
|
||||
#include "l4/usbd_config.h"
|
||||
#elif defined(SOC_SERIES_STM32L5)
|
||||
#elif defined(SOC_SERIES_STM32L5)
|
||||
#include "l5/dma_config.h"
|
||||
#include "l5/uart_config.h"
|
||||
#include "l5/spi_config.h"
|
||||
#include "l5/qspi_config.h"
|
||||
#include "l5/adc_config.h"
|
||||
#include "l5/adc_config_v2.h"
|
||||
#include "l5/dac_config.h"
|
||||
#include "l5/tim_config.h"
|
||||
#include "l5/sdio_config.h"
|
||||
#include "l5/pwm_config.h"
|
||||
#include "l5/usbd_config.h"
|
||||
#elif defined(SOC_SERIES_STM32G0)
|
||||
#elif defined(SOC_SERIES_STM32G0)
|
||||
#include "g0/dma_config.h"
|
||||
#include "g0/uart_config.h"
|
||||
#include "g0/spi_config.h"
|
||||
#include "g0/adc_config.h"
|
||||
#include "g0/adc_config_v2.h"
|
||||
#include "g0/tim_config.h"
|
||||
#include "g0/pwm_config.h"
|
||||
#include "g0/usbd_config.h"
|
||||
@@ -113,16 +123,18 @@ extern "C" {
|
||||
#include "g4/qspi_config.h"
|
||||
#include "g4/usbd_config.h"
|
||||
#include "g4/adc_config.h"
|
||||
#include "g4/adc_config_v2.h"
|
||||
#include "g4/tim_config.h"
|
||||
#include "g4/sdio_config.h"
|
||||
#include "g4/pwm_config.h"
|
||||
#include "g4/pulse_encoder_config.h"
|
||||
#elif defined(SOC_SERIES_STM32H7)
|
||||
#elif defined(SOC_SERIES_STM32H7)
|
||||
#include "h7/dma_config.h"
|
||||
#include "h7/uart_config.h"
|
||||
#include "h7/spi_config.h"
|
||||
#include "h7/qspi_config.h"
|
||||
#include "h7/adc_config.h"
|
||||
#include "h7/adc_config_v2.h"
|
||||
#include "h7/dac_config.h"
|
||||
#include "h7/tim_config.h"
|
||||
#include "h7/lptim_config.h"
|
||||
@@ -130,23 +142,23 @@ extern "C" {
|
||||
#include "h7/pwm_config.h"
|
||||
#include "h7/usbd_config.h"
|
||||
#include "h7/i2c_hard_config.h"
|
||||
|
||||
#elif defined(SOC_SERIES_STM32H7RS)
|
||||
#elif defined(SOC_SERIES_STM32H7RS)
|
||||
#include "h7/dma_config.h"
|
||||
#include "h7/uart_config.h"
|
||||
#include "h7/spi_config.h"
|
||||
#include "h7/adc_config.h"
|
||||
#include "h7rs/adc_config_v2.h"
|
||||
#include "h7/dac_config.h"
|
||||
#include "h7/tim_config.h"
|
||||
#include "h7/pwm_config.h"
|
||||
#include "h7/usbd_config.h"
|
||||
|
||||
#elif defined(SOC_SERIES_STM32U5)
|
||||
#include "u5/dma_config.h"
|
||||
#include "u5/uart_config.h"
|
||||
#include "u5/spi_config.h"
|
||||
#include "u5/qspi_config.h"
|
||||
#include "u5/adc_config.h"
|
||||
#include "u5/adc_config_v2.h"
|
||||
#include "u5/dac_config.h"
|
||||
#include "u5/tim_config.h"
|
||||
#include "u5/sdio_config.h"
|
||||
@@ -156,22 +168,26 @@ extern "C" {
|
||||
#include "h5/uart_config.h"
|
||||
#include "h5/pwm_config.h"
|
||||
#include "h5/adc_config.h"
|
||||
#elif defined(SOC_SERIES_STM32MP1)
|
||||
#include "h5/adc_config_v2.h"
|
||||
#elif defined(SOC_SERIES_STM32MP1)
|
||||
#include "mp1/dma_config.h"
|
||||
#include "mp1/uart_config.h"
|
||||
#include "mp1/qspi_config.h"
|
||||
#include "mp1/spi_config.h"
|
||||
#include "mp1/adc_config.h"
|
||||
#include "mp1/adc_config_v2.h"
|
||||
#include "mp1/dac_config.h"
|
||||
#include "mp1/tim_config.h"
|
||||
#include "mp1/pwm_config.h"
|
||||
#elif defined(SOC_SERIES_STM32WL)
|
||||
#elif defined(SOC_SERIES_STM32WL)
|
||||
#include "wl/dma_config.h"
|
||||
#include "wl/uart_config.h"
|
||||
#include "wl/spi_config.h"
|
||||
#include "wl/tim_config.h"
|
||||
#elif defined(SOC_SERIES_STM32WB)
|
||||
#include "wl/adc_config_v2.h"
|
||||
#elif defined(SOC_SERIES_STM32WB)
|
||||
#include "wb/adc_config.h"
|
||||
#include "wb/adc_config_v2.h"
|
||||
#include "wb/dma_config.h"
|
||||
#include "wb/pwm_config.h"
|
||||
#include "wb/qspi_config.h"
|
||||
@@ -179,10 +195,10 @@ extern "C" {
|
||||
#include "wb/tim_config.h"
|
||||
#include "wb/uart_config.h"
|
||||
#include "wb/usbd_config.h"
|
||||
#endif
|
||||
#endif /* defined(SOC_SERIES_STM32F0) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
#endif /* __DRV_CONFIG_H__ */
|
||||
@@ -265,6 +265,9 @@ struct stm32_dma_config
|
||||
#define STM32_DMA_RX_WORD_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \
|
||||
STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_PERIPH_TO_MEMORY, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_WORD, DMA_MDATAALIGN_WORD, DMA_NORMAL)
|
||||
|
||||
#define STM32_DMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \
|
||||
STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_PERIPH_TO_MEMORY, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_WORD, DMA_MDATAALIGN_WORD, DMA_CIRCULAR)
|
||||
|
||||
#define STM32_DMA_TX_WORD_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _channel, _request, _priority, _preempt_priority, _sub_priority) \
|
||||
STM32_DMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_channel), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_MEMORY_TO_PERIPH, DMA_PINC_DISABLE, DMA_MINC_ENABLE, DMA_PDATAALIGN_WORD, DMA_MDATAALIGN_WORD, DMA_NORMAL)
|
||||
|
||||
@@ -305,6 +308,9 @@ struct stm32_dma_config
|
||||
#define STM32_GPDMA_RX_WORD_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _request, _priority, _preempt_priority, _sub_priority) \
|
||||
STM32_GPDMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_PERIPH_TO_MEMORY, DMA_SINC_FIXED, DMA_DINC_INCREMENTED, DMA_SRC_DATAWIDTH_WORD, DMA_DEST_DATAWIDTH_WORD, DMA_NORMAL)
|
||||
|
||||
#define STM32_GPDMA_RX_WORD_CIRCULAR_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _request, _priority, _preempt_priority, _sub_priority) \
|
||||
STM32_GPDMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_PERIPH_TO_MEMORY, DMA_SINC_FIXED, DMA_DINC_INCREMENTED, DMA_SRC_DATAWIDTH_WORD, DMA_DEST_DATAWIDTH_WORD, DMA_CIRCULAR)
|
||||
|
||||
#define STM32_GPDMA_TX_WORD_CONFIG_INIT_EX(_instance, _dma_rcc, _dma_irq, _request, _priority, _preempt_priority, _sub_priority) \
|
||||
STM32_GPDMA_CONFIG_INIT_EX((_instance), (_dma_rcc), (_dma_irq), (_request), (_priority), (_preempt_priority), (_sub_priority), DMA_MEMORY_TO_PERIPH, DMA_SINC_INCREMENTED, DMA_DINC_FIXED, DMA_SRC_DATAWIDTH_WORD, DMA_DEST_DATAWIDTH_WORD, DMA_NORMAL)
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -155,6 +155,22 @@ online-packages.ai.llmchat:
|
||||
- CONFIG_PKG_USING_LLMCHAT=y
|
||||
- CONFIG_PKG_USING_LLMCHAT_LATEST_VERSION=y
|
||||
# ------ peripheral CI ------
|
||||
peripheral.adc_v2:
|
||||
kconfig:
|
||||
- CONFIG_RT_USING_ADC_V2=y
|
||||
- CONFIG_BSP_USING_ADC_V2=y
|
||||
- CONFIG_BSP_USING_ADC1=y
|
||||
- CONFIG_RT_ADC_V2_USING_MSH=y
|
||||
- CONFIG_RT_ADC_USING_STREAM=y
|
||||
- CONFIG_RT_ADC_STREAM_USING_LATEST=y
|
||||
- CONFIG_RT_ADC_STREAM_USING_FIFO=y
|
||||
- CONFIG_BSP_ADC1_USING_DMA=y
|
||||
- CONFIG_BSP_ADC_USING_TRIGGER=y
|
||||
- CONFIG_BSP_ADC_USING_TIMER_TRIGGER=y
|
||||
- CONFIG_BSP_ADC_USING_ANALOG_COMPARE_TRIGGER=y
|
||||
- CONFIG_RT_USING_CLOCK_TIME=y
|
||||
- CONFIG_BSP_USING_TIM=y
|
||||
- CONFIG_BSP_USING_TIM11=y
|
||||
peripheral.aht21:
|
||||
kconfig:
|
||||
- CONFIG_BSP_USING_AHT21=y
|
||||
|
||||
Reference in New Issue
Block a user