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[bsp][imxrt1052] fixed update sdk bug: set lcdif clock to 9.3 and astyle the file

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This commit is contained in:
liang yongxiang
2018-06-12 20:14:21 +08:00
parent c5a28a65db
commit 92d3ae35a5
1 changed files with 145 additions and 129 deletions
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bsp/imxrt1052-evk/drivers/drv_lcd.c
+26 -10
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@@ -47,15 +47,33 @@ static rt_err_t rt1050_lcd_init(rt_device_t device)
rt_memset(frame_buffer, 0x00, sizeof(frame_buffer));
/* DeInit Video PLL. */
CLOCK_DeinitVideoPll();
/* Bypass Video PLL. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
/* Set divider for Video PLL. */
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
/* Enable Video PLL output. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/*
* Initialize the Video PLL.
* Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
*/
clock_video_pll_config_t config =
{
.loopDivider = 31, .postDivider = 8, .numerator = 0, .denominator = 1,
};
CLOCK_InitVideoPll(&config);
/*
* 000 derive clock from PLL2
* 001 derive clock from PLL3 PFD3
* 010 derive clock from PLL5
* 011 derive clock from PLL2 PFD0
* 100 derive clock from PLL2 PFD1
* 101 derive clock from PLL3 PFD1
*/
CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4);
CLOCK_SetDiv(kCLOCK_LcdifDiv, 1);
/* GPIO */
CLOCK_EnableClock(kCLOCK_Iomuxc);
@@ -186,10 +204,8 @@ int rt_hw_lcd_init(void)
lcd.device.user_data = (void *)&lcd.info;
rt1050_lcd_init(&lcd.device);
ret = rt_device_register(&lcd.device, "lcd", RT_DEVICE_FLAG_RDWR);
return ret;
}
//INIT_DEVICE_EXPORT(rt_hw_lcd_init);
INIT_DEVICE_EXPORT(rt_hw_lcd_init);