From 902fe8bd5e78e64e8ae0cd70399387081cd6fe47 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E9=A9=AC=E6=B5=A9=E7=84=B6?=
 <43113435+0xcccccccccccc@users.noreply.github.com>
Date: Sun, 17 Jan 2021 23:33:48 +0800
Subject: [PATCH] Update drv_spi.c

Bug Fixed : clock division cannot been adjusted as expected due to wrong register configuration.
---
 bsp/ls2kdev/drivers/drv_spi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/bsp/ls2kdev/drivers/drv_spi.c b/bsp/ls2kdev/drivers/drv_spi.c
index 3f3ad90802..5a42acbee8 100644
--- a/bsp/ls2kdev/drivers/drv_spi.c
+++ b/bsp/ls2kdev/drivers/drv_spi.c
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author                   Notes
  * 2020-10-28     0xcccccccccccc           Initial Version
+ * 2021-01-17     0xcccccccccccc           Bug Fixed : clock division cannot been adjusted as expected due to wrong register configuration.
  */
 /**
  * @addtogroup ls2k
@@ -21,11 +22,11 @@
 #ifdef RT_USING_SPI
 static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha)
 {
-    SET_SPI(SPSR, 0xc0 | (spre_spr & 0b00000011));
+    SET_SPI(SPSR, 0xc0); 
     SET_SPI(PARAM, 0x40);
     SET_SPI(PARAM2, 0x01);
     SET_SPI(SPER, (spre_spr & 0b00001100) >> 2);
-    SET_SPI(SPCR, 0x50 | copl << 3 | cpha << 2);
+    SET_SPI(SPCR, 0x50 | copl << 3 | cpha << 2 | (spre_spr & 0b00000011)); 
     SET_SPI(SOFTCS, 0xff);
 }