mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-23 04:04:15 +08:00
[bsp][c28x] add support to not disable global interrupt in context-switch to enable zero-latency isr for critical interrupts.
This commit is contained in:
Yunjie Gu
+251
-179
@@ -11,37 +11,208 @@
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; 2019-12-05 xiaolifan add support for hardware fpu32
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; 2022-06-21 guyunjie trim pendsv (RTOSINT_Handler)
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; 2022-08-24 guyunjie fix bugs in context switching
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; 2022-10-15 guyunjie add zero-latency interrupt
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.ref _rt_interrupt_to_thread
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.ref _rt_interrupt_from_thread
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.ref _rt_thread_switch_interrupt_flag
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.ref rt_interrupt_to_thread
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.ref rt_interrupt_from_thread
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.ref rt_thread_switch_interrupt_flag
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.def _RTOSINT_Handler
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.def _rt_hw_get_st0
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.def _rt_hw_get_st1
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.def _rt_hw_calc_csb
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.def _rt_hw_context_switch_interrupt
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.def _rt_hw_context_switch
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.def _rt_hw_context_switch_to
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.def _rt_hw_interrupt_thread_switch
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.def _rt_hw_interrupt_disable
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.def _rt_hw_interrupt_enable
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.def rtosint_handler
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.def rt_hw_get_st0
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.def rt_hw_get_st1
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.def rt_hw_calc_csb
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.def rt_hw_context_switch_interrupt
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.def rt_hw_context_switch
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.def rt_hw_context_switch_to
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.def rt_hw_interrupt_thread_switch
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.def rt_hw_interrupt_disable
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.def rt_hw_interrupt_enable
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;workaround for importing fpu settings from the compiler
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;importing settings from compiler and config
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.cdecls C,NOLIST
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%{
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#include <rtconfig.h>
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#ifdef __TMS320C28XX_FPU32__
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#define __FPU32__ 1
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#else
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#define __FPU32__ 0
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#endif
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#ifdef __TMS320C28XX_FPU64__
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#define __FPU64__ 1
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#else
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#define __FPU64__ 0
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#endif
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#ifdef __TMS320C28XX_VCRC__
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#define __VCRC__ 1
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#else
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#define __VCRC__ 0
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#endif
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#ifdef RT_USING_ZERO_LATENCY
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#define ZERO_LATENCY 1
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#ifndef ZERO_LATENCY_INT_MASK
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#error ZERO_LATENCY_INT_MASK must be defined for zero latency interrupt
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#elif ZERO_LATENCY_INT_MASK & 0x8000
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#error RTOS bit (0x8000) must not be set in ZERO_LATENCY_INT_MASK
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#endif
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#else
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#define ZERO_LATENCY 0
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#endif
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%}
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RT_CTX_SAVE .macro
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.text
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.newblock
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;
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; rt_base_t rt_hw_interrupt_disable();
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;
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.asmfunc
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rt_hw_interrupt_disable:
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.if ZERO_LATENCY
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MOV AL, IER
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AND IER, #ZERO_LATENCY_INT_MASK
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.else
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PUSH ST1
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SETC INTM
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POP AL
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.endif
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MOV AH, #0
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LRETR
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.endasmfunc
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;
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; void rt_hw_interrupt_enable(rt_base_t level);
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;
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.asmfunc
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rt_hw_interrupt_enable:
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.if ZERO_LATENCY
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MOV IER, AL
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.else
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PUSH AL
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POP ST1
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.endif
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LRETR
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.endasmfunc
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;
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; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; ACC --> from
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; SP[4] --> to
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;
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.asmfunc
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rt_hw_context_switch_interrupt:
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; ACC, XAR4-7 are "save on call" following TI C28x C/C++ compiler convention
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; and therefore can be used in a function without being saved on stack first
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; (the compiler has already saved it before the call).
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; Reference: TMS320C28x Optimizing CC++ Compiler
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; note this convention is only applicable to normal functions not to isrs
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MOVL XAR6, ACC
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MOVL XAR4, *-SP[4]
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; set rt_thread_switch_interrupt_flag to 1
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MOVL XAR5, #rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR5
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BF reswitch2, NEQ ; ACC!=0
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MOVB ACC, #1
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MOVL *XAR5, ACC
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MOVL XAR5, #rt_interrupt_from_thread ; set rt_interrupt_from_thread
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MOVL *XAR5, XAR6
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reswitch2:
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MOVL XAR5, #rt_interrupt_to_thread ; set rt_interrupt_to_thread
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MOVL *XAR5, XAR4
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LRETR
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.endasmfunc
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;
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; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; ACC --> from
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; SP[4] --> to
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;
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.asmfunc
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rt_hw_context_switch:
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MOVL XAR6, ACC
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MOVL XAR4, *-SP[4]
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; set rt_thread_switch_interrupt_flag to 1
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MOVL XAR5, #rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR5
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BF reswitch1, NEQ ; ACC!=0
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MOVB ACC, #1
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MOVL *XAR5, ACC
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MOVL XAR5, #rt_interrupt_from_thread ; set rt_interrupt_from_thread
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MOVL *XAR5, XAR6
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reswitch1:
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MOVL XAR5, #rt_interrupt_to_thread ; set rt_interrupt_to_thread
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MOVL *XAR5, XAR4
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OR IFR, #0x8000
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LRETR
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.endasmfunc
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;
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * ACC --> to
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;
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.asmfunc
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rt_hw_context_switch_to:
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; get to thread
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MOVL XAR5, #rt_interrupt_to_thread
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MOVL *XAR5, ACC
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; set from thread to 0
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MOVL XAR5, #rt_interrupt_from_thread
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MOVL XAR4, #0
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MOVL *XAR5, XAR4
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; set interrupt flag to 1
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MOVL XAR5, #rt_thread_switch_interrupt_flag
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MOVL XAR4, #1
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MOVL *XAR5, XAR4
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; trigger rtos interrupt
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OR IFR, #0x8000
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OR IER, #0x8000
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CLRC INTM
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; never reach here!
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.endasmfunc
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.asmfunc
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rtosint_handler:
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.if ZERO_LATENCY
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; mask out non-critical interrupts and enable global interrupt
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; so rtosint_handler won't block critical interrupts
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AND IER, #ZERO_LATENCY_INT_MASK
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CLRC INTM
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.endif
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MOVL ACC, *-SP[4]
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MOV AR0, AL ; save original IER
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PUSH AR1H:AR0H
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PUSH XAR2
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; get rt_thread_switch_interrupt_flag
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MOVL XAR1, #rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR1
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BF rtosint_exit, EQ ; rtos_int already handled
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; clear rt_thread_switch_interrupt_flag to 0
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MOVL XAR2, #0
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MOVL *XAR1, XAR2
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MOVL XAR1, #rt_interrupt_from_thread
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MOVL ACC, *XAR1
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BF switch_to_thread, EQ ; skip register save at the first time
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PUSH XAR3
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PUSH XAR4
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PUSH XAR5
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@@ -63,20 +234,63 @@ RT_CTX_SAVE .macro
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MOV32 *SP++, R7H
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.endif
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.endm
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.if __FPU64__
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MOV32 *SP++, R0L
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MOV32 *SP++, R1L
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MOV32 *SP++, R2L
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MOV32 *SP++, R3L
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MOV32 *SP++, R4L
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MOV32 *SP++, R5L
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MOV32 *SP++, R6L
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MOV32 *SP++, R7L
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.endif
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.if __VCRC__
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VMOV32 *SP++, VCRC
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VMOV32 *SP++, VSTATUS
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VMOV32 *SP++, VCRCPOLY
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VMOV32 *SP++, VCRCSIZE
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.endif
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RT_CTX_RESTORE .macro
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MOVL ACC, *XAR1
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MOVL XAR1, ACC
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MOVZ AR2, @SP ; get from thread stack pointer
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MOVL *XAR1, XAR2 ; update from thread stack pointer
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switch_to_thread:
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MOVL XAR1, #rt_interrupt_to_thread
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MOVL ACC, *XAR1
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MOVL XAR1, ACC
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MOVL ACC, *XAR1
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MOV @SP, AL ; load thread stack pointer
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.if __VCRC__
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VMOV32 VCRCSIZE, *--SP
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VMOV32 VCRCPOLY, *--SP
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VMOV32 VSTATUS, *--SP
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VMOV32 VCRC, *--SP
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.endif
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.if __FPU64__
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MOV32 R7L, *--SP
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MOV32 R6L, *--SP
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MOV32 R5L, *--SP
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MOV32 R4L, *--SP
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MOV32 R3L, *--SP
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MOV32 R2L, *--SP
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MOV32 R1L, *--SP
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MOV32 R0L, *--SP
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.endif
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.if __FPU32__
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MOV32 R7H, *--SP, UNCF
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MOV32 R6H, *--SP, UNCF
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MOV32 R5H, *--SP, UNCF
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MOV32 R4H, *--SP, UNCF
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MOV32 R3H, *--SP, UNCF
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MOV32 R2H, *--SP, UNCF
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MOV32 R1H, *--SP, UNCF
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MOV32 R0H, *--SP, UNCF
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MOV32 R7H, *--SP
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MOV32 R6H, *--SP
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MOV32 R5H, *--SP
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MOV32 R4H, *--SP
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MOV32 R3H, *--SP
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MOV32 R2H, *--SP
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MOV32 R1H, *--SP
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MOV32 R0H, *--SP
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MOV32 STF, *--SP
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POP RB
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.endif
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@@ -88,172 +302,30 @@ RT_CTX_RESTORE .macro
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POP XAR5
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POP XAR4
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POP XAR3
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POP XAR2
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MOVZ AR0 , @SP
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SUBB XAR0, #6
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MOVL ACC , *XAR0
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AND ACC, #0xFFFF << 16
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MOV AL, IER
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MOVL *XAR0, ACC
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POP AR1H:AR0H
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.endm
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.text
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.newblock
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;
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; rt_base_t rt_hw_interrupt_disable();
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;
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.asmfunc
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_rt_hw_interrupt_disable:
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PUSH ST1
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SETC INTM,DBGM
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MOV AL, *--SP
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LRETR
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.endasmfunc
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;
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; void rt_hw_interrupt_enable(rt_base_t level);
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;
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.asmfunc
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_rt_hw_interrupt_enable:
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MOV *SP++, AL
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POP ST1
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LRETR
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.endasmfunc
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;
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; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; ACC --> from
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; SP[4] --> to
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;
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.asmfunc
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_rt_hw_context_switch_interrupt:
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MOVL XAR0, ACC
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MOVL XAR4, *-SP[4]
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; set rt_thread_switch_interrupt_flag to 1
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MOVL XAR5, #_rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR5
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BF _reswitch, NEQ ; ACC!=0
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MOVB ACC, #1
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MOVL *XAR5, ACC
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MOVL XAR5, #_rt_interrupt_from_thread ; set rt_interrupt_from_thread
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MOVL *XAR5, XAR0
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_reswitch:
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MOVL XAR5, #_rt_interrupt_to_thread ; set rt_interrupt_to_thread
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MOVL *XAR5, XAR4
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LRETR
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.endasmfunc
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;
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; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; ACC --> from
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; SP[4] --> to
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;
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.asmfunc
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_rt_hw_context_switch:
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MOVL XAR0, ACC
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MOVL XAR4, *-SP[4]
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; set rt_thread_switch_interrupt_flag to 1
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MOVL XAR5, #_rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR5
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BF _reswitch2, NEQ ; ACC!=0
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MOVB ACC, #1
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MOVL *XAR5, ACC
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MOVL XAR5, #_rt_interrupt_from_thread ; set rt_interrupt_from_thread
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MOVL *XAR5, XAR0
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_reswitch2:
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MOVL XAR5, #_rt_interrupt_to_thread ; set rt_interrupt_to_thread
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MOVL *XAR5, XAR4
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TRAP #16
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LRETR
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.endasmfunc
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;
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * ACC --> to
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;
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.asmfunc
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_rt_hw_context_switch_to:
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; get to thread
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MOVL XAR1, #_rt_interrupt_to_thread
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MOVL *XAR1, ACC
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; set from thread to 0
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MOVL XAR1, #_rt_interrupt_from_thread
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MOVL XAR0, #0
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MOVL *XAR1, XAR0
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; set interrupt flag to 1
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MOVL XAR1, #_rt_thread_switch_interrupt_flag
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MOVL XAR0, #1
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MOVL *XAR1, XAR0
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TRAP #16
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; never reach here!
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.endasmfunc
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.asmfunc
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_RTOSINT_Handler:
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; disable interrupt to protect context switch
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; DINT ;this is done by hardware so not needed
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; get rt_thread_switch_interrupt_flag
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MOVL XAR0, #_rt_thread_switch_interrupt_flag
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MOVL ACC, *XAR0
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BF rtosint_exit, EQ ; pendsv already handled
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; clear rt_thread_switch_interrupt_flag to 0
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MOVL XAR1, #0
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MOVL *XAR0, XAR1
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MOVL XAR0, #_rt_interrupt_from_thread
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MOVL ACC, *XAR0
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BF switch_to_thread, EQ ; skip register save at the first time
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RT_CTX_SAVE ; push cpu registers
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MOVL ACC, *XAR0
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MOVL XAR0, ACC
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MOVZ AR1, @SP ; get from thread stack pointer
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MOVL *XAR0, XAR1 ; update from thread stack pointer
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switch_to_thread:
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MOVL XAR1, #_rt_interrupt_to_thread
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MOVL ACC, *XAR1
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MOVL XAR1, ACC
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MOVL ACC, *XAR1
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MOV @SP, AL ; load thread stack pointer
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RT_CTX_RESTORE ; pop cpu registers
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rtosint_exit:
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; do not restore interrupt here: to be restored according to the
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; switched-to context during IRET (automaticlly by hardware)
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POP XAR2
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POP AR1H:AR0H
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MOVL ACC , *-SP[4]
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MOV AL, AR0
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MOVL *-SP[4], ACC
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IRET
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.endasmfunc
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.asmfunc
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_rt_hw_get_st0:
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rt_hw_get_st0:
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PUSH ST0
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POP AL
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LRETR
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.endasmfunc
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.asmfunc
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_rt_hw_get_st1:
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rt_hw_get_st1:
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PUSH ST1
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POP AL
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LRETR
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@@ -269,18 +341,18 @@ _rt_hw_get_st1:
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; 0x000001FF 22 8
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; 0x000001F0 22 8
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.asmfunc
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_rt_hw_calc_csb:
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rt_hw_calc_csb:
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MOV AH, #0
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CSB ACC ; T = no. of sign bits - 1
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MOVU ACC, T ; ACC = no. of sign bits - 1
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SUBB ACC, #30 ; ACC = ACC - 30
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ABS ACC ; ACC = |ACC|
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lretr
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LRETR
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.endasmfunc
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||||
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; compatible with old version
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.asmfunc
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_rt_hw_interrupt_thread_switch:
|
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rt_hw_interrupt_thread_switch:
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LRETR
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NOP
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.endasmfunc
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@@ -8,9 +8,12 @@
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* 2018-09-01 xuzhuoyi the first version.
|
||||
* 2019-07-03 zhaoxiaowei add support for __rt_ffs.
|
||||
* 2019-12-05 xiaolifan add support for hardware fpu32
|
||||
* 2022-10-17 guyunjie add support for hardware fpu64 and vcrc
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
extern volatile rt_uint8_t rt_interrupt_nest;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
rt_uint32_t rt_interrupt_from_thread;
|
||||
@@ -64,6 +67,24 @@ struct stack_frame
|
||||
rt_uint32_t r7h;
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX_FPU64__
|
||||
rt_uint32_t r0l;
|
||||
rt_uint32_t r1l;
|
||||
rt_uint32_t r2l;
|
||||
rt_uint32_t r3l;
|
||||
rt_uint32_t r4l;
|
||||
rt_uint32_t r5l;
|
||||
rt_uint32_t r6l;
|
||||
rt_uint32_t r7l;
|
||||
#endif
|
||||
|
||||
#ifdef __TMS320C28XX_VCRC__
|
||||
rt_uint32_t vcrc;
|
||||
rt_uint32_t vstatus;
|
||||
rt_uint32_t vcrcpoly;
|
||||
rt_uint32_t vcrcsize;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
@@ -81,20 +102,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
|
||||
stack_frame = (struct stack_frame *)stk;
|
||||
|
||||
/* init all register */
|
||||
/* zero all registers */
|
||||
for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
|
||||
{
|
||||
((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
|
||||
((rt_uint32_t *)stack_frame)[i] = 0;
|
||||
}
|
||||
|
||||
stack_frame->exception_stack_frame.t_st0 = 0x11110000 | rt_hw_get_st0();
|
||||
stack_frame->exception_stack_frame.acc = 0x33332222;
|
||||
stack_frame->exception_stack_frame.ar1_ar0 = 0x00001111 & (unsigned long)parameter; /* ar0 : argument */
|
||||
stack_frame->exception_stack_frame.p = 0x55554444; /* p */
|
||||
stack_frame->exception_stack_frame.dp_st1 = (0x00000000) | rt_hw_get_st1() & 0xFFFFFFFE; /* dp_st1 */
|
||||
stack_frame->exception_stack_frame.dbgstat_ier = 0; /* dbgstat_ier */
|
||||
stack_frame->exception_stack_frame.return_address = (unsigned long)tentry; /* return_address */
|
||||
stack_frame->rpc = (unsigned long)texit;
|
||||
/* configure special registers*/
|
||||
stack_frame->exception_stack_frame.dp_st1 = 0x00000A08;
|
||||
stack_frame->xar4 = (rt_uint32_t)parameter;
|
||||
stack_frame->exception_stack_frame.return_address = (rt_uint32_t)tentry;
|
||||
stack_frame->rpc = (rt_uint32_t)texit;
|
||||
|
||||
#ifdef __TMS320C28XX_FPU32__
|
||||
stack_frame->stf = 0x00000200;
|
||||
@@ -145,3 +163,32 @@ RT_WEAK void rt_hw_cpu_shutdown(void)
|
||||
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
|
||||
void rt_interrupt_enter(void)
|
||||
{
|
||||
rt_base_t level;
|
||||
|
||||
__asm(" EINT");
|
||||
level = rt_hw_interrupt_disable();
|
||||
rt_interrupt_nest ++;
|
||||
RT_OBJECT_HOOK_CALL(rt_interrupt_enter_hook,());
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
RT_DEBUG_LOG(RT_DEBUG_IRQ, ("irq has come..., irq current nest:%d\n",
|
||||
(rt_int32_t)rt_interrupt_nest));
|
||||
}
|
||||
|
||||
void rt_interrupt_leave(void)
|
||||
{
|
||||
RT_DEBUG_LOG(RT_DEBUG_IRQ, ("irq is going to leave, irq current nest:%d\n",
|
||||
(rt_int32_t)rt_interrupt_nest));
|
||||
|
||||
rt_hw_interrupt_disable();
|
||||
RT_OBJECT_HOOK_CALL(rt_interrupt_leave_hook,());
|
||||
rt_interrupt_nest --;
|
||||
if(rt_thread_switch_interrupt_flag && !rt_interrupt_nest)
|
||||
{
|
||||
__asm(" OR IFR, #0x8000"); /* trigger rtos int */
|
||||
}
|
||||
/* rt_hw_interrupt_enable auto done by hardware on IRET */
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user