[bsp][c28x] add support to not disable global interrupt in context-switch to enable zero-latency isr for critical interrupts.

This commit is contained in:
Yunjie Gu
2022-10-19 23:41:13 -04:00
committed by GitHub
parent 65baa8b697
commit 8fa9fde43a
13 changed files with 516 additions and 672 deletions
+8
View File
@@ -210,10 +210,18 @@ typedef __gnuc_va_list va_list;
* GCC and MDK) compilers. See ARM Optimizing C/C++ Compiler 5.9.3 for more
* details. */
#define RT_SECTION(x) __attribute__((section(x)))
#ifdef __TI_EABI__
#define RT_USED __attribute__((retain)) __attribute__((used))
#else
#define RT_USED __attribute__((used))
#endif
#define PRAGMA(x) _Pragma(#x)
#define ALIGN(n) __attribute__((aligned(n)))
#ifdef __TI_EABI__
#define RT_WEAK __attribute__((weak))
#else
#define RT_WEAK
#endif
#define rt_inline static inline
#define RTT_API
#elif defined (__TASKING__)