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Merge pull request #5090 from GuEe-GUI/master

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Merge AArch64 libcpu and add some drivers for their bsps
This commit is contained in:
Bernard Xiong
2021-09-26 17:18:43 +08:00
committed by GitHub
parent f44f4dfd74 740cd9dfb0
commit 8bf5c27406
71 changed files with 6137 additions and 1900 deletions
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libcpu/aarch64/common/SConscript
+5 -1
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@@ -6,9 +6,13 @@ Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
if not GetDepend('BSP_USING_GIC'):
SrcRemove(src, 'gic.c')
CPPPATH = [cwd]
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
# build for sub-directory
list = os.listdir(cwd)
libcpu/aarch64/common/cpuport.h
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@@ -0,0 +1,31 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-10 GuEe-GUI first version
*/
#ifndef __CPUPORT_H__
#define __CPUPORT_H__
#include <rtdef.h>
rt_inline void rt_hw_isb(void)
{
__asm__ volatile ("isb":::"memory");
}
rt_inline void rt_hw_dmb(void)
{
__asm__ volatile ("dmb sy":::"memory");
}
rt_inline void rt_hw_dsb(void)
{
__asm__ volatile ("dsb sy":::"memory");
}
#endif /* __CPUPORT_H__ */
libcpu/aarch64/common/gic.c
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libcpu/aarch64/common/gic.h
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@@ -0,0 +1,63 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-20 Bernard first version
*/
#ifndef __GIC_H__
#define __GIC_H__
#include <rthw.h>
#include <stdint.h>
#include <board.h>
int arm_gic_get_active_irq(rt_uint64_t index);
void arm_gic_ack(rt_uint64_t index, int irq);
void arm_gic_mask(rt_uint64_t index, int irq);
void arm_gic_umask(rt_uint64_t index, int irq);
rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq);
void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
void arm_gic_clear_pending_irq(rt_uint64_t index, int irq);
void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config);
rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
void arm_gic_clear_active(rt_uint64_t index, int irq);
void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask);
rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq);
void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority);
rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq);
void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority);
rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index);
void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point);
rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq);
void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_uint64_t filter_list);
rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index);
rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index);
void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group);
rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq);
int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start);
int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base);
void arm_gic_dump_type(rt_uint64_t index);
void arm_gic_dump(rt_uint64_t index);
#endif
libcpu/aarch64/common/gic/SConscript
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@@ -1,30 +0,0 @@
# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
gic390_group = Split('''
gic_pl390.c
''')
gic400_group = Split('''
gic_pl400.c
''')
gic500_group = Split('''
gic_pl500.c
''')
src = ()
if GetDepend('BSP_USING_GIC390'):
src = gic390_group
if GetDepend('BSP_USING_GIC400'):
src = gic400_group
if GetDepend('BSP_USING_GIC500'):
src = gic500_group
group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH)
Return('group')
libcpu/aarch64/common/gic/gic_pl390.c
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@@ -1,273 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-31 GuEe-GUI the first version
*/
#include <rtthread.h>
#include "gic_pl390.h"
#define BIT(n) (1ul<<(n))
#define MASK(n) (BIT(n)-1ul)
#define IRQ_REG(IRQ) ((IRQ) / 32)
#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
#define IRQ_MASK MASK(10)
#define IRQ_SET_ALL 0xffffffff
#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < GIC390_SPECIAL_IRQ_START)
#define TARGET_CPU_ALLINT(CPU) \
( \
(((CPU) & 0xff) << 0 ) | \
(((CPU) & 0xff) << 8 ) | \
(((CPU) & 0xff) << 16) | \
(((CPU) & 0xff) << 24) \
)
#define CPU(X) (1<<(X))
#define TARGET_CPU0_ALLINT TARGET_CPU_ALLINT(CPU(0))
/* memory map for GIC distributor */
struct gic_dist_map
{
rt_uint32_t enable; /* 0x000 */
rt_uint32_t ic_type; /* 0x004 */
rt_uint32_t dist_ident; /* 0x008 */
rt_uint32_t res1[29]; /* [0x00C, 0x080) */
rt_uint32_t security[32]; /* [0x080, 0x100) */
rt_uint32_t enable_set[32]; /* [0x100, 0x180) */
rt_uint32_t enable_clr[32]; /* [0x180, 0x200) */
rt_uint32_t pending_set[32]; /* [0x200, 0x280) */
rt_uint32_t pending_clr[32]; /* [0x280, 0x300) */
rt_uint32_t active[32]; /* [0x300, 0x380) */
rt_uint32_t res2[32]; /* [0x380, 0x400) */
rt_uint32_t priority[255]; /* [0x400, 0x7FC) */
rt_uint32_t res3; /* 0x7FC */
rt_uint32_t targets[255]; /* [0x800, 0xBFC) */
rt_uint32_t res4; /* 0xBFC */
rt_uint32_t config[64]; /* [0xC00, 0xD00) */
rt_uint32_t spi[32]; /* [0xD00, 0xD80) */
rt_uint32_t res5[20]; /* [0xD80, 0xDD0) */
rt_uint32_t res6; /* 0xDD0 */
rt_uint32_t legacy_int; /* 0xDD4 */
rt_uint32_t res7[2]; /* [0xDD8, 0xDE0) */
rt_uint32_t match_d; /* 0xDE0 */
rt_uint32_t enable_d; /* 0xDE4 */
rt_uint32_t res8[70]; /* [0xDE8, 0xF00) */
rt_uint32_t sgi_control; /* 0xF00 */
rt_uint32_t res9[3]; /* [0xF04, 0xF10) */
rt_uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
rt_uint32_t res10[40]; /* [0xF20, 0xFC0) */
rt_uint32_t periph_id[12]; /* [0xFC0, 0xFF0) */
rt_uint32_t component_id[4]; /* [0xFF0, 0xFFF] */
};
/* memory map for GIC CPU interface */
struct gic_cpu_iface_map
{
rt_uint32_t icontrol; /* 0x000 */
rt_uint32_t pri_msk_c; /* 0x004 */
rt_uint32_t pb_c; /* 0x008 */
rt_uint32_t int_ack; /* 0x00C */
rt_uint32_t eoi; /* 0x010 */
rt_uint32_t run_priority; /* 0x014 */
rt_uint32_t hi_pend; /* 0x018 */
rt_uint32_t ns_alias_bp_c; /* 0x01C */
rt_uint32_t ns_alias_ack; /* 0x020 GIC400 only */
rt_uint32_t ns_alias_eoi; /* 0x024 GIC400 only */
rt_uint32_t ns_alias_hi_pend; /* 0x028 GIC400 only */
rt_uint32_t res1[5]; /* [0x02C, 0x040) */
rt_uint32_t integ_en_c; /* 0x040 PL390 only */
rt_uint32_t interrupt_out; /* 0x044 PL390 only */
rt_uint32_t res2[2]; /* [0x048, 0x050) */
rt_uint32_t match_c; /* 0x050 PL390 only */
rt_uint32_t enable_c; /* 0x054 PL390 only */
rt_uint32_t res3[30]; /* [0x058, 0x0FC) */
rt_uint32_t active_priority[4]; /* [0x0D0, 0xDC] GIC400 only */
rt_uint32_t ns_active_priority[4]; /* [0xE0,0xEC] GIC400 only */
rt_uint32_t res4[3];
rt_uint32_t cpu_if_ident; /* 0x0FC */
rt_uint32_t res5[948]; /* [0x100. 0xFC0) */
rt_uint32_t periph_id[8]; /* [0xFC0, 9xFF0) PL390 only */
rt_uint32_t component_id[4]; /* [0xFF0, 0xFFF] PL390 only */
};
volatile struct gic_dist_map *gic_dist =
(volatile struct gic_dist_map*)(GIC_PL390_DISTRIBUTOR_PPTR);
volatile struct gic_cpu_iface_map *gic_cpuiface =
(volatile struct gic_cpu_iface_map*)(GIC_PL390_CONTROLLER_PPTR);
/*
* The only sane way to get an GIC IRQ number that can be properly
* ACKED later is through the int_ack register. Unfortunately, reading
* this register changes the interrupt state to pending so future
* reads will not return the same value For this reason, we have a
* global variable to store the IRQ number.
*/
static rt_uint32_t active_irq = GIC390_IRQ_NONE;
rt_inline int is_irq_edge_triggered(int irq)
{
int word = irq / 16;
int bit = ((irq & 0xf) * 2);
return !!(gic_dist->config[word] & BIT(bit + 1));
}
rt_inline void dist_pending_clr(int irq)
{
int word = irq / 32;
int bit = irq & 0x1f;
gic_dist->pending_clr[word] = BIT(bit);
}
rt_inline void dist_init(void)
{
int i;
int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
gic_dist->enable = 0;
for (i = 0; i < nirqs; i += 32)
{
/* disable */
gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
/* clear pending */
gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
}
/* reset interrupts priority */
for (i = 32; i < nirqs; i += 4)
{
gic_dist->priority[i / 4] = 0x0;
}
/*
* reset int target to cpu 0
* (Should really query which processor we're running on and use that)
*/
for (i = 0; i < nirqs; i += 4)
{
gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
}
/* level-triggered, 1-N */
for (i = 64; i < nirqs; i += 32)
{
gic_dist->config[i / 32] = 0;
}
/* enable the int controller */
gic_dist->enable = 1;
}
rt_inline void cpu_iface_init(void)
{
rt_uint32_t i;
/* For non-Exynos4, the registers are banked per CPU, need to clear them */
gic_dist->enable_clr[0] = IRQ_SET_ALL;
gic_dist->pending_clr[0] = IRQ_SET_ALL;
gic_dist->priority[0] = 0x00;
/* put everything in group 0 */
/* clear any software generated interrupts */
for (i = 0; i < 16; i += 4)
{
gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
}
gic_cpuiface->icontrol = 0;
gic_cpuiface->pri_msk_c = 0x000000f0;
gic_cpuiface->pb_c = 0x00000003;
while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != GIC390_IRQ_NONE)
{
gic_cpuiface->eoi = i;
}
gic_cpuiface->icontrol = 0x1;
}
void arm_gic_irq_init(void)
{
dist_init();
cpu_iface_init();
}
int arm_gic_get_active_irq(void)
{
int irq;
if (!IS_IRQ_VALID(active_irq))
{
active_irq = gic_cpuiface->int_ack;
}
if (IS_IRQ_VALID(active_irq))
{
irq = active_irq & IRQ_MASK;
}
else
{
irq = GIC390_IRQ_NONE;
}
return irq;
}
void arm_gic_mask(int irq)
{
int word = irq / 32;
int bit = irq & 0x1f;
gic_dist->enable_clr[word] = BIT(bit);
}
void arm_gic_umask(int irq)
{
int word = irq / 32;
int bit = irq & 0x1f;
gic_dist->enable_set[word] = BIT(bit);
}
void arm_gic_ack(int irq)
{
if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq))
{
return;
}
if (is_irq_edge_triggered(irq))
{
dist_pending_clr(irq);
}
gic_cpuiface->eoi = active_irq;
active_irq = GIC390_IRQ_NONE;
}
int rt_hw_interrupt_get_irq(void)
{
return arm_gic_get_active_irq();
}
void rt_hw_interrupt_ack(int fiq_irq)
{
return arm_gic_ack(fiq_irq);
}
libcpu/aarch64/common/gic/gic_pl390.h
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@@ -1,27 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-31 GuEe-GUI the first version
*/
#ifndef GIC_PL390_H__
#define GIC_PL390_H__
#include <board.h>
#define GIC390_SPECIAL_IRQ_START 1020
#define GIC390_IRQ_NONE 1023
void arm_gic_irq_init(void);
int arm_gic_get_active_irq(void);
void arm_gic_ack(int irq);
void arm_gic_mask(int irq);
void arm_gic_umask(int irq);
#endif
libcpu/aarch64/common/gic/gic_pl400.c
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@@ -1,261 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-20 Bernard first version
* 2014-04-03 Grissiom many enhancements
* 2018-11-22 Jesven add rt_hw_ipi_send()
* add rt_hw_ipi_handler_install()
*/
#include <rtthread.h>
#include "gic_pl400.h"
#include "cp15.h"
#define ARM_GIC_MAX_NR 1
struct arm_gic
{
rt_uint32_t offset; /* the first interrupt index in the vector table */
rt_uint32_t dist_hw_base; /* the base address of the gic distributor */
rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */
};
/* 'ARM_GIC_MAX_NR' is the number of cores */
static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
static unsigned int _gic_max_irq;
int arm_gic_get_active_irq(rt_uint32_t index)
{
int irq;
RT_ASSERT(index < ARM_GIC_MAX_NR);
irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
irq += _gic_table[index].offset;
return irq;
}
void arm_gic_ack(rt_uint32_t index, int irq)
{
rt_uint32_t mask = 1 << (irq % 32);
RT_ASSERT(index < ARM_GIC_MAX_NR);
irq = irq - _gic_table[index].offset;
RT_ASSERT(irq >= 0);
GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
}
void arm_gic_mask(rt_uint32_t index, int irq)
{
rt_uint32_t mask = 1 << (irq % 32);
RT_ASSERT(index < ARM_GIC_MAX_NR);
irq = irq - _gic_table[index].offset;
RT_ASSERT(irq >= 0);
GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
}
void arm_gic_clear_pending(rt_uint32_t index, int irq)
{
rt_uint32_t mask = 1 << (irq % 32);
RT_ASSERT(index < ARM_GIC_MAX_NR);
irq = irq - _gic_table[index].offset;
RT_ASSERT(irq >= 0);
GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
}
void arm_gic_clear_active(rt_uint32_t index, int irq)
{
rt_uint32_t mask = 1 << (irq % 32);
RT_ASSERT(index < ARM_GIC_MAX_NR);
irq = irq - _gic_table[index].offset;
RT_ASSERT(irq >= 0);
GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
}
/* Set up the cpu mask for the specific interrupt */
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
{
rt_uint32_t old_tgt;
RT_ASSERT(index < ARM_GIC_MAX_NR);
irq = irq - _gic_table[index].offset;
RT_ASSERT(irq >= 0);
old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
old_tgt |= cpumask << ((irq % 4)*8);
GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
}
void arm_gic_umask(rt_uint32_t index, int irq)
{
rt_uint32_t mask = 1 << (irq % 32);
RT_ASSERT(index < ARM_GIC_MAX_NR);
irq = irq - _gic_table[index].offset;
RT_ASSERT(irq >= 0);
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
}
void arm_gic_dump_type(rt_uint32_t index)
{
unsigned int gic_type;
gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
(GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
_gic_table[index].dist_hw_base,
_gic_max_irq,
gic_type & (1 << 10) ? "has" : "no",
gic_type);
}
void arm_gic_dump(rt_uint32_t index)
{
unsigned int i, k;
k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
rt_kprintf("--- hw mask ---\n");
for (i = 0; i < _gic_max_irq / 32; i++)
{
rt_kprintf("0x%08x, ",
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
i * 32));
}
rt_kprintf("\n--- hw pending ---\n");
for (i = 0; i < _gic_max_irq / 32; i++)
{
rt_kprintf("0x%08x, ",
GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
i * 32));
}
rt_kprintf("\n--- hw active ---\n");
for (i = 0; i < _gic_max_irq / 32; i++)
{
rt_kprintf("0x%08x, ",
GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
i * 32));
}
rt_kprintf("\n");
}
#ifdef RT_USING_FINSH
#include <finsh.h>
FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
#endif
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
{
unsigned int gic_type, i;
rt_uint32_t cpumask = 1 << 0;
RT_ASSERT(index < ARM_GIC_MAX_NR);
_gic_table[index].dist_hw_base = dist_base;
_gic_table[index].offset = irq_start;
/* Find out how many interrupts are supported. */
gic_type = GIC_DIST_TYPE(dist_base);
_gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
/*
* The GIC only supports up to 1020 interrupt sources.
* Limit this to either the architected maximum, or the
* platform maximum.
*/
if (_gic_max_irq > 1020)
_gic_max_irq = 1020;
if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
_gic_max_irq = ARM_GIC_NR_IRQS;
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
cpumask |= cpumask << 24;
GIC_DIST_CTRL(dist_base) = 0x0;
/* Set all global interrupts to be level triggered, active low. */
for (i = 32; i < _gic_max_irq; i += 16)
GIC_DIST_CONFIG(dist_base, i) = 0x0;
/* Set all global interrupts to this CPU only. */
for (i = 32; i < _gic_max_irq; i += 4)
GIC_DIST_TARGET(dist_base, i) = cpumask;
/* Set priority on all interrupts. */
for (i = 0; i < _gic_max_irq; i += 4)
GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
/* Disable all interrupts. */
for (i = 0; i < _gic_max_irq; i += 32)
GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
#if 0
/* All interrupts defaults to IGROUP1(IRQ). */
for (i = 0; i < _gic_max_irq; i += 32)
GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
#endif
for (i = 0; i < _gic_max_irq; i += 32)
GIC_DIST_IGROUP(dist_base, i) = 0;
/* Enable group0 and group1 interrupt forwarding. */
GIC_DIST_CTRL(dist_base) = 0x01;
return 0;
}
int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
{
RT_ASSERT(index < ARM_GIC_MAX_NR);
_gic_table[index].cpu_hw_base = cpu_base;
GIC_CPU_PRIMASK(cpu_base) = 0xf0;
GIC_CPU_BINPOINT(cpu_base) = 0x7;
/* Enable CPU interrupt */
GIC_CPU_CTRL(cpu_base) = 0x01;
return 0;
}
void arm_gic_set_group(rt_uint32_t index, int vector, int group)
{
/* As for GICv2, there are only group0 and group1. */
RT_ASSERT(group <= 1);
RT_ASSERT(vector < _gic_max_irq);
if (group == 0)
{
GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
vector) &= ~(1 << (vector % 32));
}
else if (group == 1)
{
GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
vector) |= (1 << (vector % 32));
}
}
libcpu/aarch64/common/gic/gic_pl400.h
-61
View File
@@ -1,61 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-20 Bernard first version
*/
#ifndef __GIC_PL400_H__
#define __GIC_PL400_H__
#include <rthw.h>
#include <board.h>
#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4)
#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4)
#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4)
#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
void arm_gic_mask(rt_uint32_t index, int irq);
void arm_gic_umask(rt_uint32_t index, int irq);
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
void arm_gic_set_group(rt_uint32_t index, int vector, int group);
int arm_gic_get_active_irq(rt_uint32_t index);
void arm_gic_ack(rt_uint32_t index, int irq);
void arm_gic_clear_active(rt_uint32_t index, int irq);
void arm_gic_clear_pending(rt_uint32_t index, int irq);
void arm_gic_dump_type(rt_uint32_t index);
void arm_gic_dump(rt_uint32_t index);
#endif
libcpu/aarch64/common/interrupt.c
+409
View File
@@ -0,0 +1,409 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-06 Bernard first version
* 2018-11-22 Jesven add smp support
*/
#include <rthw.h>
#include <rtthread.h>
#include "interrupt.h"
#include "gic.h"
#include "armv8.h"
#include "mmu.h"
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
#ifndef RT_USING_SMP
/* Those variables will be accessed in ISR, so we need to share them. */
rt_ubase_t rt_interrupt_from_thread = 0;
rt_ubase_t rt_interrupt_to_thread = 0;
rt_ubase_t rt_thread_switch_interrupt_flag = 0;
#endif
const unsigned int VECTOR_BASE = 0x00;
extern int system_vectors;
#ifdef RT_USING_SMP
#define rt_interrupt_nest rt_cpu_self()->irq_nest
#else
extern volatile rt_uint8_t rt_interrupt_nest;
#endif
#ifndef BSP_USING_GIC
static void default_isr_handler(int vector, void *param)
{
#ifdef RT_USING_SMP
rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
#else
rt_kprintf("unhandled irq: %d\n",vector);
#endif
}
#endif
void rt_hw_vector_init(void)
{
rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
#ifndef BSP_USING_GIC
rt_uint32_t index;
/* initialize vector table */
rt_hw_vector_init();
/* initialize exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));
/* mask all of interrupts */
IRQ_DISABLE_BASIC = 0x000000ff;
IRQ_DISABLE1 = 0xffffffff;
IRQ_DISABLE2 = 0xffffffff;
for (index = 0; index < MAX_HANDLERS; index ++)
{
isr_table[index].handler = default_isr_handler;
isr_table[index].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
isr_table[index].counter = 0;
#endif
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
#else
rt_uint64_t gic_cpu_base;
rt_uint64_t gic_dist_base;
rt_uint64_t gic_irq_start;
/* initialize vector table */
rt_hw_vector_init();
/* initialize exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));
/* initialize ARM GIC */
gic_dist_base = platform_get_gic_dist_base();
gic_cpu_base = platform_get_gic_cpu_base();
gic_irq_start = GIC_IRQ_START;
arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
arm_gic_cpu_init(0, gic_cpu_base);
#endif
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
#ifndef BSP_USING_GIC
if (vector < 32)
{
IRQ_DISABLE1 = (1 << vector);
}
else if (vector < 64)
{
vector = vector % 32;
IRQ_DISABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_DISABLE_BASIC = (1 << vector);
}
#else
arm_gic_mask(0, vector);
#endif
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
#ifndef BSP_USING_GIC
if (vector < 32)
{
IRQ_ENABLE1 = (1 << vector);
}
else if (vector < 64)
{
vector = vector % 32;
IRQ_ENABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_ENABLE_BASIC = (1 << vector);
}
#else
arm_gic_umask(0, vector);
#endif
}
/**
* This function returns the active interrupt number.
* @param none
*/
int rt_hw_interrupt_get_irq(void)
{
#ifdef BSP_USING_GIC
return arm_gic_get_active_irq(0);
#else
return 0;
#endif
}
/**
* This function acknowledges the interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_ack(int vector)
{
#ifdef BSP_USING_GIC
arm_gic_ack(0, vector);
#endif
}
/**
* This function set interrupt CPU targets.
* @param vector: the interrupt number
* cpu_mask: target cpus mask, one bit for one core
*/
void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask)
{
#ifdef BSP_USING_GIC
arm_gic_set_cpu(0, vector, cpu_mask);
#endif
}
/**
* This function get interrupt CPU targets.
* @param vector: the interrupt number
* @return target cpus mask, one bit for one core
*/
unsigned int rt_hw_interrupt_get_target_cpus(int vector)
{
#ifdef BSP_USING_GIC
return arm_gic_get_target_cpu(0, vector);
#else
return -RT_ERROR;
#endif
}
/**
* This function set interrupt triger mode.
* @param vector: the interrupt number
* mode: interrupt triger mode; 0: level triger, 1: edge triger
*/
void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode)
{
#ifdef BSP_USING_GIC
arm_gic_set_configuration(0, vector, mode);
#endif
}
/**
* This function get interrupt triger mode.
* @param vector: the interrupt number
* @return interrupt triger mode; 0: level triger, 1: edge triger
*/
unsigned int rt_hw_interrupt_get_triger_mode(int vector)
{
#ifdef BSP_USING_GIC
return arm_gic_get_configuration(0, vector);
#else
return -RT_ERROR;
#endif
}
/**
* This function set interrupt pending flag.
* @param vector: the interrupt number
*/
void rt_hw_interrupt_set_pending(int vector)
{
#ifdef BSP_USING_GIC
arm_gic_set_pending_irq(0, vector);
#endif
}
/**
* This function get interrupt pending flag.
* @param vector: the interrupt number
* @return interrupt pending flag, 0: not pending; 1: pending
*/
unsigned int rt_hw_interrupt_get_pending(int vector)
{
#ifdef BSP_USING_GIC
return arm_gic_get_pending_irq(0, vector);
#else
return -RT_ERROR;
#endif
}
/**
* This function clear interrupt pending flag.
* @param vector: the interrupt number
*/
void rt_hw_interrupt_clear_pending(int vector)
{
#ifdef BSP_USING_GIC
arm_gic_clear_pending_irq(0, vector);
#endif
}
/**
* This function set interrupt priority value.
* @param vector: the interrupt number
* priority: the priority of interrupt to set
*/
void rt_hw_interrupt_set_priority(int vector, unsigned int priority)
{
#ifdef BSP_USING_GIC
arm_gic_set_priority(0, vector, priority);
#endif
}
/**
* This function get interrupt priority.
* @param vector: the interrupt number
* @return interrupt priority value
*/
unsigned int rt_hw_interrupt_get_priority(int vector)
{
#ifdef BSP_USING_GIC
return arm_gic_get_priority(0, vector);
#else
return -RT_ERROR;
#endif
}
/**
* This function set priority masking threshold.
* @param priority: priority masking threshold
*/
void rt_hw_interrupt_set_priority_mask(unsigned int priority)
{
#ifdef BSP_USING_GIC
arm_gic_set_interface_prior_mask(0, priority);
#endif
}
/**
* This function get priority masking threshold.
* @param none
* @return priority masking threshold
*/
unsigned int rt_hw_interrupt_get_priority_mask(void)
{
#ifdef BSP_USING_GIC
return arm_gic_get_interface_prior_mask(0);
#else
return -RT_ERROR;
#endif
}
/**
* This function set priority grouping field split point.
* @param bits: priority grouping field split point
* @return 0: success; -1: failed
*/
int rt_hw_interrupt_set_prior_group_bits(unsigned int bits)
{
#ifdef BSP_USING_GIC
int status;
if (bits < 8)
{
arm_gic_set_binary_point(0, (7 - bits));
status = 0;
}
else
{
status = -1;
}
return (status);
#else
return -RT_ERROR;
#endif
}
/**
* This function get priority grouping field split point.
* @param none
* @return priority grouping field split point
*/
unsigned int rt_hw_interrupt_get_prior_group_bits(void)
{
#ifdef BSP_USING_GIC
unsigned int bp;
bp = arm_gic_get_binary_point(0) & 0x07;
return (7 - bp);
#else
return -RT_ERROR;
#endif
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
#ifdef RT_USING_SMP
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
{
#ifdef BSP_USING_GIC
arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
#endif
}
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
{
/* note: ipi_vector maybe different with irq_vector */
rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
}
#endif
libcpu/aarch64/common/interrupt.h
+60
View File
@@ -0,0 +1,60 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-06 Bernard first version
*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
#include <board.h>
#define INT_IRQ 0x00
#define INT_FIQ 0x01
#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */
#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */
void rt_hw_vector_init(void);
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
int rt_hw_interrupt_get_irq(void);
void rt_hw_interrupt_ack(int vector);
void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask);
unsigned int rt_hw_interrupt_get_target_cpus(int vector);
void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode);
unsigned int rt_hw_interrupt_get_triger_mode(int vector);
void rt_hw_interrupt_set_pending(int vector);
unsigned int rt_hw_interrupt_get_pending(int vector);
void rt_hw_interrupt_clear_pending(int vector);
void rt_hw_interrupt_set_priority(int vector, unsigned int priority);
unsigned int rt_hw_interrupt_get_priority(int vector);
void rt_hw_interrupt_set_priority_mask(unsigned int priority);
unsigned int rt_hw_interrupt_get_priority_mask(void);
int rt_hw_interrupt_set_prior_group_bits(unsigned int bits);
unsigned int rt_hw_interrupt_get_prior_group_bits(void);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
#ifdef RT_USING_SMP
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask);
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
#endif
#endif
libcpu/aarch64/cortex-a72/stack.c → libcpu/aarch64/common/stack.c
+1 -2
View File
@@ -27,8 +27,7 @@
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_ubase_t *stk;
rt_ubase_t current_el;
libcpu/aarch64/common/trap.c
+172
View File
@@ -0,0 +1,172 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-20 Bernard first version
*/
#include <rtthread.h>
#include <rthw.h>
#include <board.h>
#include <armv8.h>
#include <interrupt.h>
#ifdef RT_USING_FINSH
extern long list_thread(void);
#endif
/**
* this function will show registers of CPU
*
* @param regs the registers point
*/
void rt_hw_show_register(struct rt_hw_exp_stack *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("X00:0x%16.16p X01:0x%16.16p X02:0x%16.16p X03:0x%16.16p\n", (void *)regs->x0, (void *)regs->x1, (void *)regs->x2, (void *)regs->x3);
rt_kprintf("X04:0x%16.16p X05:0x%16.16p X06:0x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (void *)regs->x7);
rt_kprintf("X08:0x%16.16p X09:0x%16.16p X10:0x%16.16p X11:0x%16.16p\n", (void *)regs->x8, (void *)regs->x9, (void *)regs->x10, (void *)regs->x11);
rt_kprintf("X12:0x%16.16p X13:0x%16.16p X14:0x%16.16p X15:0x%16.16p\n", (void *)regs->x12, (void *)regs->x13, (void *)regs->x14, (void *)regs->x15);
rt_kprintf("X16:0x%16.16p X17:0x%16.16p X18:0x%16.16p X19:0x%16.16p\n", (void *)regs->x16, (void *)regs->x17, (void *)regs->x18, (void *)regs->x19);
rt_kprintf("X20:0x%16.16p X21:0x%16.16p X22:0x%16.16p X23:0x%16.16p\n", (void *)regs->x20, (void *)regs->x21, (void *)regs->x22, (void *)regs->x23);
rt_kprintf("X24:0x%16.16p X25:0x%16.16p X26:0x%16.16p X27:0x%16.16p\n", (void *)regs->x24, (void *)regs->x25, (void *)regs->x26, (void *)regs->x27);
rt_kprintf("X28:0x%16.16p X29:0x%16.16p X30:0x%16.16p\n", (void *)regs->x28, (void *)regs->x29, (void *)regs->x30);
rt_kprintf("SPSR :0x%16.16p\n", (void *)regs->spsr);
rt_kprintf("EPC :0x%16.16p\n", (void *)regs->pc);
}
/**
* When comes across an instruction which it cannot handle,
* it takes the undefined instruction trap.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
{
rt_kprintf("error exception:\n");
rt_hw_show_register(regs);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
void rt_hw_trap_irq(void)
{
#ifndef BSP_USING_GIC
void *param;
uint32_t irq;
rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[];
uint32_t value = 0;
value = IRQ_PEND_BASIC & 0x3ff;
#ifdef BSP_USING_CORETIMER
uint32_t cpu_id = 0;
#ifdef RT_USING_SMP
cpu_id = rt_hw_cpu_id();
#endif
uint32_t int_source = CORE_IRQSOURCE(cpu_id) & 0x3ff;
if (int_source & 0x02)
{
isr_func = isr_table[IRQ_ARM_TIMER].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[IRQ_ARM_TIMER].counter++;
#endif
if (isr_func)
{
param = isr_table[IRQ_ARM_TIMER].param;
isr_func(IRQ_ARM_TIMER, param);
}
}
#endif
/* local interrupt*/
if (value)
{
if (value & (1 << 8))
{
value = IRQ_PEND1;
irq = __rt_ffs(value) - 1;
}
else if (value & (1 << 9))
{
value = IRQ_PEND2;
irq = __rt_ffs(value) + 31;
}
else
{
value &= 0x0f;
irq = __rt_ffs(value) + 63;
}
/* get interrupt service routine */
isr_func = isr_table[irq].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[irq].counter++;
#endif
if (isr_func)
{
/* Interrupt for myself. */
param = isr_table[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
}
}
#else
void *param;
int ir;
rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[];
ir = rt_hw_interrupt_get_irq();
if (ir == 1023)
{
/* Spurious interrupt */
return;
}
/* get interrupt service routine */
isr_func = isr_table[ir].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[ir].counter++;
#endif
if (isr_func)
{
/* Interrupt for myself. */
param = isr_table[ir].param;
/* turn to interrupt service routine */
isr_func(ir, param);
}
/* end of interrupt */
rt_hw_interrupt_ack(ir);
#endif
}
void rt_hw_trap_fiq(void)
{
void *param;
int ir;
rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[];
ir = rt_hw_interrupt_get_irq();
/* get interrupt service routine */
isr_func = isr_table[ir].handler;
param = isr_table[ir].param;
/* turn to interrupt service routine */
isr_func(ir, param);
/* end of interrupt */
rt_hw_interrupt_ack(ir);
}
libcpu/aarch64/cortex-a53/SConscript → libcpu/aarch64/cortex-a/SConscript
+1 -1
View File
@@ -8,6 +8,6 @@ cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
CPPPATH = [cwd]
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
libcpu/aarch64/cortex-a/entry_point.S
+97
View File
@@ -0,0 +1,97 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2020-01-15 bigmagic the first version
* 2020-08-10 SummerGift support clang compiler
*/
.section ".text.entrypoint","ax"
.globl _start
_start:
/* Read cpu id */
mrs x1, mpidr_el1
and x1, x1, #3
cbz x1, cpu_setup /* If cpu id > 0, stop slave cores */
cpu_idle:
wfe
b cpu_idle
cpu_setup:
ldr x1, =_start
mrs x0, CurrentEL /* CurrentEL Register. bit 2, 3. Others reserved */
and x0, x0, #12 /* Clear reserved bits */
/* Running at EL3? */
cmp x0, #12 /* EL3 value is 0b1100 */
bne cpu_not_in_el3
/* Should never be executed, just for completeness. (EL3) */
mov x0, #(1 << 0) /* EL0 and EL1 are in Non-Secure state */
orr x0, x0, #(1 << 4) /* RES1 */
orr x0, x0, #(1 << 5) /* RES1 */
orr x0, x0, #(1 << 7) /* SMC instructions are undefined at EL1 and above */
orr x0, x0, #(1 << 8) /* HVC instructions are enabled at EL1 and above */
orr x0, x0, #(1 << 10) /* The next lower level is AArch64 */
msr scr_el3, x2
mov x2, #0x3c9
msr spsr_el3, x2 /* 0b1111001001 */
adr x2, cpu_not_in_el3
msr elr_el3, x2
eret /* Exception Return: from EL3, continue from cpu_not_in_el3 */
cpu_not_in_el3: /* Running at EL2 or EL1 */
cmp x0, #4 /* EL1 = 0100 */
beq cpu_in_el1 /* Halt this core if running in El1 */
cpu_in_el2:
msr sp_el1, x1
/* Enable CNTP for EL1 */
mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */
orr x0, x0, #3
msr cnthctl_el2, x0
msr cntvoff_el2, xzr
mov x0, #(1 << 31) /* Enable AArch64 in EL1 */
orr x0, x0, #(1 << 1) /* SWIO hardwired on Pi3 */
msr hcr_el2, x0
/* Change execution level to EL1 */
mov x2, #0x3c4
msr spsr_el2, x2 /* 0b1111000100 */
adr x2, cpu_in_el1
msr elr_el2, x2
eret
cpu_in_el1:
mov sp, x1 /* Set sp in el1 */
/* Avoid trap from SIMD or float point instruction */
mov x1, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
msr cpacr_el1, x1
mrs x1, sctlr_el1
orr x1, x1, #(1 << 12) /* Enable Instruction */
bic x1, x1, #(3 << 3) /* Disable SP Alignment check */
bic x1, x1, #(1 << 1) /* Disable Alignment check */
msr sctlr_el1, x1
ldr x1, =__bss_start
ldr w2, =__bss_size
clean_bss_loop:
cbz w2, jump_to_entry
str xzr, [x1], #8
sub w2, w2, #1
cbnz w2, clean_bss_loop
jump_to_entry:
b rtthread_startup
b cpu_idle /* For failsafe, halt this core too */
libcpu/aarch64/cortex-a53/entry_point.S
-116
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@@ -1,116 +0,0 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2020-01-15 bigmagic the first version
*/
.section ".text.entrypoint"
.set EL1_stack, __el1_stack
.global _start
// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
// loads 'kernel8.img' file in.
_start:
// read cpu id, stop slave cores
mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register
and x1, x1, #3
cbz x1, .L__cpu_0 // .L prefix is the local label in ELF
// cpu id > 0, stop
// cpu id == 0 will also goto here after returned from entry() if possible
.L__current_cpu_idle:
wfe
b .L__current_cpu_idle
.L__cpu_0: // cpu id == 0
// set stack before our code
/* Define stack pointer for current exception level */
// ldr x2, =EL1_stack
// mov sp, x2
ldr x1, =init_el1_stack_limit
// set up EL1
mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved
and x0, x0, #12 // clear reserved bits
// running at EL3?
cmp x0, #12 // 1100b. So, EL3
bne .L__not_in_el3 // 11? !EL3 -> 5:
// should never be executed, just for completeness. (EL3)
mov x2, #0x5b1
msr scr_el3, x2 // SCR_ELn Secure Configuration Register
mov x2, #0x3c9
msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001
adr x2, .L__not_in_el3
msr elr_el3, x2
eret // Exception Return: from EL3, continue from .L__not_in_el3
// running at EL2 or EL1
.L__not_in_el3:
cmp x0, #4 // 0x04 0100 EL1
beq .L__in_el1 // EL1 -> 5:
// in EL2
msr sp_el1, x1 // Set sp of EL1 to _start
// enable CNTP for EL1
mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register
orr x0, x0, #3
msr cnthctl_el2, x0
msr cntvoff_el2, xzr
// enable AArch64 in EL1
mov x0, #(1 << 31) // AArch64
orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3
msr hcr_el2, x0
mrs x0, hcr_el2
// change execution level to EL1
mov x2, #0x3c4
msr spsr_el2, x2 // 1111000100
adr x2, .L__in_el1
msr elr_el2, x2
eret // exception return. from EL2. continue from .L__in_el1
.L__in_el1:
mov sp, x1 // in EL1. Set sp to _start
// Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1
msr cpacr_el1, x1
mrs x1, sctlr_el1
orr x1, x1, #(1 << 12)
bic x1, x1, #(3 << 3)
bic x1, x1, #(1 << 1)
msr sctlr_el1, x1
// clear bss
ldr x1, =__bss_start
ldr w2, =__bss_size
.L__clean_bss_loop:
cbz w2, .L__jump_to_entry
str xzr, [x1], #8
sub w2, w2, #1
cbnz w2, .L__clean_bss_loop
// jump to C code, should not return
.L__jump_to_entry:
bl entry
// for failsafe, halt this core too
b .L__current_cpu_idle
.bss
.align 3
init_el1_stack:
.space 4096
init_el1_stack_limit:
libcpu/aarch64/cortex-a53/interrupt.c
-202
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@@ -1,202 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/5/3 Bernard first version
* 2019-07-28 zdzn add smp support
* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
* write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
* 2021-07-31 GuEe-GUI Add gic pl390 branch
*/
#include <rthw.h>
#include <board.h>
#include <rtthread.h>
#include "cp15.h"
#include "armv8.h"
#include "interrupt.h"
#ifdef BSP_USING_GIC390
#include <gic_pl390.h>
#endif
#define MAX_HANDLERS 72
#ifdef RT_USING_SMP
#define rt_interrupt_nest rt_cpu_self()->irq_nest
#else
extern volatile rt_uint8_t rt_interrupt_nest;
#endif
extern int system_vectors;
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_ubase_t rt_interrupt_from_thread;
rt_ubase_t rt_interrupt_to_thread;
rt_ubase_t rt_thread_switch_interrupt_flag;
void rt_hw_vector_init(void)
{
rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S
}
#ifndef BSP_USING_GIC
static void default_isr_handler(int vector, void *param)
{
#ifdef RT_USING_SMP
rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
#else
rt_kprintf("unhandled irq: %d\n",vector);
#endif
}
#endif
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
#ifdef BSP_USING_GIC390
arm_gic_irq_init();
#else
rt_uint32_t index;
/* mask all of interrupts */
IRQ_DISABLE_BASIC = 0x000000ff;
IRQ_DISABLE1 = 0xffffffff;
IRQ_DISABLE2 = 0xffffffff;
for (index = 0; index < MAX_HANDLERS; index ++)
{
isr_table[index].handler = default_isr_handler;
isr_table[index].param = NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
isr_table[index].counter = 0;
#endif
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
#endif
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
#ifdef BSP_USING_GIC390
arm_gic_mask(vector);
#else
if (vector < 32)
{
IRQ_DISABLE1 = (1 << vector);
}
else if (vector<64)
{
vector = vector % 32;
IRQ_DISABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_DISABLE_BASIC = (1 << vector);
}
#endif
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
#ifdef BSP_USING_GIC390
arm_gic_umask(vector);
#else
if (vector < 32)
{
IRQ_ENABLE1 = (1 << vector);
}
else if (vector < 64)
{
vector = vector % 32;
IRQ_ENABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_ENABLE_BASIC = (1 << vector);
}
#endif
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
#ifdef RT_USING_SMP
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
{
__DSB();
if(cpu_mask & 0x1)
{
send_ipi_msg(0, ipi_vector);
}
if(cpu_mask & 0x2)
{
send_ipi_msg(1, ipi_vector);
}
if(cpu_mask & 0x4)
{
send_ipi_msg(2, ipi_vector);
}
if(cpu_mask & 0x8)
{
send_ipi_msg(3, ipi_vector);
}
__DSB();
}
#endif
#ifdef RT_USING_SMP
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
{
/* note: ipi_vector maybe different with irq_vector */
rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
}
#endif
libcpu/aarch64/cortex-a53/interrupt.h
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@@ -1,27 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-16 bigmagic first version
*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
#include <board.h>
#define INT_IRQ 0x00
#define INT_FIQ 0x01
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
#endif
libcpu/aarch64/cortex-a53/stack.c
-90
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@@ -1,90 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-23 Bernard the first version
* 2011-10-05 Bernard add thumb mode
*/
#include <rtthread.h>
#include <board.h>
#include <armv8.h>
#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
rt_ubase_t *stk;
rt_ubase_t current_el;
stk = (rt_ubase_t*)stack_addr;
*(--stk) = ( rt_ubase_t ) 11; /* X1 */
*(--stk) = ( rt_ubase_t ) parameter; /* X0 */
*(--stk) = ( rt_ubase_t ) 33; /* X3 */
*(--stk) = ( rt_ubase_t ) 22; /* X2 */
*(--stk) = ( rt_ubase_t ) 55; /* X5 */
*(--stk) = ( rt_ubase_t ) 44; /* X4 */
*(--stk) = ( rt_ubase_t ) 77; /* X7 */
*(--stk) = ( rt_ubase_t ) 66; /* X6 */
*(--stk) = ( rt_ubase_t ) 99; /* X9 */
*(--stk) = ( rt_ubase_t ) 88; /* X8 */
*(--stk) = ( rt_ubase_t ) 11; /* X11 */
*(--stk) = ( rt_ubase_t ) 10; /* X10 */
*(--stk) = ( rt_ubase_t ) 13; /* X13 */
*(--stk) = ( rt_ubase_t ) 12; /* X12 */
*(--stk) = ( rt_ubase_t ) 15; /* X15 */
*(--stk) = ( rt_ubase_t ) 14; /* X14 */
*(--stk) = ( rt_ubase_t ) 17; /* X17 */
*(--stk) = ( rt_ubase_t ) 16; /* X16 */
*(--stk) = ( rt_ubase_t ) 19; /* X19 */
*(--stk) = ( rt_ubase_t ) 18; /* X18 */
*(--stk) = ( rt_ubase_t ) 21; /* X21 */
*(--stk) = ( rt_ubase_t ) 20; /* X20 */
*(--stk) = ( rt_ubase_t ) 23; /* X23 */
*(--stk) = ( rt_ubase_t ) 22; /* X22 */
*(--stk) = ( rt_ubase_t ) 25; /* X25 */
*(--stk) = ( rt_ubase_t ) 24; /* X24 */
*(--stk) = ( rt_ubase_t ) 27; /* X27 */
*(--stk) = ( rt_ubase_t ) 26; /* X26 */
*(--stk) = ( rt_ubase_t ) 29; /* X29 */
*(--stk) = ( rt_ubase_t ) 28; /* X28 */
*(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */
*(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */
current_el = rt_hw_get_current_el();
if(current_el == 3)
{
*(--stk) = INITIAL_SPSR_EL3;
}
else if(current_el == 2)
{
*(--stk) = INITIAL_SPSR_EL2;
}
else
{
*(--stk) = INITIAL_SPSR_EL1;
}
*(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
libcpu/aarch64/cortex-a53/trap.c
-225
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@@ -1,225 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version
* 2021-07-31 GuEe-GUI Add gic_pl390 branch
*/
#include <rtthread.h>
#include <rthw.h>
#include "interrupt.h"
#include "armv8.h"
#ifdef BSP_USING_GIC390
#include <gic_pl390.h>
#endif
extern struct rt_thread *rt_current_thread;
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
extern long list_thread(void);
#endif
/**
* this function will show registers of CPU
*
* @param regs the registers point
*/
void rt_hw_show_register(struct rt_hw_exp_stack *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
}
/**
* When comes across an instruction which it cannot handle,
* it takes the undefined instruction trap.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
{
rt_kprintf("error exception:\n");
rt_hw_show_register(regs);
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
list_thread();
#endif
rt_hw_cpu_shutdown();
}
#define GIC_ACK_INTID_MASK (0x000003ff)
#define CORE0_IRQ_SOURCE (0x40000060)
void rt_hw_trap_irq(void)
{
void *param;
uint32_t irq;
rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[];
#ifndef BSP_USING_GIC390
uint32_t value = 0;
value = IRQ_PEND_BASIC & 0x3ff;
#ifdef BSP_USING_CORETIMER
uint32_t int_source = HWREG32(CORE0_IRQ_SOURCE) & 0x3ff;
if (int_source & 0x02)
{
isr_func = isr_table[IRQ_ARM_TIMER].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[IRQ_ARM_TIMER].counter++;
#endif
if (isr_func)
{
param = isr_table[IRQ_ARM_TIMER].param;
isr_func(IRQ_ARM_TIMER, param);
}
}
#endif
/* local interrupt*/
if (value)
{
if (value & (1 << 8))
{
value = IRQ_PEND1;
irq = __rt_ffs(value) - 1;
}
else if (value & (1 << 9))
{
value = IRQ_PEND2;
irq = __rt_ffs(value) + 31;
}
else
{
value &= 0x0f;
irq = __rt_ffs(value) + 63;
}
#else
irq = arm_gic_get_active_irq();
if (irq == GIC390_IRQ_NONE)
{
/* Spurious interrupt */
return;
}
#endif
/* get interrupt service routine */
isr_func = isr_table[irq].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[irq].counter++;
#endif
if (isr_func)
{
/* Interrupt for myself. */
param = isr_table[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
}
#ifndef BSP_USING_GIC390
}
#else
/* end of interrupt */
arm_gic_ack(irq);
#endif
}
void rt_hw_trap_fiq(void)
{
#ifndef BSP_USING_GIC390
void *param;
uint32_t irq;
rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[];
uint32_t value = 0;
value = IRQ_PEND_BASIC & 0x3ff;
#ifdef RT_USING_SMP
uint32_t mailbox_data;
uint32_t cpu_id = rt_hw_cpu_id();
uint32_t int_source = CORE_IRQSOURCE(cpu_id);
mailbox_data = IPI_MAILBOX_CLEAR(cpu_id);
if (int_source & 0x0f)
{
if (int_source & 0x08)
{
isr_func = isr_table[IRQ_ARM_TIMER].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[IRQ_ARM_TIMER].counter++;
#endif
if (isr_func)
{
param = isr_table[IRQ_ARM_TIMER].param;
isr_func(IRQ_ARM_TIMER, param);
}
}
}
if (int_source & 0xf0)
{
/*it's a ipi interrupt*/
if (mailbox_data & 0x1)
{
/* clear mailbox */
IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;
isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[IRQ_ARM_MAILBOX].counter++;
#endif
if (isr_func)
{
param = isr_table[IRQ_ARM_MAILBOX].param;
isr_func(IRQ_ARM_MAILBOX, param);
}
}
else
CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
}
#endif
/* local interrupt*/
if (value)
{
if (value & (1 << 8))
{
value = IRQ_PEND1;
irq = __rt_ffs(value) - 1;
}
else if (value & (1 << 9))
{
value = IRQ_PEND2;
irq = __rt_ffs(value) + 31;
}
else
{
value &= 0x0f;
irq = __rt_ffs(value) + 63;
}
/* get interrupt service routine */
isr_func = isr_table[irq].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[irq].counter++;
#endif
if (irq > 1)
rt_kprintf("interrupt fiq %d\n", irq);
if (isr_func)
{
/* Interrupt for myself. */
param = isr_table[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
}
}
#endif
}
libcpu/aarch64/cortex-a72/SConscript
-13
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@@ -1,13 +0,0 @@
# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
CPPPATH = [cwd]
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
libcpu/aarch64/cortex-a72/entry_point.S
-111
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@@ -1,111 +0,0 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2020-01-15 bigmagic the first version
*/
.section ".text.entrypoint"
.set EL1_stack, __el1_stack
.global _start
// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
// loads 'kernel8.img' file in.
_start:
// read cpu id, stop slave cores
mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register
and x1, x1, #3
cbz x1, .L__cpu_0 // .L prefix is the local label in ELF
// cpu id > 0, stop
// cpu id == 0 will also goto here after returned from entry() if possible
.L__current_cpu_idle:
wfe
b .L__current_cpu_idle
.L__cpu_0: // cpu id == 0
// set stack before our code
/* Define stack pointer for current exception level */
// ldr x2, =EL1_stack
// mov sp, x2
ldr x1, =_start
// set up EL1
mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved
and x0, x0, #12 // clear reserved bits
// running at EL3?
cmp x0, #12 // 1100b. So, EL3
bne .L__not_in_el3 // 11? !EL3 -> 5:
// should never be executed, just for completeness. (EL3)
mov x2, #0x5b1
msr scr_el3, x2 // SCR_ELn Secure Configuration Register
mov x2, #0x3c9
msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001
adr x2, .L__not_in_el3
msr elr_el3, x2
eret // Exception Return: from EL3, continue from .L__not_in_el3
// running at EL2 or EL1
.L__not_in_el3:
cmp x0, #4 // 0x04 0100 EL1
beq .L__in_el1 // EL1 -> 5:
// in EL2
msr sp_el1, x1 // Set sp of EL1 to _start
// enable CNTP for EL1
mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register
orr x0, x0, #3
msr cnthctl_el2, x0
msr cntvoff_el2, xzr
// enable AArch64 in EL1
mov x0, #(1 << 31) // AArch64
orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3
msr hcr_el2, x0
mrs x0, hcr_el2
// change execution level to EL1
mov x2, #0x3c4
msr spsr_el2, x2 // 1111000100
adr x2, .L__in_el1
msr elr_el2, x2
eret // exception return. from EL2. continue from .L__in_el1
.L__in_el1:
mov sp, x1 // in EL1. Set sp to _start
// Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1
msr cpacr_el1, x1
mrs x1, sctlr_el1
orr x1, x1, #(1 << 12)
bic x1, x1, #(3 << 3)
bic x1, x1, #(1 << 1)
msr sctlr_el1, x1
// clear bss
ldr x1, =__bss_start
ldr w2, =__bss_size
.L__clean_bss_loop:
cbz w2, .L__jump_to_entry
str xzr, [x1], #8
sub w2, w2, #1
cbnz w2, .L__clean_bss_loop
// jump to C code, should not return
.L__jump_to_entry:
bl entry
// for failsafe, halt this core too
b .L__current_cpu_idle
libcpu/aarch64/cortex-a72/interrupt.c
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@@ -1,118 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-16 bigmagic first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <gic_pl400.h>
#include <board.h>
#include <armv8.h>
#define MAX_HANDLERS 256
#define GIC_ACK_INTID_MASK 0x000003ff
#ifdef RT_USING_SMP
#define rt_interrupt_nest rt_cpu_self()->irq_nest
#else
extern volatile rt_uint8_t rt_interrupt_nest;
#endif
extern int system_vectors;
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_ubase_t rt_interrupt_from_thread;
rt_ubase_t rt_interrupt_to_thread;
rt_ubase_t rt_thread_switch_interrupt_flag;
void rt_hw_vector_init(void)
{
rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_uint32_t gic_cpu_base = 0;
rt_uint32_t gic_dist_base = 0;
/* initialize ARM GIC */
gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR;
gic_cpu_base = GIC_PL400_CONTROLLER_PPTR;
arm_gic_dist_init(0, gic_dist_base, 0);
arm_gic_cpu_init(0, gic_cpu_base);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
arm_gic_mask(0, vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
arm_gic_umask(0, vector);
}
/**
* This function returns the active interrupt number.
* @param none
*/
int rt_hw_interrupt_get_irq(void)
{
return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
}
/**
* This function acknowledges the interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_ack(int vector)
{
arm_gic_ack(0, vector);
}
libcpu/aarch64/cortex-a72/interrupt.h
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@@ -1,27 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-16 bigmagic first version
*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
#include <board.h>
#define INT_IRQ 0x00
#define INT_FIQ 0x01
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
#endif
libcpu/aarch64/cortex-a72/trap.c
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@@ -1,98 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "interrupt.h"
#include "armv8.h"
extern struct rt_thread *rt_current_thread;
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
extern long list_thread(void);
#endif
/**
* this function will show registers of CPU
*
* @param regs the registers point
*/
void rt_hw_show_register(struct rt_hw_exp_stack *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
}
/**
* When comes across an instruction which it cannot handle,
* it takes the undefined instruction trap.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
{
rt_kprintf("error exception:\n");
rt_hw_show_register(regs);
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
list_thread();
#endif
rt_hw_cpu_shutdown();
}
#define GIC_ACK_INTID_MASK 0x000003ff
int rt_hw_interrupt_get_irq(void);
void rt_hw_interrupt_ack(int fiq_irq);
void rt_hw_trap_irq(void)
{
void *param;
int ir;
rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[];
ir = rt_hw_interrupt_get_irq();
if (ir == 1023)
{
/* Spurious interrupt */
return;
}
/* get interrupt service routine */
isr_func = isr_table[ir].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[ir].counter++;
#endif
if (isr_func)
{
/* Interrupt for myself. */
param = isr_table[ir].param;
/* turn to interrupt service routine */
isr_func(ir, param);
}
/* end of interrupt */
rt_hw_interrupt_ack(ir);
}
void rt_hw_trap_fiq(void)
{
}