Add Microchip SAM series MCU support for RT-Thread (#5771)

* Add Microchip SAM series MCU support for RT-Thread

Add Microchip SAM series MCU support for RT-Thread, including SAM Cortex-M0+, M4F and M7.

* Add bsp directory to ignored check list

Add bsp directory to ignored check list, add microchip /samc21/same54/same70 to workflows list

* remove STDIO definition and bug fix

1. remove STDIO code from Microchip official BSP. 2. bug fix of SAME70 hpl/hpl_usart.c, samc21&same54 hpl/hpl_sercom.c baudrate update interface.  3. Add RT-Thread standard STDIO implementation on Microchip SAM MCU.

* add CAN driver & example and script fix

Add CAN driver and example for SAMC21/SAME5x/SAME70 and fix rtconfig.py issue(unused space might result link error)

* Add Chinese version README

Add Chinese version README for SAMC21/E54/E70

bsp/microchip/same70/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- bsp

bsp/microchip/same70/Kconfig

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+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+# you can change the RTT_ROOT default: "rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
+config SOC_SAME70
+    bool 
+    select ARCH_ARM
+    select ARCH_ARM_CORTEX_M
+    select ARCH_ARM_CORTEX_M7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y

bsp/microchip/same70/README.md

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+# SAME70Q21B BSP Introduction
+
+[中文](README_zh.md) 
+- MCU: ATSAME70Q21B @300MHz, 2MB FLASH, 384KB RAM
+- V71: Auto grade Cortex-M7 + Advanced Feature Set + Ethernet + 2x CAN-FD
+- E70: Industrial Cortex-M7 + Advanced Feature Set + Ethernet + 2x CAN-FD
+- S70: Industrial Cortex-M7 + Advanced Feature Set
+- Pin: J=64 pins, N=100 pins, Q=144 pins
+- Flash: 19=512KB, 20=1024KB, 21=2048KB (size=2^n)
+- Datasheet: <https://www.microchip.com/en-us/product/ATSAME70Q21>
+
+#### KEY FEATURES
+
+#### Core
+  - 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 300 MHz, MPU, 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
+
+####  Memories
+  - Up to 2 Mbytes of embedded Flash with unique identifier and user signature for user-defined data
+  - Up to 384 Kbyte embedded Multi-port SRAM, can be configured as ITCM, DTCM.
+  - 16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines
+  
+####  Peripherals
+  - 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling
+  - 16-bit SDRAM Controller (SDRAMC) interfacing up to 128 MB and with on-the-fly scrambling
+  - One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE® 1588 PTP frames and 802.3az Energy-efficiency support.
+  - USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints, dedicated DMA
+  - 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
+  - Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time-triggered and event-triggered transmission
+  - MediaLB® device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks
+  - Three USARTs, USART0, USART1, USART2, support LIN mode, ISO7816, IrDA®, RS-485, SPI, Manchester and Modem modes; USART1 supports LON mode.
+  - Five 2-wire UARTs with SleepWalking™ support
+  - Three Two-Wire Interfaces (TWIHS) (I2C-compatible) with SleepWalking support
+  - Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and onthe-fly scrambling
+  - Two Serial Peripheral Interfaces (SPI)
+  - One Serial Synchronous Controller (SSC) with I2S and TDM support
+  - Two Inter-IC Sound Controllers (I2SC)
+  - One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
+  - Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
+  - Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control
+  - Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7 Msps. Offset and gain error correction feature.
+  - One 2-channel, 12-bit, 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over Sampling modes
+  - One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis
+
+#### Cryptography
+  - True Random Number Generator (TRNG)
+  - AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications
+  - Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.
+
+#### I/O
+  - Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination
+  - Five Parallel Input/Output Controllers (PIO)
+
+#### Voltage
+  - Single supply voltage from 3.0V to 3.6V for Qualification AEC - Q100 Grade 2 Devices
+  - Single Supply voltage from 1.7V to 3.6V for Industrial Temperature Devices
+
+#### Packages
+  - LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm
+  - LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.8 mm
+  - TFBGA144, 144-ball TFBGA, 10x10 mm, pitch 0.8 mm
+  - UFBGA144, 144-ball UFBGA, 6x6 mm, pitch 0.4 mm
+  - LQFP100, 100-lead LQFP, 14x14 mm, pitch 0.5 mm
+  - TFBGA100, 100-ball TFBGA, 9x9 mm, pitch 0.8 mm
+  - VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm
+  - LQFP64, 64-lead LQFP, 10x10 mm, pitch 0.5 mm
+  - QFN64, 64-pad QFN 9x9 mm, pitch 0.5 mm with wettable flanks
+
+#### Board info
+- [SAM E70 XPLAINED](https://www.microchip.com/en-us/development-tool/ATSAME70-XPLD)

bsp/microchip/same70/README_zh.md

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+# SAME70Q21B BSP 介绍
+
+[English](README.md) 
+- MCU: ATSAME70Q21B @300MHz, 2MB FLASH, 384KB RAM
+- V71: 汽车级产品 AEC-Q100 Cortex-M7内核 + 100M以太网 + 2路CAN-FD + 丰富外设
+- E70: 工业级产品 -40~105C Cortex-M7内核 + 100M以太网 + 2路CAN-FD + 丰富外设
+- S70: 工业级产品 -40~105C Cortex-M7内核 + 丰富外设
+- 管脚: J系列-64 pins, N系列-100 pins, Q系列-144 pins
+- Flash: 尾缀19=512KB, 20=1024KB, 21=2048KB (flash容量=2^n)
+- 手册: <https://www.microchip.com/en-us/product/ATSAME70Q21>
+
+#### 关键特性
+
+#### 内核
+  - 32-bit Arm® Cortex®-M7 core + 双精度FPU + L1 cache: 16 Kbytes 数据DCache and 16 Kbytes 指令 Icache; 主频高达300 MHz, MPU, 2.14 DMIPS/MHz (Dhrystone 2.1), 支持 DSP指令集
+
+#### 内存
+  - 最大提供2MB 内嵌Flash，芯片内嵌独一无二的UID信息
+  - 最大提供384KB 内嵌多端口SRAM, 可以将其配置为ITCM, DTCM.
+  - 内部集成16 Kbytes ROM，用于板载Bootloader(UART0, USB)和IAP应用.
+  
+####  外设
+  - 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling
+  - 16-bit SDRAM Controller (SDRAMC) interfacing up to 128 MB and with on-the-fly scrambling
+  - One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE® 1588 PTP frames and 802.3az Energy-efficiency support.
+  - USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints, dedicated DMA
+  - 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
+  - Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time-triggered and event-triggered transmission
+  - MediaLB® device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks
+  - Three USARTs, USART0, USART1, USART2, support LIN mode, ISO7816, IrDA®, RS-485, SPI, Manchester and Modem modes; USART1 supports LON mode.
+  - Five 2-wire UARTs with SleepWalking™ support
+  - Three Two-Wire Interfaces (TWIHS) (I2C-compatible) with SleepWalking support
+  - Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and onthe-fly scrambling
+  - Two Serial Peripheral Interfaces (SPI)
+  - One Serial Synchronous Controller (SSC) with I2S and TDM support
+  - Two Inter-IC Sound Controllers (I2SC)
+  - One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
+  - Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
+  - Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control
+  - Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7 Msps. Offset and gain error correction feature.
+  - One 2-channel, 12-bit, 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over Sampling modes
+  - One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis
+
+#### 加密模块
+  - True Random Number Generator (TRNG)
+  - AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications
+  - Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.
+
+#### I/O接口
+  - Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination
+  - Five Parallel Input/Output Controllers (PIO)
+
+#### 工作电压
+  - Single supply voltage from 3.0V to 3.6V for Qualification AEC - Q100 Grade 2 Devices
+  - Single Supply voltage from 1.7V to 3.6V for Industrial Temperature Devices
+
+#### 封装
+  - LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm
+  - LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.8 mm
+  - TFBGA144, 144-ball TFBGA, 10x10 mm, pitch 0.8 mm
+  - UFBGA144, 144-ball UFBGA, 6x6 mm, pitch 0.4 mm
+  - LQFP100, 100-lead LQFP, 14x14 mm, pitch 0.5 mm
+  - TFBGA100, 100-ball TFBGA, 9x9 mm, pitch 0.8 mm
+  - VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm
+  - LQFP64, 64-lead LQFP, 10x10 mm, pitch 0.5 mm
+  - QFN64, 64-pad QFN 9x9 mm, pitch 0.5 mm with wettable flanks
+
+#### 官方开发板信息
+- [SAM E70 XPLAINED](https://www.microchip.com/en-us/development-tool/ATSAME70-XPLD)

bsp/microchip/same70/SConscript

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+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/microchip/same70/SConstruct

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+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread-' + rtconfig.DEVICE_PART + '.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread-'+ rtconfig.DEVICE_PART + '.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/microchip/same70/applications/SConscript

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+import rtconfig
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/microchip/same70/applications/can_demo.c

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+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+#include "atmel_start.h"
+#include "driver_init.h"
+#include "utils.h"
+
+#include "can_demo.h"
+
+#ifdef SAM_CAN_EXAMPLE
+
+static volatile enum can_async_interrupt_type can_errors;
+static rt_sem_t   can_txdone;
+static rt_sem_t   can_rxdone;
+static rt_uint8_t can_stack[ 512 ];
+static struct rt_thread can_thread;
+
+/**
+ * @brief    Callback function and should be invoked after call can_async_write.
+ *
+ * @note
+ *
+ * @param    descr is CAN device description.
+ *
+ * @return   None.
+ */
+
+static void can_tx_callback(struct can_async_descriptor *const descr)
+{
+    rt_err_t result;
+
+    rt_interrupt_enter();
+    result = rt_sem_release(can_txdone);
+    if (RT_EOK != result)
+    {
+#ifndef RT_USING_FINSH
+        rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief    Callback function and should be invoked after remote device send.
+ *
+ * @note     This callback function will be called in CAN interrupt function
+ *
+ * @param    descr is CAN device description.
+ *
+ * @return   None.
+ */
+
+static void can_rx_callback(struct can_async_descriptor *const descr)
+{
+    rt_err_t result;
+
+    rt_interrupt_enter();
+    result = rt_sem_release(can_rxdone);
+    if (RT_EOK != result)
+    {
+#ifndef RT_USING_FINSH
+        rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief    Callback function and should be invoked after CAN device IRQ handler detects errors happened.
+ *
+ * @note     This callback function will be called in CAN interrupt function
+ *
+ * @param    descr is CAN device description.
+ *
+ * @return   None.
+ */
+
+static void can_err_callback(struct can_async_descriptor *const descr,
+                             enum can_async_interrupt_type type)
+{
+    rt_err_t result;
+
+    if (type == CAN_IRQ_EW)
+    {
+      /* Error warning, Error counter has reached the error warning limit of 96,
+       * An error count value greater than about 96 indicates a heavily disturbed
+       * bus. It may be of advantage to provide means to test for this condition.
+       */
+    }
+    else if (type == CAN_IRQ_EA)
+    {
+        /* Error Active State, The CAN node normally take part in bus communication
+         * and sends an ACTIVE ERROR FLAG when an error has been detected.
+         */
+    }
+    else if (type == CAN_IRQ_EP)
+    {
+        /* Error Passive State, The Can node goes into error passive state if at least
+         * one of its error counters is greater than 127. It still takes part in bus
+         * activities, but it sends a passive error frame only, on errors.
+         */
+    }
+    else if (type == CAN_IRQ_BO)
+    {
+        /* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is
+         * greater than or equal to 256.
+         */
+
+        /* Suspend CAN task and re-initialize CAN module. */
+        can_errors = type;
+        rt_interrupt_enter();
+        result = rt_sem_release(can_rxdone);
+        if (RT_EOK != result)
+        {
+#ifndef RT_USING_FINSH
+            rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+        }
+        rt_interrupt_leave();
+    }
+    else if (type == CAN_IRQ_DO)
+    {
+        /* Data Overrun in receive queue. A message was lost because the messages in
+         * the queue was not reading and releasing fast enough. There is not enough
+         * space for a new message in receive queue.
+         */
+
+        /* Suggest to delete CAN task and re-initialize it. */
+        can_errors = type;
+        rt_interrupt_enter();
+        result = rt_sem_release(can_rxdone);
+        if (RT_EOK != result)
+        {
+#ifndef RT_USING_FINSH
+            rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+        }
+        rt_interrupt_leave();
+    }
+};
+
+/**
+ * @brief    Initialize CAN module before task run.
+ *
+ * @note     This function will set CAN Tx/Rx callback function and filters.
+ *
+ * @param    None.
+ *
+ * @return   None.
+ */
+
+static inline void can_demo_init(void)
+{
+    struct can_filter  filter;
+
+    /**
+     * CAN_Node0_tx_callback callback should be invoked after call
+     * can_async_write, and remote device should receive message with ID=0x45A
+     */
+    can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback);
+
+    /**
+     * CAN_0_rx_callback callback should be invoked after call
+     * can_async_set_filter and remote device send CAN Message with the same
+     * content as the filter.
+     */
+    can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback);
+
+
+    /* Should set at least one CAN standard & message filter before enable it. */
+
+    filter.id   = 0x469;
+    filter.mask = 0;
+    can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter);
+
+    /* If set second standard message filter, should increase filter index
+     * and filter algorithm
+     * For example: index should set to 1, otherwise it will replace filter 0.
+     * can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */
+
+    filter.id   = 0x10000096;
+    filter.mask = 0;
+    can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter);
+
+    can_async_enable(&CAN_0);
+}
+
+/**
+ * @brief    CAN task.
+ *
+ * @note     This task will waiting for CAN RX semaphore and then process input.
+ *
+ * @param    parameter - task input parameter.
+ *
+ * @return   None.
+ */
+
+static void can_thread_entry(void* parameter)
+{
+    int32_t  ret;
+    rt_err_t result;
+    uint8_t  data[64];
+    uint32_t count=0;
+    struct can_message msg;
+
+    while (1)
+    {
+#ifndef RT_USING_FINSH
+        rt_kprintf("can task run count : %d\r\n",count);
+#endif
+        count++;
+
+        result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER);
+        if (RT_EOK != result)
+            continue;
+
+        do
+        {
+            /* Process the incoming packet. */
+            ret = can_async_read(&CAN_0, &msg);
+            if (ret == ERR_NONE)
+            {
+#ifndef RT_USING_FINSH
+                rt_kprintf("CAN RX Message is % frame\r\n",
+                           msg.type == CAN_TYPE_DATA ? "data" : "remote");
+                rt_kprintf("CAN RX Message is % frame\r\n",
+                           msg.type == CAN_FMT_STDID ? "Standard" : "Extended");
+                rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len);
+                rt_kprintf("CAN RX Message content: ");
+                for (uint8_t i = 0; i < msg.len; i++)
+                    rt_kprintf("0x%02X ", data[i]);
+                rt_kprintf("\r\n");
+#endif
+            }
+        } while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */
+
+        /* CAN task got CAN error message, handler CAN Error Status */
+        if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO))
+        {
+            can_async_init(&CAN_0, MCAN1);
+        }
+    }
+}
+
+/**
+ * @brief    Call this function will to send a CAN message.
+ *
+ * @note
+ *
+ * @param    msg - message to be sent, timeouts - wait timeouts for Tx completion.
+ *
+ * @return   RT_OK or RT_ERROR.
+ */
+
+rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts)
+{
+    rt_err_t result;
+
+    if (RT_NULL == msg)
+    {
+        rt_kprintf("can_send_message input message error\r\n");
+        return RT_ERROR;
+    }
+
+    can_async_write(&CAN_0, msg);
+    result = rt_sem_take(can_rxdone, timeouts);
+
+    return result;
+}
+
+/**
+ * @brief    Call this function will create a CAN task.
+ *
+ * @note     Should create Tx/Rx semaphore before run task.
+ *
+ * @param    None.
+ *
+ * @return   RT_OK or -RT_ERROR.
+ */
+
+rt_err_t can_demo_run(void)
+{
+    rt_err_t result;
+
+    can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO);
+    if (RT_NULL == can_rxdone)
+    {
+        rt_kprintf("can_rx semaphore create failed\r\n");
+        return (-RT_ERROR);
+    }
+
+    can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO);
+    if (RT_NULL == can_txdone)
+    {
+        rt_kprintf("can_tx semaphore create failed\r\n");
+        return (-RT_ERROR);
+    }
+
+    can_demo_init();
+
+    /* initialize CAN thread */
+    result = rt_thread_init(&can_thread,
+                            "can",
+                            can_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t*)&can_stack[0],
+                            sizeof(can_stack),
+                            RT_THREAD_PRIORITY_MAX/3,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&can_thread);
+    }
+
+    return result;
+}
+#endif
+
+/*@}*/

bsp/microchip/same70/applications/can_demo.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __APPLICATION_CAN_H_
+#define __APPLICATION_CAN_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+rt_err_t can_demo_run(void);
+
+rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts);
+
+#endif // __APPLICATION_CAN_H_

bsp/microchip/same70/applications/main.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+#include "atmel_start.h"
+#include <hal_gpio.h>
+
+#ifdef SAM_CAN_EXAMPLE
+#include "can_demo.h"
+#endif
+
+static rt_uint8_t led_stack[ 512 ];
+static struct rt_thread led_thread;
+
+static void led_thread_entry(void* parameter)
+{
+    unsigned int count=0;
+
+    while (1)
+    {
+        /* toggle led */
+#ifndef RT_USING_FINSH
+        rt_kprintf("led toggle, count : %d\r\n",count);
+#endif
+        count++;
+        gpio_toggle_pin_level(LED0);
+        rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
+    }
+}
+
+int main(void)
+{
+    rt_err_t result;
+
+    /* initialize led thread */
+    result = rt_thread_init(&led_thread,
+                            "led",
+                            led_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t*)&led_stack[0],
+                            sizeof(led_stack),
+                            RT_THREAD_PRIORITY_MAX/3,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&led_thread);
+    }
+
+#ifdef SAM_CAN_EXAMPLE
+    can_demo_run();
+#endif
+
+    return 0;
+}
+
+/*@}*/

bsp/microchip/same70/board/Kconfig

@@ -0,0 +1,50 @@
+menu "Hardware Drivers Config"
+
+choice
+    prompt "select chip type"
+    default SOC_SAME70Q21
+
+    config SOC_SAME70Q21
+    bool "SOC_SAME70Q21"
+    help
+        Refer to SAME70 DataSheet
+
+    config SOC_SAME70N21
+    bool "SOC_SAME70N21"
+    help
+        Refer to SAME70 DataSheet
+
+    config SOC_SAME70J21
+    bool "SOC_SAME70J21"
+    help
+        Refer to SAME70 DataSheet
+
+endchoice 
+endmenu
+
+menu "Onboard Peripheral Drivers"
+    config SAME70_CAN0
+        bool "Enable CAN0"
+        default false
+
+    config SAME70_ADC0
+        bool "Enable ADC0"
+        default false
+endmenu
+
+menu "Application Demo Config"
+    config SAM_CAN_EXAMPLE
+        bool "Enable SAM CAN Example"
+        depends on SAME70_CAN0
+        default true
+        help
+            Add CAN example task to project
+
+    config SAM_ADC_EXAMPLE
+        bool "Enable SAM ADC Example"
+        depends on SAME70_ADC0
+        default true
+        help
+            Add ADC example task to project
+
+endmenu

bsp/microchip/same70/board/SConscript

@@ -0,0 +1,17 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+# You can select chips from the list above
+CPPDEFINES = ['SAME70xxx']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/microchip/same70/board/board.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <string.h>
+
+#include <atmel_start.h>
+#include "peripheral_clk_config.h"
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef RT_USING_SERIAL
+extern int rt_hw_uart_init(void);
+#endif
+
+static struct io_descriptor* g_stdio;
+
+void rt_hw_console_output(const char *str)
+{
+    io_write(g_stdio, (uint8_t *)str, strlen(str));
+}
+RTM_EXPORT(rt_hw_console_output);
+
+static inline void hw_board_init_usart(void)
+{
+    usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
+    usart_sync_enable(&TARGET_IO);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial SAME70 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* Initializes MCU, drivers and middleware */
+    atmel_start_init();
+
+    /* Disable the watchdog */
+    WDT->WDT_MR = WDT_MR_WDDIS;
+
+    SCB_EnableICache();
+
+    /* enable USART stdout module */
+    hw_board_init_usart();
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* init systick */
+    SysTick_Config(CONF_CPU_FREQUENCY / RT_TICK_PER_SECOND);
+
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+
+#ifdef RT_USING_HEAP
+    #if defined(__CC_ARM) || defined(__CLANG_ARM)
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)HEAP_END);
+    #elif __ICCARM__
+        rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
+    #else
+        /* init memory system */
+        rt_system_heap_init((void*)&__bss_end, (void*)HEAP_END);
+    #endif
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/microchip/same70/board/board.h

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "sam.h"
+
+// <o> Internal SRAM memory size[Kbytes] <256-384>
+//  <i>Default: 384
+#if defined(__SAME70J19B__) || defined(__ATSAME70J19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAME70J20B__) || defined(__ATSAME70J20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAME70J21B__) || defined(__ATSAME70J21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAME70N19B__) || defined(__ATSAME70N19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAME70N20B__) || defined(__ATSAME70N20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAME70N21B__) || defined(__ATSAME70N21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAME70Q19B__) || defined(__ATSAME70Q19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAME70Q20B__) || defined(__ATSAME70Q20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAME70Q21B__) || defined(__ATSAME70Q21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMS70J19B__) || defined(__ATSAMS70J19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMS70J20B__) || defined(__ATSAMS70J20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMS70J21B__) || defined(__ATSAMS70J21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMS70N19B__) || defined(__ATSAMS70N19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMS70N20B__) || defined(__ATSAMS70N20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMS70N21B__) || defined(__ATSAMS70N21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMS70Q19B__) || defined(__ATSAMS70Q19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMS70Q20B__) || defined(__ATSAMS70Q20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMS70Q21B__) || defined(__ATSAMS70Q21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV70J19B__) || defined(__ATSAMV70J19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMV70J20B__) || defined(__ATSAMV70J20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV70J21B__) || defined(__ATSAMV70J21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV70N19B__) || defined(__ATSAMV70N19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMV70N20B__) || defined(__ATSAMV70N20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV70N21B__) || defined(__ATSAMV70N21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV70Q19B__) || defined(__ATSAMV70Q19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMV70Q20B__) || defined(__ATSAMV70Q20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV70Q21B__) || defined(__ATSAMV70Q21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV71J19B__) || defined(__ATSAMV71J19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMV71J20B__) || defined(__ATSAMV71J20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV71J21B__) || defined(__ATSAMV71J21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV71N19B__) || defined(__ATSAMV71N19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMV71N20B__) || defined(__ATSAMV71N20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV71N21B__) || defined(__ATSAMV71N21B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV71Q19B__) || defined(__ATSAMV71Q19B__)
+  #define SAME70_SRAM_SIZE   256
+#elif defined(__SAMV71Q20B__) || defined(__ATSAMV71Q20B__)
+  #define SAME70_SRAM_SIZE   384
+#elif defined(__SAMV71Q21B__) || defined(__ATSAMV71Q21B__)
+  #define SAME70_SRAM_SIZE   384
+#else
+#error Board does not support the specified device
+#endif
+
+#define SAME70_SRAM_END    (0x20400000 + SAME70_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN    (__segment_begin("HEAP"))
+#define HEAP_END      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN    (&__bss_end)
+#define HEAP_END      SAME70_SRAM_END
+#endif
+
+void rt_hw_board_init(void);
+
+#endif
+

bsp/microchip/same70/board/serial.c

@@ -0,0 +1,199 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <atmel_start.h>
+
+/* SAM MCU serial device */
+static struct rt_serial_device sam_serial;
+
+/**
+ * @brief Configure serial port
+ *
+ * This function will configure UART baudrate, parity and so on.
+ *
+ * @return RT_EOK.
+ */
+static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+    RT_ASSERT(cfg  != RT_NULL);
+
+    usart_sync_disable(desc);
+
+    /* Set baudrate */
+    usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
+
+    /* Set stop bit */
+    if (cfg->stop_bits == STOP_BITS_1)
+        usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
+    else if (cfg->stop_bits == STOP_BITS_2)
+        usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
+
+    if (cfg->bit_order == BIT_ORDER_LSB)
+        usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
+    else if (cfg->bit_order == BIT_ORDER_MSB)
+        usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
+
+    /* Set character size */
+    switch (cfg->data_bits)
+    {
+        case DATA_BITS_5:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
+            break;
+        case DATA_BITS_6:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
+            break;
+        case DATA_BITS_7:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
+            break;
+        case DATA_BITS_8:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
+            break;
+        case DATA_BITS_9:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
+            break;
+        default:
+            break;
+    }
+
+    if (cfg->parity == PARITY_NONE)
+        usart_sync_set_parity(desc, USART_PARITY_NONE);
+    else if (cfg->parity == PARITY_ODD)
+        usart_sync_set_parity(desc, USART_PARITY_ODD);
+    else if (cfg->parity == PARITY_EVEN)
+        usart_sync_set_parity(desc, USART_PARITY_EVEN);
+
+    usart_sync_enable(desc);
+
+    return RT_EOK;
+}
+
+/**
+ * @brief Control serial port
+ *
+ * This function provide UART enable/disable control.
+ *
+ * @return RT_EOK.
+ */
+static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    switch (cmd)
+    {
+        /* disable interrupt */
+        case RT_DEVICE_CTRL_CLR_INT:
+            usart_sync_disable(desc);
+            break;
+        /* enable interrupt */
+        case RT_DEVICE_CTRL_SET_INT:
+            usart_sync_enable(desc);
+            break;
+        /* UART config */
+        case RT_DEVICE_CTRL_CONFIG :
+            break;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief Serial sends a char
+ *
+ * This function will send a char to the UART
+ *
+ * @return 1.
+ */
+static int serial_putc(struct rt_serial_device *serial, char c)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    io_write(&desc->io, (const uint8_t *)&c, 1);
+
+    return 1;
+}
+
+/**
+ * @brief Serial gets a char
+ *
+ * This function will get a char from the UART
+ *
+ * @return received char character or -1 if no char received.
+ */
+static int serial_getc(struct rt_serial_device *serial)
+{
+    char c;
+    int ch;
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    ch = -1;
+    if (usart_sync_is_rx_not_empty(desc))
+    {
+        io_read(&desc->io, (uint8_t *)&c, 1);;
+        ch = c & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops sam_serial_ops =
+{
+    serial_configure,
+    serial_control,
+    serial_putc,
+    serial_getc,
+};
+
+/**
+ * @brief Initialize the UART
+ *
+ * This function initialize the UART
+ *
+ * @return None.
+ */
+int rt_hw_uart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    sam_serial.ops       = &sam_serial_ops;
+    sam_serial.config    = config;
+    sam_serial.serial_rx = RT_NULL;
+    sam_serial.serial_rx = RT_NULL;
+    rt_hw_serial_register(&sam_serial, "uart0",
+                          RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
+
+    return 0;
+}
+
+/*@}*/

bsp/microchip/same70/board/serial.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __BOARD_SERIAL_H_
+#define __BOARD_SERIAL_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+int rt_hw_uart_init(void);
+
+#endif // __BOARD_SERIAL_H_

bsp/microchip/same70/bsp/AtmelStart.env_conf

@@ -0,0 +1,6 @@
+<environment>
+  <configurations/>
+  <device-packs>
+    <device-pack device="ATSAME70Q21B" name="SAME70_DFP" vendor="Atmel" version="2.4.166"/>
+  </device-packs>
+</environment>

bsp/microchip/same70/bsp/AtmelStart.gpdsc

@@ -0,0 +1,179 @@
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
+  <vendor>Atmel</vendor>
+  <name>SAME70 LED switcher</name>
+  <description>Project generated by Atmel Start</description>
+  <url>http://start.atmel.com/</url>
+  <releases>
+    <release version="1.0.1">Initial version</release>
+  </releases>
+  <taxonomy>
+    <description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
+  </taxonomy>
+  <generators>
+    <generator id="AtmelStart">
+      <description>Atmel Start</description>
+      <select Dname="ATSAME70Q21B" Dvendor="Atmel:3"/>
+      <command>http://start.atmel.com/</command>
+      <files>
+        <file category="generator" name="atmel_start_config.atstart"/>
+        <file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
+      </files>
+    </generator>
+  </generators>
+  <conditions>
+    <condition id="CMSIS Device Startup">
+      <description>Dependency on CMSIS core and Device Startup components</description>
+      <require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
+      <require Cclass="Device" Cgroup="Startup" Cversion="2.4.0"/>
+    </condition>
+    <condition id="ARMCC, GCC, IAR">
+      <require Dname="ATSAME70Q21B"/>
+      <accept Tcompiler="ARMCC"/>
+      <accept Tcompiler="GCC"/>
+      <accept Tcompiler="IAR"/>
+    </condition>
+    <condition id="GCC">
+      <require Dname="ATSAME70Q21B"/>
+      <accept Tcompiler="GCC"/>
+    </condition>
+  </conditions>
+  <components generator="AtmelStart">
+    <component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
+      <description>Atmel Start Framework</description>
+      <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
+      <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_time_measure.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_can_async.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
+        <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_acc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_afec_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_chipid_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dacc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_efc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gmac_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gpbr_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hsmci_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2sc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_isi_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_lockbit_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_matrix_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mcan_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pio_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pmc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pwm_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rswdt_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtt_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdramc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_smc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_spi_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ssc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_twihs_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_uart_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usart_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usbhs_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_utmi_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e70b.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_xdmac_e70b.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="led_switcher_main.c"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/led_switcher.rst"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m7_base.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/mcan/hpl_mcan.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/mcan/hpl_mcan.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/pio/hpl_gpio_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/pmc/hpl_pmc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/pmc/hpl_pmc.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/pmc/hpl_sleep.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/systick/hpl_systick_ARMv7_base.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/usart/hpl_usart.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/usart/hpl_usart_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/xdmac/hpl_xdmac.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mcan_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_pmc_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_systick_ARMv7_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_usart_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_xdmac_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/mcan"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/pio"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/pmc"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/systick"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/usart"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/xdmac"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+      </files>
+    </component>
+  </components>
+</package>

bsp/microchip/same70/bsp/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/microchip/same70/bsp/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/microchip/same70/bsp/CMSIS/Core/Include/mpu_armv7.h

@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

bsp/microchip/same70/bsp/CMSIS/Core/Include/mpu_armv8.h

@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

bsp/microchip/same70/bsp/CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

bsp/microchip/same70/bsp/CMSIS/Documentation/Core/html/index.html

@@ -0,0 +1,196 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>Overview</title>
+<title>CMSIS-Core (Cortex-M): Overview</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<script type="text/javascript" src="printComponentTabs.js"></script>
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+  $(window).load(resizeHeight);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.1.2</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <script type="text/javascript">
+		<!--
+		writeComponentTabs.call(this);
+		//-->
+      </script>
+	  </ul>
+</div>
+<!-- Generated by Doxygen 1.8.6 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+      <div id="nav-sync" class="sync"></div>
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+$(document).ready(function(){initNavTree('index.html','');});
+</script>
+<div id="doc-content">
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+<div class="header">
+  <div class="headertitle">
+<div class="title">Overview </div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
+<ul>
+<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
+<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
+<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
+<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
+<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
+<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
+</ul>
+<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
+<ul>
+<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
+<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone&reg; for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li>
+<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
+<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
+<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
+<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
+</ul>
+<hr/>
+<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2>
+<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p>
+<table class="doxtable">
+<tr>
+<th>File/Folder </th><th>Content  </th></tr>
+<tr>
+<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
+<tr>
+<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
+<tr>
+<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr>
+<tr>
+<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr>
+</table>
+<hr/>
+<h1><a class="anchor" id="ref_v6-v8M"></a>
+Processor Support</h1>
+<p>CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.</p>
+<h2><a class="anchor" id="ref_man_sec"></a>
+Cortex-M Reference Manuals</h2>
+<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
+<ul>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
+</ul>
+<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p>
+<ul>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li>
+</ul>
+<h2><a class="anchor" id="ARMv8M"></a>
+Armv8-M Architecture</h2>
+<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.</p>
+<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
+<hr/>
+<h1><a class="anchor" id="tested_tools_sec"></a>
+Tested and Verified Toolchains</h1>
+<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p>
+<ul>
+<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)</li>
+<li>Arm: Arm Compiler 6.9</li>
+<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)</li>
+<li>GNU: GNU Tools for Arm Embedded 6.3.1 20170620</li>
+<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li>
+</ul>
+<hr/>
+ </div></div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

bsp/microchip/same70/bsp/SConscript

@@ -0,0 +1,54 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+#var defined
+CPPDEFINES = []
+
+#common lib define
+CPPDEFINES += [rtconfig.DEVICE_TYPE]
+
+# The set of source files associated with this SConscript file.
+
+src  = Glob('hal/src/*.c')
+src += Glob('hal/utils/src/*.c')
+src += Glob('hpl/core/*.c')
+src += Glob('hpl/mcan/*.c')
+src += Glob('hpl/pmc/*.c')
+src += Glob('hpl/systick/*.c')
+src += Glob('hpl/usart/*.c')
+src += Glob('hpl/xdmac/*.c')
+src += [cwd + '/atmel_start.c']
+src += [cwd + '/driver_init.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/same70b/gcc/system_same70q21b.c']
+    src += [cwd + '/same70b/gcc/gcc/startup_same70q21b.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/same70b/armcc/Source/' + 'system_same70q21b.c']
+    src += [cwd + '/same70b/armcc/Source/ARM/' + 'startup_SAME70.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/same70b/iar/' + 'system_same70q21b.c']
+    src += [cwd + '/same70b/iar/iar/' + 'startup_same70q21b.c']
+
+path = [
+    cwd,
+    cwd + '/CMSIS/Core/Include',
+    cwd + '/config',
+    cwd + '/hal/include',
+    cwd + '/hal/utils/include',
+    cwd + '/hpl/core',
+    cwd + '/hpl/mcan',
+    cwd + '/hpl/pio',
+    cwd + '/hpl/pmc',
+    cwd + '/hpl/systick',
+    cwd + '/hpl/usart',
+    cwd + '/hri',
+    cwd + '/same70b/include',]
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/microchip/same70/bsp/atmel_start.c

@@ -0,0 +1,9 @@
+#include <atmel_start.h>
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+	system_init();
+}

bsp/microchip/same70/bsp/atmel_start.h

@@ -0,0 +1,18 @@
+#ifndef ATMEL_START_H_INCLUDED
+#define ATMEL_START_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "driver_init.h"
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

bsp/microchip/same70/bsp/atmel_start_pins.h

@@ -0,0 +1,27 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef ATMEL_START_PINS_H_INCLUDED
+#define ATMEL_START_PINS_H_INCLUDED
+
+#include <hal_gpio.h>
+
+// SAME70 has 4 pin functions
+
+#define GPIO_PIN_FUNCTION_A 0
+#define GPIO_PIN_FUNCTION_B 1
+#define GPIO_PIN_FUNCTION_C 2
+#define GPIO_PIN_FUNCTION_D 3
+
+#define SW0 GPIO(GPIO_PORTA, 11)
+#define PA21 GPIO(GPIO_PORTA, 21)
+#define PB4 GPIO(GPIO_PORTB, 4)
+#define LED0 GPIO(GPIO_PORTC, 8)
+#define PC12 GPIO(GPIO_PORTC, 12)
+#define PC14 GPIO(GPIO_PORTC, 14)
+
+#endif // ATMEL_START_PINS_H_INCLUDED

bsp/microchip/same70/bsp/config/hpl_mcan_config.h

@@ -0,0 +1,379 @@
+/* Auto-generated config file hpl_mcan_config.h */
+#ifndef HPL_MCAN_CONFIG_H
+#define HPL_MCAN_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_CAN1_ENABLED
+#define CONF_CAN1_ENABLED 1
+#endif
+// <h> Basic Configuration
+
+// <o> CAN Mode Enable
+// <i> decide whether enable CAN FD mode
+// <0=> ISO11898_1
+// <1=> FD
+// <id> can_cccr_niso
+#ifndef CONF_CAN1_CCCR_NISO
+#define CONF_CAN1_CCCR_NISO 0
+#endif
+
+// </h>
+
+// <h> Normal Bit Timing and Prescaler Configuration
+
+// <o> Baud Rate Prescaler <1-512>
+// <i> The value by which the oscillator frequency is divided for generating the CAN time quanta. CAN time quantum (tq) = (This value) x CAN core clock cycles (tcore clock)
+// <id> can_nbtp_nbrp
+#ifndef CONF_CAN1_NBTP_NBRP
+#define CONF_CAN1_NBTP_NBRP 4
+#endif
+
+// <o> time segment before sample point <2-256>
+// <i> The duration of time segment = (This value) x CAN time quantum (tq)
+// <id> can_nbtp_ntseg1
+#ifndef CONF_CAN1_NBTP_NTSEG1
+#define CONF_CAN1_NBTP_NTSEG1 31
+#endif
+
+// <o> time segment after sample point <2-128>
+// <i> The duration of time segment = (This value) x CAN time quantum (tq)
+// <id> can_nbtp_ntseg2
+#ifndef CONF_CAN1_NBTP_NTSEG2
+#define CONF_CAN1_NBTP_NTSEG2 8
+#endif
+
+// <o> Data (Re)Syncronization Jump Width <1-128>
+// <i> The duration of a synchronization jump = (This value) x CAN time quantum (tq)
+// <id> can_nbtp_nsjw
+#ifndef CONF_CAN1_NBTP_NSJW
+#define CONF_CAN1_NBTP_NSJW 10
+#endif
+
+// </h>
+// <h> Data Bit Timing and Prescaler Configuration
+
+// <o> Data Baud Rate Prescaler <1-32>
+// <i> The value by which the peripheral clock is divided for generating the bit time quanta. CAN time quantum (tq) = (This value) x CAN core clock cycles (tcore clock)
+// <id> can_dbtp_dbrp
+#ifndef CONF_CAN1_DBTP_DBRP
+#define CONF_CAN1_DBTP_DBRP 1
+#endif
+
+// <o> Data time segment before sample point <2-32>
+// <i> The duration of time segment = (This value) x CAN time quantum (tq)
+// <id> can_dbtp_dtseg1
+#ifndef CONF_CAN1_DBTP_DTSEG1
+#define CONF_CAN1_DBTP_DTSEG1 31
+#endif
+
+// <o> Data time segment after sample point <1-16>
+// <i> The duration of time segment = (This value) x CAN time quantum (tq)
+// <id> can_dbtp_dtseg2
+#ifndef CONF_CAN1_DBTP_DTSEG2
+#define CONF_CAN1_DBTP_DTSEG2 8
+#endif
+
+// <o> Data (Re)Syncronization Jump Width <1-8>
+// <i> The duration of a synchronization jump = (This value) x CAN time quantum (tq)
+// <id> can_dbtp_dsjw
+#ifndef CONF_CAN1_DBTP_DSJW
+#define CONF_CAN1_DBTP_DSJW 4
+#endif
+
+// <q> Transceiver Delay Compensation Enable
+// <i> Transceiver Delay Compensation Enable
+// <id> can_dbtp_tdc
+#ifndef CONF_CAN1_DBTP_TDC
+#define CONF_CAN1_DBTP_TDC 0
+#endif
+
+// <o> Transceiver Delay Compensation Offset <0-127>
+// <i> Transceiver Delay Compensation Offset
+// <id> can_tdcr_tdco
+#ifndef CONF_CAN1_TDCR_TDCO
+#define CONF_CAN1_TDCR_TDCO 11
+#endif
+
+// <o> Transmitter Delay Compensation Filter <0-127>
+// <i> Transmitter Delay Compensation Filter
+// <id> can_tdcr_tdcf
+#ifndef CONF_CAN1_TDCR_TDCF
+#define CONF_CAN1_TDCR_TDCF 11
+#endif
+
+// </h>
+
+// <h> RX FIFO Configuration
+
+// <o> Operation Mode
+// <i> Select Operation Mode
+// <0=> blocking mode
+// <1=> overwrite mode
+// <id> can_rxf0c_f0om
+#ifndef CONF_CAN1_RXF0C_F0OM
+#define CONF_CAN1_RXF0C_F0OM 0
+#endif
+
+// <o> Watermark <0-64>
+// <i> Watermark, 0 for disable watermark interrupt
+// <id> can_rxf0c_f0wm
+#ifndef CONF_CAN1_RXF0C_F0WM
+#define CONF_CAN1_RXF0C_F0WM 0
+#endif
+
+// <o> Size <0-64>
+// <i> Number of Rx FIFO 0 element
+// <id> can_rxf0c_f0s
+#ifndef CONF_CAN1_RXF0C_F0S
+#define CONF_CAN1_RXF0C_F0S 32
+#endif
+
+// <o> Data Field Size
+// <i> Rx FIFO 0 Data Field Size
+// <0=> 8 byte data field.
+// <1=> 12 byte data field.
+// <2=> 16 byte data field.
+// <3=> 20 byte data field.
+// <4=> 24 byte data field.
+// <5=> 32 byte data field.
+// <6=> 48 byte data field.
+// <7=> 64 byte data field.
+// <id> can_rxesc_f0ds
+#ifndef CONF_CAN1_RXESC_F0DS
+#define CONF_CAN1_RXESC_F0DS 0
+#endif
+
+/* Bytes size for CAN FIFO 0 element, plus 8 bytes for R0,R1 */
+#undef CONF_CAN1_F0DS
+#define CONF_CAN1_F0DS                                                                                                 \
+	((CONF_CAN1_RXESC_F0DS < 5) ? ((CONF_CAN1_RXESC_F0DS << 2) + 16) : (40 + ((CONF_CAN1_RXESC_F0DS % 5) << 4)))
+
+// </h>
+
+// <h> TX FIFO Configuration
+
+// <o> Transmit FIFO Size <0-32>
+// <i> Number of Tx Buffers used for Tx FIFO
+// <id> can_txbc_tfqs
+#ifndef CONF_CAN1_TXBC_TFQS
+#define CONF_CAN1_TXBC_TFQS 32
+#endif
+
+// <o> Tx Buffer Data Field Size
+// <i> Tx Buffer Data Field Size
+// <0=> 8 byte data field.
+// <1=> 12 byte data field.
+// <2=> 16 byte data field.
+// <3=> 20 byte data field.
+// <4=> 24 byte data field.
+// <5=> 32 byte data field.
+// <6=> 48 byte data field.
+// <7=> 64 byte data field.
+// <id> can_txesc_tbds
+#ifndef CONF_CAN1_TXESC_TBDS
+#define CONF_CAN1_TXESC_TBDS 0
+#endif
+
+/* Bytes size for CAN Transmit Buffer element, plus 8 bytes for R0,R1 */
+#undef CONF_CAN1_TBDS
+#define CONF_CAN1_TBDS                                                                                                 \
+	((CONF_CAN1_TXESC_TBDS < 5) ? ((CONF_CAN1_TXESC_TBDS << 2) + 16) : (40 + ((CONF_CAN1_TXESC_TBDS % 5) << 4)))
+
+// </h>
+
+// <h> TX Event Configuration
+
+// <o> Watermark <0-32>
+// <i> Watermark, 0 for disable watermark interrupt
+// <id> can_txefc_efwm
+#ifndef CONF_CAN1_TXEFC_EFWM
+#define CONF_CAN1_TXEFC_EFWM 0
+#endif
+
+// <o> Size <0-32>
+// <i> Number of Event FIFO element
+// <id> can_txefc_efs
+#ifndef CONF_CAN1_TXEFC_EFS
+#define CONF_CAN1_TXEFC_EFS 32
+#endif
+
+// </h>
+
+// <h> Filter Configuration
+
+// <o> Accept Non-matching Frames Standard
+// <i> Defines how received messages with 11-bit IDs that do not match any
+// <i> element of the filter list are treated.
+// <0=> Accept in Rx FIFO 0
+// <1=> Accept in Rx FIFO 1
+// <2=> Reject
+// <id> can_gfc_anfs
+#ifndef CONF_CAN1_GFC_ANFS
+#define CONF_CAN1_GFC_ANFS 2
+#endif
+
+// <o> Accept Non-matching Frames Extended
+// <i> Defines how received messages with 29-bit IDs that do not match any
+// <i> element of the filter list are treated.
+// <0=> Accept in Rx FIFO 0
+// <1=> Accept in Rx FIFO 1
+// <2=> Reject
+// <id> can_gfc_anfe
+#ifndef CONF_CAN1_GFC_ANFE
+#define CONF_CAN1_GFC_ANFE 2
+#endif
+
+// <o> Reject Remote Frames Standard
+// <i> Defines how received remote frames with 11-bit standard IDs.
+// <0=> Filter remote frames with 11-bit standard IDs
+// <1=> Reject all remote frames with 11-bit standard IDs
+// <id> can_gfc_rrfs
+#ifndef CONF_CAN1_GFC_RRFS
+#define CONF_CAN1_GFC_RRFS 0
+#endif
+
+// <o> Reject Remote Frames Extended
+// <i> Defines how received remote frames with 29-bit standard IDs.
+// <0=> Filter remote frames with 29-bit standard IDs
+// <1=> Reject all remote frames with 29-bit standard IDs
+// <id> can_gfc_rrfe
+#ifndef CONF_CAN1_GFC_RRFE
+#define CONF_CAN1_GFC_RRFE 0
+#endif
+
+// <o> Number of standard Message ID filter elements <0-128>
+// <i> Number of standard Message ID filter elements
+// <id> can_sidfc_lss
+#ifndef CONF_CAN1_SIDFC_LSS
+#define CONF_CAN1_SIDFC_LSS 128
+#endif
+
+// <o> Number of Extended Message ID filter elements <0-64>
+// <i> Number of Extended Message ID filter elements
+// <id> can_xidfc_lss
+#ifndef CONF_CAN1_XIDFC_LSS
+#define CONF_CAN1_XIDFC_LSS 64
+#endif
+
+// <o> Extended ID Mask <0x0000-0x1FFFFFFF>
+// <i> For acceptance filtering of extended frames the Extended ID AND Mask is
+// <i> ANDed with the Message ID of a received frame. Intended for masking of
+// <i> 29-bit IDs in SAE J1939. With the reset value of all bits set to one the
+// <i> mask is not active.
+// <id> can_xidam_eidm
+#ifndef CONF_CAN1_XIDAM_EIDM
+#define CONF_CAN1_XIDAM_EIDM 0x0
+#endif
+
+// </h>
+
+// <h> Interrupt Configuration
+
+// <q> Error Warning
+// <i> Indicates whether to not disable CAN error warning interrupt
+// <id> can_ie_ew
+#ifndef CONF_CAN1_IE_EW
+#define CONF_CAN1_IE_EW 1
+#endif
+
+// <q> Error Active
+// <i> Indicates whether to not disable CAN error active interrupt
+// <id> can_ie_ea
+#ifndef CONF_CAN1_IE_EA
+#define CONF_CAN1_IE_EA 1
+#endif
+
+// <q> Error Passive
+// <i> Indicates whether to not disable CAN error passive interrupt
+// <id> can_ie_ep
+#ifndef CONF_CAN1_IE_EP
+#define CONF_CAN1_IE_EP 1
+#endif
+
+// <q> Bus Off
+// <i> Indicates whether to not disable CAN bus off interrupt
+// <id> can_ie_bo
+#ifndef CONF_CAN1_IE_BO
+#define CONF_CAN1_IE_BO 1
+#endif
+
+// <q> Data Overrun
+// <i> Indicates whether to not disable CAN data overrun interrupt
+// <id> can_ie_do
+#ifndef CONF_CAN1_IE_DO
+#define CONF_CAN1_IE_DO 1
+#endif
+
+// </h>
+
+#ifndef CONF_CAN1_CCCR_REG
+#define CONF_CAN1_CCCR_REG (CONF_CAN1_CCCR_NISO << MCAN_CCCR_NISO_Pos)
+#endif
+
+#ifndef CONF_CAN1_NBTP_REG
+#define CONF_CAN1_NBTP_REG                                                                                             \
+	MCAN_NBTP_NBRP(CONF_CAN1_NBTP_NBRP - 1) | MCAN_NBTP_NTSEG1(CONF_CAN1_NBTP_NTSEG1 - 1)                              \
+	    | MCAN_NBTP_NTSEG2(CONF_CAN1_NBTP_NTSEG2 - 1) | MCAN_NBTP_NSJW(CONF_CAN1_NBTP_NSJW - 1)
+#endif
+
+#ifndef CONF_CAN1_DBTP_REG
+#define CONF_CAN1_DBTP_REG                                                                                             \
+	(CONF_CAN1_DBTP_TDC << MCAN_DBTP_TDC_Pos) | MCAN_DBTP_DBRP(CONF_CAN1_DBTP_DBRP - 1)                                \
+	    | MCAN_DBTP_DTSEG1(CONF_CAN1_DBTP_DTSEG1 - 1) | MCAN_DBTP_DTSEG2(CONF_CAN1_DBTP_DTSEG2 - 1)                    \
+	    | MCAN_DBTP_DSJW(CONF_CAN1_DBTP_DSJW - 1)
+#endif
+
+#ifndef CONF_CAN1_TDCR_REG
+#define CONF_CAN1_TDCR_REG MCAN_TDCR_TDCF(CONF_CAN1_TDCR_TDCF) | MCAN_TDCR_TDCO(CONF_CAN1_TDCR_TDCO)
+#endif
+
+#ifndef CONF_CAN1_RXF0C_REG
+#define CONF_CAN1_RXF0C_REG                                                                                            \
+	(CONF_CAN1_RXF0C_F0OM << MCAN_RXF0C_F0OM_Pos) | MCAN_RXF0C_F0WM(CONF_CAN1_RXF0C_F0WM)                              \
+	    | MCAN_RXF0C_F0S(CONF_CAN1_RXF0C_F0S)
+#endif
+
+#ifndef CONF_CAN1_RXESC_REG
+#define CONF_CAN1_RXESC_REG MCAN_RXESC_F0DS(CONF_CAN1_RXESC_F0DS)
+#endif
+
+#ifndef CONF_CAN1_TXESC_REG
+#define CONF_CAN1_TXESC_REG MCAN_TXESC_TBDS(CONF_CAN1_TXESC_TBDS)
+#endif
+
+#ifndef CONF_CAN1_TXBC_REG
+#define CONF_CAN1_TXBC_REG MCAN_TXBC_TFQS(CONF_CAN1_TXBC_TFQS)
+#endif
+
+#ifndef CONF_CAN1_TXEFC_REG
+#define CONF_CAN1_TXEFC_REG MCAN_TXEFC_EFWM(CONF_CAN1_TXEFC_EFWM) | MCAN_TXEFC_EFS(CONF_CAN1_TXEFC_EFS)
+#endif
+
+#ifndef CONF_CAN1_GFC_REG
+#define CONF_CAN1_GFC_REG                                                                                              \
+	MCAN_GFC_ANFS(CONF_CAN1_GFC_ANFS) | MCAN_GFC_ANFE(CONF_CAN1_GFC_ANFE) | (CONF_CAN1_GFC_RRFS << MCAN_GFC_RRFS_Pos)  \
+	    | (CONF_CAN1_GFC_RRFE << MCAN_GFC_RRFE_Pos)
+#endif
+
+#ifndef CONF_CAN1_SIDFC_REG
+#define CONF_CAN1_SIDFC_REG MCAN_SIDFC_LSS(CONF_CAN1_SIDFC_LSS)
+#endif
+
+#ifndef CONF_CAN1_XIDFC_REG
+#define CONF_CAN1_XIDFC_REG MCAN_XIDFC_LSE(CONF_CAN1_XIDFC_LSS)
+#endif
+
+#ifndef CONF_CAN1_XIDAM_REG
+#define CONF_CAN1_XIDAM_REG MCAN_XIDAM_EIDM(CONF_CAN1_XIDAM_EIDM)
+#endif
+
+#ifndef CONF_CAN0_IE_REG
+#define CONF_CAN0_IE_REG                                                                                               \
+	(CONF_CAN1_IE_EW << MCAN_IR_EW_Pos) | (CONF_CAN1_IE_EA << MCAN_IR_EP_Pos) | (CONF_CAN1_IE_EP << MCAN_IR_EP_Pos)    \
+	    | (CONF_CAN1_IE_BO << MCAN_IR_BO_Pos) | (CONF_CAN1_IE_DO << MCAN_IR_RF0L_Pos)
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCAN_CONFIG_H

bsp/microchip/same70/bsp/config/hpl_systick_ARMv7_config.h

@@ -0,0 +1,18 @@
+/* Auto-generated config file hpl_systick_ARMv7_config.h */
+#ifndef HPL_SYSTICK_ARMV7_CONFIG_H
+#define HPL_SYSTICK_ARMV7_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Advanced settings
+// <q> SysTick exception request
+// <i> Indicates whether the generation of SysTick exception is enabled or not
+// <id> systick_arch_tickint
+#ifndef CONF_SYSTICK_TICKINT
+#define CONF_SYSTICK_TICKINT 0
+#endif
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_SYSTICK_ARMV7_CONFIG_H

bsp/microchip/same70/bsp/config/hpl_usart_config.h

@@ -0,0 +1,215 @@
+/* Auto-generated config file hpl_usart_config.h */
+#ifndef HPL_USART_CONFIG_H
+#define HPL_USART_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_USART_1_ENABLE
+#define CONF_USART_1_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Frame parity
+// <0x0=>Even parity
+// <0x1=>Odd parity
+// <0x2=>Parity forced to 0
+// <0x3=>Parity forced to 1
+// <0x4=>No parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_USART_1_PARITY
+#define CONF_USART_1_PARITY 0x4
+#endif
+
+// <o> Character Size
+// <0x0=>5 bits
+// <0x1=>6 bits
+// <0x2=>7 bits
+// <0x3=>8 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_USART_1_CHSIZE
+#define CONF_USART_1_CHSIZE 0x3
+#endif
+
+// <o> Stop Bit
+// <0=>1 stop bit
+// <1=>1.5 stop bits
+// <2=>2 stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_USART_1_SBMODE
+#define CONF_USART_1_SBMODE 0
+#endif
+
+// <o> Clock Output Select
+// <0=>The USART does not drive the SCK pin
+// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
+// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
+// <id> usart_clock_output_select
+#ifndef CONF_USART_1_CLKO
+#define CONF_USART_1_CLKO 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_USART_1_BAUD
+#define CONF_USART_1_BAUD 115200
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_USART_1_ADVANCED_CONFIG
+#define CONF_USART_1_ADVANCED_CONFIG 1
+#endif
+
+// <o> Channel Mode
+// <0=>Normal Mode
+// <1=>Automatic Echo
+// <2=>Local Loopback
+// <3=>Remote Loopback
+// <i> Channel mode in USART frame
+// <id> usart_channel_mode
+#ifndef CONF_USART_1_CHMODE
+#define CONF_USART_1_CHMODE 0
+#endif
+
+// <q> 9 bits character enable
+// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
+// <id> usart_9bits_enable
+#ifndef CONF_USART_1_MODE9
+#define CONF_USART_1_MODE9 0
+#endif
+
+// <o> Variable Sync
+// <0=>User defined configuration
+// <1=>sync field is updated when a character is written into US_THR
+// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
+// <id> variable_sync
+#ifndef CONF_USART_1_VAR_SYNC
+#define CONF_USART_1_VAR_SYNC 0
+#endif
+
+// <o> Oversampling Mode
+// <0=>16 Oversampling
+// <1=>8 Oversampling
+// <i> Oversampling Mode in UART mode
+// <id> usart__oversampling_mode
+#ifndef CONF_USART_1_OVER
+#define CONF_USART_1_OVER 0
+#endif
+
+// <o> Inhibit Non Ack
+// <0=>The NACK is generated
+// <1=>The NACK is not generated
+// <i> Inhibit Non Acknowledge
+// <id> usart__inack
+#ifndef CONF_USART_1_INACK
+#define CONF_USART_1_INACK 1
+#endif
+
+// <o> Disable Successive NACK
+// <0=>NACK is sent on the ISO line as soon as a parity error occurs
+// <1=>Many parity errors generate a NACK on the ISO line
+// <i> Disable Successive NACK
+// <id> usart_dsnack
+#ifndef CONF_USART_1_DSNACK
+#define CONF_USART_1_DSNACK 0
+#endif
+
+// <o> Inverted Data
+// <0=>Data isn't inverted, nomal mode
+// <1=>Data is inverted
+// <i> Inverted Data
+// <id> usart_invdata
+#ifndef CONF_USART_1_INVDATA
+#define CONF_USART_1_INVDATA 0
+#endif
+
+// <o> Maximum Number of Automatic Iteration <0-7>
+// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
+// <id> usart_max_iteration
+#ifndef CONF_USART_1_MAX_ITERATION
+#define CONF_USART_1_MAX_ITERATION 0
+#endif
+
+// <q> Receive Line Filter enable
+// <i> whether the USART filters the receive line using a three-sample filter
+// <id> usart_receive_filter_enable
+#ifndef CONF_USART_1_FILTER
+#define CONF_USART_1_FILTER 0
+#endif
+
+// <q> Manchester Encoder/Decoder Enable
+// <i> whether the USART Manchester Encoder/Decoder
+// <id> usart_manchester_filter_enable
+#ifndef CONF_USART_1_MAN
+#define CONF_USART_1_MAN 0
+#endif
+
+// <o> Manchester Synchronization Mode
+// <0=>The Manchester start bit is a 0 to 1 transition
+// <1=>The Manchester start bit is a 1 to 0 transition
+// <i> Manchester Synchronization Mode
+// <id> usart_manchester_synchronization_mode
+#ifndef CONF_USART_1_MODSYNC
+#define CONF_USART_1_MODSYNC 0
+#endif
+
+// <o> Start Frame Delimiter Selector
+// <0=>Start frame delimiter is COMMAND or DATA SYNC
+// <1=>Start frame delimiter is one bit
+// <i> Start Frame Delimiter Selector
+// <id> usart_start_frame_delimiter
+#ifndef CONF_USART_1_ONEBIT
+#define CONF_USART_1_ONEBIT 0
+#endif
+
+// <o> Fractional Part <0-7>
+// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
+// <id> usart_arch_fractional
+#ifndef CONF_USART_1_FRACTIONAL
+#define CONF_USART_1_FRACTIONAL 0x0
+#endif
+
+// <o> Data Order
+// <0=>LSB is transmitted first
+// <1=>MSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_msbf
+#ifndef CONF_USART_1_MSBF
+#define CONF_USART_1_MSBF 0
+#endif
+
+// </e>
+
+#define CONF_USART_1_MODE 0x0
+
+// Calculate BAUD register value in UART mode
+#if CONF_USART1_CK_SRC < 3
+#ifndef CONF_USART_1_BAUD_CD
+#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER))
+#endif
+#ifndef CONF_USART_1_BAUD_FP
+#define CONF_USART_1_BAUD_FP                                                                                           \
+	((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD)
+#endif
+#elif CONF_USART1_CK_SRC == 3
+// No division is active. The value written in US_BRGR has no effect.
+#ifndef CONF_USART_1_BAUD_CD
+#define CONF_USART_1_BAUD_CD 1
+#endif
+#ifndef CONF_USART_1_BAUD_FP
+#define CONF_USART_1_BAUD_FP 1
+#endif
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_USART_CONFIG_H