mirror of
https://github.com/RT-Thread/rt-thread.git
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Add Microchip SAM series MCU support for RT-Thread (#5771)
* Add Microchip SAM series MCU support for RT-Thread Add Microchip SAM series MCU support for RT-Thread, including SAM Cortex-M0+, M4F and M7. * Add bsp directory to ignored check list Add bsp directory to ignored check list, add microchip /samc21/same54/same70 to workflows list * remove STDIO definition and bug fix 1. remove STDIO code from Microchip official BSP. 2. bug fix of SAME70 hpl/hpl_usart.c, samc21&same54 hpl/hpl_sercom.c baudrate update interface. 3. Add RT-Thread standard STDIO implementation on Microchip SAM MCU. * add CAN driver & example and script fix Add CAN driver and example for SAMC21/SAME5x/SAME70 and fix rtconfig.py issue(unused space might result link error) * Add Chinese version README Add Chinese version README for SAMC21/E54/E70
This commit is contained in:
Kevin Liu
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,6 @@
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# files format check exclude path, please follow the instructions below to modify;
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# If you need to exclude an entire folder, add the folder path in dir_path;
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# If you need to exclude a file, add the path to the file in file_path.
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dir_path:
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- bsp
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@@ -0,0 +1,31 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../.."
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# you can change the RTT_ROOT default: "rt-thread"
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "board/Kconfig"
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config SOC_SAME54
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bool
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select ARCH_ARM
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select ARCH_ARM_CORTEX_M
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select ARCH_ARM_CORTEX_M4
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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@@ -0,0 +1,106 @@
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# SAME54P20A BSP Introduction
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[中文](README_zh.md)
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- MCU: ATSAME54P20A @120MHz, 1MB FLASH, 256KB RAM
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- E54: Cortex-M4F + Advanced Feature Set + Ethernet + 2x CAN-FD
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- Pin: G=48 pins, J=64 pins, N=100 pins, P=128 pins
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- Flash: 18=256KB, 19=512KB, 20=1024KB (size=2^n)
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- SRAM : 128KB(Flash 256KB), 192KB(Flash 512KB), 256KB(Flash 1MB)
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- Datasheet: <https://www.microchip.com/en-us/product/ATSAME54P20>
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#### KEY FEATURES
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#### Core
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- 32-bit Arm® Cortex®-M4 core with single-precision FPU and 4 KB combined instruction cache and data cache; frequency up to 120 MHz, MPU, 403 CoreMark® at 120 MHz, and DSP instructions
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#### Memories
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- 1 MB/512 KB/256 KB in-system self-programmable Flash with:
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- Error Correction Code (ECC)
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- Dual bank with Read-While-Write (RWW) support
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- EEPROM hardware emulation
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- 128 KB, 192 KB, 256 KB SRAM main memory
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- 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
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- Up to 4 KB of Tightly Coupled Memory (TCM)
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- Up to 8 KB additional SRAM
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- Can be retained in backup mode
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- Eight 32-bit backup registers
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#### System
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- Power-on Reset (POR) and Brown-out detection (BOD)
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- Internal and external clock options
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- External Interrupt Controller (EIC)
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- 16 external interrupts
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- One non-maskable interrupt
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- Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
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#### High-Performance Peripherals
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- 32-channel Direct Memory Access Controller (DMAC)
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- Up to two SD/MMC Host Controller (SDHC)
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- Up to 50 MHz operation
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- 4-bit or 1-bit interface
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- Compatibility with SD and SDHC memory card specification version 3.01
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- Compatibility with SDIO specification version 3.0
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- Compliant with JDEC specification, MMC memory cards V4.51
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- One Quad I/O Serial Peripheral Interface (QSPI)
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- Dedicated AHB memory zone
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- One Ethernet MAC (SAM E53 and SAM E54)– 10/100 Mbps in MII and RMII with dedicated DMA
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- IEEE® 1588 Precision Time Protocol (PTP) support
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- IEEE 1588 Time Stamping Unit (TSU) support
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- IEEE802.3AZ energy efficiency support
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- Support for 802.1AS and 1588 precision clock synchronization protocol
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- Wake on LAN support
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- Up to two Controller Area Network (CAN) (that is., SAM E51 and SAM E54)
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- Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO 11898-1:2016)
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- One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
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- Embedded host and device function
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- Eight endpoints
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- On-chip transceiver with integrated serial resistor
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#### System Peripherals
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- Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination
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- Five Parallel Input/Output Controllers (PIO)
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- 32-channel Event System
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- Up to eight Serial Communication Interfaces (SERCOM), can be configured as USART/I2C/SPI
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- Up to eight 16-bit Timers/Counters (TC), can be configured as 8/16/32bit TC.
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- Two 24-bit Timer/Counters for Control (TCC), with extended functions
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- Up to Three 16-bit Timer/Counters for Control (TCC) with extended functions.
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- 32-bit Real Time Counter (RTC) with clock/calendar function
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- Up to 4 wake-up pins with tamper detection and debouncing filter
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- Watchdog Timer (WDT) with Window mode
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- CRC-32 generator
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- One two-channel Inter-IC Sound Interface (I2S)
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- Position Decoder (PDEC)
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- Frequency meter (FREQM)
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- Four Configurable Custom Logic (CCL)
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- Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) with up to 16 channels each:
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- Dual 12-bit, 1 MSPS output Digital-to-Analog Converter (DAC)
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- Two Analog Comparators (AC) with Window Compare function
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- One temperature sensor
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- Parallel Capture Controller (PCC)
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- Peripheral Touch Controller (PTC) - Capacitive Touch buttons, sliders, and wheels
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#### Cryptography
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- One Advanced Encryption System (AES) with 256-bit key length and up to 2 MB/s data rate
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- Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
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- Supports counter with CBC-MAC mode
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- Galois Counter Mode (GCM) - True Random Number Generator (TRNG)
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- Public Key Cryptography Controller (PUKCC) and associated Classical Public Key Cryptography Library (PUKCL)
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- RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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- Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA assisted
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#### I/O
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- Up to 99 programmable I/O pins
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#### Qualification
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- AEC-Q100 Grade 1 (-40°C to 125°C)
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#### Package Type
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- VQFN48, 48-lead VQFN, 7x7 mm, pitch 0.5 mm, I/O Pins up to 37
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- VQFN64, 64-lead VQFN, 9x9 mm, pitch 0.5 mm, I/O Pins up to 51
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- TQFP64, 64-lead TQFP, 10x10 mm, pitch 0.5 mm, I/O Pins up to 51
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- TQFP100, 100-lead TQFP, 14x14 mm, pitch 0.5 mm, I/O Pins up to 81
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- TQFP128, 128-lead TQFP, 14x14 mm, pitch 0.4 mm, I/O Pins up to 99
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- TFBGA120, 120-ball TFBGA, 8x8 mm, pitch 0.5 mm, I/O Pins up to 90
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#### Board info
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- [SAM E54 XPLAINED PRO](https://www.microchip.com/en-us/development-tool/DM320019-BNDL)
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@@ -0,0 +1,106 @@
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# SAME54P20A BSP 介绍
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[English](README.md)
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- MCU: ATSAME54P20A @120MHz, 1MB FLASH, 256KB RAM
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- E54: Cortex-M4F + 100M Ethernet + 2路CAN-FD
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- 管脚: G系列-48 pins, J系列-64 pins, N系列-100 pins, P系列-128 pins
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- Flash: 尾缀18=256KB, 19=512KB, 20=1024KB (size=2^n)
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- SRAM : 128KB(Flash 256KB), 192KB(Flash 512KB), 256KB(Flash 1MB)
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- 手册: <https://www.microchip.com/en-us/product/ATSAME54P20>
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#### 关键特性
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#### 内核
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- 32-bit Arm® Cortex®-M4 内核 + 单精度FPU + 4 KB 复用的指令和数据Cache，最大工作主频120 MHz, 带MPU, 403 CoreMark®@120 MHz, 支持 DSP指令集
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#### 内存
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- 1 MB/512 KB/256 KB in-system self-programmable Flash with:
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- Error Correction Code (ECC)
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- Dual bank with Read-While-Write (RWW) support
|
||||
- EEPROM hardware emulation
|
||||
- 128 KB, 192 KB, 256 KB SRAM main memory
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- 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
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- Up to 4 KB of Tightly Coupled Memory (TCM)
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- Up to 8 KB additional SRAM
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- Can be retained in backup mode
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- Eight 32-bit backup registers
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#### 系统特性
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- Power-on Reset (POR) and Brown-out detection (BOD)
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- Internal and external clock options
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- External Interrupt Controller (EIC)
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||||
- 16 external interrupts
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- One non-maskable interrupt
|
||||
- Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
|
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|
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#### 高性能外设
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- 32-channel Direct Memory Access Controller (DMAC)
|
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- Up to two SD/MMC Host Controller (SDHC)
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||||
- Up to 50 MHz operation
|
||||
- 4-bit or 1-bit interface
|
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- Compatibility with SD and SDHC memory card specification version 3.01
|
||||
- Compatibility with SDIO specification version 3.0
|
||||
- Compliant with JDEC specification, MMC memory cards V4.51
|
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- One Quad I/O Serial Peripheral Interface (QSPI)
|
||||
- Dedicated AHB memory zone
|
||||
- One Ethernet MAC (SAM E53 and SAM E54)– 10/100 Mbps in MII and RMII with dedicated DMA
|
||||
- IEEE® 1588 Precision Time Protocol (PTP) support
|
||||
- IEEE 1588 Time Stamping Unit (TSU) support
|
||||
- IEEE802.3AZ energy efficiency support
|
||||
- Support for 802.1AS and 1588 precision clock synchronization protocol
|
||||
- Wake on LAN support
|
||||
- Up to two Controller Area Network (CAN) (that is., SAM E51 and SAM E54)
|
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- Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO 11898-1:2016)
|
||||
- One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
|
||||
- Embedded host and device function
|
||||
- Eight endpoints
|
||||
- On-chip transceiver with integrated serial resistor
|
||||
|
||||
#### 系统外设
|
||||
- Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination
|
||||
- Five Parallel Input/Output Controllers (PIO)
|
||||
- 32-channel Event System
|
||||
- Up to eight Serial Communication Interfaces (SERCOM), can be configured as USART/I2C/SPI
|
||||
- Up to eight 16-bit Timers/Counters (TC), can be configured as 8/16/32bit TC.
|
||||
- Two 24-bit Timer/Counters for Control (TCC), with extended functions
|
||||
- Up to Three 16-bit Timer/Counters for Control (TCC) with extended functions.
|
||||
- 32-bit Real Time Counter (RTC) with clock/calendar function
|
||||
- Up to 4 wake-up pins with tamper detection and debouncing filter
|
||||
- Watchdog Timer (WDT) with Window mode
|
||||
- CRC-32 generator
|
||||
- One two-channel Inter-IC Sound Interface (I2S)
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- Position Decoder (PDEC)
|
||||
- Frequency meter (FREQM)
|
||||
- Four Configurable Custom Logic (CCL)
|
||||
- Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) with up to 16 channels each:
|
||||
- Dual 12-bit, 1 MSPS output Digital-to-Analog Converter (DAC)
|
||||
- Two Analog Comparators (AC) with Window Compare function
|
||||
- One temperature sensor
|
||||
- Parallel Capture Controller (PCC)
|
||||
- Peripheral Touch Controller (PTC) - Capacitive Touch buttons, sliders, and wheels
|
||||
|
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#### 加密功能
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- One Advanced Encryption System (AES) with 256-bit key length and up to 2 MB/s data rate
|
||||
- Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
|
||||
- Supports counter with CBC-MAC mode
|
||||
- Galois Counter Mode (GCM) - True Random Number Generator (TRNG)
|
||||
- Public Key Cryptography Controller (PUKCC) and associated Classical Public Key Cryptography Library (PUKCL)
|
||||
- RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
|
||||
- Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA assisted
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#### I/O管脚
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- 最多提供99个用户可编程I/O管脚
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#### 汽车应用
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- AEC-Q100 Grade 1 (-40°C to 125°C)
|
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|
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#### 封装
|
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- VQFN48, 48-lead VQFN, 7x7 mm, pitch 0.5 mm, I/O Pins up to 37
|
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- VQFN64, 64-lead VQFN, 9x9 mm, pitch 0.5 mm, I/O Pins up to 51
|
||||
- TQFP64, 64-lead TQFP, 10x10 mm, pitch 0.5 mm, I/O Pins up to 51
|
||||
- TQFP100, 100-lead TQFP, 14x14 mm, pitch 0.5 mm, I/O Pins up to 81
|
||||
- TQFP128, 128-lead TQFP, 14x14 mm, pitch 0.4 mm, I/O Pins up to 99
|
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- TFBGA120, 120-ball TFBGA, 8x8 mm, pitch 0.5 mm, I/O Pins up to 90
|
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|
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#### 官方开发板信息
|
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- [SAM E54 XPLAINED PRO](https://www.microchip.com/en-us/development-tool/DM320019-BNDL)
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@@ -0,0 +1,14 @@
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# for module compiling
|
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
|
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|
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for d in list:
|
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path = os.path.join(cwd, d)
|
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if os.path.isfile(os.path.join(path, 'SConscript')):
|
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,41 @@
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import os
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import sys
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import rtconfig
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|
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if os.getenv('RTT_ROOT'):
|
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
|
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
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except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
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TARGET = 'rt-thread-' + rtconfig.DEVICE_PART + '.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
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AR = rtconfig.AR, ARFLAGS = '-rc',
|
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread-'+ rtconfig.DEVICE_PART + '.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,10 @@
|
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import rtconfig
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,333 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
#include <shell.h>
|
||||
#endif
|
||||
|
||||
#include "atmel_start.h"
|
||||
#include "driver_init.h"
|
||||
#include "utils.h"
|
||||
|
||||
#include "can_demo.h"
|
||||
|
||||
#ifdef SAM_CAN_EXAMPLE
|
||||
|
||||
static volatile enum can_async_interrupt_type can_errors;
|
||||
static rt_sem_t can_txdone;
|
||||
static rt_sem_t can_rxdone;
|
||||
static rt_uint8_t can_stack[ 512 ];
|
||||
static struct rt_thread can_thread;
|
||||
|
||||
/**
|
||||
* @brief Callback function and should be invoked after call can_async_write.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* @param descr is CAN device description.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
|
||||
static void can_tx_callback(struct can_async_descriptor *const descr)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
rt_interrupt_enter();
|
||||
result = rt_sem_release(can_txdone);
|
||||
if (RT_EOK != result)
|
||||
{
|
||||
#ifndef RT_USING_FINSH
|
||||
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
|
||||
#endif
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Callback function and should be invoked after remote device send.
|
||||
*
|
||||
* @note This callback function will be called in CAN interrupt function
|
||||
*
|
||||
* @param descr is CAN device description.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
|
||||
static void can_rx_callback(struct can_async_descriptor *const descr)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
rt_interrupt_enter();
|
||||
result = rt_sem_release(can_rxdone);
|
||||
if (RT_EOK != result)
|
||||
{
|
||||
#ifndef RT_USING_FINSH
|
||||
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
|
||||
#endif
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Callback function and should be invoked after CAN device IRQ handler detects errors happened.
|
||||
*
|
||||
* @note This callback function will be called in CAN interrupt function
|
||||
*
|
||||
* @param descr is CAN device description.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
|
||||
static void can_err_callback(struct can_async_descriptor *const descr,
|
||||
enum can_async_interrupt_type type)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
if (type == CAN_IRQ_EW)
|
||||
{
|
||||
/* Error warning, Error counter has reached the error warning limit of 96,
|
||||
* An error count value greater than about 96 indicates a heavily disturbed
|
||||
* bus. It may be of advantage to provide means to test for this condition.
|
||||
*/
|
||||
}
|
||||
else if (type == CAN_IRQ_EA)
|
||||
{
|
||||
/* Error Active State, The CAN node normally take part in bus communication
|
||||
* and sends an ACTIVE ERROR FLAG when an error has been detected.
|
||||
*/
|
||||
}
|
||||
else if (type == CAN_IRQ_EP)
|
||||
{
|
||||
/* Error Passive State, The Can node goes into error passive state if at least
|
||||
* one of its error counters is greater than 127. It still takes part in bus
|
||||
* activities, but it sends a passive error frame only, on errors.
|
||||
*/
|
||||
}
|
||||
else if (type == CAN_IRQ_BO)
|
||||
{
|
||||
/* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is
|
||||
* greater than or equal to 256.
|
||||
*/
|
||||
|
||||
/* Suspend CAN task and re-initialize CAN module. */
|
||||
can_errors = type;
|
||||
rt_interrupt_enter();
|
||||
result = rt_sem_release(can_rxdone);
|
||||
if (RT_EOK != result)
|
||||
{
|
||||
#ifndef RT_USING_FINSH
|
||||
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
|
||||
#endif
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
else if (type == CAN_IRQ_DO)
|
||||
{
|
||||
/* Data Overrun in receive queue. A message was lost because the messages in
|
||||
* the queue was not reading and releasing fast enough. There is not enough
|
||||
* space for a new message in receive queue.
|
||||
*/
|
||||
|
||||
/* Suggest to delete CAN task and re-initialize it. */
|
||||
can_errors = type;
|
||||
rt_interrupt_enter();
|
||||
result = rt_sem_release(can_rxdone);
|
||||
if (RT_EOK != result)
|
||||
{
|
||||
#ifndef RT_USING_FINSH
|
||||
rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
|
||||
#endif
|
||||
}
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Initialize CAN module before task run.
|
||||
*
|
||||
* @note This function will set CAN Tx/Rx callback function and filters.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
|
||||
static inline void can_demo_init(void)
|
||||
{
|
||||
struct can_filter filter;
|
||||
|
||||
/**
|
||||
* CAN_Node0_tx_callback callback should be invoked after call
|
||||
* can_async_write, and remote device should receive message with ID=0x45A
|
||||
*/
|
||||
can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback);
|
||||
|
||||
/**
|
||||
* CAN_0_rx_callback callback should be invoked after call
|
||||
* can_async_set_filter and remote device send CAN Message with the same
|
||||
* content as the filter.
|
||||
*/
|
||||
can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback);
|
||||
|
||||
|
||||
/* Should set at least one CAN standard & message filter before enable it. */
|
||||
|
||||
filter.id = 0x469;
|
||||
filter.mask = 0;
|
||||
can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter);
|
||||
|
||||
/* If set second standard message filter, should increase filter index
|
||||
* and filter algorithm
|
||||
* For example: index should set to 1, otherwise it will replace filter 0.
|
||||
* can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */
|
||||
|
||||
filter.id = 0x10000096;
|
||||
filter.mask = 0;
|
||||
can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter);
|
||||
|
||||
can_async_enable(&CAN_0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CAN task.
|
||||
*
|
||||
* @note This task will waiting for CAN RX semaphore and then process input.
|
||||
*
|
||||
* @param parameter - task input parameter.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
|
||||
static void can_thread_entry(void* parameter)
|
||||
{
|
||||
int32_t ret;
|
||||
rt_err_t result;
|
||||
uint8_t data[64];
|
||||
uint32_t count=0;
|
||||
struct can_message msg;
|
||||
|
||||
while (1)
|
||||
{
|
||||
#ifndef RT_USING_FINSH
|
||||
rt_kprintf("can task run count : %d\r\n",count);
|
||||
#endif
|
||||
count++;
|
||||
|
||||
result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER);
|
||||
if (RT_EOK != result)
|
||||
continue;
|
||||
|
||||
do
|
||||
{
|
||||
/* Process the incoming packet. */
|
||||
ret = can_async_read(&CAN_0, &msg);
|
||||
if (ret == ERR_NONE)
|
||||
{
|
||||
#ifndef RT_USING_FINSH
|
||||
rt_kprintf("CAN RX Message is % frame\r\n",
|
||||
msg.type == CAN_TYPE_DATA ? "data" : "remote");
|
||||
rt_kprintf("CAN RX Message is % frame\r\n",
|
||||
msg.type == CAN_FMT_STDID ? "Standard" : "Extended");
|
||||
rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len);
|
||||
rt_kprintf("CAN RX Message content: ");
|
||||
for (uint8_t i = 0; i < msg.len; i++)
|
||||
rt_kprintf("0x%02X ", data[i]);
|
||||
rt_kprintf("\r\n");
|
||||
#endif
|
||||
}
|
||||
} while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */
|
||||
|
||||
/* CAN task got CAN error message, handler CAN Error Status */
|
||||
if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO))
|
||||
{
|
||||
can_async_init(&CAN_0, CAN1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Call this function will to send a CAN message.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* @param msg - message to be sent, timeouts - wait timeouts for Tx completion.
|
||||
*
|
||||
* @return RT_OK or RT_ERROR.
|
||||
*/
|
||||
|
||||
rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
if (RT_NULL == msg)
|
||||
{
|
||||
rt_kprintf("can_send_message input message error\r\n");
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
can_async_write(&CAN_0, msg);
|
||||
result = rt_sem_take(can_rxdone, timeouts);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Call this function will create a CAN task.
|
||||
*
|
||||
* @note Should create Tx/Rx semaphore before run task.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return RT_OK or -RT_ERROR.
|
||||
*/
|
||||
|
||||
rt_err_t can_demo_run(void)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO);
|
||||
if (RT_NULL == can_rxdone)
|
||||
{
|
||||
rt_kprintf("can_rx semaphore create failed\r\n");
|
||||
return (-RT_ERROR);
|
||||
}
|
||||
|
||||
can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO);
|
||||
if (RT_NULL == can_txdone)
|
||||
{
|
||||
rt_kprintf("can_tx semaphore create failed\r\n");
|
||||
return (-RT_ERROR);
|
||||
}
|
||||
|
||||
can_demo_init();
|
||||
|
||||
/* initialize CAN thread */
|
||||
result = rt_thread_init(&can_thread,
|
||||
"can",
|
||||
can_thread_entry,
|
||||
RT_NULL,
|
||||
(rt_uint8_t*)&can_stack[0],
|
||||
sizeof(can_stack),
|
||||
RT_THREAD_PRIORITY_MAX/3,
|
||||
5);
|
||||
if (result == RT_EOK)
|
||||
{
|
||||
rt_thread_startup(&can_thread);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#ifndef __APPLICATION_CAN_H_
|
||||
#define __APPLICATION_CAN_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @brief External function definitions
|
||||
*
|
||||
*/
|
||||
rt_err_t can_demo_run(void);
|
||||
|
||||
rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts);
|
||||
|
||||
#endif // __APPLICATION_CAN_H_
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
#include <shell.h>
|
||||
#endif
|
||||
|
||||
#include "atmel_start.h"
|
||||
#include <hal_gpio.h>
|
||||
|
||||
#ifdef SAM_CAN_EXAMPLE
|
||||
#include "can_demo.h"
|
||||
#endif
|
||||
|
||||
static rt_uint8_t led_stack[ 512 ];
|
||||
static struct rt_thread led_thread;
|
||||
|
||||
static void led_thread_entry(void* parameter)
|
||||
{
|
||||
unsigned int count=0;
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* toggle led */
|
||||
#ifndef RT_USING_FINSH
|
||||
rt_kprintf("led toggle, count : %d\r\n",count);
|
||||
#endif
|
||||
count++;
|
||||
gpio_toggle_pin_level(LED0);
|
||||
rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
|
||||
}
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_err_t result;
|
||||
|
||||
/* initialize led thread */
|
||||
result = rt_thread_init(&led_thread,
|
||||
"led",
|
||||
led_thread_entry,
|
||||
RT_NULL,
|
||||
(rt_uint8_t*)&led_stack[0],
|
||||
sizeof(led_stack),
|
||||
RT_THREAD_PRIORITY_MAX/3,
|
||||
5);
|
||||
if (result == RT_EOK)
|
||||
{
|
||||
rt_thread_startup(&led_thread);
|
||||
}
|
||||
|
||||
#ifdef SAM_CAN_EXAMPLE
|
||||
can_demo_run();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,52 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
choice
|
||||
prompt "select chip type"
|
||||
default SOC_SAME54P20
|
||||
|
||||
config SOC_SAME54P20
|
||||
bool "SOC_SAME54P20"
|
||||
help
|
||||
Refer to SAME54 DataSheet
|
||||
|
||||
config SOC_SAME54N20
|
||||
bool "SOC_SAME54N20"
|
||||
help
|
||||
Refer to SAME54 DataSheet
|
||||
|
||||
config SOC_SAME53J20
|
||||
bool "SOC_SAME53J20"
|
||||
help
|
||||
Refer to SAME54 DataSheet
|
||||
|
||||
endchoice
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
depends on SOC_SAME54P20 || SOC_SAME54N20
|
||||
|
||||
config SAME5X_CAN0
|
||||
bool "Enable CAN0"
|
||||
default false
|
||||
|
||||
config SAME5X_ADC0
|
||||
bool "Enable ADC0"
|
||||
default false
|
||||
endmenu
|
||||
|
||||
menu "Application Demo Config"
|
||||
config SAM_CAN_EXAMPLE
|
||||
bool "Enable SAM CAN Example"
|
||||
depends on SAME5X_CAN0
|
||||
default true
|
||||
help
|
||||
Add CAN example task to project
|
||||
|
||||
config SAM_ADC_EXAMPLE
|
||||
bool "Enable SAM ADC Example"
|
||||
depends on SAME5X_ADC0
|
||||
default true
|
||||
help
|
||||
Add ADC example task to project
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,17 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
#remove other no use files
|
||||
#SrcRemove(src, '*.c')
|
||||
|
||||
# You can select chips from the list above
|
||||
CPPDEFINES = ['SAME54xxx']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include <atmel_start.h>
|
||||
#include "peripheral_clk_config.h"
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
extern int rt_hw_uart_init(void);
|
||||
#endif
|
||||
|
||||
static struct io_descriptor* g_stdio;
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
io_write(g_stdio, (uint8_t *)str, strlen(str));
|
||||
}
|
||||
RTM_EXPORT(rt_hw_console_output);
|
||||
|
||||
static inline void hw_board_init_usart(void)
|
||||
{
|
||||
usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
|
||||
usart_sync_enable(&TARGET_IO);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial SAME54 board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* Initializes MCU, drivers and middleware */
|
||||
atmel_start_init();
|
||||
|
||||
/* enable USART stdout module */
|
||||
hw_board_init_usart();
|
||||
|
||||
/* UART driver initialization is open by default */
|
||||
#ifdef RT_USING_SERIAL
|
||||
rt_hw_uart_init();
|
||||
#endif
|
||||
|
||||
/* init systick */
|
||||
SysTick_Config(CONF_CPU_FREQUENCY / RT_TICK_PER_SECOND);
|
||||
|
||||
/* set pend exception priority */
|
||||
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)HEAP_END);
|
||||
#elif __ICCARM__
|
||||
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
|
||||
#else
|
||||
/* init memory system */
|
||||
rt_system_heap_init((void*)&__bss_end, (void*)HEAP_END);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Set the shell console output device */
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
// <o> Internal SRAM memory size[Kbytes] <128-256>
|
||||
// <i>Default: 256
|
||||
#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAME53J18A__) || defined(__ATSAME53J18A__)
|
||||
#define SAME5x_SRAM_SIZE 128
|
||||
#elif defined(__SAME53J19A__) || defined(__ATSAME53J19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAME53J20A__) || defined(__ATSAME53J20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAME53N19A__) || defined(__ATSAME53N19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAME53N20A__) || defined(__ATSAME53N20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAME51J18A__) || defined(__ATSAME51J18A__)
|
||||
#define SAME5x_SRAM_SIZE 128
|
||||
#elif defined(__SAME51J19A__) || defined(__ATSAME51J19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAME51J20A__) || defined(__ATSAME51J20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAME51N19A__) || defined(__ATSAME51N19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAME51N20A__) || defined(__ATSAME51N20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__)
|
||||
#define SAME5x_SRAM_SIZE 128
|
||||
#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__)
|
||||
#define SAME5x_SRAM_SIZE 192
|
||||
#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__)
|
||||
#define SAME5x_SRAM_SIZE 256
|
||||
#else
|
||||
#error Board does not support the specified device.
|
||||
#endif
|
||||
|
||||
#define SAME5x_SRAM_END (0x20000000 + SAME5x_SRAM_SIZE * 1024)
|
||||
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_begin("HEAP"))
|
||||
#define HEAP_END (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#define HEAP_END SAME5x_SRAM_END
|
||||
#endif
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,199 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <atmel_start.h>
|
||||
|
||||
/* SAM MCU serial device */
|
||||
static struct rt_serial_device sam_serial;
|
||||
|
||||
/**
|
||||
* @brief Configure serial port
|
||||
*
|
||||
* This function will configure UART baudrate, parity and so on.
|
||||
*
|
||||
* @return RT_EOK.
|
||||
*/
|
||||
static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
usart_sync_disable(desc);
|
||||
|
||||
/* Set baudrate */
|
||||
usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
|
||||
|
||||
/* Set stop bit */
|
||||
if (cfg->stop_bits == STOP_BITS_1)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
|
||||
else if (cfg->stop_bits == STOP_BITS_2)
|
||||
usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
|
||||
|
||||
if (cfg->bit_order == BIT_ORDER_LSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
|
||||
else if (cfg->bit_order == BIT_ORDER_MSB)
|
||||
usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
|
||||
|
||||
/* Set character size */
|
||||
switch (cfg->data_bits)
|
||||
{
|
||||
case DATA_BITS_5:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
|
||||
break;
|
||||
case DATA_BITS_6:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
|
||||
break;
|
||||
case DATA_BITS_7:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
|
||||
break;
|
||||
case DATA_BITS_8:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
|
||||
break;
|
||||
case DATA_BITS_9:
|
||||
usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg->parity == PARITY_NONE)
|
||||
usart_sync_set_parity(desc, USART_PARITY_NONE);
|
||||
else if (cfg->parity == PARITY_ODD)
|
||||
usart_sync_set_parity(desc, USART_PARITY_ODD);
|
||||
else if (cfg->parity == PARITY_EVEN)
|
||||
usart_sync_set_parity(desc, USART_PARITY_EVEN);
|
||||
|
||||
usart_sync_enable(desc);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Control serial port
|
||||
*
|
||||
* This function provide UART enable/disable control.
|
||||
*
|
||||
* @return RT_EOK.
|
||||
*/
|
||||
static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
/* disable interrupt */
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
usart_sync_disable(desc);
|
||||
break;
|
||||
/* enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
usart_sync_enable(desc);
|
||||
break;
|
||||
/* UART config */
|
||||
case RT_DEVICE_CTRL_CONFIG :
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Serial sends a char
|
||||
*
|
||||
* This function will send a char to the UART
|
||||
*
|
||||
* @return 1.
|
||||
*/
|
||||
static int serial_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
io_write(&desc->io, (const uint8_t *)&c, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Serial gets a char
|
||||
*
|
||||
* This function will get a char from the UART
|
||||
*
|
||||
* @return received char character or -1 if no char received.
|
||||
*/
|
||||
static int serial_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
char c;
|
||||
int ch;
|
||||
struct usart_sync_descriptor* desc;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
desc = (struct usart_sync_descriptor *)serial->parent.user_data;
|
||||
|
||||
RT_ASSERT(desc != RT_NULL);
|
||||
|
||||
ch = -1;
|
||||
if (usart_sync_is_rx_not_empty(desc))
|
||||
{
|
||||
io_read(&desc->io, (uint8_t *)&c, 1);;
|
||||
ch = c & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops sam_serial_ops =
|
||||
{
|
||||
serial_configure,
|
||||
serial_control,
|
||||
serial_putc,
|
||||
serial_getc,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Initialize the UART
|
||||
*
|
||||
* This function initialize the UART
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
sam_serial.ops = &sam_serial_ops;
|
||||
sam_serial.config = config;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
sam_serial.serial_rx = RT_NULL;
|
||||
rt_hw_serial_register(&sam_serial, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c)
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Email Notes
|
||||
* 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_SERIAL_H_
|
||||
#define __BOARD_SERIAL_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @brief External function definitions
|
||||
*
|
||||
*/
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#endif // __BOARD_SERIAL_H_
|
||||
@@ -0,0 +1,6 @@
|
||||
<environment>
|
||||
<configurations/>
|
||||
<device-packs>
|
||||
<device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/>
|
||||
</device-packs>
|
||||
</environment>
|
||||
@@ -0,0 +1,212 @@
|
||||
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
|
||||
<vendor>Atmel</vendor>
|
||||
<name>SAME54 LED switcher</name>
|
||||
<description>Project generated by Atmel Start</description>
|
||||
<url>http://start.atmel.com/</url>
|
||||
<releases>
|
||||
<release version="1.0.1">Initial version</release>
|
||||
</releases>
|
||||
<taxonomy>
|
||||
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
|
||||
</taxonomy>
|
||||
<generators>
|
||||
<generator id="AtmelStart">
|
||||
<description>Atmel Start</description>
|
||||
<select Dname="ATSAME54P20A" Dvendor="Atmel:3"/>
|
||||
<command>http://start.atmel.com/</command>
|
||||
<files>
|
||||
<file category="generator" name="atmel_start_config.atstart"/>
|
||||
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
|
||||
</files>
|
||||
</generator>
|
||||
</generators>
|
||||
<conditions>
|
||||
<condition id="CMSIS Device Startup">
|
||||
<description>Dependency on CMSIS core and Device Startup components</description>
|
||||
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
|
||||
<require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/>
|
||||
</condition>
|
||||
<condition id="ARMCC, GCC, IAR">
|
||||
<require Dname="ATSAME54P20A"/>
|
||||
<accept Tcompiler="ARMCC"/>
|
||||
<accept Tcompiler="GCC"/>
|
||||
<accept Tcompiler="IAR"/>
|
||||
</condition>
|
||||
<condition id="GCC">
|
||||
<require Dname="ATSAME54P20A"/>
|
||||
<accept Tcompiler="GCC"/>
|
||||
</condition>
|
||||
</conditions>
|
||||
<components generator="AtmelStart">
|
||||
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
|
||||
<description>Atmel Start Framework</description>
|
||||
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
|
||||
<files>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/aes_sync.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_aes_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_aes.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_aes_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_cmcc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_aes_sync.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_cache.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_can_async.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
|
||||
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_cmcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gmac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_i2s_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_icm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pdec_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_qspi_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ramecc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdhc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
|
||||
<file category="doc" condition="ARMCC, GCC, IAR" name="documentation/aes_demo.rst"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/aes/hpl_aes.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/cmcc/hpl_cmcc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m4.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
|
||||
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
|
||||
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_aes_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_can_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
|
||||
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/aes"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/can"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/ramecc"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
|
||||
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
|
||||
</files>
|
||||
</component>
|
||||
</components>
|
||||
</package>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,266 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,270 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,333 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@@ -0,0 +1,196 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
||||
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
|
||||
<title>Overview</title>
|
||||
<title>CMSIS-Core (Cortex-M): Overview</title>
|
||||
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
||||
<link href="cmsis.css" rel="stylesheet" type="text/css" />
|
||||
<script type="text/javascript" src="jquery.js"></script>
|
||||
<script type="text/javascript" src="dynsections.js"></script>
|
||||
<script type="text/javascript" src="printComponentTabs.js"></script>
|
||||
<link href="navtree.css" rel="stylesheet" type="text/css"/>
|
||||
<script type="text/javascript" src="resize.js"></script>
|
||||
<script type="text/javascript" src="navtree.js"></script>
|
||||
<script type="text/javascript">
|
||||
$(document).ready(initResizable);
|
||||
$(window).load(resizeHeight);
|
||||
</script>
|
||||
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|
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<script type="text/javascript" src="search/search.js"></script>
|
||||
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|
||||
$(document).ready(function() { searchBox.OnSelectItem(0); });
|
||||
</script>
|
||||
</head>
|
||||
<body>
|
||||
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
|
||||
<div id="titlearea">
|
||||
<table cellspacing="0" cellpadding="0">
|
||||
<tbody>
|
||||
<tr style="height: 46px;">
|
||||
<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
|
||||
<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-Core (Cortex-M)
|
||||
 <span id="projectnumber">Version 5.1.2</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<!-- end header part -->
|
||||
<div id="CMSISnav" class="tabs1">
|
||||
<ul class="tablist">
|
||||
<script type="text/javascript">
|
||||
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|
||||
writeComponentTabs.call(this);
|
||||
//-->
|
||||
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|
||||
</ul>
|
||||
</div>
|
||||
<!-- Generated by Doxygen 1.8.6 -->
|
||||
<script type="text/javascript">
|
||||
var searchBox = new SearchBox("searchBox", "search",false,'Search');
|
||||
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||||
<div id="navrow1" class="tabs">
|
||||
<ul class="tablist">
|
||||
<li class="current"><a href="index.html"><span>Main Page</span></a></li>
|
||||
<li><a href="pages.html"><span>Usage and Description</span></a></li>
|
||||
<li><a href="modules.html"><span>Reference</span></a></li>
|
||||
<li>
|
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<img id="MSearchSelect" src="search/mag_sel.png"
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||||
onmouseover="return searchBox.OnSearchSelectShow()"
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||||
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alt=""/>
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<input type="text" id="MSearchField" value="Search" accesskey="S"
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onfocus="searchBox.OnSearchFieldFocus(true)"
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onblur="searchBox.OnSearchFieldFocus(false)"
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</span><span class="right">
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||||
<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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|
||||
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|
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</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div><!-- top -->
|
||||
<div id="side-nav" class="ui-resizable side-nav-resizable">
|
||||
<div id="nav-tree">
|
||||
<div id="nav-tree-contents">
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</div>
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</div>
|
||||
<div id="splitbar" style="-moz-user-select:none;"
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class="ui-resizable-handle">
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</div>
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||||
<script type="text/javascript">
|
||||
$(document).ready(function(){initNavTree('index.html','');});
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||||
</script>
|
||||
<div id="doc-content">
|
||||
<!-- window showing the filter options -->
|
||||
<div id="MSearchSelectWindow"
|
||||
onmouseover="return searchBox.OnSearchSelectShow()"
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||||
onmouseout="return searchBox.OnSearchSelectHide()"
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onkeydown="return searchBox.OnSearchSelectKey(event)">
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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<!-- iframe showing the search results (closed by default) -->
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<div id="MSearchResultsWindow">
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<iframe src="javascript:void(0)" frameborder="0"
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name="MSearchResults" id="MSearchResults">
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</iframe>
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</div>
|
||||
|
||||
<div class="header">
|
||||
<div class="headertitle">
|
||||
<div class="title">Overview </div> </div>
|
||||
</div><!--header-->
|
||||
<div class="contents">
|
||||
<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
|
||||
<ul>
|
||||
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
|
||||
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
|
||||
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
|
||||
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
|
||||
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
|
||||
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
|
||||
</ul>
|
||||
<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
|
||||
<ul>
|
||||
<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
|
||||
<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone® for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li>
|
||||
<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
|
||||
<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
|
||||
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||
</ul>
|
||||
<hr/>
|
||||
<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2>
|
||||
<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p>
|
||||
<table class="doxtable">
|
||||
<tr>
|
||||
<th>File/Folder </th><th>Content </th></tr>
|
||||
<tr>
|
||||
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
|
||||
<tr>
|
||||
<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
|
||||
<tr>
|
||||
<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr>
|
||||
<tr>
|
||||
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr>
|
||||
</table>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="ref_v6-v8M"></a>
|
||||
Processor Support</h1>
|
||||
<p>CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.</p>
|
||||
<h2><a class="anchor" id="ref_man_sec"></a>
|
||||
Cortex-M Reference Manuals</h2>
|
||||
<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
|
||||
<ul>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
|
||||
</ul>
|
||||
<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p>
|
||||
<ul>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li>
|
||||
</ul>
|
||||
<h2><a class="anchor" id="ARMv8M"></a>
|
||||
Armv8-M Architecture</h2>
|
||||
<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.</p>
|
||||
<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="tested_tools_sec"></a>
|
||||
Tested and Verified Toolchains</h1>
|
||||
<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p>
|
||||
<ul>
|
||||
<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)</li>
|
||||
<li>Arm: Arm Compiler 6.9</li>
|
||||
<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)</li>
|
||||
<li>GNU: GNU Tools for Arm Embedded 6.3.1 20170620</li>
|
||||
<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li>
|
||||
</ul>
|
||||
<hr/>
|
||||
</div></div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
||||
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved.
|
||||
<!--
|
||||
<a href="http://www.doxygen.org/index.html">
|
||||
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6
|
||||
-->
|
||||
</li>
|
||||
</ul>
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,59 @@
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
#var defined
|
||||
CPPDEFINES = []
|
||||
|
||||
#common lib define
|
||||
CPPDEFINES += [rtconfig.DEVICE_TYPE]
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Glob('hal/src/*.c')
|
||||
src += Glob('hal/utils/src/*.c')
|
||||
src += Glob('hpl/aes/*.c')
|
||||
src += Glob('hpl/can/*.c')
|
||||
src += Glob('hpl/cmcc/*.c')
|
||||
src += Glob('hpl/core/*.c')
|
||||
src += Glob('hpl/dmac/*.c')
|
||||
src += Glob('hpl/gclk/*.c')
|
||||
src += Glob('hpl/mclk/*.c')
|
||||
src += Glob('hpl/osc32kctrl/*.c')
|
||||
src += Glob('hpl/oscctrl/*.c')
|
||||
src += Glob('hpl/pm/*.c')
|
||||
src += Glob('hpl/port/*.c')
|
||||
src += Glob('hpl/ramecc/*.c')
|
||||
src += Glob('hpl/sercom/*.c')
|
||||
src += [cwd + '/atmel_start.c']
|
||||
src += [cwd + '/driver_init.c']
|
||||
|
||||
#add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += [cwd + '/gcc/system_same54.c']
|
||||
src += [cwd + '/gcc/gcc/startup_same54.c']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += [cwd + '/armcc/arm_addon/armcc/' + 'system_same54.c']
|
||||
src += [cwd + '/armcc/arm_addon/armcc/arm/' + 'startup_same54.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [cwd + '/iar/' + 'system_same54.c']
|
||||
src += [cwd + '/iar/iar/' + 'startup_same54.c']
|
||||
|
||||
path = [
|
||||
cwd,
|
||||
cwd + '/CMSIS/Core/Include',
|
||||
cwd + '/config',
|
||||
cwd + '/hal/include',
|
||||
cwd + '/hal/utils/include',
|
||||
cwd + '/hpl/can',
|
||||
cwd + '/hpl/core',
|
||||
cwd + '/hpl/gclk',
|
||||
cwd + '/hpl/pm',
|
||||
cwd + '/hpl/port',
|
||||
cwd + '/hri',
|
||||
cwd + '/include',]
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,225 @@
|
||||
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
ifdef SystemRoot
|
||||
SHELL = cmd.exe
|
||||
MK_DIR = mkdir
|
||||
else
|
||||
ifeq ($(shell uname), Linux)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
|
||||
ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
|
||||
MK_DIR = mkdir -p
|
||||
endif
|
||||
endif
|
||||
|
||||
# List the subdirectories for creating object files
|
||||
SUB_DIRS += \
|
||||
\
|
||||
hpl/pm \
|
||||
hpl/osc32kctrl \
|
||||
hpl/can \
|
||||
hpl/ramecc \
|
||||
hpl/dmac \
|
||||
hal/src \
|
||||
hpl/mclk \
|
||||
hpl/aes \
|
||||
hpl/sercom \
|
||||
examples \
|
||||
hpl/gclk \
|
||||
hpl/oscctrl \
|
||||
hal/utils/src \
|
||||
armcc/arm_addon/armcc/arm \
|
||||
armcc/arm_addon/armcc \
|
||||
hpl/core \
|
||||
hpl/cmcc
|
||||
|
||||
# List the object files
|
||||
OBJS += \
|
||||
hal/src/hal_io.o \
|
||||
hal/src/hal_can_async.o \
|
||||
armcc/arm_addon/armcc/system_same54.o \
|
||||
hpl/can/hpl_can.o \
|
||||
hpl/core/hpl_core_m4.o \
|
||||
hal/src/hal_cache.o \
|
||||
hpl/aes/hpl_aes.o \
|
||||
hal/src/hal_delay.o \
|
||||
hpl/pm/hpl_pm.o \
|
||||
hpl/core/hpl_init.o \
|
||||
hpl/gclk/hpl_gclk.o \
|
||||
hal/utils/src/utils_list.o \
|
||||
hal/utils/src/utils_assert.o \
|
||||
hpl/dmac/hpl_dmac.o \
|
||||
hpl/oscctrl/hpl_oscctrl.o \
|
||||
hal/src/hal_usart_sync.o \
|
||||
hpl/mclk/hpl_mclk.o \
|
||||
hpl/ramecc/hpl_ramecc.o \
|
||||
hal/src/hal_init.o \
|
||||
main.o \
|
||||
hpl/osc32kctrl/hpl_osc32kctrl.o \
|
||||
examples/driver_examples.o \
|
||||
driver_init.o \
|
||||
hpl/sercom/hpl_sercom.o \
|
||||
hal/src/hal_gpio.o \
|
||||
hal/utils/src/utils_event.o \
|
||||
hal/src/hal_sleep.o \
|
||||
hal/src/hal_aes_sync.o \
|
||||
hpl/cmcc/hpl_cmcc.o \
|
||||
atmel_start.o \
|
||||
hal/src/hal_atomic.o \
|
||||
armcc/arm_addon/armcc/arm/startup_same54.o
|
||||
|
||||
OBJS_AS_ARGS += \
|
||||
"hal/src/hal_io.o" \
|
||||
"hal/src/hal_can_async.o" \
|
||||
"armcc/arm_addon/armcc/system_same54.o" \
|
||||
"hpl/can/hpl_can.o" \
|
||||
"hpl/core/hpl_core_m4.o" \
|
||||
"hal/src/hal_cache.o" \
|
||||
"hpl/aes/hpl_aes.o" \
|
||||
"hal/src/hal_delay.o" \
|
||||
"hpl/pm/hpl_pm.o" \
|
||||
"hpl/core/hpl_init.o" \
|
||||
"hpl/gclk/hpl_gclk.o" \
|
||||
"hal/utils/src/utils_list.o" \
|
||||
"hal/utils/src/utils_assert.o" \
|
||||
"hpl/dmac/hpl_dmac.o" \
|
||||
"hpl/oscctrl/hpl_oscctrl.o" \
|
||||
"hal/src/hal_usart_sync.o" \
|
||||
"hpl/mclk/hpl_mclk.o" \
|
||||
"hpl/ramecc/hpl_ramecc.o" \
|
||||
"hal/src/hal_init.o" \
|
||||
"main.o" \
|
||||
"hpl/osc32kctrl/hpl_osc32kctrl.o" \
|
||||
"examples/driver_examples.o" \
|
||||
"driver_init.o" \
|
||||
"hpl/sercom/hpl_sercom.o" \
|
||||
"hal/src/hal_gpio.o" \
|
||||
"hal/utils/src/utils_event.o" \
|
||||
"hal/src/hal_sleep.o" \
|
||||
"hal/src/hal_aes_sync.o" \
|
||||
"hpl/cmcc/hpl_cmcc.o" \
|
||||
"atmel_start.o" \
|
||||
"hal/src/hal_atomic.o" \
|
||||
"armcc/arm_addon/armcc/arm/startup_same54.o"
|
||||
|
||||
# List the dependency files
|
||||
DEPS := $(OBJS:%.o=%.d)
|
||||
|
||||
DEPS_AS_ARGS += \
|
||||
"hal/utils/src/utils_event.d" \
|
||||
"hal/src/hal_io.d" \
|
||||
"armcc/arm_addon/armcc/system_same54.d" \
|
||||
"hal/src/hal_can_async.d" \
|
||||
"hpl/core/hpl_core_m4.d" \
|
||||
"hpl/can/hpl_can.d" \
|
||||
"hpl/aes/hpl_aes.d" \
|
||||
"hal/utils/src/utils_list.d" \
|
||||
"hpl/cmcc/hpl_cmcc.d" \
|
||||
"hpl/dmac/hpl_dmac.d" \
|
||||
"hal/utils/src/utils_assert.d" \
|
||||
"hal/src/hal_delay.d" \
|
||||
"hpl/core/hpl_init.d" \
|
||||
"hpl/pm/hpl_pm.d" \
|
||||
"hpl/ramecc/hpl_ramecc.d" \
|
||||
"hpl/gclk/hpl_gclk.d" \
|
||||
"hal/src/hal_init.d" \
|
||||
"hal/src/hal_usart_sync.d" \
|
||||
"hpl/mclk/hpl_mclk.d" \
|
||||
"driver_init.d" \
|
||||
"hpl/osc32kctrl/hpl_osc32kctrl.d" \
|
||||
"hal/src/hal_cache.d" \
|
||||
"main.d" \
|
||||
"examples/driver_examples.d" \
|
||||
"hal/src/hal_aes_sync.d" \
|
||||
"hal/src/hal_sleep.d" \
|
||||
"hpl/sercom/hpl_sercom.d" \
|
||||
"hal/src/hal_gpio.d" \
|
||||
"hal/src/hal_atomic.d" \
|
||||
"hpl/oscctrl/hpl_oscctrl.d" \
|
||||
"armcc/arm_addon/armcc/arm/startup_same54.d" \
|
||||
"atmel_start.d"
|
||||
|
||||
OUTPUT_FILE_NAME :=AtmelStart
|
||||
QUOTE := "
|
||||
OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
|
||||
OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
|
||||
|
||||
vpath %.c ../
|
||||
vpath %.s ../
|
||||
vpath %.S ../
|
||||
|
||||
# All Target
|
||||
all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
|
||||
|
||||
# Linker target
|
||||
|
||||
$(OUTPUT_FILE_PATH): $(OBJS)
|
||||
@echo Building target: $@
|
||||
@echo Invoking: ARMCC Linker
|
||||
$(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \
|
||||
--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \
|
||||
--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \
|
||||
-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \
|
||||
$(OBJS_AS_ARGS)
|
||||
|
||||
@echo Finished building target: $@
|
||||
|
||||
# Compiler target(s)
|
||||
|
||||
|
||||
|
||||
|
||||
%.o: %.c
|
||||
@echo Building file: $<
|
||||
@echo ARMCC Compiler
|
||||
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
|
||||
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||
--depend "$@" -o "$@" "$<"
|
||||
|
||||
@echo Finished building: $<
|
||||
|
||||
%.o: %.s
|
||||
@echo Building file: $<
|
||||
@echo ARMCC Assembler
|
||||
$(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAME54P20A__ SETA 1" \
|
||||
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||
--depend "$(@:%.o=%.d)" -o "$@" "$<"
|
||||
|
||||
@echo Finished building: $<
|
||||
|
||||
%.o: %.S
|
||||
@echo Building file: $<
|
||||
@echo ARMCC Preprocessing Assembler
|
||||
$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
|
||||
-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \
|
||||
--depend "$@" -o "$@" "$<"
|
||||
|
||||
@echo Finished building: $<
|
||||
|
||||
# Detect changes in the dependent files and recompile the respective object files.
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(DEPS)),)
|
||||
-include $(DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
$(SUB_DIRS):
|
||||
$(MK_DIR) "$@"
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS_AS_ARGS)
|
||||
rm -f $(OUTPUT_FILE_PATH)
|
||||
rm -f $(DEPS_AS_ARGS)
|
||||
rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,70 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2016 Atmel Corporation,
|
||||
* a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "same54.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if __FPU_USED
|
||||
/* Enable FPU */
|
||||
SCB->CPACR |= (0xFu << 20);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
#include <atmel_start.h>
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void)
|
||||
{
|
||||
system_init();
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
#ifndef ATMEL_START_H_INCLUDED
|
||||
#define ATMEL_START_H_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "driver_init.h"
|
||||
|
||||
/**
|
||||
* Initializes MCU, drivers and middleware in the project
|
||||
**/
|
||||
void atmel_start_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Code generated from Atmel Start.
|
||||
*
|
||||
* This file will be overwritten when reconfiguring your Atmel Start project.
|
||||
* Please copy examples or other code you want to keep to a separate file
|
||||
* to avoid losing it when reconfiguring.
|
||||
*/
|
||||
#ifndef ATMEL_START_PINS_H_INCLUDED
|
||||
#define ATMEL_START_PINS_H_INCLUDED
|
||||
|
||||
#include <hal_gpio.h>
|
||||
|
||||
// SAME54 has 14 pin functions
|
||||
|
||||
#define GPIO_PIN_FUNCTION_A 0
|
||||
#define GPIO_PIN_FUNCTION_B 1
|
||||
#define GPIO_PIN_FUNCTION_C 2
|
||||
#define GPIO_PIN_FUNCTION_D 3
|
||||
#define GPIO_PIN_FUNCTION_E 4
|
||||
#define GPIO_PIN_FUNCTION_F 5
|
||||
#define GPIO_PIN_FUNCTION_G 6
|
||||
#define GPIO_PIN_FUNCTION_H 7
|
||||
#define GPIO_PIN_FUNCTION_I 8
|
||||
#define GPIO_PIN_FUNCTION_J 9
|
||||
#define GPIO_PIN_FUNCTION_K 10
|
||||
#define GPIO_PIN_FUNCTION_L 11
|
||||
#define GPIO_PIN_FUNCTION_M 12
|
||||
#define GPIO_PIN_FUNCTION_N 13
|
||||
|
||||
#define PB12 GPIO(GPIO_PORTB, 12)
|
||||
#define PB13 GPIO(GPIO_PORTB, 13)
|
||||
#define PB24 GPIO(GPIO_PORTB, 24)
|
||||
#define PB25 GPIO(GPIO_PORTB, 25)
|
||||
#define LED0 GPIO(GPIO_PORTC, 18)
|
||||
|
||||
#endif // ATMEL_START_PINS_H_INCLUDED
|
||||
@@ -0,0 +1,20 @@
|
||||
/* Auto-generated config file hpl_aes_config.h */
|
||||
#ifndef HPL_AES_CONFIG_H
|
||||
#define HPL_AES_CONFIG_H
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Advanced configurations
|
||||
|
||||
// <q> Run In Debug
|
||||
// <i> Indicates whether the AES to continue normal operation during debug mode
|
||||
// <id> aes_dbgctrl
|
||||
#ifndef CONF_AES_DBGCTRL
|
||||
#define CONF_AES_DBGCTRL 0
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
||||
#endif // HPL_AES_CONFIG_H
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user