Add Microchip SAM series MCU support for RT-Thread (#5771)

* Add Microchip SAM series MCU support for RT-Thread

Add Microchip SAM series MCU support for RT-Thread, including SAM Cortex-M0+, M4F and M7.

* Add bsp directory to ignored check list

Add bsp directory to ignored check list, add microchip /samc21/same54/same70 to workflows list

* remove STDIO definition and bug fix

1. remove STDIO code from Microchip official BSP. 2. bug fix of SAME70 hpl/hpl_usart.c, samc21&same54 hpl/hpl_sercom.c baudrate update interface.  3. Add RT-Thread standard STDIO implementation on Microchip SAM MCU.

* add CAN driver & example and script fix

Add CAN driver and example for SAMC21/SAME5x/SAME70 and fix rtconfig.py issue(unused space might result link error)

* Add Chinese version README

Add Chinese version README for SAMC21/E54/E70

bsp/microchip/samc21/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- bsp

bsp/microchip/samc21/Kconfig

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+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+# you can change the RTT_ROOT default: "rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
+config SOC_SAMC21
+    bool 
+    select ARCH_ARM
+    select ARCH_ARM_CORTEX_M
+    select ARCH_ARM_CORTEX_M0
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y

bsp/microchip/samc21/README.md

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+# SAMC21J18A BSP Introduction
+
+[中文](README_zh.md) 
+
+- MCU: ATSAMC21J18A @64MHz, 256KB FLASH, 32KB RAM, 2.7V – 5.5V
+- C21: Cortex-M0+ + Advanced Feature Set + 2x CAN-FD + Delta-Sigma ADC
+- Pin: N=100 pins, J=64 pins, G=48 pins, E=32 pins
+- Flash: 18=256KB, 17=128KB, 16=64KB , 15=32KB(size=2^n)
+- SRAM : 32KB(Flash 256KB), 16KB(Flash 128KB), 8KB(Flash 64KB), 4KB(Flash 32KB)
+## Datasheet: <https://www.microchip.com/en-us/product/ATSAMC21J18A>
+
+#### KEY FEATURES
+
+#### Core
+  - 32-bit Arm® Cortex®-M0+ CPU running at up to 48 MHz or 64 MHz with Single-cycle hardware multiplier
+
+####  Memories
+  - 32/64/128/256 KB in-system self-programmable Flash
+  - 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation
+  - 4/8/16/32 KB SRAM main memory
+
+#### System
+  - Power-on Reset (POR) and Brown-out Detection (BOD)
+  - Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)
+  - External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C20/C21 N)
+  - 16 external interrupts
+  - One non-maskable interrupt
+  - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
+
+#### High-Performance Peripherals
+  - Hardware Divide and Square Root Accelerator (DIVAS)
+  - 12-channel Direct Memory Access Controller (DMAC)
+  - 12-channel Event System
+  - Up to eight 16-bit Timer/Counters (TC), configurable as either
+  - Two 24-bit and one 16-bit Timer/Counter for Control (TCC), with extended functions
+  - Frequency Meter (The division reference clock is only available in the SAM C21N)
+  - 32-bit Real Time Counter (RTC) with clock/calendar function
+  - Watchdog Timer (WDT)
+  - CRC-32 generator
+  - Up to two Controller Area Network (CAN) interfaces in the SAM C21
+  - Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as USART/I2C/SPI
+  - One Configurable Custom Logic (CCL)
+  - Up to Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels each (20 unique channels)
+  - One 16-bit Sigma-Delta Analog-to-Digital Converter (SDADC) with up to 3 differential channels in the SAM C21
+  - 10-bit, 350 ksps Digital-to-Analog Converter (DAC) in the SAM C21
+  - Up to four Analog Comparators (AC) with Window Compare function
+  - Integrated Temperature Sensor in the SAM C21
+  - Peripheral Touch Controller (PTC)
+  - 256-Channel capacitive touch
+
+#### I/O
+  - Up to 84 programmable I/O pins
+
+#### Qualification
+  - AEC - Q100 Grade 1 (-40°C to 125°C)
+
+#### Voltage
+  - 2.7V – 5.5V
+  - -40°C to +125°C, DC to 48 MHz
+  - -40°C to +85°C, DC to 64 MHz
+
+#### Packages
+  - 100-pin TQFP
+  - 64-pin TQFP, VQFN
+  - 56-pin WLCSP
+  - 48-pin TQFP, VQFN
+  - 32-pin TQFP, VQFN
+
+#### Board info
+- [SAM C21 XPLAINED PRO]（https://www.microchip.com/en-us/development-tool/ATSAMC21-XPRO）

bsp/microchip/samc21/README_zh.md

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+# SAMC21J18A BSP 介绍
+
+[English](README.md) 
+
+- MCU: ATSAMC21J18A @64MHz, 256KB FLASH, 32KB RAM, 2.7V – 5.5V
+- C21: Cortex-M0+内核 + 丰富外设 + 2路CAN-FD + Delta-Sigma ADC
+- 管脚: N系列-100 pins, J系列-64 pins, G系列-48 pins, E系列-32 pins
+- Flash: 18=256KB, 17=128KB, 16=64KB , 15=32KB(size=2^n)
+- SRAM : 32KB(Flash 256KB), 16KB(Flash 128KB), 8KB(Flash 64KB), 4KB(Flash 32KB)
+## 手册: <https://www.microchip.com/en-us/product/ATSAMC21J18A>
+
+#### KEY FEATURES
+
+#### 内核
+  - 32-bit Arm® Cortex®-M0+ 内核， 主频最高48MHz和64 MHz+单指令周期的硬件乘法器
+
+####  内存
+  - 32/64/128/256 KB in-system self-programmable Flash
+  - 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation
+  - 4/8/16/32 KB SRAM main memory
+
+#### 系统特性
+  - Power-on Reset (POR) and Brown-out Detection (BOD)
+  - Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)
+  - External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C20/C21 N)
+  - 16 external interrupts
+  - One non-maskable interrupt
+  - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
+
+#### 高性能外设
+  - Hardware Divide and Square Root Accelerator (DIVAS)
+  - 12-channel Direct Memory Access Controller (DMAC)
+  - 12-channel Event System
+  - Up to eight 16-bit Timer/Counters (TC), configurable as either
+  - Two 24-bit and one 16-bit Timer/Counter for Control (TCC), with extended functions
+  - Frequency Meter (The division reference clock is only available in the SAM C21N)
+  - 32-bit Real Time Counter (RTC) with clock/calendar function
+  - Watchdog Timer (WDT)
+  - CRC-32 generator
+  - Up to two Controller Area Network (CAN) interfaces in the SAM C21
+  - Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as USART/I2C/SPI
+  - One Configurable Custom Logic (CCL)
+  - Up to Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels each (20 unique channels)
+  - One 16-bit Sigma-Delta Analog-to-Digital Converter (SDADC) with up to 3 differential channels in the SAM C21
+  - 10-bit, 350 ksps Digital-to-Analog Converter (DAC) in the SAM C21
+  - Up to four Analog Comparators (AC) with Window Compare function
+  - Integrated Temperature Sensor in the SAM C21
+  - Peripheral Touch Controller (PTC)
+  - 256-Channel capacitive touch
+
+#### I/O管脚
+  - 最多提供84个用户可编程I/O管脚
+
+#### 汽车应用
+  - AEC - Q100 Grade 1 (-40°C to 125°C)
+
+#### 工作电压
+  - 2.7V – 5.5V
+  - -40°C to +125°C, DC to 48 MHz
+  - -40°C to +85°C, DC to 64 MHz
+
+#### 封装
+  - 100-pin TQFP
+  - 64-pin TQFP, VQFN
+  - 56-pin WLCSP
+  - 48-pin TQFP, VQFN
+  - 32-pin TQFP, VQFN
+
+#### 官方开发板信息
+- [SAM C21 XPLAINED PRO]（https://www.microchip.com/en-us/development-tool/ATSAMC21-XPRO）

bsp/microchip/samc21/SConscript

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+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/microchip/samc21/SConstruct

@@ -0,0 +1,41 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread-' + rtconfig.DEVICE_PART + '.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread-'+ rtconfig.DEVICE_PART + '.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/microchip/samc21/applications/SConscript

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+import rtconfig
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/microchip/samc21/applications/can_demo.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __APPLICATION_CAN_H_
+#define __APPLICATION_CAN_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+rt_err_t can_demo_run(void);
+
+rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts);
+
+#endif // __APPLICATION_CAN_H_

bsp/microchip/samc21/applications/main.c

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+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+#include "atmel_start.h"
+#include <hal_gpio.h>
+
+#ifdef SAM_CAN_EXAMPLE
+#include "can_demo.h"
+#endif
+
+static rt_uint8_t led_stack[ 512 ];
+static struct rt_thread led_thread;
+
+static void led_thread_entry(void* parameter)
+{
+    unsigned int count=0;
+
+    while (1)
+    {
+        /* toggle led */
+#ifndef RT_USING_FINSH
+        rt_kprintf("led toggle, count : %d\r\n",count);
+#endif
+        count++;
+        gpio_toggle_pin_level(LED0);
+        rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
+    }
+}
+
+int main(void)
+{
+    rt_err_t result;
+
+    /* initialize led thread */
+    result = rt_thread_init(&led_thread,
+                            "led",
+                            led_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t*)&led_stack[0],
+                            sizeof(led_stack),
+                            RT_THREAD_PRIORITY_MAX/3,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&led_thread);
+    }
+
+#ifdef SAM_CAN_EXAMPLE
+    can_demo_run();
+#endif
+
+    return 0;
+}
+
+/*@}*/

bsp/microchip/samc21/board/Kconfig

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+menu "Hardware Drivers Config"
+
+choice
+    prompt "select chip type"
+    default SOC_SAMC21J18
+
+    config SOC_SAMC21J18
+    bool "SOC_SAMC21J18"
+    help
+        Refer to SAMC21 DataSheet
+
+    config SOC_SAMC21G18
+    bool "SOC_SAMC21G18"
+    help
+        Refer to SAMC21 DataSheet
+
+    config SOC_SAMC21E18
+    bool "SOC_SAMC21E18"
+    help
+        Refer to SAMC21 DataSheet
+
+endchoice 
+endmenu
+
+menu "Onboard Peripheral Drivers"
+    depends on SOC_SAMC21J18
+
+    config SAMC21_CAN0
+        bool "Enable CAN0"
+        default false
+
+    config SAMC21_ADC0
+        bool "Enable ADC0"
+        default false
+endmenu
+
+menu "Application Demo Config"
+    config SAM_CAN_EXAMPLE
+        bool "Enable SAM CAN Example"
+        depends on SAMC21_CAN0
+        default true
+        help
+            Add CAN example task to project
+
+    config SAM_ADC_EXAMPLE
+        bool "Enable SAM ADC Example"
+        depends on SAMC21_ADC0
+        default true
+        help
+            Add ADC example task to project
+
+endmenu

bsp/microchip/samc21/board/SConscript

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+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+# You can select chips from the list above
+CPPDEFINES = ['SAMC21xxx']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/microchip/samc21/board/board.c

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <string.h>
+
+#include <atmel_start.h>
+#include "peripheral_clk_config.h"
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef RT_USING_SERIAL
+extern int rt_hw_uart_init(void);
+#endif
+
+static struct io_descriptor* g_stdio;
+
+void rt_hw_console_output(const char *str)
+{
+    io_write(g_stdio, (uint8_t *)str, strlen(str));
+}
+RTM_EXPORT(rt_hw_console_output);
+
+static inline void hw_board_init_usart(void)
+{
+    usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
+    usart_sync_enable(&TARGET_IO);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial SAMC21 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* Initializes MCU, drivers and middleware */
+    atmel_start_init();
+
+    /* enable USART stdout module */
+    hw_board_init_usart();
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* init systick */
+    SysTick_Config(CONF_CPU_FREQUENCY / RT_TICK_PER_SECOND);
+
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+
+#ifdef RT_USING_HEAP
+    #if defined(__CC_ARM) || defined(__CLANG_ARM)
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)HEAP_END);
+    #elif __ICCARM__
+        rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
+    #else
+        /* init memory system */
+        rt_system_heap_init((void*)&__bss_end, (void*)HEAP_END);
+    #endif
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/microchip/samc21/board/board.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+// <o> Internal SRAM memory size[Kbytes] <4-32>
+//  <i>Default: 32
+#if   defined(__SAMC21E15A__) || defined(__ATSAMC21E15A__)
+  #define SAMC21_SRAM_SIZE   4
+#elif defined(__SAMC21E16A__) || defined(__ATSAMC21E16A__)
+  #define SAMC21_SRAM_SIZE   8
+#elif defined(__SAMC21E17A__) || defined(__ATSAMC21E17A__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21E18A__) || defined(__ATSAMC21E18A__)
+  #define SAMC21_SRAM_SIZE   32
+#elif defined(__SAMC21G15A__) || defined(__ATSAMC21G15A__)
+  #define SAMC21_SRAM_SIZE   4
+#elif defined(__SAMC21G16A__) || defined(__ATSAMC21G16A__)
+  #define SAMC21_SRAM_SIZE   8
+#elif defined(__SAMC21G17A__) || defined(__ATSAMC21G17A__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21G18A__) || defined(__ATSAMC21G18A__)
+  #define SAMC21_SRAM_SIZE   32
+#elif defined(__SAMC21J15A__) || defined(__ATSAMC21J15A__)
+  #define SAMC21_SRAM_SIZE   4
+#elif defined(__SAMC21J16A__) || defined(__ATSAMC21J16A__)
+  #define SAMC21_SRAM_SIZE   8
+#elif defined(__SAMC21J17A__) || defined(__ATSAMC21J17A__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21J17AU__) || defined(__ATSAMC21J17AU__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21J18A__) || defined(__ATSAMC21J18A__)
+  #define SAMC21_SRAM_SIZE   32
+#elif defined(__SAMC21J18AU__) || defined(__ATSAMC21J18AU__)
+  #define SAMC21_SRAM_SIZE   32
+#else
+  #error Board does not support the specified device.
+#endif
+
+#define SAMC21_SRAM_END        (0x20000000 + SAMC21_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN    (__segment_begin("HEAP"))
+#define HEAP_END      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN    (&__bss_end)
+#define HEAP_END      SAMC21_SRAM_END
+#endif
+
+void rt_hw_board_init(void);
+
+#endif
+

bsp/microchip/samc21/board/serial.c

@@ -0,0 +1,199 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <atmel_start.h>
+
+/* SAM MCU serial device */
+static struct rt_serial_device sam_serial;
+
+/**
+ * @brief Configure serial port
+ *
+ * This function will configure UART baudrate, parity and so on.
+ *
+ * @return RT_EOK.
+ */
+static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+    RT_ASSERT(cfg  != RT_NULL);
+
+    usart_sync_disable(desc);
+
+    /* Set baudrate */
+    usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
+
+    /* Set stop bit */
+    if (cfg->stop_bits == STOP_BITS_1)
+        usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
+    else if (cfg->stop_bits == STOP_BITS_2)
+        usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
+
+    if (cfg->bit_order == BIT_ORDER_LSB)
+        usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
+    else if (cfg->bit_order == BIT_ORDER_MSB)
+        usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
+
+    /* Set character size */
+    switch (cfg->data_bits)
+    {
+        case DATA_BITS_5:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
+            break;
+        case DATA_BITS_6:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
+            break;
+        case DATA_BITS_7:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
+            break;
+        case DATA_BITS_8:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
+            break;
+        case DATA_BITS_9:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
+            break;
+        default:
+            break;
+    }
+
+    if (cfg->parity == PARITY_NONE)
+        usart_sync_set_parity(desc, USART_PARITY_NONE);
+    else if (cfg->parity == PARITY_ODD)
+        usart_sync_set_parity(desc, USART_PARITY_ODD);
+    else if (cfg->parity == PARITY_EVEN)
+        usart_sync_set_parity(desc, USART_PARITY_EVEN);
+
+    usart_sync_enable(desc);
+
+    return RT_EOK;
+}
+
+/**
+ * @brief Control serial port
+ *
+ * This function provide UART enable/disable control.
+ *
+ * @return RT_EOK.
+ */
+static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    switch (cmd)
+    {
+        /* disable interrupt */
+        case RT_DEVICE_CTRL_CLR_INT:
+            usart_sync_disable(desc);
+            break;
+        /* enable interrupt */
+        case RT_DEVICE_CTRL_SET_INT:
+            usart_sync_enable(desc);
+            break;
+        /* UART config */
+        case RT_DEVICE_CTRL_CONFIG :
+            break;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief Serial sends a char
+ *
+ * This function will send a char to the UART
+ *
+ * @return 1.
+ */
+static int serial_putc(struct rt_serial_device *serial, char c)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    io_write(&desc->io, (const uint8_t *)&c, 1);
+
+    return 1;
+}
+
+/**
+ * @brief Serial gets a char
+ *
+ * This function will get a char from the UART
+ *
+ * @return received char character or -1 if no char received.
+ */
+static int serial_getc(struct rt_serial_device *serial)
+{
+    char c;
+    int ch;
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    ch = -1;
+    if (usart_sync_is_rx_not_empty(desc))
+    {
+        io_read(&desc->io, (uint8_t *)&c, 1);;
+        ch = c & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops sam_serial_ops =
+{
+    serial_configure,
+    serial_control,
+    serial_putc,
+    serial_getc,
+};
+
+/**
+ * @brief Initialize the UART
+ *
+ * This function initialize the UART
+ *
+ * @return None.
+ */
+int rt_hw_uart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    sam_serial.ops       = &sam_serial_ops;
+    sam_serial.config    = config;
+    sam_serial.serial_rx = RT_NULL;
+    sam_serial.serial_rx = RT_NULL;
+    rt_hw_serial_register(&sam_serial, "uart0",
+                          RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
+
+    return 0;
+}
+
+/*@}*/

bsp/microchip/samc21/board/serial.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __BOARD_SERIAL_H_
+#define __BOARD_SERIAL_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+int rt_hw_uart_init(void);
+
+#endif // __BOARD_SERIAL_H_

bsp/microchip/samc21/bsp/AtmelStart.env_conf

@@ -0,0 +1,6 @@
+<environment>
+  <configurations/>
+  <device-packs>
+    <device-pack device="ATSAMC21J18A" name="SAMC21_DFP" vendor="Atmel" version="1.2.176"/>
+  </device-packs>
+</environment>

bsp/microchip/samc21/bsp/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/microchip/samc21/bsp/CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

bsp/microchip/samc21/bsp/CMSIS/Documentation/Core/html/index.html

@@ -0,0 +1,196 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>Overview</title>
+<title>CMSIS-Core (Cortex-M): Overview</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<script type="text/javascript" src="printComponentTabs.js"></script>
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+  $(window).load(resizeHeight);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.1.2</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <script type="text/javascript">
+		<!--
+		writeComponentTabs.call(this);
+		//-->
+      </script>
+	  </ul>
+</div>
+<!-- Generated by Doxygen 1.8.6 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+      <div id="nav-sync" class="sync"></div>
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+$(document).ready(function(){initNavTree('index.html','');});
+</script>
+<div id="doc-content">
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+<div class="header">
+  <div class="headertitle">
+<div class="title">Overview </div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
+<ul>
+<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
+<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
+<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
+<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
+<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
+<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
+</ul>
+<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
+<ul>
+<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
+<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone&reg; for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li>
+<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
+<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
+<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
+<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
+</ul>
+<hr/>
+<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2>
+<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p>
+<table class="doxtable">
+<tr>
+<th>File/Folder </th><th>Content  </th></tr>
+<tr>
+<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
+<tr>
+<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
+<tr>
+<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr>
+<tr>
+<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr>
+</table>
+<hr/>
+<h1><a class="anchor" id="ref_v6-v8M"></a>
+Processor Support</h1>
+<p>CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.</p>
+<h2><a class="anchor" id="ref_man_sec"></a>
+Cortex-M Reference Manuals</h2>
+<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
+<ul>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
+</ul>
+<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p>
+<ul>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li>
+</ul>
+<h2><a class="anchor" id="ARMv8M"></a>
+Armv8-M Architecture</h2>
+<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.</p>
+<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
+<hr/>
+<h1><a class="anchor" id="tested_tools_sec"></a>
+Tested and Verified Toolchains</h1>
+<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p>
+<ul>
+<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)</li>
+<li>Arm: Arm Compiler 6.9</li>
+<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)</li>
+<li>GNU: GNU Tools for Arm Embedded 6.3.1 20170620</li>
+<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li>
+</ul>
+<hr/>
+ </div></div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

bsp/microchip/samc21/bsp/SConscript

@@ -0,0 +1,58 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+#var defined
+CPPDEFINES = []
+
+#common lib define
+CPPDEFINES += [rtconfig.DEVICE_TYPE]
+
+# The set of source files associated with this SConscript file.
+src  = Glob('hal/src/*.c')
+src += Glob('hal/utils/src/*.c')
+src += Glob('hpl/can/*.c')
+src += Glob('hpl/core/*.c')
+src += Glob('hpl/divas/*.c')
+src += Glob('hpl/dmac/*.c')
+src += Glob('hpl/gclk/*.c')
+src += Glob('hpl/mclk/*.c')
+src += Glob('hpl/nvmctrl/*.c')
+src += Glob('hpl/osc32kctrl/*.c')
+src += Glob('hpl/oscctrl/*.c')
+src += Glob('hpl/pm/*.c')
+src += Glob('hpl/port/*.c')
+src += Glob('hpl/sercom/*.c')
+src += [cwd + '/atmel_start.c']
+src += [cwd + '/driver_init.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/samc21/gcc/system_samc21.c']
+    src += [cwd + '/samc21/gcc/gcc/startup_samc21.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/samc21/armcc/arm_addon/armcc/' + 'system_samc21.c']
+    src += [cwd + '/samc21/armcc/arm_addon/armcc/arm/' + 'startup_samc21.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/samc21/iar/' + 'system_samc21.c']
+    src += [cwd + '/samc21/iar/iar/' + 'startup_samc21.c']
+
+path = [
+    cwd,
+    cwd + '/CMSIS/Core/Include',
+    cwd + '/config',
+    cwd + '/hal/include',
+    cwd + '/hal/utils/include',
+    cwd + '/hpl/can',
+    cwd + '/hpl/core',
+    cwd + '/hpl/gclk',
+    cwd + '/hpl/pm',
+    cwd + '/hpl/port',
+    cwd + '/hri',
+    cwd + '/samc21/include']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/microchip/samc21/bsp/atmel_start.c

@@ -0,0 +1,9 @@
+#include <atmel_start.h>
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+	system_init();
+}

bsp/microchip/samc21/bsp/atmel_start.h

@@ -0,0 +1,18 @@
+#ifndef ATMEL_START_H_INCLUDED
+#define ATMEL_START_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "driver_init.h"
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

bsp/microchip/samc21/bsp/atmel_start_pins.h

@@ -0,0 +1,31 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file
+ * to avoid losing it when reconfiguring.
+ */
+#ifndef ATMEL_START_PINS_H_INCLUDED
+#define ATMEL_START_PINS_H_INCLUDED
+
+#include <hal_gpio.h>
+
+// SAMC21 has 9 pin functions
+
+#define GPIO_PIN_FUNCTION_A 0
+#define GPIO_PIN_FUNCTION_B 1
+#define GPIO_PIN_FUNCTION_C 2
+#define GPIO_PIN_FUNCTION_D 3
+#define GPIO_PIN_FUNCTION_E 4
+#define GPIO_PIN_FUNCTION_F 5
+#define GPIO_PIN_FUNCTION_G 6
+#define GPIO_PIN_FUNCTION_H 7
+#define GPIO_PIN_FUNCTION_I 8
+
+#define LED0 GPIO(GPIO_PORTA, 15)
+#define PA24 GPIO(GPIO_PORTA, 24)
+#define PA25 GPIO(GPIO_PORTA, 25)
+#define PB10 GPIO(GPIO_PORTB, 10)
+#define PB11 GPIO(GPIO_PORTB, 11)
+
+#endif // ATMEL_START_PINS_H_INCLUDED

bsp/microchip/samc21/bsp/config/hpl_divas_config.h

@@ -0,0 +1,13 @@
+
+// <h> Advanced settings
+
+// <q> Disable Leading Zero Optimization
+// <i> Leading zero optimization makes division faster but cycles to take varias according to input values
+// <i> With leading zero optimization the clock cycles are 2-8 for 16-bit and 2-16 for 32-bit
+// <i> Disable leading zero optimization will force the division to take a fixed time of maximum number of cycles
+// <id> divas_arch_dlz
+#ifndef CONF_DIVAS_DLZ
+#define CONF_DIVAS_DLZ 0
+#endif
+
+// </h>

bsp/microchip/samc21/bsp/config/hpl_mclk_config.h

@@ -0,0 +1,72 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Basic settings
+// <y> CPU Clock source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <i> This defines the clock source for the CPU
+// <id> cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> CPU Clock Division Factor
+// <MCLK_CPUDIV_CPUDIV_DIV1_Val"> 1
+// <MCLK_CPUDIV_CPUDIV_DIV2_Val"> 2
+// <MCLK_CPUDIV_CPUDIV_DIV4_Val"> 4
+// <MCLK_CPUDIV_CPUDIV_DIV8_Val"> 8
+// <MCLK_CPUDIV_CPUDIV_DIV16_Val"> 16
+// <MCLK_CPUDIV_CPUDIV_DIV32_Val"> 32
+// <MCLK_CPUDIV_CPUDIV_DIV64_Val"> 64
+// <MCLK_CPUDIV_CPUDIV_DIV128_Val"> 128
+// <i> Prescalar for CPU clock
+// <id> cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val
+#endif
+
+// </h>
+
+// <h> NVM Settings
+// <o> NVM Wait States
+// <i> These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <id> nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 4
+#endif
+
+// </h>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H

bsp/microchip/samc21/bsp/config/hpl_nvmctrl_config.h

@@ -0,0 +1,38 @@
+/* Auto-generated config file hpl_nvmctrl_config.h */
+#ifndef HPL_NVMCTRL_CONFIG_H
+#define HPL_NVMCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Settings
+
+// <o> Read Mode Selection
+// <0x00=> No Miss Penalty
+// <0x01=> Low Power
+// <0x02=> Deterministic
+// <id> nvm_arch_read_mode
+#ifndef CONF_NVM_READ_MODE
+#define CONF_NVM_READ_MODE 0
+#endif
+
+// <o> Power Reduction Mode During Sleep
+// <0x00=> Wake On Access
+// <0x01=> Wake Up Instant
+// <0x03=> Disabled
+// <id> nvm_arch_sleepprm
+#ifndef CONF_NVM_SLEEPPRM
+#define CONF_NVM_SLEEPPRM 0
+#endif
+
+// <q> Cache Disable
+// <i> Indicate whether cache is disable or not
+// <id> nvm_arch_cache
+#ifndef CONF_NVM_CACHE
+#define CONF_NVM_CACHE 0
+#endif
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_NVMCTRL_CONFIG_H

bsp/microchip/samc21/bsp/config/peripheral_clk_config.h

@@ -0,0 +1,113 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 40001536
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM4_CORE_SRC
+#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM4_SLOW_SRC
+#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY
+ * \brief SERCOM4's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 40001536
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY
+ * \brief SERCOM4's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 4000000
+#endif
+
+// <y> CAN0 Clock Source
+// <id> can_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <i> Select the clock source for CAN0.
+#ifndef CONF_GCLK_CAN0_SRC
+#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_CAN0_FREQUENCY
+ * \brief CAN0's Clock frequency
+ */
+#ifndef CONF_GCLK_CAN0_FREQUENCY
+#define CONF_GCLK_CAN0_FREQUENCY 40001536
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H