[bsp][renesas]add EK-RA2A1 support #10610

.github/ALL_BSP_COMPILE.json

@@ -262,6 +262,7 @@
         "renesas/rzt2m_rsk",
         "renesas/rzn2l_rsk",
         "renesas/rzn2l_etherkit",
+        "renesas/ra2a1-ek",
         "frdm-k64f",
         "xplorer4330/M4"
       ]
@@ -501,4 +502,4 @@
       ]
     }
   ]
-}
+}

bsp/renesas/libraries/HAL_Drivers/config/drv_config.h

@@ -7,6 +7,7 @@
 * Date           Author            Notes
 * 2021-07-29     KyleChan          first version
 * 2022-12-7      Vandoul           ADD ra4m2
+* 2025-08-17     CYFS              ADD ra2a1
 */
 
 #ifndef __DRV_CONFIG_H__
@@ -203,6 +204,30 @@ extern "C"
 #endif
 #endif /* SOC_SERIES_R7FA6E2 */
 
+#if defined(SOC_SERIES_R7FA2A1)
+#include "ra2a1/uart_config.h"
+
+#ifdef BSP_USING_ADC
+#include "ra2a1/adc_config.h"
+#endif
+
+#ifdef BSP_USING_DAC
+#include "ra2a1/dac_config.h"
+#endif
+
+#ifdef BSP_USING_PWM
+#include "ra2a1/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_TIM
+#include "ra2a1/timer_config.h"
+#endif
+
+#ifdef BSP_USING_CAN
+#include "ra2a1/can_config.h"
+#endif
+#endif /* SOC_SERIES_R7FA2A1 */
+
 #ifdef __cplusplus
 }
 #endif

bsp/renesas/libraries/HAL_Drivers/config/ra2a1/adc_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-17     CYFS         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
+
+struct rt_adc_dev
+{
+    struct rt_adc_ops ops;
+    struct rt_adc_device adc_device;
+};
+
+struct ra_adc_map
+{
+    const char *device_name;
+    const adc_cfg_t *g_cfg;
+    const adc_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/libraries/HAL_Drivers/config/ra2a1/can_config.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_CAN0)
+#ifndef CAN0_CONFIG
+#define CAN0_CONFIG                                                 \
+    {                                                               \
+        .name = "can0",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0,             \
+        .p_api_ctrl = &g_can0_ctrl,                                \
+        .p_cfg = &g_can0_cfg,                                      \
+    }
+#endif /* CAN0_CONFIG */
+#endif /* BSP_USING_CAN0 */
+
+#if defined(BSP_USING_CAN1)
+#ifndef CAN1_CONFIG
+#define CAN1_CONFIG                                                 \
+    {                                                               \
+        .name = "can1",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1,             \
+        .p_api_ctrl = &g_can1_ctrl,                                \
+        .p_cfg = &g_can1_cfg,                                      \
+    }
+#endif /* CAN1_CONFIG */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif

bsp/renesas/libraries/HAL_Drivers/config/ra2a1/dac_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-17     CYFS         first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC
+struct ra_dac_map
+{
+    char name;
+    const struct st_dac_cfg *g_cfg;
+    const struct st_dac_instance_ctrl *g_ctrl;
+};
+
+struct ra_dac_dev
+{
+    rt_dac_device_t       ra_dac_device_t;
+    struct ra_dac_map    *ra_dac_map_dev;
+};
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/libraries/HAL_Drivers/config/ra2a1/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    BSP_PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    BSP_PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    BSP_PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    BSP_PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/renesas/libraries/HAL_Drivers/config/ra2a1/uart_config.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+        .p_api_ctrl = &g_uart0_ctrl,                                \
+        .p_cfg = &g_uart0_cfg,                                      \
+    }
+#endif /* UART0_CONFIG */
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .p_api_ctrl = &g_uart1_ctrl,                                \
+        .p_cfg = &g_uart1_cfg,                                      \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART9)
+#ifndef UART9_CONFIG
+#define UART9_CONFIG                                                \
+    {                                                               \
+        .name = "uart9",                                            \
+        .p_api_ctrl = &g_uart9_ctrl,                                \
+        .p_cfg = &g_uart9_cfg,                                      \
+    }
+#endif /* UART9_CONFIG */
+#endif /* BSP_USING_UART9 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/renesas/libraries/Kconfig

@@ -59,4 +59,10 @@ config SOC_SERIES_R7FA6E2
     bool
     select ARCH_ARM_CORTEX_M33
     select SOC_FAMILY_RENESAS_RA
+    default n
+
+config SOC_SERIES_R7FA2A1
+    bool
+    select ARCH_ARM_CORTEX_M23
+    select SOC_FAMILY_RENESAS_RA
     default n

bsp/renesas/ra2a1-ek/.api_xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<ddscApi/>

bsp/renesas/ra2a1-ek/.gitignore

@@ -0,0 +1,5 @@
+/RTE
+/Listings
+/Objects
+ra_cfg.txt
+

bsp/renesas/ra2a1-ek/.ignore_format.yml

@@ -0,0 +1,9 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- ra
+- ra_gen
+- ra_cfg
+- RTE

bsp/renesas/ra2a1-ek/.secure_azone

@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<azone>
+    <rzone name="R7FA2A1AB3CFM.rzone"/>
+    <partition>
+        <peripheral name="PORT0.CM23" group="PORT">
+            <slot name="P001.CM23" secure="false"/>
+            <slot name="P003.CM23" secure="false"/>
+        </peripheral>
+        <peripheral name="PORT1.CM23" group="PORT">
+            <slot name="P108.CM23" secure="false"/>
+            <slot name="P111.CM23" secure="false"/>
+            <slot name="P112.CM23" secure="false"/>
+        </peripheral>
+        <peripheral name="PORT2.CM23" group="PORT">
+            <slot name="P201.CM23" secure="false"/>
+            <slot name="P205.CM23" secure="false"/>
+            <slot name="P206.CM23" secure="false"/>
+        </peripheral>
+        <peripheral name="PORT3.CM23" group="PORT">
+            <slot name="P300.CM23" secure="false"/>
+            <slot name="P301.CM23" secure="false"/>
+            <slot name="P302.CM23" secure="false"/>
+            <slot name="P303.CM23" secure="false"/>
+            <slot name="P304.CM23" secure="false"/>
+        </peripheral>
+        <peripheral name="PORT4.CM23" group="PORT">
+            <slot name="P407.CM23" secure="false"/>
+            <slot name="P409.CM23" secure="false"/>
+            <slot name="P410.CM23" secure="false"/>
+            <slot name="P411.CM23" secure="false"/>
+        </peripheral>
+        <peripheral name="PORT9.CM23" group="PORT">
+            <slot name="P914.CM23" secure="false"/>
+            <slot name="P915.CM23" secure="false"/>
+        </peripheral>
+        <peripheral name="SCI0.CM23" group="SCI" security=""/>
+        <peripheral name="ICU.CM23">
+            <slot name="IRQ0.CM23" secure="false"/>
+            <slot name="IRQ1.CM23" secure="false"/>
+            <slot name="IRQ2.CM23" secure="false"/>
+            <slot name="IRQ3.CM23" secure="false"/>
+        </peripheral>
+    </partition>
+</azone>

bsp/renesas/ra2a1-ek/.secure_rzone

@@ -0,0 +1,242 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<rzone>
+    <device Dvendor="Renesas" Dname="R7FA2A1">
+        <processor Pname="CM23" Dcore="Cortex-M23" Dfpu="0" Dmpu="1" Dtz="NO_TZ" Ddsp="1" Dendian="Little-endian" Dclock="48000000" DcoreVersion="r1p0" DnumInterrupts="32" DnumSauRegions="0"/>
+    </device>
+    <resources>
+        <memories>
+            <memory name="RAM" type="RAM" start="0x20000000" size="0x00008000" access="rwx" security="" info="On chip RAM memory"/>
+            <memory name="FLASH" type="ROM" start="0x00000000" size="0x00040000" access="rx" security="" info="On chip flash memory"/>
+            <memory name="DATA_FLASH" type="ROM" start="0x40100000" size="0x00002000" access="rx" security="" info="On chip data flash memory"/>
+            <memory name="OPTION_SETTING_OFS0" type="ROM" start="0x00000400" size="0x00000004" access="r" security="" info="Option Function Select Register 0"/>
+            <memory name="OPTION_SETTING_OFS1" type="ROM" start="0x00000404" size="0x00000004" access="r" security="" info="Option Function Select Register 1"/>
+            <memory name="OPTION_SETTING_SECMPU" type="ROM" start="0x00000408" size="0x00000034" access="r" security="" info="Security MPU Registers"/>
+            <memory name="OPTION_SETTING_OSIS" type="ROM" start="0x01010018" size="0x00000020" access="r" security="" info="OCD/Serial Programmer ID setting register"/>
+        </memories>
+        <peripherals>
+            <peripheral name="ACMP" start="0x00000000" size="0x00000000" info="Analog Comparator Pins"/>
+            <group name="ACMPHS" start="0x40085000" size="0x00000100" info="High Speed Analog Comparator">
+                <peripheral name="ACMPHS0" start="0x40085000" size="0x00000100"/>
+            </group>
+            <group name="ACMPLP" start="0x40085e00" size="0x00000100" info="Low Power Analog Comparator">
+                <peripheral name="ACMPLP0" start="0x40085e00" size="0x00000100"/>
+                <peripheral name="ACMPLP1" start="0x40085e00" size="0x00000100"/>
+            </group>
+            <group name="ADC" start="0x4005c000" size="0x00000200" info="A/D Converter">
+                <peripheral name="ADC0" start="0x4005c000" size="0x00000200"/>
+            </group>
+            <group name="AGT" start="0x40084000" size="0x00000100" info="Asynchronous General Purpose Timer">
+                <peripheral name="AGT0" start="0x40084000" size="0x00000100"/>
+                <peripheral name="AGT1" start="0x40084100" size="0x00000100"/>
+            </group>
+            <peripheral name="ANALOG" start="0x00000000" size="0x00000000" info="Analog-Pins"/>
+            <peripheral name="CAC" start="0x40044600" size="0x00000100" info="Clock Frequency Accuracy Measurement Circuit"/>
+            <group name="CAN" start="0x40050000" size="0x00001000" info="Controller Area Network (CAN) Module">
+                <peripheral name="CAN0" start="0x40050000" size="0x00001000"/>
+            </group>
+            <peripheral name="CGC" start="0x00000000" size="0x00000000" info="Clock Generation Circuit"/>
+            <peripheral name="CRC" start="0x40074000" size="0x00000100" info="Cyclic Redundancy Check (CRC) Calculator"/>
+            <peripheral name="CTSU" start="0x40081000" size="0x00000020" info="Capacitive Touch Sensing Unit"/>
+            <group name="DAC" start="0x4005e000" size="0x00000100" info="D/A Converter">
+                <peripheral name="DAC0" start="0x4005e000" size="0x00000100"/>
+            </group>
+            <group name="DAC12" start="0x4005e000" size="0x00000100" info="D/A Converter">
+                <peripheral name="DAC120" start="0x4005e000" size="0x00000100"/>
+            </group>
+            <group name="DAC8" start="0x4009e000" size="0x00000100" info="8-Bit D/A Converter">
+                <peripheral name="DAC80" start="0x4009e000" size="0x00000100"/>
+                <peripheral name="DAC81" start="0x4009e000" size="0x00000100"/>
+            </group>
+            <peripheral name="DEBUG" start="0x4001b000" size="0x00000000" info="Debug Function"/>
+            <peripheral name="DOC" start="0x40054100" size="0x00000010" info="Data Operation Circuit"/>
+            <peripheral name="DTC" start="0x40005400" size="0x00000100" info="Data Transfer Controller"/>
+            <peripheral name="ELC" start="0x40041000" size="0x00000100" info="Event Link Controller">
+                <slot name="GPT_A"/>
+                <slot name="GPT_B"/>
+                <slot name="GPT_C"/>
+                <slot name="GPT_D"/>
+                <slot name="ADC0"/>
+                <slot name="ADC0_B"/>
+                <slot name="DAC0"/>
+                <slot name="IOPORT1"/>
+                <slot name="IOPORT2"/>
+                <slot name="CTSU"/>
+                <slot name="DA8_0"/>
+                <slot name="DA8_1"/>
+                <slot name="SDADC0"/>
+            </peripheral>
+            <peripheral name="FCACHE" start="0x4001c000" size="0x00000000" info="Flash Memory Cache"/>
+            <peripheral name="FLASH" start="0x00000000" size="0x00000100" info="Flash"/>
+            <peripheral name="FLASH_LP" start="0x00000000" size="0x00000100" info="Low Power Flash"/>
+            <group name="GPT" start="0x40078000" size="0x00000100" info="General PWM Timer">
+                <peripheral name="GPT0" start="0x40078000" size="0x00000100"/>
+                <peripheral name="GPT1" start="0x40078100" size="0x00000100"/>
+                <peripheral name="GPT2" start="0x40078200" size="0x00000100"/>
+                <peripheral name="GPT3" start="0x40078300" size="0x00000100"/>
+                <peripheral name="GPT4" start="0x40078400" size="0x00000100"/>
+                <peripheral name="GPT5" start="0x40078500" size="0x00000100"/>
+                <peripheral name="GPT6" start="0x40078600" size="0x00000100"/>
+            </group>
+            <peripheral name="GPT_OPS" start="0x40078ff0" size="0x00000010" info="Output Phase Switching Controller"/>
+            <group name="GPT_POEG" start="0x40042000" size="0x00000100" info="Port Output Enable for GPT">
+                <peripheral name="GPT_POEG0" start="0x40042000" size="0x00000100"/>
+                <peripheral name="GPT_POEG1" start="0x40042100" size="0x00000100"/>
+            </group>
+            <peripheral name="ICU" start="0x40006000" size="0x00000100" info="Interrupt Controller Unit">
+                <slot name="IRQ0"/>
+                <slot name="IRQ1"/>
+                <slot name="IRQ2"/>
+                <slot name="IRQ3"/>
+                <slot name="IRQ4"/>
+                <slot name="IRQ5"/>
+                <slot name="IRQ6"/>
+                <slot name="IRQ7"/>
+                <slot name="IRQ8"/>
+                <slot name="IRQ9"/>
+                <slot name="IRQ10"/>
+                <slot name="IRQ11"/>
+                <slot name="IRQ12"/>
+                <slot name="IRQ13"/>
+                <slot name="IRQ14"/>
+                <slot name="IRQ15"/>
+                <slot name="IRQ16"/>
+                <slot name="IRQ17"/>
+                <slot name="IRQ18"/>
+                <slot name="IRQ19"/>
+                <slot name="IRQ20"/>
+                <slot name="IRQ21"/>
+                <slot name="IRQ22"/>
+                <slot name="IRQ23"/>
+                <slot name="IRQ24"/>
+                <slot name="IRQ25"/>
+                <slot name="IRQ26"/>
+                <slot name="IRQ27"/>
+                <slot name="IRQ28"/>
+                <slot name="IRQ29"/>
+                <slot name="IRQ30"/>
+                <slot name="IRQ31"/>
+            </peripheral>
+            <peripheral name="ICU_EXT_IRQ" start="0x40006000" size="0x00000001" info="Interrupt Controller Unit (External Pins Only)">
+                <slot name="ICU_EXT_IRQ0"/>
+                <slot name="ICU_EXT_IRQ1"/>
+                <slot name="ICU_EXT_IRQ2"/>
+                <slot name="ICU_EXT_IRQ3"/>
+                <slot name="ICU_EXT_IRQ4"/>
+                <slot name="ICU_EXT_IRQ5"/>
+                <slot name="ICU_EXT_IRQ6"/>
+                <slot name="ICU_EXT_IRQ7"/>
+                <slot name="ICU_EXT_SNZCANCEL"/>
+            </peripheral>
+            <group name="IIC" start="0x40053000" size="0x00000100" info="I2C Bus Interface">
+                <peripheral name="IIC0" start="0x40053000" size="0x00000100"/>
+                <peripheral name="IIC1" start="0x40053100" size="0x00000100"/>
+            </group>
+            <peripheral name="IWDT" start="0x40044400" size="0x00000100" info="Independent Watchdog Timer"/>
+            <group name="KINT" start="0x40080000" size="0x00000010" info="Key Interrupt Function">
+                <peripheral name="KINT0" start="0x40080000" size="0x00000010"/>
+            </group>
+            <peripheral name="MMF" start="0x40001000" size="0x00000020" info="Memory Mirror Function"/>
+            <group name="MPU" start="0x40000000" size="0x00001000" info="Memory Protection Unit">
+                <peripheral name="MPU0" start="0x40000000" size="0x00001000"/>
+            </group>
+            <peripheral name="MSTP" start="0x40047000" size="0x00000000" info="System-Module Stop"/>
+            <group name="OPAMP" start="0x40086800" size="0x00000100" info="Operational Amplifier">
+                <peripheral name="OPAMP0" start="0x40086800" size="0x00000100"/>
+                <peripheral name="OPAMP1" start="0x40086900" size="0x00000100"/>
+                <peripheral name="OPAMP2" start="0x40086a00" size="0x00000100"/>
+            </group>
+            <peripheral name="PFS" start="0x40040800" size="0x00000004" info="Pin Function Control Register"/>
+            <peripheral name="PMISC" start="0x40040d00" size="0x00000004" info="Miscellaneous Port Control Register"/>
+            <group name="PORT" start="0x40040000" size="0x00000020" info="I/O Ports">
+                <peripheral name="PORT0" start="0x40040000" size="0x00000020">
+                    <slot name="P000"/>
+                    <slot name="P001"/>
+                    <slot name="P002"/>
+                    <slot name="P003"/>
+                    <slot name="P012"/>
+                    <slot name="P013"/>
+                    <slot name="P014"/>
+                    <slot name="P015"/>
+                </peripheral>
+                <peripheral name="PORT1" start="0x40040020" size="0x00000020">
+                    <slot name="P100"/>
+                    <slot name="P101"/>
+                    <slot name="P102"/>
+                    <slot name="P103"/>
+                    <slot name="P104"/>
+                    <slot name="P105"/>
+                    <slot name="P106"/>
+                    <slot name="P107"/>
+                    <slot name="P108"/>
+                    <slot name="P109"/>
+                    <slot name="P110"/>
+                    <slot name="P111"/>
+                    <slot name="P112"/>
+                </peripheral>
+                <peripheral name="PORT2" start="0x40040040" size="0x00000020">
+                    <slot name="P200"/>
+                    <slot name="P201"/>
+                    <slot name="P204"/>
+                    <slot name="P205"/>
+                    <slot name="P206"/>
+                    <slot name="P212"/>
+                    <slot name="P213"/>
+                    <slot name="P214"/>
+                    <slot name="P215"/>
+                </peripheral>
+                <peripheral name="PORT3" start="0x40040060" size="0x00000020">
+                    <slot name="P300"/>
+                    <slot name="P301"/>
+                    <slot name="P302"/>
+                    <slot name="P303"/>
+                    <slot name="P304"/>
+                </peripheral>
+                <peripheral name="PORT4" start="0x40040080" size="0x00000020">
+                    <slot name="P400"/>
+                    <slot name="P401"/>
+                    <slot name="P402"/>
+                    <slot name="P403"/>
+                    <slot name="P407"/>
+                    <slot name="P408"/>
+                    <slot name="P409"/>
+                    <slot name="P410"/>
+                    <slot name="P411"/>
+                </peripheral>
+                <peripheral name="PORT5" start="0x400400a0" size="0x00000020">
+                    <slot name="P500"/>
+                    <slot name="P501"/>
+                    <slot name="P502"/>
+                </peripheral>
+                <peripheral name="PORT9" start="0x40040120" size="0x00000020">
+                    <slot name="P914"/>
+                    <slot name="P915"/>
+                </peripheral>
+            </group>
+            <peripheral name="RSIP" start="0x00000000" size="0x00000000" info="Renesas Secure IP"/>
+            <peripheral name="RTC" start="0x40044000" size="0x00000100" info="Realtime Clock"/>
+            <group name="SCI" start="0x40070000" size="0x00000020" info="Serial Communications Interface">
+                <peripheral name="SCI0" start="0x40070000" size="0x00000020"/>
+                <peripheral name="SCI1" start="0x40070020" size="0x00000020"/>
+                <peripheral name="SCI9" start="0x40070120" size="0x00000020"/>
+            </group>
+            <group name="SDADC" start="0x4009c000" size="0x00000000" info="Sigma Delta A/D Converter">
+                <peripheral name="SDADC0" start="0x4009c000" size="0x00000000"/>
+            </group>
+            <group name="SPI" start="0x40072000" size="0x00000100" info="Serial Peripheral Interface">
+                <peripheral name="SPI0" start="0x40072000" size="0x00000100"/>
+                <peripheral name="SPI1" start="0x40072100" size="0x00000100"/>
+            </group>
+            <peripheral name="SPMON" start="0x40000d00" size="0x00000100" info="CPU Stack Pointer Monitor"/>
+            <peripheral name="SRAM" start="0x40002000" size="0x00000008" info="SRAM Control"/>
+            <peripheral name="SYSTEM" start="0x4001e000" size="0x00001000" info="System Pins"/>
+            <peripheral name="TSN" start="0x407ec000" size="0x00000000" info="Temperature Sensor"/>
+            <group name="USB" start="0x40090000" size="0x00000800" info="USB 2.0 Module">
+                <peripheral name="USB0" start="0x40090000" size="0x00000800"/>
+            </group>
+            <peripheral name="USB_FS" start="0x40090000" size="0x00000800" info="USB Full Speed 2.0 Module"/>
+            <group name="WDT" start="0x40044200" size="0x00000100" info="Watchdog Timer">
+                <peripheral name="WDT0" start="0x40044200" size="0x00000100"/>
+            </group>
+        </peripherals>
+    </resources>
+</rzone>

bsp/renesas/ra2a1-ek/.secure_xml

@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="11">
+  <generalSettings>
+    <option key="#Board#" value="board.ra2a1_ek"/>
+    <option key="CPU" value="RA2A1"/>
+    <option key="Core" value="CM23"/>
+    <option key="#TargetName#" value="R7FA2A1AB3CFM"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m23"/>
+    <option key="#DeviceCommand#" value="R7FA2A1AB"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA2A1AB3CFM.pincfg"/>
+    <option key="#FSPVersion#" value="6.0.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra2a1_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
+  </generalSettings>
+  <raBspConfiguration/>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+    <node id="board.clock.sdadcclk.source" option="board.clock.sdadcclk.source.disabled"/>
+    <node id="board.clock.sdadcclk.div" option="board.clock.sdadcclk.div.12"/>
+    <node id="board.clock.sdadcclk.display" option="board.clock.sdadcclk.display.value"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+  </raClockConfiguration>
+  <raPinConfiguration>
+    <pincfg active="true" name="" symbol="">
+      <configSetting altId="adc0.an06.p003" configurationId="adc0.an06" peripheral="ADC0"/>
+      <configSetting altId="ctsu0.ts15.p001" configurationId="ctsu0.ts15" peripheral="CTSU0"/>
+      <configSetting altId="ctsu0.tscap.p409" configurationId="ctsu0.tscap" peripheral="CTSU0"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk" isUsedByDriver="true" peripheral="DEBUG0"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio" isUsedByDriver="true" peripheral="DEBUG0"/>
+      <configSetting altId="p201.input" configurationId="p201"/>
+      <configSetting altId="p205.output.low" configurationId="p205"/>
+      <configSetting altId="p206.input" configurationId="p206"/>
+      <configSetting altId="sci0.rxd.p301" configurationId="sci0.rxd" isUsedByDriver="true" peripheral="SCI0"/>
+      <configSetting altId="sci0.txd.p302" configurationId="sci0.txd" isUsedByDriver="true" peripheral="SCI0"/>
+      <configSetting altId="sci1.rxd.p411" configurationId="sci1.rxd" peripheral="SCI1"/>
+      <configSetting altId="sci1.txd.p410" configurationId="sci1.txd" peripheral="SCI1"/>
+      <configSetting altId="spi0.miso.p304" configurationId="spi0.miso" peripheral="SPI0"/>
+      <configSetting altId="spi0.mosi.p303" configurationId="spi0.mosi" peripheral="SPI0"/>
+      <configSetting altId="spi0.rspck.p111" configurationId="spi0.rspck" peripheral="SPI0"/>
+      <configSetting altId="spi0.ssl0.p112" configurationId="spi0.ssl0" peripheral="SPI0"/>
+      <configSetting altId="usbfs0.dm.p915" configurationId="usbfs0.dm" peripheral="USB_FS0"/>
+      <configSetting altId="usbfs0.dp.p914" configurationId="usbfs0.dp" peripheral="USB_FS0"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus" peripheral="USB_FS0"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>

bsp/renesas/ra2a1-ek/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

bsp/renesas/ra2a1-ek/Kconfig

@@ -0,0 +1,17 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+PKGS_DIR := packages
+
+ENV_DIR := /
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+source "$(BSP_DIR)/board/Kconfig"

bsp/renesas/ra2a1-ek/README.md

@@ -0,0 +1,177 @@
+# 瑞萨 EK-RA2A1 开发板
+
+## 简介
+
+本文档为瑞萨 EK-RA2A1 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+主要内容如下：
+
+- 开发板介绍
+- BSP 快速上手指南
+
+## 开发板介绍
+
+CPK-RA2L1 评估板可通过灵活配置软件包和 IDE，可帮助用户对RA2A1 MCU 群组的特性轻松进行评估，并对嵌入系统应用程序进行开发。
+
+开发板正面外观如下图：
+
+![EK-RA2A1 Evaluation Board](docs/picture/ek-ra2a1-evaluation-board_0.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：R7FA2L1AB2DFM，48MHz，Arm Cortex®-M23 内核，256kB 代码闪存, 32kB SRAM
+- 调试接口：板载 J-Link 接口
+- 扩展接口：两个 PMOD 连接器
+
+**更多详细资料及工具**
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+- 进阶使用
+
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+**硬件连接**
+
+使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。使用 USB 转串口工具连接 UART0：P302(TXD)、P301(RXD)。
+
+![PixPin_2025-08-17_23-14-53](docs/picture/PixPin_2025-08-17_23-14-53.png)
+
+**编译下载**
+
+- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
+
+> 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
+
+- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA2L1AB，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/ra6m4.hex 文件，点击 Program Device 按钮开始烧录。具体操作过程可参考下图步骤：
+
+![PixPin_2025-08-17_23-17-25](docs/picture/PixPin_2025-08-17_23-17-25.png)
+
+![PixPin_2025-08-17_23-18-20](docs/picture/PixPin_2025-08-17_23-18-20.png)
+
+选择hex文件,点击烧录
+
+![PixPin_2025-08-17_23-20-37](docs/picture/PixPin_2025-08-17_23-20-37.png)
+
+
+
+**查看运行结果**
+
+下载程序成功之后，系统会自动运行并打印系统信息。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.1 build Aug 17 2025 23:22:17
+ 2006 - 2024 Copyright by RT-Thread team
+
+Hello RT-Thread!
+msh >
+RT-Thread shell commands:
+pin              - pin [option]
+reboot           - Reboot System
+clear            - clear the terminal screen
+version          - show RT-Thread version information
+list             - list objects
+help             - RT-Thread shell help
+ps               - List threads in the system
+free             - Show the memory usage in the system
+backtrace        - print backtrace of a thread
+
+msh >
+
+
+```
+
+**应用入口函数**
+
+应用层的入口函数在 **bsp\ra2a1-ek\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
+
+```c
+#define LED_PIN    BSP_IO_PORT_02_PIN_05 /* Onboard LED pins */
+
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
+    while (1)
+    {   
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+```
+
+### 进阶使用
+
+**资料及文档**
+
+- [芯片官网主页](https://www.renesas.cn/zh/products/ra2a1)
+- [开发板官网主页](https://www.renesas.cn/zh/design-resources/boards-kits/ek-ra2a1?queryID=2377dd332697b5265bd3eca038979315)
+- [datasheet](https://www.renesas.com/en/document/dst/renesas-ra2a1-group-datasheet-0?r=1054141)
+
+**FSP 配置**
+
+需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 FSP 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
+
+1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 6.0.0 版本
+
+目前仓库 bsp 默认使能最小体量配置，用户可通过如下步骤使能 env 外设配置：
+
+**Keil使用方法**
+
+1. 在 bsp 目录下打开 env 工具，使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件，选择上方导航栏的 `Software Components`配置，打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮，该操作会自动查找当前电脑环境下安装的 fsp 版本，选择指定版本后进入 fsp。 
+    ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现，已经存在了一些已经配置完成的外设，此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+    ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env，使能所需的外设配置后保存退出即可。
+
+**GCC**
+
+1.fsp的使用，打开当前目录下的`configuration.xml`
+
+2.配置完外设之后点击`Generate Project Content`按钮即可生成所需驱动文件。
+
+**注意：重新生成配置需要把当前路径下的`bsp_linker_info.h`删掉**
+
+**ENV 配置**
+
+- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
+
+此 BSP 默认只开启了UART和IRQ3外设功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
+
+步骤如下：
+1. 在 bsp 下打开 env 工具。
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+3. 输入`pkgs --update`命令更新软件包。
+4. 输入`scons --target=mdk5` 命令重新生成工程。
+
+## FAQ
+
+### 使用 MDK 的 DEBUG 时如果遇到提示  “Error: Flash Download failed Cortex-M23” 怎么办？
+
+可按照下图操作，修改 Utilities 中的选项：
+
+![image-20211214102231248](docs/picture/readme_faq1.png) 
+
+## 联系人信息
+
+在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们  [RT-Thread 社区论坛](https://club.rt-thread.org/)
+
+## 贡献代码
+
+如果您对此BSP感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

bsp/renesas/ra2a1-ek/SConscript

@@ -0,0 +1,28 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+CPPPATH = []
+list = os.listdir(cwd)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    if GetOption('target') != 'mdk5':
+        src = Glob('./src/*.c')
+
+if rtconfig.PLATFORM in ['armclang']:
+    CPPPATH = [cwd + '/script/bsp_link/Keil']
+elif rtconfig.PLATFORM in ['gcc']:
+    CPPPATH = [cwd + '/script/bsp_link/GCC']
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+Return('group')

bsp/renesas/ra2a1-ek/SConstruct

@@ -0,0 +1,66 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+rtconfig.BSP_LIBRARY_TYPE = None
+
+def startup_check():
+    import subprocess
+    startup_check_path = os.getcwd() + "/../tools/startup_check.py"
+
+    if os.path.exists(startup_check_path):
+        try:
+            subprocess.call(["python", startup_check_path])
+        except:
+            subprocess.call(["python3", startup_check_path])
+
+RegisterPreBuildingAction(startup_check)
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/renesas/ra2a1-ek/board/Kconfig

@@ -0,0 +1,112 @@
+menu "Hardware Drivers Config"
+
+    config SOC_R7FA2A1AB
+        bool
+        select SOC_SERIES_R7FA2A1
+        select RT_USING_COMPONENTS_INIT
+        select RT_USING_USER_MAIN
+        default y
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+
+        rsource "../../libraries/HAL_Drivers/Kconfig"
+
+        menuconfig BSP_USING_UART
+            bool "Enable UART"
+            default y
+            select RT_USING_SERIAL
+            select RT_USING_SERIAL_V2
+            if BSP_USING_UART
+
+                menuconfig BSP_USING_UART0
+                    bool "Enable UART0"
+                    default n
+                    if BSP_USING_UART0
+                        config BSP_UART0_RX_USING_DMA
+                            bool "Enable UART0 RX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_TX_USING_DMA
+                            bool "Enable UART0 TX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_RX_BUFSIZE
+                            int "Set UART0 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART0_TX_BUFSIZE
+                            int "Set UART0 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+                
+                menuconfig BSP_USING_UART1
+                    bool "Enable UART1"
+                    default n
+                    if BSP_USING_UART1
+                        config BSP_UART1_RX_USING_DMA
+                            bool "Enable UART1 RX DMA"
+                            depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART1_TX_USING_DMA
+                            bool "Enable UART1 TX DMA"
+                            depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART1_RX_BUFSIZE
+                            int "Set UART1 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART1_TX_BUFSIZE
+                            int "Set UART1 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+                
+                menuconfig BSP_USING_UART9
+                    bool "Enable UART9"
+                    default n
+                    if BSP_USING_UART9
+                        config BSP_UART9_RX_USING_DMA
+                            bool "Enable UART9 RX DMA"
+                            depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART9_TX_USING_DMA
+                            bool "Enable UART9 TX DMA"
+                            depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART9_RX_BUFSIZE
+                            int "Set UART9 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART9_TX_BUFSIZE
+                            int "Set UART9 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+            endif
+
+    endmenu
+
+    menu "Board extended module Drivers"
+
+    endmenu
+endmenu

bsp/renesas/ra2a1-ek/board/SConscript

@@ -0,0 +1,16 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+CPPPATH = [cwd]
+src = Glob('*.c')
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/renesas/ra2a1-ek/board/board.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-10      Sherman      first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RA_SRAM_SIZE    32 /* The SRAM size of the chip needs to be modified */
+#define RA_SRAM_END     (0x20000000 + RA_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$__RAM_end$$ZI$$Base;
+#define HEAP_BEGIN  ((void *)&Image$$__RAM_end$$ZI$$Base)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __ddsc_RAM_END;
+#define HEAP_BEGIN      (&__ddsc_RAM_END)
+#endif
+
+#define HEAP_END        RA_SRAM_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/renesas/ra2a1-ek/board/ports/SConscript

@@ -0,0 +1,19 @@
+
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src = []
+
+CPPPATH = [cwd]
+LOCAL_CFLAGS = ''
+
+if rtconfig.PLATFORM in ['gcc', 'armclang']:
+    LOCAL_CFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM in ['armcc']:
+    LOCAL_CFLAGS += ' --c99'
+
+group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')

bsp/renesas/ra2a1-ek/board/ports/gpio_cfg.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-21     CYFS              first version
+ */
+
+/* Number of IRQ channels on the device */
+#define RA_IRQ_MAX  7
+
+/* PIN to IRQx table */
+#define PIN2IRQX_TABLE                      \
+{                                           \
+    switch (pin)                            \
+    {                                       \
+    case BSP_IO_PORT_04_PIN_00:             \
+    case BSP_IO_PORT_00_PIN_01:             \
+    case BSP_IO_PORT_02_PIN_05:             \
+        return 0;                           \
+    case BSP_IO_PORT_04_PIN_08:             \
+    case BSP_IO_PORT_04_PIN_07:             \
+    case BSP_IO_PORT_05_PIN_02:             \
+        return 1;                           \
+    case BSP_IO_PORT_01_PIN_10:             \
+    case BSP_IO_PORT_02_PIN_13:             \
+    case BSP_IO_PORT_05_PIN_01:             \
+        return 2;                           \
+    case BSP_IO_PORT_01_PIN_09:             \
+    case BSP_IO_PORT_02_PIN_12:             \
+    case BSP_IO_PORT_05_PIN_00:             \
+        return 3;                           \
+    case BSP_IO_PORT_00_PIN_00:             \
+    case BSP_IO_PORT_03_PIN_02:             \
+    case BSP_IO_PORT_01_PIN_00:             \
+        return 4;                           \
+    case BSP_IO_PORT_03_PIN_01:             \
+    case BSP_IO_PORT_04_PIN_01:             \
+    case BSP_IO_PORT_01_PIN_01:             \
+        return 5;                           \
+    case BSP_IO_PORT_02_PIN_06:             \
+    case BSP_IO_PORT_01_PIN_11:             \
+    case BSP_IO_PORT_01_PIN_04:             \
+        return 6;                           \
+    case BSP_IO_PORT_04_PIN_09:             \
+    case BSP_IO_PORT_01_PIN_12:             \
+    case BSP_IO_PORT_01_PIN_05:             \
+        return 7;                           \
+    default  :                              \
+        return -1;                          \
+    }                                       \
+}

bsp/renesas/ra2a1-ek/buildinfo.gpdsc

@@ -0,0 +1,183 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+  <vendor>Renesas</vendor>
+  <name>Project Content</name>
+  <description>Project content managed by the Renesas Smart Configurator</description>
+  <url/>
+  <releases>
+    <release version="1.0.0"/>
+  </releases>
+  <generators>
+    <generator id="Renesas RA Smart Configurator">
+      <project_files>
+        <file category="include" name="src/"/>
+        <file category="source" name="src/hal_entry.c"/>
+      </project_files>
+    </generator>
+  </generators>
+  <components generator="Renesas RA Smart Configurator">
+    <component Cclass="Flex Software" Cgroup="Components" Csub="ra">
+      <files>
+        <file category="include" name="ra/arm/CMSIS_6/CMSIS/Core/Include/"/>
+        <file category="include" name="ra/fsp/inc/"/>
+        <file category="include" name="ra/fsp/inc/api/"/>
+        <file category="include" name="ra/fsp/inc/instances/"/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h" path=""/>
+        <file category="other" name="ra/arm/CMSIS_6/LICENSE"/>
+        <file category="header" name="ra/board/ra2a1_ek/board.h" path=""/>
+        <file category="source" name="ra/board/ra2a1_ek/board_init.c"/>
+        <file category="header" name="ra/board/ra2a1_ek/board_init.h" path=""/>
+        <file category="source" name="ra/board/ra2a1_ek/board_leds.c"/>
+        <file category="header" name="ra/board/ra2a1_ek/board_leds.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/fsp_common_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_exceptions.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_ipc.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_ipc.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_ipc.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_macl.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_macl.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_macl.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mmf.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2a1/bsp_elc.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/ra2a1/bsp_linker.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/ra2a1/bsp_linker.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2a1/bsp_override.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2a1/bsp_peripheral.h" path=""/>
+        <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
+        <file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
+        <file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
+        <file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
+        <file category="other" name="ra/SConscript"/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Build Configuration">
+      <files>
+        <file category="include" name="ra_cfg/fsp_cfg/"/>
+        <file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_ofs_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
+        <file category="other" name="ra_cfg/SConscript"/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Generated Data">
+      <files>
+        <file category="include" name="ra_gen/"/>
+        <file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
+        <file category="source" name="ra_gen/common_data.c"/>
+        <file category="header" name="ra_gen/common_data.h" path=""/>
+        <file category="source" name="ra_gen/hal_data.c"/>
+        <file category="header" name="ra_gen/hal_data.h" path=""/>
+        <file category="source" name="ra_gen/main.c"/>
+        <file category="source" name="ra_gen/pin_data.c"/>
+        <file category="other" name="ra_gen/SConscript"/>
+        <file category="source" name="ra_gen/vector_data.c"/>
+        <file category="header" name="ra_gen/vector_data.h" path=""/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Linker Script">
+      <files>
+        <file category="linkerScript" name="script/fsp.scat"/>
+      </files>
+    </component>
+  </components>
+</package>

bsp/renesas/ra2a1-ek/configuration.xml

@@ -0,0 +1,312 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="11">
+  <generalSettings>
+    <option key="#Board#" value="board.ra2a1_ek"/>
+    <option key="CPU" value="RA2A1"/>
+    <option key="Core" value="CM23"/>
+    <option key="#TargetName#" value="R7FA2A1AB3CFM"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m23"/>
+    <option key="#DeviceCommand#" value="R7FA2A1AB"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA2A1AB3CFM.pincfg"/>
+    <option key="#FSPVersion#" value="6.0.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra2a1_ek##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra2a1.R7FA2A1AB3CFM">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+      <property id="config.bsp.number_of_cores" value="1"/>
+      <property id="config.bsp.irq_count_hidden" value="32"/>
+    </config>
+    <config id="config.bsp.ra2a1">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra2a1.fsp">
+      <property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.disabled"/>
+      <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="32000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="3333333"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
+      <property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="1"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="8000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="16000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.fsp.mcu.rtc.err_adjustment_value.max_value" value="63"/>
+    </config>
+    <config id="config.bsp.ra2a1.linker">
+      <property id="config.bsp.option_setting.ofs0" value="config.bsp.option_setting.ofs0.enabled"/>
+      <property id="config.bsp.option_setting.ofs0.iwdt_start_mode" value="config.bsp.option_setting.ofs0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.option_setting.ofs0.iwdt_timeout" value="config.bsp.option_setting.ofs0.iwdt_timeout.2048"/>
+      <property id="config.bsp.option_setting.ofs0.iwdt_divisor" value="config.bsp.option_setting.ofs0.iwdt_divisor.128"/>
+      <property id="config.bsp.option_setting.ofs0.iwdt_window_end" value="config.bsp.option_setting.ofs0.iwdt_window_end.0"/>
+      <property id="config.bsp.option_setting.ofs0.iwdt_window_start" value="config.bsp.option_setting.ofs0.iwdt_window_start.100"/>
+      <property id="config.bsp.option_setting.ofs0.iwdt_reset_interrupt" value="config.bsp.option_setting.ofs0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.option_setting.ofs0.iwdt_stop_control" value="config.bsp.option_setting.ofs0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.option_setting.ofs0.wdt_start_mode" value="config.bsp.option_setting.ofs0.wdt_start_mode.register"/>
+      <property id="config.bsp.option_setting.ofs0.wdt_timeout" value="config.bsp.option_setting.ofs0.wdt_timeout.16384"/>
+      <property id="config.bsp.option_setting.ofs0.wdt_divisor" value="config.bsp.option_setting.ofs0.wdt_divisor.128"/>
+      <property id="config.bsp.option_setting.ofs0.wdt_window_end" value="config.bsp.option_setting.ofs0.wdt_window_end.0"/>
+      <property id="config.bsp.option_setting.ofs0.wdt_window_start" value="config.bsp.option_setting.ofs0.wdt_window_start.100"/>
+      <property id="config.bsp.option_setting.ofs0.wdt_reset_interrupt" value="config.bsp.option_setting.ofs0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.option_setting.ofs0.wdt_stop_control" value="config.bsp.option_setting.ofs0.wdt_stop_control.stops"/>
+      <property id="config.bsp.option_setting.ofs1" value="config.bsp.option_setting.ofs1.enabled"/>
+      <property id="config.bsp.option_setting.ofs1.voltage_detection0.start" value="config.bsp.option_setting.ofs1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.option_setting.ofs1.voltage_detection0_level" value="config.bsp.option_setting.ofs1.voltage_detection0_level.190"/>
+      <property id="config.bsp.option_setting.ofs1.hoco_osc" value="config.bsp.option_setting.ofs1.hoco_osc.disabled"/>
+      <property id="config.bsp.option_setting.secmpu" value="config.bsp.option_setting.secmpu.disabled"/>
+      <property id="config.bsp.option_setting.secmpu.pc0.enable" value="config.bsp.option_setting.secmpu.pc0.enable.disabled"/>
+      <property id="config.bsp.option_setting.secmpu.pc0.start" value="0x0003FFFC"/>
+      <property id="config.bsp.option_setting.secmpu.pc0.end" value="0x0003FFFF"/>
+      <property id="config.bsp.option_setting.secmpu.pc1.enable" value="config.bsp.option_setting.secmpu.pc1.enable.disabled"/>
+      <property id="config.bsp.option_setting.secmpu.pc1.start" value="0x0003FFFC"/>
+      <property id="config.bsp.option_setting.secmpu.pc1.end" value="0x0003FFFF"/>
+      <property id="config.bsp.option_setting.secmpu.region0.enable" value="config.bsp.option_setting.secmpu.region0.enable.disabled"/>
+      <property id="config.bsp.option_setting.secmpu.region0.start" value="0x0003FFFC"/>
+      <property id="config.bsp.option_setting.secmpu.region0.end" value="0x0003FFFF"/>
+      <property id="config.bsp.option_setting.secmpu.region1.enable" value="config.bsp.option_setting.secmpu.region1.enable.disabled"/>
+      <property id="config.bsp.option_setting.secmpu.region1.start" value="0x20007FFC"/>
+      <property id="config.bsp.option_setting.secmpu.region1.end" value="0x20007FFF"/>
+      <property id="config.bsp.option_setting.secmpu.region2.enable" value="config.bsp.option_setting.secmpu.region2.enable.disabled"/>
+      <property id="config.bsp.option_setting.secmpu.region2.start" value="0x400DFFFC"/>
+      <property id="config.bsp.option_setting.secmpu.region2.end" value="0x400DFFFF"/>
+      <property id="config.bsp.option_setting.secmpu.region3.enable" value="config.bsp.option_setting.secmpu.region3.enable.disabled"/>
+      <property id="config.bsp.option_setting.secmpu.region3.start" value="0x400DFFFC"/>
+      <property id="config.bsp.option_setting.secmpu.region3.end" value="0x400DFFFF"/>
+      <property id="config.bsp.option_setting.secmpu.enable" value=""/>
+      <property id="config.bsp.option_setting.osis" value="config.bsp.option_setting.osis.disabled"/>
+      <property id="config.bsp.option_setting.osis.id_mode" value="config.bsp.option_setting.osis.id_mode.unlocked"/>
+      <property id="config.bsp.option_setting.osis.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
+      <property id="config.bsp.option_setting.osis.id_fixed.1" value=""/>
+      <property id="config.bsp.option_setting.osis.id_fixed.2" value=""/>
+      <property id="config.bsp.option_setting.osis.id_fixed.3" value=""/>
+      <property id="config.bsp.option_setting.osis.id_fixed.4" value=""/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x400"/>
+      <property id="config.bsp.common.heap" value="0"/>
+      <property id="config.bsp.common.bootloader.xip_enable" value="config.bsp.common.bootloader.xip_enable.disabled"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="12000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.fclk.div" option="board.clock.fclk.div.2"/>
+    <node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
+    <node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
+    <node id="board.clock.sdadcclk.source" option="board.clock.sdadcclk.source.disabled"/>
+    <node id="board.clock.sdadcclk.div" option="board.clock.sdadcclk.div.12"/>
+    <node id="board.clock.sdadcclk.display" option="board.clock.sdadcclk.display.value"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="6.0.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="6.0.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="Main" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.6.0.0">
+      <description>Arm CMSIS Version 6 - Core (M)</description>
+      <originalPack>Arm.CMSIS6.6.1.0+fsp.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="R7FA2A1AB3CFM" vendor="Renesas" version="6.0.0">
+      <description>Board support package for R7FA2A1AB3CFM</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="device" variant="" vendor="Renesas" version="6.0.0">
+      <description>Board support package for RA2A1</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="fsp" variant="" vendor="Renesas" version="6.0.0">
+      <description>Board support package for RA2A1 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="events" variant="" vendor="Renesas" version="6.0.0">
+      <description>Board support package for RA2A1 - Events</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2a1" subgroup="linker" variant="" vendor="Renesas" version="6.0.0">
+      <description>Board support package for RA2A1 - Linker</description>
+      <originalPack>Renesas.RA_mcu_ra2a1.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra2a1_ek" variant="" vendor="Renesas" version="6.0.0">
+      <description>RA2A1-EK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra2a1_ek.6.0.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="6.0.0">
+      <description>SCI UART</description>
+      <originalPack>Renesas.RA.6.0.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <module id="module.driver.uart_on_sci_uart.1578673258">
+      <property id="module.driver.uart.name" value="g_uart0"/>
+      <property id="module.driver.uart.channel" value="0"/>
+      <property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
+      <property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
+      <property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
+      <property id="module.driver.uart.baud" value="115200"/>
+      <property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
+      <property id="module.driver.uart.baudrate_max_err" value="5"/>
+      <property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
+      <property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
+      <property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
+      <property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
+      <property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
+      <property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
+      <property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
+      <property id="module.driver.uart.irda.ire" value="module.driver.uart.irda.ire.disabled"/>
+      <property id="module.driver.uart.irda.irrxinv" value="module.driver.uart.irda.irrxinv.disabled"/>
+      <property id="module.driver.uart.irda.irtxinv" value="module.driver.uart.irda.irtxinv.disabled"/>
+      <property id="module.driver.uart.rs485.de_enable" value="module.driver.uart.rs485.de_enable.disabled"/>
+      <property id="module.driver.uart.rs485.de_polarity" value="module.driver.uart.rs485.de_polarity.high"/>
+      <property id="module.driver.uart.rs485.de_port_number" value="module.driver.uart.rs485.de_port_number.PORT_DISABLE"/>
+      <property id="module.driver.uart.rs485.de_pin_number" value="module.driver.uart.rs485.de_pin_number.PIN_DISABLE"/>
+      <property id="module.driver.uart.callback" value="user_uart0_callback"/>
+      <property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority2"/>
+      <property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority2"/>
+      <property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority2"/>
+      <property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority2"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+      <stack module="module.driver.uart_on_sci_uart.1578673258"/>
+    </context>
+    <config id="config.driver.sci_uart">
+      <property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
+      <property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
+      <property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
+      <property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
+      <property id="config.driver.sci_uart.rs485" value="config.driver.sci_uart.rs485.disabled"/>
+      <property id="config.driver.sci_uart.irda" value="config.driver.sci_uart.irda.disabled"/>
+    </config>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <pincfg active="true" name="RA2A1-EK.pincfg" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc0.an06.p003" configurationId="adc0.an06"/>
+      <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
+      <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
+      <configSetting altId="ctsu0.ts15.p001" configurationId="ctsu0.ts15"/>
+      <configSetting altId="ctsu0.tscap.p409" configurationId="ctsu0.tscap"/>
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p001.ctsu0.ts15" configurationId="p001"/>
+      <configSetting altId="p001.gpio_mode.gpio_mode_peripheral" configurationId="p001.gpio_mode"/>
+      <configSetting altId="p003.adc0.an06" configurationId="p003"/>
+      <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p111.spi0.rspck" configurationId="p111"/>
+      <configSetting altId="p111.gpio_mode.gpio_mode_peripheral" configurationId="p111.gpio_mode"/>
+      <configSetting altId="p112.spi0.ssl0" configurationId="p112"/>
+      <configSetting altId="p112.gpio_mode.gpio_mode_peripheral" configurationId="p112.gpio_mode"/>
+      <configSetting altId="p201.input" configurationId="p201"/>
+      <configSetting altId="p201.gpio_mode.gpio_mode_in" configurationId="p201.gpio_mode"/>
+      <configSetting altId="p205.output.low" configurationId="p205"/>
+      <configSetting altId="p205.gpio_mode.gpio_mode_out.low" configurationId="p205.gpio_mode"/>
+      <configSetting altId="p206.input" configurationId="p206"/>
+      <configSetting altId="p206.gpio_irq.gpio_irq_enabled" configurationId="p206.gpio_irq"/>
+      <configSetting altId="p206.gpio_mode.gpio_mode_in" configurationId="p206.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p301.sci0.rxd" configurationId="p301"/>
+      <configSetting altId="p301.gpio_mode.gpio_mode_peripheral" configurationId="p301.gpio_mode"/>
+      <configSetting altId="p302.sci0.txd" configurationId="p302"/>
+      <configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/>
+      <configSetting altId="p303.spi0.mosi" configurationId="p303"/>
+      <configSetting altId="p303.gpio_mode.gpio_mode_peripheral" configurationId="p303.gpio_mode"/>
+      <configSetting altId="p304.spi0.miso" configurationId="p304"/>
+      <configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/>
+      <configSetting altId="p407.usbfs0.vbus" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p409.ctsu0.tscap" configurationId="p409"/>
+      <configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/>
+      <configSetting altId="p410.sci1.txd" configurationId="p410"/>
+      <configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/>
+      <configSetting altId="p411.sci1.rxd" configurationId="p411"/>
+      <configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
+      <configSetting altId="p914.usbfs0.dp" configurationId="p914"/>
+      <configSetting altId="p914.gpio_mode.gpio_mode_peripheral" configurationId="p914.gpio_mode"/>
+      <configSetting altId="p915.usbfs0.dm" configurationId="p915"/>
+      <configSetting altId="p915.gpio_mode.gpio_mode_peripheral" configurationId="p915.gpio_mode"/>
+      <configSetting altId="sci0.mode.asynchronous.free" configurationId="sci0.mode"/>
+      <configSetting altId="sci0.rxd.p301" configurationId="sci0.rxd"/>
+      <configSetting altId="sci0.txd.p302" configurationId="sci0.txd"/>
+      <configSetting altId="sci1.mode.asynchronous.free" configurationId="sci1.mode"/>
+      <configSetting altId="sci1.rxd.p411" configurationId="sci1.rxd"/>
+      <configSetting altId="sci1.txd.p410" configurationId="sci1.txd"/>
+      <configSetting altId="spi0.miso.p304" configurationId="spi0.miso"/>
+      <configSetting altId="spi0.mode.enabled.b" configurationId="spi0.mode"/>
+      <configSetting altId="spi0.mosi.p303" configurationId="spi0.mosi"/>
+      <configSetting altId="spi0.pairing.b" configurationId="spi0.pairing"/>
+      <configSetting altId="spi0.rspck.p111" configurationId="spi0.rspck"/>
+      <configSetting altId="spi0.ssl0.p112" configurationId="spi0.ssl0"/>
+      <configSetting altId="usbfs0.dm.p915" configurationId="usbfs0.dm"/>
+      <configSetting altId="usbfs0.dp.p914" configurationId="usbfs0.dp"/>
+      <configSetting altId="usbfs0.mode.device" configurationId="usbfs0.mode"/>
+      <configSetting altId="usbfs0.vbus.p407" configurationId="usbfs0.vbus"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA2A1AB3CFM.pincfg" selected="false" symbol="">
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>

bsp/renesas/ra2a1-ek/fsp_gen.scat

@@ -0,0 +1,323 @@
+LOAD_REGION_DATA_FLASH DATA_FLASH_START NOCOMPRESS DATA_FLASH_LENGTH
+{
+  __DATA_FLASH_start +0 EMPTY 0 {}
+  __DATA_FLASH_init +0 EMPTY 0 {}
+        
+  
+  __ddsc_DATA_FLASH_START +0 EMPTY 0 {}
+  .data_flash.startof +0 EMPTY 0
+  {
+  }
+  __RAM_start RAM_START +0 EMPTY 0 {}
+  
+  __ddsc_RAM_START +0 EMPTY 0 {}
+  .ram.startof +0 EMPTY 0
+  {
+  }
+
+  
+  __ram_dtc_vector +0 UNINIT
+  {
+  *(.bss.fsp_dtc_vector_table)
+  }
+
+  ; ram initialized from data_flash
+  __ram_from_data_flash +0
+  {
+  ; section.ram.from_data_flash
+  *(.ram_from_data_flash)
+  ; section.ram.code_from_data_flash
+  *(.ram_code_from_data_flash)
+  }
+        } ; create a root region after the RAM init ERs for remainder of ROM ERs
+         LOAD_REGION_DATA_FLASH_JUMP +0 NOCOMPRESS
+         {
+  
+  __data_flash_readonly +0 FIXED
+  {
+  ; section.data_flash.readonly
+  *(.data_flash)
+  ; section.data_flash.code
+  *(.data_flash_code)
+  }
+
+        
+  
+  __data_flash_noinit +0 FIXED UNINIT
+  {
+  ; section.data_flash.noinit
+  *(.bss.data_flash_noinit)
+  }
+
+        
+  
+  __ddsc_DATA_FLASH_END AlignExpr(+0, 512) EMPTY 0 {}
+  .data_flash.endof AlignExpr(+0, 512) EMPTY 0
+  {
+  }
+
+
+  __DATA_FLASH_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__DATA_FLASH_end) - LoadBase(__DATA_FLASH_start)) <= DATA_FLASH_LENGTH )
+}
+LOAD_REGION_FLASH_GAP FLASH_GAP_START NOCOMPRESS FLASH_GAP_LENGTH
+{
+  __FLASH_GAP_start +0 EMPTY 0 {}
+  __FLASH_GAP_init +0 EMPTY 0 {}
+        
+  
+  __ddsc_FLASH_START +0 EMPTY 0 {}
+  .flash.startof +0 EMPTY 0
+  {
+  }
+
+        
+  ; MCU vector table
+  _VECTORS +0 EMPTY 0 {}
+  __flash_gap_vectors +0 FIXED
+  {
+  *(.fixed_vectors, +FIRST)
+  *(.application_vectors)
+  }
+
+        
+  ; Sections that can be used to fill flash gap
+  __flash_gap_readonly_gap +0 FIXED
+  {
+  ; section.flash.readonly_gap
+    ; *bsp_linker.?*(.rodata.*)
+    *bsp_linker.?*(.rodata.*)
+  *(.flash_gap)
+  ; section.flash.code_gap
+    ; *startup.?*(.text.Reset_Handler)
+    *startup.?*(.text.Reset_Handler)
+    ; *system.?*(.text.*)
+    *system.?*(.text.*)
+  *(.flash_gap_code)
+  }
+
+  __FLASH_GAP_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__FLASH_GAP_end) - LoadBase(__FLASH_GAP_start)) <= FLASH_GAP_LENGTH )
+}
+LOAD_REGION_FLASH FLASH_START NOCOMPRESS FLASH_LENGTH
+{
+  __FLASH_start +0 EMPTY 0 {}
+  __FLASH_init +0 EMPTY 0 {}
+        
+  
+  __flash_noinit +0 FIXED UNINIT
+  {
+  ; section.flash.noinit
+  *(.bss.flash_noinit)
+  }
+  __ram_from_data_flash_jump ImageLimit(__ram_from_data_flash) EMPTY 0 {}
+  ; ram initialized from flash
+  __ram_from_flash +0
+  {
+  ; section.ram.from_flash
+  *(.ram_from_flash)
+  ; section.ram.code_from_flash
+  *(.ram_code_from_flash)
+  .ANY(+RW )
+  *(vtable)
+  }
+
+  ; Non-initialized ram
+  __ram_noinit +0 UNINIT
+  {
+  ; section.ram.noinit
+    ; *(.bss.g_heap)
+    ; In case this execution region becomes empty due to heap placement place dummy selector
+    $$.$$(.$$)
+  }
+    ARM_LIB_STACK +0 UNINIT EMPTY 0
+  {
+  }
+  ARM_LIB_HEAP +0 UNINIT
+  {
+    *(.bss.g_heap)
+  }
+  __post_heap +0 UNINIT
+  {
+    ; *(.bss.g_main_stack)
+    *(.bss.g_main_stack)
+  *(.bss.ram_noinit)
+  *(.bss.noinit)
+  }
+
+  ; Zeroed ram
+  __ram_zero +0
+  {
+  ; section.ram.zero
+  *(.bss.ram)
+  .ANY(+ZI )
+  }
+
+  ; Thread Stacks
+  __ram_thread_stack AlignExpr(+0, 8) UNINIT
+  {
+  *(.bss.stack?*)
+  }
+
+  
+  __ddsc_RAM_END AlignExpr(+0, 512) EMPTY 0 {}
+  .ram.endof AlignExpr(+0, 512) EMPTY 0
+  {
+  }
+
+  __RAM_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__RAM_end) - LoadBase(__RAM_start)) <= RAM_LENGTH )
+        } ; create a root region after the RAM init ERs for remainder of ROM ERs
+         LOAD_REGION_FLASH_JUMP +0 NOCOMPRESS
+         {
+  
+  __flash_readonly +0 FIXED
+  {
+  ; section.flash.readonly
+  *(.flash)
+  ; section.flash.code
+  *(.flash_code)
+  .ANY(+RO-CODE )
+  .ANY(+RO-DATA )
+  *(.mcuboot_sce9_key)
+  *(.version)
+  }
+
+        
+  
+  __init_array_start +0 EMPTY 0 {}
+  __flash_init_array +0 FIXED
+  {
+  *(.init_array.*)
+  *(.init_array)
+  }
+  __init_array_end +0 EMPTY 0 {}
+
+        
+  
+  __ddsc_FLASH_END AlignExpr(+0, 512) EMPTY 0 {}
+  .flash.endof AlignExpr(+0, 512) EMPTY 0
+  {
+  }
+
+  __FLASH_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__FLASH_end) - LoadBase(__FLASH_start)) <= FLASH_LENGTH )
+}
+LOAD_REGION_OPTION_SETTING_OFS0 OPTION_SETTING_OFS0_START NOCOMPRESS OPTION_SETTING_OFS0_LENGTH
+{
+  __OPTION_SETTING_OFS0_start +0 EMPTY 0 {}
+  __OPTION_SETTING_OFS0_init +0 EMPTY 0 {}
+        
+  
+  __ddsc_OPTION_SETTING_OFS0_START +0 EMPTY 0 {}
+  .option_setting_ofs0.startof +0 EMPTY 0
+  {
+  }
+
+        
+  ; Option Function Select Register 0
+  __option_setting_ofs0_reg +0 FIXED
+  {
+  *(.option_setting_ofs0)
+  }
+
+        
+  
+  __ddsc_OPTION_SETTING_OFS0_END +0 EMPTY 0 {}
+  .option_setting_ofs0.endof +0 EMPTY 0
+  {
+  }
+
+
+  __OPTION_SETTING_OFS0_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__OPTION_SETTING_OFS0_end) - LoadBase(__OPTION_SETTING_OFS0_start)) <= OPTION_SETTING_OFS0_LENGTH )
+}
+LOAD_REGION_OPTION_SETTING_OFS1 OPTION_SETTING_OFS1_START NOCOMPRESS OPTION_SETTING_OFS1_LENGTH
+{
+  __OPTION_SETTING_OFS1_start +0 EMPTY 0 {}
+  __OPTION_SETTING_OFS1_init +0 EMPTY 0 {}
+        
+  
+  __ddsc_OPTION_SETTING_OFS1_START +0 EMPTY 0 {}
+  .option_setting_ofs1.startof +0 EMPTY 0
+  {
+  }
+
+        
+  ; Option Function Select Register 1
+  __option_setting_ofs1_reg +0 FIXED
+  {
+  *(.option_setting_ofs1)
+  }
+
+        
+  
+  __ddsc_OPTION_SETTING_OFS1_END +0 EMPTY 0 {}
+  .option_setting_ofs1.endof +0 EMPTY 0
+  {
+  }
+
+
+  __OPTION_SETTING_OFS1_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__OPTION_SETTING_OFS1_end) - LoadBase(__OPTION_SETTING_OFS1_start)) <= OPTION_SETTING_OFS1_LENGTH )
+}
+LOAD_REGION_OPTION_SETTING_SECMPU OPTION_SETTING_SECMPU_START NOCOMPRESS OPTION_SETTING_SECMPU_LENGTH
+{
+  __OPTION_SETTING_SECMPU_start +0 EMPTY 0 {}
+  __OPTION_SETTING_SECMPU_init +0 EMPTY 0 {}
+        
+  
+  __ddsc_OPTION_SETTING_SECMPU_START +0 EMPTY 0 {}
+  .option_setting_secmpu.startof +0 EMPTY 0
+  {
+  }
+
+        
+  ; Security MPU Registers
+  __option_setting_secmpu_reg +0 FIXED
+  {
+  *(.option_setting_secmpu)
+  }
+
+        
+  
+  __ddsc_OPTION_SETTING_SECMPU_END +0 EMPTY 0 {}
+  .option_setting_secmpu.endof +0 EMPTY 0
+  {
+  }
+
+
+  __OPTION_SETTING_SECMPU_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__OPTION_SETTING_SECMPU_end) - LoadBase(__OPTION_SETTING_SECMPU_start)) <= OPTION_SETTING_SECMPU_LENGTH )
+}
+LOAD_REGION_OPTION_SETTING_OSIS OPTION_SETTING_OSIS_START NOCOMPRESS OPTION_SETTING_OSIS_LENGTH
+{
+  __OPTION_SETTING_OSIS_start +0 EMPTY 0 {}
+  __OPTION_SETTING_OSIS_init +0 EMPTY 0 {}
+        
+  
+  __ddsc_OPTION_SETTING_OSIS_START +0 EMPTY 0 {}
+  .option_setting_osis.startof +0 EMPTY 0
+  {
+  }
+
+        
+  ; OCD/Serial Programmer ID setting register
+  __option_setting_osis_reg +0 FIXED
+  {
+  *(.option_setting_osis)
+  }
+
+        
+  
+  __ddsc_OPTION_SETTING_OSIS_END +0 EMPTY 0 {}
+  .option_setting_osis.endof +0 EMPTY 0
+  {
+  }
+
+
+  __OPTION_SETTING_OSIS_end +0 EMPTY 0 {}
+  SCatterAssert( (LoadBase(__OPTION_SETTING_OSIS_end) - LoadBase(__OPTION_SETTING_OSIS_start)) <= OPTION_SETTING_OSIS_LENGTH )
+}
+
+

bsp/renesas/ra2a1-ek/memory_regions.scat

@@ -0,0 +1,17 @@
+  /* generated memory regions file - do not edit */
+  #define RAM_START 0x20000000
+  #define RAM_LENGTH 0x00008000
+  #define FLASH_START 0x00000440
+  #define FLASH_LENGTH 0x0003fbc0
+  #define DATA_FLASH_START 0x40100000
+  #define DATA_FLASH_LENGTH 0x00002000
+  #define OPTION_SETTING_OFS0_START 0x00000400
+  #define OPTION_SETTING_OFS0_LENGTH 0x00000004
+  #define OPTION_SETTING_OFS1_START 0x00000404
+  #define OPTION_SETTING_OFS1_LENGTH 0x00000004
+  #define OPTION_SETTING_SECMPU_START 0x00000408
+  #define OPTION_SETTING_SECMPU_LENGTH 0x00000034
+  #define OPTION_SETTING_OSIS_START 0x01010018
+  #define OPTION_SETTING_OSIS_LENGTH 0x00000020
+  #define FLASH_GAP_START 0x00000000
+  #define FLASH_GAP_LENGTH 0x00000400

bsp/renesas/ra2a1-ek/ra/SConscript

@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    if GetOption('target') != 'mdk5':
+        src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
+        src += Glob(cwd + '/fsp/src/bsp/mcu/ra2a1/*.c')
+        src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
+        src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
+        src += Glob(cwd + '/fsp/src/r_*/*.c')
+        CPPPATH = [ cwd + '/arm/CMSIS_6/CMSIS/Core/Include',
+                    cwd + '/fsp/inc',
+                    cwd + '/fsp/inc/api',
+                    cwd + '/fsp/inc/instances',]
+
+group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')

bsp/renesas/ra2a1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h

@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File
+ */
+
+#ifndef __CMSIS_ARMCLANG_A_H
+#define __CMSIS_ARMCLANG_A_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __CMSIS_ARMCLANG_H
+  #error "This file must not be included directly"
+#endif
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
+}
+
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+    uint32_t result;
+    if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
+    {
+        __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
+    }
+    else
+    {
+        result = __SXTB16(__ROR(op1, rotate));
+    }
+    return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
+{
+    uint32_t result;
+    if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
+    {
+        __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
+    }
+    else
+    {
+        result = __SXTAB16(op1, __ROR(op2, rotate));
+    }
+    return result;
+}
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return (result);
+}
+
+#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
+ /** @} end of group CMSIS_SIMD_intrinsics */
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+  __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %0 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : : "memory"
+   );
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %0 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
+   );
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/** @} end of CMSIS_Core_RegAccFunctions */
+
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    // Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    // Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    // Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    // Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    // Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+    // Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+  // Initialise FPSCR to a known state
+    "        VMRS    R1,FPSCR          \n"
+    "        LDR     R2,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R1,R1,R2          \n"
+    "        VMSR    FPSCR,R1            "
+    : : : "cc", "r1", "r2"
+  );
+}
+
+#endif /* __CMSIS_ARMCLANG_A_H */

bsp/renesas/ra2a1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h

@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2023-2024 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS-Core(A) Compiler LLVM/Clang Header File
+ */
+
+#ifndef __CMSIS_CLANG_A_H
+#define __CMSIS_CLANG_A_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __CMSIS_CLANG_H
+  #error "This file must not be included directly"
+#endif
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
+}
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+    uint32_t result;
+    if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
+    {
+        __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
+    }
+    else
+    {
+        result = __SXTB16(__ROR(op1, rotate));
+    }
+    return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
+{
+    uint32_t result;
+    if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
+    {
+        __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
+    }
+    else
+    {
+        result = __SXTAB16(op1, __ROR(op2, rotate));
+    }
+    return result;
+}
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return (result);
+}
+
+#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
+ /** @} end of group CMSIS_SIMD_intrinsics */
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+  __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %0 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : : "memory"
+   );
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %0 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
+   );
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/** @} end of CMSIS_Core_RegAccFunctions */
+
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  // Permit access to VFP/NEON, registers by modifying CPACR
+  const uint32_t cpacr = __get_CPACR();
+  __set_CPACR(cpacr | 0x00F00000ul);
+  __ISB();
+
+  // Enable VFP/NEON
+  const uint32_t fpexc = __get_FPEXC();
+  __set_FPEXC(fpexc | 0x40000000ul);
+
+  __ASM volatile(
+    // Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    // Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+    // Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+    : : : "cc", "r2"
+  );
+
+  // Initialise FPSCR to a known state
+  const uint32_t fpscr = __get_FPSCR();
+  __set_FPSCR(fpscr & 0x00086060ul);
+}
+
+/*@} end of group CMSIS_Core_intrinsics */
+
+#pragma clang diagnostic pop
+
+#endif /* __CMSIS_CLANG_A_H */

bsp/renesas/ra2a1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h

@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_A_H
+#define __CMSIS_GCC_A_H
+
+#ifndef __CMSIS_GCC_H
+  #error "This file must not be included directly"
+#endif
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+
+/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+  __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr = __get_CPSR();
+  uint32_t result;
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     %0, sp   " : "=r"(result) : : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr = __get_CPSR();
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     sp, %0   " : : "r" (topOfProcStack) : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  // Permit access to VFP/NEON, registers by modifying CPACR
+  const uint32_t cpacr = __get_CPACR();
+  __set_CPACR(cpacr | 0x00F00000ul);
+  __ISB();
+
+  // Enable VFP/NEON
+  const uint32_t fpexc = __get_FPEXC();
+  __set_FPEXC(fpexc | 0x40000000ul);
+
+  __ASM volatile(
+    // Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    // Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+    // Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+    : : : "cc", "r2"
+  );
+
+  // Initialise FPSCR to a known state
+  const uint32_t fpscr = __get_FPSCR();
+  __set_FPSCR(fpscr & 0x00086060ul);
+}
+
+/*@} end of group CMSIS_Core_intrinsics */
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_A_H */

bsp/renesas/ra2a1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h

@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2017-2020 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS-Core(A) Interrupt Controller API Header File
+ */
+
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#include <stdint.h>
+
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+/// Interrupt handler data type
+typedef void (*IRQHandler_t) (void);
+#endif
+
+#ifndef IRQN_ID_T
+#define IRQN_ID_T
+/// Interrupt ID number data type
+typedef int32_t IRQn_ID_t;
+#endif
+
+/* Interrupt mode bit-masks */
+#define IRQ_MODE_TRIG_Pos           (0U)
+#define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+#define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
+#define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
+
+#define IRQ_MODE_TYPE_Pos           (3U)
+#define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)
+#define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line
+#define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line
+
+#define IRQ_MODE_DOMAIN_Pos         (4U)
+#define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)
+#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain
+#define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain
+
+#define IRQ_MODE_CPU_Pos            (5U)
+#define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)
+#define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs
+#define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0
+#define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1
+#define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2
+#define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3
+#define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4
+#define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5
+#define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
+#define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
+
+// Encoding in some early GIC implementations
+#define IRQ_MODE_MODEL_Pos          (13U)
+#define IRQ_MODE_MODEL_Msk          (0x1UL << IRQ_MODE_MODEL_Pos)
+#define IRQ_MODE_MODEL_NN           (0x0UL << IRQ_MODE_MODEL_Pos)     ///< Corresponding interrupt is handled using the N-N model
+#define IRQ_MODE_MODEL_1N           (0x1UL << IRQ_MODE_MODEL_Pos)     ///< Corresponding interrupt is handled using the 1-N model
+
+#define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
+
+/* Interrupt priority bit-masks */
+#define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask
+#define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error
+
+/// Initialize interrupt controller.
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Initialize (void);
+
+/// Register interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     handler       interrupt handler function address
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
+
+/// Get the registered interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \return registered interrupt handler function address.
+IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
+
+/// Enable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Enable (IRQn_ID_t irqn);
+
+/// Disable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Disable (IRQn_ID_t irqn);
+
+/// Get interrupt enable state.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
+uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
+
+/// Configure interrupt request mode.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     mode          mode configuration
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
+
+/// Get interrupt mode configuration.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+uint32_t IRQ_GetMode (IRQn_ID_t irqn);
+
+/// Get ID number of current interrupt request (IRQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveIRQ (void);
+
+/// Get ID number of current fast interrupt request (FIQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveFIQ (void);
+
+/// Signal end of interrupt processing.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
+
+/// Set interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPending (IRQn_ID_t irqn);
+
+/// Get interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
+uint32_t IRQ_GetPending (IRQn_ID_t irqn);
+
+/// Clear interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_ClearPending (IRQn_ID_t irqn);
+
+/// Set interrupt priority value.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     priority      interrupt priority value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
+
+/// Get interrupt priority.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
+
+/// Set priority masking threshold.
+/// \param[in]     priority      priority masking threshold value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityMask (uint32_t priority);
+
+/// Get priority masking threshold
+/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityMask (void);
+
+/// Set priority grouping field split point
+/// \param[in]     bits          number of MSB bits included in the group priority field comparison
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
+
+/// Get priority grouping field split point
+/// \return current number of MSB bits included in the group priority field comparison with
+///         optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityGroupBits (void);
+
+#endif  // IRQ_CTRL_H_

bsp/renesas/ra2a1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS Compiler Generic Header File
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+/*
+ * TI Arm Clang Compiler (tiarmclang)
+ */
+#elif defined (__ti__)
+  #include "cmsis_tiarmclang.h"
+
+
+/*
+ * LLVM/Clang Compiler
+ */
+#elif defined ( __clang__ )
+  #include "cmsis_clang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #if __ARM_ARCH_PROFILE == 'A'
+    #include "a-profile/cmsis_iccarm_a.h"
+  #elif __ARM_ARCH_PROFILE == 'R'
+    #include "r-profile/cmsis_iccarm_r.h"
+  #elif __ARM_ARCH_PROFILE == 'M'
+    #include "m-profile/cmsis_iccarm_m.h"
+  #else
+    #error "Unknown Arm architecture profile"
+  #endif
+
+
+/*
+ * TI Arm Compiler (armcl)
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+  #ifndef __NO_INIT
+    #define __NO_INIT                              __attribute__ ((section (".noinit")))
+  #endif
+  #ifndef __ALIAS
+    #define __ALIAS(x)                             __attribute__ ((alias(x)))
+  #endif
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/renesas/ra2a1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2009-2023 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * CMSIS Core Version Definitions
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS-Core(M) Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 6U)                                    /*!< \brief [31:16] CMSIS-Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                    /*!< \brief [15:0]  CMSIS-Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )     /*!< \brief CMSIS Core(M) version number */
+
+/*  CMSIS-Core(A) Version definitions */
+#define __CA_CMSIS_VERSION_MAIN  ( 6U)                                    /*!< \brief [31:16] CMSIS-Core(A) main version */
+#define __CA_CMSIS_VERSION_SUB   ( 1U)                                    /*!< \brief [15:0]  CMSIS-Core(A) sub version */
+#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CA_CMSIS_VERSION_SUB          )      /*!< \brief CMSIS-Core(A) version number */
+
+#endif