From 882a0af94ed60e181b7d8a509b6d3675286e7305 Mon Sep 17 00:00:00 2001 From: Yaochenger <1516081466@qq.com> Date: Wed, 28 Dec 2022 14:06:39 +0800 Subject: [PATCH] =?UTF-8?q?[libcpu][riscv]=20=E6=B7=BB=E5=8A=A0=E5=AE=8F?= =?UTF-8?q?=E7=94=A8=E4=BA=8E=E5=8C=BA=E5=88=AB=E6=98=AF=E5=90=A6=E5=BC=80?= =?UTF-8?q?=E5=90=AFFPU=EF=BC=8C=E6=9B=B4=E6=96=B0ch32v208v-r0=20->ch32v20?= =?UTF-8?q?8w-r0=EF=BC=8C=E6=9B=B4=E6=96=B0=E6=B3=A8=E9=87=8A?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/wch/risc-v/Libraries/Kconfig | 1 + .../risc-v/{ch32v208v-r0 => ch32v208w-r0}/.config | 0 .../risc-v/{ch32v208v-r0 => ch32v208w-r0}/Kconfig | 0 .../{ch32v208v-r0 => ch32v208w-r0}/SConscript | 0 .../{ch32v208v-r0 => ch32v208w-r0}/SConstruct | 0 .../applications/SConscript | 0 .../applications/main.c | 0 .../{ch32v208v-r0 => ch32v208w-r0}/board/Kconfig | 0 .../{ch32v208v-r0 => ch32v208w-r0}/board/SConscript | 0 .../{ch32v208v-r0 => ch32v208w-r0}/board/board.c | 0 .../{ch32v208v-r0 => ch32v208w-r0}/board/board.h | 0 .../board/linker_scripts/link.lds | 0 .../figures/ch32v208.png | Bin .../figures/config.png | Bin .../{ch32v208v-r0 => ch32v208w-r0}/figures/dist.png | Bin .../{ch32v208v-r0 => ch32v208w-r0}/figures/end.png | Bin .../figures/import.png | Bin .../figures/prefix.png | Bin .../figures/scons.png | Bin .../figures/sconscompile.jpg | Bin .../{ch32v208v-r0 => ch32v208w-r0}/figures/set.png | Bin .../figures/success.png | Bin .../{ch32v208v-r0 => ch32v208w-r0}/figures/tool.png | Bin .../figures/toolchain.png | Bin .../figures/toolset.png | Bin .../figures/vscode-terminal.png | Bin .../figures/windows.png | Bin .../README_zh.md => ch32v208w-r0/readme.md} | 0 .../{ch32v208v-r0 => ch32v208w-r0}/rtconfig.h | 0 .../{ch32v208v-r0 => ch32v208w-r0}/rtconfig.py | 0 libcpu/risc-v/ch32/context_gcc.S | 1 + libcpu/risc-v/ch32/cpuport.c | 1 + libcpu/risc-v/ch32/interrupt_gcc.S | 1 + libcpu/risc-v/common/context_gcc.S | 6 +++++- 34 files changed, 9 insertions(+), 1 deletion(-) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/.config (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/Kconfig (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/SConscript (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/SConstruct (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/applications/SConscript (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/applications/main.c (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/board/Kconfig (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/board/SConscript (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/board/board.c (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/board/board.h (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/board/linker_scripts/link.lds (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/ch32v208.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/config.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/dist.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/end.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/import.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/prefix.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/scons.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/sconscompile.jpg (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/set.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/success.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/tool.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/toolchain.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/toolset.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/vscode-terminal.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/figures/windows.png (100%) rename bsp/wch/risc-v/{ch32v208v-r0/README_zh.md => ch32v208w-r0/readme.md} (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/rtconfig.h (100%) rename bsp/wch/risc-v/{ch32v208v-r0 => ch32v208w-r0}/rtconfig.py (100%) diff --git a/bsp/wch/risc-v/Libraries/Kconfig b/bsp/wch/risc-v/Libraries/Kconfig index 298f56a9aa..6dad90ac06 100644 --- a/bsp/wch/risc-v/Libraries/Kconfig +++ b/bsp/wch/risc-v/Libraries/Kconfig @@ -14,6 +14,7 @@ config SOC_RISCV_SERIES_CH32V2 config SOC_RISCV_SERIES_CH32V3 bool select ARCH_RISCV + select ARCH_RISCV_FPU select SOC_RISCV_FAMILY_CH32 config SOC_FAMILY_CH56X diff --git a/bsp/wch/risc-v/ch32v208v-r0/.config b/bsp/wch/risc-v/ch32v208w-r0/.config similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/.config rename to bsp/wch/risc-v/ch32v208w-r0/.config diff --git a/bsp/wch/risc-v/ch32v208v-r0/Kconfig b/bsp/wch/risc-v/ch32v208w-r0/Kconfig similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/Kconfig rename to bsp/wch/risc-v/ch32v208w-r0/Kconfig diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConscript b/bsp/wch/risc-v/ch32v208w-r0/SConscript similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/SConscript rename to bsp/wch/risc-v/ch32v208w-r0/SConscript diff --git a/bsp/wch/risc-v/ch32v208v-r0/SConstruct b/bsp/wch/risc-v/ch32v208w-r0/SConstruct similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/SConstruct rename to bsp/wch/risc-v/ch32v208w-r0/SConstruct diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/SConscript b/bsp/wch/risc-v/ch32v208w-r0/applications/SConscript similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/applications/SConscript rename to bsp/wch/risc-v/ch32v208w-r0/applications/SConscript diff --git a/bsp/wch/risc-v/ch32v208v-r0/applications/main.c b/bsp/wch/risc-v/ch32v208w-r0/applications/main.c similarity index 100% rename from bsp/wch/risc-v/ch32v208v-r0/applications/main.c rename to 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Notes * 2021-09-09 WCH the first version + * 2022-12-27 WangShun Merge WCH series mcu port files */ #include "cpuport.h" diff --git a/libcpu/risc-v/ch32/cpuport.c b/libcpu/risc-v/ch32/cpuport.c index e42bab949e..c1c609c58d 100644 --- a/libcpu/risc-v/ch32/cpuport.c +++ b/libcpu/risc-v/ch32/cpuport.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-09-09 WCH the first version + * 2022-12-27 WangShun Merge WCH series mcu port files */ #include diff --git a/libcpu/risc-v/ch32/interrupt_gcc.S b/libcpu/risc-v/ch32/interrupt_gcc.S index 96c61ddd33..4d16a5b054 100644 --- a/libcpu/risc-v/ch32/interrupt_gcc.S +++ b/libcpu/risc-v/ch32/interrupt_gcc.S @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-09-09 WCH the first version + * 2022-12-27 WangShun Merge WCH series mcu port files */ #include "cpuport.h" diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index e458268e11..dbb5f8f4b5 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -8,6 +8,7 @@ * 2018/10/28 Bernard The unify RISC-V porting implementation * 2018/12/27 Jesven Add SMP support * 2020/11/20 BalanceTWK Add FPU support + * 2022/12/28 WangShun Add macro to distinguish whether FPU is supported */ #define __ASSEMBLY__ @@ -212,8 +213,11 @@ rt_hw_context_switch_exit: csrw mepc, a0 LOAD x1, 1 * REGBYTES(sp) - + #ifdef ARCH_RISCV_FPU li t0, 0x00007800 + #else + li t0, 0x00001800 + #endif csrw mstatus, t0 LOAD a0, 2 * REGBYTES(sp) csrs mstatus, a0