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rename c906 FPU macro (#9290)

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1. 修改 ENABLE_FPU 为 ARCH_RISCV_FPU，与libcpu/common 保持统一
2. 对 bsp/cvitek/cv18xx_risc-v 中增加使能 ARCH_RISCV_FPU 的动作。解决了 issue #9075
This commit is contained in:
flyingcys
2024-08-27 00:46:41 -04:00
committed by GitHub
parent fd496e4cc4
commit 82f30aa54f
16 changed files with 463 additions and 227 deletions
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libcpu/risc-v/t-head/c906/cpuport.c
+1 -1
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@@ -76,7 +76,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
frame->user_sp_exc_stack = (rt_ubase_t)(((rt_ubase_t)stk) + sizeof(struct rt_hw_stack_frame));
/* force to supervisor mode(SPP=1) and set SPIE and SUM to 1 */
#ifdef ENABLE_FPU
#ifdef ARCH_RISCV_FPU
frame->sstatus = 0x00046120; /* enable FPU */
#else
frame->sstatus = 0x00040120;
libcpu/risc-v/t-head/c906/cpuport.h
+1 -1
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@@ -26,7 +26,7 @@
/* 33 general register */
#define CTX_GENERAL_REG_NR 33
#ifdef ENABLE_FPU
#ifdef ARCH_RISCV_FPU
/* 32 fpu register */
#define CTX_FPU_REG_NR 32
#else
libcpu/risc-v/t-head/c906/stack.h
+2 -1
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@@ -13,6 +13,7 @@
#define __STACK_H__
#include <rtthread.h>
struct rt_hw_stack_frame
{
rt_ubase_t epc; /* epc - epc - program counter */
@@ -48,7 +49,7 @@ struct rt_hw_stack_frame
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */
#ifdef ENABLE_FPU
#ifdef ARCH_RISCV_FPU
rt_ubase_t f[CTX_FPU_REG_NR]; /* f0~f31 */
#endif
};
libcpu/risc-v/t-head/c906/stackframe.h
+8 -8
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@@ -21,7 +21,7 @@
#include "cpuport.h"
#include "encoding.h"
#ifdef ENABLE_FPU
#ifdef ARCH_RISCV_FPU
#define FPU_CTX_F0_OFF 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */
#define FPU_CTX_F1_OFF 8 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */
#define FPU_CTX_F2_OFF 16 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */
@@ -54,7 +54,7 @@
#define FPU_CTX_F29_OFF 232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */
#define FPU_CTX_F30_OFF 240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */
#define FPU_CTX_F31_OFF 248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
#endif /* ENABLE_FPU */
#endif /* ARCH_RISCV_FPU */
/**
* The register `tp` always save/restore when context switch,
@@ -66,10 +66,10 @@
.macro SAVE_ALL
#ifdef ENABLE_FPU
#ifdef ARCH_RISCV_FPU
/* reserve float registers */
addi sp, sp, -CTX_FPU_REG_NR * REGBYTES
#endif /* ENABLE_FPU */
#endif /* ARCH_RISCV_FPU */
/* save general registers */
addi sp, sp, -CTX_GENERAL_REG_NR * REGBYTES
@@ -113,7 +113,7 @@
csrr t0, sscratch
STORE t0, 32 * REGBYTES(sp)
#ifdef ENABLE_FPU
#ifdef ARCH_RISCV_FPU
/* backup sp and adjust sp to save float registers */
mv t1, sp
addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES
@@ -160,13 +160,13 @@
li t0, SSTATUS_FS_CLEAN
csrs sstatus, t0
#endif /* ENABLE_FPU */
#endif /* ARCH_RISCV_FPU */
.endm
.macro RESTORE_ALL
#ifdef ENABLE_FPU
#ifdef ARCH_RISCV_FPU
/* restore float register */
mv t2, sp
addi t2, t2, CTX_GENERAL_REG_NR * REGBYTES /* skip all normal reg */
@@ -213,7 +213,7 @@
li t0, SSTATUS_FS_CLEAN
csrs sstatus, t0
#endif /* ENABLE_FPU */
#endif /* ARCH_RISCV_FPU */
/* restore general register */