mirror of
https://github.com/RT-Thread/rt-thread.git
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rm48: move some asm file to libcpu
This commit is contained in:
Grissiom
@@ -0,0 +1,255 @@
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/*
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* File : context_ccs.asm
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-20 Bernard first version
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* 2011-07-22 Bernard added thumb mode porting
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* 2013-05-24 Grissiom port to CCS
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* 2013-05-26 Grissiom optimize for ARMv7
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* 2013-10-20 Grissiom port to GCC
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*/
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#include <rtconfig.h>
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.text
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.arm
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_hw_trap_irq
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/*
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* rt_base_t rt_hw_interrupt_disable()
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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MRS r0, cpsr
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CPSID IF
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BX lr
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/*
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* void rt_hw_interrupt_enable(rt_base_t level)
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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MSR cpsr_c, r0
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BX lr
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
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* r0 --> from
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* r1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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STMDB sp!, {lr} @ push pc (lr should be pushed in place of PC)
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STMDB sp!, {r0-r12, lr} @ push lr & register file
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MRS r4, cpsr
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TST lr, #0x01
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ORRNE r4, r4, #0x20 @ it's thumb code
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STMDB sp!, {r4} @ push cpsr
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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VMRS r4, fpexc
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TST r4, #0x40000000
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BEQ __no_vfp_frame1
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VSTMDB sp!, {d0-d15}
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VMRS r5, fpscr
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@ TODO: add support for Common VFPv3.
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@ Save registers like FPINST, FPINST2
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STMDB sp!, {r5}
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__no_vfp_frame1:
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STMDB sp!, {r4}
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#endif
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STR sp, [r0] @ store sp in preempted tasks TCB
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LDR sp, [r1] @ get new task stack pointer
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} @ get fpexc
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VMSR fpexc, r0 @ restore fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame2
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LDMIA sp!, {r1} @ get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame2:
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#endif
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LDMIA sp!, {r4} @ pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
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/*
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* void rt_hw_context_switch_to(rt_uint32 to)
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* r0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LDR sp, [r0] @ get new task stack pointer
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} @ get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_to
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LDMIA sp!, {r1} @ get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_to:
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#endif
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LDMIA sp!, {r4} @ pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)@
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*/
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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LDR r2, =rt_thread_switch_interrupt_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 @ set rt_thread_switch_interrupt_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch:
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LDR r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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.globl IRQ_Handler
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IRQ_Handler:
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STMDB sp!, {r0-r12,lr}
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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VMRS r0, fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame_str_irq
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VSTMDB sp!, {d0-d15}
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VMRS r1, fpscr
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@ TODO: add support for Common VFPv3.
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@ Save registers like FPINST, FPINST2
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STMDB sp!, {r1}
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__no_vfp_frame_str_irq:
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STMDB sp!, {r0}
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#endif
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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@ if rt_thread_switch_interrupt_flag set, jump to
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@ rt_hw_context_switch_interrupt_do and don't return
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LDR r0, =rt_thread_switch_interrupt_flag
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LDR r1, [r0]
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CMP r1, #1
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BEQ rt_hw_context_switch_interrupt_do
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} @ get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_ldr_irq
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LDMIA sp!, {r1} @ get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_ldr_irq:
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#endif
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LDMIA sp!, {r0-r12,lr}
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SUBS pc, lr, #4
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/*
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* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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*/
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.globl rt_hw_context_switch_interrupt_do
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rt_hw_context_switch_interrupt_do:
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MOV r1, #0 @ clear flag
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STR r1, [r0]
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} @ get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do1
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LDMIA sp!, {r1} @ get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_do1:
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#endif
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LDMIA sp!, {r0-r12,lr} @ reload saved registers
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STMDB sp, {r0-r3} @ save r0-r3. We will restore r0-r3 in the SVC
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@ mode so there is no need to update SP.
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SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3.
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SUB r2, lr, #4 @ save old task's pc to r2
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MRS r3, spsr @ get cpsr of interrupt thread
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@ switch to SVC mode and no interrupt
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CPSID IF, #0x13
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STMDB sp!, {r2} @ push old task's pc
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STMDB sp!, {r4-r12,lr} @ push old task's lr,r12-r4
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LDMIA r1!, {r4-r7} @ restore r0-r3 of the interrupted thread
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STMDB sp!, {r4-r7} @ push old task's r3-r0. We don't need to push/pop them to
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@ r0-r3 because we just want to transfer the data and don't
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@ use them here.
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STMDB sp!, {r3} @ push old task's cpsr
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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VMRS r0, fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do2
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VSTMDB sp!, {d0-d15}
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VMRS r1, fpscr
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@ TODO: add support for Common VFPv3.
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@ Save registers like FPINST, FPINST2
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STMDB sp!, {r1}
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__no_vfp_frame_do2:
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STMDB sp!, {r0}
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#endif
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LDR r4, =rt_interrupt_from_thread
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LDR r5, [r4]
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STR sp, [r5] @ store sp in preempted tasks's TCB
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LDR r6, =rt_interrupt_to_thread
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LDR r6, [r6]
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LDR sp, [r6] @ get new task's stack pointer
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} @ get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do3
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LDMIA sp!, {r1} @ get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_do3:
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#endif
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LDMIA sp!, {r4} @ pop new task's cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,452 @@
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@-------------------------------------------------------------------------------
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@ sys_core.asm
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@
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@ (c) Texas Instruments 2009-2013, All rights reserved.
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@
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#include <rtconfig.h>
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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.equ UND_Stack_Size, 0x00000000
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.equ SVC_Stack_Size, 0x00000100
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.equ ABT_Stack_Size, 0x00000000
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.equ FIQ_Stack_Size, 0x00000000
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.equ IRQ_Stack_Size, 0x00000100
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.equ USR_Stack_Size, 0x00000100
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.section .bss.noinit
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/* stack */
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.globl stack_start
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.globl stack_top
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stack_start:
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.rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
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.long 0
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.endr
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stack_top:
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.section .text, "ax"
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.text
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.arm
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.globl _c_int00
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.globl _reset
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_reset:
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@-------------------------------------------------------------------------------
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@ Initialize CPU Registers
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@ After reset, the CPU is in the Supervisor mode (M = 10011)
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cpsid if, #19
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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@ Turn on FPV coprocessor
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mrc p15, #0x00, r2, c1, c0, #0x02
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orr r2, r2, #0xF00000
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mcr p15, #0x00, r2, c1, c0, #0x02
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fmrx r2, fpexc
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orr r2, r2, #0x40000000
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fmxr fpexc, r2
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#endif
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@-------------------------------------------------------------------------------
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@ Initialize Stack Pointers
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ldr r0, =stack_top
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@ Enter Undefined Instruction Mode and set its Stack Pointer
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msr cpsr_c, #Mode_UND|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #UND_Stack_Size
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@ Enter Abort Mode and set its Stack Pointer
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msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #ABT_Stack_Size
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@ Enter FIQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #FIQ_Stack_Size
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@ Enter IRQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #IRQ_Stack_Size
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@ Enter Supervisor Mode and set its Stack Pointer
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msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #SVC_Stack_Size
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@ Enter User Mode and set its Stack Pointer
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mov sp, r0
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sub sl, sp, #USR_Stack_Size
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bl next1
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next1:
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bl next2
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next2:
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bl next3
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next3:
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bl next4
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next4:
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ldr lr, =_c_int00
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bx lr
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.globl data_init
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data_init:
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/* copy .data to SRAM */
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ldr r1, =_sidata /* .data start in image */
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ldr r2, =_edata /* .data end in image */
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ldr r3, =_sdata /* sram data start */
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data_loop:
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ldr r0, [r1, #0]
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str r0, [r3]
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add r1, r1, #4
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add r3, r3, #4
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cmp r3, r2 /* check if data to clear */
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blo data_loop /* loop until done */
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
|
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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|
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r3, ip, lr}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r3, ip, lr}
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b ctor_loop
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ctor_end:
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bx lr
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|
||||
@-------------------------------------------------------------------------------
|
||||
@ Enable RAM ECC Support
|
||||
|
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.globl _coreEnableRamEcc_
|
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_coreEnableRamEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Disable RAM ECC Support
|
||||
|
||||
.globl _coreDisableRamEcc_
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_coreDisableRamEcc_:
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|
||||
stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
|
||||
bic r0, r0, #0x0C000000
|
||||
mcr p15, #0x00, r0, c1, c0, #0x01
|
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ldmfd sp!, {r0}
|
||||
bx lr
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||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Enable Flash ECC Support
|
||||
|
||||
.globl _coreEnableFlashEcc_
|
||||
_coreEnableFlashEcc_:
|
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|
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stmfd sp!, {r0}
|
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mrc p15, #0x00, r0, c1, c0, #0x01
|
||||
orr r0, r0, #0x02000000
|
||||
dmb
|
||||
mcr p15, #0x00, r0, c1, c0, #0x01
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Disable Flash ECC Support
|
||||
|
||||
.globl _coreDisableFlashEcc_
|
||||
_coreDisableFlashEcc_:
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mrc p15, #0x00, r0, c1, c0, #0x01
|
||||
bic r0, r0, #0x02000000
|
||||
mcr p15, #0x00, r0, c1, c0, #0x01
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Get data fault status register
|
||||
|
||||
.globl _coreGetDataFault_
|
||||
_coreGetDataFault_:
|
||||
|
||||
mrc p15, #0, r0, c5, c0, #0
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Clear data fault status register
|
||||
|
||||
.globl _coreClearDataFault_
|
||||
_coreClearDataFault_:
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Get instruction fault status register
|
||||
|
||||
.globl _coreGetInstructionFault_
|
||||
_coreGetInstructionFault_:
|
||||
|
||||
mrc p15, #0, r0, c5, c0, #1
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Clear instruction fault status register
|
||||
|
||||
.globl _coreClearInstructionFault_
|
||||
_coreClearInstructionFault_:
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c0, #1
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Get data fault address register
|
||||
|
||||
.globl _coreGetDataFaultAddress_
|
||||
_coreGetDataFaultAddress_:
|
||||
|
||||
mrc p15, #0, r0, c6, c0, #0
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Clear data fault address register
|
||||
|
||||
.globl _coreClearDataFaultAddress_
|
||||
_coreClearDataFaultAddress_:
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c0, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Get instruction fault address register
|
||||
|
||||
.globl _coreGetInstructionFaultAddress_
|
||||
_coreGetInstructionFaultAddress_:
|
||||
|
||||
mrc p15, #0, r0, c6, c0, #2
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Clear instruction fault address register
|
||||
|
||||
.globl _coreClearInstructionFaultAddress_
|
||||
_coreClearInstructionFaultAddress_:
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c6, c0, #2
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Get auxiliary data fault status register
|
||||
|
||||
.globl _coreGetAuxiliaryDataFault_
|
||||
_coreGetAuxiliaryDataFault_:
|
||||
|
||||
mrc p15, #0, r0, c5, c1, #0
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Clear auxiliary data fault status register
|
||||
|
||||
.globl _coreClearAuxiliaryDataFault_
|
||||
_coreClearAuxiliaryDataFault_:
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mcr p15, #0, r0, c5, c1, #0
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Get auxiliary instruction fault status register
|
||||
|
||||
.globl _coreGetAuxiliaryInstructionFault_
|
||||
_coreGetAuxiliaryInstructionFault_:
|
||||
|
||||
mrc p15, #0, r0, c5, c1, #1
|
||||
bx lr
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Clear auxiliary instruction fault status register
|
||||
|
||||
.globl _coreClearAuxiliaryInstructionFault_
|
||||
_coreClearAuxiliaryInstructionFault_:
|
||||
|
||||
stmfd sp!, {r0}
|
||||
mov r0, #0
|
||||
mrc p15, #0, r0, c5, c1, #1
|
||||
ldmfd sp!, {r0}
|
||||
bx lr
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Clear ESM CCM errorss
|
||||
|
||||
.globl _esmCcmErrorsClear_
|
||||
_esmCcmErrorsClear_:
|
||||
|
||||
stmfd sp!, {r0-r2}
|
||||
ldr r0, ESMSR1_REG @ load the ESMSR1 status register address
|
||||
ldr r2, ESMSR1_ERR_CLR
|
||||
str r2, [r0] @ clear the ESMSR1 register
|
||||
|
||||
ldr r0, ESMSR2_REG @ load the ESMSR2 status register address
|
||||
ldr r2, ESMSR2_ERR_CLR
|
||||
str r2, [r0] @ clear the ESMSR2 register
|
||||
|
||||
ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address
|
||||
ldr r2, ESMSSR2_ERR_CLR
|
||||
str r2, [r0] @ clear the ESMSSR2 register
|
||||
|
||||
ldr r0, ESMKEY_REG @ load the ESMKEY register address
|
||||
mov r2, #0x5 @ load R2 with 0x5
|
||||
str r2, [r0] @ clear the ESMKEY register
|
||||
|
||||
ldr r0, VIM_INTREQ @ load the INTREQ register address
|
||||
ldr r2, VIM_INT_CLR
|
||||
str r2, [r0] @ clear the INTREQ register
|
||||
ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address
|
||||
ldr r2, CCMR4_ERR_CLR
|
||||
str r2, [r0] @ clear the CCMR4 status register
|
||||
ldmfd sp!, {r0-r2}
|
||||
bx lr
|
||||
|
||||
ESMSR1_REG: .word 0xFFFFF518
|
||||
ESMSR2_REG: .word 0xFFFFF51C
|
||||
ESMSR3_REG: .word 0xFFFFF520
|
||||
ESMKEY_REG: .word 0xFFFFF538
|
||||
ESMSSR2_REG: .word 0xFFFFF53C
|
||||
CCMR4_STAT_REG: .word 0xFFFFF600
|
||||
ERR_CLR_WRD: .word 0xFFFFFFFF
|
||||
CCMR4_ERR_CLR: .word 0x00010000
|
||||
ESMSR1_ERR_CLR: .word 0x80000000
|
||||
ESMSR2_ERR_CLR: .word 0x00000004
|
||||
ESMSSR2_ERR_CLR: .word 0x00000004
|
||||
VIM_INT_CLR: .word 0x00000001
|
||||
VIM_INTREQ: .word 0xFFFFFE20
|
||||
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Work Around for Errata CORTEX-R4#57:
|
||||
@
|
||||
@ Errata Description:
|
||||
@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
|
||||
@ Workaround:
|
||||
@ Disable out-of-order single-precision floating point
|
||||
@ multiply-accumulate instruction completion
|
||||
|
||||
.globl _errata_CORTEXR4_57_
|
||||
_errata_CORTEXR4_57_:
|
||||
|
||||
push {r0}
|
||||
mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register
|
||||
orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS)
|
||||
mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register
|
||||
pop {r0}
|
||||
bx lr
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ Work Around for Errata CORTEX-R4#66:
|
||||
@
|
||||
@ Errata Description:
|
||||
@ Register Corruption During A Load-Multiple Instruction At
|
||||
@ an Exception Vector
|
||||
@ Workaround:
|
||||
@ Disable out-of-order completion for divide instructions in
|
||||
@ Auxiliary Control register
|
||||
|
||||
.globl _errata_CORTEXR4_66_
|
||||
_errata_CORTEXR4_66_:
|
||||
|
||||
push {r0}
|
||||
mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register
|
||||
orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
|
||||
@ for divide instructions.)
|
||||
mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
|
||||
pop {r0}
|
||||
bx lr
|
||||
|
||||
.globl turnon_VFP
|
||||
turnon_VFP:
|
||||
@ Enable FPV
|
||||
STMDB sp!, {r0}
|
||||
fmrx r0, fpexc
|
||||
orr r0, r0, #0x40000000
|
||||
fmxr fpexc, r0
|
||||
LDMIA sp!, {r0}
|
||||
subs pc, lr, #4
|
||||
|
||||
.globl _dabort
|
||||
_dabort:
|
||||
stmfd r13!, {r0 - r12, lr}
|
||||
ldmfd r13!, {r0 - r12, lr}
|
||||
subs pc, lr, #8
|
||||
@@ -0,0 +1,36 @@
|
||||
;-------------------------------------------------------------------------------
|
||||
; sys_intvecs.asm
|
||||
;
|
||||
; (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
;
|
||||
|
||||
.sect ".intvecs"
|
||||
.arm
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; import reference for interrupt routines
|
||||
|
||||
.ref _reset
|
||||
.ref _dabort
|
||||
.ref turnon_VFP
|
||||
.ref IRQ_Handler
|
||||
|
||||
.def resetEntry
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
; interrupt vectors
|
||||
|
||||
resetEntry
|
||||
b _reset
|
||||
b turnon_VFP
|
||||
svcEntry
|
||||
b svcEntry
|
||||
prefetchEntry
|
||||
b prefetchEntry
|
||||
b _dabort
|
||||
reservedEntry
|
||||
b reservedEntry
|
||||
b IRQ_Handler
|
||||
ldr pc,[pc,#-0x1b0]
|
||||
|
||||
;-------------------------------------------------------------------------------
|
||||
@@ -0,0 +1,31 @@
|
||||
@-------------------------------------------------------------------------------
|
||||
@ sys_intvecs.asm
|
||||
@
|
||||
@ (c) Texas Instruments 2009-2013, All rights reserved.
|
||||
@
|
||||
|
||||
.section .vectors, "ax"
|
||||
.code 32
|
||||
|
||||
@-------------------------------------------------------------------------------
|
||||
@ import reference for interrupt routines
|
||||
|
||||
.globl _reset
|
||||
.globl _dabort
|
||||
.globl turnon_VFP
|
||||
.globl IRQ_Handler
|
||||
|
||||
|
||||
.globl system_vectors
|
||||
system_vectors:
|
||||
b _reset
|
||||
b turnon_VFP
|
||||
svcEntry:
|
||||
b svcEntry
|
||||
prefetchEntry:
|
||||
b prefetchEntry
|
||||
b _dabort
|
||||
reservedEntry:
|
||||
b reservedEntry
|
||||
b IRQ_Handler
|
||||
ldr pc,[pc,#-0x1b0]
|
||||
Reference in New Issue
Block a user