From 80a4912baf79d46c696ab4a5c7da92fb511d8cd9 Mon Sep 17 00:00:00 2001 From: ZhangTao Date: Tue, 5 Nov 2019 10:30:47 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E4=BA=86=E4=B8=8A=E4=B8=8B?= =?UTF-8?q?=E6=96=87=E5=88=87=E6=8D=A2=E9=80=80=E5=87=BA=E6=97=B6=E7=9A=84?= =?UTF-8?q?bug=EF=BC=8C=E8=AF=A5bug=E4=BC=9A=E5=AF=BC=E8=87=B4=E4=B8=AD?= =?UTF-8?q?=E6=96=AD=E8=A2=AB=E6=8F=90=E5=89=8D=E6=89=93=E5=BC=80=E9=80=A0?= =?UTF-8?q?=E6=88=90=E6=AD=BB=E9=94=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/risc-v/common/context_gcc.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index f28b15319b..5c9f05c4e8 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -175,7 +175,7 @@ rt_hw_context_switch_exit: LOAD x1, 1 * REGBYTES(sp) li t0, 0x00001800 - csrs mstatus, t0 + csrw mstatus, t0 LOAD a0, 2 * REGBYTES(sp) csrs mstatus, a0