+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 ((q31_t)(0x100))
+#define DELTA_Q15 ((q15_t)0x5)
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macros for complex numbers
+ */
+
+ /* Dimension C vector space */
+ #define CMPLX_DIM 2
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief vector types
+ */
+#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI)
+ /**
+ * @brief 64-bit fractional 128-bit vector data type in 1.63 format
+ */
+ typedef int64x2_t q63x2_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector data type in 1.31 format.
+ */
+ typedef int32x4_t q31x4_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format.
+ */
+ typedef __ALIGNED(2) int16x8_t q15x8_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format.
+ */
+ typedef __ALIGNED(1) int8x16_t q7x16_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
+ */
+ typedef int32x4x2_t q31x4x2_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
+ */
+ typedef int32x4x4_t q31x4x4_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
+ */
+ typedef int16x8x2_t q15x8x2_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
+ */
+ typedef int16x8x4_t q15x8x4_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
+ */
+ typedef int8x16x2_t q7x16x2_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
+ */
+ typedef int8x16x4_t q7x16x4_t;
+
+ /**
+ * @brief 32-bit fractional data type in 9.23 format.
+ */
+ typedef int32_t q23_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector data type in 9.23 format.
+ */
+ typedef int32x4_t q23x4_t;
+
+ /**
+ * @brief 64-bit status 128-bit vector data type.
+ */
+ typedef int64x2_t status64x2_t;
+
+ /**
+ * @brief 32-bit status 128-bit vector data type.
+ */
+ typedef int32x4_t status32x4_t;
+
+ /**
+ * @brief 16-bit status 128-bit vector data type.
+ */
+ typedef int16x8_t status16x8_t;
+
+ /**
+ * @brief 8-bit status 128-bit vector data type.
+ */
+ typedef int8x16_t status8x16_t;
+
+
+#endif
+
+#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/
+ /**
+ * @brief 32-bit floating-point 128-bit vector type
+ */
+ typedef float32x4_t f32x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector data type
+ */
+ typedef __ALIGNED(2) float16x8_t f16x8_t;
+#endif
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector pair data type
+ */
+ typedef float32x4x2_t f32x4x2_t;
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector quadruplet data type
+ */
+ typedef float32x4x4_t f32x4x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector pair data type
+ */
+ typedef float16x8x2_t f16x8x2_t;
+
+ /**
+ * @brief 16-bit floating-point 128-bit vector quadruplet data type
+ */
+ typedef float16x8x4_t f16x8x4_t;
+#endif
+
+ /**
+ * @brief 32-bit ubiquitous 128-bit vector data type
+ */
+ typedef union _any32x4_t
+ {
+ float32x4_t f;
+ int32x4_t i;
+ } any32x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit ubiquitous 128-bit vector data type
+ */
+ typedef union _any16x8_t
+ {
+ float16x8_t f;
+ int16x8_t i;
+ } any16x8_t;
+#endif
+
+#endif
+
+#if defined(ARM_MATH_NEON)
+ /**
+ * @brief 32-bit fractional 64-bit vector data type in 1.31 format.
+ */
+ typedef int32x2_t q31x2_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector data type in 1.15 format.
+ */
+ typedef __ALIGNED(2) int16x4_t q15x4_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector data type in 1.7 format.
+ */
+ typedef __ALIGNED(1) int8x8_t q7x8_t;
+
+ /**
+ * @brief 32-bit float 64-bit vector data type.
+ */
+ typedef float32x2_t f32x2_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit float 64-bit vector data type.
+ */
+ typedef __ALIGNED(2) float16x4_t f16x4_t;
+#endif
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector triplet data type
+ */
+ typedef float32x4x3_t f32x4x3_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector triplet data type
+ */
+ typedef float16x8x3_t f16x8x3_t;
+#endif
+
+ /**
+ * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
+ */
+ typedef int32x4x3_t q31x4x3_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
+ */
+ typedef int16x8x3_t q15x8x3_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
+ */
+ typedef int8x16x3_t q7x16x3_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector pair data type
+ */
+ typedef float32x2x2_t f32x2x2_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector triplet data type
+ */
+ typedef float32x2x3_t f32x2x3_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector quadruplet data type
+ */
+ typedef float32x2x4_t f32x2x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 64-bit vector pair data type
+ */
+ typedef float16x4x2_t f16x4x2_t;
+
+ /**
+ * @brief 16-bit floating-point 64-bit vector triplet data type
+ */
+ typedef float16x4x3_t f16x4x3_t;
+
+ /**
+ * @brief 16-bit floating-point 64-bit vector quadruplet data type
+ */
+ typedef float16x4x4_t f16x4x4_t;
+#endif
+
+ /**
+ * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
+ */
+ typedef int32x2x2_t q31x2x2_t;
+
+ /**
+ * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
+ */
+ typedef int32x2x3_t q31x2x3_t;
+
+ /**
+ * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
+ */
+ typedef int32x4x3_t q31x2x4_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
+ */
+ typedef int16x4x2_t q15x4x2_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
+ */
+ typedef int16x4x2_t q15x4x3_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
+ */
+ typedef int16x4x3_t q15x4x4_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
+ */
+ typedef int8x8x2_t q7x8x2_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
+ */
+ typedef int8x8x3_t q7x8x3_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
+ */
+ typedef int8x8x4_t q7x8x4_t;
+
+ /**
+ * @brief 32-bit ubiquitous 64-bit vector data type
+ */
+ typedef union _any32x2_t
+ {
+ float32x2_t f;
+ int32x2_t i;
+ } any32x2_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit ubiquitous 64-bit vector data type
+ */
+ typedef union _any16x4_t
+ {
+ float16x4_t f;
+ int16x4_t i;
+ } any16x4_t;
+#endif
+
+ /**
+ * @brief 32-bit status 64-bit vector data type.
+ */
+ typedef int32x4_t status32x2_t;
+
+ /**
+ * @brief 16-bit status 64-bit vector data type.
+ */
+ typedef int16x8_t status16x4_t;
+
+ /**
+ * @brief 8-bit status 64-bit vector data type.
+ */
+ typedef int8x16_t status8x8_t;
+
+#endif
+
+
+
+/**
+ @brief definition to read/write two 16 bit values.
+ @deprecated
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __un(aligned) int32_t
+#elif defined(_MSC_VER )
+ #define __SIMD32_TYPE int32_t
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
+#define __SIMD64(addr) (*( int64_t **) & (addr))
+
+#define STEP(x) (x) <= 0 ? 0 : 1
+#define SQ(x) ((x) * (x))
+
+/* SIMD replacement */
+
+
+/**
+ @brief Read 2 Q15 from Q15 pointer.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2 (
+ q15_t * pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, pQ15, 4);
+#else
+ val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
+#endif
+
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_ia (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ15, 4);
+#else
+ val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
+#endif
+
+ *pQ15 += 2;
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_da (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ15, 4);
+#else
+ val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
+#endif
+
+ *pQ15 -= 2;
+ return (val);
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2_ia (
+ q15_t ** pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (*pQ15, &val, 4);
+#else
+ (*pQ15)[0] = (val & 0x0FFFF);
+ (*pQ15)[1] = (val >> 16) & 0x0FFFF;
+#endif
+
+ *pQ15 += 2;
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2 (
+ q15_t * pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (pQ15, &val, 4);
+#else
+ pQ15[0] = val & 0x0FFFF;
+ pQ15[1] = val >> 16;
+#endif
+}
+
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_ia (
+ q7_t ** pQ7)
+{
+ q31_t val;
+
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ7, 4);
+#else
+ val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
+#endif
+
+ *pQ7 += 4;
+
+ return (val);
+}
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_da (
+ q7_t ** pQ7)
+{
+ q31_t val;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ7, 4);
+#else
+ val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
+#endif
+ *pQ7 -= 4;
+
+ return (val);
+}
+
+/**
+ @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q7x4_ia (
+ q7_t ** pQ7,
+ q31_t value)
+{
+ q31_t val = value;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (*pQ7, &val, 4);
+#else
+ (*pQ7)[0] = val & 0x0FF;
+ (*pQ7)[1] = (val >> 8) & 0x0FF;
+ (*pQ7)[2] = (val >> 16) & 0x0FF;
+ (*pQ7)[3] = (val >> 24) & 0x0FF;
+
+#endif
+ *pQ7 += 4;
+}
+
+/*
+
+Normally those kind of definitions are in a compiler file
+in Core or Core_A.
+
+But for MSVC compiler it is a bit special. The goal is very specific
+to CMSIS-DSP and only to allow the use of this library from other
+systems like Python or Matlab.
+
+MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
+compiler file in Core or Core_A would not make sense.
+
+*/
+#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
+ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#ifndef ARM_MATH_DSP
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+ #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+#endif
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_FORCEINLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+ __STATIC_FORCEINLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y) ) );
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ const q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ const q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+/**
+ * @brief Integer exponentiation
+ * @param[in] x value
+ * @param[in] nb integer exponent >= 1
+ * @return x^nb
+ *
+ */
+__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb)
+{
+ float32_t r = x;
+ nb --;
+ while(nb > 0)
+ {
+ r = r * x;
+ nb--;
+ }
+ return(r);
+}
+
+/**
+ * @brief 64-bit to 32-bit unsigned normalization
+ * @param[in] in is input unsigned long long value
+ * @param[out] normalized is the 32-bit normalized value
+ * @param[out] norm is norm scale
+ */
+__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm)
+{
+ int32_t n1;
+ int32_t hi = (int32_t) (in >> 32);
+ int32_t lo = (int32_t) ((in << 32) >> 32);
+
+ n1 = __CLZ(hi) - 32;
+ if (!n1)
+ {
+ /*
+ * input fits in 32-bit
+ */
+ n1 = __CLZ(lo);
+ if (!n1)
+ {
+ /*
+ * MSB set, need to scale down by 1
+ */
+ *norm = -1;
+ *normalized = (((uint32_t) lo) >> 1);
+ } else
+ {
+ if (n1 == 32)
+ {
+ /*
+ * input is zero
+ */
+ *norm = 0;
+ *normalized = 0;
+ } else
+ {
+ /*
+ * 32-bit normalization
+ */
+ *norm = n1 - 1;
+ *normalized = lo << *norm;
+ }
+ }
+ } else
+ {
+ /*
+ * input fits in 64-bit
+ */
+ n1 = 1 - n1;
+ *norm = -n1;
+ /*
+ * 64 bit normalization
+ */
+ *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1));
+ }
+}
+
+__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den)
+{
+ q31_t result;
+ uint64_t absNum;
+ int32_t normalized;
+ int32_t norm;
+
+ /*
+ * if sum fits in 32bits
+ * avoid costly 64-bit division
+ */
+ absNum = num > 0 ? num : -num;
+ arm_norm_64_to_32u(absNum, &normalized, &norm);
+ if (norm > 0)
+ /*
+ * 32-bit division
+ */
+ result = (q31_t) num / den;
+ else
+ /*
+ * 64-bit division
+ */
+ result = (q31_t) (num / den);
+
+ return result;
+}
+
+
+/*
+ * @brief C custom defined intrinsic functions
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX
+ */
+ __STATIC_FORCEINLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD
+ */
+ __STATIC_FORCEINLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB
+ */
+ __STATIC_FORCEINLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA
+ */
+ __STATIC_FORCEINLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns either
+ * ARM_MATH_SUCCESS if initialization was successful or
+ * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ /**
+ * @brief Instance structure for the modified Biquad coefs required by vectorized code.
+ */
+ typedef struct
+ {
+ float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */
+ } arm_biquad_mod_coef_f32;
+#endif
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version).
+ * @param[in] pState points to the state buffer.
+ */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ void arm_biquad_cascade_df1_mve_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ arm_biquad_mod_coef_f32 * pCoeffsMod,
+ float32_t * pState);
+#endif
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u16(
+ const uint16_t * pSrc,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u32(
+ const uint32_t * pSrc,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u8(
+ const uint8_t * pSrc,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_BITONIC = 0,
+ /**< Bitonic sort */
+ ARM_SORT_BUBBLE = 1,
+ /**< Bubble sort */
+ ARM_SORT_HEAP = 2,
+ /**< Heap sort */
+ ARM_SORT_INSERTION = 3,
+ /**< Insertion sort */
+ ARM_SORT_QUICK = 4,
+ /**< Quick sort */
+ ARM_SORT_SELECTION = 5
+ /**< Selection sort */
+ } arm_sort_alg;
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_DESCENDING = 0,
+ /**< Descending order (9 to 0) */
+ ARM_SORT_ASCENDING = 1
+ /**< Ascending order (0 to 9) */
+ } arm_sort_dir;
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_alg alg; /**< Sorting algorithm selected */
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ } arm_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] alg Selected algorithm.
+ * @param[in] dir Sorting order.
+ */
+ void arm_sort_init_f32(
+ arm_sort_instance_f32 * S,
+ arm_sort_alg alg,
+ arm_sort_dir dir);
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ float32_t * buffer; /**< Working buffer */
+ } arm_merge_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in,out] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_merge_sort_f32(
+ const arm_merge_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t *pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] dir Sorting order.
+ * @param[in] buffer Working buffer.
+ */
+ void arm_merge_sort_init_f32(
+ arm_merge_sort_instance_f32 * S,
+ arm_sort_dir dir,
+ float32_t * buffer);
+
+ /**
+ * @brief Struct for specifying cubic spline type
+ */
+ typedef enum
+ {
+ ARM_SPLINE_NATURAL = 0, /**< Natural spline */
+ ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */
+ } arm_spline_type;
+
+ /**
+ * @brief Instance structure for the floating-point cubic spline interpolation.
+ */
+ typedef struct
+ {
+ arm_spline_type type; /**< Type (boundary conditions) */
+ const float32_t * x; /**< x values */
+ const float32_t * y; /**< y values */
+ uint32_t n_x; /**< Number of known data points */
+ float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */
+ } arm_spline_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point cubic spline interpolation.
+ * @param[in] S points to an instance of the floating-point spline structure.
+ * @param[in] xq points to the x values ot the interpolated data points.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples of output data.
+ */
+ void arm_spline_f32(
+ arm_spline_instance_f32 * S,
+ const float32_t * xq,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point cubic spline interpolation.
+ * @param[in,out] S points to an instance of the floating-point spline structure.
+ * @param[in] type type of cubic spline interpolation (boundary conditions)
+ * @param[in] x points to the x values of the known data points.
+ * @param[in] y points to the y values of the known data points.
+ * @param[in] n number of known data points.
+ * @param[in] coeffs coefficients array for b, c, and d
+ * @param[in] tempBuffer buffer array for internal computations
+ */
+ void arm_spline_init_f32(
+ arm_spline_instance_f32 * S,
+ arm_spline_type type,
+ const float32_t * x,
+ const float32_t * y,
+ uint32_t n,
+ float32_t * coeffs,
+ float32_t * tempBuffer);
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q15_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q15;
+
+arm_status arm_cfft_init_q15(
+ arm_cfft_instance_q15 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q31_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q31;
+
+arm_status arm_cfft_init_q31(
+ arm_cfft_instance_q31 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const float32_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_f32;
+
+
+ arm_status arm_cfft_init_f32(
+ arm_cfft_instance_f32 * S,
+ uint16_t fftLen);
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float64_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f64;
+
+ void arm_cfft_f64(
+ const arm_cfft_instance_f64 * S,
+ float64_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI)
+ arm_cfft_instance_q15 cfftInst;
+#else
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI)
+ arm_cfft_instance_q31 cfftInst;
+#else
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f64 ;
+
+arm_status arm_rfft_fast_init_f64 (
+ arm_rfft_fast_instance_f64 * S,
+ uint16_t fftLen);
+
+
+void arm_rfft_fast_f64(
+ arm_rfft_fast_instance_f64 * S,
+ float64_t * p, float64_t * pOut,
+ uint8_t ifftFlag);
+
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+
+ void arm_rfft_fast_f32(
+ const arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ const float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ const float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ const float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ const q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ const q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ const q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ const q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ const q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ const q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ const float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ const q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ const q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ const q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+/**
+ @brief Instance structure for floating-point FIR decimator.
+ */
+typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+/**
+ @brief Processing function for floating-point FIR decimator.
+ @param[in] S points to an instance of the floating-point FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ @brief Initialization function for the floating-point FIR decimator.
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+#if defined(ARM_MATH_NEON)
+void arm_biquad_cascade_df2T_compute_coefs_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs);
+#endif
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ const float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ @brief Correlation of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+ */
+void arm_correlate_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence.
+ @param[in] srcALen length of the first input sequence.
+ @param[in] pSrcB points to the second input sequence.
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ @brief Correlation of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return processed output sample.
+ */
+ __STATIC_FORCEINLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+/**
+ @brief Process function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+__STATIC_FORCEINLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+/**
+ @brief Process function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+__STATIC_FORCEINLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+/**
+ @brief Clarke transform for Q31 version
+ @param[in] Ia input three-phase coordinate a
+ @param[in] Ib input three-phase coordinate b
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+/**
+ @brief Inverse Clarke transform for Q31 version
+ @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ @param[in] Ibeta input two-phase orthogonal vector axis beta
+ @param[out] pIa points to output three-phase coordinate a
+ @param[out] pIb points to output three-phase coordinate b
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ __STATIC_FORCEINLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+/**
+ @brief Park transform for Q31 version
+ @param[in] Ialpha input two-phase vector coordinate alpha
+ @param[in] Ibeta input two-phase vector coordinate beta
+ @param[out] pId points to output rotor reference frame d
+ @param[out] pIq points to output rotor reference frame q
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+/**
+ @brief Inverse Park transform for Q31 version
+ @param[in] Id input coordinate of rotor reference frame d
+ @param[in] Iq input coordinate of rotor reference frame q
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ __STATIC_FORCEINLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= (S->nValues - 1))
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ __STATIC_FORCEINLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+/**
+ @brief Floating-point vector of log values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vlog_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ @brief Floating-point vector of exp values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vexp_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ @brief Floating-point square root function.
+ @param[in] in input value
+ @param[out] pOut square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ *pOut = __sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+/**
+ @brief Q31 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+/**
+ @brief Q15 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @brief Vector Floating-point square root function.
+ * @param[in] pIn input vector.
+ * @param[out] pOut vector of square roots of input elements.
+ * @param[in] len length of input vector.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ void arm_vsqrt_f32(
+ float32_t * pIn,
+ float32_t * pOut,
+ uint16_t len);
+
+ void arm_vsqrt_q31(
+ q31_t * pIn,
+ q31_t * pOut,
+ uint16_t len);
+
+ void arm_vsqrt_q15(
+ q15_t * pIn,
+ q15_t * pOut,
+ uint16_t len);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset;
+ int32_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q15_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q7_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ const q15_t * pSrcCmplx,
+ const q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ const q31_t * pSrcCmplx,
+ const q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ const float32_t * pSrcCmplx,
+ const float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_f32(
+ const float32_t *pSrc,
+ uint32_t blockSize,
+ float32_t *pResult);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ const q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ const q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ const q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ const q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ const q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ const q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Struct for specifying SVM Kernel
+ */
+typedef enum
+{
+ ARM_ML_KERNEL_LINEAR = 0,
+ /**< Linear kernel */
+ ARM_ML_KERNEL_POLYNOMIAL = 1,
+ /**< Polynomial kernel */
+ ARM_ML_KERNEL_RBF = 2,
+ /**< Radial Basis Function kernel */
+ ARM_ML_KERNEL_SIGMOID = 3
+ /**< Sigmoid kernel */
+} arm_ml_kernel_type;
+
+
+/**
+ * @brief Instance structure for linear SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+} arm_svm_linear_instance_f32;
+
+
+/**
+ * @brief Instance structure for polynomial SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ int32_t degree; /**< Polynomial degree */
+ float32_t coef0; /**< Polynomial constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_polynomial_instance_f32;
+
+/**
+ * @brief Instance structure for rbf SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_rbf_instance_f32;
+
+/**
+ * @brief Instance structure for sigmoid SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t coef0; /**< Independant constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_sigmoid_instance_f32;
+
+/**
+ * @brief SVM linear instance init function
+ * @param[in] S Parameters for SVM functions
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes);
+
+/**
+ * @brief SVM linear prediction
+ * @param[in] S Pointer to an instance of the linear SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+
+void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM polynomial instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] degree Polynomial degree
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ int32_t degree,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in] S Pointer to an instance of the polynomial SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM radial basis function instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult decision value
+ * @return none.
+ *
+ */
+void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+/**
+ * @brief SVM sigmoid instance init function
+ * @param[in] S points to an instance of the rbf SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+
+/**
+ * @brief Instance structure for Naive Gaussian Bayesian estimator.
+ */
+typedef struct
+{
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ uint32_t numberOfClasses; /**< Number of different classes */
+ const float32_t *theta; /**< Mean values for the Gaussians */
+ const float32_t *sigma; /**< Variances for the Gaussians */
+ const float32_t *classPriors; /**< Class prior probabilities */
+ float32_t epsilon; /**< Additive value to variances */
+} arm_gaussian_naive_bayes_instance_f32;
+
+/**
+ * @brief Naive Gaussian Bayesian Estimator
+ *
+ * @param[in] S points to a naive bayes instance structure
+ * @param[in] in points to the elements of the input vector.
+ * @param[in] pBuffer points to a buffer of length numberOfClasses
+ * @return The predicted class
+ *
+ */
+
+
+uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S,
+ const float32_t * in,
+ float32_t *pBuffer);
+
+/**
+ * @brief Computation of the LogSumExp
+ *
+ * In probabilistic computations, the dynamic of the probability values can be very
+ * wide because they come from gaussian functions.
+ * To avoid underflow and overflow issues, the values are represented by their log.
+ * In this representation, multiplying the original exp values is easy : their logs are added.
+ * But adding the original exp values is requiring some special handling and it is the
+ * goal of the LogSumExp function.
+ *
+ * If the values are x1...xn, the function is computing:
+ *
+ * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that
+ * rounding issues are minimised.
+ *
+ * The max xm of the values is extracted and the function is computing:
+ * xm + ln(exp(x1 - xm) + ... + exp(xn - xm))
+ *
+ * @param[in] *in Pointer to an array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return LogSumExp
+ *
+ */
+
+
+float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize);
+
+/**
+ * @brief Dot product with log arithmetic
+ *
+ * Vectors are containing the log of the samples
+ *
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[in] pTmpBuffer temporary buffer of length blockSize
+ * @return The log of the dot product .
+ *
+ */
+
+
+float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t *pTmpBuffer);
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize);
+
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float32_t arm_kullback_leibler_f32(const float32_t * pSrcA
+ ,const float32_t * pSrcB
+ ,uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float64_t arm_kullback_leibler_f64(const float64_t * pSrcA,
+ const float64_t * pSrcB,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Weighted sum
+ *
+ *
+ * @param[in] *in Array of input values.
+ * @param[in] *weigths Weights
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Weighted sum
+ *
+ */
+float32_t arm_weighted_sum_f32(const float32_t *in
+ , const float32_t *weigths
+ , uint32_t blockSize);
+
+
+/**
+ * @brief Barycenter
+ *
+ *
+ * @param[in] in List of vectors
+ * @param[in] weights Weights of the vectors
+ * @param[out] out Barycenter
+ * @param[in] nbVectors Number of vectors
+ * @param[in] vecDim Dimension of space (vector dimension)
+ * @return None
+ *
+ */
+void arm_barycenter_f32(const float32_t *in
+ , const float32_t *weights
+ , float32_t *out
+ , uint32_t nbVectors
+ , uint32_t vecDim);
+
+/**
+ * @brief Euclidean distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Bray-Curtis distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Canberra distance between two vectors
+ *
+ * This function may divide by zero when samples pA[i] and pB[i] are both zero.
+ * The result of the computation will be correct. So the division per zero may be
+ * ignored.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Chebyshev distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Cityblock (Manhattan) distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Correlation distance between two vectors
+ *
+ * The input vectors are modified in place !
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cosine distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Jensen-Shannon distance between two vectors
+ *
+ * This function is assuming that elements of second vector are > 0
+ * and 0 only when the corresponding element of first vector is 0.
+ * Otherwise the result of the computation does not make sense
+ * and for speed reasons, the cases returning NaN or Infinity are not
+ * managed.
+ *
+ * When the function is computing x log (x / y) with x 0 and y 0,
+ * it will compute the right value (0) but a division per zero will occur
+ * and shoudl be ignored in client code.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
+
+/**
+ * @brief Minkowski distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] n Norm order (>= 2)
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+
+
+float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
+
+/**
+ * @brief Dice distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] order Distance order
+ * @param[in] blockSize Number of samples
+ * @return distance
+ *
+ */
+
+
+float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Hamming distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Jaccard distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Kulsinski distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Roger Stanimoto distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Russell-Rao distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Michener distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Sneath distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Yule distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex ) + (yIndex ) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex ) + (yIndex+1) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0x0FFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+#endif
+
+
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#elif defined ( _MSC_VER )
+
+#else
+ #error Unknown compiler
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/arm_mve_tables.h b/bsp/tae32f5300/Libraries/CMSIS/Include/arm_mve_tables.h
new file mode 100644
index 0000000000..4d2c135ac6
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/arm_mve_tables.h
@@ -0,0 +1,235 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mve_tables.h
+ * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
+ * used for MVE implementation only
+ *
+ * $Date: 08. January 2020
+ * $Revision: V1.7.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ #ifndef _ARM_MVE_TABLES_H
+ #define _ARM_MVE_TABLES_H
+
+ #include "arm_math.h"
+
+
+
+
+
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
+extern float32_t rearranged_twiddle_stride1_16_f32[8];
+extern float32_t rearranged_twiddle_stride2_16_f32[8];
+extern float32_t rearranged_twiddle_stride3_16_f32[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
+extern float32_t rearranged_twiddle_stride1_64_f32[40];
+extern float32_t rearranged_twiddle_stride2_64_f32[40];
+extern float32_t rearranged_twiddle_stride3_64_f32[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
+extern float32_t rearranged_twiddle_stride1_256_f32[168];
+extern float32_t rearranged_twiddle_stride2_256_f32[168];
+extern float32_t rearranged_twiddle_stride3_256_f32[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
+extern float32_t rearranged_twiddle_stride1_1024_f32[680];
+extern float32_t rearranged_twiddle_stride2_1024_f32[680];
+extern float32_t rearranged_twiddle_stride3_1024_f32[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
+extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
+extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
+extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
+extern q31_t rearranged_twiddle_stride1_16_q31[8];
+extern q31_t rearranged_twiddle_stride2_16_q31[8];
+extern q31_t rearranged_twiddle_stride3_16_q31[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
+extern q31_t rearranged_twiddle_stride1_64_q31[40];
+extern q31_t rearranged_twiddle_stride2_64_q31[40];
+extern q31_t rearranged_twiddle_stride3_64_q31[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
+extern q31_t rearranged_twiddle_stride1_256_q31[168];
+extern q31_t rearranged_twiddle_stride2_256_q31[168];
+extern q31_t rearranged_twiddle_stride3_256_q31[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
+extern q31_t rearranged_twiddle_stride1_1024_q31[680];
+extern q31_t rearranged_twiddle_stride2_1024_q31[680];
+extern q31_t rearranged_twiddle_stride3_1024_q31[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
+extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
+extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
+extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
+extern q15_t rearranged_twiddle_stride1_16_q15[8];
+extern q15_t rearranged_twiddle_stride2_16_q15[8];
+extern q15_t rearranged_twiddle_stride3_16_q15[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
+extern q15_t rearranged_twiddle_stride1_64_q15[40];
+extern q15_t rearranged_twiddle_stride2_64_q15[40];
+extern q15_t rearranged_twiddle_stride3_64_q15[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
+extern q15_t rearranged_twiddle_stride1_256_q15[168];
+extern q15_t rearranged_twiddle_stride2_256_q15[168];
+extern q15_t rearranged_twiddle_stride3_256_q15[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
+extern q15_t rearranged_twiddle_stride1_1024_q15[680];
+extern q15_t rearranged_twiddle_stride2_1024_q15[680];
+extern q15_t rearranged_twiddle_stride3_1024_q15[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
+extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
+extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
+extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#endif /*_ARM_MVE_TABLES_H*/
+
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/arm_vec_math.h b/bsp/tae32f5300/Libraries/CMSIS/Include/arm_vec_math.h
new file mode 100644
index 0000000000..0ce9464bcb
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/arm_vec_math.h
@@ -0,0 +1,372 @@
+/******************************************************************************
+ * @file arm_vec_math.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.7.0
+ * @date 15. October 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_VEC_MATH_H
+#define _ARM_VEC_MATH_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_helium_utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#define INV_NEWTON_INIT_F32 0x7EF127EA
+
+static const float32_t __logf_rng_f32=0.693147180f;
+
+
+/* fast inverse approximation (3x newton) */
+__STATIC_INLINE f32x4_t vrecip_medprec_f32(
+ f32x4_t x)
+{
+ q31x4_t m;
+ f32x4_t b;
+ any32x4_t xinv;
+ f32x4_t ax = vabsq(x);
+
+ xinv.f = ax;
+ m = 0x3F800000 - (xinv.i & 0x7F800000);
+ xinv.i = xinv.i + m;
+ xinv.f = 1.41176471f - 0.47058824f * xinv.f;
+ xinv.i = xinv.i + m;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
+ /*
+ * restore sign
+ */
+ xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
+
+ return xinv.f;
+}
+
+/* fast inverse approximation (4x newton) */
+__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
+ f32x4_t x)
+{
+ q31x4_t m;
+ f32x4_t b;
+ any32x4_t xinv;
+ f32x4_t ax = vabsq(x);
+
+ xinv.f = ax;
+
+ m = 0x3F800000 - (xinv.i & 0x7F800000);
+ xinv.i = xinv.i + m;
+ xinv.f = 1.41176471f - 0.47058824f * xinv.f;
+ xinv.i = xinv.i + m;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
+ /*
+ * restore sign
+ */
+ xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
+
+ return xinv.f;
+}
+
+__STATIC_INLINE f32x4_t vdiv_f32(
+ f32x4_t num, f32x4_t den)
+{
+ return vmulq(num, vrecip_hiprec_f32(den));
+}
+
+/**
+ @brief Single-precision taylor dev.
+ @param[in] x f32 quad vector input
+ @param[in] coeffs f32 quad vector coeffs
+ @return destination f32 quad vector
+ */
+
+__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
+ f32x4_t x,
+ const float32_t * coeffs)
+{
+ f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
+ f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
+ f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
+ f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
+ f32x4_t x2 = vmulq(x, x);
+ f32x4_t x4 = vmulq(x2, x2);
+ f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
+
+ return res;
+}
+
+__STATIC_INLINE f32x4_t vmant_exp_f32(
+ f32x4_t x,
+ int32x4_t * e)
+{
+ any32x4_t r;
+ int32x4_t n;
+
+ r.f = x;
+ n = r.i >> 23;
+ n = n - 127;
+ r.i = r.i - (n << 23);
+
+ *e = n;
+ return r.f;
+}
+
+
+__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
+{
+ q31x4_t vecExpUnBiased;
+ f32x4_t vecTmpFlt0, vecTmpFlt1;
+ f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
+ f32x4_t vecExpUnBiasedFlt;
+
+ /*
+ * extract exponent
+ */
+ vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
+
+ vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
+ /*
+ * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
+ */
+ vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
+ vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
+ /*
+ * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
+ */
+ vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
+ vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
+ /*
+ * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
+ */
+ vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
+ vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
+ /*
+ * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
+ */
+ vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
+ vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
+ /*
+ * a = a + b * xx;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
+ /*
+ * c = c + d * xx;
+ */
+ vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
+ /*
+ * xx = xx * xx;
+ */
+ vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
+ vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
+ /*
+ * r.f = a + c * xx;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
+ /*
+ * add exponent
+ * r.f = r.f + ((float32_t) m) * __logf_rng_f32;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
+ // set log0 down to -inf
+ vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
+ return vecAcc0;
+}
+
+__STATIC_INLINE f32x4_t vexpq_f32(
+ f32x4_t x)
+{
+ // Perform range reduction [-log(2),log(2)]
+ int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
+ f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
+
+ // Polynomial Approximation
+ f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
+
+ // Reconstruct
+ poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
+
+ poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
+ return poly;
+}
+
+__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
+{
+ f32x4_t r = x;
+ nb--;
+ while (nb > 0) {
+ r = vmulq(r, x);
+ nb--;
+ }
+ return (r);
+}
+
+__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
+{
+ f32x4_t vecSx, vecW, vecTmp;
+ any32x4_t v;
+
+ vecSx = vabsq(vecIn);
+
+ v.f = vecIn;
+ v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
+
+ vecW = vmulq(vecSx, v.f);
+
+ // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
+ vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
+ vecTmp = vfmasq(vecW, vecTmp, -28.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 56.0f);
+ vecTmp = vfmasq(vecW, vecTmp, -70.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 56.0f);
+ vecTmp = vfmasq(vecW, vecTmp, -28.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 8.0f);
+ v.f = vmulq(v.f, vecTmp);
+
+ v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
+ /*
+ * restore sign
+ */
+ v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
+ return v.f;
+}
+
+__STATIC_INLINE f32x4_t vtanhq_f32(
+ f32x4_t val)
+{
+ f32x4_t x =
+ vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
+ f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
+ f32x4_t num = vsubq_n_f32(exp2x, 1.f);
+ f32x4_t den = vaddq_n_f32(exp2x, 1.f);
+ f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
+ return tanh;
+}
+
+__STATIC_INLINE f32x4_t vpowq_f32(
+ f32x4_t val,
+ f32x4_t n)
+{
+ return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
+}
+
+#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
+
+#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
+#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
+
+#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#include "NEMath.h"
+/**
+ * @brief Vectorized integer exponentiation
+ * @param[in] x value
+ * @param[in] nb integer exponent >= 1
+ * @return x^nb
+ *
+ */
+__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
+{
+ float32x4_t r = x;
+ nb --;
+ while(nb > 0)
+ {
+ r = vmulq_f32(r , x);
+ nb--;
+ }
+ return(r);
+}
+
+
+__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
+{
+ float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
+ float32x4_t e = vrsqrteq_f32(x1);
+ e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
+ e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
+ return vmulq_f32(x, e);
+}
+
+__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
+{
+ float32x4_t tempF;
+ int32x4_t tempHI,tempLO;
+
+ tempLO = vmovl_s16(vget_low_s16(vec));
+ tempF = vcvtq_n_f32_s32(tempLO,15);
+ tempF = __arm_vec_sqrt_f32_neon(tempF);
+ tempLO = vcvtq_n_s32_f32(tempF,15);
+
+ tempHI = vmovl_s16(vget_high_s16(vec));
+ tempF = vcvtq_n_f32_s32(tempHI,15);
+ tempF = __arm_vec_sqrt_f32_neon(tempF);
+ tempHI = vcvtq_n_s32_f32(tempF,15);
+
+ return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
+}
+
+__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
+{
+ float32x4_t temp;
+
+ temp = vcvtq_n_f32_s32(vec,31);
+ temp = __arm_vec_sqrt_f32_neon(temp);
+ return(vcvtq_n_s32_f32(temp,31));
+}
+
+#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_VEC_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cachel1_armv7.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cachel1_armv7.h
new file mode 100644
index 0000000000..d2c3e2291f
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cachel1_armv7.h
@@ -0,0 +1,411 @@
+/******************************************************************************
+ * @file cachel1_armv7.h
+ * @brief CMSIS Level 1 Cache API for Armv7-M and later
+ * @version V1.0.0
+ * @date 03. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_CACHEL1_ARMV7_H
+#define ARM_CACHEL1_ARMV7_H
+
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_CACHEL1_ARMV7_H */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 0000000000..237ff6ec3e
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,885 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.2.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+ /* __ARM_ARCH_8_1M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 0000000000..90de9dbf8f
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1467 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.3.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armclang_ltm.h
new file mode 100644
index 0000000000..0e5c7349d3
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1893 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 0000000000..adbf296f15
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 0000000000..a2778f58e8
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2177 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi":::"memory")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe":::"memory")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+ return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 0000000000..7eeffca5c7
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,968 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.2.0
+ * @date 28. January 2020
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_version.h b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_version.h
new file mode 100644
index 0000000000..2f048e4552
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.4
+ * @date 23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv81mml.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv81mml.h
new file mode 100644
index 0000000000..1ad19e215a
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv81mml.h
@@ -0,0 +1,4191 @@
+/**************************************************************************//**
+ * @file core_armv81mml.h
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version V1.3.1
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMV81MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS ARMV81MML definitions */
+#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+#if defined ( __CC_ARM )
+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV81MML_H_DEPENDANT
+#define __CORE_ARMV81MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv81MML_REV
+ #define __ARMv81MML_REV 0x0000U
+ #warning "__ARMv81MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __FPU_PRESENT != 0U
+ #ifndef __FPU_DP
+ #define __FPU_DP 0U
+ #warning "__FPU_DP not defined in device header file; using default!"
+ #endif
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __PMU_PRESENT
+ #define __PMU_PRESENT 0U
+ #warning "__PMU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __PMU_PRESENT != 0U
+ #ifndef __PMU_NUM_EVENTCNT
+ #define __PMU_NUM_EVENTCNT 2U
+ #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
+ #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2)
+ #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
+ #endif
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
+ \brief Type definitions for the Performance Monitoring Unit (PMU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
+ uint32_t RESERVED1[224];
+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
+ uint32_t RESERVED3[480];
+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
+ uint32_t RESERVED4[7];
+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
+ uint32_t RESERVED5[7];
+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
+ uint32_t RESERVED6[7];
+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
+ uint32_t RESERVED7[7];
+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
+ uint32_t RESERVED8[7];
+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
+ uint32_t RESERVED9[7];
+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
+ uint32_t RESERVED10[79];
+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
+ uint32_t RESERVED11[108];
+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
+ uint32_t RESERVED12[4];
+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
+ uint32_t RESERVED13[3];
+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
+ uint32_t RESERVED14[3];
+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions */
+
+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## PMU functions and events #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ########################## MVE functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_MveFunctions MVE Functions
+ \brief Function that provides MVE type.
+ @{
+ */
+
+/**
+ \brief get MVE type
+ \details returns the MVE type
+ \returns
+ - \b 0: No Vector Extension (MVE)
+ - \b 1: Integer Vector Extension (MVE-I)
+ - \b 2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+ const uint32_t mvfr1 = FPU->MVFR1;
+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+ {
+ return 2U;
+ }
+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+ {
+ return 1U;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 0000000000..932d3d188b
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,2222 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MBL_REV
+ #define __ARMv8MBL_REV 0x0000U
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 0000000000..71f000bcad
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,3196 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.2.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (80U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm0.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..6441ff3419
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm0.h
@@ -0,0 +1,952 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000..4e7179a614
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1087 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+#endif
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+#endif
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm1.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm1.h
new file mode 100644
index 0000000000..76b4569743
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm1.h
@@ -0,0 +1,979 @@
+/**************************************************************************//**
+ * @file core_cm1.h
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version V1.0.1
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M1
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (1U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM1_REV
+ #define __CM1_REV 0x0100U
+ #warning "__CM1_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm23.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm23.h
new file mode 100644
index 0000000000..55fff99509
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm23.h
@@ -0,0 +1,2297 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 11. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm3.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..24453a8863
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1943 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.1.1
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm33.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm33.h
new file mode 100644
index 0000000000..13359be3ed
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3264 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.2.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm35p.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm35p.h
new file mode 100644
index 0000000000..6a5f6ad147
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm35p.h
@@ -0,0 +1,3264 @@
+/**************************************************************************//**
+ * @file core_cm35p.h
+ * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
+ * @version V1.1.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM35P_H_GENERIC
+#define __CORE_CM35P_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M35P
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM35P definitions */
+#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
+ __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (35U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM35P_H_DEPENDANT
+#define __CORE_CM35P_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM35P_REV
+ #define __CM35P_REV 0x0000U
+ #warning "__CM35P_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M35P */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm4.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..4e0e886697
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.1.1
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm55.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm55.h
new file mode 100644
index 0000000000..6efaa3f842
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm55.h
@@ -0,0 +1,4215 @@
+/**************************************************************************//**
+ * @file core_cm55.h
+ * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM55_H_GENERIC
+#define __CORE_CM55_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_CM55
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM55 definitions */
+#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \
+ __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (55U) /*!< Cortex-M Core */
+
+#if defined ( __CC_ARM )
+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM55_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM55_H_DEPENDANT
+#define __CORE_CM55_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM55_REV
+ #define __CM55_REV 0x0000U
+ #warning "__CM55_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __FPU_PRESENT != 0U
+ #ifndef __FPU_DP
+ #define __FPU_DP 0U
+ #warning "__FPU_DP not defined in device header file; using default!"
+ #endif
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __PMU_PRESENT
+ #define __PMU_PRESENT 0U
+ #warning "__PMU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __PMU_PRESENT != 0U
+ #ifndef __PMU_NUM_EVENTCNT
+ #define __PMU_NUM_EVENTCNT 8U
+ #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
+ #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)
+ #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
+ #endif
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M55 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
+ \brief Type definitions for the Performance Monitoring Unit (PMU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
+ uint32_t RESERVED1[224];
+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
+ uint32_t RESERVED3[480];
+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
+ uint32_t RESERVED4[7];
+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
+ uint32_t RESERVED5[7];
+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
+ uint32_t RESERVED6[7];
+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
+ uint32_t RESERVED7[7];
+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
+ uint32_t RESERVED8[7];
+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
+ uint32_t RESERVED9[7];
+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
+ uint32_t RESERVED10[79];
+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
+ uint32_t RESERVED11[108];
+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
+ uint32_t RESERVED12[4];
+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
+ uint32_t RESERVED13[3];
+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
+ uint32_t RESERVED14[3];
+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions */
+
+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## PMU functions and events #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+/**
+ \brief Cortex-M55 PMU events
+ \note Architectural PMU events can be found in pmu_armv8.h
+*/
+
+#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */
+#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */
+#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */
+#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */
+#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */
+#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/
+#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */
+#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */
+#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */
+#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */
+#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */
+#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */
+#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */
+#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
+#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
+#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
+#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
+#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ########################## MVE functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_MveFunctions MVE Functions
+ \brief Function that provides MVE type.
+ @{
+ */
+
+/**
+ \brief get MVE type
+ \details returns the MVE type
+ \returns
+ - \b 0: No Vector Extension (MVE)
+ - \b 1: Integer Vector Extension (MVE-I)
+ - \b 2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+ const uint32_t mvfr1 = FPU->MVFR1;
+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+ {
+ return 2U;
+ }
+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+ {
+ return 1U;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM55_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm7.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000000..e1c31c275d
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2362 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.1.2
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_sc000.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000..dbc755fff3
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1030 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/core_sc300.h b/bsp/tae32f5300/Libraries/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000..e8914ba601
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1917 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/tae32f5300/Libraries/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 0000000000..791a8dae65
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.1
+ * @date 10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/tae32f5300/Libraries/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 0000000000..ef44ad01df
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version V5.1.2
+ * @date 10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ (((BASE) & MPU_RBAR_BASE_Msk) | \
+ (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/pmu_armv8.h b/bsp/tae32f5300/Libraries/CMSIS/Include/pmu_armv8.h
new file mode 100644
index 0000000000..dbd39d20c7
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/pmu_armv8.h
@@ -0,0 +1,337 @@
+/******************************************************************************
+ * @file pmu_armv8.h
+ * @brief CMSIS PMU API for Armv8.1-M PMU
+ * @version V1.0.0
+ * @date 24. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_PMU_ARMV8_H
+#define ARM_PMU_ARMV8_H
+
+/**
+ * \brief PMU Events
+ * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
+ * */
+
+#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
+#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
+#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
+#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
+#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
+#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
+#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
+#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
+#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
+#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
+#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
+#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
+#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
+#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
+#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
+#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
+#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
+#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
+#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
+#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
+#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
+#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
+#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
+#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
+#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
+#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
+#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
+#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
+#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
+#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
+#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
+#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
+#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
+#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
+#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
+#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
+#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
+#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
+#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
+#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
+#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
+#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
+#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
+#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
+#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
+#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
+#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
+#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
+#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
+#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
+#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
+#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
+#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
+#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
+#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
+#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
+#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
+#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
+#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
+#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
+#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
+#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
+#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
+#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
+#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
+#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
+#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
+#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
+#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
+#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
+#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
+#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
+#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
+#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
+#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
+
+/** \brief PMU Functions */
+
+__STATIC_INLINE void ARM_PMU_Enable(void);
+__STATIC_INLINE void ARM_PMU_Disable(void);
+
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
+
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
+
+/**
+ \brief Enable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Enable(void)
+{
+ PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
+}
+
+/**
+ \brief Disable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Disable(void)
+{
+ PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
+}
+
+/**
+ \brief Set event to count for PMU eventer counter
+ \param [in] num Event counter (0-30) to configure
+ \param [in] type Event to count
+*/
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
+{
+ PMU->EVTYPER[num] = type;
+}
+
+/**
+ \brief Reset cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
+{
+ PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
+}
+
+/**
+ \brief Reset all event counters
+*/
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
+{
+ PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
+}
+
+/**
+ \brief Enable counters
+ \param [in] mask Counters to enable
+ \note Enables one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
+{
+ PMU->CNTENSET = mask;
+}
+
+/**
+ \brief Disable counters
+ \param [in] mask Counters to enable
+ \note Disables one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
+{
+ PMU->CNTENCLR = mask;
+}
+
+/**
+ \brief Read cycle counter
+ \return Cycle count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
+{
+ return PMU->CCNTR;
+}
+
+/**
+ \brief Read event counter
+ \param [in] num Event counter (0-30) to read
+ \return Event count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
+{
+ return PMU->EVCNTR[num];
+}
+
+/**
+ \brief Read counter overflow status
+ \return Counter overflow status bits for the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
+{
+ return PMU->OVSSET;
+}
+
+/**
+ \brief Clear counter overflow status
+ \param [in] mask Counter overflow status bits to clear
+ \note Clears overflow status bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
+{
+ PMU->OVSCLR = mask;
+}
+
+/**
+ \brief Enable counter overflow interrupt request
+ \param [in] mask Counter overflow interrupt request bits to set
+ \note Sets overflow interrupt request bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
+{
+ PMU->INTENSET = mask;
+}
+
+/**
+ \brief Disable counter overflow interrupt request
+ \param [in] mask Counter overflow interrupt request bits to clear
+ \note Clears overflow interrupt request bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
+{
+ PMU->INTENCLR = mask;
+}
+
+/**
+ \brief Software increment event counter
+ \param [in] mask Counters to increment
+ \note Software increment bits for one or more event counters (0-30)
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
+{
+ PMU->SWINC = mask;
+}
+
+#endif
diff --git a/bsp/tae32f5300/Libraries/CMSIS/Include/tz_context.h b/bsp/tae32f5300/Libraries/CMSIS/Include/tz_context.h
new file mode 100644
index 0000000000..0d09749f3a
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file tz_context.h
+ * @brief Context Management for Armv8-M TrustZone
+ * @version V1.0.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/bsp/tae32f5300/Libraries/SConscript b/bsp/tae32f5300/Libraries/SConscript
new file mode 100644
index 0000000000..f316ba52e6
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/SConscript
@@ -0,0 +1,58 @@
+# RT-Thread building script for bridge
+
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+CMSIS/Device/Tai_action/TAE32F53xx/Source/system_tae32f53xx.c
+TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll.c
+TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_cortex.c
+TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_sysctrl.c
+TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_fpll.c
+TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_gpio.c
+TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dma.c
+""")
+
+if GetDepend(['RT_USING_SERIAL']):
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_uart.c']
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_tmr.c']
+
+if GetDepend(['RT_USING_I2C']):
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_i2c.c']
+
+if GetDepend(['RT_USING_CAN']):
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_can.c']
+
+if GetDepend(['RT_USING_ADC']):
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_adc.c']
+
+if GetDepend(['RT_USING_WDT']):
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_wwdg.c']
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iwdg.c']
+
+if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM'] or GetDepend(['RT_USING_PULSE_ENCODER'])):
+ src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_tmr.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+ src = src + ['CMSIS/Device/Tai_action/TAE32F53xx/Source/GCC/startup_ARMCM3.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src = src + ['CMSIS/Device/Tai_action/TAE32F53xx/Source/startup_tae32f53xx.c']
+elif rtconfig.CROSS_TOOL == 'iar':
+ src = src + ['CMSIS/Device/Tai_action/TAE32F53xx/Source/IAR/startup_ARMCM3.s']
+
+#add headfile script
+path = [cwd + '/CMSIS/Include',
+ cwd + '/CMSIS/Device/Tai_action/TAE32F53xx/Include',
+ cwd + '/TAE32F53xx_StdPeriph_Driver/inc']
+
+CPPDEFINES = ['USE_TAE_DRIVER', rtconfig.MCU_TYPE, '__DEBUG']
+
+group = DefineGroup('TAE32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll.h
new file mode 100644
index 0000000000..0c289ca40b
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll.h
@@ -0,0 +1,166 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the LL
+ * module driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_H_
+#define _TAE32F53XX_LL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_conf.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup TAE32F53xx_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TAE32F53xx_LL_Exported_Constants TAE32F53xx LL Exported Constants
+ * @brief TAE32F53xx LL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief TAE32F53xx LL Driver version number V1.2.0
+ */
+#define __TAE32F53xx_LL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __TAE32F53xx_LL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __TAE32F53xx_LL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __TAE32F53xx_LL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __TAE32F53xx_LL_VERSION ((__TAE32F53xx_LL_VERSION_MAIN << 24) |\
+ (__TAE32F53xx_LL_VERSION_SUB1 << 16) |\
+ (__TAE32F53xx_LL_VERSION_SUB2 << 8 ) |\
+ (__TAE32F53xx_LL_VERSION_RC))
+
+/**
+ * @brief TAE32F53xx SDK Stage String definition
+ * @note Value range: "Alpha" "Beta" "RC" "Trial" "Release"
+ */
+#define SDK_STAGE_STR "Release"
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TAE32F53xx_LL_Exported_Types TAE32F53xx LL Exported Types
+ * @brief TAE32F53xx LL Exported Types
+ * @{
+ */
+
+/**
+ * LL Tick Freq Enum Type Definition
+ */
+typedef enum {
+ LL_TICK_FREQ_10HZ = 100U, /*!< Tick Frequency 10Hz */
+ LL_TICK_FREQ_100HZ = 10U, /*!< Tick Frequency 100Hz */
+ LL_TICK_FREQ_1KHZ = 1U, /*!< Tick Frequency 1KHz */
+ LL_TICK_FREQ_DEFAULT = LL_TICK_FREQ_1KHZ, /*!< Tick Frequency default */
+} LL_TickFreqETypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TAE32F53xx_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TAE32F53xx_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_Init(void);
+LL_StatusETypeDef LL_DeInit(void);
+void LL_MspInit(void);
+void LL_MspDeInit(void);
+
+LL_StatusETypeDef LL_InitTick(uint32_t TickPriority);
+/**
+ * @}
+ */
+
+
+/** @addtogroup TAE32F53xx_LL_Exported_Functions_Group2
+ * @{
+ */
+void LL_IncTick(void);
+uint32_t LL_GetTick(void);
+uint32_t LL_GetTickPrio(void);
+LL_StatusETypeDef LL_SetTickFreq(LL_TickFreqETypeDef Freq);
+LL_TickFreqETypeDef LL_GetTickFreq(void);
+void LL_SuspendTick(void);
+void LL_ResumeTick(void);
+void LL_Delay(uint32_t Delay);
+uint32_t LL_GetHalVersion(void);
+void LL_GetUID(uint32_t *UID[4]);
+/**
+ * @}
+ */
+
+
+/** @addtogroup TAE32F53xx_LL_Exported_Functions_Group3
+ * @{
+ */
+void LL_ShowInfo(void);
+void delay_ms(uint32_t ms);
+void printf_array(void *ptr, uint32_t len);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _TAE32F53XX_LL_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_adc.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_adc.h
new file mode 100644
index 0000000000..202a6ff6c3
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_adc.h
@@ -0,0 +1,3582 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_ADC_H_
+#define _TAE32F53XX_LL_ADC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC LL Exported Constants
+ * @brief ADC LL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief regular trigger edge
+ * Internal mask for ADC group regular trigger:
+ * To select into literal LL_ADC_REG_TRIG_x the relevant bits for:
+ */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_LR_EXTEN_0)
+
+/**
+ * @brief Mask containing trigger source masks for each of possible
+ * trigger edge selection duplicated with shifts [0; 4; 8; 12]
+ * corresponding to {SW start; ext trigger; ext trigger; ext trigger}
+ */
+#define ADC_REG_TRIG_SOURCE_MASK (((ADC_REG_TRIG_SOFTWARE & ADC_LR_EXTSEL) << (4U * 0UL)) | \
+ ((ADC_LR_EXTSEL) << (4U * 1UL)) | \
+ ((ADC_LR_EXTSEL) << (4U * 2UL)) | \
+ ((ADC_LR_EXTSEL) << (4U * 3UL)) )
+
+/**
+ * @brief Mask containing trigger edge masks for each of possible
+ * trigger edge selection duplicated with shifts [0; 4; 8; 12]
+ * corresponding to {SW start; ext trigger; ext trigger; ext trigger}
+ */
+#define ADC_REG_TRIG_EDGE_MASK (((ADC_REG_TRIG_SOFTWARE & ADC_LR_EXTEN) << (4U * 0UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
+
+/**
+ * @brief Definition of ADC group regular trigger bits information
+ */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_LR_EXTSEL_Pos)
+
+/**
+ * @brief Definition of ADC group regular trigger bits information
+ */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_LR_EXTEN_Pos)
+
+/**
+ * @brief Internal mask for ADC group injected trigger:
+ * To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:
+ */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JLR_JEXTEN_0)
+
+/**
+ * @brief Mask containing trigger source masks for each of possible
+ * trigger edge selection duplicated with shifts [0; 4; 8; 12]
+ * corresponding to {SW start; ext trigger; ext trigger; ext trigger}
+ */
+#define ADC_INJ_TRIG_SOURCE_MASK (((ADC_INJ_TRIG_SOFTWARE & ADC_JLR_JEXTSEL) << (4U * 0UL)) | \
+ ((ADC_JLR_JEXTSEL) << (4U * 1UL)) | \
+ ((ADC_JLR_JEXTSEL) << (4U * 2UL)) | \
+ ((ADC_JLR_JEXTSEL) << (4U * 3UL)) )
+
+/**
+ * @brief Mask containing trigger edge masks for each of possible
+ * trigger edge selection duplicated with shifts [0; 4; 8; 12]
+ * corresponding to {SW start; ext trigger; ext trigger; ext trigger}
+ */
+#define ADC_INJ_TRIG_EDGE_MASK (((ADC_INJ_TRIG_SOFTWARE & ADC_JLR_JEXTEN) << (4U * 0UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
+
+/**
+ * @brief Definition of ADC group injected trigger bits information
+ */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JLR_JEXTSEL_Pos)
+
+/**
+ * @brief Definition of ADC group injected trigger bits information
+ */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JLR_JEXTEN_Pos)
+
+/**
+ * @brief Definition of ADC group injected trigger bits information
+ */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT (0x00000001UL)
+
+/**
+ * @brief Definition of ADC group injected trigger bits information
+ */
+#define ADC_JSQX_REGOFFSET (0x00000002UL)
+
+/**
+ * @brief Definition of ADC group injected trigger bits information
+ */
+#define ADC_SMPRX_REGOFFSET (0x00000002UL)
+
+/**
+ * @brief Definition of ADC group injected trigger bits information
+ */
+#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
+
+
+/**
+ * @brief ADC register CR bits: Software can read as well as set this bit. Writing '0' has no effect on the bit value.
+ */
+#define ADC_CR0_BITS_PROPERTY_RS (ADC_CR0_JADSTP | ADC_CR0_ADSTP | ADC_CR0_JADSTART | ADC_CR0_ADSTART)
+
+
+
+/** @defgroup ADC_LL_AWD_CHANNELS ADC LL AWD CHANNELS
+ * @brief Analog watchdog Monitored channels
+ * @{
+ */
+
+/** @brief ADC analog watchdog monitoring disabled */
+#define ADC_AWD_DISABLE (0x00000000UL)
+/** @brief ADC analog watchdog monitoring enable */
+#define ADC_AWD_ALL_CHANNELS (0x00000FFFUL)
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define ADC_AWD_CHANNEL_0 (ADC_AWD0CR_AWD0CH_0 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define ADC_AWD_CHANNEL_1 (ADC_AWD0CR_AWD0CH_1 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define ADC_AWD_CHANNEL_2 (ADC_AWD0CR_AWD0CH_2 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define ADC_AWD_CHANNEL_3 (ADC_AWD0CR_AWD0CH_3 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define ADC_AWD_CHANNEL_4 (ADC_AWD0CR_AWD0CH_4 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define ADC_AWD_CHANNEL_5 (ADC_AWD0CR_AWD0CH_5 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define ADC_AWD_CHANNEL_6 (ADC_AWD0CR_AWD0CH_6 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define ADC_AWD_CHANNEL_7 (ADC_AWD0CR_AWD0CH_7 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define ADC_AWD_CHANNEL_8 (ADC_AWD0CR_AWD0CH_8 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define ADC_AWD_CHANNEL_9 (ADC_AWD0CR_AWD0CH_9 )
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define ADC_AWD_CHANNEL_10 (ADC_AWD0CR_AWD0CH_10)
+/** @brief ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define ADC_AWD_CHANNEL_TEMPSENSOR (ADC_AWD0CR_AWD0CH_11)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_IT ADC LL IT
+ * @brief ADC interruptions for configuration (interruption enable or disable)
+ * @note IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
+#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
+#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
+#define ADC_IT_AWD0 ADC_IER_AWD0IE /*!< ADC interruption ADC analog watchdog 0 */
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_FLAG ADC FLAG
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
+#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
+#define ADC_FLAG_AWD0 ADC_ISR_AWD0 /*!< ADC flag ADC analog watchdog 1 */
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 2 */
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 3 */
+
+#define ADC_AWD_THRESHOLDS_HIGH_POS (16U) /*!< ADC AWD Thresholds high pos */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Types ADC LL Exported Types
+ * @brief ADC LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief Oversampling - Data shift
+ */
+typedef enum {
+ ADC_OVSS_SHIFT_NONE = 0x0,
+ /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_1 = ADC_CR1_OVSS_0,
+ /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_2 = ADC_CR1_OVSS_1,
+ /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_3 = ADC_CR1_OVSS_1 | ADC_CR1_OVSS_0,
+ /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_4 = ADC_CR1_OVSS_2,
+ /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_5 = ADC_CR1_OVSS_2 | ADC_CR1_OVSS_0,
+ /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_6 = ADC_CR1_OVSS_2 | ADC_CR1_OVSS_1,
+ /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_7 = ADC_CR1_OVSS_2 | ADC_CR1_OVSS_1 | ADC_CR1_OVSS_0,
+ /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+ ADC_OVSS_SHIFT_RIGHT_8 = ADC_CR1_OVSS_3,
+ /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+} ADC_OverSampShiftETypeDef;
+
+/**
+ * @brief Oversampling - Ratio
+ */
+typedef enum {
+ ADC_OVSR_RATIO_2 = 0x0,
+ /*!< ADC oversampling ratio of 2 (before potential shift) */
+ ADC_OVSR_RATIO_4 = ADC_CR1_OVSR_0,
+ /*!< ADC oversampling ratio of 4 (before potential shift) */
+ ADC_OVSR_RATIO_8 = ADC_CR1_OVSR_1,
+ /*!< ADC oversampling ratio of 8 (before potential shift) */
+ ADC_OVSR_RATIO_16 = ADC_CR1_OVSR_1 | ADC_CR1_OVSR_0,
+ /*!< ADC oversampling ratio of 16 (before potential shift) */
+ ADC_OVSR_RATIO_32 = ADC_CR1_OVSR_2,
+ /*!< ADC oversampling ratio of 32 (before potential shift) */
+ ADC_OVSR_RATIO_64 = ADC_CR1_OVSR_2 | ADC_CR1_OVSR_0,
+ /*!< ADC oversampling ratio of 64 (before potential shift) */
+ ADC_OVSR_RATIO_128 = ADC_CR1_OVSR_2 | ADC_CR1_OVSR_1,
+ /*!< ADC oversampling ratio of 128 (before potential shift) */
+ ADC_OVSR_RATIO_256 = ADC_CR1_OVSR_2 | ADC_CR1_OVSR_1 | ADC_CR1_OVSR_0,
+ /*!< ADC oversampling ratio of 256 (before potential shift) */
+} ADC_OverSampRatioETypeDef;
+
+/**
+ * @brief Oversampling scope
+ */
+typedef enum {
+ ADC_OVS_DISABLE = 0x0,
+ /*!< ADC oversampling disabled. */
+ ADC_OVS_GRP_REGULAR_CONTINUED = ADC_CR1_ROVSE,
+ /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular:
+ when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
+ ADC_OVS_GRP_REGULAR_RESUMED = ADC_CR1_ROVSM | ADC_CR1_ROVSE,
+ /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular:
+ when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+ ADC_OVS_GRP_INJECTED = ADC_CR1_JOVSE,
+ /*!< ADC oversampling on conversions of ADC group injected. */
+ ADC_OVS_GRP_INJ_REG_RESUMED = ADC_CR1_JOVSE | ADC_CR1_ROVSE,
+ /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular:
+ when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+} ADC_OverSampModeETypeDef;
+
+/**
+ * @brief Oversampling scope for ADC group regular valid
+ */
+typedef enum {
+ ADC_OVS_CONTINUED_MODE = 0x0,
+ /*!< Oversampling buffer maintained during injection sequence */
+ ADC_OVS_RESUMED_MODE = ADC_CR1_ROVSM,
+ /*!< Oversampling buffer zeroed during injection sequence */
+} ADC_OverSampROVSMETypeDef;
+
+/**
+ * @brief Discontinuous mode Trigger over sample
+ */
+typedef enum {
+ ADC_OVS_TRIG_CONT = 0x0,
+ /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+ ADC_OVS_TRIG_DISCONT = ADC_CR1_TROVS,
+ /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+} ADC_OverSampTROVSETypeDef;
+
+/**
+ * @brief Synchronization
+ */
+typedef enum {
+ ADC_SYNCEN_DIS = 0x0,
+ /*!< ADC synchronization is disable */
+ ADC_SYNCEN_EN = ADC_CR1_SYNCEN,
+ /*!< ADC synchronization is enabled */
+} ADC_SyncEnETypeDef;
+
+/**
+ * @brief ADC TBIMOD SEL
+ */
+typedef enum {
+ ADC_TBIMOD_MUX_CLOSE = 0x0,
+ ADC_TBIMOD_A_SH = ADC_CR1_OVSR_2,
+ ADC_TBIMOD_A_ADC = ADC_CR1_OVSR_2 | ADC_CR1_OVSR_0,
+ ADC_TBIMOD_B_SH = ADC_CR1_OVSR_2 | ADC_CR1_OVSR_1,
+ ADC_TBIMOD_B_ADC = ADC_CR1_OVSR_2 | ADC_CR1_OVSR_1 | ADC_CR1_OVSR_0,
+} ADC_TestBuffModeETypeDef;
+
+/**
+ * @brief ADC ANOLOG CTL
+ */
+typedef enum {
+ ADC_ANOLOG_CTL_DEFAULT = ADC_CR2_ISEL_1 | ADC_CR2_CH_EN | ADC_CR2_FADC_EN | ADC_CR2_REF_EN | ADC_CR2_BIAS_EN,
+ ADC_ANOLOG_CTL_A_SH = ADC_ANOLOG_CTL_DEFAULT | ADC_TBIMOD_A_SH,
+ ADC_ANOLOG_CTL_A_ADC = ADC_ANOLOG_CTL_DEFAULT | ADC_TBIMOD_A_ADC,
+ ADC_ANOLOG_CTL_B_SH = ADC_ANOLOG_CTL_DEFAULT | ADC_TBIMOD_B_SH,
+ ADC_ANOLOG_CTL_B_ADC = ADC_ANOLOG_CTL_DEFAULT | ADC_TBIMOD_B_ADC,
+} ADC_AnologCtlETypeDef;
+
+/**
+ * @brief Channel Sampling time
+ */
+typedef enum {
+ ADC_SAMPLINGTIME_6CYCLES = 0x0,
+ /*!< Sampling time 6 ADC clock cycles */
+ ADC_SAMPLINGTIME_18CYCLES = ADC_SMPR0_SMP0_0,
+ /*!< Sampling time 18 ADC clock cycles */
+ ADC_SAMPLINGTIME_42CYCLES = ADC_SMPR0_SMP0_1,
+ /*!< Sampling time 42 ADC clock cycles */
+ ADC_SAMPLINGTIME_90CYCLES = ADC_SMPR0_SMP0_1 | ADC_SMPR0_SMP0_0,
+ /*!< Sampling time 90 ADC clock cycles */
+ ADC_SAMPLINGTIME_186CYCLES = ADC_SMPR0_SMP0_2,
+ /*!< Sampling time 186 ADC clock cycles */
+ ADC_SAMPLINGTIME_378CYCLES = ADC_SMPR0_SMP0_2 | ADC_SMPR0_SMP0_0,
+ /*!< Sampling time 378 ADC clock cycles */
+ ADC_SAMPLINGTIME_762CYCLES = ADC_SMPR0_SMP0_2 | ADC_SMPR0_SMP0_1,
+ /*!< Sampling time 762 ADC clock cycles */
+ ADC_SAMPLINGTIME_1530CYCLES = ADC_SMPR0_SMP0_2 | ADC_SMPR0_SMP0_1 | ADC_SMPR0_SMP0_0,
+ /*!< Sampling time 1530 ADC clock cycles */
+} ADC_SampTimeETypeDef;
+
+/**
+ * @brief ADC CALCULATE OFFST GROUP SELECT
+ */
+typedef enum {
+ ADC_CAL_OFFSET_GROUP0 = 0x0,
+ /*ADC calibration offset/gain register gruop 0 -- OFR0*/
+ ADC_CAL_OFFSET_GROUP1 = ADC_CALR0_CAL0_0,
+ /*ADC calibration offset/gain register gruop 1 -- OFR1*/
+ ADC_CAL_OFFSET_GROUP2 = ADC_CALR0_CAL0_1,
+ /*ADC calibration offset/gain register gruop 2 -- OFR2*/
+ ADC_CAL_OFFSET_GROUP3 = ADC_CALR0_CAL0_1 | ADC_CALR0_CAL0_0,
+ /*ADC calibration offset/gain register gruop 3 -- OFR3*/
+} ADC_CalrGroupETypeDef;
+
+/**
+ * @brief Trigger edge
+ */
+typedef enum {
+ LL_ADC_REG_TRIG_SOFT = 0x0,
+ /*!< ADC group regular conversion software trigger */
+ ADC_REG_TRIG_EXT_RISING = ADC_LR_EXTEN_0,
+ /*!< ADC group regular conversion trigger polarity set to rising edge */
+ ADC_REG_TRIG_EXT_FALLING = ADC_LR_EXTEN_1,
+ /*!< ADC group regular conversion trigger polarity set to falling edge */
+ ADC_REG_TRIG_EXT_RISINGFALLING = ADC_LR_EXTEN_1 | ADC_LR_EXTEN_0,
+ /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+} ADC_RegTrigEdgeETypeDef;
+
+/**
+ * @brief Continuous mode
+ */
+typedef enum {
+ ADC_REG_CONV_SINGLE = 0x0,
+ /*!< ADC conversions are performed in single mode: one conversion per trigger */
+ ADC_REG_CONV_CONTINUOUS = ADC_CR1_CONT,
+ /*!< ADC conversions are performed in continuous mode: after the first trigger,
+ following conversions launched successively automatically */
+} ADC_RegConvModeETypeDef;
+
+/**
+ * @brief Overrun behavior on conversion data
+ */
+typedef enum {
+ ADC_OVR_DATA_PRESERVED = 0x0,
+ /*!< ADC group regular behavior in case of overrun: data preserved */
+ ADC_OVR_DATA_OVERWRITTEN = ADC_CR1_OVRMOD,
+ /*!< ADC group regular behavior in case of overrun: data overwritten */
+} ADC_OverRunModeETypeDef;
+
+/**
+ * @brief Sequencer discontinuous mode
+ */
+typedef enum {
+ ADC_REG_SEQ_DISCON_DISABLE = 0x0,
+ /*!< ADC group regular sequencer discontinuous mode disable */
+ ADC_REG_SEQ_DISNUM_1RANK = ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+ ADC_REG_SEQ_DISNUM_2RANKS = ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 2 ranks */
+ ADC_REG_SEQ_DISNUM_3RANKS = ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+ ADC_REG_SEQ_DISNUM_4RANKS = ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+ ADC_REG_SEQ_DISNUM_5RANKS = ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+ ADC_REG_SEQ_DISNUM_6RANKS = ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+ ADC_REG_SEQ_DISNUM_7RANKS = ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+ ADC_REG_SEQ_DISNUM_8RANKS = ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN,
+ /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+} ADC_RegDiscontETypeDef;
+
+/**
+ * @brief Sequencer length
+ */
+typedef enum {
+ ADC_REG_SEQ_LENGTH_1 = 0x0,
+ /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+ ADC_REG_SEQ_LENGTH_2 = ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_3 = ADC_LR_LEN_1,
+ /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_4 = ADC_LR_LEN_1 | ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_5 = ADC_LR_LEN_2,
+ /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_6 = ADC_LR_LEN_2 | ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_7 = ADC_LR_LEN_2 | ADC_LR_LEN_1,
+ /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_8 = ADC_LR_LEN_2 | ADC_LR_LEN_1 | ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_9 = ADC_LR_LEN_3,
+ /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_10 = ADC_LR_LEN_3 | ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_11 = ADC_LR_LEN_3 | ADC_LR_LEN_1,
+ /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_12 = ADC_LR_LEN_3 | ADC_LR_LEN_1 | ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_13 = ADC_LR_LEN_3 | ADC_LR_LEN_2,
+ /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_14 = ADC_LR_LEN_3 | ADC_LR_LEN_2 | ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_15 = ADC_LR_LEN_3 | ADC_LR_LEN_2 | ADC_LR_LEN_1,
+ /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+ ADC_REG_SEQ_LENGTH_16 = ADC_LR_LEN_3 | ADC_LR_LEN_2 | ADC_LR_LEN_1 | ADC_LR_LEN_0,
+ /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+} ADC_RegSeqLengthETypeDef;
+
+/**
+ * @brief Sequencer ranks
+ */
+typedef enum {
+ ADC_REG_RANK_1 = 0x0UL,
+ /*!< ADC group regular sequencer rank 1 */
+ ADC_REG_RANK_2 = 0x1UL,
+ /*!< ADC group regular sequencer rank 2 */
+ ADC_REG_RANK_3 = 0x2UL,
+ /*!< ADC group regular sequencer rank 3 */
+ ADC_REG_RANK_4 = 0x3UL,
+ /*!< ADC group regular sequencer rank 4 */
+ ADC_REG_RANK_5 = 0x4UL,
+ /*!< ADC group regular sequencer rank 5 */
+ ADC_REG_RANK_6 = 0x5UL,
+ /*!< ADC group regular sequencer rank 6 */
+ ADC_REG_RANK_7 = 0x6UL,
+ /*!< ADC group regular sequencer rank 7 */
+ ADC_REG_RANK_8 = 0x7UL,
+ /*!< ADC group regular sequencer rank 8 */
+ ADC_REG_RANK_9 = 0x8UL,
+ /*!< ADC group regular sequencer rank 9 */
+ ADC_REG_RANK_10 = 0x9UL,
+ /*!< ADC group regular sequencer rank 10 */
+ ADC_REG_RANK_11 = 0xAUL,
+ /*!< ADC group regular sequencer rank 11 */
+ ADC_REG_RANK_12 = 0xBUL,
+ /*!< ADC group regular sequencer rank 12 */
+ ADC_REG_RANK_13 = 0xCUL,
+ /*!< ADC group regular sequencer rank 13 */
+ ADC_REG_RANK_14 = 0xDUL,
+ /*!< ADC group regular sequencer rank 14 */
+ ADC_REG_RANK_15 = 0xEUL,
+ /*!< ADC group regular sequencer rank 15 */
+ ADC_REG_RANK_16 = 0xFUL,
+ /*!< ADC group regular sequencer rank 16 */
+} ADC_RegSeqRankETypeDef;
+
+/**
+ * @brief Trigger source
+ */
+typedef enum {
+ ADC_REG_TRIG_SOFTWARE = 0x0,
+ /*!TCR
+ */
+typedef enum {
+ ADC_REG_DMA_TRANSFER_DISABLE = 0x0,
+ ADC_REG_DMA_TRANSFER_SINGLE = ADC_DMA_TCR_START,
+ ADC_REG_DMA_TRANSFER_CIRCLE = ADC_DMA_TCR_CIRC | ADC_DMA_TCR_START,
+} ADC_DMATransferModeETypeDef;
+
+/**
+ * @brief ADC instance Channel number
+ */
+typedef enum {
+ ADC_CHANNEL_0 = 0UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+ ADC_CHANNEL_1 = 1UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+ ADC_CHANNEL_2 = 2UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+ ADC_CHANNEL_3 = 3UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+ ADC_CHANNEL_4 = 4UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+ ADC_CHANNEL_5 = 5UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+ ADC_CHANNEL_6 = 6UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+ ADC_CHANNEL_7 = 7UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+ ADC_CHANNEL_8 = 8UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+ ADC_CHANNEL_9 = 9UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+ ADC_CHANNEL_10 = 10UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+ ADC_CHANNEL_TEMPSENSOR = 11UL,
+ /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+} ADC_ChannelSelETypeDef;
+
+
+/**
+ * @brief ADC group regular oversampling structure definition
+ */
+typedef struct __ADC_OversamplingTypeDef {
+ ADC_OverSampROVSMETypeDef OverSampResetMode; /*!< Set ADC over sample reset mode,only regular group is valid */
+ ADC_OverSampTROVSETypeDef TrigOverSamp; /*!< Set ADC trigger over sample */
+ ADC_OverSampShiftETypeDef OverSampShiftBit; /*!< Set ADC over sample shift bit */
+ ADC_OverSampRatioETypeDef OverSampRatio; /*!< Set ADC over sample ratio */
+} ADC_OversamplingTypeDef;
+
+/** @defgroup LL_ADC_INIT ADC Exported Init structure
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected.
+ * Refer to corresponding unitary functions into
+ * @note The setting of these parameters by function reference LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ */
+typedef struct __ADC_InitTypeDef {
+ uint32_t NormInterrupt; /*!< Set ADC Normal interrupt paramter cconfig.
+ This parameter can be combination value of reference LL_ADC_IT */
+ ADC_SyncEnETypeDef Synchronization; /*!< Set ADC synchronization */
+ ADC_AnologCtlETypeDef AnologCfg; /*!< Set ADC anolog paramter cconfig */
+ ADC_OverRunModeETypeDef Overrun; /*!< Set ADC group regular behavior in case of overrun: data preserved or overwritten */
+ LL_FuncStatusETypeDef RegOversampMode; /*!< Specify whether the regular group oversampling feature is enabled or disabled */
+ LL_FuncStatusETypeDef InjOversampMode; /*!< Specify whether the injected group oversampling feature is enabled or disabled */
+ ADC_OversamplingTypeDef OverSampling; /*!< Specify the Oversampling parameters.Caution: this setting overwrites the
+ previous oversampling configuration if oversampling is already enabled. */
+} ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * (functions with prefix "REG").
+ */
+typedef struct __ADC_REG_InitTypeDef {
+ ADC_ChannelSelETypeDef Channel; /*!< Set ADC group regular conversion Channel. */
+ LL_FuncStatusETypeDef SampInterrupt; /*!< Configures the ADC conversion Channel Sample interrupt. */
+ ADC_RegSeqRankETypeDef SequencerPos; /*!< Set SQR is configured in combination with length for the number of conversions */
+ ADC_RegExtTrigSrcETypeDef TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start)
+ or from external peripheral(timer event,hrpwm trigger , up edge). */
+ ADC_RegSeqLengthETypeDef SequencerLength; /*!< Set ADC group regular sequencer length. */
+ ADC_RegDiscontETypeDef SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
+ and scan conversions interrupted every selected number of ranks. */
+ ADC_RegConvModeETypeDef ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
+ conversions are performedin single mode (one conversion per trigger). or in
+ continuous mode (after the first trigger,following conversions launched
+ successively automatically). */
+ ADC_DiffSelETypeDef DifferSel; /*!< Set ADC group regular channel is differential or single mode */
+ ADC_SampTimeETypeDef SampTimClk; /*!< Set ADC group regular channel sample clk length */
+} ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * (functions with prefix "INJ").
+ */
+typedef struct __ADC_INJ_InitTypeDef {
+ ADC_ChannelSelETypeDef Channel; /*!< Set ADC group injected conversion Channel. */
+ ADC_InjSeqRankETypeDef SequencerPos; /*!< Set JSQR is configured in combination with length for the number of
+ conversions the channel is placed on. */
+ ADC_InjExtTrigSrcETypeDef TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
+ or from external peripheral (timer event, external interrupt line). */
+ ADC_InjSeqLengthETypeDef SequencerLength; /*!< Set ADC group injected sequencer length. */
+ ADC_InjDiscontEnETypeDef SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence
+ subdivided and scan conversions interrupted every selected number of ranks. */
+ ADC_InjAutoTrigETypeDef TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. */
+
+} ADC_INJ_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC to ECU.
+ * @note These parameters have an impact on ADC scope: ADC to ECU.
+ * Electric quantity parameter calculation configuration.
+ */
+typedef struct __ADC_ECUConfTypeDef {
+ ADC_EcuGroupETypeDef GroupSel; /*!< Each ADC has four sets of ECU configurations, and the ECU is divided into four events. */
+ ADC_ChannelSelETypeDef AddrDataSel; /*!< Set ADC to ECU: The ECU fetches data from the channel address of the ADC . */
+ ADC_AnologWDETypeDef PingPongUpZero; /*!< Set Sinusoidal wave above zero detection of the selected watchdog. */
+ ADC_AnologWDETypeDef PingPongDownZero; /*!< SetSinusoidal wave down through zero detection of the selected watchdog. */
+ ADC_ChannelSelETypeDef AWD2SourceSel; /*!< Set Watchdog 2 monitors channel sources. */
+ ADC_ChannelSelETypeDef AWD1SourceSel; /*!< Set Watchdog 1 monitors channel sources. */
+ ADC_ChannelSelETypeDef AWD0SourceSel; /*!< Set Watchdog 0 monitors channel sources. */
+} ADC_ECUConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going
+ * on ADC groups regular and injected.
+ * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups.
+ */
+typedef struct __ADC_AnalogWDGCfgTypeDef {
+
+ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
+ This parameter can be combination value of reference LL_ADC_AWD_CHANNELS. */
+
+ int16_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ int16_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ ADC_AnologWDETypeDef WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. */
+
+ ADC_AnologWDFliterETypeDef Filtering; /*!< Specify whether filtering should be use and the number of samples to consider.
+ Before setting flag or raising interrupt, analog watchdog can wait to have several
+ consecutive out-of-window samples. This parameter allows to configure this number. */
+} ADC_AnalogWDGCfgTypeDef;
+
+/**
+ * @brief Structure definition of ADC DMA Transfer
+ * @note The setting of these parameters by function LL_ADC_DMATransferConfig() is conditioned to ADC state.
+ * Each channel corresponds to a set of DMA, and only regular channels can use DMA.
+ */
+typedef struct __ADC_DMATransferCfgTypeDef {
+ ADC_ChannelSelETypeDef Channel; /*!< Select which ADC direct memory access the selected channel. */
+ LL_FuncStatusETypeDef HalfInterrupt; /*!< Configures the ADC direct memory access Half interrupt. */
+ LL_FuncStatusETypeDef FullInterrupt; /*!< Configures the ADC direct memory access Full interrupt. */
+ ADC_DMATransferModeETypeDef TransferMode; /*!< Configure the DMA transfer mode to be single or cyclic. */
+ uint32_t Address; /*!< Configure the address of the DMA transfer Buffer ,Only SECTION_RAMB,
+ SECTION_RAMB can be configured . */
+ uint32_t Length; /*!< Configure the length of data (byte units) for a single DMA transfer.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+} ADC_DMATransferCfgTypeDef;
+
+
+/**
+ * @brief Calibration parameter definitions for ADC groups regular and injected
+ */
+typedef struct __ADC_CalibrationTypeDef {
+ ADC_ChannelSelETypeDef Channel; /*!< Select which ADC channel congfigure Calibration parameters. */
+ ADC_CalibGroupETypeDef CalibrationGroup; /*!< Set ADC calibration group parameter selection. */
+
+ int16_t Offset; /*!< Configure ADC calibration offset,default value is 0x0.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint16_t Gain; /*!< Configure ADC calibration gain defaulr value is 0x2000.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} ADC_CalibrationTypeDef;
+
+/**
+ * @brief Read ADC self-calibration data
+ */
+typedef struct {
+ int16_t SingleOffset; /*!< Read ADC single-ended self-calibration data*/
+
+ uint16_t SingleGain; /*!< Read ADC single-ended self-calibration data*/
+
+ int16_t DiffOffset; /*!< Read ADC differential self-calibration data*/
+
+ uint16_t DiffGain; /*!< Read ADC differential self-calibration data*/
+
+ int16_t SingleBuffOffset; /*!< Read ADC single-ended plus BUFF self-calibration data*/
+
+ uint16_t SingleBuffGain; /*!< Read ADC single-ended plus BUFF self-calibration data*/
+
+} ADC_CalibrationDataTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC LL Exported Macros
+ * @brief ADC LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+
+/** @addtogroup ADC_LL_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+/**
+ * @brief Start ADC group regular conversion.
+ * @note This function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note Setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @param Instance ADC instance
+ * @retval None
+ */
+#define __LL_ADC_REG_StartConversion(__INSTANCE__) MODIFY_REG((__INSTANCE__)->CR0, ADC_CR0_BITS_PROPERTY_RS, ADC_CR0_ADSTART)
+
+/**
+ * @brief Stop ADC group regular conversion.
+ * @note Setting of this feature is conditioned to ADC state:
+ * ADC must be enabled with conversion on going on group regular,
+ * without ADC disable command on going.
+ * @param Instance ADC instance
+ * @retval None
+ */
+#define __LL_ADC_REG_StopConversion(__INSTANCE__) MODIFY_REG((__INSTANCE__)->CR0, ADC_CR0_BITS_PROPERTY_RS, ADC_CR0_ADSTP)
+
+/**
+ * @brief Get ADC group regular conversion state.
+ * @param Instance ADC instance
+ * @retval 0: no conversion is on going on ADC group regular.
+ */
+#define __LL_ADC_REG_IsConversionOngoing(__INSTANCE__) \
+ ((READ_BIT((__INSTANCE__)->CR0, ADC_CR0_ADSTART) == (ADC_CR0_ADSTART)) ? 1UL : 0UL)
+
+/**
+ * @brief Get ADC group regular command of conversion stop state
+ * @param Instance ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group regular.
+ */
+#define __LL_ADC_REG_IsStopConversionOngoing(__INSTANCE__) \
+ ((READ_BIT((__INSTANCE__)->CR0, ADC_CR0_ADSTP) == (ADC_CR0_ADSTP)) ? 1UL : 0UL)
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations.
+ * @param Instance ADC instance
+ * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+#define __LL_ADC_REG_ReadConversionData(__INSTANCE__) (READ_BIT((__INSTANCE__)->DR, ADC_DR_RDATA))
+
+/**
+ * @brief Get ADC group regular every channel conversion data, range fit for
+ * all ADC configurations.
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+#define __LL_ADC_REG_ReadChannelConversionData(__INSTANCE__, __CHANNEL__) \
+ (READ_BIT((__INSTANCE__)->CDR[__CHANNEL__], ADC_CDR_RDATA))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_LL_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+/**
+ * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
+ * Channel to which the offset programmed will be applied
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @param GroupSel value can be one of the following values:
+ * @arg @ref ADC_OFFSET_1
+ * @arg @ref ADC_OFFSET_2
+ * @arg @ref ADC_OFFSET_3
+ * @arg @ref ADC_OFFSET_4
+ */
+#define __LL_ADC_SetCalGroup(__INSTANCE__, __CHANNEL__, __GROUPSEL__) \
+ (__CHANNEL__ > 7) ? \
+ MODIFY_REG((__INSTANCE__)->CALR1, ADC_CALR1_CAL8 << ((__CHANNEL__ - 8) << ADC_SMPRX_REGOFFSET), \
+ ((__GROUPSEL__) << ((__CHANNEL__ - 8) << ADC_SMPRX_REGOFFSET))) : \
+ MODIFY_REG((__INSTANCE__)->CALR0, ADC_CALR0_CAL0 << ((__CHANNEL__) << ADC_SMPRX_REGOFFSET), \
+ ((__GROUPSEL__) << ((__CHANNEL__) << ADC_SMPRX_REGOFFSET)))
+
+
+/**
+ * @brief Set ADC selected offset number 1, 2, 3 or 4.
+ * @note This function set the 2 items of offset configuration:
+ * - ADC channel to which the offset programmed will be applied
+ * (Single mode)
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note This function enables the offset, by default. It can be forced
+ * to disable state using function LL_ADC_SetOffsetState().
+ * @param Instance ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref ADC_OFFSET_1
+ * @arg @ref ADC_OFFSET_2
+ * @arg @ref ADC_OFFSET_3
+ * @arg @ref ADC_OFFSET_4
+ * @param OffsetValue Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+#define __LL_ADC_SetOffset(__INSTANCE__, __OFFSETY__, __VALUE__) \
+ MODIFY_REG((__INSTANCE__)->OFR[__OFFSETY__], ADC_OFR0_OFFSET, (__VALUE__))
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Offset level (offset to be subtracted from the raw
+ * converted data). Single mode.
+ * @param Instance ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref ADC_OFFSET_1
+ * @arg @ref ADC_OFFSET_2
+ * @arg @ref ADC_OFFSET_3
+ * @arg @ref ADC_OFFSET_4
+ * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+#define __LL_ADC_GetOffset(__INSTANCE__, __OFFSETY__) READ_BIT((__INSTANCE__)->OFR[__OFFSETY__], ADC_OFR0_OFFSET)
+
+/**
+ * @brief Set ADC selected gain compensation number 1, 2, 3 or 4.Single mode.
+ * @note This function set the gain compensation coefficient
+ * that is applied to raw converted data using the formula:
+ * DATA = DATA(raw) * (gain compensation coef) >> 12
+ * @param Instance ADC instance
+ * @param Gainy This parameter can be one of the following values:
+ * @arg @ref ADC_GAIN_1
+ * @arg @ref ADC_GAIN_2
+ * @arg @ref ADC_GAIN_3
+ * @arg @ref ADC_GAIN_4
+ * @param GainCompensation This parameter can be:
+ * 0 Gain compensation will be disabled and value set to 0
+ * 1 -> 8192 Gain compensation will be enabled with specified value(default)
+ * @retval None
+ */
+#define __LL_ADC_SetGainCompensation(__INSTANCE__,__GAINY__, __VALUE__) \
+ MODIFY_REG((__INSTANCE__)->GCR[(__GAINY__)], ADC_GCR0_GAIN, (__VALUE__))
+
+/**
+ * @brief Get the ADC gain compensation value
+ * @param Instance ADC instance
+ * @param Gainy This parameter can be one of the following values:
+ * @arg @ref ADC_GAIN_1
+ * @arg @ref ADC_GAIN_2
+ * @arg @ref ADC_GAIN_3
+ * @arg @ref ADC_GAIN_4
+ * @retval Returned value can be:
+ * 0 Gain compensation is disabled
+ * 1 -> 8192 Gain compensation is enabled with returned value
+ */
+#define __LL_ADC_GetGainCompensation(__INSTANCE__,__GAINY__) READ_BIT((__INSTANCE__)->GCR[(__GAINY__)], ADC_GCR0_GAIN)
+
+/**
+ * @brief Set ADC selected offset number 1, 2, 3 or 4.
+ * @note This function set the 2 items of offset configuration:
+ * - ADC channel to which the offset programmed will be applied
+ * (Single mode)
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note This function enables the offset, by default. It can be forced
+ * to disable state using function LL_ADC_SetOffsetState().
+ * @param Instance ADC instance
+ * @param Doffsety This parameter can be one of the following values:
+ * @arg @ref ADC_OFFSET_1
+ * @arg @ref ADC_OFFSET_2
+ * @arg @ref ADC_OFFSET_3
+ * @arg @ref ADC_OFFSET_4
+ * @param OffsetValue Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+#define __LL_ADC_SetDiffOffset(__INSTANCE__, __DOFFSETY__, __VALUE__) \
+ MODIFY_REG((__INSTANCE__)->DOFR[(__DOFFSETY__)], ADC_DOFR0_OFFSET, (__VALUE__))
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Offset level (offset to be subtracted from the raw
+ * converted data). Single mode.
+ * @param Instance ADC instance
+ * @param Doffsety This parameter can be one of the following values:
+ * @arg @ref ADC_OFFSET_1
+ * @arg @ref ADC_OFFSET_2
+ * @arg @ref ADC_OFFSET_3
+ * @arg @ref ADC_OFFSET_4
+ * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+#define __LL_ADC_GetDiffOffset(__INSTANCE__, __DOFFSETY__) READ_BIT((__INSTANCE__)->DOFR[(__DOFFSETY__)], ADC_DOFR0_OFFSET)
+
+/**
+ * @brief Set ADC selected gain compensation number 1, 2, 3 or 4.Single mode.
+ * @note This function set the gain compensation coefficient
+ * that is applied to raw converted data using the formula:
+ * DATA = DATA(raw) * (gain compensation coef) >> 12
+ * @param Instance ADC instance
+ * @param Dgainy This parameter can be one of the following values:
+ * @arg @ref ADC_GAIN_1
+ * @arg @ref ADC_GAIN_2
+ * @arg @ref ADC_GAIN_3
+ * @arg @ref ADC_GAIN_4
+ * @param GainCompensation This parameter can be:
+ * 0 Gain compensation will be disabled and value set to 0
+ * 1 -> 8192 Gain compensation will be enabled with specified value(default)
+ * @retval None
+ */
+#define __LL_ADC_SetDiffGainCompensation(__INSTANCE__,__DGAINY__, __VALUE__) \
+ MODIFY_REG((__INSTANCE__)->DGCR[(__DGAINY__)], ADC_DGCR0_GAIN, (__VALUE__))
+
+/**
+ * @brief Get the ADC gain compensation value ,Differential.
+ * @param Instance ADC instance
+ * @param Dgainy This parameter can be one of the following values:
+ * @arg @ref ADC_GAIN_1
+ * @arg @ref ADC_GAIN_2
+ * @arg @ref ADC_GAIN_3
+ * @arg @ref ADC_GAIN_4
+ * @retval Returned value can be:
+ * 0 Gain compensation is disabled
+ * 1 -> 8192 Gain compensation is enabled with returned value
+ */
+#define __LL_ADC_GetDiffGainCompensation(__INSTANCE__,__DGAINY__) READ_BIT((__INSTANCE__)->DGCR[(__DGAINY__)], ADC_DGCR0_GAIN)
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note setting trigger source to external trigger
+ * also set trigger polarity to rising edge.
+ * ADC must be without conversion on going on group regular.
+ * @param Instance ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref ADC_REG_TRIG_SOFTWARE)
+ * @arg @ref ADC_REG_TRIG_EXT_TIM0_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM1_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM2_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM3_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM4_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM5_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM6_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM7_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM0_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM5_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM7_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG0
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG1
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG2
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG3
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG4
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG5
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG6
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG7
+ * @arg @ref ADC_REG_TRIG_EXT_PIN
+ * @retval None
+ */
+#define __LL_ADC_REG_SetTriggerSource(__INSTANCE__, __TRIGSRC__) \
+ MODIFY_REG((__INSTANCE__)->LR, ADC_LR_EXTEN | ADC_LR_EXTSEL, (__TRIGSRC__))
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_REG_TRIG_SOFTWARE)
+ * @arg @ref ADC_REG_TRIG_EXT_TIM0_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM1_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM2_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM3_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM4_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM5_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM6_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM7_CC
+ * @arg @ref ADC_REG_TRIG_EXT_TIM0_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM5_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_TIM7_TRGO
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG0
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG1
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG2
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG3
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG4
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG5
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG6
+ * @arg @ref ADC_REG_TRIG_EXT_HRPWM_ADC_TRG7
+ * @arg @ref ADC_REG_TRIG_EXT_PIN)
+ */
+#define __LL_ADC_REG_GetTriggerSource(__INSTANCE__) (READ_BIT((__INSTANCE__)->LR, ADC_LR_EXTSEL)
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ * or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @param Instance ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+#define __LL_ADC_REG_IsTriggerSourceSWStart(__INSTANCE__) \
+ ((READ_BIT((__INSTANCE__)->LR, ADC_LR_EXTEN) == (ADC_REG_TRIG_SOFTWARE)) ? 1UL : 0UL)
+
+/**
+ * @brief Set ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @param Instance ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref ADC_REG_TRIG_EXT_RISING
+ * @arg @ref ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref ADC_REG_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+#define __LL_ADC_REG_SetTriggerEdge(__INSTANCE__, __EXIT_EDGE__) MODIFY_REG((__INSTANCE__)->LR, ADC_LR_EXTEN, (__EXIT_EDGE__))
+
+/**
+ * @brief Get ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_REG_TRIG_EXT_RISING
+ * @arg @ref ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref ADC_REG_TRIG_EXT_RISINGFALLING
+ */
+#define __LL_ADC_REG_GetTriggerEdge(__INSTANCE__) READ_BIT((__INSTANCE__)->LR, ADC_LR_EXTEN)
+
+/**
+ * @brief Set ADC group regular sequencer length.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * @note Sequencer length value 0 is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @param Instance ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref ADC_REG_SEQ_ENABLE_1
+ * @arg @ref ADC_REG_SEQ_ENABLE_2
+ * @arg @ref ADC_REG_SEQ_ENABLE_3
+ * @arg @ref ADC_REG_SEQ_ENABLE_4
+ * @arg @ref ADC_REG_SEQ_ENABLE_5
+ * @arg @ref ADC_REG_SEQ_ENABLE_6
+ * @arg @ref ADC_REG_SEQ_ENABLE_7
+ * @arg @ref ADC_REG_SEQ_ENABLE_8
+ * @arg @ref ADC_REG_SEQ_ENABLE_9
+ * @arg @ref ADC_REG_SEQ_ENABLE_10
+ * @arg @ref ADC_REG_SEQ_ENABLE_11
+ * @arg @ref ADC_REG_SEQ_ENABLE_12
+ * @arg @ref ADC_REG_SEQ_ENABLE_13
+ * @arg @ref ADC_REG_SEQ_ENABLE_14
+ * @arg @ref ADC_REG_SEQ_ENABLE_15
+ * @arg @ref ADC_REG_SEQ_ENABLE_16
+ * @retval None
+ */
+#define __LL_ADC_REG_SetSequencerLength(__INSTANCE__, __SEQUENCERANKS__) \
+ MODIFY_REG((__INSTANCE__)->LR, ADC_LR_LEN, (__SEQUENCERANKS__))
+
+/**
+ * @brief Get ADC group regular sequencer length.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * @note Sequencer length value 0 is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_REG_SEQ_ENABLE_1
+ * @arg @ref ADC_REG_SEQ_ENABLE_2
+ * @arg @ref ADC_REG_SEQ_ENABLE_3
+ * @arg @ref ADC_REG_SEQ_ENABLE_4
+ * @arg @ref ADC_REG_SEQ_ENABLE_5
+ * @arg @ref ADC_REG_SEQ_ENABLE_6
+ * @arg @ref ADC_REG_SEQ_ENABLE_7
+ * @arg @ref ADC_REG_SEQ_ENABLE_8
+ * @arg @ref ADC_REG_SEQ_ENABLE_9
+ * @arg @ref ADC_REG_SEQ_ENABLE_10
+ * @arg @ref ADC_REG_SEQ_ENABLE_11
+ * @arg @ref ADC_REG_SEQ_ENABLE_12
+ * @arg @ref ADC_REG_SEQ_ENABLE_13
+ * @arg @ref ADC_REG_SEQ_ENABLE_14
+ * @arg @ref ADC_REG_SEQ_ENABLE_15
+ * @arg @ref ADC_REG_SEQ_ENABLE_16
+ */
+#define __LL_ADC_REG_GetSequencerLength(__INSTANCE__) READ_BIT((__INSTANCE__)->LR, ADC_LR_LEN)
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @param Instance ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref ADC_REG_SEQ_DISCON_DISABLE
+ * @arg @ref ADC_REG_SEQ_DISNUM_1
+ * @arg @ref ADC_REG_SEQ_DISNUM_2
+ * @arg @ref ADC_REG_SEQ_DISNUM_3
+ * @arg @ref ADC_REG_SEQ_DISNUM_4
+ * @arg @ref ADC_REG_SEQ_DISNUM_5
+ * @arg @ref ADC_REG_SEQ_DISNUM_6
+ * @arg @ref ADC_REG_SEQ_DISNUM_7
+ * @arg @ref ADC_REG_SEQ_DISNUM_8
+ * @retval None
+ */
+#define __LL_ADC_REG_SetSequencerDiscont(__INSTANCE__, __SEQDISCONT__) \
+ MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, (__SEQDISCONT__))
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref ADC_REG_SEQ_DISCONT_1
+ * @arg @ref ADC_REG_SEQ_DISCONT_2
+ * @arg @ref ADC_REG_SEQ_DISCONT_3
+ * @arg @ref ADC_REG_SEQ_DISCONT_4
+ * @arg @ref ADC_REG_SEQ_DISCONT_5
+ * @arg @ref ADC_REG_SEQ_DISCONT_6
+ * @arg @ref ADC_REG_SEQ_DISCONT_7
+ * @arg @ref ADC_REG_SEQ_DISCONT_8
+ */
+#define __LL_ADC_REG_GetSequencerDiscont(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note ADC group regular sequencer is fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @param Instance ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref ADC_REG_RANK_1
+ * @arg @ref ADC_REG_RANK_2
+ * @arg @ref ADC_REG_RANK_3
+ * @arg @ref ADC_REG_RANK_4
+ * @arg @ref ADC_REG_RANK_5
+ * @arg @ref ADC_REG_RANK_6
+ * @arg @ref ADC_REG_RANK_7
+ * @arg @ref ADC_REG_RANK_8
+ * @arg @ref ADC_REG_RANK_9
+ * @arg @ref ADC_REG_RANK_10
+ * @arg @ref ADC_REG_RANK_11
+ * @arg @ref ADC_REG_RANK_12
+ * @arg @ref ADC_REG_RANK_13
+ * @arg @ref ADC_REG_RANK_14
+ * @arg @ref ADC_REG_RANK_15
+ * @arg @ref ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @retval None
+ */
+#define __LL_ADC_REG_SetSequencerRanks(__INSTANCE__, __RANK__, __CHANNEL__) \
+ (__RANK__) > 7 ? \
+ MODIFY_REG((__INSTANCE__)->SQR1, ADC_SQR1_SQ9 << ((__RANK__ - 8) << ADC_SMPRX_REGOFFSET), \
+ ((__CHANNEL__) << ((__RANK__ - 8) << ADC_SMPRX_REGOFFSET))) : \
+ MODIFY_REG((__INSTANCE__)->SQR0, ADC_SQR0_SQ1 << ((__RANK__) << ADC_SMPRX_REGOFFSET), \
+ ((__CHANNEL__) << ((__RANK__) << ADC_SMPRX_REGOFFSET)))
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note ADC group regular sequencer is fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @param Instance ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref ADC_REG_RANK_1
+ * @arg @ref ADC_REG_RANK_2
+ * @arg @ref ADC_REG_RANK_3
+ * @arg @ref ADC_REG_RANK_4
+ * @arg @ref ADC_REG_RANK_5
+ * @arg @ref ADC_REG_RANK_6
+ * @arg @ref ADC_REG_RANK_7
+ * @arg @ref ADC_REG_RANK_8
+ * @arg @ref ADC_REG_RANK_9
+ * @arg @ref ADC_REG_RANK_10
+ * @arg @ref ADC_REG_RANK_11
+ * @arg @ref ADC_REG_RANK_12
+ * @arg @ref ADC_REG_RANK_13
+ * @arg @ref ADC_REG_RANK_14
+ * @arg @ref ADC_REG_RANK_15
+ * @arg @ref ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ */
+#define __LL_ADC_REG_GetSequencerRanks(__INSTANCE__, __RANK__) \
+ (__RANK__) > 7 ? \
+ (READ_BIT((__INSTANCE__)->SQR1, ADC_SQR1_SQ9 << ((__RANK__ - 8) << ADC_SMPRX_REGOFFSET))) : \
+ (READ_BIT((__INSTANCE__)->SQR0, ADC_SQR0_SQ1 << ((__RANK__) << ADC_SMPRX_REGOFFSET)))
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @param Instance ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref ADC_REG_CONV_SINGLE
+ * @arg @ref ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+#define __LL_ADC_REG_SetContinuousMode(__INSTANCE__, __COUNT__) MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_CONT, (__COUNT__))
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_REG_CONV_SINGLE
+ * @arg @ref ADC_REG_CONV_CONTINUOUS
+ */
+#define __LL_ADC_REG_GetContinuousMode(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_CONT)
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA.
+ * @note If transfer by DMA selected, This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA is set to single and DMA is set to mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular.
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref ADC_REG_DMA_TRANSFER_SINGLE
+ * @arg @ref ADC_REG_DMA_TRANSFER_CIRCLE
+ * @retval None
+ */
+#define __LL_ADC_REG_SetDMATransfer(__INSTANCE__, __CHANNLE__, __DMAMODE__) \
+ MODIFY_REG((__INSTANCE__)->DMA_CR[__CHANNLE__].TCR, ADC_DMA_TCR_CIRC | ADC_DMA_TCR_START, (__DMAMODE__))
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA.
+ * @note If transfer by DMA selected:
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA is set to single and DMA is set to mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_REG_DMA_TRANSFER_SINGLE
+ * @arg @ref ADC_REG_DMA_TRANSFER_CIRCLE
+ */
+#define __LL_ADC_REG_GetDMATransfer(__INSTANCE__, __CHANNLE__) \
+ READ_BIT((__INSTANCE__)->DMA_CR[__CHANNLE__].TCR, ADC_DMA_TCR_CIRC | ADC_DMA_TCR_START)
+
+/**
+ * @brief Set the DMA transfer address.
+ * @note If transfer by DMA selected:
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA is set to single and DMA is set to mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @param Address dma transfer buffer addresss
+ * @retval None
+ */
+#define __LL_ADC_REG_SetDMAAddr(__INSTANCE__, __CHANNLE__, __ADDR__) \
+ MODIFY_REG((__INSTANCE__)->DMA_CR[__CHANNLE__].TAR, ADC_DMA_TAR_ADDR, (__ADDR__))
+
+/**
+ * @brief Set the DMA transfer length
+ * @param __INSTANCE__ Special ADC Peripheral
+ * @param __CHANNLE__ ADC Channel
+ * @param __LENGTH__ dma transfer length
+ * @return None
+ */
+#define __LL_ADC_REG_SetDMALength(__INSTANCE__, __CHANNLE__, __LENGTH__) \
+ MODIFY_REG((__INSTANCE__)->DMA_CR[__CHANNLE__].TLR, ADC_DMA_TLR_LENG, (__LENGTH__))
+
+/**
+ * @brief Set ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @note Compatibility with devices without feature overrun:
+ * other devices without this feature have a behavior
+ * equivalent to data overwritten.
+ * The default setting of overrun is data preserved.
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @param Instance ADC instance
+ * @param Overrun This parameter can be one of the following values:
+ * @arg @ref ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref ADC_REG_OVR_DATA_OVERWRITTEN
+ * @retval None
+ */
+#define __LL_ADC_REG_SetOverrun(__INSTANCE__, __OVRRUN__) MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_OVRMOD, (__OVRRUN__))
+
+/**
+ * @brief Get ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref ADC_REG_OVR_DATA_OVERWRITTEN
+ */
+#define __LL_ADC_REG_GetOverrun(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_OVRMOD)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note setting trigger source to external trigger also set trigger polarity to rising edge
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM0_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM1_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM2_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM3_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM4_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM5_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM6_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM7_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM0_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM5_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM7_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG0
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG1
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG2
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG3
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG4
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG5
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG6
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG7
+ * @arg @ref ADC_INJ_TRIG_EXT_PIN
+ * @retval None
+ */
+#define __LL_ADC_INJ_SetTriggerSource(__INSTANCE__, __TRIGSRC__) \
+ MODIFY_REG((__INSTANCE__)->JLR, ADC_JLR_JEXTSEL | ADC_JLR_JEXTEN, (__TRIGSRC__))
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * @note setting trigger source to external trigger also set trigger polarity to rising edge
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM0_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM1_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM2_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM3_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM4_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM5_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM6_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM7_CC
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM0_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM5_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_TIM7_TRGO
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG0
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG1
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG2
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG3
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG4
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG5
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG6
+ * @arg @ref ADC_INJ_TRIG_EXT_HRPWM_ADC_TRG7
+ * @arg @ref ADC_INJ_TRIG_EXT_PIN
+ * @retval None
+ */
+#define __LL_ADC_INJ_GetTriggerSource(__INSTANCE__) READ_BIT((__INSTANCE__)->JLR, ADC_JLR_JEXTSEL)
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @param Instance ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+#define __LL_ADC_INJ_IsTriggerSourceSWStart(__INSTANCE__) \
+ ((READ_BIT((__INSTANCE__)->JLR, ADC_JLR_JEXTEN) == (ADC_INJ_TRIG_SOFTWARE & ADC_JLR_JEXTEN)) ? 1UL : 0UL)
+
+/**
+ * @brief Set ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref ADC_INJ_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+#define __LL_ADC_INJ_SetTriggerEdge(__INSTANCE__, __TRIG_EDGE__) \
+ MODIFY_REG((__INSTANCE__)->JLR, ADC_JLR_JEXTEN, (__TRIG_EDGE__))
+
+/**
+ * @brief Get ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref ADC_INJ_TRIG_EXT_RISINGFALLING
+ */
+#define __LL_ADC_INJ_GetTriggerEdge(__INSTANCE__) READ_BIT((__INSTANCE__)->JLR, ADC_JLR_JEXTEN)
+
+/**
+ * @brief Set ADC group injected sequencer length.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_SEQ_LENGTH_1
+ * @arg @ref ADC_INJ_SEQ_LENGTH_2
+ * @arg @ref ADC_INJ_SEQ_LENGTH_3
+ * @arg @ref ADC_INJ_SEQ_LENGTH_4
+ * @retval None
+ */
+#define __LL_ADC_INJ_SetSequencerLength(__INSTANCE__, __SEQUENCERANK__) \
+ MODIFY_REG((__INSTANCE__)->JLR, ADC_JLR_JLEN, (__SEQUENCERANK__))
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_INJ_SEQ_LENGTH_1
+ * @arg @ref ADC_INJ_SEQ_LENGTH_2
+ * @arg @ref ADC_INJ_SEQ_LENGTH_3
+ * @arg @ref ADC_INJ_SEQ_LENGTH_4
+ */
+#define __LL_ADC_INJ_GetSequencerLength(__INSTANCE__) READ_BIT((__INSTANCE__)->JLR, ADC_JLR_JLEN)
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @param Instance ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref ADC_INJ_SEQ_DISCONT_ENABLE
+ * @retval None
+ */
+#define __LL_ADC_INJ_SetSequencerDiscont(__INSTANCE__, __SEQDISCONT__) \
+ MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_JDISCEN, (__SEQDISCONT__))
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref ADC_INJ_SEQ_DISCONT_ENABLE
+ */
+#define __LL_ADC_INJ_GetSequencerDiscont(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_JDISCEN)
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * @note setting of this feature is conditioned to ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups injected.
+ * @param Instance ADC instance
+ * @param Rank Position This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_RANK_1
+ * @arg @ref ADC_INJ_RANK_2
+ * @arg @ref ADC_INJ_RANK_3
+ * @arg @ref ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @retval None
+ */
+#define __LL_ADC_INJ_SetSequencerRanks(__INSTANCE__, __RANK__, __CHANNEL__) \
+ MODIFY_REG((__INSTANCE__)->JSQR, (ADC_JSQR_JSQ1 << (__RANK__)), (__CHANNEL__) << (__RANK__))
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note setting of this feature is conditioned to ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_RANK_1
+ * @arg @ref ADC_INJ_RANK_2
+ * @arg @ref ADC_INJ_RANK_3
+ * @arg @ref ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @retval None
+ */
+#define __LL_ADC_INJ_GetSequencerRanks(__INSTANCE__, __RANK__) READ_BIT((__INSTANCE__)->JSQR, (ADC_JSQR_JSQ1 << (__RANK__)))
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept , up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+#define __LL_ADC_INJ_SetTrigAuto(__INSTANCE__, __TRIGAUTO__) MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_JAUTO, (__TRIGAUTO__))
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+#define __LL_ADC_INJ_GetTrigAuto(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_JAUTO)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+/**
+ * @brief Set sampling time of the selected ADC channel Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * ADC processing time is: 12.5 ADC clock cycles at ADC resolution 12 bits
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref ADC_SAMPLINGTIME_6CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_18CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_42CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_90CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_186CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_378CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_762CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_1530CYCLES
+ * @retval None
+ */
+
+#define __LL_ADC_SetChannelSamplingTime(__INSTANCE__, __CHANNEL__, __SAMPTIME__) \
+ (__CHANNEL__ > 7) ? \
+ MODIFY_REG((__INSTANCE__)->SMPR1, ADC_SMPR1_SMP8 << ((__CHANNEL__ - 8) << ADC_SMPRX_REGOFFSET), \
+ ((__SAMPTIME__) << ((__CHANNEL__ - 8) << ADC_SMPRX_REGOFFSET))) : \
+ MODIFY_REG((__INSTANCE__)->SMPR0, ADC_SMPR0_SMP0 << ((__CHANNEL__) << ADC_SMPRX_REGOFFSET), \
+ ((__SAMPTIME__) << ((__CHANNEL__) << ADC_SMPRX_REGOFFSET)))
+
+/**
+ * @brief Get sampling time of the selected ADC channel Unit: ADC clock cycles.
+ * @note sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref ADC_SAMPLINGTIME_6CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_18CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_42CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_90CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_186CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_378CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_762CYCLES
+ * @arg @ref ADC_SAMPLINGTIME_1530CYCLES
+ */
+#define __LL_ADC_GetChannelSamplingTime(__INSTANCE__, __CHANNEL__) (__CHANNEL__ > 7) ? \
+ (READ_BIT((__INSTANCE__)->SMPR1, ADC_SMPR1_SMP8 << (((__CHANNEL__ - 8) << ADC_SMPRX_REGOFFSET)))) : \
+ (READ_BIT((__INSTANCE__)->SMPR0, ADC_SMPR0_SMP0 << (((__INSTANCE__) << ADC_SMPRX_REGOFFSET))))
+
+
+/**
+ * @brief Set mode single-ended or differential input of the selected
+ * ADC channel.
+ * In differential mode: Differential measurement is carried out
+ * between the selected channel 'i' (positive input) and
+ * channel 'i+1' (negative input). Only channel 'i' has to be
+ * configured, channel 'i+1' is configured automatically.
+ * @note For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.refer to device datasheet
+ * for more details.
+ * @note For ADC channels configured in differential mode, both inputs
+ * should be biased at (Vref+)/2 +/-200mV.
+ * (Vref+ is the analog voltage reference)
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @param SingleDiff This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+#define __LL_ADC_SetChannelSingleDiff(__INSTANCE__, __CHANNEL__, __SINGLEDIFF__) \
+ MODIFY_REG((__INSTANCE__)->DIFSEL, \
+ ADC_SINGLEDIFF_CHANNEL_SHIFT << (__CHANNEL__), \
+ (((__SINGLEDIFF__) & ADC_SINGLEDIFF_CHANNEL_SHIFT) << (__CHANNEL__)))
+
+/**
+ * @brief Get mode single-ended or differential input of the selected
+ * ADC channel.
+ * In differential mode: Differential measurement is carried out
+ * between the selected channel 'i' (positive input) and
+ * channel 'i+1' (negative input). Only channel 'i' has to be
+ * configured, channel 'i+1' is configured automatically.
+ * @note For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.refer to device datasheet
+ * for more details.
+ * @note For ADC channels configured in differential mode, both inputs
+ * should be biased at (Vref+)/2 +/-200mV.
+ * (Vref+ is the analog voltage reference)
+ * @param Instance ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR
+ * @retval SingleDiff This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ */
+#define __LL_ADC_GetChannelSingleDiff(__INSTANCE__, __CHANNEL__) \
+ ((READ_BIT((__INSTANCE__)->DIFSEL, ADC_SINGLEDIFF_CHANNEL_SHIFT << (__CHANNEL__)) == \
+ (ADC_SINGLEDIFF_CHANNEL_SHIFT << (__CHANNEL__))) ? 0x1U : 0x0U)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel, multiple channels or all channels,
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * @note Analog watchdog instance:
+ * - AWD standard (instance AWD0\1\2):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref ADC_AWD0
+ * @arg @ref ADC_AWD1
+ * @arg @ref ADC_AWD2
+ * @param AWDChannelGroup This parameter can combination of the following values:
+ * @arg @ref ADC_AWD_DISABLE
+ * @arg @ref ADC_AWD_ALL_CHANNELS
+ * @arg @ref ADC_AWD_CHANNEL_0
+ * @arg @ref ADC_AWD_CHANNEL_1
+ * @arg @ref ADC_AWD_CHANNEL_2
+ * @arg @ref ADC_AWD_CHANNEL_3
+ * @arg @ref ADC_AWD_CHANNEL_4
+ * @arg @ref ADC_AWD_CHANNEL_5
+ * @arg @ref ADC_AWD_CHANNEL_6
+ * @arg @ref ADC_AWD_CHANNEL_7
+ * @arg @ref ADC_AWD_CHANNEL_8
+ * @arg @ref ADC_AWD_CHANNEL_9
+ * @arg @ref ADC_AWD_CHANNEL_10
+ * @arg @ref ADC_AWD_CHANNEL_11
+ * @retval None
+ */
+#define __LL_ADC_SetAnalogWDMonitChannels(__INSTANCE__, __AWDY__, __AWDCHANNEL__) \
+ MODIFY_REG((__INSTANCE__)->AWDCR[__AWDY__], ADC_AWD0CR_AWD0CH, __AWDCHANNEL__)
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * @note Once monitored channels are selected, analog watchdog is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * @param Instance ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref ADC_AWD0
+ * @arg @ref ADC_AWD1
+ * @arg @ref ADC_AWD2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_AWD_DISABLE
+ * @arg @ref ADC_AWD_ALL_CHANNELS
+ * @arg @ref ADC_AWD_CHANNEL_0
+ * @arg @ref ADC_AWD_CHANNEL_1
+ * @arg @ref ADC_AWD_CHANNEL_2
+ * @arg @ref ADC_AWD_CHANNEL_3
+ * @arg @ref ADC_AWD_CHANNEL_4
+ * @arg @ref ADC_AWD_CHANNEL_5
+ * @arg @ref ADC_AWD_CHANNEL_6
+ * @arg @ref ADC_AWD_CHANNEL_7
+ * @arg @ref ADC_AWD_CHANNEL_8
+ * @arg @ref ADC_AWD_CHANNEL_9
+ * @arg @ref ADC_AWD_CHANNEL_10
+ * @arg @ref ADC_AWD_CHANNEL_11
+ */
+#define __LL_ADC_GetAnalogWDMonitChannels(__INSTANCE__, __AWDY__) \
+ READ_BIT((Instance->AWDCR[AWDy]), ADC_AWD0CR_AWD0CH & ADC_AWD_ALL_CHANNELS)
+
+/**
+ * @brief Set ADC analog watchdog thresholds value of both thresholds
+ * high and low.
+ * @note If value of only one threshold high or low must be set,
+ * use function @ref LL_ADC_SetAnalogWDThresholds().
+ * @note In case of ADC resolution different of 16 bits.
+ * @note Analog watchdog instance:
+ * - AWD standard (instance AWD0\1\2):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * @note ADC data register bitfield [15:0] (16 most significant bits).
+ * @param Instance ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref ADC_AWD0
+ * @arg @ref ADC_AWD1
+ * @arg @ref ADC_AWD2
+ * @param AWDThresholdHighValue Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @param AWDThresholdLowValue Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+#define __LL_ADC_ConfigAnalogWDThresholds(__INSTANCE__, __AWDY__, __HIGHVALUE__, __LOWVALUE__) \
+ WRITE_REG((__INSTANCE__)->TR[__AWDY__], ((__HIGHVALUE__) << ADC_AWD_THRESHOLDS_HIGH_POS) | (__LOWVALUE__))
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note If value of only one threshold high or low must be set,
+ * use function @ref LL_ADC_SetAnalogWDThresholds().
+ * @note In case of ADC resolution different of 16 bits.
+ * @note Analog watchdog instance:
+ * - AWD standard (instance AWD0\1\2):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * @note ADC data register bitfield [15:0] (16 most significant bits).
+ * @param Instance ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref ADC_AWD0
+ * @arg @ref ADC_AWD1
+ * @arg @ref ADC_AWD2
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+#define __LL_ADC_SetAnalogWDThresholds(__INSTANCE__, __AWDY__, __SIGN__, __VALUE__) \
+ MODIFY_REG((__INSTANCE__)->TR[__AWDY__], (__SIGN__), \
+ ((((__VALUE__) << ADC_AWD_THRESHOLDS_HIGH_POS) | (__VALUE__)) & __SIGN__))
+
+/**
+ * @brief Set ADC analog watchdog filtering configuration
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref ADC_AWD0\1\2
+ * @param FilteringConfig This parameter can be one of the following values:
+ * @arg @ref ADC_AWD_FILTERING_NONE
+ * @arg @ref ADC_AWD_FILTERING_2
+ * @arg @ref ADC_AWD_FILTERING_3
+ * @arg @ref ADC_AWD_FILTERING_4
+ * @arg @ref ADC_AWD_FILTERING_5
+ * @arg @ref ADC_AWD_FILTERING_6
+ * @arg @ref ADC_AWD_FILTERING_7
+ * @arg @ref ADC_AWD_FILTERING_8
+ * @arg @ref ADC_AWD_FILTERING_9
+ * @arg @ref ADC_AWD_FILTERING_10
+ * @arg @ref ADC_AWD_FILTERING_11
+ * @arg @ref ADC_AWD_FILTERING_12
+ * @arg @ref ADC_AWD_FILTERING_13
+ * @arg @ref ADC_AWD_FILTERING_14
+ * @arg @ref ADC_AWD_FILTERING_15
+ * @arg @ref ADC_AWD_FILTERING_16
+ * @retval None
+ */
+#define __LL_ADC_SetAWDFilteringConfiguration(__INSTANCE__, __AWDY__, __AWDFILTER__) \
+ MODIFY_REG((__INSTANCE__)->AWDCR[__AWDY__], ADC_AWD0CR_AWD0FILT, (__AWDFILTER__))
+
+/**
+ * @brief Get ADC analog watchdog filtering configuration
+ * @note On this TMF5 serie, this feature is only available on first
+ * analog watchdog (AWD0\1\2)
+ * @param Instance ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref ADC_AWD0\1\2
+ * @param FilteringConfig This parameter can be one of the following values:
+ * @arg @ref ADC_AWD_FILTERING_NONE
+ * @arg @ref ADC_AWD_FILTERING_2
+ * @arg @ref ADC_AWD_FILTERING_3
+ * @arg @ref ADC_AWD_FILTERING_4
+ * @arg @ref ADC_AWD_FILTERING_5
+ * @arg @ref ADC_AWD_FILTERING_6
+ * @arg @ref ADC_AWD_FILTERING_7
+ * @arg @ref ADC_AWD_FILTERING_8
+ * @arg @ref ADC_AWD_FILTERING_9
+ * @arg @ref ADC_AWD_FILTERING_10
+ * @arg @ref ADC_AWD_FILTERING_11
+ * @arg @ref ADC_AWD_FILTERING_12
+ * @arg @ref ADC_AWD_FILTERING_13
+ * @arg @ref ADC_AWD_FILTERING_14
+ * @arg @ref ADC_AWD_FILTERING_15
+ * @arg @ref ADC_AWD_FILTERING_16
+ */
+#define __LL_ADC_GetAWDFilteringConfiguration(__INSTANCE__, __AWDY__) \
+ READ_BIT((__INSTANCE__)->AWDCR[__AWDY__], ADC_AWD0CR_AWD0FILT)
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+ * @{
+ */
+/**
+ * @brief Set ADC oversampling scope: ADC groups regular and-or injected.
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @param Instance ADC instance
+ * @param This parameter can be one of the following values:
+ * @arg @ref ADC_OVS_DISABLE
+ * @arg @ref ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref ADC_OVS_GRP_INJECTED
+ * @arg @ref ADC_OVS_GRP_INJ_REG_RESUMED
+ * @retval None
+ */
+#define __LL_ADC_SetOverSamplingScope(__INSTANCE__, __OVRSCOPE__) \
+ MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_ROVSE | ADC_CR1_JOVSE | ADC_CR1_ROVSM, __OVRSCOPE__)
+
+/**
+ * @brief Get ADC oversampling scope: ADC groups regular and-or injected.
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_OVS_DISABLE
+ * @arg @ref ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref ADC_OVS_GRP_INJECTED
+ * @arg @ref ADC_OVS_GRP_INJ_REG_RESUMED
+ */
+#define __LL_ADC_GetOverSamplingScope(__INSTANCE__) \
+ READ_BIT((__INSTANCE__)->CR1, ADC_CR1_ROVSE | ADC_CR1_JOVSE | ADC_CR1_ROVSM)
+
+/**
+ * @brief Set ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @note oversampling discontinuous mode (triggered mode) can be used only
+ * when oversampling is set on group regular only and in resumed mode.
+ * @param Instance ADC instance
+ * @param OverSamplingDiscont This parameter can be one of the following values:
+ * @arg @ref ADC_OVS_REG_CONT
+ * @arg @ref ADC_OVS_REG_DISCONT
+ * @retval None
+ */
+#define __LL_ADC_SetOverSamplingDiscont(__INSTANCE__, __TROVS__) MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_TROVS, (__TROVS__))
+
+/**
+ * @brief Get ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @param Instance ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_OVS_REG_CONT
+ * @arg @ref ADC_OVS_REG_DISCONT
+ */
+#define __LL_ADC_GetOverSamplingDiscont(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_TROVS)
+
+/**
+ * @brief Set ADC oversampling
+ * (impacting both ADC groups regular and injected)
+ * @note This function set the 2 items of oversampling configuration:
+ * - ratio
+ * - shift
+ * @param Instance ADC instance
+ * @param Ratio This parameter can be one of the following values:
+ * @arg @ref ADC_OVSR_RATIO_2
+ * @arg @ref ADC_OVSR_RATIO_4
+ * @arg @ref ADC_OVSR_RATIO_8
+ * @arg @ref ADC_OVSR_RATIO_16
+ * @arg @ref ADC_OVSR_RATIO_32
+ * @arg @ref ADC_OVSR_RATIO_64
+ * @arg @ref ADC_OVSR_RATIO_128
+ * @arg @ref ADC_OVSR_RATIO_256
+ * @param Shift This parameter can be one of the following values:
+ * @arg @ref ADC_OVSS_SHIFT_NONE
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_1
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_2
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_3
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_4
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_5
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_6
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_7
+ * @arg @ref ADC_OVSS_SHIFT_RIGHT_8
+ * @retval None
+ */
+#define __LL_ADC_ConfigOverSamplingRatioShift(__INSTANCE__, __RATIO__, __SHIFT__) \
+ MODIFY_REG((__INSTANCE__)->CR1, (ADC_CR1_OVSS | ADC_CR1_OVSR), (__SHIFT__ | __RATIO__))
+
+/**
+ * @brief Get ADC oversampling ratio
+ * (impacting both ADC groups regular and injected)
+ * @param Instance ADC instance
+ * @retval Ratio This parameter can be one of the following values:
+ * @arg @ref ADC_OVSR_RATIO_2
+ * @arg @ref ADC_OVSR_RATIO_4
+ * @arg @ref ADC_OVSR_RATIO_8
+ * @arg @ref ADC_OVSR_RATIO_16
+ * @arg @ref ADC_OVSR_RATIO_32
+ * @arg @ref ADC_OVSR_RATIO_64
+ * @arg @ref ADC_OVSR_RATIO_128
+ * @arg @ref ADC_OVSR_RATIO_256
+ */
+#define __LL_ADC_GetOverSamplingRatio(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_OVSR)
+
+/**
+ * @brief Get ADC oversampling shift
+ * (impacting both ADC groups regular and injected)
+ * @param Instance ADC instance
+ * @retval Shift This parameter can be one of the following values:
+ * @arg @ref ADC_OVS_SHIFT_NONE
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_1
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_2
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_3
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_4
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_5
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_6
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_7
+ * @arg @ref ADC_OVS_SHIFT_RIGHT_8
+ */
+#define __LL_ADC_GetOverSamplingShift(__INSTANCE__) READ_BIT((__INSTANCE__)->CR1, ADC_CR1_OVSS)
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+/**
+ * @brief Start ADC group injected conversion.
+ * @note This function is relevant for both internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note Setting of this feature is conditioned to ADC state:
+ * ADC must be enabled without conversion on going on group injected,
+ * without conversion stop command on going on group injected.
+ * @param Instance ADC instance
+ * @retval None
+ */
+#define __LL_ADC_INJ_StartConversion(__INSTANCE__) MODIFY_REG((__INSTANCE__)->CR0, ADC_CR0_BITS_PROPERTY_RS, ADC_CR0_JADSTART)
+
+/**
+ * @brief Stop ADC group injected conversion.
+ * @note Setting of this feature is conditioned to ADC state:
+ * ADC must be enabled with conversion on going on group injected,
+ * without ADC disable command on going.
+ * @param Instance ADC instance
+ * @retval None
+ */
+#define __LL_ADC_INJ_StopConversion(__INSTANCE__) MODIFY_REG((__INSTANCE__)->CR0, ADC_CR0_BITS_PROPERTY_RS, ADC_CR0_JADSTP)
+
+/**
+ * @brief Get ADC group injected conversion state.
+ * @param Instance ADC instance
+ * @retval 0: no conversion is on going on ADC group injected.
+ */
+#define __LL_ADC_INJ_IsConversionOngoing(__INSTANCE__) \
+ ((READ_BIT((__INSTANCE__)->CR0, ADC_CR0_JADSTART) == (ADC_CR0_JADSTART)) ? 1UL : 0UL)
+
+/**
+ * @brief Get ADC group injected command of conversion stop state
+ * @param Instance ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group injected.
+ */
+#define __LL_ADC_INJ_IsStopConversionOngoing(__INSTANCE__) \
+ ((READ_BIT((__INSTANCE__)->CR0, ADC_CR0_JADSTP) == (ADC_CR0_JADSTP)) ? 1UL : 0UL)
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * all ADC configurations.
+ * @param Instance ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref ADC_INJ_RANK_1
+ * @arg @ref ADC_INJ_RANK_2
+ * @arg @ref ADC_INJ_RANK_3
+ * @arg @ref ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+#define __LL_ADC_INJ_ReadConversionData(__INSTANCE__, __RANK__) \
+ READ_BIT((__INSTANCE__)->JDR[(__RANK__) >> ADC_JSQX_REGOFFSET], ADC_JDR0_JDATA)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_ECU related register interface functions are configured in the ADC
+ * @{
+ */
+/**
+ * @brief Sets the source channel for the data Address flag bit.
+ * @note The linkage with the ECU must work in DMA cycle mode.
+ * @param Instance ADC instance
+ * @param GroupSel ADC_ECR_GROUP_SEL
+ * @param Channel ADC_CHANNEL
+ * @retval None
+ */
+#define __LL_ADC_ECU_SetAddrDataFlag(__INSTANCE__, __GROUP__, __CHANNLE__) \
+ MODIFY_REG((__INSTANCE__)->ECR[__GROUP__], ADC_ECR0_ADSRC, ((__CHANNLE__) << ADC_ECR0_ADSRC_Pos))
+
+/**
+ * @brief Set PINGPONG to rise and fall over zero and choose which watchdog to monitor.
+ * @note Try to use different watchdogs for ascending and
+ * descending zero - crossing monitoring.
+ * @param Instance ADC instance
+ * @param GroupSel ADC_ECR_GROUP_SEL
+ * @param UpZeroAWD the range of value AWD0\1\2
+ * @param DownZeroAWD the range of value AWD0\1\2
+ * @retval None
+ */
+#define __LL_ADC_ECU_SetUpDownPPFlag(__INSTANCE__, __GROUP__, __UPAWD__, __DOWNAWD__) \
+ MODIFY_REG((__INSTANCE__)->ECR[__GROUP__], \
+ ADC_ECR0_PSRCU | ADC_ECR0_PSRCD, \
+ (((__UPAWD__) << ADC_ECR0_PSRCU_Pos) | ((__DOWNAWD__) << ADC_ECR0_PSRCD_Pos)))
+
+/**
+ * @brief Set up a watch-dog 2 monitoring channel.
+ * @note The selected channel for ascending and descending zero crossing
+ * monitoring watchdog must be configured to be the same.
+ * @param Instance ADC instance
+ * @param GroupSel ADC_ECR_GROUP_SEL
+ * @param Channel ADC_CHANNEL
+ * @retval None
+ */
+#define __LL_ADC_ECU_SetAWD2Channel(__INSTANCE__, __GROUP__, __CHANNLE__) \
+ MODIFY_REG((__INSTANCE__)->ECR[__GROUP__], ADC_ECR0_AWD2SEL, ((__CHANNLE__) << ADC_ECR0_AWD2SEL_Pos))
+
+/**
+ * @brief Set up a watch-dog 1 monitoring channel.
+ * @note The selected channel for ascending and descending zero crossing
+ * monitoring watchdog must be configured to be the same.
+ * @param Instance ADC instance
+ * @param GroupSel ADC_ECR_GROUP_SEL
+ * @param Channel ADC_CHANNEL
+ * @retval None
+ */
+#define __LL_ADC_ECU_SetAWD1Channel(__INSTANCE__, __GROUP__, __CHANNLE__) \
+ MODIFY_REG((__INSTANCE__)->ECR[__GROUP__], ADC_ECR0_AWD1SEL, ((__CHANNLE__) << ADC_ECR0_AWD1SEL_Pos))
+
+/**
+ * @brief Set up a watch-dog 0 monitoring channel.
+ * @note The selected channel for ascending and descending zero crossing
+ * monitoring watchdog must be configured to be the same.
+ * @param Instance ADC instance
+ * @param GroupSel ADC_ECR_GROUP_SEL
+ * @param Channel ADC_CHANNEL
+ * @retval None
+ */
+#define __LL_ADC_ECU_SetAWD0Channel(__INSTANCE__, __GROUP__, __CHANNLE__) \
+ MODIFY_REG((__INSTANCE__)->ECR[__GROUP__], ADC_ECR0_AWD0SEL, ((__CHANNLE__) << ADC_ECR0_AWD0SEL_Pos))
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_FLAG_Management ADC normal flag management
+ * @{
+ */
+/**
+ * @brief Get flag ADC ready.
+ * @note Flag ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_ADRDY(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_ADRDY) == (ADC_FLAG_ADRDY)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC group regular end of unitary conversion.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_EOC(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_EOC) == (ADC_FLAG_EOC)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_EOS(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_EOS) == (ADC_FLAG_EOS)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC group regular overrun.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_OVR(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_OVR) == (ADC_FLAG_OVR)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC group regular end of sampling phase.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_EOSMP(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_EOSMP) == (ADC_FLAG_EOSMP)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC group injected end of unitary conversion.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_JEOC(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_JEOC) == (ADC_FLAG_JEOC)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_JEOS(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_JEOS) == (ADC_FLAG_JEOS)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC analog watchdog 0 flag
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_AWD0(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_AWD0) == (ADC_FLAG_AWD0)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC analog watchdog 1.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_AWD1(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_AWD1) == (ADC_FLAG_AWD1)) ? 1UL : 0UL)
+
+/**
+ * @brief Get flag ADC analog watchdog 2.
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_AWD2(__INSTANCE__) ((READ_BIT((__INSTANCE__)->ISR, ADC_FLAG_AWD2) == (ADC_FLAG_AWD2)) ? 1UL : 0UL)
+
+/**
+ * @brief Clear flag ADC ready.
+ * @note Flag ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_ADRDY(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_ADRDY)
+
+/**
+ * @brief Clear flag ADC group regular end of unitary conversion.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_EOC(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_EOC)
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_EOS(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_EOS)
+
+/**
+ * @brief Clear flag ADC group regular overrun.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_OVR(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_OVR)
+
+/**
+ * @brief Clear flag ADC group regular end of sampling phase.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_EOSMP(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_EOSMP)
+
+/**
+ * @brief Clear flag ADC group injected end of unitary conversion.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_JEOC(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_JEOC)
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_JEOS(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_JEOS)
+
+/**
+ * @brief Clear flag ADC analog watchdog 0.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_AWD0(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_AWD0)
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_AWD1(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_AWD1)
+
+/**
+ * @brief Clear flag ADC analog watchdog 2.
+ * @param __INSTANCE__ ADC instance
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_AWD2(__INSTANCE__) WRITE_REG((__INSTANCE__)->ISR, ADC_FLAG_AWD2)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_IT_Management ADC IT management
+ * @{
+ */
+/**
+ * @brief Enable the specified ADC interrupt.
+ * @param __INSTANCE__ ADC instance
+ * @param __INTERRUPT__ specifies the ADC flags to clear.
+ * This parameter can be any combination of @ref ADC_Flag_definition:
+ * @arg ADC_IT_ADRDY ADC flag ADC instance ready
+ * @arg ADC_IT_EOC ADC flag ADC group regular end of unitary conversion
+ * @arg ADC_IT_EOS ADC flag ADC group regular end of sequence conversions
+ * @arg ADC_IT_OVR ADC flag ADC group regular overrun
+ * @arg ADC_IT_EOSMP ADC flag ADC group regular end of sampling phase
+ * @arg ADC_IT_JEOC ADC flag ADC group injected end of unitary conversion
+ * @arg ADC_IT_JEOS ADC flag ADC group injected end of sequence conversions
+ * @arg ADC_IT_AWD0 ADC flag ADC analog watchdog 1
+ * @arg ADC_IT_AWD1 ADC flag ADC analog watchdog 2
+ * @arg ADC_IT_AWD2 ADC flag ADC analog watchdog 3
+ * @retval None
+ */
+#define __LL_ADC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->IER, __INTERRUPT__)
+
+/**
+ * @brief Disable the specified ADC interrupt.
+ * @param __INSTANCE__ ADC instance
+ * @param __INTERRUPT__ specifies the TMR flags to clear.
+ * This parameter can be any combination of @ref TMR_Flag_definition:
+ * @arg ADC_IT_ADRDY ADC flag ADC instance ready
+ * @arg ADC_IT_EOC ADC flag ADC group regular end of unitary conversion
+ * @arg ADC_IT_EOS ADC flag ADC group regular end of sequence conversions
+ * @arg ADC_IT_OVR ADC flag ADC group regular overrun
+ * @arg ADC_IT_EOSMP ADC flag ADC group regular end of sampling phase
+ * @arg ADC_IT_JEOC ADC flag ADC group injected end of unitary conversion
+ * @arg ADC_IT_JEOS ADC flag ADC group injected end of sequence conversions
+ * @arg ADC_IT_AWD0 ADC flag ADC analog watchdog 1
+ * @arg ADC_IT_AWD1 ADC flag ADC analog watchdog 2
+ * @arg ADC_IT_AWD2 ADC flag ADC analog watchdog 3
+ * @retval None
+ */
+#define __LL_ADC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->IER, __INTERRUPT__)
+
+/**
+ * @brief Get state of interruption ADC ready
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+
+#define __LL_ADC_GET_IT_ADRDY(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_ADRDY) == (ADC_IT_ADRDY)) ? 1UL : 0UL)
+/**
+ * @brief Get state of interruption ADC group regular end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_EOC(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_EOC) == (ADC_IT_EOC)) ? 1UL : 0UL)
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_EOS(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_EOS) == (ADC_IT_EOS)) ? 1UL : 0UL)
+
+/**
+ * @brief Get state of interruption ADC group regular overrun
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_OVR(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_OVR) == (ADC_IT_OVR)) ? 1UL : 0UL)
+
+/**
+ * @brief Get state of interruption ADC group regular end of sampling
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_EOSMP(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_EOSMP) == (ADC_IT_EOSMP)) ? 1UL : 0UL)
+
+/**
+ * @brief Get state of interruption ADC group injected end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_JEOC(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_JEOC) == (ADC_IT_JEOC)) ? 1UL : 0UL)
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_JEOS(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_JEOS) == (ADC_IT_JEOS)) ? 1UL : 0UL)
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 0
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_AWD0(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_AWD0) == (ADC_IT_AWD0)) ? 1UL : 0UL)
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_AWD1(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_AWD1) == (ADC_IT_AWD1)) ? 1UL : 0UL)
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 2
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_AWD2(__INSTANCE__) ((READ_BIT((__INSTANCE__)->IER, ADC_IT_AWD2) == (ADC_IT_AWD2)) ? 1UL : 0UL)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_SAMP_INT_FLAG ADC Sample interrupt management
+ * @{
+ */
+/**
+ * @brief Enable interruption ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_ENABLE_IT_DONE(__INSTANCE__, __CHANNEL__) \
+ SET_BIT((__INSTANCE__)->SIER, (ADC_SIER_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Disable interruption ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_DISABLE_IT_DONE(__INSTANCE__, __CHANNEL__) \
+ CLEAR_BIT((__INSTANCE__)->SIER, (ADC_SIER_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Get state of interruption Get ADC every channel Sample done.
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_DONE(__INSTANCE__, __CHANNEL__) \
+ ((READ_BIT((__INSTANCE__)->SIER, (ADC_SIER_CHANNEL_0 << (__CHANNEL__))) == \
+ ((ADC_SIER_CHANNEL_0 << (__CHANNEL__)))) ? 1UL : 0UL)
+
+/**
+ * @brief Clear flag ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_DONE(__INSTANCE__, __CHANNEL__) \
+ WRITE_REG((__INSTANCE__)->SISR, (ADC_SISR_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Get flagADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_DONE(__INSTANCE__, __CHANNEL__) \
+ ((READ_BIT((__INSTANCE__)->SISR, (ADC_SISR_CHANNEL_0 << (__CHANNEL__))) == \
+ (ADC_SISR_CHANNEL_0 << (__CHANNEL__))) ? 1UL : 0UL)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_HALF_INT_FLAG ADC Half interrupt management
+ * @{
+ */
+/**
+ * @brief Enable interruption ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_ENABLE_IT_HALF(__INSTANCE__, __CHANNEL__) \
+ SET_BIT((__INSTANCE__)->HIER, (ADC_HIER_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Disable interruption ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_DISABLE_IT_HALF(__INSTANCE__, __CHANNEL__) \
+ CLEAR_BIT((__INSTANCE__)->HIER, (ADC_HIER_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Get state of interruption Get ADC every channel Sample done.
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_HALF(__INSTANCE__, __CHANNEL__) \
+ ((READ_BIT((__INSTANCE__)->HIER, (ADC_HIER_CHANNEL_0 << (__CHANNEL__))) == \
+ ((ADC_HIER_CHANNEL_0 << (__CHANNEL__)))) ? 1UL : 0UL)
+
+/**
+ * @brief Clear flag ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_HALF(__INSTANCE__, __CHANNEL__) \
+ WRITE_REG((__INSTANCE__)->HISR, (ADC_HISR_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Get flagADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_HALF(__INSTANCE__, __CHANNEL__) \
+ ((READ_BIT((__INSTANCE__)->HISR, (ADC_HISR_CHANNEL_0 << (__CHANNEL__))) == \
+ (ADC_HISR_CHANNEL_0 << (__CHANNEL__))) ? 1UL : 0UL)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_FULL_INT_FLAG ADC Full interrupt management
+ * @{
+ */
+/**
+ * @brief Enable interruption ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_ENABLE_IT_FULL(__INSTANCE__, __CHANNEL__) \
+ SET_BIT((__INSTANCE__)->FIER, (ADC_FIER_CHANNEL_0 << (__CHANNEL__)))
+/**
+ * @brief Disable interruption ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_DISABLE_IT_FULL(__INSTANCE__, __CHANNEL__) \
+ CLEAR_BIT((__INSTANCE__)->FIER, (ADC_FIER_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Get state of interruption Get ADC every channel Sample done.
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_IT_FULL(__INSTANCE__, __CHANNEL__) \
+ ((READ_BIT((__INSTANCE__)->FIER, (ADC_FIER_CHANNEL_0 << (__CHANNEL__))) == \
+ ((ADC_FIER_CHANNEL_0 << (__CHANNEL__)))) ? 1UL : 0UL)
+
+/**
+ * @brief Clear flag ADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval None
+ */
+#define __LL_ADC_CLEAR_FLAG_FULL(__INSTANCE__, __CHANNEL__) \
+ WRITE_REG((__INSTANCE__)->FISR, (ADC_FISR_CHANNEL_0 << (__CHANNEL__)))
+
+/**
+ * @brief Get flagADC every channel Sample done.
+ * @param __INSTANCE__ ADC instance
+ * @param Channel 0~11
+ * @retval State of bit (1 or 0).
+ */
+#define __LL_ADC_GET_FLAG_FULL(__INSTANCE__, __CHANNEL__) \
+ ((READ_BIT((__INSTANCE__)->FISR, (ADC_FISR_CHANNEL_0 << (__CHANNEL__))) == \
+ (ADC_FISR_CHANNEL_0 << (__CHANNEL__))) ? 1UL : 0UL)
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_ADC_Init(ADC_TypeDef *Instance, ADC_InitTypeDef *ADC_InitStruct);
+LL_StatusETypeDef LL_ADC_DeInit(ADC_TypeDef *Instance);
+LL_StatusETypeDef LL_ADC_REG_Init(ADC_TypeDef *Instance, ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+LL_StatusETypeDef LL_ADC_INJ_Init(ADC_TypeDef *Instance, ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_MspInit(ADC_TypeDef *Instance);
+void LL_ADC_MspDeInit(ADC_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_ADC_ECU_Config(ADC_TypeDef *Instance, ADC_ECUConfTypeDef *ADC_ECU_Config);
+LL_StatusETypeDef LL_ADC_AnalogWDGConfig(ADC_TypeDef *Instance, ADC_AnalogWDGCfgTypeDef *AnalogWDGConfig);
+LL_StatusETypeDef LL_ADC_DMATransferConfig(ADC_TypeDef *Instance, ADC_DMATransferCfgTypeDef *DMATransferConfig);
+LL_StatusETypeDef LL_ADC_CalibrationConfig(ADC_TypeDef *Instance, ADC_CalibrationTypeDef *CalibrationConfig);
+float LL_ADC_TemperatureCovert(uint16_t voltage_data);
+/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_ADC_AdRdyCallback(ADC_TypeDef *Instance);
+void LL_ADC_EosmpCallback(ADC_TypeDef *Instance);
+void LL_ADC_AnologWD2Callback(ADC_TypeDef *Instance);
+void LL_ADC_AnologWD1Callback(ADC_TypeDef *Instance);
+void LL_ADC_AnologWD0Callback(ADC_TypeDef *Instance);
+void LL_ADC_OverRunCallback(ADC_TypeDef *Instance);
+void LL_ADC_JeosCallback(ADC_TypeDef *Instance);
+void LL_ADC_EosCallback(ADC_TypeDef *Instance);
+void LL_ADC_JeocCallback(ADC_TypeDef *Instance);
+void LL_ADC_EocCallback(ADC_TypeDef *Instance);
+void LL_ADC_SampCallback(ADC_TypeDef *Instance, uint8_t Channel);
+void LL_ADC_HalfCallback(ADC_TypeDef *Instance, uint8_t Channel);
+void LL_ADC_FullCallback(ADC_TypeDef *Instance, uint8_t Channel);
+
+void LL_ADC_NORM_IRQHandler(ADC_TypeDef *Instance);
+void LL_ADC_SAMP_IRQHandler(ADC_TypeDef *Instance, uint8_t Channel);
+void LL_ADC_HALF_IRQHandler(ADC_TypeDef *Instance, uint8_t Channel);
+void LL_ADC_FULL_IRQHandler(ADC_TypeDef *Instance, uint8_t Channel);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC LL Private Macros
+ * @brief ADC LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is ADC synchronization or not
+ * @param __SYNCHRONZATION__ synchronization to judge
+ * @retval 0 isn't ADC synchronization
+ * @retval 1 is ADC synchronization
+ */
+#define IS_ADC_SYNCHRONIZATION(__SYNCHRONZATION__) \
+ ( ((__SYNCHRONZATION__) == ADC_SYNCEN_DIS) \
+ || ((__SYNCHRONZATION__) == ADC_SYNCEN_EN) \
+ )
+
+/**
+ * @brief Judge is ADC over samp mode set or not
+ * @param __OVER_SAMP_MODE__ over samp mode to judge
+ * @retval 0 isn't ADC over samp mode set
+ * @retval 1 is ADC over samp mode set
+ */
+#define IS_ADC_OVERSAMPMODE_SET(__OVER_SAMP_MODE__) \
+ ( ((__OVER_SAMP_MODE__) == ADC_OVS_CONTINUED_MODE) \
+ || ((__OVER_SAMP_MODE__) == ADC_OVS_RESUMED_MODE) \
+ )
+
+/**
+ * @brief Judge is ADC trig over samp or not
+ * @param __TRIG_OVER_SAMP__ trig over samp to judge
+ * @retval 0 isn't ADC trig over samp
+ * @retval 1 is ADC trig over samp
+ */
+#define IS_ADC_TRIGOVERSAMP(__TRIG_OVER_SAMP__) \
+ ( ((__TRIG_OVER_SAMP__) == ADC_OVS_TRIG_CONT) \
+ || ((__TRIG_OVER_SAMP__) == ADC_OVS_TRIG_DISCONT) \
+ )
+
+/**
+ * @brief Judge is ADC over samp shift or not
+ * @param __OVER_SAMP_SHIFT__ over samp shift to judge
+ * @retval 0 isn't ADC over samp shift
+ * @retval 1 is ADC over samp shift
+ */
+#define IS_ADC_OVERSAMPSHIFT(__OVER_SAMP_SHIFT__) \
+ ( ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_NONE) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_1) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_2) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_3) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_4) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_5) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_6) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_7) \
+ || ((__OVER_SAMP_SHIFT__) == ADC_OVSS_SHIFT_RIGHT_8) \
+ )
+
+/**
+ * @brief Judge is ADC over samp ratio or not
+ * @param __OVER_SAMP_RATIO__ over samp ratio to judge
+ * @retval 0 isn't ADC over samp ratio
+ * @retval 1 is ADC over samp ratio
+ */
+#define IS_ADC_OVERSAMPRATIO(__OVER_SAMP_RATIO__) \
+ ( ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_2) \
+ || ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_4) \
+ || ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_8) \
+ || ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_16) \
+ || ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_32) \
+ || ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_64) \
+ || ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_128) \
+ || ((__OVER_SAMP_RATIO__) == ADC_OVSR_RATIO_256) \
+ )
+
+/**
+ * @brief Judge is ADC anolog set or not
+ * @param __ANOLOG_SET__ anolog set to judge
+ * @retval 0 isn't ADC anolog set
+ * @retval 1 is ADC anolog set
+ */
+#define IS_ADC_ANOLOGSET(__ANOLOG_SET__) \
+ ( ((__ANOLOG_SET__) == ADC_ANOLOG_CTL_DEFAULT) \
+ || ((__ANOLOG_SET__) == ADC_ANOLOG_CTL_A_SH) \
+ || ((__ANOLOG_SET__) == ADC_ANOLOG_CTL_A_ADC) \
+ || ((__ANOLOG_SET__) == ADC_ANOLOG_CTL_B_SH) \
+ || ((__ANOLOG_SET__) == ADC_ANOLOG_CTL_B_ADC) \
+ )
+
+/**
+ * @brief Judge is ADC channel or not
+ * @param __ADC_CHANNEL__ ADC channel to judge
+ * @retval 0 isn't ADC channel
+ * @retval 1 is ADC channel
+ */
+#define IS_ADC_CHANNEL(__ADC_CHANNEL__) \
+ ( ((__ADC_CHANNEL__) == ADC_CHANNEL_0) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_1) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_2) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_3) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_4) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_5) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_6) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_7) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_8) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_9) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_10) \
+ || ((__ADC_CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \
+ )
+
+
+/**
+ * @brief Judge is ADC reg trig source or not
+ * @param __REG_TRIG_SOURCE__ reg trig source to judge
+ * @retval 0 isn't ADC reg trig source
+ * @retval 1 is ADC reg trig source
+ */
+#define IS_ADC_REG_TRIG_SOURCE( __REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == ADC_REG_TRIG_SOFTWARE) \
+ || (((__REG_TRIG_SOURCE__) & (ADC_LR_EXTSEL_Msk | ADC_LR_EXTEN_Msk)) != 0x00U) \
+ )
+
+/**
+ * @brief Judge is ADC reg continuous mode or not
+ * @param __REG_CONTINUOUS_MODE__ reg continuous mode to judge
+ * @retval 0 isn't ADC reg continuous mode
+ * @retval 1 is ADC reg continuous mode
+ */
+#define IS_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == ADC_REG_CONV_CONTINUOUS) \
+ )
+
+/**
+ * @brief Judge is ADC reg seq discont or not
+ * @param __REG_DISCONT_MODE__ reg seq discont to judge
+ * @retval 0 isn't ADC reg seq discont
+ * @retval 1 is ADC reg seq discont
+ */
+#define IS_ADC_REG_SEQ_DISCONT(__REG_DISCONT_MODE__) \
+ ( ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISCON_DISABLE) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_1RANK) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_2RANKS) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_3RANKS) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_4RANKS) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_5RANKS) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_6RANKS) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_7RANKS) \
+ || ((__REG_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_8RANKS) \
+ )
+
+/**
+ * @brief Judge is ADC reg differ sel or not
+ * @param __DIFSEL_MODE__ differ sel mode to judge
+ * @retval 0 isn't ADC reg differ sel
+ * @retval 1 is ADC reg differ sel
+ */
+#define IS_ADC_REG_DIFFERSEL(__DIFSEL_MODE__) \
+ ( ((__DIFSEL_MODE__) == ADC_DIFSEL_DIFFER) \
+ || ((__DIFSEL_MODE__) == ADC_DIFSEL_SINGLE) \
+ )
+
+/**
+ * @brief Judge is ADC reg samp time clock or not
+ * @param __REG_SAMPTIMCLK__ reg samp time clock to judge
+ * @retval 0 isn't ADC reg samp time clock
+ * @retval 1 is ADC reg samp time clock
+ */
+#define IS_ADC_REG_SAMPTIMCLK(__REG_SAMPTIMCLK__) \
+ ( ((__REG_SAMPTIMCLK__) == ADC_SAMPLINGTIME_6CYCLES) \
+ || (((__REG_SAMPTIMCLK__) & ADC_SMPR0_SMP0_Msk) != 0x00U) \
+ )
+
+/**
+ * @brief Judge is ADC LL cal coef sel or not
+ * @param __CALCOEFSEL__ cal coef sel to judge
+ * @retval 0 isn't ADC LL cal coef sel
+ * @retval 1 is ADC LL cal coef sel
+ */
+#define IS_LL_ADC_CALCOEFSEL(__CALCOEFSEL__) \
+ ( ((__CALCOEFSEL__) == ADC_CALIB_GROUP0) \
+ || ((__CALCOEFSEL__) == ADC_CALIB_GROUP1) \
+ || ((__CALCOEFSEL__) == ADC_CALIB_GROUP2) \
+ || ((__CALCOEFSEL__) == ADC_CALIB_GROUP3) \
+ )
+
+/**
+ * @brief Judge is ADC over data behavior or not
+ * @param __REG_OVR_DATA_BEHAVIOR__ over data behavior to judge
+ * @retval 0 isn't ADC over data behavior
+ * @retval 1 is ADC over data behavior
+ */
+#define IS_ADC_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
+ ( ((__REG_OVR_DATA_BEHAVIOR__) == ADC_OVR_DATA_PRESERVED) \
+ || ((__REG_OVR_DATA_BEHAVIOR__) == ADC_OVR_DATA_OVERWRITTEN) \
+ )
+
+/**
+ * @brief Judge is ADC reg dma transfer or not
+ * @param __REG_DMA_TRANSFER__ reg dma transfer to judge
+ * @retval 0 isn't ADC reg dma transfer
+ * @retval 1 is ADC reg dma transfer
+ */
+#define IS_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == ADC_REG_DMA_TRANSFER_SINGLE) \
+ || ((__REG_DMA_TRANSFER__) == ADC_REG_DMA_TRANSFER_CIRCLE) \
+ || ((__REG_DMA_TRANSFER__) == ADC_REG_DMA_TRANSFER_DISABLE) \
+ )
+
+/**
+ * @brief Judge is ADC reg awd filter or not
+ * @param __REG_AWD_FILTER__ reg awd filter to judge
+ * @retval 0 isn't ADC reg awd filter
+ * @retval 1 is ADC reg awd filter
+ */
+#define IS_ADC_REG_AWD_FILTER(__REG_AWD_FILTER__) \
+ ( (((__REG_AWD_FILTER__) & ADC_AWD0CR_AWD0FILT_Msk) != 0x00U) \
+ || ((__REG_AWD_FILTER__) == ADC_AWD_FILTERING_NONE) \
+ )
+
+/**
+ * @brief Judge is ADC reg awd sel or not
+ * @param __REG_AWD_SEL__ reg awd sel to judge
+ * @retval 0 isn't ADC reg awd sel
+ * @retval 1 is ADC reg awd sel
+ */
+#define IS_ADC_REG_AWD_SEL(__REG_AWD_SEL__) \
+ ( ((__REG_AWD_SEL__) == ADC_AWD2) \
+ || ((__REG_AWD_SEL__) == ADC_AWD0) \
+ || ((__REG_AWD_SEL__) == ADC_AWD1) \
+ )
+
+/**
+ * @brief Judge is ADC awd channel or not
+ * @param __AWD_CHANNEL__ awd channel to judge
+ * @retval 0 isn't ADC awd channel
+ * @retval 1 is ADC awd channel
+ */
+#define IS_ADC_AWD_CHANNEL(__AWD_CHANNEL__) \
+ ( (((__AWD_CHANNEL__) & ADC_AWD0CR_AWD0CH_Msk) != 0x00U) \
+ || (((__AWD_CHANNEL__) & (ADC_AWD0CR_AWD0CH_Msk)) == 0x00U) \
+ )
+
+/**
+ * @brief Judge is ADC reg seq length or not
+ * @param __REG_SEQ_LENGTH__ reg seq length to judge
+ * @retval 0 isn't ADC reg seq length
+ * @retval 1 is ADC reg seq length
+ */
+#define IS_ADC_REG_SEQ_LENGTH(__REG_SEQ_LENGTH__) \
+ ( ((__REG_SEQ_LENGTH__) == ADC_REG_SEQ_LENGTH_1) \
+ || (((__REG_SEQ_LENGTH__) & ADC_LR_LEN_Msk) != 0x00U) \
+ )
+
+/**
+ * @brief Judge is ADC reg seq pos or not
+ * @param __REG_SEQ_POS_ reg seq pos to judge
+ * @retval 0 isn't ADC reg seq pos
+ * @retval 1 is ADC reg seq pos
+ */
+#define IS_ADC_REG_SEQ_POS(__REG_SEQ_POS_) \
+ ( ((__REG_SEQ_POS_) == ADC_REG_RANK_1) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_2) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_3) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_4) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_5) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_6) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_7) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_8) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_9) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_10) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_11) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_12) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_13) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_14) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_15) \
+ || ((__REG_SEQ_POS_) == ADC_REG_RANK_16) \
+ )
+
+/**
+ * @brief Judge is ADC reg seq discont mode or not
+ * @param __REG_SEQ_DISCONT_MODE__ reg seq discont mode to judge
+ * @retval 0 isn't ADC reg seq discont mode
+ * @retval 1 is ADC reg seq discont mode
+ */
+#define IS_ADC_REG_SEQ_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISCON_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == ADC_REG_SEQ_DISNUM_8RANKS) \
+ )
+
+
+/**
+ * @brief Judge is ADC inj trig source or not
+ * @param __INJ_TRIG_SOURCE__ inj trig source to judge
+ * @retval 0 isn't ADC inj trig source
+ * @retval 1 is ADC inj trig source
+ */
+#define IS_ADC_INJ_TRIG_SOURCE( __INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == ADC_INJ_TRIG_SOFTWARE) \
+ || (((__INJ_TRIG_SOURCE__) & (ADC_JLR_JEXTSEL_Msk | ADC_JLR_JEXTEN_Msk)) != 0x00U) \
+ )
+
+/**
+ * @brief Judge is ADC inj trig ext edge or not
+ * @param __INJ_TRIG_EXT_EDGE__ inj trig ext edge to judge
+ * @retval 0 isn't ADC inj trig ext edge
+ * @retval 1 is ADC inj trig ext edge
+ */
+#define IS_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
+ ( ((__INJ_TRIG_EXT_EDGE__) == ADC_INJ_TRIG_EXT_RISING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == ADC_INJ_TRIG_EXT_FALLING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == ADC_INJ_TRIG_EXT_RISINGFALLING) \
+ )
+
+/**
+ * @brief Judge is ADC inj trig auto or not
+ * @param __INJ_TRIG_AUTO__ inj trig auto to judge
+ * @retval 0 isn't ADC inj trig auto
+ * @retval 1 is ADC inj trig auto
+ */
+#define IS_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == ADC_INJ_TRIG_FROM_GRP_REGULAR) \
+ )
+
+/**
+ * @brief Judge is ADC inj seq scan length or not
+ * @param __INJ_SEQ_LENGTH__ inj seq scan length to judge
+ * @retval 0 isn't ADC inj seq scan length
+ * @retval 1 is ADC inj seq scan length
+ */
+#define IS_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_LENGTH__) \
+ ( ((__INJ_SEQ_LENGTH__) == ADC_INJ_SEQ_LENGTH_1) \
+ || ((__INJ_SEQ_LENGTH__) == ADC_INJ_SEQ_LENGTH_2) \
+ || ((__INJ_SEQ_LENGTH__) == ADC_INJ_SEQ_LENGTH_3) \
+ || ((__INJ_SEQ_LENGTH__) == ADC_INJ_SEQ_LENGTH_4) \
+ )
+
+/**
+ * @brief Judge is ADC inj jseq pos or not
+ * @param __INJ_SEQ_LENGTH__ inj jseq pos to judge
+ * @retval 0 isn't ADC inj jseq pos
+ * @retval 1 is ADC inj jseq pos
+ */
+#define IS_ADC_INJ_JSEQ_POS(__INJ_SEQ_LENGTH__) \
+ ( ((__INJ_SEQ_LENGTH__) == ADC_INJ_RANK_1) \
+ || ((__INJ_SEQ_LENGTH__) == ADC_INJ_RANK_2) \
+ || ((__INJ_SEQ_LENGTH__) == ADC_INJ_RANK_3) \
+ || ((__INJ_SEQ_LENGTH__) == ADC_INJ_RANK_4) \
+ )
+
+/**
+ * @brief Judge is ADC inj seq scan discont mode or not
+ * @param __INJ_SEQ_DISCONT_MODE__ inj seq scan discont mode to judge
+ * @retval 0 isn't ADC inj seq scan discont mode
+ * @retval 1 is ADC inj seq scan discont mode
+ */
+#define IS_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == ADC_INJ_SEQ_DISCONT_ENABLE) \
+ )
+
+
+/**
+ * @brief Judge is ADC ECU group sel or not
+ * @param __ECU_GROUP_SEL__ ECU group sel to judge
+ * @retval 0 isn't ADC ECU group sel
+ * @retval 1 is ADC ECU group sel
+ */
+#define IS_ADC_ECU_GROUPSEL(__ECU_GROUP_SEL__) \
+ ( ((__ECU_GROUP_SEL__) == ADC_CALIB_GROUP0) \
+ || ((__ECU_GROUP_SEL__) == ADC_CALIB_GROUP1) \
+ || ((__ECU_GROUP_SEL__) == ADC_CALIB_GROUP2) \
+ || ((__ECU_GROUP_SEL__) == ADC_CALIB_GROUP3) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_ADC_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_can.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_can.h
new file mode 100644
index 0000000000..e739b4f9dc
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_can.h
@@ -0,0 +1,1030 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_can.h
+ * @author MCD Application Team
+ * @brief Header file for CAN LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_CAN_H_
+#define _TAE32F53XX_LL_CAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_LL_Exported_Types CAN LL Exported Types
+ * @brief CAN LL Exported Types
+ * @{
+ */
+
+/**
+ *@brief CAN RX buffer status enum type define
+ */
+typedef enum {
+ CAN_RX_BUF_STA_EMPTY = 0, /*!< CAN RX buffer empty */
+ CAN_RX_BUF_STA_FEW, /*!< CAN RX buffer few */
+ CAN_RX_BUF_STA_ALMOST_FULL, /*!< CAN RX buffer almost full */
+ CAN_RX_BUF_STA_FULL, /*!< CAN RX buffer full */
+} CAN_RxBufStaETypeDef;
+
+/**
+ * @brief CAN acceptance filter slot definition.
+ */
+typedef enum {
+ CAN_ACCEPT_FILT_SLOT_0 = 0, /*!< CAN acceptance filter slot 0 */
+ CAN_ACCEPT_FILT_SLOT_1, /*!< CAN acceptance filter slot 1 */
+ CAN_ACCEPT_FILT_SLOT_2, /*!< CAN acceptance filter slot 2 */
+ CAN_ACCEPT_FILT_SLOT_3, /*!< CAN acceptance filter slot 3 */
+ CAN_ACCEPT_FILT_SLOT_4, /*!< CAN acceptance filter slot 4 */
+ CAN_ACCEPT_FILT_SLOT_5, /*!< CAN acceptance filter slot 5 */
+ CAN_ACCEPT_FILT_SLOT_6, /*!< CAN acceptance filter slot 6 */
+ CAN_ACCEPT_FILT_SLOT_7, /*!< CAN acceptance filter slot 7 */
+ CAN_ACCEPT_FILT_SLOT_8, /*!< CAN acceptance filter slot 8 */
+ CAN_ACCEPT_FILT_SLOT_9, /*!< CAN acceptance filter slot 9 */
+ CAN_ACCEPT_FILT_SLOT_10, /*!< CAN acceptance filter slot 10 */
+ CAN_ACCEPT_FILT_SLOT_11, /*!< CAN acceptance filter slot 11 */
+ CAN_ACCEPT_FILT_SLOT_12, /*!< CAN acceptance filter slot 12 */
+ CAN_ACCEPT_FILT_SLOT_13, /*!< CAN acceptance filter slot 13 */
+ CAN_ACCEPT_FILT_SLOT_14, /*!< CAN acceptance filter slot 14 */
+ CAN_ACCEPT_FILT_SLOT_15, /*!< CAN acceptance filter slot 15 */
+} CAN_AcceptFilSlotETypeDef;
+
+/**
+ * @brief CAN RX buffer almost full warnning limit definition
+ */
+typedef enum {
+ CAN_RX_ALMOST_FULL_LIMIT_0 = 0, /*!< CAN RX buffer almost full warnning limit: 0 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_1, /*!< CAN RX buffer almost full warnning limit: 1 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_2, /*!< CAN RX buffer almost full warnning limit: 2 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_3, /*!< CAN RX buffer almost full warnning limit: 3 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_4, /*!< CAN RX buffer almost full warnning limit: 4 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_5, /*!< CAN RX buffer almost full warnning limit: 5 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_6, /*!< CAN RX buffer almost full warnning limit: 6 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_7, /*!< CAN RX buffer almost full warnning limit: 7 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_8, /*!< CAN RX buffer almost full warnning limit: 8 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_9, /*!< CAN RX buffer almost full warnning limit: 9 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_10, /*!< CAN RX buffer almost full warnning limit: 10 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_11, /*!< CAN RX buffer almost full warnning limit: 11 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_12, /*!< CAN RX buffer almost full warnning limit: 12 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_13, /*!< CAN RX buffer almost full warnning limit: 13 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_14, /*!< CAN RX buffer almost full warnning limit: 14 Byte */
+ CAN_RX_ALMOST_FULL_LIMIT_15, /*!< CAN RX buffer almost full warnning limit: 15 Byte */
+} CAN_RxAlmostFullLimitETypeDef;
+
+/**
+ * @brief CAN programmable error warning limit definition
+ */
+typedef enum {
+ CAN_ERR_WARN_LIMIT_8 = 0, /*!< CAN programmable error warning limit: 8 bytes */
+ CAN_ERR_WARN_LIMIT_16, /*!< CAN programmable error warning limit: 16 bytes */
+ CAN_ERR_WARN_LIMIT_24, /*!< CAN programmable error warning limit: 24 bytes */
+ CAN_ERR_WARN_LIMIT_32, /*!< CAN programmable error warning limit: 32 bytes */
+ CAN_ERR_WARN_LIMIT_40, /*!< CAN programmable error warning limit: 40 bytes */
+ CAN_ERR_WARN_LIMIT_48, /*!< CAN programmable error warning limit: 48 bytes */
+ CAN_ERR_WARN_LIMIT_56, /*!< CAN programmable error warning limit: 56 bytes */
+ CAN_ERR_WARN_LIMIT_64, /*!< CAN programmable error warning limit: 64 bytes */
+ CAN_ERR_WARN_LIMIT_72, /*!< CAN programmable error warning limit: 72 bytes */
+ CAN_ERR_WARN_LIMIT_80, /*!< CAN programmable error warning limit: 80 bytes */
+ CAN_ERR_WARN_LIMIT_88, /*!< CAN programmable error warning limit: 88 bytes */
+ CAN_ERR_WARN_LIMIT_96, /*!< CAN programmable error warning limit: 96 bytes */
+ CAN_ERR_WARN_LIMIT_104, /*!< CAN programmable error warning limit: 104 bytes */
+ CAN_ERR_WARN_LIMIT_112, /*!< CAN programmable error warning limit: 112 bytes */
+ CAN_ERR_WARN_LIMIT_120, /*!< CAN programmable error warning limit: 120 bytes */
+ CAN_ERR_WARN_LIMIT_128, /*!< CAN programmable error warning limit: 128 bytes */
+} CAN_ErrWarnLimitETypeDef;
+
+
+/**
+ * @brief CAN RX buffer format type definition
+ */
+typedef struct __CAN_RxBufFormatTypeDef {
+ /*! Standard/Extended iDentifier value
+ */
+ uint32_t id : 29,
+
+ /*! Reserved bit.
+ */
+ reserved1 : 2,
+
+ /*! Error State Indicator. This is a read-only status bit for RBUF and is not available
+ * in TBUF. The protocol machine automatically embeds the correct value of ESI into
+ * transmitted frames. ESI is only included in CAN FD frames and does not exist in CAN
+ * 2.0 frames.
+ */
+ err_state_indicator : 1;
+
+ /*! The Data Length Code (DLC) in RBUF and TBUF defines the length of the payload(the
+ * number of payload bytes in a frame).
+ */
+ uint32_t data_len_code : 4,
+
+ /*! Bit Rate Switch
+ * 0: nominal / slow bit rate for the complete frame.
+ * 1: switch to data / fast bit rate for the data payload and the CRC
+ * Only CAN FD frames can switch the bitrate. Therefore BRS is forced to 0 if EDL=0
+ */
+ bit_rate_switch : 1,
+
+ /*! Extended Data Length
+ * 0: CAN 2.0 frame (up to 8 bytes payload)
+ * 1: CAN FD frame (up to 64 bytes payload)
+ */
+ extended_data_len : 1,
+
+ /*! Remote Transmission Request
+ * 0: data frame
+ * 1: remote frame
+ * Only CAN 2.0 frames can be remote frames. There is no remote frame for CAN FD.
+ * Therefore RTR is forced to 0 if EDL=1 in the TBUF.
+ */
+ remote_tx_req : 1,
+
+ /*! IDentifier Extension
+ * 0: Standard Format: ID(10:0)
+ * 1: Extended Format: ID(28:0)
+ */
+ id_extension : 1,
+
+ /*! Reserved bit.
+ */
+ reserved2 : 24;
+} CAN_RxBufFormatTypeDef;
+
+/**
+ * @brief CAN TX buffer format type definition
+ */
+typedef struct __CAN_TxBufFormatTypeDef {
+ /*! Standard/Extended iDentifier value
+ */
+ uint32_t id : 29,
+
+ /*! Reserved bit.
+ */
+ reserved1 : 3;
+
+ /*! The Data Length Code (DLC) in RBUF and TBUF defines the length of the payload(the
+ * number of payload bytes in a frame).
+ */
+ uint32_t data_len_code : 4,
+
+ /*! Bit Rate Switch
+ * 0: nominal / slow bit rate for the complete frame.
+ * 1: switch to data / fast bit rate for the data payload and the CRC
+ * Only CAN FD frames can switch the bitrate. Therefore BRS is forced to 0 if EDL=0
+ */
+ bit_rate_switch : 1,
+
+ /*! Extended Data Length
+ * 0: CAN 2.0 frame (up to 8 bytes payload)
+ * 1: CAN FD frame (up to 64 bytes payload)
+ */
+ extended_data_len : 1,
+
+ /*! Remote Transmission Request
+ * 0: data frame
+ * 1: remote frame
+ * Only CAN 2.0 frames can be remote frames. There is no remote frame for CAN FD.
+ * Therefore RTR is forced to 0 if EDL=1 in the TBUF.
+ */
+ remote_tx_req : 1,
+
+ /*! IDentifier Extension
+ * 0: Standard Format: ID(10:0)
+ * 1: Extended Format: ID(28:0)
+ */
+ id_extension : 1,
+
+ /*! Reserved bit.
+ */
+ reserved2 : 24;
+} CAN_TxBufFormatTypeDef;
+
+/**
+ * @brief CAN acceptance filter config type definition
+ */
+typedef struct __CAN_AcceptFilCfgTypeDef {
+ CAN_AcceptFilSlotETypeDef slot; /*!< acceptance filter slot number */
+ uint32_t code_val; /*!< acceptance filter code value */
+ uint32_t mask_val; /*!< acceptance filter mask value */
+} CAN_AcceptFilCfgTypeDef;
+
+/**
+ * @brief CAN user config type definition
+ */
+typedef struct __CAN_UserCfgTypeDef {
+ uint32_t baudrate; /*!< baudrate */
+ uint8_t bit_timing_seg1; /*!< bit timing segment1 */
+ uint8_t bit_timing_seg2; /*!< bit timing degment2 */
+ uint8_t bit_timing_sjw; /*!< bit timing synchronization jump width */
+ CAN_RxAlmostFullLimitETypeDef rx_almost_full_limit; /*!< rx buffer almost full warning limit */
+ CAN_ErrWarnLimitETypeDef err_limit; /*!< error warning limit */
+ CAN_AcceptFilCfgTypeDef *accept_fil_cfg_ptr; /*!< acceptance filter config pointer */
+ uint8_t accept_fil_cfg_num; /*!< acceptance filter config number */
+} CAN_UserCfgTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CAN_LL_Exported_Macros CAN LL Exported Macros
+ * @brief CAN LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief CAN reset set
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_Reset_Set(__CAN__) SET_BIT((__CAN__)->CFG_STAT, CAN_RESET_Msk)
+
+/**
+ * @brief CAN reset clear
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_Reset_Clr(__CAN__) CLEAR_BIT((__CAN__)->CFG_STAT, CAN_RESET_Msk)
+
+/**
+ * @brief CAN reset status get
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 CAN reset has set
+ * @retval 1 CAN reset has clear
+ */
+#define __LL_CAN_ResetSta_Get(__CAN__) (READ_BIT((__CAN__)->CFG_STAT, CAN_RESET_Msk) >> CAN_RESET_Pos)
+
+/**
+ * @brief CAN loop back mode external enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_LoopBackModeExt_En(__CAN__) SET_BIT((__CAN__)->CFG_STAT, CAN_LOOP_BACK_EXTERNAL_Msk)
+
+/**
+ * @brief CAN loop back mode external disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_LoopBackModeExt_Dis(__CAN__) CLEAR_BIT((__CAN__)->CFG_STAT, CAN_LOOP_BACK_EXTERNAL_Msk)
+
+/**
+ * @brief CAN loop back mode internal enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_LoopBackModeInternal_En(__CAN__) SET_BIT((__CAN__)->CFG_STAT, CAN_LOOP_BACK_INTERNAL_Msk)
+
+/**
+ * @brief CAN loop back mode internal disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_LoopBackModeInternal_Dis(__CAN__) CLEAR_BIT((__CAN__)->CFG_STAT, CAN_LOOP_BACK_INTERNAL_Msk)
+
+/**
+ * @brief CAN TX primary single shot enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxPriSingleShot_En(__CAN__) SET_BIT((__CAN__)->CFG_STAT, CAN_TX_PRI_SINGLE_SHOT_Msk)
+
+/**
+ * @brief CAN TX primary single shot disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxPriSingleShot_Dis(__CAN__) CLEAR_BIT((__CAN__)->CFG_STAT, CAN_TX_PRI_SINGLE_SHOT_Msk)
+
+/**
+ * @brief CAN TX secondary single shot enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSecSingleShot_En(__CAN__) SET_BIT((__CAN__)->CFG_STAT, CAN_TX_SEC_SINGLE_SHOT_Msk)
+
+/**
+ * @brief CAN TX secondary single shot disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSecSingleShot_Dis(__CAN__) CLEAR_BIT((__CAN__)->CFG_STAT, CAN_TX_SEC_SINGLE_SHOT_Msk)
+
+/**
+ * @brief Judge is RX active or not
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 Isn't RX active
+ * @retval 1 Is RX active
+ */
+#define __LL_CAN_IsRxActive(__CAN__) (READ_BIT((__CAN__)->CFG_STAT, CAN_RX_ACT_Msk) >> CAN_RX_ACT_Pos)
+
+/**
+ * @brief Judge is TX active or not
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 Isn't TX active
+ * @retval 1 Is TX active
+ */
+#define __LL_CAN_IsTxActive(__CAN__) (READ_BIT((__CAN__)->CFG_STAT, CAN_TX_ACT_Msk) >> CAN_TX_ACT_Pos)
+
+/**
+ * @brief Judge is bus off or not
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 Is bus on
+ * @retval 1 Is bus off
+ */
+#define __LL_CAN_IsBusOff(__CAN__) (READ_BIT((__CAN__)->CFG_STAT, CAN_BUS_OFF_Msk) >> CAN_BUS_OFF_Pos)
+
+
+/**
+ * @brief TX buffer select PTB
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxBufSel_PTB(__CAN__) CLEAR_BIT((__CAN__)->TCMD, CAN_TX_BUF_SEL_Msk)
+
+/**
+ * @brief TX buffer select STB
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxBufSel_STB(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_TX_BUF_SEL_Msk)
+
+/**
+ * @brief Listen only mode enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_ListenOnlyMode_En(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_LISTEN_ONLY_Msk)
+
+/**
+ * @brief Listen only mode disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_ListenOnlyMode_Dis(__CAN__) CLEAR_BIT((__CAN__)->TCMD, CAN_LISTEN_ONLY_Msk)
+
+/**
+ * @brief TX standby mode enalbe
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxStandbyMode_En(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_TX_STANDBY_Msk)
+
+/**
+ * @brief TX standby mode disalbe
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxStandbyMode_Dis(__CAN__) CLEAR_BIT((__CAN__)->TCMD, CAN_TX_STANDBY_Msk)
+
+/**
+ * @brief TX primary enable set
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxPriEn_Set(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_TX_PRI_EN_Msk)
+
+/**
+ * @brief TX primary enable get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return TX primary enable status
+ */
+#define __LL_CAN_TxPriEn_Get(__CAN__) (READ_BIT((__CAN__)->TCMD, CAN_TX_PRI_EN_Msk) >> CAN_TX_PRI_EN_Pos)
+
+/**
+ * @brief TX primary abort set
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxPriAbort_Set(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_TX_PRI_ABORT_Msk)
+
+/**
+ * @brief TX secondary one set
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSecOne_Set(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_TX_SEC_ONE_Msk)
+
+/**
+ * @brief TX secondary one get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return TX secondary one status
+ */
+#define __LL_CAN_TxSecOne_Get(__CAN__) (READ_BIT((__CAN__)->TCMD, CAN_TX_SEC_ONE_Msk) >> CAN_TX_SEC_ONE_Pos)
+
+/**
+ * @brief TX secondary all set
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSecAll_Set(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_TX_SEC_ALL_Msk)
+
+/**
+ * @brief TX secondary all get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return TX secondary send all status
+ */
+#define __LL_CAN_TxSecAll_Get(__CAN__) (READ_BIT((__CAN__)->TCMD, CAN_TX_SEC_ALL_Msk) >> CAN_TX_SEC_ALL_Pos)
+
+/**
+ * @brief TX secondary abort set
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSecAbort_Set(__CAN__) SET_BIT((__CAN__)->TCMD, CAN_TX_SEC_ABORT_Msk)
+
+
+/**
+ * @brief FD ISO enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_FD_ISO_En(__CAN__) SET_BIT((__CAN__)->TCTRL, CAN_FD_ISO_Msk)
+
+/**
+ * @brief FD ISO disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_FD_ISO_Dis(__CAN__) CLEAR_BIT((__CAN__)->TCTRL, CAN_FD_ISO_Msk)
+
+/**
+ * @brief TX secondary buffer next set
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSecNext_Set(__CAN__) SET_BIT((__CAN__)->TCTRL, CAN_TX_SEC_NEXT_Msk)
+
+/**
+ * @brief TX secondary status get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return Number of filled message secondary buffers
+ */
+#define __LL_CAN_TxSecSta_Get(__CAN__) (READ_BIT((__CAN__)->TCTRL, CAN_TX_SEC_STA_Msk) >> CAN_TX_SEC_STA_Pos)
+
+
+/**
+ * @brief Judge is RX buffer overflow or not
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 Isn't RX buffer overflow
+ * @retval 1 Is RX buffer overflow
+ */
+#define __LL_CAN_IsRxBufOver(__CAN__) (READ_BIT((__CAN__)->RCTRL, CAN_RX_BUF_OVER_Msk) >> CAN_RX_BUF_OVER_Pos)
+
+/**
+ * @brief RX buffer release
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_RxBufRelease(__CAN__) SET_BIT((__CAN__)->RCTRL, CAN_RX_BUF_REL_Msk)
+
+/**
+ * @brief RX buffer status get
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 RX buffer empty
+ * @retval 1 empty < RX buffer < almost full
+ * @retval 2 RX buffer >= almost full
+ * @retval 3 RX buffer full
+ */
+#define __LL_CAN_RxBufSta_Get(__CAN__) (READ_BIT((__CAN__)->RCTRL, CAN_RX_BUF_STA_Msk) >> CAN_RX_BUF_STA_Pos)
+
+
+/**
+ * @brief RX interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_Rx_INT_EN(__CAN__) SET_BIT((__CAN__)->RTIE, CAN_RX_INT_EN_Msk)
+
+/**
+ * @brief RX interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_Rx_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->RTIE, CAN_RX_INT_EN_Msk)
+
+/**
+ * @brief RX buffer overrun interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_RxBufOver_INT_EN(__CAN__) SET_BIT((__CAN__)->RTIE, CAN_RX_BUF_OVER_INT_EN_Msk)
+
+/**
+ * @brief RX buffer overrun interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_RxBufOver_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->RTIE, CAN_RX_BUF_OVER_INT_EN_Msk)
+
+/**
+ * @brief RX buffer full interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_RxBufFull_INT_EN(__CAN__) SET_BIT((__CAN__)->RTIE, CAN_RX_BUF_FULL_INT_EN_Msk)
+
+/**
+ * @brief RX buffer full interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_RxBufFull_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->RTIE, CAN_RX_BUF_FULL_INT_EN_Msk)
+
+/**
+ * @brief RX buffer almost full interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_RxBufAlmostFull_INT_EN(__CAN__) SET_BIT((__CAN__)->RTIE, CAN_RX_BUF_ALMOST_FULL_INT_EN_Msk)
+
+/**
+ * @brief RX buffer almost full interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_RxBufAlmostFull_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->RTIE, CAN_RX_BUF_ALMOST_FULL_INT_EN_Msk)
+
+/**
+ * @brief TX primary interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxPri_INT_En(__CAN__) SET_BIT((__CAN__)->RTIE, CAN_TX_PRI_INT_EN_Msk)
+
+/**
+ * @brief TX primary interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxPri_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->RTIE, CAN_TX_PRI_INT_EN_Msk)
+
+/**
+ * @brief TX secondary interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSec_INT_En(__CAN__) SET_BIT((__CAN__)->RTIE, CAN_TX_SEC_INT_EN_Msk)
+
+/**
+ * @brief TX secondary interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxSec_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->RTIE, CAN_TX_SEC_INT_EN_Msk)
+
+/**
+ * @brief Error interrupt enalbe
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_Err_INT_En(__CAN__) SET_BIT((__CAN__)->RTIE, CAN_ERR_INT_EN_Msk)
+
+/**
+ * @brief Error interrupt disalbe
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_Err_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->RTIE, CAN_ERR_INT_EN_Msk)
+
+/**
+ * @brief Judge is TX secondary buffer full or not
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 Isn't TX secondary buffer full
+ * @retval 1 Is TX secondary buffer full
+ */
+#define __LL_CAN_IsTxSecBufFull(__CAN__) (READ_BIT((__CAN__)->RTIE, CAN_TX_SEC_BUF_FULL_Msk) >> CAN_TX_SEC_BUF_FULL_Pos)
+
+
+/**
+ * @brief Interrupt status get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return Interrupt status
+ */
+#define __LL_CAN_IntSta_Get(__CAN__) READ_REG((__CAN__)->RTIF)
+
+
+/**
+ * @brief Judge is error warning limit reached or not
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 Isn't error warning limit reached
+ * @retval 1 Is error warning limit reached
+ */
+#define __LL_CAN_IsErrWarnLimitReached(__CAN__) \
+ (READ_BIT((__CAN__)ERRINT, CAN_ERR_WARN_LIMIT_REACHED_Msk) >> CAN_ERR_WARN_LIMIT_REACHED_Pos)
+
+/**
+ * @brief Judge is error passive mode active or not
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 Error passive mode isn't active
+ * @retval 1 Error passive mode is active
+ */
+#define __LL_CAN_IsErrPassiveModeActive(__CAN__) (READ_BIT((__CAN__)->ERRINT, CAN_ERR_PASS_ACT_Msk) >> CAN_ERR_PASS_ACT_Pos)
+
+/**
+ * @brief Error passive interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_ErrPassive_INT_En(__CAN__) SET_BIT((__CAN__)->ERRINT, CAN_ERR_PASS_INT_EN_Msk)
+
+/**
+ * @brief Error passive interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_ErrPassive_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->ERRINT, CAN_ERR_PASS_INT_EN_Msk)
+
+/**
+ * @brief Arbitration lost interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_ArbLost_INT_En(__CAN__) SET_BIT((__CAN__)->ERRINT, CAN_ARB_LOST_INT_EN_Msk)
+
+/**
+ * @brief Arbitration lost interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_ArbLost_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->ERRINT, CAN_ARB_LOST_INT_EN_Msk)
+
+/**
+ * @brief Bus error interrupt enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_BusErr_INT_En(__CAN__) SET_BIT((__CAN__)->ERRINT, CAN_BUS_ERR_INT_EN_Msk)
+
+/**
+ * @brief Bus error interrupt disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_BusErr_INT_Dis(__CAN__) CLEAR_BIT((__CAN__)->ERRINT, CAN_BUS_ERR_INT_EN_Msk)
+
+/**
+ * @brief Error interrupt status get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return Error interrupt status
+ */
+#define __LL_CAN_ErrIntSta_Get(__CAN__) \
+ (READ_BIT((__CAN__)->ERRINT, (CAN_ERR_PASS_INT_STA_Msk | CAN_ARB_LOST_INT_STA_Msk | CAN_BUS_ERR_INT_STA_Msk)))
+
+
+/**
+ * @brief RX buffer almost full warning limit set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_RxBufAlmostFullLimit_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->LIMIT, CAN_RX_BUF_ALMOST_FULL_LIMIT_Msk, ((val & 0xfUL) << CAN_RX_BUF_ALMOST_FULL_LIMIT_Pos))
+
+/**
+ * @brief Error warning limit set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_ErrWarnLimit_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->LIMIT, CAN_ERR_WARN_LIMIT_Msk, ((val & 0xfUL) << CAN_ERR_WARN_LIMIT_Pos))
+
+
+/**
+ * @brief Fast speed synchronization jump width set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_FS_SyncJumpWidth_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->BITTIME0, CAN_FS_SYNC_JUMP_WIDTH_Msk, ((val & 0x3UL) << CAN_FS_SYNC_JUMP_WIDTH_Pos))
+
+/**
+ * @brief Slow speed bit timing segment1 set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_SS_BitTimingSeg1_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->BITTIME0, CAN_SS_SEG1_Msk, ((val & 0x3fUL) << CAN_SS_SEG1_Pos))
+
+
+/**
+ * @brief Fast speed bit timing segment2 set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_FS_BitTimingSeg2_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->BITTIME1, CAN_FS_SEG2_Msk, ((val & 0x7UL) << CAN_FS_SEG2_Pos))
+
+/**
+ * @brief Slow speed bit timing segment2 set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_SS_BitTimingSeg2_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->BITTIME1, CAN_SS_SEG2_Msk, ((val & 0x1fUL) << CAN_SS_SEG2_Pos))
+
+
+/**
+ * @brief Fast speed bit timing segment1 set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_FS_BitTimingSeg1_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->BITTIME2, CAN_FS_SEG1_Msk, ((val & 0xfUL) << CAN_FS_SEG1_Pos))
+
+/**
+ * @brief Slow speed synchronization jump width set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_SS_SyncJumpWidth_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->BITTIME2, CAN_SS_SYNC_JUMP_WIDTH_Msk, ((val & 0xfUL) << CAN_SS_SYNC_JUMP_WIDTH_Pos))
+
+
+/**
+ * @brief Slow speed prescaler set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_SS_Prescaler_Set(__CAN__,val) WRITE_REG((__CAN__)->S_PRESC, ((val) & CAN_SS_PRESCALER_Msk))
+
+
+/**
+ * @brief Fast speed prescaler set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_FS_Prescaler_Set(__CAN__,val) WRITE_REG((__CAN__)->F_PRESC, ((val) & CAN_FS_PRESCALER_Msk))
+
+
+/**
+ * @brief TX delay compensation enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxDelayComp_En(__CAN__) SET_BIT((__CAN__)->TDC, CAN_TX_DELAY_COMP_EN_Msk)
+
+/**
+ * @brief TX delay compensation disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_TxDelayComp_Dis(__CAN__) CLEAR_BIT((__CAN__)->TDC, CAN_TX_DELAY_COMP_EN_Msk)
+
+/**
+ * @brief Secondary sample point offset set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_SecSamplePointOffset_Set(__CAN__,val) \
+ MODIFY_REG((__CAN__)->TDC, CAN_SEC_SAMPLE_POINT_OFFSET_Msk, ((val & 0x1f) << CAN_SEC_SAMPLE_POINT_OFFSET_Pos))
+
+
+/**
+ * @brief Error code get
+ * @param __CAN__ Specifies CAN peripheral
+ * @retval 0 no error
+ * @retval 1 bit error
+ * @retval 2 form error
+ * @retval 3 stuff error
+ * @retval 4 acknowledgement error
+ * @retval 5 CRC error
+ * @retval 6 other error
+ * @retval 7 not used
+ */
+#define __LL_CAN_ErrCode_Get(__CAN__) (READ_BIT((__CAN__)->EALCAP, CAN_ERR_CODE_Msk) >> CAN_ERR_CODE_Pos)
+
+/**
+ * @brief Arbitration lost capture get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return bit position in the frame where the arbitration has been lost
+ */
+#define __LL_CAN_ArbLostCapture_Get(__CAN__) (READ_BIT((__CAN__)->EALCAP, CAN_ARB_LOST_CAPTURE_Msk) >> CAN_ARB_LOST_CAPTURE_Pos)
+
+
+/**
+ * @brief RX error count get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return RX error count
+ */
+#define __LL_CAN_RxErrCnt_Get(__CAN__) READ_REG((__CAN__)->RECNT)
+
+
+/**
+ * @brief TX error count get
+ * @param __CAN__ Specifies CAN peripheral
+ * @return TX error count
+ */
+#define __LL_CAN_TxErrCnt_Get(__CAN__) READ_REG((__CAN__)->TECNT)
+
+
+/**
+ * @brief Acceptance filter content select mask
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_AcceptFilContentSel_Mask(__CAN__) SET_BIT((__CAN__)->ACFCTRL, CAN_ACPT_FIL_CONTENT_SEL_Msk)
+
+/**
+ * @brief Acceptance filter content select code
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_AcceptFilContentSel_Code(__CAN__) CLEAR_BIT((__CAN__)->ACFCTRL, CAN_ACPT_FIL_CONTENT_SEL_Msk)
+
+/**
+ * @brief Acceptance filter address set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_AcceptFilAddr_Set(__CAN__, val) \
+ MODIFY_REG((__CAN__)->ACFCTRL, CAN_ACPT_FIL_ADDR_Msk, ((val & 0xfUL) << CAN_ACPT_FIL_ADDR_Pos))
+
+
+/**
+ * @brief Acceptance filter enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @param fil_num Acceptance filter slot number
+ * @note fil_num value range [0, 15]
+ * @return None
+ */
+#define __LL_CAN_AcceptFil_En(__CAN__, fil_num) \
+ do { \
+ if(fil_num < 8) { \
+ MODIFY_REG((__CAN__)->ACF_EN_0, (0x1UL<ACF_EN_1, (0x1UL<<(fil_num-8)), (0x1UL<<(fil_num-8))); \
+ } \
+ } while(0)
+
+
+/**
+ * @brief Acceptance mask IDE bit check enable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_AcceptFilMaskIDE_En(__CAN__) SET_BIT((__CAN__)->ACF, CAN_ACPT_MASK_IDE_CHK_EN_Msk)
+
+/**
+ * @brief Acceptance mask IDE bit check disable
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_AcceptFilMaskIDE_Dis(__CAN__) CLEAR_BIT((__CAN__)->ACF, CAN_ACPT_MASK_IDE_CHK_EN_Msk)
+
+/**
+ * @brief Acceptance filter accepts only extended frames
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_AcceptFilMaskIDESel_Ext(__CAN__) SET_BIT((__CAN__)->ACF, CAN_ACPT_MASK_IDE_BIT_VAL_Msk)
+
+/**
+ * @brief Acceptance filter accepts only standard frames
+ * @param __CAN__ Specifies CAN peripheral
+ * @return None
+ */
+#define __LL_CAN_AcceptFilMaskIDESel_Std(__CAN__) CLEAR_BIT((__CAN__)->ACF, CAN_ACPT_MASK_IDE_BIT_VAL_Msk)
+
+/**
+ * @brief Acceptance filter code or mask set
+ * @param __CAN__ Specifies CAN peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_CAN_AcceptFilCodeOrMaskVal_Set(__CAN__, val) \
+ MODIFY_REG((__CAN__)->ACF, CAN_ACPT_CODE_OR_MASK_Msk, ((val & 0x1fffffffUL) << CAN_ACPT_CODE_OR_MASK_Pos))
+
+
+
+/**
+ * @brief CAN frame ID format to 11 bits
+ */
+#define __LL_CAN_FrameIDFormat_11Bits(n) ((n) & 0x7FFUL)
+
+/**
+ * @brief CAN frame ID format to 29 bits
+ */
+#define __LL_CAN_FrameIDFormat_29Bits(n) ((n) & 0x1FFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CAN_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_CAN_Init(CAN_TypeDef *Instance, CAN_UserCfgTypeDef *user_cfg);
+LL_StatusETypeDef LL_CAN_DeInit(CAN_TypeDef *Instance);
+void LL_CAN_MspInit(CAN_TypeDef *Instance);
+void LL_CAN_MspDeInit(CAN_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_LL_Exported_Functions_Group2
+ * @{
+ */
+uint32_t LL_CAN_SendStandard_PTB(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf);
+uint32_t LL_CAN_SendStandard_STB(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf);
+uint32_t LL_CAN_SendStandard_STB_Multi(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt,
+ uint32_t *buf, uint32_t send_cnt);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_CAN_IRQHandler(CAN_TypeDef *Instance);
+
+void LL_CAN_RxCallback(CAN_TypeDef *Instance);
+void LL_CAN_RxOverCallback(CAN_TypeDef *Instance);
+void LL_CAN_RxFullCallback(CAN_TypeDef *Instance);
+void LL_CAN_RxAlmostFullCallback(CAN_TypeDef *Instance);
+void LL_CAN_TxPriCallback(CAN_TypeDef *Instance);
+void LL_CAN_TxSecCallback(CAN_TypeDef *Instance);
+void LL_CAN_ErrCallback(CAN_TypeDef *Instance);
+void LL_CAN_AbortCallback(CAN_TypeDef *Instance);
+
+void LL_CAN_ErrPassiveCallback(CAN_TypeDef *Instance);
+void LL_CAN_ArbLostCallback(CAN_TypeDef *Instance);
+void LL_CAN_BusErrCallback(CAN_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_CAN_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_cmp.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_cmp.h
new file mode 100644
index 0000000000..d5ccc24284
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_cmp.h
@@ -0,0 +1,570 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_cmp.h
+ * @author MCD Application Team
+ * @brief Header file for CMP Module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_CMP_H_
+#define _TAE32F53XX_LL_CMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup CMP_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CMP_LL_Exported_Constants CMP LL Exported Constants
+ * @brief CMP LL Exported Constants
+ * @{
+ */
+
+/** @defgroup CMP_Channel_selection CMP Channel selection
+ * @{
+ */
+#define CMP_CHANNEL_0 (0x00000001U)
+#define CMP_CHANNEL_1 (0x00000002U)
+#define CMP_CHANNEL_2 (0x00000004U)
+#define CMP_CHANNEL_3 (0x00000008U)
+#define CMP_CHANNEL_ALL (CMP_CHANNEL_0 | CMP_CHANNEL_1 | CMP_CHANNEL_2 | CMP_CHANNEL_3 )
+/**
+ * @}
+ */
+
+/** @defgroup CMP_Interrupt_definition CMP Interrupt definition
+ * @{
+ */
+#define CMP_IT_FALIE CMP_CR_FALIE /*!< CMP_CHx failing edge interrupt */
+#define CMP_IT_RISIE CMP_CR_RISIE /*!< CMP_CHx rising edge interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup CMP_Flag_definition CMP Flag Definition
+ * @{
+ */
+#define CMP_FLAG_FAL3IF CMP_SR_FALIF_3
+#define CMP_FLAG_FAL2IF CMP_SR_FALIF_2
+#define CMP_FLAG_FAL1IF CMP_SR_FALIF_1
+#define CMP_FLAG_FAL0IF CMP_SR_FALIF_0
+#define CMP_FLAG_RIS3IF CMP_SR_RISIF_3
+#define CMP_FLAG_RIS2IF CMP_SR_RISIF_2
+#define CMP_FLAG_RIS1IF CMP_SR_RISIF_1
+#define CMP_FLAG_RIS0IF CMP_SR_RISIF_0
+#define CMP_FLAG_ALLIF (CMP_SR_FALIF_3 | CMP_SR_FALIF_2 | \
+ CMP_SR_FALIF_1 | CMP_SR_FALIF_0 | \
+ CMP_SR_RISIF_3 | CMP_SR_RISIF_2 | \
+ CMP_SR_RISIF_1 | CMP_SR_RISIF_0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CMP_LL_Exported_Macros CMP LL Exported Macros
+ * @brief CMP LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable CMP Channel
+ * @param __INSTANCE__ CMP peripheral
+ * @param __CHN_NB__ Specifies CMP Channel
+ * This parameter can be a value of 0 to (CMP_CHN_NB - 1)
+ * @return None
+ */
+#define __LL_CMP_ENABLE(__INSTANCE__, __CHN_NB__) SET_BIT((__INSTANCE__)->CR[__CHN_NB__], CMP_CR_PEN)
+
+/**
+ * @brief Disable CMP Channel
+ * @param __INSTANCE__ CMP peripheral
+ * @param __CHN_NB__ Specifies CMP Channel
+ * This parameter can be a value of 0 to (CMP_CHN_NB - 1)
+ * @return None
+ */
+#define __LL_CMP_DISABLE(__INSTANCE__, __CHN_NB__) CLEAR_BIT((__INSTANCE__)->CR[__CHN_NB__], CMP_CR_PEN)
+
+/**
+ * @brief Enable the specified CMP Channel Interrupts
+ * @param __INSTANCE__ CMP peripheral
+ * @param __CHN_NB__ Specifies CMP Channel
+ * This parameter can be a value of 0 to (CMP_CHN_NB - 1)
+ * @param __INTERRUPT__ specifies the CMP Channel interrupt source to enable.
+ * This parameter can be any combination of @ref CMP_Interrupt_definition:
+ * @arg CMP_IT_FALIE : CMP_CHx failing edge interrupt
+ * @arg CMP_IT_RISIE : CMP_CHx rising edge interrupt
+ * @return None
+ */
+#define __LL_CMP_IT_ENABLE(__INSTANCE__, __CHN_NB__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CR[__CHN_NB__], (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CMP Channel Interrupts
+ * @param __INSTANCE__ CMP peripheral
+ * @param __CHN_NB__ Specifies CMP Channel
+ * This parameter can be a value of 0 to (CMP_CHN_NB - 1)
+ * @param __INTERRUPT__ specifies the CMP Channel interrupt source to disable.
+ * This parameter can be any combination of @ref CMP_Interrupt_definition:
+ * @arg CMP_IT_FALIE : CMP_CHx failing edge interrupt
+ * @arg CMP_IT_RISIE : CMP_CHx rising edge interrupt
+ * @return None
+ */
+#define __LL_CMP_IT_DISABLE(__INSTANCE__, __CHN_NB__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CR[__CHN_NB__], (__INTERRUPT__))
+
+
+/**
+ * @brief Check whether the specified CMP Channel interrupt source is set or not.
+ * @param __INSTANCE__ CMP peripheral
+ * @param __CHN_NB__ Specifies CMP Channel
+ * This parameter can be a value of 0 to (CMP_CHN_NB - 1)
+ * @param __INTERRUPT__ specifies the CMP Channel interrupt source to check.
+ * This parameter can be ONE of @ref CMP_Interrupt_definition:
+ * @arg CMP_IT_FALIE : CMP_CHx failing edge interrupt
+ * @arg CMP_IT_RISIE : CMP_CHx rising edge interrupt
+ * @return None
+ */
+#define __LL_CMP_IT_CHECK_SOURCE(__INSTANCE__, __CHN_NB__, __INTERRUPT__) \
+ ((READ_BIT((__INSTANCE__)->CR[__CHN_NB__], (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified pending flag is SET or not.
+ * @param __INSTANCE__ CMP peripheral.
+ * @param __FLAG__ specifies the CMP pending flag to check.
+ * This parameter can be ONE of the following values where x can be a value of
+ * 0, 1 ... (CMP_CHN_NB - 1):
+ * @arg CMP_FLAG_FALxIF : CMP_CHx failing edge interrupt pending flag
+ * @arg CMP_FLAG_RISxIF : CMP_CHx rising interrupt pending flag
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_CMP_PENDING_FLAG_GET(__INSTANCE__, __FLAG__) ((READ_BIT((__INSTANCE__)->SR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the specified pending flags
+ * @param __INSTANCE__ CMP peripheral.
+ * @param __FLAG__ specifies the CMP pending flag to clear.
+ * This parameter can be any combination of the following values where x can be a value of
+ * 0, 1 ... (CMP_CHN_NB - 1):
+ * @arg CMP_FLAG_FALxIF : CMP_CHx failing edge interrupt pending flag
+ * @arg CMP_FLAG_RISxIF : CMP_CHx rising interrupt pending flag
+ * @arg CMP_FLAG_ALLIF : CMP All interrupt pending flags
+ * @return None
+ */
+#define __LL_CMP_PENDING_FLAG_CLEAR(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->SR, (__FLAG__))
+
+
+/**
+ * @brief Set the specified CMP Channel output debounce value
+ * @param __INSTANCE__ CMP peripheral.
+ * @param __CHN_NB__ Specifies CMP Channel
+ * This parameter can be a value of 0 to (CMP_CHN_NB - 1)
+ * @param __VAL__ Specifies debounce value
+ * This value can be a range from 0 - 0xFFF (in System Clocks)
+ * @return None
+ */
+#define __LL_CMP_DEBOUNCE_VALUE_SET(__INSTANCE__, __CHN_NB__, __VAL__) WRITE_REG((__INSTANCE__)->DEBR[__CHN_NB__], (__VAL__))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CMP_LL_Exported_Types CMP LL Exported Types
+ * @brief CMP LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief CMP input minus (INM)
+ */
+typedef enum {
+ CMP_INPUT_MINUS_GND = 0x0U,
+ /*!< Comparator input minus connected to GND */
+ CMP_INPUT_MINUS_IO1 = CMP_CR_INM_0,
+ /*!< Comparator input minus connected to IO1, Note: For CMPx instance availability, please refer to SPEC Document */
+ CMP_INPUT_MINUS_IO2 = CMP_CR_INM_1,
+ /*!< Comparator input minus connected to IO2, Note: For CMPx instance availability, please refer to SPEC Document */
+ CMP_INPUT_MINUS_DAC = CMP_CR_INM_1 | CMP_CR_INM_0,
+ /*!< Comparator input minus connected to DAC Channel x for CMP Channel x.
+ Note: For CMPx & DACx instances availability, please refer to SPEC Document */
+} CMP_InputMinusETypeDef;
+
+/**
+ * @brief CMP Hysteresis
+ */
+typedef enum {
+ CMP_HYSTERESIS_NONE = 0x0U, /*!< No hysteresis */
+ CMP_HYSTERESIS_10MV = CMP_CR_HYST_0, /*!< Hysteresis level 10mV */
+ CMP_HYSTERESIS_20MV = CMP_CR_HYST_1, /*!< Hysteresis level 20mV */
+ CMP_HYSTERESIS_30MV = CMP_CR_HYST_1 | CMP_CR_HYST_0, /*!< Hysteresis level 30mV */
+} CMP_HysteresisETypeDef;
+
+/**
+ * @brief CMP Blanking Source
+ * @note For CMPx & TMRx instances availability, please refer to SPEC Document
+ */
+typedef enum {
+ CMP_BLANKINGSRC_NONE = 0x00000000U,
+
+ CMP_BLANKINGSRC_TMR0_PWM_CMP0 = CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR0_PWM (specific to CMP Channel0). */
+ CMP_BLANKINGSRC_TMR1_PWM_CMP1 = CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR1_PWM (specific to CMP Channel1). */
+ CMP_BLANKINGSRC_TMR0_PWM_CMP2 = CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR0_PWM (specific to CMP Channel2). */
+ CMP_BLANKINGSRC_TMR1_PWM_CMP3 = CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR1_PWM (specific to CMP Channel3). */
+
+ CMP_BLANKINGSRC_TMR1_PWM_CMP0 = CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR1_PWM (specific to CMP Channel0). */
+ CMP_BLANKINGSRC_TMR2_PWM_CMP1 = CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR2_PWM (specific to CMP Channel1). */
+ CMP_BLANKINGSRC_TMR1_PWM_CMP2 = CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR1_PWM (specific to CMP Channel2). */
+ CMP_BLANKINGSRC_TMR2_PWM_CMP3 = CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR2_PWM (specific to CMP Channel3). */
+
+ CMP_BLANKINGSRC_TMR2_PWM_CMP0 = CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR2_PWM (specific to CMP Channel0). */
+ CMP_BLANKINGSRC_TMR3_PWM_CMP1 = CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR3_PWM (specific to CMP Channel1). */
+ CMP_BLANKINGSRC_TMR2_PWM_CMP2 = CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR2_PWM (specific to CMP Channel2). */
+ CMP_BLANKINGSRC_TMR3_PWM_CMP3 = CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR3_PWM (specific to CMP Channel3). */
+
+ CMP_BLANKINGSRC_TMR3_PWM_CMP0 = CMP_CR_BLANKING_2,
+ /*!< CMP output blanking source TMR3_PWM (specific to CMP Channel0). */
+ CMP_BLANKINGSRC_TMR4_PWM_CMP1 = CMP_CR_BLANKING_2,
+ /*!< CMP output blanking source TMR4_PWM (specific to CMP Channel1). */
+ CMP_BLANKINGSRC_TMR3_PWM_CMP2 = CMP_CR_BLANKING_2,
+ /*!< CMP output blanking source TMR3_PWM (specific to CMP Channel2). */
+ CMP_BLANKINGSRC_TMR4_PWM_CMP3 = CMP_CR_BLANKING_2,
+ /*!< CMP output blanking source TMR4_PWM (specific to CMP Channel3). */
+
+ CMP_BLANKINGSRC_TMR4_PWM_CMP0 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR4_PWM (specific to CMP Channel0). */
+ CMP_BLANKINGSRC_TMR5_PWM_CMP1 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR5_PWM (specific to CMP Channel1). */
+ CMP_BLANKINGSRC_TMR4_PWM_CMP2 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR4_PWM (specific to CMP Channel2). */
+ CMP_BLANKINGSRC_TMR5_PWM_CMP3 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR5_PWM (specific to CMP Channel3). */
+
+ CMP_BLANKINGSRC_TMR5_PWM_CMP0 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR5_PWM (specific to CMP Channel0). */
+ CMP_BLANKINGSRC_TMR6_PWM_CMP1 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR6_PWM (specific to CMP Channel1). */
+ CMP_BLANKINGSRC_TMR5_PWM_CMP2 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR5_PWM (specific to CMP Channel2). */
+ CMP_BLANKINGSRC_TMR6_PWM_CMP3 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1,
+ /*!< CMP output blanking source TMR6_PWM (specific to CMP Channel3). */
+
+ CMP_BLANKINGSRC_TMR6_PWM_CMP0 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR6_PWM (specific to CMP Channel0). */
+ CMP_BLANKINGSRC_TMR7_PWM_CMP1 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR7_PWM (specific to CMP Channel1). */
+ CMP_BLANKINGSRC_TMR6_PWM_CMP2 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR6_PWM (specific to CMP Channel2). */
+ CMP_BLANKINGSRC_TMR7_PWM_CMP3 = CMP_CR_BLANKING_2 | CMP_CR_BLANKING_1 | CMP_CR_BLANKING_0,
+ /*!< CMP output blanking source TMR7_PWM (specific to CMP Channel3). */
+} CMP_BlankingSrcETypeDef;
+
+/**
+ * @brief CMP Output Debounce
+ */
+typedef enum {
+ CMP_OUTPUT_DEBOUNCE_DISABLE = 0x0U, /*!< Disable CMP output debounce */
+ CMP_OUTPUT_DEBOUNCE_ENABLE = CMP_CR_ODEB, /*!< Enable CMP output debounce */
+} CMP_OutputDebounceETypeDef;
+
+/**
+ * @brief CMP output polarity
+ */
+typedef enum {
+ CMP_OUPUT_POLARITY_NON_INVERTED = 0x0U,
+ /*!< CMP output level is not inverted. CMP output HIGH when the input plus(INP) is at a higher voltage than the input minus(INM) */
+ CMP_OUPUT_POLARITY_INVERTED = CMP_CR_OPOL,
+ /*!< CMP output level is inverted. CMP output LOW when the input plus(INP) is at a higher voltage than the input minus(INM) */
+} CMP_OutputPolarityETypeDef;
+
+/**
+ * @brief CMP trigger interrupt
+ */
+typedef enum {
+ CMP_TRIGGER_IT_DISABLE = 0x00000000U,
+ /*!< CMP output triggering event without interrupt */
+ CMP_TRIGGER_IT_FALLING = CMP_CR_FALIE,
+ /*!< CMP output triggering event with interrupt on falling edge */
+ CMP_TRIGGER_IT_RISING = CMP_CR_RISIE,
+ /*!< CMP output triggering event with interrupt on rising edge */
+ CMP_TRIGGER_IT_RISING_FALLING = CMP_CR_RISIE | CMP_CR_FALIE,
+ /*!< CMP output triggering event with interrupt on both rising and falling edges */
+} CMP_TriggerITETypeDef;
+
+
+/**
+ * @brief CMP Channel Configuration structure definition
+ */
+typedef struct __CMP_ChannelConfTypeDef {
+ CMP_InputMinusETypeDef InputMinus; /*!< Set comparator input minus (INM). */
+ CMP_HysteresisETypeDef Hysteresis; /*!< Set comparator hysteresis mode of the input minus(INM). */
+ CMP_BlankingSrcETypeDef BlankingSource; /*!< Set comparator blanking source. */
+ CMP_OutputDebounceETypeDef OutputDebounce; /*!< Set comparator output debounce. */
+ CMP_OutputPolarityETypeDef OutputPolarity; /*!< Set comparator output polarity. */
+ CMP_TriggerITETypeDef TriggerInterrupt; /*!< Set the comparator output triggering with or without interrupt. */
+
+ uint32_t OutputDebounceValue; /*!< Set comparator output debounce vaule. This Should be configured when
+ Output Debounce is enabled.
+ this value can be a range from 0 - 0xFFF (in System Clocks) */
+} CMP_ChannelConfTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CMP_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_CMP_Init(CMP_TypeDef *Instance);
+LL_StatusETypeDef LL_CMP_DeInit(CMP_TypeDef *Instance);
+void LL_CMP_MspInit(CMP_TypeDef *Instance);
+void LL_CMP_MspDeInit(CMP_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup CMP_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_CMP_ChannelConfig(CMP_TypeDef *Instance, uint32_t Channel, CMP_ChannelConfTypeDef *sConfig);
+/**
+ * @}
+ */
+
+
+/** @addtogroup CMP_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_CMP_Start(CMP_TypeDef *Instance, uint32_t Channel);
+LL_StatusETypeDef LL_CMP_Stop(CMP_TypeDef *Instance, uint32_t Channel);
+/**
+ * @}
+ */
+
+
+/** @addtogroup CMP_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_CMP_IRQHandler(CMP_TypeDef *Instance);
+void LL_CMP_FailingEdgeTrigCallback(CMP_TypeDef *Instance, uint32_t Channel);
+void LL_CMP_RisingEdgeTrigCallback(CMP_TypeDef *Instance, uint32_t Channel);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CMP_LL_Private_Macros CMP LL Private Macros
+ * @brief CMP LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is CMP channel number or not
+ * @param CHN_NB channel number to judge
+ * @retval 0 isn't CMP channel number
+ * @retval 1 is CMP channel number
+ */
+#define IS_CMP_NUMBER(CHN_NB) ((CHN_NB) < CMP_CHN_NB)
+
+/**
+ * @brief Judge is CMP Channel or not
+ * @param CHN Channel to judge
+ * @retval 0 isn't CMP Channel
+ * @retval 1 is CMP Channel
+ */
+#define IS_CMP_CHANNEL(CHN) (((CHN) == CMP_CHANNEL_0) || \
+ ((CHN) == CMP_CHANNEL_1) || \
+ ((CHN) == CMP_CHANNEL_2) || \
+ ((CHN) == CMP_CHANNEL_3))
+
+/**
+ * @brief Judge is CMP input minus or not
+ * @param INM input minus to judge
+ * @retval 0 isn't CMP input minus
+ * @retval 1 is CMP input minus
+ */
+#define IS_CMP_INPUT_MINUS(INM) (((INM) == CMP_INPUT_MINUS_GND) || \
+ ((INM) == CMP_INPUT_MINUS_IO1) || \
+ ((INM) == CMP_INPUT_MINUS_IO2) || \
+ ((INM) == CMP_INPUT_MINUS_DAC))
+
+/**
+ * @brief Judge is CMP hysteresis or not
+ * @param HYST hysteresis to judge
+ * @retval 0 isn't CMP hysteresis
+ * @retval 1 is CMP hysteresis
+ */
+#define IS_CMP_HYSTERESIS(HYST) (((HYST) == CMP_HYSTERESIS_NONE) || \
+ ((HYST) == CMP_HYSTERESIS_10MV) || \
+ ((HYST) == CMP_HYSTERESIS_20MV) || \
+ ((HYST) == CMP_HYSTERESIS_30MV))
+
+/**
+ * @brief Judge is CMP blanking source or not
+ * @param CHN CMP channel to judge
+ * @param BLANKING blanking to judge
+ * @retval 0 isn't CMP blanking source
+ * @retval 1 is CMP blanking source
+ */
+#define IS_CMP_BLANKING_SOURCE(CHN, BLANKING) ( \
+ (((CHN) == CMP_CHANNEL_0) && \
+ (((BLANKING) == CMP_BLANKINGSRC_NONE) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR0_PWM_CMP0) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR1_PWM_CMP0) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR2_PWM_CMP0) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR3_PWM_CMP0) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR4_PWM_CMP0) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR5_PWM_CMP0) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR6_PWM_CMP0))) \
+ || \
+ (((CHN) == CMP_CHANNEL_1) && \
+ (((BLANKING) == CMP_BLANKINGSRC_NONE) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR1_PWM_CMP1) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR2_PWM_CMP1) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR3_PWM_CMP1) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR4_PWM_CMP1) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR5_PWM_CMP1) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR6_PWM_CMP1) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR7_PWM_CMP1))) \
+ || \
+ (((CHN) == CMP_CHANNEL_2) && \
+ (((BLANKING) == CMP_BLANKINGSRC_NONE) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR0_PWM_CMP2) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR1_PWM_CMP2) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR2_PWM_CMP2) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR3_PWM_CMP2) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR4_PWM_CMP2) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR5_PWM_CMP2) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR6_PWM_CMP2))) \
+ || \
+ (((CHN) == CMP_CHANNEL_3) && \
+ (((BLANKING) == CMP_BLANKINGSRC_NONE) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR1_PWM_CMP3) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR2_PWM_CMP3) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR3_PWM_CMP3) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR4_PWM_CMP3) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR5_PWM_CMP3) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR6_PWM_CMP3) || \
+ ((BLANKING) == CMP_BLANKINGSRC_TMR7_PWM_CMP3))) \
+ )
+
+/**
+ * @brief Judge is CMP output debounce or not
+ * @param DEB debounce to judge
+ * @retval 0 isn't CMP output debounce
+ * @retval 1 is CMP output debounce
+ */
+#define IS_CMP_OUTPUT_DEBOUNCE(DEB) (((DEB) == CMP_OUTPUT_DEBOUNCE_DISABLE) || \
+ ((DEB) == CMP_OUTPUT_DEBOUNCE_ENABLE))
+
+/**
+ * @brief Jugdge is CMP output debounce value or not
+ * @param VAL value to judge
+ * @retval 0 isn't CMP output debounce value
+ * @retval 1 is CMP output debounce value
+ */
+#define IS_CMP_OUTPUT_DEBOUNCE_VAL(VAL) ((VAL) <= 0xFFFUL)
+
+
+/**
+ * @brief Jugdge is CMP output debounce polarity or not
+ * @param POL polarity to judge
+ * @retval 0 isn't CMP output debounce polarity
+ * @retval 1 is CMP output debounce polarity
+ */
+#define IS_CMP_OUTPUT_POLARITY(POL) (((POL) == CMP_OUPUT_POLARITY_NON_INVERTED) || \
+ ((POL) == CMP_OUPUT_POLARITY_INVERTED))
+
+/**
+ * @brief Judge is CMP trigger interrupt or not
+ * @param INTERRUPT trigger interrupt to judge
+ * @retval 0 isn't CMP trigger interrupt
+ * @retval 1 is CMP trigger interrupt
+ */
+#define IS_CMP_TRIGGER_IT(INTERRUPT) (((INTERRUPT) == CMP_TRIGGER_IT_DISABLE) || \
+ ((INTERRUPT) == CMP_TRIGGER_IT_FALLING) || \
+ ((INTERRUPT) == CMP_TRIGGER_IT_RISING) || \
+ ((INTERRUPT) == CMP_TRIGGER_IT_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_CMP_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_cortex.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_cortex.h
new file mode 100644
index 0000000000..5e4c0a8bc5
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_cortex.h
@@ -0,0 +1,208 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_cortex.h
+ * @author MCD Application Team
+ * @brief Head file for CORTEX LL module driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_CORTEX_H_
+#define _TAE32F53XX_LL_CORTEX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
+ * @brief CORTEX LL Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority, 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority, 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority, 1 bit for subpriority */
+#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority, 0 bit for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_Clock_Source CORTEX SysTick Clock Source
+ * @brief CORTEX SysTick Clock Source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< SYSTICK Clock Source HCLK Div8 */
+#define SYSTICK_CLKSOURCE_HCLK 0x00000004U /*!< SYSTICK Clock Source HCLK */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_LL_Exported_Functions_Group1
+ * @{
+ */
+void LL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+uint32_t LL_NVIC_GetPriorityGrouping(void);
+void LL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void LL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
+/**
+ * @}
+ */
+
+
+/** @addtogroup CORTEX_LL_Exported_Functions_Group2
+ * @{
+ */
+void LL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void LL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void LL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+uint32_t LL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void LL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t LL_NVIC_GetActive(IRQn_Type IRQn);
+void LL_NVIC_SystemReset(void);
+/**
+ * @}
+ */
+
+
+/** @addtogroup CORTEX_LL_Exported_Functions_Group3
+ * @{
+ */
+void LL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+uint32_t LL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+
+/** @addtogroup CORTEX_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_SYSTICK_IRQHandler(void);
+void LL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Private_Macros CORTEX LL Private Macros
+ * @brief CORTEX LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is NVIC priority group or not
+ * @param GROUP priority group to judge
+ * @retval 0 isn't NVIC priority group
+ * @retval 1 is NVIC priority group
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3))
+
+/**
+ * @brief Judge is NVIC preemption priority or not
+ * @param PRIORITY preemption priority to judge
+ * @retval 0 isn't NVIC preemption priority
+ * @retval 1 is NVIC preemption priority
+ */
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+/**
+ * @brief Judge is NVIC SubPriority or not
+ * @param PRIORITY SubPriority to judge
+ * @retval 0 isn't NVIC SubPriority
+ * @retval 1 is NVIC SubPriority
+ */
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+/**
+ * @brief Judge is NVIC device IRQ or not
+ * @param IRQ IRQ to judge
+ * @retval 0 isn't NVIC device IRQ
+ * @retval 1 is NVIC device IRQ
+ */
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
+
+/**
+ * @brief Judge is SYSTICK clock source or not
+ * @param SOURCE clock source to judge
+ * @retval 0 isn't SYSTICK clock source
+ * @retval 1 is SYSTICK clock source
+ */
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_CORTEX_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dac.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dac.h
new file mode 100644
index 0000000000..bb589b0394
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dac.h
@@ -0,0 +1,606 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dac.h
+ * @author MCD Application Team
+ * @brief Header file for DAC Module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_DAC_H_
+#define _TAE32F53XX_LL_DAC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC LL Exported Constants
+ * @brief DAC LL Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+ * @brief DAC Channel selection
+ * @{
+ */
+#define DAC_CHANNEL_0 (0x00000001U) /*!< DAC Channel 0 */
+#define DAC_CHANNEL_1 (0x00000002U) /*!< DAC Channel 1 */
+#define DAC_CHANNEL_2 (0x00000004U) /*!< DAC Channel 2 */
+#define DAC_CHANNEL_3 (0x00000008U) /*!< DAC Channel 3 */
+#define DAC_CHANNEL_ALL (DAC_CHANNEL_0 | DAC_CHANNEL_1 | DAC_CHANNEL_2 | DAC_CHANNEL_3 )
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Interrupt_definition DAC Interrupt definition
+ * @brief DAC Interrupt definition
+ * @{
+ */
+#define DAC_IT_DIE DAC_CR_DIE /*!< DAC_CHx DONE interrupt */
+#define DAC_IT_DBIE DAC_CR_DBIE /*!< DAC_CHx DONEB interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Flag_definition DAC Flag Definition
+ * @{
+ */
+#define DAC_FLAG_D0IF DAC_ISR_D0IF /*!< DAC Channel0 DONE pending flag */
+#define DAC_FLAG_D1IF DAC_ISR_D1IF /*!< DAC Channel1 DONE pending flag */
+#define DAC_FLAG_D2IF DAC_ISR_D2IF /*!< DAC Channel2 DONE pending flag */
+#define DAC_FLAG_D3IF DAC_ISR_D3IF /*!< DAC Channel0 DONE pending flag */
+#define DAC_FLAG_DB0IF DAC_ISR_DB0IF /*!< DAC Channel0 DONEB pending flag */
+#define DAC_FLAG_DB1IF DAC_ISR_DB1IF /*!< DAC Channel1 DONEB pending flag */
+#define DAC_FLAG_DB2IF DAC_ISR_DB2IF /*!< DAC Channel2 DONEB pending flag */
+#define DAC_FLAG_DB3IF DAC_ISR_DB3IF /*!< DAC Channel3 DONEB pending flag */
+#define DAC_FLAG_ALLIF (DAC_FLAG_D0IF | DAC_FLAG_D1IF | \
+ DAC_FLAG_D2IF | DAC_FLAG_D3IF | \
+ DAC_FLAG_DB0IF | DAC_FLAG_DB1IF | \
+ DAC_FLAG_DB2IF | DAC_FLAG_DB3IF )
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC LL Exported Macros
+ * @brief DAC LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable DAC Channel
+ * @param __INSTANCE__ DAC peripheral
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @return None
+ */
+#define __LL_DAC_ENABLE(__INSTANCE__, __CHN_NB__) SET_BIT((__INSTANCE__)->CR[__CHN_NB__], DAC_CR_PEN)
+
+/**
+ * @brief Disable DAC Channel
+ * @param __INSTANCE__ DAC peripheral
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @return None
+ */
+#define __LL_DAC_DISABLE(__INSTANCE__, __CHN_NB__) CLEAR_BIT((__INSTANCE__)->CR[__CHN_NB__], DAC_CR_PEN)
+
+
+/**
+ * @brief Enable DAC Channel Output to IO feature
+ * @param __INSTANCE__ DAC peripheral
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @return None
+ */
+#define __LL_DAC_OUTPUT_ENABLE(__INSTANCE__, __CHN_NB__) SET_BIT((__INSTANCE__)->CR[__CHN_NB__], DAC_CR_OEN)
+
+/**
+ * @brief Disable DAC Channel Output to IO feature
+ * @param __INSTANCE__ DAC peripheral
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @return None
+ */
+#define __LL_DAC_OUTPUT_DISABLE(__INSTANCE__, __CHN_NB__) CLEAR_BIT((__INSTANCE__)->CR[__CHN_NB__], DAC_CR_OEN)
+
+/**
+ * @brief Enable the specified DAC Channel Interrupts
+ * @param __INSTANCE__ DAC peripheral
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @param __INTERRUPT__ specifies the DAC Channel interrupt source to enable.
+ * This parameter can be any combination of @ref DAC_Interrupt_definition:
+ * @arg DAC_IT_DIE : DAC_CHx DONE interrupt
+ * @arg DAC_IT_DBIE : DAC_CHx DONEB interrupt
+ * @return None
+ */
+#define __LL_DAC_IT_ENABLE(__INSTANCE__, __CHN_NB__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CR[__CHN_NB__], __INTERRUPT__)
+
+/**
+ * @brief Disable the specified DAC Channel Interrupts
+ * @param __INSTANCE__ DAC peripheral
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @param __INTERRUPT__ specifies the DAC Channel interrupt source to disable.
+ * This parameter can be any combination of @ref DAC_Interrupt_definition:
+ * @arg DAC_IT_DIE : DAC_CHx DONE interrupt
+ * @arg DAC_IT_DBIE : DAC_CHx DONEB interrupt
+ * @return None
+ */
+#define __LL_DAC_IT_DISABLE(__INSTANCE__, __CHN_NB__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CR[__CHN_NB__], __INTERRUPT__)
+
+/**
+ * @brief Check whether the specified DAC Channel interrupt source is set or not.
+ * @param __INSTANCE__ DAC peripheral
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @param __INTERRUPT__ specifies the DAC Channel interrupt source to check.
+ * This parameter can be ONE of @ref DAC_Interrupt_definition:
+ * @arg DAC_IT_DIE : DAC_CHx DONE interrupt
+ * @arg DAC_IT_DBIE : DAC_CHx DONEB interrupt
+ * @return None
+ */
+#define __LL_DAC_IT_CHECK_SOURCE(__INSTANCE__, __CHN_NB__, __INTERRUPT__) \
+ ((READ_BIT((__INSTANCE__)->CR[__CHN_NB__], (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified pending flag is SET or not.
+ * @param __INSTANCE__ DAC peripheral.
+ * @param __FLAG__ specifies the DAC pending flag to check.
+ * This parameter can be ONE of the following values where x can be a value of
+ * 0, 1 ... (DAC_CHN_NB - 1):
+ * @arg DAC_FLAG_DxIF : DAC_CHx DONE interrupt pending flag
+ * @arg DAC_FLAG_DBxIF : DAC_CHx DONEB interrupt pending flag
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_DAC_PENDING_FLAG_GET(__INSTANCE__, __FLAG__) \
+ ((READ_BIT((__INSTANCE__)->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the specified pending flags
+ * @param __INSTANCE__ DAC peripheral.
+ * @param __FLAG__ specifies the DAC pending flag to clear.
+ * This parameter can be any combination of the following values where x can be a value of
+ * 0, 1 ... (DAC_CHN_NB - 1):
+ * @arg DAC_FLAG_DxIF : DAC_CHx DONE interrupt pending flag
+ * @arg DAC_FLAG_DBxIF : DAC_CHx DONEB interrupt pending flag
+ * @arg DAC_FLAG_ALLIF : DAC All interrupt pending flags
+ * @return None
+ */
+#define __LL_DAC_PENDING_FLAG_CLEAR(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->ISR, (__FLAG__))
+
+
+/**
+ * @brief Set the data for DAC channel conversion on runtime
+ * @param __INSTANCE__ DAC peripheral.
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @param __DATA__ Data to be loaded
+ * @return None
+ */
+#define __LL_DAC_SET_VALUE(__INSTANCE__, __CHN_NB__, __DATA__) WRITE_REG((__INSTANCE__)->WDR[__CHN_NB__], __DATA__)
+
+
+/**
+ * @brief Get the DAC channel conversion value on runtime
+ * @param __INSTANCE__ DAC peripheral.
+ * @param __CHN_NB__ Specifies DAC Channel
+ * This parameter can be a value of 0 to (DAC_CHN_NB - 1)
+ * @return Conversion value
+ */
+#define __LL_DAC_GET_VALUE(__INSTANCE__, __CHN_NB__) READ_REG((__INSTANCE__)->RDR[__CHN_NB__])
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Types DAC LL Exported Types
+ * @brief DAC LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief DAC Channel Output
+ */
+typedef enum {
+ DAC_CHANNEL_OUTPUT_DISABLE = 0x00000000U, /*!< DAC Channel Disable */
+ DAC_CHANNEL_OUTPUT_ENABLE = DAC_CR_OEN, /*!< DAC Channel Enable */
+} DAC_OutputEnETypedef;
+
+/**
+ * @brief DAC Channel Interrupt Done
+ */
+typedef enum {
+ DAC_CHANNEL_DONE_IT_DISABLE = 0x00000000U, /*!< DAC Channel Done Interrupt Disable */
+ DAC_CHANNEL_DONE_IT_ENABLE = DAC_CR_DIE, /*!< DAC Channel Done Interrupt Enable */
+} DAC_DoneITEnETypedef;
+
+/**
+ * @brief DAC Channel Interrupt DoneB
+ */
+typedef enum {
+ DAC_CHANNEL_DONEB_IT_DISABLE = 0x00000000U, /*!< DAC Channel DoneB Interrupt Disable */
+ DAC_CHANNEL_DONEB_IT_ENABLE = DAC_CR_DBIE, /*!< DAC Channel DoneB Interrupt Enable */
+} DAC_DoneBITEnETypedef;
+
+/**
+ * @brief DAC Sawtooth Polarity
+ */
+typedef enum {
+ DAC_SAWTOOTH_POLARITY_DEC = 0x00000000U, /*!< Sawtooth wave generation, polarity is decrement */
+ DAC_SAWTOOTH_POLARITY_INC = DAC_CR_STDIR, /*!< Sawtooth wave generation, polarity is increment */
+} DAC_SawthoothPolETypedef;
+
+/**
+ * @brief DAC Triangle Initial Direction
+ */
+typedef enum {
+ DAC_TRIANGLE_INITIALDIRECTION_DEC = 0x00000000U, /*!< Triangle wave generation, initial direction is decrement */
+ DAC_TRIANGLE_INITIALDIRECTION_INC = DAC_CR_TGDIR, /*!< Triangle wave generation, initial direction is increment */
+} DAC_TriangleInitDirETypedef;
+
+/**
+ * @brief DAC Triangle Amplitude
+ */
+typedef enum {
+ DAC_TRIANGLE_AMPLITUDE_1 = 0x00000000U, /*!< Amplitude of 1 */
+ DAC_TRIANGLE_AMPLITUDE_3 = DAC_CR_TGAMP_0, /*!< Amplitude of 3 */
+ DAC_TRIANGLE_AMPLITUDE_7 = DAC_CR_TGAMP_1, /*!< Amplitude of 7 */
+ DAC_TRIANGLE_AMPLITUDE_15 = DAC_CR_TGAMP_1 | DAC_CR_TGAMP_0, /*!< Amplitude of 15 */
+ DAC_TRIANGLE_AMPLITUDE_31 = DAC_CR_TGAMP_2, /*!< Amplitude of 31 */
+ DAC_TRIANGLE_AMPLITUDE_63 = DAC_CR_TGAMP_2 | DAC_CR_TGAMP_0, /*!< Amplitude of 63 */
+ DAC_TRIANGLE_AMPLITUDE_127 = DAC_CR_TGAMP_2 | DAC_CR_TGAMP_1, /*!< Amplitude of 127 */
+ DAC_TRIANGLE_AMPLITUDE_255 = DAC_CR_TGAMP_2 | DAC_CR_TGAMP_1 | DAC_CR_TGAMP_0, /*!< Amplitude of 255 */
+ DAC_TRIANGLE_AMPLITUDE_511 = DAC_CR_TGAMP_3, /*!< Amplitude of 511 */
+ DAC_TRIANGLE_AMPLITUDE_1023 = DAC_CR_TGAMP_3 | DAC_CR_TGAMP_0, /*!< Amplitude of 1023 */
+ DAC_TRIANGLE_AMPLITUDE_2047 = DAC_CR_TGAMP_3 | DAC_CR_TGAMP_1, /*!< Amplitude of 2047 */
+ DAC_TRIANGLE_AMPLITUDE_4095 = DAC_CR_TGAMP_3 | DAC_CR_TGAMP_1 | DAC_CR_TGAMP_0, /*!< Amplitude of 4095 */
+} DAC_TrangleAmplETypedef;
+
+/**
+ * @brief DAC Trigger Selection
+ */
+typedef enum {
+ DAC_TRIGGER_SOFTWARE = 0x0U, /*!< Software trigger by setting bit[s] in DAC_SWTR register */
+ DAC_TRIGGER_TMR0_TRGO = 0x1U, /*!< TRGO signal exported from TMR0 (source from Update Event) */
+ DAC_TRIGGER_TMR1_TRGO = 0x2U, /*!< TRGO signal exported from TMR1 (source from Update Event) */
+ DAC_TRIGGER_TMR2_TRGO = 0x3U, /*!< TRGO signal exported from TMR2 (source from Update Event) */
+ DAC_TRIGGER_TMR3_TRGO = 0x3U, /*!< TRGO signal exported from TMR3 (source from Update Event) */
+ DAC_TRIGGER_TMR4_TRGO = 0x4U, /*!< TRGO signal exported from TMR4 (source from Update Event) */
+ DAC_TRIGGER_TMR5_TRGO = 0x5U, /*!< TRGO signal exported from TMR5 (source from Update Event) */
+ DAC_TRIGGER_TMR6_TRGO = 0x6U, /*!< TRGO signal exported from TMR6 (source from Update Event) */
+ DAC_TRIGGER_TMR7_TRGO = 0x7U, /*!< TRGO signal exported from TMR7 (source from Update Event) */
+ DAC_TRIGGER_HRPWM_DAC_RESET_TRG0 = 0x8U, /*!< DAC Reset Trigger event from HRPWM Slave timer0 */
+ DAC_TRIGGER_HRPWM_DAC_RESET_TRG1 = 0x9U, /*!< DAC Reset Trigger event from HRPWM Slave timer1 */
+ DAC_TRIGGER_HRPWM_DAC_RESET_TRG2 = 0xAU, /*!< DAC Reset Trigger event from HRPWM Slave timer2 */
+ DAC_TRIGGER_HRPWM_DAC_RESET_TRG3 = 0xBU, /*!< DAC Reset Trigger event from HRPWM Slave timer3 */
+ DAC_TRIGGER_HRPWM_DAC_RESET_TRG4 = 0xCU, /*!< DAC Reset Trigger event from HRPWM Slave timer4 */
+ DAC_TRIGGER_HRPWM_DAC_RESET_TRG5 = 0xDU, /*!< DAC Reset Trigger event from HRPWM Slave timer5 */
+ DAC_TRIGGER_HRPWM_DAC_STEP_TRG0 = 0x8U, /*!< DAC Step Trigger event from HRPWM Slave timer0 */
+ DAC_TRIGGER_HRPWM_DAC_STEP_TRG1 = 0x9U, /*!< DAC Step Trigger event from HRPWM Slave timer1 */
+ DAC_TRIGGER_HRPWM_DAC_STEP_TRG2 = 0xAU, /*!< DAC Step Trigger event from HRPWM Slave timer2 */
+ DAC_TRIGGER_HRPWM_DAC_STEP_TRG3 = 0xBU, /*!< DAC Step Trigger event from HRPWM Slave timer3 */
+ DAC_TRIGGER_HRPWM_DAC_STEP_TRG4 = 0xCU, /*!< DAC Step Trigger event from HRPWM Slave timer4 */
+ DAC_TRIGGER_HRPWM_DAC_STEP_TRG5 = 0xDU, /*!< DAC Step Trigger event from HRPWM Slave timer5 */
+ DAC_TRIGGER_HRPWM_ADC_TRG0 = 0xEU, /*!< DAC0 Step Trigger event from HRPWM Common ADDA Trigger 0 */
+ DAC_TRIGGER_HRPWM_ADC_TRG1 = 0xEU, /*!< DAC1 Step Trigger event from HRPWM Common ADDA Trigger 1 */
+ DAC_TRIGGER_HRPWM_ADC_TRG2 = 0xEU, /*!< DAC2 Step Trigger event from HRPWM Common ADDA Trigger 2 */
+ DAC_TRIGGER_HRPWM_ADC_TRG3 = 0xEU, /*!< DAC3 Step Trigger event from HRPWM Common ADDA Trigger 3 */
+ DAC_TRIGGER_HRPWM_ADC_TRG4 = 0xEU, /*!< DAC0 Reset Trigger event from HRPWM Common ADDA Trigger 4 */
+ DAC_TRIGGER_HRPWM_ADC_TRG5 = 0xEU, /*!< DAC1 Reset Trigger event from HRPWM Common ADDA Trigger 5 */
+ DAC_TRIGGER_HRPWM_ADC_TRG6 = 0xEU, /*!< DAC2 Reset Trigger event from HRPWM Common ADDA Trigger 6 */
+ DAC_TRIGGER_HRPWM_ADC_TRG7 = 0xEU, /*!< DAC3 Reset Trigger event from HRPWM Common ADDA Trigger 7 */
+ DAC_TRIGGER_EXTERNAL_INPUT_IO1 = 0xFU, /*!< DAC External Trigger from IO1, please see SPEC from more details */
+ DAC_TRIGGER_EXTERNAL_INPUT_IO2 = 0xFU, /*!< DAC External Trigger from IO2, please see SPEC from more details */
+} DAC_TriggerSrcETypedef;
+
+
+/**
+ * @brief DAC Channel Configuration structure definition
+ */
+typedef struct __DAC_ChannelConfTypeDef {
+ DAC_OutputEnETypedef Output; /*!< Specifies the DAC conversion output to IO or not. */
+
+ uint32_t DoneIntPending; /*!< Specifies the interrupt for DONE pending flag enable or disable
+ This parameter can be a value of @ref DAC_Channel_Interrupt_Done
+ Note: Sawtooth Reset or Tranigle Step convert done will trigger the DONE flag */
+
+ uint32_t DoneBIntPending; /*!< Specifies the interrupt for DONEB pending flag enable or disable
+ This parameter can be a value of @ref DAC_Channel_Interrupt_DoneB
+ Note: Sawtooth Step convert done will trigger the DONEB flag */
+} DAC_ChannelConfTypeDef;
+
+/**
+ * @brief DAC Sawtooth Wave Configuration structure definition
+ */
+typedef struct __DAC_SawtoothConfTypeDef {
+ uint16_t ResetData; /*!< Specifies the Sawtooth wave Reset value.
+ This parameter can be a number in range from 0 to DAC full range 4095(0xFFF) */
+
+ uint16_t StepData; /*!< Specifies the Sawtooth wave step value.
+ 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
+ Step value step is 1/16 = 0.0625
+ Step value range is 0.0000 to 4095.9375 (0xFFF.F) */
+
+ DAC_TriggerSrcETypedef ResetTrigger; /*!< Specifies the external trigger source for the Sawtooth wave reset trigger
+ Please see the SPEC Document for more details about the trigger selections */
+ DAC_TriggerSrcETypedef StepTrigger; /*!< Specifies the external trigger source for the Sawtooth wave step trigger
+ Please see the SPEC Document for more details about the trigger selections */
+ DAC_SawthoothPolETypedef Polarity; /*!< Specifies the Sawtooth wave step polarity.*/
+} DAC_SawtoothConfTypeDef;
+
+/**
+ * @brief DAC Triangle Wave Configuration structure definition
+ */
+typedef struct __DAC_TriangleConfTypeDef {
+ DAC_TriangleInitDirETypedef InitialDirection; /*!< Specifies the Triangle wave initial step direction. */
+ DAC_TrangleAmplETypedef Amplitude; /*!< Specifies max triangle amplitude. */
+ DAC_TriggerSrcETypedef StepTrigger; /*!< Specifies the external trigger source for the Triangle wave step trigger
+ Please see the SPEC Document for more details about the trigger selections */
+} DAC_TriangleConfTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_DAC_Init(DAC_TypeDef *Instance);
+LL_StatusETypeDef LL_DAC_DeInit(DAC_TypeDef *Instance);
+void LL_DAC_MspInit(DAC_TypeDef *Instance);
+void LL_DAC_MspDeInit(DAC_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DAC_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_DAC_ChannelConfig(DAC_TypeDef *Instance, uint32_t Channel, DAC_ChannelConfTypeDef *sConfig);
+LL_StatusETypeDef LL_DAC_SawtoothWaveGenerate(DAC_TypeDef *Instance, uint32_t Channel, DAC_SawtoothConfTypeDef *sConfig);
+LL_StatusETypeDef LL_DAC_TriangleWaveGenerate(DAC_TypeDef *Instance, uint32_t Channel, DAC_TriangleConfTypeDef *sConfig);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DAC_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_DAC_Start(DAC_TypeDef *Instance, uint32_t Channel);
+LL_StatusETypeDef LL_DAC_Stop(DAC_TypeDef *Instance, uint32_t Channel);
+LL_StatusETypeDef LL_DAC_SetValue(DAC_TypeDef *Instance, uint32_t Channel, uint16_t Data);
+uint16_t LL_DAC_GetValue(DAC_TypeDef *Instance, uint32_t Channel);
+LL_StatusETypeDef LL_DAC_SawtoothWaveDataStep(DAC_TypeDef *Instance, uint32_t Channel);
+LL_StatusETypeDef LL_DAC_SawtoothWaveDataReset(DAC_TypeDef *Instance, uint32_t Channel);
+LL_StatusETypeDef LL_DAC_TriangleWaveStep(DAC_TypeDef *Instance, uint32_t Channel);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DAC_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_DAC_IRQHandler(DAC_TypeDef *Instance);
+void LL_DAC_ConvDoneCallback(DAC_TypeDef *Instance, uint32_t Channel);
+void LL_DAC_ConvDoneBCallback(DAC_TypeDef *Instance, uint32_t Channel);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC LL Private Macros
+ * @brief DAC LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is DAC channel number or not
+ * @param CHN_NB channel number to judge
+ * @retval 0 isn't DAC channel number
+ * @retval 1 is DAC channel number
+ */
+#define IS_DAC_NUMBER(CHN_NB) ((CHN_NB) < DAC_CHN_NB)
+
+/**
+ * @brief Judge is DAC channel or not
+ * @param CHN channel to judge
+ * @retval 0 isn't DAC channel
+ * @retval 1 is DAC channel
+ */
+#define IS_DAC_CHANNEL(CHN) (((CHN) == DAC_CHANNEL_0) || \
+ ((CHN) == DAC_CHANNEL_1) || \
+ ((CHN) == DAC_CHANNEL_2) || \
+ ((CHN) == DAC_CHANNEL_3))
+
+/**
+ * @brief Judge is DAC channels mask or not
+ * @param CHN channels mask to judge
+ * @retval 0 isn't DAC channels mask
+ * @retval 1 is DAC channels mask
+ */
+#define IS_DAC_CHANNELS_MASK(CHN) ((((CHN) & DAC_CHANNEL_ALL) != 0x00UL) && \
+ (((CHN) & ~(DAC_CHANNEL_ALL)) == 0x00UL))
+
+/**
+ * @brief Judge is DAC channel output select or not
+ * @param OUTPUT output select
+ * @retval 0 isn't DAC channel output select
+ * @retval 1 is DAC channel output select
+ */
+#define IS_DAC_CHANNEL_OUTPUT_SEL(OUTPUT) (((OUTPUT) == DAC_CHANNEL_OUTPUT_DISABLE) || \
+ ((OUTPUT) == DAC_CHANNEL_OUTPUT_ENABLE))
+
+/**
+ * @brief Judge is DAC channel done interrupt pending config or not
+ * @param PENDING pending config to judge
+ * @retval 0 isn't DAC channel done interrupt pending config
+ * @retval 1 is DAC channel done interrupt pending config
+ */
+#define IS_DAC_CHANNEL_DONE_IT_PENDING_CFG(PENDING) (((PENDING) == DAC_CHANNEL_DONE_IT_DISABLE) || \
+ ((PENDING) == DAC_CHANNEL_DONE_IT_ENABLE))
+
+/**
+ * @brief Judge is DAC channel doneB interrupt pending config or not
+ * @param PENDING pending config to judge
+ * @retval 0 isn't DAC channel doneB interrupt pending config
+ * @retval 1 is DAC channel doneB interrupt pending config
+ */
+#define IS_DAC_CHANNEL_DONEB_IT_PENDING_CFG(PENDING) (((PENDING) == DAC_CHANNEL_DONEB_IT_DISABLE) || \
+ ((PENDING) == DAC_CHANNEL_DONEB_IT_ENABLE))
+
+/**
+ * @brief Judge is DAC sawtooth reset data or not
+ * @param DATA data to judge
+ * @retval 0 isn't DAC sawtooth reset data
+ * @retval 1 is DAC sawtooth reset data
+ */
+#define IS_DAC_SAWTOOTH_RESET_DATA(DATA) ((DATA) <= 0xFFFUL)
+
+/**
+ * @brief Judge is DAC sawtooth step data or not
+ * @param DATA data to judge
+ * @retval 0 isn't DAC sawtooth step data
+ * @retval 1 is DAC sawtooth step data
+ */
+#define IS_DAC_SAWTOOTH_STEP_DATA(DATA) ((DATA) <= 0xFFFFUL)
+
+/**
+ * @brief Judge is DAC sawtooth reset trigger or not
+ * @param TRIGGER trigger to judge
+ * @retval 0 isn't DAC sawtooth reset trigger
+ * @retval 1 is DAC sawtooth reset trigger
+ */
+#define IS_DAC_SAWTOOTH_RESET_TRIGGER(TRIGGER) ((TRIGGER) < 16U)
+
+/**
+ * @brief Judge is DAC sawtooth step trigger or not
+ * @param TRIGGER trigger to judge
+ * @retval 0 isn't DAC sawtooth step trigger
+ * @retval 1 is DAC sawtooth step trigger
+ */
+#define IS_DAC_SAWTOOTH_STEP_TRIGGER(TRIGGER) ((TRIGGER) < 16U)
+
+/**
+ * @brief Judge is DAC sawtooth polarity or not
+ * @param POLARITY polarity to judge
+ * @retval 0 isn't DAC sawtooth polarity
+ * @retval 1 is DAC sawtooth polarity
+ */
+#define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DEC) || \
+ ((POLARITY) == DAC_SAWTOOTH_POLARITY_INC))
+
+/**
+ * @brief Judge is DAC triangle initial direction or not
+ * @param DIR direction to judge
+ * @retval 0 isn't DAC triangle initial direction
+ * @retval 1 is DAC triangle initial direction
+ */
+#define IS_DAC_TRIANGLE_INITIALDIRECTION(DIR) (((DIR) == DAC_TRIANGLE_INITIALDIRECTION_DEC) || \
+ ((DIR) == DAC_TRIANGLE_INITIALDIRECTION_INC))
+
+/**
+ * @brief Judge is DAC triangle amplitude or not
+ * @param AMP amplitude to judge
+ * @retval 0 isn't DAC triangle amplitude
+ * @retval 1 is DAC triangle amplitude
+ */
+#define IS_DAC_TRIANGLE_AMPLITUDE(AMP) (((AMP) == DAC_TRIANGLE_AMPLITUDE_1) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_3) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_7) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_15) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_31) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_63) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_127) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_255) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_511) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_1023) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_2047) || \
+ ((AMP) == DAC_TRIANGLE_AMPLITUDE_4095))
+
+/**
+ * @brief Judge is DAC triangle step trigger or not
+ * @param TRIGGER trigger to judge
+ * @retval 0 isn't DAC triangle step trigger
+ * @retval 1 is DAC triangle step trigger
+ */
+#define IS_DAC_TRIANGLE_STEP_TRIGGER(TRIGGER) ((TRIGGER) < 16U)
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_DAC_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dali.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dali.h
new file mode 100644
index 0000000000..0c043f9558
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dali.h
@@ -0,0 +1,499 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dali.h
+ * @author MCD Application Team
+ * @brief Header file for DALI module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_DALI_H_
+#define _TAE32F53XX_LL_DALI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup DALI_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DALI_LL_Exported_Types DALI LL Exported Types
+ * @brief DALI LL Exported Types
+ * @{
+ */
+
+/** @defgroup DALI_Mode_Selection DALI mode selection
+ * @brief DALI mode selection
+ * @{
+ */
+typedef enum {
+ DALI_MODE_SLAVE = 0, /*!< Slave mode */
+ DALI_MODE_MASTER = DALI_CR_MODE, /*!< Master mode */
+} DALI_ModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup DALI_Forward_Message_Length DALI forward frame message length
+ * @brief DALI forward frame message length
+ * @{
+ */
+typedef enum {
+ DALI_MESSAGELENGTH_16Bit = 0, /*!< DALI Forward frame message length sets to 16 bits */
+ DALI_MESSAGELENGTH_17Bit = DALI_CR_ML_0, /*!< DALI Forward frame message length sets to 17 bits */
+ DALI_MESSAGELENGTH_18Bit = DALI_CR_ML_1, /*!< DALI Forward frame message length sets to 18 bits */
+ DALI_MESSAGELENGTH_24Bit = (DALI_CR_ML_0 | DALI_CR_ML_1), /*!< DALI Forward frame message length sets to 24 bits */
+} DALI_MsgLenETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup DALI_Polarity_Selection DALI polarity selection
+ * @brief DALI polarity selection
+ * @{
+ */
+typedef enum {
+ DALI_POLARITY_ACTIVE_HIGH = 0, /*!< Active High */
+ DALI_POLARITY_ACTIVE_LOW = DALI_CR_POL, /*!< Active Low */
+} DALI_PolETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup DALI_Filter_Selection DALI filter selection
+ * @brief DALI filter selection
+ * @{
+ */
+typedef enum {
+ DALI_FILTER_DISABLE = 0, /*!< Disable filter feature */
+ DALI_FILTER_ENABLE = DALI_FCR_FE, /*!< Enable filter feature */
+} DALI_FilterETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup DALI_Interrupt_definition DALI Interrupt Definition
+ * @brief DALI Interrupt Definition
+ * @{
+ */
+typedef enum {
+ DALI_IT_BEIE = DALI_CR_BEIE, /*!< DALI Backward Error Interrupt Enable */
+ DALI_IT_FEIE = DALI_CR_FEIE, /*!< DALI Forward Error Interrupt Enable */
+ DALI_IT_BDIE = DALI_CR_BDIE, /*!< DALI Backward Done Interrupt Enable */
+ DALI_IT_FDIE = DALI_CR_FDIE, /*!< DALI Forward Done Interrupt Enable */
+} DALI_IntETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup DALI_Pending_Flag_definition DALI Pending Flag Definition
+ * @brief DALI Pending Flag Definition
+ * @{
+ */
+typedef enum {
+ DALI_FLAG_BEIF = DALI_ISR_BEIF, /*!< DALI Backward Error Pending Flag */
+ DALI_FLAG_FEIF = DALI_ISR_FEIF, /*!< DALI Forward Error Pending Flag */
+ DALI_FLAG_BDIF = DALI_ISR_BDIF, /*!< DALI Backward Done Pending Flag */
+ DALI_FLAG_FDIF = DALI_ISR_FDIF, /*!< DALI Forward Done Pending Flag */
+} DALI_FlagTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup DALI_Status_Flag_definition DALI Status Flag Definition
+ * @brief DALI Status Flag Definition
+ * @{
+ */
+typedef enum {
+ DALI_FLAG_BSY = DALI_ISR_BSY, /*!< DALI BUSY Status Flag */
+} DALI_StatusTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup DALI_Baudrate_definition DALI Baudrate Definition
+ * @brief DALI Baudrate Definition
+ * @{
+ */
+typedef enum {
+ DALI_BAUDRATE_1K2 = 1200U, /*!< DALI Baudrate 1.2K */
+ DALI_BAUDRATE_2K4 = 2400U, /*!< DALI Baudrate 2.4K */
+ DALI_BAUDRATE_4K8 = 4800U, /*!< DALI Baudrate 4.8K */
+} DALI_BaudETypeDef;
+/**
+ * @}
+ */
+
+
+/**
+ * @brief DALI Initialization Structure definition
+ */
+typedef struct __DALI_InitTypeDef {
+ DALI_ModeETypeDef Mode; /*!< Specifies the DALI working mode.
+ This parameter can be a value in @ref DALI_ModeETypeDef */
+
+ DALI_BaudETypeDef Baudrate; /*!< Specifies the DALI division value
+ This parameter can be a value in @ref DALI_BaudETypeDef */
+
+ DALI_MsgLenETypeDef MessageLen; /*!< Specifies the DALI Forward frame message length.
+ This parameter can be a value in @ref DALI_MsgLenETypeDef */
+
+ DALI_PolETypeDef Polarity; /*!< Specifies the DALI polarity
+ This parameter can be a value in @ref DALI_PolETypeDef */
+
+ DALI_FilterETypeDef Filter; /*!< Specifies the DALI enable filter or not.
+ This parameter can be a value in @ref DALI_FilterETypeDef */
+
+ uint16_t FilterCounter; /*!< Specifies the DALI filter counter value (in APB1 Clock)
+ This parameter can be a number in range from 0 to 0xFFFF */
+
+ uint16_t ForwardDelay; /*!< Specifies the DALI forward frame delay timing.
+ This parameter can be a number in range from 0 to 511
+ DelayTime(ms) = (22 + ForwardDelay) * T */
+
+ uint16_t BackwardDelay; /*!< Specifies the DALI backward frame delay timing.
+ This parameter can be a number in range from 0 to 127
+ DelayTime(ms) = (7 + BackwardDelay) * T */
+} DALI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DALI_LL_Exported_Macros DALI LL Exported Macros
+ * @brief DALI LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the DALI peripheral
+ * @param __INSTANCE__ DALI peripheral
+ * @return None
+ */
+#define __LL_DALI_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, DALI_CR_PEN)
+
+/**
+ * @brief Disable the DALI peripheral
+ * @param __INSTANCE__ DALI peripheral
+ * @return None
+ */
+#define __LL_DALI_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, DALI_CR_PEN)
+
+
+/**
+ * @brief Enable the specified DALI Interrupts
+ * @param __INSTANCE__ DALI peripheral
+ * @param __IT__ specifies the DALI interrupt source to enable.
+ * This parameter can be any combination of @enum DALI_IntETypeDef in
+ * @ref DALI_Interrupt_definition
+ * @return None
+ */
+#define __LL_DALI_IT_ENABLE(__INSTANCE__, __IT__) SET_BIT((__INSTANCE__)->CR, (__IT__))
+
+/**
+ * @brief Disable the specified DALI Interrupts
+ * @param __INSTANCE__ DALI peripheral
+ * @param __IT__ specifies the DALI interrupt source to disable.
+ * This parameter can be any combination of @enum DALI_IntETypeDef in
+ * @ref DALI_Interrupt_definition
+ * @return None
+ */
+#define __LL_DALI_IT_DISABLE(__INSTANCE__, __IT__) CLEAR_BIT((__INSTANCE__)->CR, (__IT__))
+
+/**
+ * @brief Check whether the specified DALI Channel interrupt source is set or not.
+ * @param __INSTANCE__ DALI peripheral
+ * @param __IT__ specifies the DALI Channel interrupt source to check.
+ * This parameter can be ONE of @enum DALI_IntETypeDef in @ref DALI_Interrupt_definition
+ @return The state of __IT__ (SET or RESET).
+ */
+#define __LL_DALI_IT_SOURCE_CHECK(__INSTANCE__, __IT__) ((READ_BIT((__INSTANCE__)->CR, (__IT__)) == (__IT__)) ? SET : RESET)
+
+/**
+ * @brief Clear the specified pending flags
+ * @param __INSTANCE__ DALI peripheral.
+ * @param __FLAG__ Specifies the DALI pending flag to clear.
+ * This parameter can be any combination of @enum DALI_FlagTypeDef in
+ * @ref DALI_Pending_Flag_definition
+ * @return None
+ */
+#define __LL_DALI_PENDING_FLAG_CLEAR(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->ISR, (__FLAG__))
+
+/**
+ * @brief Check whether the specified pending flag is SET or not.
+ * @param __INSTANCE__ DALI peripheral.
+ * @param __FLAG__ Specifies the DALI pending flag to get.
+ * This parameter can be ONE of @enum DALI_FlagTypeDef in @ref DALI_Pending_Flag_definition
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_DALI_PENDING_FLAG_GET(__INSTANCE__, __FLAG__) ((READ_BIT((__INSTANCE__)->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+
+/**
+ * @brief Check whether the specified status flag is SET or not.
+ * @param __INSTANCE__ DALI peripheral.
+ * @param __FLAG__ Specifies the DALI pending flag to get.
+ * This parameter can be ONE of @enum DALI_StatusTypeDef in @ref DALI_Status_Flag_definition
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_DALI_STATUS_FLAG_GET(__INSTANCE__, __STA__) ((READ_BIT((__INSTANCE__)->ISR, (__STA__)) == (__STA__)) ? SET : RESET)
+
+/**
+ * @brief DALI master writes forward data to DALI_FDR register on runtime
+ * @param __INSTANCE__ DALI peripheral.
+ * @param __DATA__ Forward frame data
+ * @return None
+ */
+#define __LL_DALI_MSTR_WRITE_FORWARD_DATA(__INSTANCE__, __DATA__) WRITE_REG((__INSTANCE__)->FDR, (__DATA__) & 0xFFFFFFUL)
+
+/**
+ * @brief DALI master reads backward data from DALI_BDR register on runtime
+ * @param __INSTANCE__ DALI peripheral.
+ * @return Backward data
+ */
+#define __LL_DALI_MSTR_READ_BACKWARD_DATA(__INSTANCE__) (READ_REG((__INSTANCE__)->BDR) & 0xFFUL)
+
+/**
+ * @brief DALI slave writes backward data to DALI_BDR register on runtime
+ * @param __INSTANCE__ DALI peripheral.
+ * @param __DATA__ Backward frame data
+ * @return None
+ */
+#define __LL_DALI_SLV_WRITE_BACKWARD_DATA(__INSTANCE__, __DATA__) WRITE_REG((__INSTANCE__)->BDR, (__DATA__) & 0xFFUL)
+
+/**
+ * @brief DALI slave reads forward data from DALI_FDR register on runtime
+ * @param __INSTANCE__ DALI peripheral.
+ * @return Forward data
+ */
+#define __LL_DALI_SLV_READ_FORWARD_DATA(__INSTANCE__) (READ_REG((__INSTANCE__)->FDR) & 0xFFFFFFUL)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DALI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DALI_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_DALI_Init(DALI_TypeDef *Instance, DALI_InitTypeDef *Init);
+LL_StatusETypeDef LL_DALI_DeInit(DALI_TypeDef *Instance);
+void LL_DALI_MspInit(DALI_TypeDef *Instance);
+void LL_DALI_MspDeInit(DALI_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DALI_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_DALI_WaitForLastOperation(DALI_TypeDef *Instance, uint32_t Timeout);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DALI_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_DALI_Master_Transmit(DALI_TypeDef *Instance, uint32_t ForwardData);
+LL_StatusETypeDef LL_DALI_Master_Transmit_IT(DALI_TypeDef *Instance, uint32_t ForwardData);
+LL_StatusETypeDef LL_DALI_Master_Receive(DALI_TypeDef *Instance, uint8_t *BackwardData);
+LL_StatusETypeDef LL_DALI_Master_Receive_IT(DALI_TypeDef *Instance);
+
+LL_StatusETypeDef LL_DALI_Slave_Transmit(DALI_TypeDef *Instance, uint8_t BackwardData);
+LL_StatusETypeDef LL_DALI_Slave_Transmit_IT(DALI_TypeDef *Instance, uint8_t BackwardData);
+LL_StatusETypeDef LL_DALI_Slave_Receive(DALI_TypeDef *Instance, uint32_t *ForwardData);
+LL_StatusETypeDef LL_DALI_Slave_Receive_IT(DALI_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DALI_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_DALI_IRQHandler(DALI_TypeDef *Instance);
+
+void LL_DALI_MstrRecviveDoneCallback(DALI_TypeDef *Instance);
+void LL_DALI_MstrRecviveErrorCallback(DALI_TypeDef *Instance);
+void LL_DALI_MstrTransmitDoneCallback(DALI_TypeDef *Instance);
+void LL_DALI_MstrTransmitErrorCallback(DALI_TypeDef *Instance);
+
+void LL_DALI_SlvReceiveDoneCallback(DALI_TypeDef *Instance);
+void LL_DALI_SlvReceiveErrorCallback(DALI_TypeDef *Instance);
+void LL_DALI_SlvTransmitDoneCallback(DALI_TypeDef *Instance);
+void LL_DALI_SlvTransmitErrorCallback(DALI_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DALI_LL_Private_Constants DALI LL private constants
+ * @brief DALI LL private constants
+ * @{
+ */
+
+/**
+ * @brief Max timeout for DALI operations, Default 1000 ticks
+ */
+#define DALI_TIMEOUT_MAX_VALUE 1000UL
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DALI_LL_Private_Macros DALI LL private macros
+ * @brief DALI LL private macros
+ * @{
+ */
+
+/**
+ * @brief Judge is DALI mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't DALI mode
+ * @retval 1 is DALI mode
+ */
+#define IS_DALI_MODE(__MODE__) (((__MODE__) == DALI_MODE_MASTER) || \
+ ((__MODE__) == DALI_MODE_SLAVE))
+
+/**
+ * @brief Judge is DALI message length or not
+ * @param __LEN__ length to judge
+ * @retval 0 isn't DALI message length
+ * @retval 1 is DALI message length
+ */
+#define IS_DALI_MESSAGE_LEN(__LEN__) (((__LEN__) == DALI_MESSAGELENGTH_16Bit) || \
+ ((__LEN__) == DALI_MESSAGELENGTH_17Bit) || \
+ ((__LEN__) == DALI_MESSAGELENGTH_18Bit) || \
+ ((__LEN__) == DALI_MESSAGELENGTH_24Bit))
+
+/**
+ * @brief Judge is DALI polarity or not
+ * @param __POL__ polarity to judge
+ * @retval 0 isn't DALI polarity
+ * @retval 1 is DALI polarity
+ */
+#define IS_DALI_POLARITY(__POL__) (((__POL__) == DALI_POLARITY_ACTIVE_HIGH) || \
+ ((__POL__) == DALI_POLARITY_ACTIVE_LOW))
+
+/**
+ * @brief Judge is DALI filter enable or not
+ * @param __EN__ enable to judge
+ * @retval 0 isn't DALI filter enable
+ * @retval 1 is DALI filter enable
+ */
+#define IS_DALI_FILTER_ENABLE(__EN__) (((__EN__) == DALI_FILTER_DISABLE) || \
+ ((__EN__) == DALI_FILTER_ENABLE))
+
+/**
+ * @brief Judge is DALI filter counter or not
+ * @param __CNT__ counter to judge
+ * @retval 0 isn't DALI filter counter
+ * @retval 1 is DALI filter counter
+ */
+#define IS_DALI_FILTER_COUNTER(__CNT__) ((__CNT__) <= 0xFFFFUL)
+
+/**
+ * @brief Judge is DALI forward delay or not
+ * @param __DLY__ delay to judge
+ * @retval 0 isn't DALI forward delay
+ * @retval 1 is DALI forward delay
+ */
+#define IS_DALI_FORWARD_DELAY(__DLY__) ((__DLY__) <= 0x1FFUL)
+
+/**
+ * @brief Judge is DALI backward delay or not
+ * @param __DLY__ delay to judge
+ * @retval 0 isn't DALI backward delay
+ * @retval 1 is DALI backward delay
+ */
+#define IS_DALI_BACKWARD_DELAY(__DLY__) ((__DLY__) <= 0x7FUL)
+
+/**
+ * @brief Judge is DALI prescale or not
+ * @param __PSC__ prescale to judge
+ * @retval 0 isn't DALI prescale
+ * @retval 1 is DALI prescale
+ */
+#define IS_DALI_PRESCALE(__PSC__) ((__PSC__) <= 0xFFFUL)
+
+/**
+ * @brief Judge is DALI supported baudrate or not
+ * @param __BRT__ Baudrate to judge
+ * @retval 0 isn't DALI supported baudrate
+ * @retval 1 is DALI supported baudrate
+ */
+#define IS_DALI_BAUDRATE(__BRT__) (((__BRT__) == DALI_BAUDRATE_1K2) || \
+ ((__BRT__) == DALI_BAUDRATE_2K4) || \
+ ((__BRT__) == DALI_BAUDRATE_4K8))
+
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_DALI_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_def.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_def.h
new file mode 100644
index 0000000000..edae4890ee
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_def.h
@@ -0,0 +1,306 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_def.h
+ * @author MCD Application Team
+ * @brief This file contains LL common defines, enumeration, macros and
+ * structures definitions.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_DEF_H_
+#define _TAE32F53XX_LL_DEF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include
+#include "tae32f53xx.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup DEFINE_LL DEFINE LL
+ * @brief DEFINE LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DEFINE_LL_Exported_Constants DEFINE LL Exported Constants
+ * @brief DEFINE LL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief LL wait forever time definition
+ */
+#define LL_WAIT_FOREVER 0xFFFFFFFFUL
+
+/**
+ * @brief LL wait max delay time definition
+ */
+#define LL_MAX_DELAY (LL_WAIT_FOREVER - 1U)
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DEFINE_LL_Exported_Types DEFINE LL Exported Types
+ * @brief DEFINE LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief LL Status type definition
+ */
+typedef enum {
+ LL_OK = 0x00U, /*! LL status OK */
+ LL_ERROR = 0x01U, /*! LL status ERROR */
+ LL_BUSY = 0x02U, /*! LL status BUSY */
+ LL_TIMEOUT = 0x03U, /*! LL status TIMEOUT */
+ LL_FAILED = 0x04U, /*! LL status FAILED */
+} LL_StatusETypeDef;
+
+/**
+ * @brief LL Flag status type definition
+ */
+typedef enum {
+ RESET = 0, /*!< LL flag status RESET */
+ SET = !RESET, /*!< LL flag status SET */
+} LL_FlagStatusETypeDef;
+
+/**
+ * @brief LL Functional status type definition
+ */
+typedef enum {
+ DISABLE = 0, /*!< LL functional status DISABLE */
+ ENABLE = !DISABLE, /*!< LL functional status ENABLE */
+} LL_FuncStatusETypeDef;
+
+/**
+ * @brief LL Error status type definiton
+ */
+typedef enum {
+ SUCCESS = 0U, /*!< LL error status SUCCESS */
+ ERROR = !SUCCESS, /*!< LL error status ERROR */
+} LL_ErrStatusETypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DEFINE_LL_Exported_Macros DEFINE LL Exported Macros
+ * @brief DEFINE LL Exported Macros
+ * @{
+ */
+
+/* Compiler ALIAS and WEAK attribute definition */
+#if defined (__CC_ARM) /*!< AC5 Compiler */
+#define __ALIAS_FUNC(FUNC) __attribute__ ((weak, alias(#FUNC)))
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void) __attribute__ ((weak, alias(#FUNC_ALIAS)));
+#elif defined (__ICCARM__) /*!< IAR Compiler */
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void);_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS)))
+#define _WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) weak WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /*!< AC6 Compiler */
+#define __ALIAS_FUNC(FUNC) __attribute__ ((weak, alias(#FUNC)))
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void) __attribute__ ((weak, alias(#FUNC_ALIAS)));
+#elif defined (__GNUC__) /*!< GCC Compiler */
+#define __ALIAS_FUNC(FUNC) __attribute__ ((weak, alias(#FUNC)))
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void) __attribute__ ((weak, alias(#FUNC_ALIAS)));
+#else
+#error Not supported compiler type
+#endif
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+/* Compiler aligned on 4-bytes attribute definition */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4)))
+#endif
+
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+
+#else
+
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif
+
+#ifndef __ALIGN_BEGIN
+#if defined (__CC_ARM) /* ARM Compiler */
+#define __ALIGN_BEGIN __align(4)
+#elif defined (__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif
+#endif
+#endif
+
+
+/* Compiler __NOINLINE attribute definition */
+#if defined (__CC_ARM) || defined (__GNUC__) /* ARM & GNUCompiler */
+#define __NOINLINE __attribute__ ( (noinline) )
+#elif defined (__ICCARM__) /* ICCARM Compiler */
+#define __NOINLINE _Pragma("optimize = no_inline")
+#endif
+
+
+/* Compiler misc attribute definition */
+#if defined (__CC_ARM) /*!< AC5 Compiler */
+#define __NO_INIT __attribute__((zero_init))
+#define __AT(n) __attribute__((at(n)))
+#define __SECTION(SECT) __attribute__((section(#SECT)))
+#elif defined (__ICCARM__) /*!< IAR Compiler */
+#define __NO_INIT __no_init
+#define __AT(n) @(n)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /*!< AC6 Compiler */
+#define __NO_INIT
+#define __AT(n) __attribute__ ((section(".ARM.__at_"#n)))
+#define __SECTION(SECT) __attribute__((section(#SECT)))
+#elif defined (__GNUC__) /*!< GCC Compiler */
+#define __NO_INIT __attribute__((zero_init))
+#define __AT(n)
+#define __SECTION(SECT) __attribute__((section(#SECT)))
+#endif
+
+
+/**
+ * @brief Bit left shift definition
+ * @param pos left shift position
+ * @return Bit left shift value
+ */
+#define BIT(pos) (1U << (pos))
+
+/**
+ * @brief Set bit definition
+ * @param REG register
+ * @param BIT Bit to set
+ * @return None
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+/**
+ * @brief Clear bit definition
+ * @param REG register
+ * @param BIT Bit to clear
+ * @return None
+ */
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+/**
+ * @brief Read bit definition
+ * @param REG register
+ * @param BIT Bit to read
+ * @return None
+ */
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+/**
+ * @brief Clear register definiton
+ * @param REG register
+ * @return None
+ */
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+/**
+ * @brief Write register definiton
+ * @param REG register
+ * @param VAL write value
+ * @return None
+ */
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+/**
+ * @brief Read register definition
+ * @param REG register
+ * @return None
+ */
+#define READ_REG(REG) ((REG))
+
+/**
+ * @brief Modify register definition
+ * @param REG register
+ * @param CLEARMASK clear mask
+ * @param SETMASK set mask
+ * @return None
+ */
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @brief Position value definition
+ * @param VAL value
+ * @return None
+ */
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+
+/**
+ * @brief To avoid gcc/g++ warnings
+ * @param X avoid warning param
+ * @return None
+ */
+#define LL_UNUSED(X) (void)X
+
+/**
+ * @brief Macro for counting the element number of an array
+ * @param a Array to be Counted
+ * @return size of Array
+ */
+#define ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0]))
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_DEF_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dflash.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dflash.h
new file mode 100644
index 0000000000..3ddd325b7d
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dflash.h
@@ -0,0 +1,271 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dflash.h
+ * @author MCD Application Team
+ * @brief Header file for DataFlash module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_DFLASH_H_
+#define _TAE32F53XX_LL_DFLASH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup DFLASH_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DFLASH_LL_Exported_Constants DFLASH LL Exported Constants
+ * @brief DFLASH LL Exported Constants
+ * @{
+ */
+
+/** @defgroup DFLASH_Keys DFLASH Keys
+ * @brief DFLASH Keys
+ * @{
+ */
+#define DFLASH_KEY1 0x32107654U /*!< DFLASH key1 */
+#define DFLASH_KEY2 0xFEDCBA98U /*!< DFLASH key2: used with DFLASH_KEY1 to unlock the DFLASH Program/Read/Erase features*/
+/**
+ * @}
+ */
+
+/** @defgroup DFLASH_Flag_definition DFLASH Flag Definition
+ * @brief DFLASH Flag Definition
+ * @{
+ */
+#define DFLASH_FLAG_BSY DFLASH_SR_BSY /*!< DFLASH flag BSY */
+#define DFLASH_FLAG_DIF DFLASH_ISR_DIF /*!< DFLASH flag DIF */
+#define DFLASH_FLAG_EIF DFLASH_ISR_EIF /*!< DFLASH flag EIF */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DFLASH_LL_Exported_Macros DFLASH LL Exported Macros
+ * @brief DFLASH LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set the DFLASH_DR Register value.
+ * @param __DATA__ specifies the Data value.
+ * @return None
+ */
+#define __LL_DFLASH_DATA_SET(__DATA__) WRITE_REG(DFLASH->DR, (__DATA__))
+
+/**
+ * @brief Get the TMR Counter Register value on runtime.
+ * @return Value in the DFLASH_DR Register
+ */
+#define __LL_DFLASH_DATA_GET() READ_REG(DFLASH->DR)
+
+/**
+ * @brief Check whether the specified status flag in DFLASH_SR Register is SET or not.
+ * @param __FLAG__ specifies the DFLASH status flag to check.
+ * This parameter can be ONE of the following values:
+ * @arg DFLASH_FLAG_BSY : DFLASH BUSY Status
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_DFLASH_STATUS_FLAG_GET(__FLAG__) ((READ_BIT(DFLASH->SR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified interrupt pending flag in DFLASH_ISR Register is SET or not.
+ * @param __FLAG__ specifies the DFLASH interrupt pending flag to check.
+ * This parameter can be ONE of the following values:
+ * @arg DFLASH_FLAG_DIF : Done
+ * @arg DFLASH_FLAG_EIF : Operation Error
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_DFLASH_PENDING_FLAG_GET(__FLAG__) ((READ_BIT(DFLASH->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the DFLASH's Pending Register flag.
+ * @param __FLAG__ specifies the DFLASH pending flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DFLASH_FLAG_DIF : Done
+ * @arg DFLASH_FLAG_EIF : Operation Error
+ * @return None
+ */
+#define __LL_DFLASH_PENDING_FLAG_CLEAR(__FLAG__) WRITE_REG(DFLASH->ISR, (__FLAG__))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DFLASH_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DFLASH_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_DFLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DFLASH_LL_Exported_Functions_Group2
+ * @{
+ */
+
+/**
+ * @brief Unlock the DFLASH Program/Read/Erase access.
+ * @param None
+ * @return LL Status
+ */
+__STATIC_INLINE LL_StatusETypeDef LL_DFLASH_Unlock(void)
+{
+ if (READ_BIT(DFLASH->CR, DFLASH_CR_LOCK) != RESET) {
+ /* Authorize the DFLASH Program/Read/Erase access */
+ WRITE_REG(DFLASH->KEYR, DFLASH_KEY1);
+ WRITE_REG(DFLASH->KEYR, DFLASH_KEY2);
+
+ /* Verify DFLASH is unlocked */
+ if (READ_BIT(DFLASH->CR, DFLASH_CR_LOCK_Msk) != RESET) {
+ return LL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Lock the DFLASH Program/Read/Erase access.
+ * @param None
+ * @return LL Status
+ */
+__STATIC_INLINE LL_StatusETypeDef LL_DFLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the DFLASH Program/Read/Erase access */
+ SET_BIT(DFLASH->CR, DFLASH_CR_LOCK);
+
+ /* Verify DFLASH is locked */
+ if (READ_BIT(DFLASH->CR, DFLASH_CR_LOCK_Msk) == RESET) {
+ return LL_ERROR;
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+LL_StatusETypeDef LL_DFLASH_Program_Byte(uint32_t Address, uint8_t Data);
+LL_StatusETypeDef LL_DFLASH_Program_Word(uint32_t Address, uint32_t Data);
+
+LL_StatusETypeDef LL_DFLASH_Read_Byte(uint32_t Address, uint8_t *Data);
+LL_StatusETypeDef LL_DFLASH_Read_Word(uint32_t Address, uint32_t *Data);
+
+LL_StatusETypeDef LL_DFLASH_MassErase(void);
+LL_StatusETypeDef LL_DFLASH_SectorErase(uint16_t Sector);
+LL_StatusETypeDef LL_DFLASH_MultiSectorsErase(uint16_t Sector, uint16_t Num, uint16_t *SectorError);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DFLASH_LL_Private_Constants DFLASH LL Private Constants
+ * @brief DFLASH LL Private Constants
+ * @{
+ */
+
+#define DFLASH_PROGRAM_ADDRESS_MASK 0x0000FFFFU /*!< Program address mask */
+#define DFLASH_TIMEOUT_MAX_VALUE 300U /*!< Max timeout for data flash operations. Default 300 ticks */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DFLASH_LL_Private_Macros DFLASH LL Private Macros
+ * @brief DFLASH LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is DFLASH address mask or not
+ * @param ADDRESS address to judge
+ * @retval 0 isn't DFLASH address mask
+ * @retval 1 is DFLASH address mask
+ */
+#define IS_DFLASH_ADDRESS_MASK(ADDRESS) ((ADDRESS) < (0x4800U))
+
+/**
+ * @brief Judge is DFLASH address check align or not
+ * @param ADDRESS address to judge
+ * @retval 0 isn't DFLASH address check align
+ * @retval 1 is DFLASH address check align
+ */
+#define IS_DFLASH_ADDRESS_CHECK_ALIGN(ADDRESS) (((ADDRESS) & 0x3) == 0x00U)
+
+/**
+ * @brief Judge is DFLASH sector or not
+ * @param SECTOR sector to judge
+ * @retval 0 isn't DFLASH sector
+ * @retval 1 is DFLASH sector
+ */
+#define IS_DFLASH_NB_SECTORS(SECTOR) ((SECTOR) < 36U)
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_DFLASH_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dma.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dma.h
new file mode 100644
index 0000000000..c99743058d
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_dma.h
@@ -0,0 +1,1193 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file for DMA LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_DMA_H_
+#define _TAE32F53XX_LL_DMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA LL Exported Constants
+ * @brief DMA LL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief DMA block size max
+ */
+#define LL_DMA_BLOCK_SIZE_MAX (0xfffU)
+
+/**
+ * @brief SRAMBC address start
+ */
+#define LL_DMA_SRMBC_ADDR_START (0x20004000UL)
+
+/**
+ * @brief SRAMBC address end
+ */
+#define LL_DMA_SRMBC_ADDR_END (0x20006000UL - 1)
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Types DMA LL Exported Types
+ * @brief DMA LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Source Peripheral bus type definition
+ */
+typedef enum {
+ DMA_SRC_PERIPH_BUS_AHB_MST1 = DMA_CH_CR0_SMS_AHB_MST1, /*!< Source Peripheral bus AHB Master1 */
+ DMA_SRC_PERIPH_BUS_AHB_MST2 = DMA_CH_CR0_SMS_AHB_MST2, /*!< Source Peripheral bus AHB Master2 */
+} DMA_SrcPeriphBusETypeDef;
+
+/**
+ * @brief DMA Destination Peripheral bus type definition
+ */
+typedef enum {
+ DMA_DST_PERIPH_BUS_AHB_MST1 = DMA_CH_CR0_DMS_AHB_MST1, /*!< Destination Peripheral bus AHB Master1 */
+ DMA_DST_PERIPH_BUS_AHB_MST2 = DMA_CH_CR0_DMS_AHB_MST2, /*!< Destination Peripheral bus AHB Master2 */
+} DMA_DstPeriphBusETypeDef;
+
+/**
+ * brief DMA transfer type type definition
+ */
+typedef enum {
+ DMA_TRANS_TYPE_M2M = DMA_CH_CR0_TTC_M2M, /*!< Transfer type M2M */
+ DMA_TRANS_TYPE_M2P = DMA_CH_CR0_TTC_M2P, /*!< Transfer type M2P */
+ DMA_TRANS_TYPE_P2M = DMA_CH_CR0_TTC_P2M, /*!< Transfer type P2M */
+ DMA_TRANS_TYPE_P2P = DMA_CH_CR0_TTC_P2P, /*!< Transfer type P2P */
+} DMA_TransTypeETypeDef;
+
+/**
+ * @brief DMA Source burst length type definition
+ */
+typedef enum {
+ DMA_SRC_BURST_LEN_1 = DMA_CH_CR0_SBTL_1, /*!< Source burst length 1 */
+ DMA_SRC_BURST_LEN_4 = DMA_CH_CR0_SBTL_4, /*!< Source burst length 4 */
+ DMA_SRC_BURST_LEN_8 = DMA_CH_CR0_SBTL_8, /*!< Source burst length 8 */
+} DMA_SrcBurstLenETypeDef;
+
+/**
+ * @brief DMA Destination burst length type definition
+ */
+typedef enum {
+ DMA_DST_BURST_LEN_1 = DMA_CH_CR0_DBTL_1, /*!< Destination burst length 1 */
+ DMA_DST_BURST_LEN_4 = DMA_CH_CR0_DBTL_4, /*!< Destination burst length 4 */
+ DMA_DST_BURST_LEN_8 = DMA_CH_CR0_DBTL_8, /*!< Destination burst length 8 */
+} DMA_DstBurstLenETypeDef;
+
+/**
+ * @brief DMA Source address mode type definition
+ */
+typedef enum {
+ DMA_SRC_ADDR_MODE_INC = DMA_CH_CR0_SINC_INC, /*!< Source address mode Increase */
+ DMA_SRC_ADDR_MODE_DEC = DMA_CH_CR0_SINC_DEC, /*!< Source address mode Decrease */
+ DMA_SRC_ADDR_MODE_FIX = DMA_CH_CR0_SINC_FIX, /*!< Source address mode Fixed */
+} DMA_SrcAddrModeETypeDef;
+
+/**
+ * @brief DMA Destination address mode type definition
+ */
+typedef enum {
+ DMA_DST_ADDR_MODE_INC = DMA_CH_CR0_DINC_INC, /*!< Destination address mode Increase */
+ DMA_DST_ADDR_MODE_DEC = DMA_CH_CR0_DINC_DEC, /*!< Destination address mode Decrease */
+ DMA_DST_ADDR_MODE_FIX = DMA_CH_CR0_DINC_FIX, /*!< Destination address mode Fixed */
+} DMA_DstAddrModeETypeDef;
+
+/**
+ * @brief DMA Source transfer width type definition
+ */
+typedef enum {
+ DMA_SRC_TRANS_WIDTH_8b = DMA_CH_CR0_STW_8b, /*!< Source transfer width 8bit */
+ DMA_SRC_TRANS_WIDTH_16b = DMA_CH_CR0_STW_16b, /*!< Source transfer width 16bit */
+ DMA_SRC_TRANS_WIDTH_32b = DMA_CH_CR0_STW_32b, /*!< Source transfer width 32bit */
+} DMA_SrcTransWidthETypeDef;
+
+/**
+ * @brief DMA Destination transfer width type definition
+ */
+typedef enum {
+ DMA_DST_TRANS_WIDTH_8b = DMA_CH_CR0_DTW_8b, /*!< Destination transfer width 8bit */
+ DMA_DST_TRANS_WIDTH_16b = DMA_CH_CR0_DTW_16b, /*!< Destination transfer width 16bit */
+ DMA_DST_TRANS_WIDTH_32b = DMA_CH_CR0_DTW_32b, /*!< Destination transfer width 32bit */
+} DMA_DstTransWidthETypeDef;
+
+/**
+ * @brief DMA Source handshaking interface type definition
+ */
+typedef enum {
+ DMA_SRC_HANDSHAKE_IFC_MEMORY = 0, /*!< Source handshaking interface MEMORY */
+ DMA_SRC_HANDSHAKE_IFC_I2C0_TX = DMA_CH_CR3_SHSIF_I2C0_TX, /*!< Source handshaking interface I2C0_TX */
+ DMA_SRC_HANDSHAKE_IFC_I2C0_RX = DMA_CH_CR3_SHSIF_I2C0_RX, /*!< Source handshaking interface I2C0_RX */
+ DMA_SRC_HANDSHAKE_IFC_I2C1_TX = DMA_CH_CR3_SHSIF_I2C1_TX, /*!< Source handshaking interface I2C1_TX */
+ DMA_SRC_HANDSHAKE_IFC_I2C1_RX = DMA_CH_CR3_SHSIF_I2C1_RX, /*!< Source handshaking interface I2C1_RX */
+ DMA_SRC_HANDSHAKE_IFC_UART0_TX = DMA_CH_CR3_SHSIF_UART0_TX, /*!< Source handshaking interface UART0_TX */
+ DMA_SRC_HANDSHAKE_IFC_UART0_RX = DMA_CH_CR3_SHSIF_UART0_RX, /*!< Source handshaking interface UART0_RX */
+ DMA_SRC_HANDSHAKE_IFC_UART1_TX = DMA_CH_CR3_SHSIF_UART1_TX, /*!< Source handshaking interface UART1_TX */
+ DMA_SRC_HANDSHAKE_IFC_UART1_RX = DMA_CH_CR3_SHSIF_UART1_RX, /*!< Source handshaking interface UART1_RX */
+} DMA_SrcHandshakeIfcETypeDef;
+
+/**
+ * @brief DMA Destination handshaking interface type definition
+ */
+typedef enum {
+ DMA_DST_HANDSHAKE_IFC_MEMORY = 0, /*!< Destination handshaking interface MEMORY */
+ DMA_DST_HANDSHAKE_IFC_I2C0_TX = DMA_CH_CR3_DHSIF_I2C0_TX, /*!< Destination handshaking interface I2C0_TX */
+ DMA_DST_HANDSHAKE_IFC_I2C0_RX = DMA_CH_CR3_DHSIF_I2C0_RX, /*!< Destination handshaking interface I2C0_RX */
+ DMA_DST_HANDSHAKE_IFC_I2C1_TX = DMA_CH_CR3_DHSIF_I2C1_TX, /*!< Destination handshaking interface I2C1_TX */
+ DMA_DST_HANDSHAKE_IFC_I2C1_RX = DMA_CH_CR3_DHSIF_I2C1_RX, /*!< Destination handshaking interface I2C1_RX */
+ DMA_DST_HANDSHAKE_IFC_UART0_TX = DMA_CH_CR3_DHSIF_UART0_TX, /*!< Destination handshaking interface UART0_TX */
+ DMA_DST_HANDSHAKE_IFC_UART0_RX = DMA_CH_CR3_DHSIF_UART0_RX, /*!< Destination handshaking interface UART0_RX */
+ DMA_DST_HANDSHAKE_IFC_UART1_TX = DMA_CH_CR3_DHSIF_UART1_TX, /*!< Destination handshaking interface UART1_TX */
+ DMA_DST_HANDSHAKE_IFC_UART1_RX = DMA_CH_CR3_DHSIF_UART1_RX, /*!< Destination handshaking interface UART1_RX */
+} DMA_DstHandshakeIfcETypeDef;
+
+/**
+ * @brief DMA channel type definition
+ */
+typedef enum {
+ DMA_CHANNEL_0 = 0U, /*!< DMA Channel 0 */
+ DMA_CHANNEL_1 = 1U, /*!< DMA Channel 1 */
+ DMA_CHANNEL_NUM = 2U, /*!< DMA Channel Number */
+ DMA_CHANNEL_INVALID = 0xFFU, /*!< DMA Channel Invalid */
+} DMA_ChannelETypeDef;
+
+/**
+ * @brief DMA State type definition
+ */
+typedef enum {
+ DMA_STATE_RESET = 0, /*!< DMA State Reset: not yet initialized or disabled */
+ DMA_STATE_READY, /*!< DMA State Ready: initialized and ready for use */
+ DMA_STATE_BUSY, /*!< DMA State Busy: process is ongoing */
+} DMA_StateETypeDef;
+
+
+/**
+ * @brief DMA IRQ callback function type definition
+ */
+typedef void (*DMA_IRQCallback)(void *arg);
+
+
+/**
+ * @brief DMA user config type definition
+ */
+typedef struct __DMA_UserCfgTypeDef {
+ DMA_TransTypeETypeDef trans_type; /*!< transfer type */
+ DMA_SrcAddrModeETypeDef src_addr_mode; /*!< source address mode */
+ DMA_DstAddrModeETypeDef dst_addr_mode; /*!< destination address mode */
+ DMA_SrcTransWidthETypeDef src_data_width; /*!< source data width */
+ DMA_DstTransWidthETypeDef dst_data_width; /*!< destination data width */
+ DMA_SrcHandshakeIfcETypeDef src_hs_ifc; /*!< source handshake interface */
+ DMA_DstHandshakeIfcETypeDef dst_hs_ifc; /*!< destination handshake interface */
+
+ void *end_arg; /*!< argument of transfer complete callback fucntion */
+ DMA_IRQCallback end_callback; /*!< transfer complete callback fucntion */
+ void *err_arg; /*!< argument of transfer error callback fucntion */
+ DMA_IRQCallback err_callback; /*!< transfer error callback fucntion */
+} DMA_UserCfgTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA LL Exported Macros
+ * @brief DMA LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Source address set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param addr Source address
+ * @return None
+ */
+#define __LL_DMA_SrcAddr_Set(__DMA__, ch, addr) WRITE_REG((__DMA__)->CH[(ch)].SAR, addr)
+
+
+/**
+ * @brief Destination address set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param addr Destination address
+ * @return None
+ */
+#define __LL_DMA_DstAddr_Set(__DMA__, ch, addr) WRITE_REG((__DMA__)->CH[(ch)].DAR, addr)
+
+
+/**
+ * @brief Source peripheral bus set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param bus Source peripheral bus
+ * @return None
+ */
+#define __LL_DMA_SrcPeriphBus_Set(__DMA__, ch, bus) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_SMS_Msk, bus)
+
+/**
+ * @brief Destination peripheral bus set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param bus Destination peripheral bus
+ * @return None
+ */
+#define __LL_DMA_DstPeriphBus_Set(__DMA__, ch, bus) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DMS_Msk, bus)
+
+/**
+ * @brief Transfer type set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param type Transfer type
+ * @return None
+ */
+#define __LL_DMA_TransType_Set(__DMA__, ch, type) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_TTC_Msk, type)
+
+/**
+ * @brief Source burst length set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param len Source burst length
+ * @return None
+ */
+#define __LL_DMA_SrcBurstLen_Set(__DMA__, ch, len) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_SBTL_Msk, len)
+
+/**
+ * @brief Destination burst length set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param len Destination burst length
+ * @return None
+ */
+#define __LL_DMA_DstBurstLen_Set(__DMA__, ch, len) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DBTL_Msk, len)
+
+/**
+ * @brief Source address mode set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param mode Source address mode
+ * @return None
+ */
+#define __LL_DMA_SrcAddrMode_Set(__DMA__, ch, mode) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_SINC_Msk, mode)
+
+/**
+ * @brief Destination address mode set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param mode Destination address mode
+ * @return None
+ */
+#define __LL_DMA_DstAddrMode_Set(__DMA__, ch, mode) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DINC_Msk, mode)
+
+/**
+ * @brief Source transfer width set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param width Source transfer width
+ * @return None
+ */
+#define __LL_DMA_SrcTransWidth_Set(__DMA__, ch, width) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_STW_Msk, width)
+
+/**
+ * @brief Source transfer width get
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @retval 0 8 bits
+ * @retval 1 16 bits
+ * @retval 2 32 bits
+ */
+#define __LL_DMA_SrcTransWidth_Get(__DMA__, ch) (READ_BIT((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_STW_Msk) >> DMA_CH_CR0_STW_Pos)
+
+/**
+ * @brief Destination transfer width set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param width Destination transfer width
+ * @return None
+ */
+#define __LL_DMA_DstTransWidth_Set(__DMA__, ch, width) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DTW_Msk, width)
+
+/**
+ * @brief Channel interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_Channel_Int_En(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_CHIE_Msk)
+
+/**
+ * @brief Channel interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_Channel_Int_Dis(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_CHIE_Msk)
+
+/**
+ * @brief Channel register CR0 write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_ChannelRegCR0_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR0, val)
+
+
+/**
+ * @brief Judge is block transfer done or not
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @retval 0 isn't block transfer done
+ * @retval 1 is block transfer done
+ */
+#define __LL_DMA_IsBlockTransDone(__DMA__, ch) (READ_BIT((__DMA__)->CH[(ch)].CR1, DMA_CH_CR1_DONE_Msk) >> DMA_CH_CR1_DONE_Pos)
+
+/**
+ * @brief Block transfer done clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_BlockTransDone_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR1, DMA_CH_CR1_DONE_Msk)
+
+/**
+ * @brief Block transfer count set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param cnt Block transfer count
+ * @return None
+ */
+#define __LL_DMA_BlockTransCnt_Set(__DMA__, ch, cnt) \
+ MODIFY_REG((__DMA__)->CH[(ch)].CR1, DMA_CH_CR1_BTCNT_Msk, (((cnt) & 0xfffUL) << DMA_CH_CR1_BTCNT_Pos))
+
+/**
+ * @brief Channel register CR1 write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param val write value
+ * @return None
+ */
+#define __LL_DAM_ChannelRegCR1_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR1, val)
+
+
+/**
+ * @brief Burst length max set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param max Burst length max
+ * @return None
+ */
+#define __LL_DMA_BurstLenMax_Set(__DMA__, ch, max) \
+ MODIFY_REG((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_MBL_Msk, (((max) & 0x3ffUL) << DMA_CH_CR2_MBL_Pos))
+
+/**
+ * @brief Source handshake mode set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_SrcHandshakeMode_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SHSM_Msk)
+
+/**
+ * @brief Source handshake mode clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_SrcHandshakeMode_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SHSM_Msk)
+
+/**
+ * @brief Destination handshake mode set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_DstHandshakeMode_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_DHSM_Msk)
+
+/**
+ * @brief Destination handshake mode clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_DstHandshakeMode_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_DHSM_Msk)
+
+/**
+ * @brief Judge is channel FIFO empty or not
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @retval 0 isn't channel FIFO empty
+ * @retval 1 is channel FIFO empty
+ */
+#define __LL_DMA_IsChannelFIFOEmpty(__DMA__, ch) \
+ (READ_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_FIFO_EF_Msk) >> DMA_CH_CR2_FIFO_EF_Pos)
+
+/**
+ * @brief Channel suspend set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_ChannelSuspend_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SUSP_Msk)
+
+/**
+ * @brief Channel suspend clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_ChannelSuspend_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SUSP_Msk)
+
+/**
+ * @brief Channel priority set high
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_ChannelPriHigh_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_PRI_Msk)
+
+/**
+ * @brief Channel priority set low
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_ChannelPriLow_Set(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_PRI_Msk)
+
+/**
+ * @brief Channel register CR2 write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param val write value
+ * @return None
+ */
+#define __LL_DAM_ChannelRegCR2_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR2, val)
+
+
+/**
+ * @brief Destination handshake interface set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param ifc Destination handshake interface
+ * @return None
+ */
+#define __LL_DMA_DstHandshakeIfc_Set(__DMA__, ch, ifc) MODIFY_REG((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_DHSIF_Msk, ifc)
+
+/**
+ * @brief Source handshake interface set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param ifc Source handshake interface
+ * @return None
+ */
+#define __LL_DMA_SrcHandshakeIfc_Set(__DMA__, ch, ifc) MODIFY_REG((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_SHSIF_Msk, ifc)
+
+/**
+ * @brief FIFO mode half set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_FIFOModeHalf_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FMD_Msk)
+
+/**
+ * @brief FIFO mode once set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_FIFOModeOnce_Set(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FMD_Msk)
+
+/**
+ * @brief Channel folw control mode source request set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_ChFlowModeSrcReq_Set(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FCMD_Msk)
+
+/**
+ * @brief Channel folw control mode destination request set
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @return None
+ */
+#define __LL_DMA_ChFlowModeDstReq_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FCMD_Msk)
+
+/**
+ * @brief Channel register CR3 write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param ch DMA channel
+ * @param val write value
+ * @return None
+ */
+#define __LL_DAM_ChannelRegCR3_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR3, val)
+
+
+/**
+ * @brief Channel 1 transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 1 transfer hasn't completed
+ * @retval 1 Channel 1 transfer has completed
+ */
+#define __LL_DMA_Ch1TransComSta_Get(__DMA__) (READ_BIT((__DMA__)->TSR, DMA_TSR_TS_CH1_Msk) >> DMA_TSR_TS_CH1_Pos)
+
+/**
+ * @brief Channel 0 transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 0 transfer hasn't completed
+ * @retval 1 Channel 0 transfer has completed
+ */
+#define __LL_DMA_Ch0TransComSta_Get(__DMA__) (READ_BIT((__DMA__)->TSR, DMA_TSR_TS_CH0_Msk) >> DMA_TSR_TS_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 block transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 1 block transfer hasn't completed
+ * @retval 1 Channel 1 block transfer has completed
+ */
+#define __LL_DMA_Ch1BlockTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->BTSR, DMA_BTSR_BTS_CH1_Msk) >> DMA_BTSR_BTS_CH1_Pos)
+
+/**
+ * @brief Channel 0 block transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 0 block transfer hasn't completed
+ * @retval 1 Channel 0 block transfer has completed
+ */
+#define __LL_DMA_Ch0BlockTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->BTSR, DMA_BTSR_BTS_CH0_Msk) >> DMA_BTSR_BTS_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 source transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 1 source transfer hasn't completed
+ * @retval 1 Channel 1 source transfer has completed
+ */
+#define __LL_DMA_Ch1SrcTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->STSR, DMA_STSR_STS_CH1_Msk) >> DMA_STSR_STS_CH1_Pos)
+
+/**
+ * @brief Channel 0 source transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 0 source transfer hasn't completed
+ * @retval 1 Channel 0 source transfer has completed
+ */
+#define __LL_DMA_Ch0SrcTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->STSR, DMA_STSR_STS_CH0_Msk) >> DMA_STSR_STS_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 destination transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 1 destination transfer hasn't completed
+ * @retval 1 Channel 1 destination transfer has completed
+ */
+#define __LL_DMA_Ch1DstTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->DTSR, DMA_DTSR_DTS_CH1_Msk) >> DMA_DTSR_DTS_CH1_Pos)
+
+/**
+ * @brief Channel 0 destination transfer complete status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 0 destination transfer hasn't completed
+ * @retval 1 Channel 0 destination transfer has completed
+ */
+#define __LL_DMA_Ch0DstTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->DTSR, DMA_DTSR_DTS_CH0_Msk) >> DMA_DTSR_DTS_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 transfer error status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 1 transfer normal
+ * @retval 1 Channel 1 transfer error
+ */
+#define __LL_DMA_Ch1TransErrSta_Get(__DMA__) (READ_BIT((__DMA__)->TESR, DMA_TESR_TES_CH1_Msk) >> DMA_TESR_TES_CH1_Pos)
+
+/**
+ * @brief Channel 0 transfer error status get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 Channel 0 transfer normal
+ * @retval 1 Channel 0 transfer error
+ */
+#define __LL_DMA_Ch0TransErrSta_Get(__DMA__) (READ_BIT((__DMA__)->TESR, DMA_TESR_TES_CH0_Msk) >> DMA_TESR_TES_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch1TransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TIPR, DMA_TIPR_TIP_CH1_Msk) >> DMA_TIPR_TIP_CH1_Pos)
+
+/**
+ * @brief Channel 0 transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch0TransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TIPR, DMA_TIPR_TIP_CH0_Msk) >> DMA_TIPR_TIP_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 block transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch1BlockTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->BTIPR, DMA_BTIPR_BTIF_CH1_Msk) >> DMA_BTIPR_BTIF_CH1_Pos)
+
+/**
+ * @brief Channel 0 block transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch0BlockTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->BTIPR, DMA_BTIPR_BTIF_CH0_Msk) >> DMA_BTIPR_BTIF_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 source transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch1SrcTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->STIPR, DMA_STIPR_STIF_CH1_Msk) >> DMA_STIPR_STIF_CH1_Pos)
+
+/**
+ * @brief Channel 0 source transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch0SrcTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->STIPR, DMA_STIPR_STIF_CH0_Msk) >> DMA_STIPR_STIF_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 destination transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch1DstTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->DTIPR, DMA_DTIPR_DTIF_CH1_Msk) >> DMA_DTIPR_DTIF_CH1_Pos)
+
+/**
+ * @brief Channel 0 destination transfer complete interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch0DstTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->DTIPR, DMA_DTIPR_DTIF_CH0_Msk) >> DMA_DTIPR_DTIF_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 transfer error interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch1TransErrIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TEIPR, DMA_TEIPR_TEIF_CH1_Msk) >> DMA_TEIPR_TEIF_CH1_Pos)
+
+/**
+ * @brief Channel 0 transfer error interrupt pending get
+ * @param __DMA__ Specifies DMA peripheral
+ * @retval 0 no pending
+ * @retval 1 pending
+ */
+#define __LL_DMA_Ch0TransErrIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TEIPR, DMA_TEIPR_TEIF_CH0_Msk) >> DMA_TEIPR_TEIF_CH0_Pos)
+
+
+/**
+ * @brief Channel 1 transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1TransCom_Int_En(__DMA__) SET_BIT((__DMA__)->TIMR, DMA_TIMR_TIWE_CH1_Msk | DMA_TIMR_TIE_CH1_Msk)
+
+/**
+ * @brief Channel 1 transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1TransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->TIMR, DMA_TIMR_TIWE_CH1_Msk | DMA_TIMR_TIE_CH1_Msk, DMA_TIMR_TIWE_CH1_Msk | (0x0 << DMA_TIMR_TIE_CH1_Pos))
+
+/**
+ * @brief Channel 0 transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0TransCom_Int_En(__DMA__) SET_BIT((__DMA__)->TIMR, DMA_TIMR_TIWE_CH0_Msk | DMA_TIMR_TIE_CH0_Msk)
+
+/**
+ * @brief Channel 0 transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0TransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->TIMR, DMA_TIMR_TIWE_CH0_Msk | DMA_TIMR_TIE_CH0_Msk, DMA_TIMR_TIWE_CH0_Msk | (0x0 << DMA_TIMR_TIE_CH0_Pos))
+
+/**
+ * @brief Reg TIMR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->TIMR, val)
+
+
+/**
+ * @brief Channel 1 block transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1BlockTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH1_Msk | DMA_BTIMR_BTIE_CH1_Msk)
+
+/**
+ * @brief Channel 1 block transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1BlockTransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH1_Msk | DMA_BTIMR_BTIE_CH1_Msk, DMA_BTIMR_BTIWE_CH1_Msk | (0x0 << DMA_BTIMR_BTIE_CH1_Pos))
+
+/**
+ * @brief Channel 0 block transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0BlockTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH0_Msk | DMA_BTIMR_BTIE_CH0_Msk)
+
+/**
+ * @brief Channel 0 block transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0BlockTransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH0_Msk | DMA_BTIMR_BTIE_CH0_Msk, DMA_BTIMR_BTIWE_CH0_Msk | (0x0 << DMA_BTIMR_BTIE_CH0_Pos))
+
+/**
+ * @brief Reg BTIMR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegBTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->BTIMR, val)
+
+
+/**
+ * @brief Channel 1 source transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1SrcTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->STIMR, DMA_STIMR_STIWE_CH1_Msk | DMA_STIMR_STIE_CH1_Msk)
+
+/**
+ * @brief Channel 1 source transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1SrcTransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->STIMR, DMA_STIMR_STIWE_CH1_Msk | DMA_STIMR_STIE_CH1_Msk, DMA_STIMR_STIWE_CH1_Msk | (0x0 << DMA_STIMR_STIE_CH1_Pos))
+
+/**
+ * @brief Channel 0 source transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0SrcTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->STIMR, DMA_STIMR_STIWE_CH0_Msk | DMA_STIMR_STIE_CH0_Msk)
+
+/**
+ * @brief Channel 0 source transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0SrcTransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->STIMR, DMA_STIMR_STIWE_CH0_Msk | DMA_STIMR_STIE_CH0_Msk, DMA_STIMR_STIWE_CH0_Msk | (0x0 << DMA_STIMR_STIE_CH0_Pos))
+
+/**
+ * @brief Reg STIMR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegSTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->STIMR, val)
+
+
+/**
+ * @brief Channel 1 destination transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1DstTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH1_Msk | DMA_DTIMR_DTIE_CH1_Msk)
+
+/**
+ * @brief Channel 1 destination transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1DstTransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH1_Msk | DMA_DTIMR_DTIE_CH1_Msk, DMA_DTIMR_DTIWE_CH1_Msk | (0x0 << DMA_DTIMR_DTIE_CH1_Pos))
+
+/**
+ * @brief Channel 0 destination transfer complete interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0DstTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH0_Msk | DMA_DTIMR_DTIE_CH0_Msk)
+
+/**
+ * @brief Channel 0 destination transfer complete interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0DstTransCom_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH0_Msk | DMA_DTIMR_DTIE_CH0_Msk, DMA_DTIMR_DTIWE_CH0_Msk | (0x0 << DMA_DTIMR_DTIE_CH0_Pos))
+
+/**
+ * @brief Reg DTIMR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegDTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->DTIMR, val)
+
+
+/**
+ * @brief Channel 1 transfer error interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1TransErr_Int_En(__DMA__) SET_BIT((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH1_Msk | DMA_TEIMR_TEIE_CH1_Msk)
+
+/**
+ * @brief Channel 1 transfer error interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1TransErr_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH1_Msk | DMA_TEIMR_TEIE_CH1_Msk, DMA_TEIMR_TEIWE_CH1_Msk | (0x0 << DMA_TEIMR_TEIE_CH1_Pos))
+
+/**
+ * @brief Channel 0 transfer error interrupt enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0TransErr_Int_En(__DMA__) SET_BIT((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH0_Msk | DMA_TEIMR_TEIE_CH0_Msk)
+
+/**
+ * @brief Channel 0 transfer error interrupt disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0TransErr_Int_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH0_Msk | DMA_TEIMR_TEIE_CH0_Msk, DMA_TEIMR_TEIWE_CH0_Msk | (0x0 << DMA_TEIMR_TEIE_CH0_Pos))
+
+/**
+ * @brief Reg TEIMR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegTEIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->TEIMR, val)
+
+
+/**
+ * @brief Channel 1 transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1TransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->TCR, DMA_TCR_TC_CH1_Msk)
+
+/**
+ * @brief Channel 0 transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0TransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->TCR, DMA_TCR_TC_CH0_Msk)
+
+/**
+ * @brief Reg TCR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->TCR, val)
+
+
+/**
+ * @brief Channel 1 block transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1BlockTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->BTCR, DMA_BTCR_BTC_CH1_Msk)
+
+/**
+ * @brief Channel 0 block transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0BlockTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->BTCR, DMA_BTCR_BTC_CH0_Msk)
+
+/**
+ * @brief Reg BTCR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegBTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->BTCR, val)
+
+
+/**
+ * @brief Channel 1 source transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1SrcTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->STCR, DMA_STCR_STC_CH1_Msk)
+
+/**
+ * @brief Channel 0 source transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0SrcTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->STCR, DMA_STCR_STC_CH0_Msk)
+
+/**
+ * @brief Reg STCR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegSTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->STCR, val)
+
+
+/**
+ * @brief Channel 1 destination transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1DstTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->DTCR, DMA_DTCR_DTC_CH1_Msk)
+
+/**
+ * @brief Channel 0 destination transfer complete status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0DstTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->DTCR, DMA_DTCR_DTC_CH0_Msk)
+
+/**
+ * @brief Reg DTCR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegDTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->DTCR, val)
+
+
+/**
+ * @brief Channel 1 transfer error status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1TransErrSta_Clr(__DMA__) WRITE_REG((__DMA__)->TECR, DMA_TECR_TEC_CH1_Msk)
+
+/**
+ * @brief Channel 0 transfer error status clear
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0TransErrSta_Clr(__DMA__) WRITE_REG((__DMA__)->TECR, DMA_TECR_TEC_CH0_Msk)
+
+/**
+ * @brief Reg TECR Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegTECR_Write(__DMA__, val) WRITE_REG((__DMA__)->TECR, val)
+
+
+/**
+ * @brief Peripheral enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Periph_En(__DMA__) SET_BIT((__DMA__)->CR0, DMA_CR0_PEN_Msk)
+
+/**
+ * @brief Peripheral disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Periph_Dis(__DMA__) CLEAR_BIT((__DMA__)->CR0, DMA_CR0_PEN_Msk)
+
+/**
+ * @brief Reg CR0 Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegCR0_Write(__DMA__, val) WRITE_REG((__DMA__)->CR0, val)
+
+
+/**
+ * @brief Channel 1 enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1_En(__DMA__) SET_BIT((__DMA__)->CR1, DMA_CR1_CHWE_CH1_Msk | DMA_CR1_CHEN_CH1_Msk)
+
+/**
+ * @brief Channel 1 disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch1_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->CR1, DMA_CR1_CHWE_CH1_Msk | DMA_CR1_CHEN_CH1_Msk, DMA_CR1_CHWE_CH1_Msk | (0x0 << DMA_CR1_CHEN_CH1_Pos))
+
+/**
+ * @brief Channel 0 enable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0_En(__DMA__) SET_BIT((__DMA__)->CR1, DMA_CR1_CHWE_CH0_Msk | DMA_CR1_CHEN_CH0_Msk)
+
+/**
+ * @brief Channel 0 disable
+ * @param __DMA__ Specifies DMA peripheral
+ * @return None
+ */
+#define __LL_DMA_Ch0_Dis(__DMA__) \
+ MODIFY_REG((__DMA__)->CR1, DMA_CR1_CHWE_CH0_Msk | DMA_CR1_CHEN_CH0_Msk, DMA_CR1_CHWE_CH0_Msk | (0x0 << DMA_CR1_CHEN_CH0_Pos))
+
+/**
+ * @brief Reg CR1 Write
+ * @param __DMA__ Specifies DMA peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_DMA_RegCR1_Write(__DMA__, val) WRITE_REG((__DMA__)->CR1, val)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_DMA_Init(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, DMA_UserCfgTypeDef *user_cfg);
+LL_StatusETypeDef LL_DMA_DeInit(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DMA_LL_Exported_Functions_Group2
+ * @{
+ */
+DMA_ChannelETypeDef LL_DMA_ChannelRequest(void);
+DMA_ChannelETypeDef LL_DMA_ChReqSpecific(DMA_ChannelETypeDef ch);
+void LL_DMA_ChannelRelease(DMA_ChannelETypeDef ch);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DMA_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_DMA_Start_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch,
+ uint32_t src_addr, uint32_t dst_addr, uint32_t data_len);
+LL_StatusETypeDef LL_DMA_Start_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch,
+ uint32_t src_addr, uint32_t dst_addr, uint32_t data_len);
+LL_StatusETypeDef LL_DMA_Stop_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch);
+LL_StatusETypeDef LL_DMA_Stop_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch);
+LL_StatusETypeDef LL_DMA_WaitComplete_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, uint32_t timeout);
+/**
+ * @}
+ */
+
+
+/** @addtogroup DMA_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_DMA_IRQHandler(DMA_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_DMA_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_ecu.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_ecu.h
new file mode 100644
index 0000000000..71279e206a
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_ecu.h
@@ -0,0 +1,726 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_ecu.h
+ * @author MCD Application Team
+ * @brief Header file of ECU LL module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_ECU_H_
+#define _TAE32F53XX_LL_ECU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup ECU_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ECU_LL_Exported_Constants ECU LL Exported Constants
+ * @brief ECU LL Exported Constants
+ * @{
+ */
+
+/** @defgroup LL_ECU_ENABLE ECU enable define
+ * @brief ECU Enable Bit Set and Bit Reset
+ * @{
+ */
+#define ECU_DISABLE (0x00000000U) /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC0_DTFLAG0 = 0x0,
+ /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC0_DTFLAG1 = ECU_PRC_DATSEL_0,
+ /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC0_DTFLAG2 = ECU_PRC_DATSEL_1,
+ /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC0_DTFLAG3 = ECU_PRC_DATSEL_1 | ECU_PRC_DATSEL_0,
+ /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC1_DTFLAG0 = ECU_PRC_DATSEL_2,
+ /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC1_DTFLAG1 = ECU_PRC_DATSEL_2 | ECU_PRC_DATSEL_0,
+ /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC1_DTFLAG2 = ECU_PRC_DATSEL_2 | ECU_PRC_DATSEL_1,
+ /*!ADDR_DATA_FLAG */
+ ECU_PSR_DATSEL_ADC1_DTFLAG3 = ECU_PRC_DATSEL_2 | ECU_PRC_DATSEL_1 | ECU_PRC_DATSEL_0,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC0_ADFLAG0 = 0x0,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC0_ADFLAG1 = ECU_PRC_ADRSEL_0,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC0_ADFLAG2 = ECU_PRC_ADRSEL_1,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC0_ADFLAG3 = ECU_PRC_ADRSEL_1 | ECU_PRC_ADRSEL_0,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC1_ADFLAG0 = ECU_PRC_ADRSEL_2,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC1_ADFLAG1 = ECU_PRC_ADRSEL_2 | ECU_PRC_ADRSEL_0,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC1_ADFLAG2 = ECU_PRC_ADRSEL_2 | ECU_PRC_ADRSEL_1,
+ /*!ADDR_DATA_FLAG*/
+ ECU_PSR_ADRSEL_ADC1_ADFLAG3 = ECU_PRC_ADRSEL_2 | ECU_PRC_ADRSEL_1 | ECU_PRC_ADRSEL_0,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC0_PPFLAG0 = 0x0,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC0_PPFLAG1 = ECU_PRC_CRSSEL_0,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC0_PPFLAG2 = ECU_PRC_CRSSEL_1,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC0_PPFLAG3 = ECU_PRC_CRSSEL_1 | ECU_PRC_CRSSEL_0,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC1_PPFLAG0 = ECU_PRC_CRSSEL_2,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC1_PPFLAG1 = ECU_PRC_CRSSEL_2 | ECU_PRC_CRSSEL_0,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC1_PPFLAG2 = ECU_PRC_CRSSEL_2 | ECU_PRC_CRSSEL_1,
+ /*!PSRCU/PSRCD */
+ ECU_PSR_CRSSEL_ADC1_PPFLAG3 = ECU_PRC_CRSSEL_2 | ECU_PRC_CRSSEL_1 | ECU_PRC_CRSSEL_0,
+ /*!CON, ECU_CON_ENABLE)
+
+/**
+ * @brief Disable the ECU module.
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return None
+ */
+#define __LL_ECU_MODULE_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CON, ECU_CON_ENABLE)
+
+/**
+ * @brief Get the ECU module states.
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return ENABLE : the module is enable
+ * DISABLE : the module is disable
+ */
+#define __LL_ECU_GET_STA(__INSTANCE__) ((((__INSTANCE__)->CON & (ECU_CON_ENABLE)) == 0x1UL) ? ENABLE : DISABLE)
+
+/**
+ * @brief Enable the specified ECU Calculate complete interrupt.
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return None
+ */
+#define __LL_ECU_DONE_IT_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CON, ECU_CON_INTEN)
+
+/**
+ * @brief Disable the specified ECU Calculate complete interrupt.
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return None
+ */
+#define __LL_ECU_DONE_IT_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CON, ECU_CON_INTEN)
+
+/**
+ * @brief Check the ECU Calculate complete interrupts are enabled or disable.
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return SET : the interrupt is enable
+ * RESET : the interrupt is disable
+ */
+#define __LL_ECU_DONE_GET_IT(__INSTANCE__) ((((__INSTANCE__)->CON & (ECU_CON_INTEN)) == 0x02UL) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified ECU Calculate complete pending flag is set or not.
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return SET : the interrupt flag is set
+ * RESET : the interrupt flag is reset
+ */
+#define __LL_ECU_DONE_GET_FLAG(__INSTANCE__) ((((__INSTANCE__)->CON & (ECU_CON_INT)) == 0x8000UL) ? SET : RESET)
+
+/**
+ * @brief Clear the specified ECU Calculate complete pending flags.
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return None
+ */
+#define __LL_ECU_DONE_CLEAR_FLAG(__INSTANCE__) SET_BIT((__INSTANCE__)->CON, ECU_CON_INT)
+
+/**
+ * @brief Input data square enable, after the completion of the calculation automatically reset
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return None
+ */
+#define __LL_ECU_SQRT_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CON, ECU_CON_SQRT)
+
+/**
+ * @brief Gets the square root completion flag
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return RESET That means the square root is complete
+ * SET That means the square root is not complete
+ */
+#define __LL_ECU_SQRT_DONE_FLAG(__INSTANCE__) ((((__INSTANCE__)->CON & (ECU_CON_SQRT)) == 0x4000UL) ? SET : RESET)
+
+/**
+ * @brief Sets the zero crossing event that needs to be selected
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @param __EVENT__ cross zero event as follow:
+ * @arg @ref ECU_PSR_CRSSEL_ADC0_PPFLAF0
+ * @arg @ref ECU_PSR_CRSSEL_ADC0_PPFLAG1
+ * @arg @ref ECU_PSR_CRSSEL_ADC0_PPFLAG2
+ * @arg @ref ECU_PSR_CRSSEL_ADC0_PPFLAG3
+ * @arg @ref ECU_PSR_CRSSEL_ADC1_PPFLAG0
+ * @arg @ref ECU_PSR_CRSSEL_ADC1_PPFLAG1
+ * @arg @ref ECU_PSR_CRSSEL_ADC1_PPFLAG2
+ * @arg @ref ECU_PSR_CRSSEL_ADC1_PPFLAG3
+ * @arg @ref ECU_PSR_CRSSEL_TIM0_OC
+ * @arg @ref ECU_PSR_CRSSEL_TIM1_OC
+ * @arg @ref ECU_PSR_CRSSEL_TIM2_OC
+ * @arg @ref ECU_PSR_CRSSEL_TIM3_OC
+ * @arg @ref ECU_PSR_CRSSEL_TIM4_OC
+ * @arg @ref ECU_PSR_CRSSEL_TIM5_OC
+ * @arg @ref ECU_PSR_CRSSEL_TIM6_OC
+ * @arg @ref ECU_PSR_CRSSEL_TIM7_OC
+ * @return None
+ */
+#define __LL_ECU_CROSS_ZERO_EVENT(__INSTANCE__, __EVENT__) MODIFY_REG((__INSTANCE__)->PRC, ECU_PRC_CRSSEL, __EVENT__)
+
+/**
+ * @brief Sets the data event that needs to be selected
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @param __EVENT__ cross zero event as follow:
+ * @arg @ref ECU_PSR_DATSEL_ADC0_PPFLAF0
+ * @arg @ref ECU_PSR_DATSEL_ADC0_PPFLAG1
+ * @arg @ref ECU_PSR_DATSEL_ADC0_PPFLAG2
+ * @arg @ref ECU_PSR_DATSEL_ADC0_PPFLAG3
+ * @arg @ref ECU_PSR_DATSEL_ADC1_PPFLAG0
+ * @arg @ref ECU_PSR_DATSEL_ADC1_PPFLAG1
+ * @arg @ref ECU_PSR_DATSEL_ADC1_PPFLAG2
+ * @arg @ref ECU_PSR_DATSEL_ADC1_PPFLAG3
+ * @arg @ref ECU_PSR_DATSEL_TIM0_OC
+ * @arg @ref ECU_PSR_DATSEL_TIM1_OC
+ * @arg @ref ECU_PSR_DATSEL_TIM2_OC
+ * @arg @ref ECU_PSR_DATSEL_TIM3_OC
+ * @arg @ref ECU_PSR_DATSEL_TIM4_OC
+ * @arg @ref ECU_PSR_DATSEL_TIM5_OC
+ * @arg @ref ECU_PSR_DATSEL_TIM6_OC
+ * @arg @ref ECU_PSR_DATSEL_TIM7_OC
+ * @return None
+ */
+#define __LL_ECU_DATA_FLAG_EVENT(__INSTANCE__, __EVENT__) MODIFY_REG((__INSTANCE__)->PRC, ECU_PRC_DATSEL, __EVENT__)
+
+
+/**
+ * @brief Sets the addr_data flag event that needs to be selected
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @param __EVENT__ cross zero event as follow:
+ * @arg @ref ECU_PSR_ADRSEL_ADC0_PPFLAF0
+ * @arg @ref ECU_PSR_ADRSEL_ADC0_PPFLAG1
+ * @arg @ref ECU_PSR_ADRSEL_ADC0_PPFLAG2
+ * @arg @ref ECU_PSR_ADRSEL_ADC0_PPFLAG3
+ * @arg @ref ECU_PSR_ADRSEL_ADC1_PPFLAG0
+ * @arg @ref ECU_PSR_ADRSEL_ADC1_PPFLAG1
+ * @arg @ref ECU_PSR_ADRSEL_ADC1_PPFLAG2
+ * @arg @ref ECU_PSR_ADRSEL_ADC1_PPFLAG3
+ * @arg @ref ECU_PSR_ADRSEL_TIM0_OC
+ * @arg @ref ECU_PSR_ADRSEL_TIM1_OC
+ * @arg @ref ECU_PSR_ADRSEL_TIM2_OC
+ * @arg @ref ECU_PSR_ADRSEL_TIM3_OC
+ * @arg @ref ECU_PSR_ADRSEL_TIM4_OC
+ * @arg @ref ECU_PSR_ADRSEL_TIM5_OC
+ * @arg @ref ECU_PSR_ADRSEL_TIM6_OC
+ * @arg @ref ECU_PSR_ADRSEL_TIM7_OC
+ * @return None
+ */
+#define __LL_ECU_ADDR_FLAG_EVENT(__INSTANCE__, __EVENT__) MODIFY_REG((__INSTANCE__)->PRC, ECU_PRC_ADRSEL, __EVENT__)
+
+/**
+ * @brief Get the average effective value of the voltage
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return The result of the voltage
+ */
+#define __LL_ECU_GET_VRMS(__INSTANCE__) READ_BIT((__INSTANCE__)->V, ECU_V_VRMS)
+
+/**
+ * @brief Get the average effective value of the current
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return The result of the current
+ */
+#define __LL_ECU_GET_IRMS(__INSTANCE__) READ_BIT((__INSTANCE__)->I, ECU_I_IRMS)
+
+/**
+ * @brief Get the average active power
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return The result of average active power
+ */
+#define __LL_ECU_P_PAVG(__INSTANCE__) READ_REG((__INSTANCE__)->P)
+
+/**
+ * @brief Get the average reactive power
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return The result of average reactive power
+ */
+#define __LL_ECU_Q_QAVG(__INSTANCE__) READ_REG((__INSTANCE__)->Q)
+
+/**
+ * @brief Get the apparent power value
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return The result of apparent power
+ */
+#define __LL_ECU_S_SCAL(__INSTANCE__) READ_REG((__INSTANCE__)->S)
+
+/**
+ * @brief Get the power factor value
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return The result of power factor
+ */
+#define __LL_ECU_PF_PFCAL(__INSTANCE__) READ_REG((__INSTANCE__)->PF)
+
+/**
+ * @brief Get the fundamental frequency value
+ * @param __INSTANCE__ Specifies ECU peripheral
+ * @return The result of fundamental frequency
+ */
+#define __LL_ECU_F_FCNT(__INSTANCE__) READ_BIT((__INSTANCE__)->F, ECU_F_FCNT)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ECU_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ECU_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_ECU_Init(ECU_TypeDef *Instance, ECU_InitTypeDef *ECU_Init);
+LL_StatusETypeDef LL_ECU_DeInit(ECU_TypeDef *Instance);
+void LL_ECU_MspInit(ECU_TypeDef *Instance);
+void LL_ECU_MspDeInit(ECU_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/** @addtogroup ECU_LL_Exported_Functions_Group2
+ * @{
+ */
+void LL_ECU_WriteSqrtInData(ECU_TypeDef *Instance, uint32_t SqrtValue);
+uint32_t LL_ECU_ReadSqrtOutData(ECU_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/** @addtogroup ECU_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_ECU_IRQHandler(ECU_TypeDef *Instance);
+void LL_ECU_CalDoneCallback(ECU_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ECU_LL_Private_Macros ECU LL Private Macros
+ * @brief ECU LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is ECU enable/disable mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't ECU enable/disable mode
+ * @retval 1 is ECU enable/disable mode
+ */
+#define IS_ECU_MODULE(__MODE__) \
+ ( ((__MODE__) == ECU_DISABLE) \
+ || ((__MODE__) == ECU_ENABLE) \
+ )
+
+/**
+ * @brief Judge is ECU average or not
+ * @param __AVERAGE__ average to judge
+ * @retval 0 isn't ECU average
+ * @retval 1 is ECU average
+ */
+#define IS_ECU_AVERAGE(__AVERAGE__) \
+ ( ((__AVERAGE__) == ECU_AVERAGE_DISABLE) \
+ || ((__AVERAGE__) == ECU_AVERAGE_2PERIOD) \
+ || ((__AVERAGE__) == ECU_AVERAGE_4PERIOD) \
+ || ((__AVERAGE__) == ECU_AVERAGE_8PERIOD) \
+ )
+
+/**
+ * @brief Judge is ECU acsft or not
+ * @param __ACSFT__ acsft to judge
+ * @retval 0 isn't ECU acsft
+ * @retval 1 is ECU acsft
+ */
+#define IS_ECU_ACSFT(__ACSFT__) \
+ ( ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_DISABLE) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_1) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_2) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_3) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_4) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_5) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_6) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_7) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_8) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_9) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_10) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_11) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_12) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_13) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_14) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_15) \
+ || ((__ACSFT__) == ECU_ACPOWER_LEFT_SHIFT_16) \
+ )
+
+/**
+ * @brief Judge is ECU apsft or not
+ * @param __APSFT__ apsft to judge
+ * @retval 0 isn't ECU apsft
+ * @retval 1 is ECU apsft
+ */
+#define IS_ECU_APSFT(__APSFT__) \
+ ( ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_DISABLE) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_1) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_2) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_3) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_4) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_5) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_6) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_7) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_8) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_9) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_10) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_11) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_12) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_13) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_14) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_15) \
+ || ((__APSFT__) == ECU_APPOWER_RIGHT_SHIFT_16) \
+ )
+
+/**
+ * @brief Judge is ECU datsel or not
+ * @param __DATSEL__ datsel to judge
+ * @retval 0 isn't ECU datsel
+ * @retval 1 is ECU datsel
+ */
+#define IS_ECU_DATSEL(__DATSEL__) \
+ ( ((__DATSEL__) == ECU_PSR_DATSEL_ADC0_DTFLAG0) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_ADC0_DTFLAG1) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_ADC0_DTFLAG2) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_ADC0_DTFLAG3) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_ADC1_DTFLAG0) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_ADC1_DTFLAG1) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_ADC1_DTFLAG2) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_ADC1_DTFLAG3) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM0_OC) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM1_OC) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM2_OC) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM3_OC) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM4_OC) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM5_OC) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM6_OC) \
+ || ((__DATSEL__) == ECU_PSR_DATSEL_TIM7_OC) \
+ )
+
+/**
+ * @brief Judge is ECU crssel or not
+ * @param __CRSSEL__ crssel to judge
+ * @retval 0 isn't ECU crssel
+ * @retval 1 is ECU crssel
+ */
+#define IS_ECU_CRSSEL(__CRSSEL__) \
+ ( ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC0_PPFLAG0) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC0_PPFLAG1) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC0_PPFLAG2) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC0_PPFLAG3) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC1_PPFLAG0) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC1_PPFLAG1) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC1_PPFLAG2) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_ADC1_PPFLAG3) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM0_OC) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM1_OC) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM2_OC) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM3_OC) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM4_OC) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM5_OC) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM6_OC) \
+ || ((__CRSSEL__) == ECU_PSR_CRSSEL_TIM7_OC) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_ECU_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_flash.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_flash.h
new file mode 100644
index 0000000000..df8c01002d
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_flash.h
@@ -0,0 +1,451 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_flash.h
+ * @author MCD Application Team
+ * @brief Head file for FLASH module LL driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_FLASH_H_
+#define _TAE32F53XX_LL_FLASH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_LL_Exported_Types FLASH LL Exported Types
+ * @brief Set the read protection level
+ * @{
+ */
+
+/**
+ @brief Set the read protection level
+*/
+typedef enum {
+ FLASH_RDP_LEVEL_0 = 0xAAU, /*!< FLASH Read Protection Level 0 */
+ FLASH_RDP_LEVEL_1 = 0xFFU, /*!< FLASH Read Protection Level 1 */
+ FLASH_RDP_LEVEL_2 = 0xCCU, /*!< FLASH Read Protection Level 2, Warning: When enabling read protection
+ level 2,it's no more possible to go back to level 1 or 0 */
+} FLASH_RDPLVETypeDef;
+
+
+/**
+ @brief Write Protection State
+ */
+typedef enum {
+ FLASH_WRPSTATE_DISABLE = 0x00U, /*!< Disable the write protection of the desired sections */
+ FLASH_WRPSTATE_ENABLE = 0x01U, /*!< Enable the write protection of the desired sections */
+} FLASH_WRPSTETypeDef;
+
+/**
+ * @brief Write Permission Area Control. Each AREA control 8 sections (refer to one area) in Main Memory Array
+ */
+typedef enum {
+ FLASH_WRP_AREA_1 = 0x00000001, /*!< FLASH Write Protection Area 1 */
+ FLASH_WRP_AREA_2 = 0x00000002, /*!< FLASH Write Protection Area 2 */
+ FLASH_WRP_AREA_3 = 0x00000004, /*!< FLASH Write Protection Area 3 */
+ FLASH_WRP_AREA_4 = 0x00000008, /*!< FLASH Write Protection Area 4 */
+ FLASH_WRP_AREA_5 = 0x00000010, /*!< FLASH Write Protection Area 5 */
+ FLASH_WRP_AREA_6 = 0x00000020, /*!< FLASH Write Protection Area 6 */
+ FLASH_WRP_AREA_7 = 0x00000040, /*!< FLASH Write Protection Area 7 */
+ FLASH_WRP_AREA_8 = 0x00000080, /*!< FLASH Write Protection Area 8 */
+ FLASH_WRP_AREA_9 = 0x00000100, /*!< FLASH Write Protection Area 9 */
+ FLASH_WRP_AREA_10 = 0x00000200, /*!< FLASH Write Protection Area 10 */
+ FLASH_WRP_AREA_11 = 0x00000400, /*!< FLASH Write Protection Area 11 */
+ FLASH_WRP_AREA_12 = 0x00000800, /*!< FLASH Write Protection Area 12 */
+ FLASH_WRP_AREA_13 = 0x00001000, /*!< FLASH Write Protection Area 13 */
+ FLASH_WRP_AREA_14 = 0x00002000, /*!< FLASH Write Protection Area 14 */
+ FLASH_WRP_AREA_15 = 0x00004000, /*!< FLASH Write Protection Area 15 */
+ FLASH_WRP_AREA_16 = 0x00008000, /*!< FLASH Write Protection Area 16 */
+ FLASH_WRP_AREA_17 = 0x00010000, /*!< FLASH Write Protection Area 17 */
+ FLASH_WRP_AREA_18 = 0x00020000, /*!< FLASH Write Protection Area 18 */
+ FLASH_WRP_AREA_19 = 0x00040000, /*!< FLASH Write Protection Area 19 */
+ FLASH_WRP_AREA_20 = 0x00080000, /*!< FLASH Write Protection Area 20 */
+ FLASH_WRP_AREA_ALL = 0x000FFFFF, /*!< FLASH Write Protection Area ALL */
+ FLASH_WRP_AREA_Msk = FLASH_WRP_AREA_ALL, /*!< FLASH Write Protection Area Mask */
+} FLASH_WRPAREAETypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_LL_Exported_Constants FLASH LL Exported Constants
+ * @brief FLASH LL Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+ * @{
+ */
+#define FLASH_ERROR_NONE 0x00U /*!< No error */
+#define FLASH_ERROR_OPT 0x01U /*!< Operation error */
+#define FLASH_ERROR_WRP 0x02U /*!< Write protection error */
+#define FLASH_ERROR_RDP 0x04U /*!< Read protection error */
+#define FLASH_ERROR_ECC 0x08U /*!< ECC validity error */
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASH_Program_Width FLASH Program Width
+ * @{
+ */
+#define FLASH_PROG_DATA_WIDTH 16U /*!< Data width in a single programming operation.Number in bytes */
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASH_Keys FLASH Keys
+ * @{
+ */
+#define FLASH_KEY1 0x32107654U /*!< FLASH key1 */
+#define FLASH_KEY2 0xFEDCBA98U /*!< FLASH key2: used with FLASH_KEY1
+ to unlock the FLASH Program/Erase features */
+
+#define FLASH_OP_KEY 0x50035003U /*!< FLASH Operation Protection Key :
+ Unlock the operation of FLASH Read/Write Protection Register */
+
+#define FLASH_PWR_KEY 0x50030000U /*!< FLASH pwr key: unlock the FLASH Standby/Wakeup features */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag Definition
+ * @{
+ */
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Flag BSY */
+#define FLASH_FLAG_DIF FLASH_ISR_DIF /*!< FLASH Flag DIF */
+#define FLASH_FLAG_ECCEIF FLASH_ISR_ECCEIF /*!< FLASH Flag ECCEIF */
+#define FLASH_FLAG_RPEIF FLASH_ISR_RPEIF /*!< FLASH Flag RPEIF */
+#define FLASH_FLAG_WPEIF FLASH_ISR_WPEIF /*!< FLASH Flag WPEIF */
+#define FLASH_FLAG_OPTEIF FLASH_ISR_OPTEIF /*!< FLASH Flag OPEIF */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_LL_Exported_Macros FLASH LL Exported Macros
+ * @brief FLASH LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable FLASH I BUS Prefetch feature.
+ * @note Prefetch feature should not be enabled when CPU frequency is lower than 40MHz.
+ * @param None
+ * @return None
+ */
+#define __LL_FLASH_I_BUS_PREFETCH_ENABLE() SET_BIT(FLASH->CR, FLASH_CR_IBPE)
+
+/**
+ * @brief Disable FLASH I BUS Prefetch feature.
+ * @param None
+ * @return None
+ */
+#define __LL_FLASH_I_BUS_PREFETCH_DISABLE() CLEAR_BIT(FLASH->CR, FLASH_CR_IBPE)
+
+/**
+ * @brief Enable FLASH D BUS Prefetch feature.
+ * @note Prefetch feature should not be enabled when CPU frequency is lower than 40MHz.
+ * @param None
+ * @return None
+ */
+#define __LL_FLASH_D_BUS_PREFETCH_ENABLE() SET_BIT(FLASH->CR, FLASH_CR_DBPE)
+
+/**
+ * @brief Disable FLASH D BUS Prefetch feature.
+ * @param None
+ * @return None
+ */
+#define __LL_FLASH_D_BUS_PREFETCH_DISABLE() CLEAR_BIT(FLASH->CR, FLASH_CR_DBPE)
+
+/**
+ * @brief FLASH Standby.
+ * Flash will enter standby mode aim for low power mode.
+ * @param None
+ * @return None
+ */
+#define __LL_FLASH_STANDBY_ENABLE() do{ WRITE_REG(FLASH->LPR, FLASH_PWR_KEY); \
+ SET_BIT(FLASH->LPR, FLASH_LPR_STDBY); \
+ } while (0);
+
+/**
+ * @brief FLASH Wakeup.
+ * Flash will exit from standby mode.
+ * @param None
+ * @return None
+ */
+#define __LL_FLASH_WAKEUP_ENABLE() do{ WRITE_REG(FLASH->LPR, FLASH_PWR_KEY); \
+ SET_BIT(FLASH->LPR, FLASH_LPR_WKUP); \
+ } while (0);
+
+/**
+ * @brief Check whether the specified status flag in FLASH_SR Register is SET or not.
+ * @param __FLAG__ specifies the FLASH status flag to check.
+ * This parameter can be ONE of the following values:
+ * @arg FLASH_FLAG_BSY : FLASH BUSY Status
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_FLASH_GET_STATUS_FLAG(__FLAG__) ((READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified interrupt pending flag in FLASH_ISR Register is SET or not.
+ * @param __FLAG__ specifies the FLASH interrupt pending flag to check.
+ * This parameter can be ONE of the following values:
+ * @arg FLASH_FLAG_DIF : Done
+ * @arg FLASH_FLAG_ECCEIF : ECC Error
+ * @arg FLASH_FLAG_RPEIF : Read Protection Error
+ * @arg FLASH_FLAG_WPEIF : Write Protection Error
+ * @arg FLASH_FLAG_OPTEIF : Operation Error
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_FLASH_GET_PENDING_FLAG(__FLAG__) ((READ_BIT(FLASH->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the FLASH's Pending Register flag.
+ * @param __FLAG__ specifies the FLASH pending flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_DIF : Done
+ * @arg FLASH_FLAG_ECCEIF : ECC Error
+ * @arg FLASH_FLAG_RPEIF : Read Protection Error
+ * @arg FLASH_FLAG_WPEIF : Write Protection Error
+ * @arg FLASH_FLAG_OPTEIF : Operation Error
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_FLASH_CLEAR_PENDING_FLAG(__FLAG__) WRITE_REG(FLASH->ISR, (__FLAG__))
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_FLASH_ReadProtectLevelConfig(FLASH_RDPLVETypeDef RDPLevel);
+LL_StatusETypeDef LL_FLASH_WriteProtectConfig(FLASH_WRPAREAETypeDef WRPAreas, FLASH_WRPSTETypeDef WRPState);
+/**
+ * @}
+ */
+
+
+/** @addtogroup FLASH_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_FLASH_WaitForLastOperation(uint32_t Timeout);
+uint32_t LL_FLASH_GetError(void);
+/**
+ * @}
+ */
+
+
+/** @addtogroup FLASH_LL_Exported_Functions_Group3
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH Program/Erase access.
+ * @param None
+ * @return LL Status
+ */
+__STATIC_INLINE LL_StatusETypeDef LL_FLASH_Unlock(void)
+{
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) {
+ /* Authorize the FLASH Program/Erase access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+ /* Verify FLASH is unlocked */
+ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK_Msk) != RESET) {
+ return LL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Program/Erase access.
+ * @param None
+ * @return LL Status
+ */
+__STATIC_INLINE LL_StatusETypeDef LL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Program/Erase access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Unlock the FLASH write/read Protection Feature access.
+ * @param None
+ * @return LL Status
+ */
+__STATIC_INLINE LL_StatusETypeDef LL_FLASH_PF_Unlock(void)
+{
+ /* Unlock the FLASH Read/Write Operation Protection access */
+ WRITE_REG(FLASH->KEYR, FLASH_OP_KEY);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Lock the FLASH write/read Protection Feature access.
+ * @param None
+ * @return LL Status
+ */
+__STATIC_INLINE LL_StatusETypeDef LL_FLASH_PF_Lock(void)
+{
+ /* Lock the Read/Write Operation Protection access */
+ WRITE_REG(FLASH->KEYR, 0x00000000UL);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Launch the write/read Protection Feature reloading.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE LL_StatusETypeDef LL_FLASH_PF_Launch(void)
+{
+ /* Set the LAU bit in FLASH_CR register to reload */
+ SET_BIT(FLASH->CR, FLASH_CR_LAU);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+
+LL_StatusETypeDef LL_FLASH_Program(uint32_t Address, uint8_t Data[FLASH_PROG_DATA_WIDTH]);
+
+LL_StatusETypeDef LL_FLASH_MultiSectorsErase(uint16_t Sector, uint16_t Num, uint16_t *SectorError);
+LL_StatusETypeDef LL_FLASH_SectorErase(uint16_t Sector);
+
+LL_StatusETypeDef LL_FLASH_ChipErase(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_LL_Private_Constants FLASH LL Private Constants
+ * @brief FLASH LL Private Constants
+ * @{
+ */
+
+#define FLASH_PROGRAM_ADDRESS_MASK 0x00FFFFFFU /*!< Program address mask */
+#define FLASH_TIMEOUT_MAX_VALUE 300U /*!< Max timeout for flash operations. Default 300 ticks */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_LL_Private_Macros FLASH LL Private Macros
+ * @brief FLASH LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is write protect state or not
+ * @param STATE state to judge
+ * @retval 0 isn't write protect state
+ * @retval 1 is write protect state
+ */
+#define IS_WRITE_PROTECT_STATE(STATE) (((STATE) == FLASH_WRPSTATE_DISABLE) || \
+
+/**
+ * @brief Judge is flash program address align 128bit or not
+ * @param ADDRESS address to judge
+ * @retval 0 isn't flash program address align 128bit
+ * @retval 1 is flash program address align 128bit
+ */
+#define IS_FLASH_PROGRAM_ADDRESS_ALIGN_128BIT(ADDRESS) (((ADDRESS) & 0xF) == 0x00U)
+
+/**
+ * @brief Judge is flash sector or not
+ * @param SECTOR sector to judge
+ * @retval 0 isn't flash sector
+ * @retval 1 is flash sector
+ */
+#define IS_FLASH_NB_SECTORS(SECTOR) ((SECTOR) < 160U)
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_FLASH_H_ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_fpll.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_fpll.h
new file mode 100644
index 0000000000..f0abf10366
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_fpll.h
@@ -0,0 +1,148 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_fpll.h
+ * @author MCD Application Team
+ * @brief Header file for FPLL LL Module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_FPLL_H_
+#define _TAE32F53XX_LL_FPLL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup FPLL_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FPLL_LL_Exported_Macros FPLL LL Exported Macros
+ * @brief FPLL LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief FPLL Enable
+ * @param __FPLL__ Specifies FPLL peripheral
+ * @return None
+ */
+#define __LL_FPLL_En(__FPLL__) SET_BIT((__FPLL__)->FCR, FPLL_EN_Msk)
+
+/**
+ * @brief FPLL Disable
+ * @param __FPLL__ Specifies FPLL peripheral
+ * @return None
+ */
+#define __LL_FPLL_Dis(__FPLL__) CLEAR_BIT((__FPLL__)->FCR, FPLL_EN_Msk)
+
+/**
+ * @brief FPLL Start
+ * @param __FPLL__ Specifies FPLL peripheral
+ * @return None
+ */
+#define __LL_FPLL_Start(__FPLL__) SET_BIT((__FPLL__)->FCR, FPLL_START_Msk)
+
+
+/**
+ * @brief FPLL Div Integer Set
+ * @param __FPLL__ Specifies FPLL peripheral
+ * @param integer FPLL Div Integer
+ * @return None
+ */
+#define __LL_FPLL_DivInt_Set(__FPLL__, integer) \
+ MODIFY_REG((__FPLL__)->FDR, FPLL_DIV_INT_Msk, ((integer & 0x3fffUL) << FPLL_DIV_INT_Pos))
+
+/**
+ * @brief FPLL Div Fraction Set
+ * @param __FPLL__ Specifies FPLL peripheral
+ * @param frac FPLL Div Fraction
+ * @return None
+ */
+#define __LL_FPLL_DivFrac_Set(__FPLL__, frac) \
+ MODIFY_REG((__FPLL__)->FDR, FPLL_DIV_FRAC_Msk, ((frac & 0xffffUL) << FPLL_DIV_FRAC_Pos))
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FPLL_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FPLL_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_FPLL_Init(FPLL_TypeDef *Instance);
+LL_StatusETypeDef LL_FPLL_DeInit(FPLL_TypeDef *Instance);
+void LL_FPLL_MspInit(FPLL_TypeDef *Instance);
+void LL_FPLL_MspDeInit(FPLL_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup FPLL_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_FPLL_DivStart(FPLL_TypeDef *Instance, uint16_t integer, uint16_t frac);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_FPLL_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_gpio.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_gpio.h
new file mode 100644
index 0000000000..2739175777
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_gpio.h
@@ -0,0 +1,518 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_GPIO_H_
+#define _TAE32F53XX_LL_GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Types GPIO LL Exported Types
+ * @brief GPIO LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0Y0000Z
+ * - X : GPIO mode or Interrupt Mode
+ * - Y : External IT detection
+ * - Z : IO Direction mode (Input, Output or Alternate)
+ * @note External Interrupt only vailed in input mode
+ */
+typedef enum {
+ GPIO_MODE_INPUT = 0x00000000u, /*!< GPIO Input Mode */
+ GPIO_MODE_OUTPUT = 0x00000001u, /*!< GPIO Output Mode */
+ GPIO_MODE_AF = 0x00000002u, /*!< GPIO Alternate Mode */
+ GPIO_MODE_ANALOG = 0x00000003u, /*!< Analog Mode */
+ GPIO_MODE_IT_RISING = 0x10100000u, /*!< External Interrupt Mode with Rising edge trigger detection */
+ GPIO_MODE_IT_FALLING = 0x10200000u, /*!< External Interrupt Mode with Falling edge trigger detection */
+ GPIO_MODE_IT_RISING_FALLING = 0x10300000u, /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+} GPIO_ModeETypeDef;
+
+/**
+ * @brief GPIO AF Mode enumeration
+ */
+
+typedef enum {
+ GPIO_AF0_INPUT = ((uint8_t)0x0), /*!< GPIO alternate function 0 INPUT */
+
+ GPIO_AF1_OUTPUT = ((uint8_t)0x1), /*!< GPIO alternate function 1 OUTPUT */
+
+ GPIO_AF2_MCO = ((uint8_t)0x2), /*!< GPIO alternate function 2 MCO */
+ GPIO_AF2_SWDAT = ((uint8_t)0x2), /*!< GPIO alternate function 2 SWDAT */
+ GPIO_AF2_SWCLK = ((uint8_t)0x2), /*!< GPIO alternate function 2 SWCLK */
+ GPIO_AF2_SWO = ((uint8_t)0x2), /*!< GPIO alternate function 2 SWO */
+ GPIO_AF2_SYSDBOUT = ((uint8_t)0x2), /*!< GPIO alternate function 2 SYSDBOUT */
+
+ GPIO_AF3_TMR0 = ((uint8_t)0x3), /*!< GPIO alternate function 3 TMR0 */
+ GPIO_AF3_TMR1 = ((uint8_t)0x3), /*!< GPIO alternate function 3 TMR1 */
+ GPIO_AF3_TMR2 = ((uint8_t)0x3), /*!< GPIO alternate function 3 TMR2 */
+ GPIO_AF3_TMR3 = ((uint8_t)0x3), /*!< GPIO alternate function 3 TMR3 */
+
+ GPIO_AF4_TMR0 = ((uint8_t)0x4), /*!< GPIO alternate function 4 TMR0 */
+ GPIO_AF4_TMR1 = ((uint8_t)0x4), /*!< GPIO alternate function 4 TMR1 */
+ GPIO_AF4_TMR2 = ((uint8_t)0x4), /*!< GPIO alternate function 4 TMR2 */
+ GPIO_AF4_TMR3 = ((uint8_t)0x4), /*!< GPIO alternate function 4 TMR3 */
+
+ GPIO_AF5_TMR4 = ((uint8_t)0x5), /*!< GPIO alternate function 5 TMR4 */
+ GPIO_AF5_TMR5 = ((uint8_t)0x5), /*!< GPIO alternate function 5 TMR5 */
+ GPIO_AF5_TMR6 = ((uint8_t)0x5), /*!< GPIO alternate function 5 TMR6 */
+ GPIO_AF5_TMR7 = ((uint8_t)0x5), /*!< GPIO alternate function 5 TMR7 */
+
+ GPIO_AF6_TMR4 = ((uint8_t)0x6), /*!< GPIO alternate function 6 TMR4 */
+ GPIO_AF6_TMR5 = ((uint8_t)0x6), /*!< GPIO alternate function 6 TMR5 */
+ GPIO_AF6_TMR6 = ((uint8_t)0x6), /*!< GPIO alternate function 6 TMR6 */
+ GPIO_AF6_TMR7 = ((uint8_t)0x6), /*!< GPIO alternate function 6 TMR7 */
+
+ GPIO_AF7_CAN = ((uint8_t)0x7), /*!< GPIO alternate function 7 CAN */
+ GPIO_AF7_I2C0 = ((uint8_t)0x7), /*!< GPIO alternate function 7 I2C0 */
+
+ GPIO_AF8_I2C0 = ((uint8_t)0x8), /*!< GPIO alternate function 8 I2C0 */
+ GPIO_AF8_DALI = ((uint8_t)0x8), /*!< GPIO alternate function 8 DALI */
+
+ GPIO_AF9_I2C1 = ((uint8_t)0x9), /*!< GPIO alternate function 9 I2C1 */
+ GPIO_AF9_UART1 = ((uint8_t)0x9), /*!< GPIO alternate function 9 UART1 */
+
+ GPIO_AF10_UART0 = ((uint8_t)0xA), /*!< GPIO alternate function 10 UART0 */
+ GPIO_AF10_UART1 = ((uint8_t)0xA), /*!< GPIO alternate function 10 UART1 */
+
+ GPIO_AF11_HRPWM = ((uint8_t)0xB), /*!< GPIO alternate function 11 HRPWM */
+ GPIO_AF11_USB = ((uint8_t)0xB), /*!< GPIO alternate function 1 USB */
+
+ GPIO_AF12_HRPWM = ((uint8_t)0xC), /*!< GPIO alternate function 12 HRPWM */
+
+ GPIO_AF13_HRPWM = ((uint8_t)0xD), /*!< GPIO alternate function 13 HRPWM */
+
+ GPIO_AF14_CMP0 = ((uint8_t)0xE), /*!< GPIO alternate function 14 CMP0 */
+ GPIO_AF14_CMP1 = ((uint8_t)0xE), /*!< GPIO alternate function 14 CMP1 */
+ GPIO_AF14_CMP2 = ((uint8_t)0xE), /*!< GPIO alternate function 14 CMP2 */
+ GPIO_AF14_CMP3 = ((uint8_t)0xE), /*!< GPIO alternate function 14 CMP3 */
+
+ GPIO_AF15_ANALOG = ((uint8_t)0xF), /*!< GPIO alternate function 15 ANALOG */
+ GPIO_AF15_ADC0 = ((uint8_t)0xF), /*!< GPIO alternate function 15 ADC0 */
+ GPIO_AF15_ADC1 = ((uint8_t)0xF), /*!< GPIO alternate function 15 ADC1 */
+ GPIO_AF15_DAC0 = ((uint8_t)0xF), /*!< GPIO alternate function 15 DAC0 */
+ GPIO_AF15_DAC1 = ((uint8_t)0xF), /*!< GPIO alternate function 15 DAC1 */
+ GPIO_AF15_DAC2 = ((uint8_t)0xF), /*!< GPIO alternate function 15 DAC2 */
+ GPIO_AF15_DAC3 = ((uint8_t)0xF), /*!< GPIO alternate function 15 DAC3 */
+ GPIO_AF15_CMP0 = ((uint8_t)0xF), /*!< GPIO alternate function 15 CMP0 */
+ GPIO_AF15_CMP1 = ((uint8_t)0xF), /*!< GPIO alternate function 15 CMP1 */
+ GPIO_AF15_CMP2 = ((uint8_t)0xF), /*!< GPIO alternate function 15 CMP2 */
+ GPIO_AF15_CMP3 = ((uint8_t)0xF), /*!< GPIO alternate function 15 CMP3 */
+ GPIO_AF15_USB = ((uint8_t)0xF), /*!< GPIO alternate function 15 USB */
+} GPIO_AFETypeDef;
+
+/**
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ */
+typedef enum {
+ GPIO_NOPULL = 0x00000000U, /*!< No Pull-up or Pull-down activation */
+ GPIO_PULLUP = 0x00000001U, /*!< Pull-up activation */
+ GPIO_PULLDOWN = 0x00000002U, /*!< Pull-down activation */
+} GPIO_PullETypeDef;
+
+/**
+ * @brief GPIO output type: Push-Pull or Open-Drain
+ */
+typedef enum {
+ GPIO_OTYPE_PP = 0x00000000U, /*!< Output Push Pull Type */
+ GPIO_OTYPE_OD = 0x00000001U, /*!< Output Open Drain Type */
+} GPIO_OutputETypeDef;
+
+/**
+ * @brief GPIO Output Maximum frequency
+ */
+typedef enum {
+ GPIO_SPEED_FREQ_LOW = 0x00000000U, /*!< Low speed */
+ GPIO_SPEED_FREQ_HIGH = 0x00000001U, /*!< High speed */
+} GPIO_SpeedETypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum {
+ GPIO_PIN_RESET = 0, /*!< GPIO pin state RESET */
+ GPIO_PIN_SET, /*!< GPIO pin state SET */
+} GPIO_PinStateETypeDef;
+
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct __GPIO_InitTypeDef {
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIO_ModeETypeDef Mode; /*!< Specifies the operating mode for the selected pins. */
+
+ GPIO_OutputETypeDef OType; /*!< Specifies the output type for the selected pins(output or AF output mode only). */
+
+ GPIO_PullETypeDef Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. */
+
+ GPIO_SpeedETypeDef Speed; /*!< Specifies the speed for the selected pins. */
+
+ GPIO_AFETypeDef Alternate; /*!< Peripheral to be connected to the selected pins. */
+} GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO LL Exported Constants
+ * @brief GPIO LL Exported Constants
+ * @{
+ */
+
+/** @addtogroup GPIO_pins_define GPIO pins define
+ * @{
+ */
+#define GPIO_NUMBER 16U
+
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO LL Exported Macros
+ * @brief GPIO LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the specified GPIO_Port interrupt.
+ * @param __GPIO__ specifies GPIO Port to enable.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @return None
+ */
+#define __LL_GPIO_PORT_IT_ENABLE(__GPIO__) WRITE_REG((__GPIO__)->IER, 0x01U)
+
+/**
+ * @brief Disable the specified GPIO_Port interrupt.
+ * @param __GPIO__ specifies GPIO Port to disable.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @return None
+ */
+#define __LL_GPIO_PORT_IT_DISABLE(__GPIO__) WRITE_REG((__GPIO__)->IER, 0x00U)
+
+/**
+ * @brief Enable the specified GPIO_Pin interrupt.
+ * @note GPIO_Port interrupt must also be enabled.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_IT_ENABLE(__GPIO__, __PIN__) SET_BIT((__GPIO__)->ITER, (__PIN__))
+
+/**
+ * @brief Disable the specified GPIO_Pin interrupt.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_IT_DISABLE(__GPIO__, __PIN__) CLEAR_BIT((__GPIO__)->ITER, (__PIN__))
+
+/**
+ * @brief Check whether the specified GPIO_Pin Interrupt is enabled or not.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return The interrupt settings for specified GPIO_Pin(ENABLE or DISABLE)
+ */
+#define __LL_GPIO_IT_CHECK_SOURCE(__GPIO__, __PIN__) ((((__GPIO__)->ITER & GPIO_ITER_ITE) == (__PIN__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified GPIO_Pin pending flag is set or not.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return The pending state of __PIN__
+ * @retval SET At least one of __PIN__ is Pending
+ * @retval RESET None of __PIN__ is Pending
+ */
+#define __LL_GPIO_GET_FLAG(__GPIO__, __PIN__) ((((__GPIO__)->PR & (__PIN__)) != 0x00UL) ? SET : RESET)
+
+/**
+ * @brief Clear the specified GPIO_Pin pending flags
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_CLEAR_FLAG(__GPIO__, __PIN__) ((__GPIO__)->PR = (__PIN__))
+
+/**
+ * @brief Check whether the specified GPIO_Pin interrupt pending flag is asserted or not.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return The interrupt pending state of __PIN__
+ * @retval SET At least one of __PIN__ is pending interrupt
+ * @retval RESET None of __PIN__ is pending interrupt
+ */
+#define __LL_GPIO_GET_IT(__GPIO__, __PIN__) ((((__GPIO__)->PR & (__PIN__)) != 0x00UL) ? SET : RESET)
+
+/**
+ * @brief Clear the specified GPIO_Pin interrupt pending flags
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_CLEAR_IT(__GPIO__, __PIN__) ((__GPIO__)->PR = (__PIN__))
+
+/**
+ * @brief Enable the specified GPIO_Pin input debounce feature.
+ * The external signal will debounce 4 HCLK time before enter GPIO module
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_INPUT_DEB_ENABLE(__GPIO__, __PIN__) SET_BIT((__GPIO__)->SDER, (__PIN__))
+
+/**
+ * @brief Disable the specified GPIO_Pin input debounce feature.
+ * The external signal will enter GPIO module without any debounce
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_INPUT_DEB_DISABLE(__GPIO__, __PIN__) CLEAR_BIT((__GPIO__)->SDER, (__PIN__))
+
+/**
+ * @brief Enable the specified GPIO_Pin input synchronize feature.
+ * The external signal will be aligned with HCLK before enter GPIO module
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_INPUT_SYNC_ENABLE(__GPIO__, __PIN__) SET_BIT((__GPIO__)->SDER, ((__PIN__) << 16U))
+
+/**
+ * @brief Disable the specified GPIO_Pin input synchronize feature.
+ * The external signal will enter GPIO module without synchronization
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_INPUT_SYNC_DISABLE(__GPIO__, __PIN__) CLEAR_BIT((__GPIO__)->SDER, ((__PIN__) << 16U))
+
+/**
+ * @brief Enable the specified GPIO_Pin input Hysteresis feature.
+ * When enable hysteresis, the rising edge?threshold?voltage is larger than the falling edge?threshold?voltage
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_INPUT_HY_ENABLE(__GPIO__, __PIN__) SET_BIT((__GPIO__)->IHYR, (__PIN__))
+
+/**
+ * @brief Disable the specified GPIO_Pin input Hysteresis feature.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_INPUT_HY_DISABLE(__GPIO__, __PIN__) CLEAR_BIT((__GPIO__)->IHYR, (__PIN__))
+
+/**
+ * @brief Set low output driver strenght (8mA) for specified GPIO_Pin.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_OUTPUT_DRV_STRENGHT_LOW(__GPIO__, __PIN__) CLEAR_BIT((__GPIO__)->DSR, (__PIN__))
+
+/**
+ * @brief Set high output driver strenght (24mA) for specified GPIO_Pin.
+ * @param __GPIO__ specifies GPIO Port.
+ * This parameter can be one of GPIOx where x can be (A, B, ...)
+ * @param __PIN__ specifies GPIO Pin.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return None
+ */
+#define __LL_GPIO_OUTPUT_DRV_STRENGHT_HIGH(__GPIO__, __PIN__) SET_BIT((__GPIO__)->DSR, (__PIN__))
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+LL_StatusETypeDef LL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+
+/** @addtogroup GPIO_LL_Exported_Functions_Group2
+ * @{
+ */
+void LL_GPIO_AF_Config(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_AFETypeDef Alternate);
+/**
+ * @}
+ */
+
+
+/** @addtogroup GPIO_LL_Exported_Functions_Group3
+ * @{
+ */
+GPIO_PinStateETypeDef LL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) ;
+void LL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinStateETypeDef PinState);
+void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+uint16_t LL_GPIO_ReadData(GPIO_TypeDef *GPIOx);
+void LL_GPIO_WriteData(GPIO_TypeDef *GPIOx, uint16_t Data);
+/**
+ * @}
+ */
+
+
+/** @addtogroup GPIO_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_GPIO_IRQHandler(GPIO_TypeDef *GPIOx);
+void LL_GPIO_ExtTrigCallback(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Private_Macros GPIO LL Private Macros
+ * @brief GPIO LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is GPIO pin or not
+ * @param __PIN__ pin to judge
+ * @retval 0 isn't GPIO pin
+ * @retval 1 is GPIO pin
+ */
+#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) && \
+ (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_GPIO_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_hrpwm.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_hrpwm.h
new file mode 100644
index 0000000000..22e14f3ac7
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_hrpwm.h
@@ -0,0 +1,3550 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_hrpwm.h
+ * @author MCD Application Team
+ * @brief Header file of HRPWM LL module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_HRPWM_H_
+#define _TAE32F53XX_LL_HRPWM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup HRPWM_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRPWM_LL_Exported_Constants HRPWM LL Exported Constants
+ * @brief HRPWM LL Exported Constants
+ * @{
+ */
+
+/** @defgroup HRPWM_Max_Timer HRPWM Max Timer
+ * @{
+ */
+#define MAX_HRPWM_TIMER 6U
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Index HRPWM Index
+ * @brief Constants defining the hrpwm indexes
+ * @{
+ */
+#define HRPWM_INDEX_SLAVE_0 0x0U /*!< Index used to access slave pwm 0 registers */
+#define HRPWM_INDEX_SLAVE_1 0x1U /*!< Index used to access slave pwm 1 registers */
+#define HRPWM_INDEX_SLAVE_2 0x2U /*!< Index used to access slave pwm 2 registers */
+#define HRPWM_INDEX_SLAVE_3 0x3U /*!< Index used to access slave pwm 3 registers */
+#define HRPWM_INDEX_SLAVE_4 0x4U /*!< Index used to access slave pwm 4 registers */
+#define HRPWM_INDEX_SLAVE_5 0x5U /*!< Index used to access slave pwm 5 registers */
+#define HRPWM_INDEX_MASTER 0x6U /*!< Index used to access master registers */
+#define HRPWM_INDEX_COMMON 0xFFU /*!< Index used to access HRPWM common registers */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Compare_Unit HRPWM Compare Unit
+ * @brief Constants defining compare unit identifiers
+ * @{
+ */
+#define HRPWM_COMPAREUNIT_A 0x00000001U /*!< Compare unit A identifier */
+#define HRPWM_COMPAREUNIT_B 0x00000002U /*!< Compare unit B identifier */
+#define HRPWM_COMPAREUNIT_C 0x00000004U /*!< Compare unit C identifier */
+#define HRPWM_COMPAREUNIT_D 0x00000008U /*!< Compare unit D identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Output_Start HRPWM Timer Output
+ * @brief Constants defining timer output identifiers -- output enable,not enable cannot output wave
+ * @{
+ */
+#define HRPWM_OUTPUT_OEN0A 0x00000001U /*!< Timer 0 - Output A identifier */
+#define HRPWM_OUTPUT_OEN0B 0x00000002U /*!< Timer 0 - Output B identifier */
+#define HRPWM_OUTPUT_OEN1A 0x00000004U /*!< Timer 1 - Output A identifier */
+#define HRPWM_OUTPUT_OEN1B 0x00000008U /*!< Timer 1 - Output B identifier */
+#define HRPWM_OUTPUT_OEN2A 0x00000010U /*!< Timer 2 - Output A identifier */
+#define HRPWM_OUTPUT_OEN2B 0x00000020U /*!< Timer 2 - Output B identifier */
+#define HRPWM_OUTPUT_OEN3A 0x00000040U /*!< Timer 3 - Output A identifier */
+#define HRPWM_OUTPUT_OEN3B 0x00000080U /*!< Timer 3 - Output B identifier */
+#define HRPWM_OUTPUT_OEN4A 0x00000100U /*!< Timer 4 - Output A identifier */
+#define HRPWM_OUTPUT_OEN4B 0x00000200U /*!< Timer 4 - Output B identifier */
+#define HRPWM_OUTPUT_OEN5A 0x00000400U /*!< Timer 5 - Output A identifier */
+#define HRPWM_OUTPUT_OEN5B 0x00000800U /*!< Timer 5 - Output B identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Output_Stop HRPWM Timer Output Disable
+ * @brief Constants defining timer disable output identifiers
+ * @{
+ */
+#define HRPWM_OUTPUT_ODIS0A 0x00000001U /*!< Timer 0 - Disable Output A identifier */
+#define HRPWM_OUTPUT_ODIS0B 0x00000002U /*!< Timer 0 - Disable Output B identifier */
+#define HRPWM_OUTPUT_ODIS1A 0x00000004U /*!< Timer 1 - Disable Output A identifier */
+#define HRPWM_OUTPUT_ODIS1B 0x00000008U /*!< Timer 1 - Disable Output B identifier */
+#define HRPWM_OUTPUT_ODIS2A 0x00000010U /*!< Timer 2 - Disable Output A identifier */
+#define HRPWM_OUTPUT_ODIS2B 0x00000020U /*!< Timer 2 - Disable Output B identifier */
+#define HRPWM_OUTPUT_ODIS3A 0x00000040U /*!< Timer 3 - Disable Output A identifier */
+#define HRPWM_OUTPUT_ODIS3B 0x00000080U /*!< Timer 3 - Disable Output B identifier */
+#define HRPWM_OUTPUT_ODIS4A 0x00000100U /*!< Timer 4 - Disable Output A identifier */
+#define HRPWM_OUTPUT_ODIS4B 0x00000200U /*!< Timer 4 - Disable Output B identifier */
+#define HRPWM_OUTPUT_ODIS5A 0x00000400U /*!< Timer 5 - Disable Output A identifier */
+#define HRPWM_OUTPUT_ODIS5B 0x00000800U /*!< Timer 5 - Disable Output B identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Synchronization_Options HRPWM Synchronization Options
+ * @brief Constants defining the options for synchronizing multiple HRPWM
+ * instances, as a master unit (generating a synchronization signal)
+ * or as a slave (waiting for a trigger to be synchronized)
+ * @{
+ */
+#define HRPWM_SYNCOPTION_NONE 0x0 /*!< HRPWM instance doesn't handle external sync signals (SYNCIN, SYNCOUT) */
+#define HRPWM_SYNCOPTION_MASTER 0x1U/*!< HRPWM instance acts as a MASTER, i.e. generates external sync output (SYNCOUT) */
+#define HRPWM_SYNCOPTION_SLAVE 0x2U/*!< HRPWM instance acts as a SLAVE, i.e. it is sync by external sources (SYNCIN) */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Update_Trigger HRPWM Timer Update Trigger
+ * @brief Constants defining whether the registers update is done synchronously with any other timer or master update
+ * @{
+ */
+#define HRPWM_UPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */
+#define HRPWM_UPDATETRIGGER_MASTER (HRPWM_CR0_MUPD) /*!< Register update is triggered by the master timer update */
+#define HRPWM_UPDATETRIGGER_TIMER_0 (HRPWM_CR0_UPD0) /*!< Register update is triggered by the timer 0 update */
+#define HRPWM_UPDATETRIGGER_TIMER_1 (HRPWM_CR0_UPD1) /*!< Register update is triggered by the timer 1 update */
+#define HRPWM_UPDATETRIGGER_TIMER_2 (HRPWM_CR0_UPD2) /*!< Register update is triggered by the timer 2 update */
+#define HRPWM_UPDATETRIGGER_TIMER_3 (HRPWM_CR0_UPD3) /*!< Register update is triggered by the timer 3 update */
+#define HRPWM_UPDATETRIGGER_TIMER_4 (HRPWM_CR0_UPD4) /*!< Register update is triggered by the timer 4 update */
+#define HRPWM_UPDATETRIGGER_TIMER_5 (HRPWM_CR0_UPD5) /*!< Register update is triggered by the timer 5 update */
+#define HRPWM_UPDATETRIGGER_REP (HRPWM_CR0_UPDREP) /*!< Register update is triggered by the Repetition update */
+#define HRPWM_UPDATETRIGGER_RST (HRPWM_CR0_UPDRST) /*!< Register update is triggered by the reset update */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Set_Trigger HRPWM Output Set A\B Source
+ * @brief Constants defining the events that can be selected to configure the set crossbar of a timer output
+ * @{
+ */
+#define HRPWM_OUTPUT_SET_NONE (0x00000000U) /*!< HRPWM output set none */
+#define HRPWM_OUTPUT_SET_SST (1UL << 18) /*!< Timer reset event coming solely from software forces the output
+ to its active state */
+#define HRPWM_OUTPUT_SET_RESYNC (1UL << 17) /*!< SYNC input forces the output to its active state */
+#define HRPWM_OUTPUT_SET_EXTEVNT5 (1UL << 16) /*!< External event 5 forces the output to its active state */
+#define HRPWM_OUTPUT_SET_EXTEVNT4 (1UL << 15) /*!< External event 4 forces the output to its active state */
+#define HRPWM_OUTPUT_SET_EXTEVNT3 (1UL << 14) /*!< External event 3 forces the output to its active state */
+#define HRPWM_OUTPUT_SET_EXTEVNT2 (1UL << 13) /*!< External event 2 forces the output to its active state */
+#define HRPWM_OUTPUT_SET_EXTEVNT1 (1UL << 12) /*!< External event 1 forces the output to its active state */
+#define HRPWM_OUTPUT_SET_EXTEVNT0 (1UL << 11) /*!< External event 0 forces the output to its active state */
+#define HRPWM_OUTPUT_SET_MSTPRD (1UL << 10) /*!< The master timer period event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_MSTCMPD (1UL << 9) /*!< Master Timer compare D event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_MSTCMPC (1UL << 8) /*!< Master Timer compare C event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_MSTCMPB (1UL << 7) /*!< Master Timer compare B event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_MSTCMPA (1UL << 6) /*!< Master Timer compare A event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_PRD (1UL << 5) /*!< Timer period event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_CMPD (1UL << 4) /*!< Timer compare D event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_CMPC (1UL << 3) /*!< Timer compare C event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_CMPB (1UL << 2) /*!< Timer compare B event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_CMPA (1UL << 1) /*!< Timer compare A event forces the output to its active state */
+#define HRPWM_OUTPUT_SET_UPDATE (1UL << 0) /*!< Timer register update event forces the output to its active state */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Clear_Trigger HRPWM Output Clear A\B Source
+ * @brief Constants defining the events that can be selected to configure the clear crossbar of a timer output
+ * @{
+ */
+#define HRPWM_OUTPUT_CLEAR_NONE (0x00000000U) /*!< HRPWM output clear None */
+#define HRPWM_OUTPUT_CLEAR_SST (1UL << 18) /*!< Timer reset event coming solely from software forces the output
+ to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_RESYNC (1UL << 17) /*!< SYNC input forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_EXTEVNT5 (1UL << 16) /*!< External event 5 forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_EXTEVNT4 (1UL << 15) /*!< External event 4 forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_EXTEVNT3 (1UL << 14) /*!< External event 3 forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_EXTEVNT2 (1UL << 13) /*!< External event 2 forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_EXTEVNT1 (1UL << 12) /*!< External event 1 forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_EXTEVNT0 (1UL << 11) /*!< External event 0 forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_MSTPRD (1UL << 10) /*!< The master timer period event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_MSTCMPD (1UL << 9) /*!< Master Timer compare D event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_MSTCMPC (1UL << 8) /*!< Master Timer compare C event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_MSTCMPB (1UL << 7) /*!< Master Timer compare B event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_MSTCMPA (1UL << 6) /*!< Master Timer compare A event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_PRD (1UL << 5) /*!< Timer period event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_CMPD (1UL << 4) /*!< Timer compare D event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_CMPC (1UL << 3) /*!< Timer compare C event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_CMPB (1UL << 2) /*!< Timer compare B event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_CMPA (1UL << 1) /*!< Timer compare A event forces the output to its inactive state */
+#define HRPWM_OUTPUT_CLEAR_UPDATE (1UL << 0) /*!< Timer register update event forces the output to its inactive state */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Reset_Trigger HRPWM Timer Reset Trigger
+ * @brief Constants defining the events that can be selected to trigger the reset of the timer counter
+ * @{
+ */
+#define HRPWM_RESET_TRIGGER_NONE 0x00000000U /*!< No counter reset trigger */
+#define HRPWM_RESET_TRIGGER_EXTEVT5 (HRPWM_RSTR_EXTEVT5) /*!< The timer counter is reset upon external event 5 */
+#define HRPWM_RESET_TRIGGER_EXTEVT4 (HRPWM_RSTR_EXTEVT4) /*!< The timer counter is reset upon external event 4 */
+#define HRPWM_RESET_TRIGGER_EXTEVT3 (HRPWM_RSTR_EXTEVT3) /*!< The timer counter is reset upon external event 3 */
+#define HRPWM_RESET_TRIGGER_UPD_CMPA5 (HRPWM_RSTR_UPD_CMPA5) /*!< The timer counter is reset upon other timer 5 update and Compare A event */
+#define HRPWM_RESET_TRIGGER_CMPD4 (HRPWM_RSTR_CMPD4 ) /*!< The timer counter is reset upon other timer 4 Compare D event */
+#define HRPWM_RESET_TRIGGER_CMPB4 (HRPWM_RSTR_CMPB4 ) /*!< The timer counter is reset upon other timer 4 Compare B event */
+#define HRPWM_RESET_TRIGGER_UPD_CMPA4 (HRPWM_RSTR_UPD_CMPA4) /*!< The timer counter is reset upon other timer 4 update and Compare A event */
+#define HRPWM_RESET_TRIGGER_CMPD3 (HRPWM_RSTR_CMPD3 ) /*!< The timer counter is reset upon other timer 3 Compare D event */
+#define HRPWM_RESET_TRIGGER_CMPB3 (HRPWM_RSTR_CMPB3 ) /*!< The timer counter is reset upon other timer 3 Compare B event */
+#define HRPWM_RESET_TRIGGER_UPD_CMPA3 (HRPWM_RSTR_UPD_CMPA3) /*!< The timer counter is reset upon other timer 3 update and Compare A event */
+#define HRPWM_RESET_TRIGGER_CMPD2 (HRPWM_RSTR_CMPD2 ) /*!< The timer counter is reset upon other timer 2 Compare D event */
+#define HRPWM_RESET_TRIGGER_CMPB2 (HRPWM_RSTR_CMPB2 ) /*!< The timer counter is reset upon other timer 2 Compare B event */
+#define HRPWM_RESET_TRIGGER_UPD_CMPA2 (HRPWM_RSTR_UPD_CMPA2) /*!< The timer counter is reset upon other timer 2 update and Compare A event */
+#define HRPWM_RESET_TRIGGER_CMPD1 (HRPWM_RSTR_CMPD1 ) /*!< The timer counter is reset upon other timer 1 Compare D event */
+#define HRPWM_RESET_TRIGGER_CMPB1 (HRPWM_RSTR_CMPB1 ) /*!< The timer counter is reset upon other timer 1 Compare B event */
+#define HRPWM_RESET_TRIGGER_UPD_CMPA1 (HRPWM_RSTR_UPD_CMPA1) /*!< The timer counter is reset upon other timer 1 update and Compare A event */
+#define HRPWM_RESET_TRIGGER_CMPD0 (HRPWM_RSTR_CMPD0 ) /*!< The timer counter is reset upon other timer 0 Compare D event */
+#define HRPWM_RESET_TRIGGER_CMPB0 (HRPWM_RSTR_CMPB0 ) /*!< The timer counter is reset upon other timer 0 Compare B event */
+#define HRPWM_RESET_TRIGGER_UPD_CMPA0 (HRPWM_RSTR_UPD_CMPA0) /*!< The timer counter is reset upon other timer 0 update and Compare A event */
+#define HRPWM_RESET_TRIGGER_CMPD5 (HRPWM_RSTR_CMPD5 ) /*!< The timer counter is reset upon other timer 5 Compare D event */
+#define HRPWM_RESET_TRIGGER_CMPB5 (HRPWM_RSTR_CMPB5 ) /*!< The timer counter is reset upon other timer 5 Compare B event */
+#define HRPWM_RESET_TRIGGER_EXTEVT2 (HRPWM_RSTR_EXTEVT2 ) /*!< The timer counter is reset upon external event 2 */
+#define HRPWM_RESET_TRIGGER_EXTEVT1 (HRPWM_RSTR_EXTEVT1 ) /*!< The timer counter is reset upon external event 1 */
+#define HRPWM_RESET_TRIGGER_EXTEVT0 (HRPWM_RSTR_EXTEVT0 ) /*!< The timer counter is reset upon external event 0 */
+#define HRPWM_RESET_TRIGGER_MSTPER (HRPWM_RSTR_MSTPER ) /*!< The timer counter is reset upon master timer period event */
+#define HRPWM_RESET_TRIGGER_MSTCMPD (HRPWM_RSTR_MSTCMPD ) /*!< The timer counter is reset upon master timer Compare 1 event */
+#define HRPWM_RESET_TRIGGER_MSTCMPC (HRPWM_RSTR_MSTCMPC ) /*!< The timer counter is reset upon master timer Compare 2 event */
+#define HRPWM_RESET_TRIGGER_MSTCMPB (HRPWM_RSTR_MSTCMPB ) /*!< The timer counter is reset upon master timer Compare 3 event */
+#define HRPWM_RESET_TRIGGER_MSTCMPA (HRPWM_RSTR_MSTCMPA ) /*!< The timer counter is reset upon master timer Compare 4 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Fault_Enabling HRPWM Timer Fault Enabling
+ * @brief Constants defining whether a fault channel is enabled for a timer
+ * @{
+ */
+#define HRPWM_FAULTEN_NONE 0x00000000U /*!< No fault enabled */
+#define HRPWM_FAULTEN_FAULT0 (HRPWM_FLTR_FLT0EN) /*!< Fault 0 enabled */
+#define HRPWM_FAULTEN_FAULT1 (HRPWM_FLTR_FLT1EN) /*!< Fault 1 enabled */
+#define HRPWM_FAULTEN_FAULT2 (HRPWM_FLTR_FLT2EN) /*!< Fault 2 enabled */
+#define HRPWM_FAULTEN_FAULT3 (HRPWM_FLTR_FLT3EN) /*!< Fault 3 enabled */
+#define HRPWM_FAULTEN_FAULT4 (HRPWM_FLTR_FLT4EN) /*!< Fault 4 enabled */
+#define HRPWM_FAULTEN_FAULT5 (HRPWM_FLTR_FLT5EN) /*!< Fault 5 enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_ADC_Trigger_Event HRPWM ADC Trigger Event
+ * @brief constants defining the events triggering ADC conversion.
+ * HRPWM_ADCTRIGEVENT0246*: ADC Triggers 0 and 2 and 4 and 6
+ * HRPWM_ADCTRIGEVENT1357_*: ADC Triggers 1 and 3 and 5 and 7
+ * @{
+ */
+#define HRPWM_ADCTRIGEVENT0_CMPD5 (HRPWM_ADT0R_CMPD5) /*!< ADC Trigger on Slave Timer 5 compare D */
+#define HRPWM_ADCTRIGEVENT0_CMPC5 (HRPWM_ADT0R_CMPC5) /*!< ADC Trigger on Slave Timer 5 compare C */
+#define HRPWM_ADCTRIGEVENT0_PER4 (HRPWM_ADT0R_PER4) /*!< ADC Trigger on Slave Timer 4 period */
+#define HRPWM_ADCTRIGEVENT0_CMPD4 (HRPWM_ADT0R_CMPD4) /*!< ADC Trigger on Slave Timer 4 compare D */
+#define HRPWM_ADCTRIGEVENT0_CMPC4 (HRPWM_ADT0R_CMPC4) /*!< ADC Trigger on Slave Timer 4 compare C */
+#define HRPWM_ADCTRIGEVENT0_CMPB4 (HRPWM_ADT0R_CMPB4) /*!< ADC Trigger on Slave Timer 4 compare B */
+#define HRPWM_ADCTRIGEVENT0_RST3 (HRPWM_ADT0R_RST3) /*!< ADC Trigger on Slave Timer 3 reset */
+#define HRPWM_ADCTRIGEVENT0_CMPD3 (HRPWM_ADT0R_CMPD3) /*!< ADC Trigger on Slave Timer 3 compare D */
+#define HRPWM_ADCTRIGEVENT0_CMPC3 (HRPWM_ADT0R_CMPC3) /*!< ADC Trigger on Slave Timer 3 compare C */
+#define HRPWM_ADCTRIGEVENT0_CMPB3 (HRPWM_ADT0R_CMPB3) /*!< ADC Trigger on Slave Timer 3 compare B */
+#define HRPWM_ADCTRIGEVENT0_PER2 (HRPWM_ADT0R_PER2) /*!< ADC Trigger on Slave Timer 2 period */
+#define HRPWM_ADCTRIGEVENT0_CMPD2 (HRPWM_ADT0R_CMPD2) /*!< ADC Trigger on Slave Timer 2 compare D */
+#define HRPWM_ADCTRIGEVENT0_CMPC2 (HRPWM_ADT0R_CMPC2) /*!< ADC Trigger on Slave Timer 2 compare C */
+#define HRPWM_ADCTRIGEVENT0_CMPB2 (HRPWM_ADT0R_CMPB2) /*!< ADC Trigger on Slave Timer 2 compare B */
+#define HRPWM_ADCTRIGEVENT0_RST1 (HRPWM_ADT0R_RST1) /*!< ADC Trigger on Slave Timer 1 reset */
+#define HRPWM_ADCTRIGEVENT0_CMPD1 (HRPWM_ADT0R_CMPD1) /*!< ADC Trigger on Slave Timer 1 compare D */
+#define HRPWM_ADCTRIGEVENT0_CMPC1 (HRPWM_ADT0R_CMPC1) /*!< ADC Trigger on Slave Timer 1 compare C */
+#define HRPWM_ADCTRIGEVENT0_CMPB1 (HRPWM_ADT0R_CMPB1) /*!< ADC Trigger on Slave Timer 1 compare B */
+#define HRPWM_ADCTRIGEVENT0_PER0 (HRPWM_ADT0R_PER0) /*!< ADC Trigger on Slave Timer 0 period */
+#define HRPWM_ADCTRIGEVENT0_CMPD0 (HRPWM_ADT0R_CMPD0) /*!< ADC Trigger on Slave Timer 0 compare D */
+#define HRPWM_ADCTRIGEVENT0_CMPC0 (HRPWM_ADT0R_CMPC0) /*!< ADC Trigger on Slave Timer 0 compare C */
+#define HRPWM_ADCTRIGEVENT0_CMPB0 (HRPWM_ADT0R_CMPB0) /*!< ADC Trigger on Slave Timer 0 compare B */
+#define HRPWM_ADCTRIGEVENT0_RST5 (HRPWM_ADT0R_RST5) /*!< ADC Trigger on Slave Timer 5 reset */
+#define HRPWM_ADCTRIGEVENT0_CMPB5 (HRPWM_ADT0R_CMPB5) /*!< ADC Trigger on Slave Timer 5 compare B */
+#define HRPWM_ADCTRIGEVENT0_EEV2 (HRPWM_ADT0R_EEV2) /*!< ADC Trigger on external event 2 */
+#define HRPWM_ADCTRIGEVENT0_EEV1 (HRPWM_ADT0R_EEV1) /*!< ADC Trigger on external event 1 */
+#define HRPWM_ADCTRIGEVENT0_EEV0 (HRPWM_ADT0R_EEV0) /*!< ADC Trigger on external event 0 */
+#define HRPWM_ADCTRIGEVENT0_MPER (HRPWM_ADT0R_MPER) /*!< ADC Trigger on Master Timer period */
+#define HRPWM_ADCTRIGEVENT0_MCMPD (HRPWM_ADT0R_MCMPD) /*!< ADC Trigger on Master Timer compare D */
+#define HRPWM_ADCTRIGEVENT0_MCMPC (HRPWM_ADT0R_MCMPC) /*!< ADC Trigger on Master Timer compare C */
+#define HRPWM_ADCTRIGEVENT0_MCMPB (HRPWM_ADT0R_MCMPB) /*!< ADC Trigger on Master Timer compare B */
+#define HRPWM_ADCTRIGEVENT0_MCMPA (HRPWM_ADT0R_MCMPA) /*!< ADC Trigger on Master Timer compare A */
+
+#define HRPWM_ADCTRIGEVENT1_CMPD5 (HRPWM_ADT1R_CMPD5) /*!< ADC Trigger on Slave Timer 5 compare D */
+#define HRPWM_ADCTRIGEVENT1_CMPC5 (HRPWM_ADT1R_CMPC5) /*!< ADC Trigger on Slave Timer 5 compare C */
+#define HRPWM_ADCTRIGEVENT1_RST4 (HRPWM_ADT1R_RST4) /*!< ADC Trigger on Slave Timer 4 reset */
+#define HRPWM_ADCTRIGEVENT1_CMPD4 (HRPWM_ADT1R_CMPD4) /*!< ADC Trigger on Slave Timer 4 compare D */
+#define HRPWM_ADCTRIGEVENT1_CMPC4 (HRPWM_ADT1R_CMPC4) /*!< ADC Trigger on Slave Timer 4 compare C */
+#define HRPWM_ADCTRIGEVENT1_CMPB4 (HRPWM_ADT1R_CMPB4) /*!< ADC Trigger on Slave Timer 4 compare B */
+#define HRPWM_ADCTRIGEVENT1_PER3 (HRPWM_ADT1R_PER3) /*!< ADC Trigger on Slave Timer 3 period */
+#define HRPWM_ADCTRIGEVENT1_CMPD3 (HRPWM_ADT1R_CMPD3) /*!< ADC Trigger on Slave Timer 3 compare D */
+#define HRPWM_ADCTRIGEVENT1_CMPC3 (HRPWM_ADT1R_CMPC3) /*!< ADC Trigger on Slave Timer 3 compare C */
+#define HRPWM_ADCTRIGEVENT1_CMPB3 (HRPWM_ADT1R_CMPB3) /*!< ADC Trigger on Slave Timer 3 compare B */
+#define HRPWM_ADCTRIGEVENT1_RST2 (HRPWM_ADT1R_RST2) /*!< ADC Trigger on Slave Timer 2 reset */
+#define HRPWM_ADCTRIGEVENT1_CMPD2 (HRPWM_ADT1R_CMPD2) /*!< ADC Trigger on Slave Timer 2 compare D */
+#define HRPWM_ADCTRIGEVENT1_CMPC2 (HRPWM_ADT1R_CMPC2) /*!< ADC Trigger on Slave Timer 2 compare C */
+#define HRPWM_ADCTRIGEVENT1_CMPB2 (HRPWM_ADT1R_CMPB2) /*!< ADC Trigger on Slave Timer 2 compare B */
+#define HRPWM_ADCTRIGEVENT1_PER1 (HRPWM_ADT1R_PER1) /*!< ADC Trigger on Slave Timer 1 period */
+#define HRPWM_ADCTRIGEVENT1_CMPD1 (HRPWM_ADT1R_CMPD1) /*!< ADC Trigger on Slave Timer 1 compare D */
+#define HRPWM_ADCTRIGEVENT1_CMPC1 (HRPWM_ADT1R_CMPC1) /*!< ADC Trigger on Slave Timer 1 compare C */
+#define HRPWM_ADCTRIGEVENT1_CMPB1 (HRPWM_ADT1R_CMPB1) /*!< ADC Trigger on Slave Timer 1 compare B */
+#define HRPWM_ADCTRIGEVENT1_RST0 (HRPWM_ADT1R_RST0) /*!< ADC Trigger on Slave Timer 0 reset */
+#define HRPWM_ADCTRIGEVENT1_CMPD0 (HRPWM_ADT1R_CMPD0) /*!< ADC Trigger on Slave Timer 0 compare D */
+#define HRPWM_ADCTRIGEVENT1_CMPC0 (HRPWM_ADT1R_CMPC0) /*!< ADC Trigger on Slave Timer 0 compare C */
+#define HRPWM_ADCTRIGEVENT1_CMPB0 (HRPWM_ADT1R_CMPB0) /*!< ADC Trigger on Slave Timer 0 compare B */
+#define HRPWM_ADCTRIGEVENT1_PER5 (HRPWM_ADT1R_PER5) /*!< ADC Trigger on Slave Timer 5 period */
+#define HRPWM_ADCTRIGEVENT1_CMPB5 (HRPWM_ADT1R_CMPB5) /*!< ADC Trigger on Slave Timer 5 compare B */
+#define HRPWM_ADCTRIGEVENT1_EEV2 (HRPWM_ADT1R_EEV5) /*!< ADC Trigger on external event 2 */
+#define HRPWM_ADCTRIGEVENT1_EEV1 (HRPWM_ADT1R_EEV4) /*!< ADC Trigger on external event 1 */
+#define HRPWM_ADCTRIGEVENT1_EEV0 (HRPWM_ADT1R_EEV3) /*!< ADC Trigger on external event 0 */
+#define HRPWM_ADCTRIGEVENT1_MPER (HRPWM_ADT1R_MPER) /*!< ADC Trigger on Master Timer period */
+#define HRPWM_ADCTRIGEVENT1_MCMPD (HRPWM_ADT1R_MCMPD) /*!< ADC Trigger on Master Timer compare D */
+#define HRPWM_ADCTRIGEVENT1_MCMPC (HRPWM_ADT1R_MCMPC) /*!< ADC Trigger on Master Timer compare C */
+#define HRPWM_ADCTRIGEVENT1_MCMPB (HRPWM_ADT1R_MCMPB) /*!< ADC Trigger on Master Timer compare B */
+#define HRPWM_ADCTRIGEVENT1_MCMPA (HRPWM_ADT1R_MCMPA) /*!< ADC Trigger on Master Timer compare A */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Software_Timer_Update HRPWM Software Timer Update
+ * @brief Constants used to force timer registers update
+ * @{
+ */
+#define HRPWM_UPDATE_MASTER (HRPWM_CR1_MSWU)/*!< Force an immediate transfer from the preload to the active register in the master timer */
+#define HRPWM_UPDATE_SLAVE_0 (HRPWM_CR1_SWU0)/*!< Force an immediate transfer from the preload to the active register in the slave timer 0 */
+#define HRPWM_UPDATE_SLAVE_1 (HRPWM_CR1_SWU1)/*!< Force an immediate transfer from the preload to the active register in the slave timer 1 */
+#define HRPWM_UPDATE_SLAVE_2 (HRPWM_CR1_SWU2)/*!< Force an immediate transfer from the preload to the active register in the slave timer 2 */
+#define HRPWM_UPDATE_SLAVE_3 (HRPWM_CR1_SWU3)/*!< Force an immediate transfer from the preload to the active register in the slave timer 3 */
+#define HRPWM_UPDATE_SLAVE_4 (HRPWM_CR1_SWU4)/*!< Force an immediate transfer from the preload to the active register in the slave timer 4 */
+#define HRPWM_UPDATE_SLAVE_5 (HRPWM_CR1_SWU5)/*!< Force an immediate transfer from the preload to the active register in the slave timer 5 */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Software_Timer_SwapOutput HRPWM Software Timer swap Output
+ * @brief Constants used to swap the output of the timer registers
+ * @{
+ */
+#define HRPWM_SWAP_SLAVE_0 (HRPWM_CR1_SWP0) /*!< Swap the output of the slave Timer 0 */
+#define HRPWM_SWAP_SLAVE_1 (HRPWM_CR1_SWP1) /*!< Swap the output of the slave Timer 1 */
+#define HRPWM_SWAP_SLAVE_2 (HRPWM_CR1_SWP2) /*!< Swap the output of the slave Timer 2 */
+#define HRPWM_SWAP_SLAVE_3 (HRPWM_CR1_SWP3) /*!< Swap the output of the slave Timer 3 */
+#define HRPWM_SWAP_SLAVE_4 (HRPWM_CR1_SWP4) /*!< Swap the output of the slave Timer 4 */
+#define HRPWM_SWAP_SLAVE_5 (HRPWM_CR1_SWP5) /*!< Swap the output of the slave Timer 5 */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Software_Timer_Reset HRPWM Software Timer Reset
+ * @brief Constants used to force timer counter reset
+ * @{
+ */
+#define HRPWM_RESET_MASTER (HRPWM_CR1_MRST) /*!< Reset the master timer counter */
+#define HRPWM_RESET_SLAVE_0 (HRPWM_CR1_RST0) /*!< Reset the slave timer 0 counter */
+#define HRPWM_RESET_SLAVE_1 (HRPWM_CR1_RST1) /*!< Reset the slave timer 1 counter */
+#define HRPWM_RESET_SLAVE_2 (HRPWM_CR1_RST2) /*!< Reset the slave timer 2 counter */
+#define HRPWM_RESET_SLAVE_3 (HRPWM_CR1_RST3) /*!< Reset the slave timer 3 counter */
+#define HRPWM_RESET_SLAVE_4 (HRPWM_CR1_RST4) /*!< Reset the slave timer 4 counter */
+#define HRPWM_RESET_SLAVE_5 (HRPWM_CR1_RST5) /*!< Reset the slave timer 5 counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Software_Timer_Update_Disable HRPWM Software Timer Update Disable
+ * @brief Constants used to force timer counter Update Disable
+ * @{
+ */
+#define HRPWM_UPDISABLE_MASTER (HRPWM_CR0_MUDIS) /*!< Update Disable the master timer counter */
+#define HRPWM_UPDISABLE_SLAVE_0 (HRPWM_CR0_UDIS0) /*!< Update Disable the slave timer 0 counter */
+#define HRPWM_UPDISABLE_SLAVE_1 (HRPWM_CR0_UDIS1) /*!< Update Disable the slave timer 1 counter */
+#define HRPWM_UPDISABLE_SLAVE_2 (HRPWM_CR0_UDIS2) /*!< Update Disable the slave timer 2 counter */
+#define HRPWM_UPDISABLE_SLAVE_3 (HRPWM_CR0_UDIS3) /*!< Update Disable the slave timer 3 counter */
+#define HRPWM_UPDISABLE_SLAVE_4 (HRPWM_CR0_UDIS4) /*!< Update Disable the slave timer 4 counter */
+#define HRPWM_UPDISABLE_SLAVE_5 (HRPWM_CR0_UDIS5) /*!< Update Disable the slave timer 5 counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Software_forced_update HRPWM Software forced update
+ * @brief Constants used to force timer counter Software forced update
+ * @{
+ */
+#define HRPWM_SOFT_UPDATE_MASTER (HRPWM_CR1_MSWU) /*!< Update Disable the master timer counter */
+#define HRPWM_SOFT_UPDATE_SLAVE_0 (HRPWM_CR1_SWU0) /*!< Update Disable the slave timer 0 counter */
+#define HRPWM_SOFT_UPDATE_SLAVE_1 (HRPWM_CR1_SWU1) /*!< Update Disable the slave timer 1 counter */
+#define HRPWM_SOFT_UPDATE_SLAVE_2 (HRPWM_CR1_SWU2) /*!< Update Disable the slave timer 2 counter */
+#define HRPWM_SOFT_UPDATE_SLAVE_3 (HRPWM_CR1_SWU3) /*!< Update Disable the slave timer 3 counter */
+#define HRPWM_SOFT_UPDATE_SLAVE_4 (HRPWM_CR1_SWU4) /*!< Update Disable the slave timer 4 counter */
+#define HRPWM_SOFT_UPDATE_SLAVE_5 (HRPWM_CR1_SWU5) /*!< Update Disable the slave timer 5 counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Output_State HRPWM Output State
+ * @brief Constants defining the state of a timer output
+ * @{
+ */
+#define HRPWM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
+ inactive level as programmed in the crossbar unit */
+#define HRPWM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRPWM reset, when the
+ outputs are disabled by software or during a burst mode operation */
+#define HRPWM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
+ FAULTx inputs */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Common_Interrupt_Enable HRPWM Common Interrupt Enable
+ * @{
+ */
+#define HRPWM_IT_SRC (0x0000003FU)
+#define HRPWM_IT_NONE (0x00000000U) /*!< No interrupt enabled */
+#define HRPWM_IT_FLT0 HRPWM_IER_FLT0IE /*!< Fault 0 interrupt enable */
+#define HRPWM_IT_FLT1 HRPWM_IER_FLT1IE /*!< Fault 1 interrupt enable */
+#define HRPWM_IT_FLT2 HRPWM_IER_FLT2IE /*!< Fault 2 interrupt enable */
+#define HRPWM_IT_FLT3 HRPWM_IER_FLT3IE /*!< Fault 3 interrupt enable */
+#define HRPWM_IT_FLT4 HRPWM_IER_FLT4IE /*!< Fault 4 interrupt enable */
+#define HRPWM_IT_FLT5 HRPWM_IER_FLT5IE /*!< Fault 5 interrupt enable */
+#define HRPWM_IT_SYSFLT HRPWM_IER_SYSFLTIE /*!< System Fault interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Common_Interrupt_Flag HRPWM Common Interrupt Flag
+ * @{
+ */
+#define HRPWM_FLAG_FLT0 HRPWM_ISR_FLT0 /*!< Fault 0 interrupt flag */
+#define HRPWM_FLAG_FLT1 HRPWM_ISR_FLT1 /*!< Fault 1 interrupt flag */
+#define HRPWM_FLAG_FLT2 HRPWM_ISR_FLT2 /*!< Fault 2 interrupt flag */
+#define HRPWM_FLAG_FLT3 HRPWM_ISR_FLT3 /*!< Fault 3 interrupt flag */
+#define HRPWM_FLAG_FLT4 HRPWM_ISR_FLT4 /*!< Fault 4 interrupt flag */
+#define HRPWM_FLAG_FLT5 HRPWM_ISR_FLT5 /*!< Fault 5 interrupt flag */
+#define HRPWM_FLAG_SYSFLT HRPWM_ISR_SYSFLT /*!< System Fault interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Master_Interrupt_Enable HRPWM Master Interrupt Enable
+ * @{
+ */
+#define HRPWM_MASTER_IT_SRC 0x000000FFU /*!< ALL interrupt enabled */
+#define HRPWM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */
+#define HRPWM_MASTER_IT_MCMPA HRPWM_MIER_MCMPAIE /*!< Master compare A interrupt enable */
+#define HRPWM_MASTER_IT_MCMPB HRPWM_MIER_MCMPBIE /*!< Master compare B interrupt enable */
+#define HRPWM_MASTER_IT_MCMPC HRPWM_MIER_MCMPCIE /*!< Master compare C interrupt enable */
+#define HRPWM_MASTER_IT_MCMPD HRPWM_MIER_MCMPDIE /*!< Master compare D interrupt enable */
+#define HRPWM_MASTER_IT_MPER HRPWM_MIER_MPERIE /*!< Master Period interrupt enable */
+#define HRPWM_MASTER_IT_SYNC HRPWM_MIER_SYNCIE /*!< Synchronization input interrupt enable */
+#define HRPWM_MASTER_IT_MUPD HRPWM_MIER_MUPDIE /*!< Master update interrupt enable */
+#define HRPWM_MASTER_IT_MREP HRPWM_MIER_MREPIE /*!< Master Repetition interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Master_Interrupt_Flag HRPWM Master Interrupt flag
+ * @{
+ */
+#define HRPWM_MASTER_FLAG_NONE 0x00000000U /*!< No interrupt flag */
+#define HRPWM_MASTER_FLAG_MCMPA HRPWM_MISR_MCMPA /*!< Master compare A interrupt flag */
+#define HRPWM_MASTER_FLAG_MCMPB HRPWM_MISR_MCMPB /*!< Master compare B interrupt flag */
+#define HRPWM_MASTER_FLAG_MCMPC HRPWM_MISR_MCMPC /*!< Master compare C interrupt flag */
+#define HRPWM_MASTER_FLAG_MCMPD HRPWM_MISR_MCMPD /*!< Master compare D interrupt flag */
+#define HRPWM_MASTER_FLAG_MPER HRPWM_MISR_MPER /*!< Master Period interrupt flag */
+#define HRPWM_MASTER_FLAG_SYNC HRPWM_MISR_SYNC /*!< Synchronization input interrupt flag */
+#define HRPWM_MASTER_FLAG_MUPD HRPWM_MISR_MUPD /*!< Master update interrupt flag */
+#define HRPWM_MASTER_FLAG_MREP HRPWM_MISR_MREP /*!< Master Repetition interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Slave_Timer_Unit_Interrupt_Enable HRPWM Timing Unit Interrupt Enable
+ * @{
+ */
+#define HRPWM_IT_TIMER_SRC 0x00000FFFU /*!< ALL interrupt enabled */
+#define HRPWM_IT_TIMER_NONE 0x00000000U /*!< No interrupt enabled */
+#define HRPWM_IT_CMPA HRPWM_IER_CMPAIE /*!< Timer compare A interrupt enable */
+#define HRPWM_IT_CMPB HRPWM_IER_CMPBIE /*!< Timer compare B interrupt enable */
+#define HRPWM_IT_CMPC HRPWM_IER_CMPCIE /*!< Timer compare C interrupt enable */
+#define HRPWM_IT_CMPD HRPWM_IER_CMPDIE /*!< Timer compare D interrupt enable */
+#define HRPWM_IT_PER HRPWM_IER_PERIE /*!< Timer period interrupt enable */
+#define HRPWM_IT_UPD HRPWM_IER_UPDIE /*!< Timer update interrupt enable */
+#define HRPWM_IT_SETA HRPWM_IER_SETAIE /*!< Timer output 1 set interrupt enable */
+#define HRPWM_IT_CLRA HRPWM_IER_CLRAIE /*!< Timer output 1 reset interrupt enable */
+#define HRPWM_IT_SETB HRPWM_IER_SETBIE /*!< Timer output 2 set interrupt enable */
+#define HRPWM_IT_CLRB HRPWM_IER_CLRBIE /*!< Timer output 2 reset interrupt enable */
+#define HRPWM_IT_RST HRPWM_IER_RSTIE /*!< Timer reset interrupt enable */
+#define HRPWM_IT_REP HRPWM_IER_REPIE /*!< Timer repetition interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Slave_Timer_Unit_Interrupt_Flag HRPWM Timing Unit Interrupt Flag
+ * @{
+ */
+#define HRPWM_FLAG_CMPA HRPWM_ISR_CMPA /*!< Timer compare A interrupt flag */
+#define HRPWM_FLAG_CMPB HRPWM_ISR_CMPB /*!< Timer compare B interrupt flag */
+#define HRPWM_FLAG_CMPC HRPWM_ISR_CMPC /*!< Timer compare C interrupt flag */
+#define HRPWM_FLAG_CMPD HRPWM_ISR_CMPD /*!< Timer compare D interrupt flag */
+#define HRPWM_FLAG_PER HRPWM_ISR_PER /*!< Timer period interrupt flag */
+#define HRPWM_FLAG_UPD HRPWM_ISR_UPD /*!< Timer update interrupt flag */
+#define HRPWM_FLAG_SETA HRPWM_ISR_SETA /*!< Timer output 1 set interrupt flag */
+#define HRPWM_FLAG_CLRA HRPWM_ISR_CLRA /*!< Timer output 1 reset interrupt flag */
+#define HRPWM_FLAG_SETB HRPWM_ISR_SETB /*!< Timer output 2 set interrupt flag */
+#define HRPWM_FLAG_CLRB HRPWM_ISR_CLRB /*!< Timer output 2 reset interrupt flag */
+#define HRPWM_FLAG_RST HRPWM_ISR_RST /*!< Timer reset interrupt flag */
+#define HRPWM_FLAG_REP HRPWM_ISR_REP /*!< Timer repetition interrupt flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HRPWM_LL_Exported_Types HRPWM LL Exported Types
+ * @brief HRPWM LL Exported Types
+ * @{
+ */
+
+/** @defgroup HRPWM_DLL_CURRENT HRPWM DLL CURRENT
+ * @brief Constants defining dll current identifiers
+ * @{
+ */
+typedef enum {
+ HRPWM_DLLCR_DLLGCP_4 = 0x0, /*!< DLL current selector bit: 4uA */
+ HRPWM_DLLCR_DLLGCP_6 = HRPWM_DLLCR_DLLGCP_0, /*!< DLL current selector bit: 6uA */
+ HRPWM_DLLCR_DLLGCP_8 = HRPWM_DLLCR_DLLGCP_1 | HRPWM_DLLCR_DLLGCP_0, /*!< DLL current selector bit: 8uA */
+} HRPWM_DllCurrentETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_ADC_Trigger HRPWM ADC Trigger
+ * @brief Constants defining ADC triggers identifiers
+ * @{
+ */
+typedef enum {
+ HRPWM_ADCTRIGGER_0 = 0x0U, /*!< ADC trigger 0 identifier */
+ HRPWM_ADCTRIGGER_1 = 0x1U, /*!< ADC trigger 1 identifier */
+ HRPWM_ADCTRIGGER_2 = 0x2U, /*!< ADC trigger 2 identifier */
+ HRPWM_ADCTRIGGER_3 = 0x3U, /*!< ADC trigger 3 identifier */
+ HRPWM_ADCTRIGGER_4 = 0x4U, /*!< ADC trigger 4 identifier */
+ HRPWM_ADCTRIGGER_5 = 0x5U, /*!< ADC trigger 5 identifier */
+ HRPWM_ADCTRIGGER_6 = 0x6U, /*!< ADC trigger 6 identifier */
+ HRPWM_ADCTRIGGER_7 = 0x7U, /*!< ADC trigger 7 identifier */
+} HRPWM_AdcTrigGroupETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Channels HRPWM External Event Channels
+ * @brief Constants defining external event channel identifiers
+ * @{
+ */
+typedef enum {
+ HRPWM_EVENT_NONE = 0x6U, /*!< None Event */
+ HRPWM_EVENT_0 = 0x0U, /*!< External event channel 0 identifier */
+ HRPWM_EVENT_1 = 0x1U, /*!< External event channel 1 identifier */
+ HRPWM_EVENT_2 = 0x2U, /*!< External event channel 2 identifier */
+ HRPWM_EVENT_3 = 0x3U, /*!< External event channel 3 identifier */
+ HRPWM_EVENT_4 = 0x4U, /*!< External event channel 4 identifier */
+ HRPWM_EVENT_5 = 0x5U, /*!< External event channel 5 identifier */
+} HRPWM_EventSelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Channel HRPWM Fault Channel
+ * @brief Constants defining fault channel identifiers
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULT_0 = 0x00U, /*!< Fault channel 0 identifier */
+ HRPWM_FAULT_1 = 0x01U, /*!< Fault channel 1 identifier */
+ HRPWM_FAULT_2 = 0x02U, /*!< Fault channel 2 identifier */
+ HRPWM_FAULT_3 = 0x03U, /*!< Fault channel 3 identifier */
+ HRPWM_FAULT_4 = 0x04U, /*!< Fault channel 4 identifier */
+ HRPWM_FAULT_5 = 0x05U, /*!< Fault channel 5 identifier */
+ HRPWM_SYSFAULT = 0x06U, /*!< Fault channel 5 identifier */
+} HRPWM_FaultSelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Prescaler_Ratio HRPWM Prescaler Ratio
+ * @brief Constants defining timer high-resolution clock prescaler ratio.
+ * @{
+ */
+typedef enum {
+ HRPWM_PRESCALERRATIO_MUL32 = 0x0U, /*!< fHRCK: fHRPWM x 32U = 5.12 GHz - Resolution: 195 ps */
+ HRPWM_PRESCALERRATIO_MUL16 = 0x1U, /*!< fHRCK: fHRPWM x 16U = 2.56 GHz - Resolution: 390 ps */
+ HRPWM_PRESCALERRATIO_MUL8 = 0x2U, /*!< fHRCK: fHRPWM x 8U = 1.28 GHz - Resolution: 781 ps */
+ HRPWM_PRESCALERRATIO_MUL4 = 0x3U, /*!< fHRCK: fHRPWM x 4U = 640 MHz - Resolution: 1.56 ns */
+ HRPWM_PRESCALERRATIO_MUL2 = 0x4U, /*!< fHRCK: fHRPWM x 2U = 320 MHz - Resolution: 3.125 ns */
+ HRPWM_PRESCALERRATIO_DIV1 = 0x5U, /*!< fHRCK: fHRPWM = 160 MHz - Resolution: 6.25 ns */
+ HRPWM_PRESCALERRATIO_DIV2 = 0x6U, /*!< fHRCK: fHRPWM / 2U = 80 MHz - Resolution: 12.5 ns */
+ HRPWM_PRESCALERRATIO_DIV4 = 0x7U, /*!< fHRCK: fHRPWM / 4U = 40 MHz - Resolution: 25 ns */
+} HRPWM_PrescalerRatioETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Counter_Operating_Mode HRPWM Counter Operating Mode
+ * @brief Constants defining timer counter operating mode.
+ * @{
+ */
+typedef enum {
+ HRPWM_MODE_CONTINUOUS = HRPWM_CR0_CONT, /*!< The timer operates in continuous (free-running) mode */
+ HRPWM_MODE_SINGLESHOT = 0x0, /*!< The timer operates in non retriggerable single-shot mode */
+ HRPWM_MODE_SINGLESHOT_RETRIGGERABLE = HRPWM_CR0_RETRIG, /*!< The timer operates in retriggerable single-shot mode */
+} HRPWM_ModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Half_Mode_Enable HRPWM Half Mode Enable
+ * @brief Constants defining half mode enabling status.
+ * @{
+ */
+typedef enum {
+ HRPWM_HALFMODE_DISABLE = 0x0, /*!< Half mode is disabled */
+ HRPWM_HALFMODE_ENABLE = HRPWM_CR0_HALF, /*!< Half mode is enabled */
+} HRPWM_HalfModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Interleaved_Mode HRPWM Interleaved Mode
+ * @brief Constants defining interleaved mode enabling status.
+ * @{
+ */
+typedef enum {
+ HRPWM_INTERLEAVED_MODE_DISABLE = 0x0, /*!< HRPWM interleaved Mode is disabled */
+ HRPWM_INTERLEAVED_MODE_TRIPLE = HRPWM_CR0_INTLVD_0, /*!< HRPWM interleaved Mode is Triple */
+ HRPWM_INTERLEAVED_MODE_QUAD = HRPWM_CR0_INTLVD_1, /*!< HRPWM interleaved Mode is Quad */
+} HRPWM_InterleavedModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Push_Pull_Mode HRPWM Timer Push Pull Mode
+ * @brief Constants defining whether or not the push-pull mode is enabled for a timer.
+ * @{
+ */
+typedef enum {
+ HRPWM_PUSHPULLMODE_DISABLE = 0x0, /*!< Push-Pull mode disabled */
+ HRPWM_PUSHPULLMODE_ENABLE = HRPWM_CR0_PSHPLL, /*!< Push-Pull mode enabled */
+} HRPWM_PushpullModeETypeDef;
+
+typedef enum {
+ HRPWM_MODE_NONE = 0, /*!< HRPWM mode none */
+ HRPWM_MODE_HALF = HRPWM_CR0_HALF, /*!< HRPWM mode half */
+ HRPWM_MODE_PUSHPULL = HRPWM_CR0_PSHPLL, /*!< HRPWM mode push pull */
+ HRPWM_MODE_INTERLEAVED_TRIPLE = HRPWM_CR0_INTLVD_0, /*!< HRPWM mode interleaved triple */
+ HRPWM_MODE_INTERLEAVED_QUAD = HRPWM_CR0_INTLVD_1, /*!< HRPWM mode interleaved quad */
+ HRPWM_MODE_HALF_PUSHPULL = HRPWM_CR0_HALF | HRPWM_CR0_PSHPLL, /*!< HRPWM mode half push pull */
+ HRPWM_MODE_HALF_INTERLEAVED_TRIPLE = HRPWM_CR0_HALF | HRPWM_CR0_INTLVD_0, /*!< HRPWM mode half interleaved triple */
+ HRPWM_MODE_HALF_INTERLEAVED_QUAD = HRPWM_CR0_HALF | HRPWM_CR0_INTLVD_1, /*!< HRPWM mode half interleaved quad */
+ HRPWM_MODE_PUSHPULL_INTERLEAVED_TRIPLE = HRPWM_CR0_PSHPLL | HRPWM_CR0_INTLVD_0, /*!< HRPWM mode push pull interleaved triple*/
+ HRPWM_MODE_PUSHPULL_INTERLEAVED_QUAD = HRPWM_CR0_PSHPLL | HRPWM_CR0_INTLVD_1, /*!< HRPWM mode push pull interleaved quad */
+} HRPWM_OutputModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Start_On_Sync_Input_Event HRPWM Start On Sync Input Event
+ * @brief Constants defining the timer behavior following the synchronization event
+ * @{
+ */
+typedef enum {
+ HRPWM_SYNCSTART_DISABLE = 0x0, /*!< Synchronization input event has effect on the timer */
+ HRPWM_SYNCSTART_ENABLE = HRPWM_CR0_SYNCSTRT, /*!< Synchronization input event starts the timer */
+} HRPWM_SyncStartETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Reset_On_Sync_Input_Event HRPWM Reset On Sync Input Event
+ * @brief Constants defining the timer behavior following the synchronization event
+ * @{
+ */
+typedef enum {
+ HRPWM_SYNCRESET_DISABLE = 0x0, /*!< Synchronization input event has effect on the timer */
+ HRPWM_SYNCRESET_ENABLE = HRPWM_CR0_SYNCRST, /*!< Synchronization input event resets the timer */
+} HRPWM_SyncResetETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Resync_Update_Enable HRPWM Re-Synchronized Update
+ * @brief Constants defining whether the update source coming outside from the timing unit must be synchronized
+ * @{
+ */
+typedef enum {
+ HRPWM_RSYNCUPDATE_DISABLE = 0x0, /*!< The update is taken into account immediately */
+ HRPWM_RSYNCUPDATE_ENABLE = HRPWM_CR0_RSYNCU, /*!< The update is taken into account on the following Reset/Roll-over event*/
+} HRPWM_RsyncUpdateETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Register_Preload_Enable HRPWM Register Preload Enable
+ * @brief Constants defining whether a write access into a preloadable
+ * register is done into the active or the preload register.
+ * @{
+ */
+typedef enum {
+ HRPWM_PRELOAD_DISABLE = 0x0, /*!< Preload disabled: the write access is directly done into the active register */
+ HRPWM_PRELOAD_ENABLE = HRPWM_MCR_PREEN,/*!< Preload enabled: the write access is done into the preload register */
+} HRPWM_PreloadEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Synchronization_Input_Source HRPWM Synchronization Input Source
+ * @brief Constants defining the synchronization input source
+ * @{
+ */
+typedef enum {
+ HRPWM_SYNCINPUTSOURCE_NONE = 0x0, /*!< HRPWM Synchronization Input Source None */
+ HRPWM_SYNCINPUTSOURCE_TIM0_TRGO_EVENT = HRPWM_MCR_SYNCIN_EN, /*!< The HRPWM is synchronized with TIM0_TRGO */
+ HRPWM_SYNCINPUTSOURCE_EVENT = HRPWM_MCR_SYNCIN_SRC | HRPWM_MCR_SYNCIN_EN,
+ /*!< A positive pulse on SYNCIN input triggers the HRPWM */
+} HRPWM_SyncInputSrcETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Synchronization_Output_Source HRPWM Synchronization Output Source
+ * @brief Constants defining the source and event to be sent on the synchronization outputs
+ * @{
+ */
+#define HRPWM_SYNCOUTPUTSOURCE_SRC ( HRPWM_MCR_SYNCOUT_SRC_1 | HRPWM_MCR_SYNCOUT_SRC_0)
+typedef enum {
+ HRPWM_SYNCOUTPUTSOURCE_MASTER_START = 0x0,
+ /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
+ HRPWM_SYNCOUTPUTSOURCE_MASTER_CMPA = HRPWM_MCR_SYNCOUT_SRC_0,
+ /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event */
+ HRPWM_SYNCOUTPUTSOURCE_SLAVE0_STARTRST = HRPWM_MCR_SYNCOUT_SRC_1,
+ /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
+ HRPWM_SYNCOUTPUTSOURCE_SLAVE0_CMPA = HRPWM_MCR_SYNCOUT_SRC_1 | HRPWM_MCR_SYNCOUT_SRC_0,
+ /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+} HRPWM_SyncOutputSrcETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Synchronization_Output_Polarity HRPWM Synchronization Output Polarity
+ * @brief Constants defining the routing and conditioning of the synchronization output event
+ * @{
+ */
+typedef enum {
+ HRPWM_SYNCOUTPUTPOLARITY_NEGATIVE = HRPWM_MCR_SYNCOUT_POL,
+ /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRPWM clock cycles length for the synchronization */
+ HRPWM_SYNCOUTPUTPOLARITY_POSITIVE = 0x0,
+ /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRPWM clock cycles length for the synchronization */
+} HRPWM_SyncOutputPolETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Synchronization_Output_Enable HRPWM Synchronization Output Polarity
+ * @brief Constants defining the routing and conditioning of the synchronization output event
+ * @{
+ */
+typedef enum {
+ HRPWM_SYNCOUTPUT_ENABLE = HRPWM_MCR_SYNCOUT_EN,
+ /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRPWM clock cycles length for the synchronization */
+ HRPWM_SYNCOUTPUT_DISABLE = 0x0,
+ /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRPWM clock cycles length for the synchronization */
+} HRPWM_SyncOutputEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Fault_RollOver_Mode HRPWM Timer RollOver Mode
+ * @brief Constants defining when the roll-over is generated upon Timerx
+ * event generated when the counter is equal to 0 or to HRPWM_PERxR value or BOTH
+ * This setting only applies when the UDM bit is set. It is not significant otherwise.
+ * @{
+ */
+typedef enum {
+ HRPWM_FLTROM_BOTH = 0x0, /*!< The roll-over event is generated when the count is Period / 0 */
+ HRPWM_FLTROM_ZERO = HRPWM_CR1_FLTROM_0, /*!< The roll-over event is generated when the count is 0 */
+ HRPWM_FLTROM_PERIOD = HRPWM_CR1_FLTROM_1, /*!< The roll-over event is generated when the count is Period */
+} HRPWM_FltRollOverETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Event_RollOver_Mode HRPWM Timer RollOver Mode
+ * @brief HRPWM Timer RollOver Mode
+ * @{
+ */
+typedef enum {
+ HRPWM_EEVROM_BOTH = 0x0, /*!< The roll-over event is generated when the count is Period / 0 */
+ HRPWM_EEVROM_ZERO = HRPWM_CR1_EEVROM_0, /*!< The roll-over event is generated when the count is 0 */
+ HRPWM_EEVROM_PERIOD = HRPWM_CR1_EEVROM_1, /*!< The roll-over event is generated when the count is Period */
+} HRPWM_EventRollOverETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_ADTrig_RollOver_Mode HRPWM Timer RollOver Mode
+ * @brief HRPWM Timer RollOver Mode
+ * @{
+ */
+typedef enum {
+ HRPWM_ADROM_BOTH = 0x0, /*!< The roll-over event is generated when the count is Period / 0 */
+ HRPWM_ADROM_ZERO = HRPWM_CR1_ADROM_0, /*!< The roll-over event is generated when the count is 0 */
+ HRPWM_ADROM_PERIOD = HRPWM_CR1_ADROM_1, /*!< The roll-over event is generated when the count is Period */
+} HRPWM_AdcRollOverETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_Output_RollOver_Mode HRPWM Timer RollOver Mode
+ * @brief HRPWM Timer RollOver Mode
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTROM_BOTH = 0x0, /*!< The roll-over event is generated when the count is Period / 0 */
+ HRPWM_OUTROM_ZERO = HRPWM_CR1_OUTROM_0, /*!< The roll-over event is generated when the count is 0 */
+ HRPWM_OUTROM_PERIOD = HRPWM_CR1_OUTROM_1, /*!< The roll-over event is generated when the count is Period */
+} HRPWM_OutputRollOverETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_RollOver_Mode HRPWM Timer RollOver Mode
+ * @breif HRPWM Timer RollOver Mode
+ * @{
+ */
+typedef enum {
+ HRPWM_ROM_BOTH = 0x0, /*!< The roll-over event is generated when the count is Period / 0 */
+ HRPWM_ROM_ZERO = HRPWM_CR1_ROM_0, /*!< The roll-over event is generated when the count is 0 */
+ HRPWM_ROM_PERIOD = HRPWM_CR1_ROM_1, /*!< The roll-over event is generated when the count is Period */
+} HRPWM_RollOverETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_UpDown_Mode HRPWM Timer UpDown Mode
+ * @brief Constants defining how the timer counter operates
+ * @{
+ */
+typedef enum {
+ HRPWM_COUNT_UP = 0x0, /*!< Timer counter is operating in up-counting mode */
+ HRPWM_COUNT_UPDOWN = HRPWM_CR1_UDM, /*!< Timer counter is operating in up-down counting mode */
+} HRPWM_CounterModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_DualChannelDac_Reset HRPWM Dual Channel Dac Reset Trigger
+ * @brief Constants defining when the HRPWM_dac_reset_trgx trigger is generated
+ * @{
+ */
+typedef enum {
+ HRPWM_DAC_DCDR_SETA = 0x0, /*!< the trigger is generated on output A set event */
+ HRPWM_DAC_DCDR_RESET = HRPWM_CR1_DCDR, /*!< the trigger is generated on counter reset or roll-over event */
+} HRPWM_DacResetSelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_DualChannelDac_Step HRPWM Dual Channel Dac Step Trigger
+ * @brief Constants defining when the HRPWM_dac_step_trgx trigger is generated
+ * @{
+ */
+typedef enum {
+ HRPWM_DAC_DCDS_CLEARA = 0x0, /*!< the trigger is generated on output 1 reset event */
+ HRPWM_DAC_DCDS_CMPD = HRPWM_CR1_DCDS, /*!< the trigger is generated on compare D event */
+} HRPWM_DacStepSelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_DualChannelDac_Enable HRPWM Dual Channel DAC Trigger Enable
+ * @brief Constants enabling the dual channel DAC triggering mechanism
+ * @{
+ */
+typedef enum {
+ HRPWM_DAC_DCDE_DISABLE = 0x0, /*!< the Dual channel DAC trigger is disabled */
+ HRPWM_DAC_DCDE_ENABLE = HRPWM_CR1_DCDE, /*!< the Dual channel DAC trigger is enabled */
+} HRPWM_DacTrigEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Deadtime_Rising_Sign HRPWM Dead-time Rising Sign
+ * @brief Constants defining whether the dead-time is positive or negative (overlapping signal) on rising edge
+ * @{
+ */
+typedef enum {
+ HRPWM_DEADTIME_RSIGN_NEGATIVE = 0x0, /*!< Negative dead-time on rising edge */
+ HRPWM_DEADTIME_RSIGN_POSITIVE = HRPWM_DTR_SDTR, /*!< Positive dead-time on rising edge */
+} HRPWM_DeadTimeRiseSignETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Deadtime_Falling_Sign HRPWM Dead-time Falling Sign
+ * @brief Constants defining whether the dead-time is positive or negative (overlapping signal) on falling edge
+ * @{
+ */
+typedef enum {
+ HRPWM_DEADTIME_FSIGN_NEGATIVE = 0x0, /*!< Negative dead-time on falling edge */
+ HRPWM_DEADTIME_FSIGN_POSITIVE = HRPWM_DTR_SDTF, /*!< Positive dead-time on falling edge */
+} HRPWM_DeadTimeFallSignETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_External_Event_Filter HRPWM Timer External Event Filter
+ * @brief Constants defining the event filtering applied to external events
+ * by a timer0 (5bit), the position of eventx need to left x*5bit;
+ * @{
+ */
+typedef enum {
+ HRPWM_EEVFLT_NONE = 0x0,
+ /*!< HRPWM EEFVLT NONE */
+ HRPWM_EEVFLT_BLANKING_CMPA = HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Blanking from counter reset/roll-over to Compare A */
+ HRPWM_EEVFLT_BLANKING_CMPB = HRPWM_EEFR0_EE0FLTR_1,
+ /*!< Blanking from counter reset/roll-over to Compare B */
+ HRPWM_EEVFLT_BLANKING_CMPC = HRPWM_EEFR0_EE0FLTR_1 | HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Blanking from counter reset/roll-over to Compare C */
+ HRPWM_EEVFLT_BLANKING_CMPD = HRPWM_EEFR0_EE0FLTR_2,
+ /*!< Blanking from counter reset/roll-over to Compare D */
+ HRPWM_EEVFLT_BLANKING_UPCMPA_UPCMPB = HRPWM_EEFR0_EE0FLTR_2 | HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Blanking from counter up compare A to compare B only up_down mode valid */
+ HRPWM_EEVFLT_BLANKING_UPCMPC_UPCMPD = HRPWM_EEFR0_EE0FLTR_2 | HRPWM_EEFR0_EE0FLTR_1,
+ /*!< Blanking from counter up compare C to compare D only up_down mode valid */
+ HRPWM_EEVFLT_BLANKING_DOWNCMPA_DOWNCMPB = HRPWM_EEFR0_EE0FLTR_2 | HRPWM_EEFR0_EE0FLTR_1 | HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Blanking from counter down compare A to compare B only up_down mode valid */
+ HRPWM_EEVFLT_BLANKING_DOWNCMPC_DOWNCMPD = HRPWM_EEFR0_EE0FLTR_3,
+ /*!< Blanking from counter down compare C to compare D only up_down mode valid */
+ HRPWM_EEVFLT_WINDOWS_BLANKING_CMPA = HRPWM_EEFR0_EE0FLTR_3 | HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Windows from counter reset/roll-over to Compare A */
+ HRPWM_EEVFLT_WINDOWS_BLANKING_CMPB = HRPWM_EEFR0_EE0FLTR_3 | HRPWM_EEFR0_EE0FLTR_1,
+ /*!< Windows from counter reset/roll-over to Compare B */
+ HRPWM_EEVFLT_WINDOWS_BLANKING_CMPC = HRPWM_EEFR0_EE0FLTR_3 | HRPWM_EEFR0_EE0FLTR_1 | HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Windows from counter reset/roll-over to Compare C */
+ HRPWM_EEVFLT_WINDOWS_BLANKING_CMPD = HRPWM_EEFR0_EE0FLTR_3 | HRPWM_EEFR0_EE0FLTR_2,
+ /*!< Windows from counter reset/roll-over to Compare D */
+ HRPWM_EEVFLT_WINDOWS_UPCMPB_UPCMPC = HRPWM_EEFR0_EE0FLTR_3 | HRPWM_EEFR0_EE0FLTR_2 | HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Windows from counter up compare B to compare C only up_down mode valid */
+ HRPWM_EEVFLT_WINDOWS_DOWNCMPB_DOWNCMPC = HRPWM_EEFR0_EE0FLTR_3 | HRPWM_EEFR0_EE0FLTR_2 | HRPWM_EEFR0_EE0FLTR_1,
+ /*!< Windows from counter down compare B to compare C only up_down mode valid */
+ HRPWM_EEVFLT_WINDOWS_UPCMPB_DOWNCMPC = HRPWM_EEFR0_EE0FLTR_3 | HRPWM_EEFR0_EE0FLTR_2 | HRPWM_EEFR0_EE0FLTR_1 | HRPWM_EEFR0_EE0FLTR_0,
+ /*!< Windows from counter up compare B to down compare C only up_down mode valid */
+} HRPWM_EventAFilterWindowETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_External_Event_Latch HRPWM Timer External Event Latch
+ * @brief Constants defining whether or not the external event is
+ * memorized (latched) and generated as soon as the blanking period
+ * is completed or the window ends, the position of eventx need to left x*5bit;
+ * @{
+ */
+typedef enum {
+ HRPWM_EVENTLATCH_DISABLE = 0x0,
+ /*!< Event is ignored if it happens during a blank, or passed through during a window */
+ HRPWM_EVENTLATCH_ENABLE = HRPWM_EEFR0_EE0LTCH,
+ /*!< Event is latched and delayed till the end of the blanking or windowing period */
+} HRPWM_EventALatchETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Source_Select HRPWM Timer External Event Counter A source selection
+ * @brief Constants defining the External Event Counter A source selection
+ * @{
+ */
+typedef enum {
+ HRPWM_EEVASEL_SOURCE_EEVENT0 = 0x00U, /*!< External Event A selected event 0 as the source */
+ HRPWM_EEVASEL_SOURCE_EEVENT1 = 0x10U, /*!< External Event A selected event 1 as the source */
+ HRPWM_EEVASEL_SOURCE_EEVENT2 = 0x20U, /*!< External Event A selected event 2 as the source */
+ HRPWM_EEVASEL_SOURCE_EEVENT3 = 0x30U, /*!< External Event A selected event 3 as the source */
+ HRPWM_EEVASEL_SOURCE_EEVENT4 = 0x40U, /*!< External Event A selected event 4 as the source */
+ HRPWM_EEVASEL_SOURCE_EEVENT5 = 0x50U, /*!< External Event A selected event 5 as the source */
+} HRPWM_EventASourceSelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_External_Event_Counter HRPWM Timer External Event Counter
+ * @brief Constants enabling the External Event A Counter
+ * @{
+ */
+typedef enum {
+ HRPWM_EEVACOUNTER_DISABLE = 0x0, /*!< External Event Counter disabled */
+ HRPWM_EEVACOUNTER_ENABLE = HRPWM_EEFR1_EEVACE, /*!< External Event Counter enabled */
+} HRPWM_EventACouterEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Timer_External_Event_ResetMode HRPWM Timer External Counter Reset Mode
+ * @brief Constants enabling the External Event Counter A Reset Mode
+ * @{
+ */
+typedef enum {
+ HRPWM_EEVARSTM_UNCONDITIONAL = 0x0,
+ /*!< External Event Counter is reset on each reset / roll-over event */
+ HRPWM_EEVARSTM_CONDITIONAL = HRPWM_EEFR1_EEVARSTM,
+ /*!< External Event Counter is reset on each reset / roll-over event only if no event occurs during last counting period */
+} HRPWM_EventARstModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Chopper_Frequency HRPWM Chopper Frequency
+ * @brief Constants defining the frequency of the generated high frequency carrier
+ * @{
+ */
+typedef enum {
+ HRPWM_CHOPPER_CARFRQ_DIV16 = 0x0,
+ /*!< fCHPFRQ = fHRPWM / 16 */
+ HRPWM_CHOPPER_CARFRQ_DIV32 = HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 32 */
+ HRPWM_CHOPPER_CARFRQ_DIV48 = HRPWM_CHPR_CARFRQ_1,
+ /*!< fCHPFRQ = fHRPWM / 48 */
+ HRPWM_CHOPPER_CARFRQ_DIV64 = HRPWM_CHPR_CARFRQ_1 | HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 64 */
+ HRPWM_CHOPPER_CARFRQ_DIV80 = HRPWM_CHPR_CARFRQ_2,
+ /*!< fCHPFRQ = fHRPWM / 80 */
+ HRPWM_CHOPPER_CARFRQ_DIV96 = HRPWM_CHPR_CARFRQ_2 | HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 96 */
+ HRPWM_CHOPPER_CARFRQ_DIV112 = HRPWM_CHPR_CARFRQ_2 | HRPWM_CHPR_CARFRQ_1,
+ /*!< fCHPFRQ = fHRPWM / 112 */
+ HRPWM_CHOPPER_CARFRQ_DIV128 = HRPWM_CHPR_CARFRQ_2 | HRPWM_CHPR_CARFRQ_1 | HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 128 */
+ HRPWM_CHOPPER_CARFRQ_DIV144 = HRPWM_CHPR_CARFRQ_3,
+ /*!< fCHPFRQ = fHRPWM / 144 */
+ HRPWM_CHOPPER_CARFRQ_DIV160 = HRPWM_CHPR_CARFRQ_3 | HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 160 */
+ HRPWM_CHOPPER_CARFRQ_DIV176 = HRPWM_CHPR_CARFRQ_3 | HRPWM_CHPR_CARFRQ_1,
+ /*!< fCHPFRQ = fHRPWM / 176 */
+ HRPWM_CHOPPER_CARFRQ_DIV192 = HRPWM_CHPR_CARFRQ_3 | HRPWM_CHPR_CARFRQ_1 | HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 192 */
+ HRPWM_CHOPPER_CARFRQ_DIV208 = HRPWM_CHPR_CARFRQ_3 | HRPWM_CHPR_CARFRQ_2,
+ /*!< fCHPFRQ = fHRPWM / 208 */
+ HRPWM_CHOPPER_CARFRQ_DIV224 = HRPWM_CHPR_CARFRQ_3 | HRPWM_CHPR_CARFRQ_2 | HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 224 */
+ HRPWM_CHOPPER_CARFRQ_DIV240 = HRPWM_CHPR_CARFRQ_3 | HRPWM_CHPR_CARFRQ_2 | HRPWM_CHPR_CARFRQ_1,
+ /*!< fCHPFRQ = fHRPWM / 240 */
+ HRPWM_CHOPPER_CARFRQ_DIV256 = HRPWM_CHPR_CARFRQ_3 | HRPWM_CHPR_CARFRQ_2 | HRPWM_CHPR_CARFRQ_1 | HRPWM_CHPR_CARFRQ_0,
+ /*!< fCHPFRQ = fHRPWM / 256 */
+} HRPWM_ChopperCarfreqETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Chopper_Duty_Cycle HRPWM Chopper Duty Cycle
+ * @brief Constants defining the duty cycle of the generated high frequency carrier
+ * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
+ * @{
+ */
+typedef enum {
+ HRPWM_CHOPPER_DUTYCYCLE_0 = 0x0,
+ /*!< Only 1st pulse is present */
+ HRPWM_CHOPPER_DUTYCYCLE_1 = HRPWM_CHPR_CARDTY_0,
+ /*!< Duty cycle of the carrier signal is 12.5U % */
+ HRPWM_CHOPPER_DUTYCYCLE_2 = HRPWM_CHPR_CARDTY_1,
+ /*!< Duty cycle of the carrier signal is 25U % */
+ HRPWM_CHOPPER_DUTYCYCLE_3 = HRPWM_CHPR_CARDTY_1 | HRPWM_CHPR_CARDTY_0,
+ /*!< Duty cycle of the carrier signal is 37.5U % */
+ HRPWM_CHOPPER_DUTYCYCLE_4 = HRPWM_CHPR_CARDTY_2,
+ /*!< Duty cycle of the carrier signal is 50U % */
+ HRPWM_CHOPPER_DUTYCYCLE_5 = HRPWM_CHPR_CARDTY_2 | HRPWM_CHPR_CARDTY_0,
+ /*!< Duty cycle of the carrier signal is 62.5U % */
+ HRPWM_CHOPPER_DUTYCYCLE_6 = HRPWM_CHPR_CARDTY_2 | HRPWM_CHPR_CARDTY_1,
+ /*!< Duty cycle of the carrier signal is 75U % */
+ HRPWM_CHOPPER_DUTYCYCLE_7 = HRPWM_CHPR_CARDTY_2 | HRPWM_CHPR_CARDTY_1 | HRPWM_CHPR_CARDTY_0,
+ /*!< Duty cycle of the carrier signal is 87.5U % */
+} HRPWM_ChopperDutyETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Chopper_Start_Pulse_Width HRPWM Chopper Start Pulse Width
+ * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier
+ * @{
+ */
+typedef enum {
+ HRPWM_CHOPPER_PULSEWIDTH_16 = 0x0,
+ /*!< tSTPW = tHRPWM x 16 */
+ HRPWM_CHOPPER_PULSEWIDTH_32 = HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 32 */
+ HRPWM_CHOPPER_PULSEWIDTH_48 = HRPWM_CHPR_STRPW_1,
+ /*!< tSTPW = tHRPWM x 48 */
+ HRPWM_CHOPPER_PULSEWIDTH_64 = HRPWM_CHPR_STRPW_1 | HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 64 */
+ HRPWM_CHOPPER_PULSEWIDTH_80 = HRPWM_CHPR_STRPW_2,
+ /*!< tSTPW = tHRPWM x 80 */
+ HRPWM_CHOPPER_PULSEWIDTH_96 = HRPWM_CHPR_STRPW_2 | HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 96 */
+ HRPWM_CHOPPER_PULSEWIDTH_112 = HRPWM_CHPR_STRPW_2 | HRPWM_CHPR_STRPW_1,
+ /*!< tSTPW = tHRPWM x 112 */
+ HRPWM_CHOPPER_PULSEWIDTH_128 = HRPWM_CHPR_STRPW_2 | HRPWM_CHPR_STRPW_1 | HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 128 */
+ HRPWM_CHOPPER_PULSEWIDTH_144 = HRPWM_CHPR_STRPW_3,
+ /*!< tSTPW = tHRPWM x 144 */
+ HRPWM_CHOPPER_PULSEWIDTH_160 = HRPWM_CHPR_STRPW_3 | HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 160 */
+ HRPWM_CHOPPER_PULSEWIDTH_176 = HRPWM_CHPR_STRPW_3 | HRPWM_CHPR_STRPW_1,
+ /*!< tSTPW = tHRPWM x 176 */
+ HRPWM_CHOPPER_PULSEWIDTH_192 = HRPWM_CHPR_STRPW_3 | HRPWM_CHPR_STRPW_1 | HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 192 */
+ HRPWM_CHOPPER_PULSEWIDTH_208 = HRPWM_CHPR_STRPW_3 | HRPWM_CHPR_STRPW_2,
+ /*!< tSTPW = tHRPWM x 208 */
+ HRPWM_CHOPPER_PULSEWIDTH_224 = HRPWM_CHPR_STRPW_3 | HRPWM_CHPR_STRPW_2 | HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 224 */
+ HRPWM_CHOPPER_PULSEWIDTH_240 = HRPWM_CHPR_STRPW_3 | HRPWM_CHPR_STRPW_2 | HRPWM_CHPR_STRPW_1,
+ /*!< tSTPW = tHRPWM x 240 */
+ HRPWM_CHOPPER_PULSEWIDTH_256 = HRPWM_CHPR_STRPW_3 | HRPWM_CHPR_STRPW_2 | HRPWM_CHPR_STRPW_1 | HRPWM_CHPR_STRPW_0,
+ /*!< tSTPW = tHRPWM x 256 */
+} HRPWM_ChopperPulseWidthETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Output_ChopperA_Mode_Enable HRPWM Output Chopper Mode Enable
+ * @brief Constants defining whether or not chopper mode is enabled for a timer
+ output
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUTCHOPPERA_DISABLE = 0x0, /*!< Output signal is not altered */
+ HRPWM_OUTPUTCHOPPERA_ENABLE = HRPWM_OUTR_CHPA, /*!< Output signal is chopped by a carrier signal */
+} HRPWM_ChopperAEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_OutputA_IDLE_Level HRPWM Output IDLE Level
+ * @brief Constants defining the output level when output is in IDLE state
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUTIDLEA_INACTIVE = 0x0, /*!< Output at inactive level when in IDLE state */
+ HRPWM_OUTPUTIDLEA_ACTIVE = HRPWM_OUTR_IDLESA, /*!< Output at active level when in IDLE state */
+} HRPWM_IdelALevelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_OutputA_FAULT_Level HRPWM Output FAULT Level
+ * @brief Constants defining the output level when output is in FAULT state
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUTFAULTA_NONE = 0x0, /*!< The output is not affected by the fault input */
+ HRPWM_OUTPUTFAULTA_ACTIVE = HRPWM_OUTR_FAULTA_0, /*!< Output at active level when in FAULT state */
+ HRPWM_OUTPUTFAULTA_INACTIVE = HRPWM_OUTR_FAULTA_1, /*!< Output at inactive level when in FAULT state */
+ HRPWM_OUTPUTFAULTA_HIGHZ = HRPWM_OUTR_FAULTA_1 | HRPWM_OUTR_FAULTA_0,/*!< Output is tri-stated when in FAULT state */
+} HRPWM_FaultALevelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_OutputA_Active_Polarity HRPWM Output Active_Polarity
+ * @brief Constants whether the effective polarity is low level valid or high level valid
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUT_POLA_POSITIVE = 0x0, /*!< Positive polarity, high output efficiency */
+ HRPWM_OUTPUT_POLA_NEGATIVE = HRPWM_OUTR_POLA, /*!< Negative polarity, low output efficiency */
+} HRPWM_OutputAPolETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Output_ChopperB_Mode_Enable HRPWM Output Chopper Mode Enable
+ * @brief Constants defining whether or not chopper mode is enabled for a timer output
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUTCHOPPERB_DISABLE = 0x0, /*!< Output signal is not altered */
+ HRPWM_OUTPUTCHOPPERB_ENABLE = HRPWM_OUTR_CHPB, /*!< Output signal is chopped by a carrier signal */
+} HRPWM_ChopperBEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_OutputB_IDLE_Level HRPWM Output IDLE Level
+ * @brief Constants defining the output level when output is in IDLE state
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUTIDLEB_INACTIVE = 0x0, /*!< Output at inactive level when in IDLE state */
+ HRPWM_OUTPUTIDLEB_ACTIVE = HRPWM_OUTR_IDLESB, /*!< Output at active level when in IDLE state */
+} HRPWM_IdelBLevelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_OutputB_FAULT_Level HRPWM Output FAULT Level
+ * @brief Constants defining the output level when output is in FAULT state
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUTFAULTB_NONE = 0x0, /*!< The output is not affected by the fault input */
+ HRPWM_OUTPUTFAULTB_ACTIVE = HRPWM_OUTR_FAULTB_0, /*!< Output at active level when in FAULT state */
+ HRPWM_OUTPUTFAULTB_INACTIVE = HRPWM_OUTR_FAULTB_1, /*!< Output at inactive level when in FAULT state */
+ HRPWM_OUTPUTFAULTB_HIGHZ = HRPWM_OUTR_FAULTB_1 | HRPWM_OUTR_FAULTB_0,/*!< Output is tri-stated when in FAULT state */
+} HRPWM_FaultBLevelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_OutputB_Active_Polarity HRPWM Output Active_Polarity
+ * @brief Constants whether the effective polarity is low level valid or high level valid
+ * @{
+ */
+typedef enum {
+ HRPWM_OUTPUT_POLB_POSITIVE = 0x0, /*!< Positive polarity, high output efficiency */
+ HRPWM_OUTPUT_POLB_NEGATIVE = HRPWM_OUTR_POLB, /*!< Negative polarity, low output efficiency */
+} HRPWM_OutputBPolETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_ADC_Trigger_PostScaler HRPWM ADC Trigger PostScaler
+ * @brief constants defining the adc trigger PostScaler 0~0xf;
+ * @{
+ */
+typedef enum {
+ HRPWM_ADCTRIG_PSC_1 = 0x0,
+ /*!< The PostScaler number of 1 */
+ HRPWM_ADCTRIG_PSC_2 = HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 2 */
+ HRPWM_ADCTRIG_PSC_3 = HRPWM_ADPSR_ADPSC0_1,
+ /*!< The PostScaler number of 3 */
+ HRPWM_ADCTRIG_PSC_4 = HRPWM_ADPSR_ADPSC0_1 | HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 4 */
+ HRPWM_ADCTRIG_PSC_5 = HRPWM_ADPSR_ADPSC0_2,
+ /*!< The PostScaler number of 5 */
+ HRPWM_ADCTRIG_PSC_6 = HRPWM_ADPSR_ADPSC0_2 | HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 6 */
+ HRPWM_ADCTRIG_PSC_7 = HRPWM_ADPSR_ADPSC0_2 | HRPWM_ADPSR_ADPSC0_1,
+ /*!< The PostScaler number of 7 */
+ HRPWM_ADCTRIG_PSC_8 = HRPWM_ADPSR_ADPSC0_2 | HRPWM_ADPSR_ADPSC0_1 | HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 8 */
+ HRPWM_ADCTRIG_PSC_9 = HRPWM_ADPSR_ADPSC0_3,
+ /*!< The PostScaler number of 9 */
+ HRPWM_ADCTRIG_PSC_10 = HRPWM_ADPSR_ADPSC0_3 | HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 10 */
+ HRPWM_ADCTRIG_PSC_11 = HRPWM_ADPSR_ADPSC0_3 | HRPWM_ADPSR_ADPSC0_1,
+ /*!< The PostScaler number of 11 */
+ HRPWM_ADCTRIG_PSC_12 = HRPWM_ADPSR_ADPSC0_3 | HRPWM_ADPSR_ADPSC0_1 | HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 12 */
+ HRPWM_ADCTRIG_PSC_13 = HRPWM_ADPSR_ADPSC0_3 | HRPWM_ADPSR_ADPSC0_2,
+ /*!< The PostScaler number of 13 */
+ HRPWM_ADCTRIG_PSC_14 = HRPWM_ADPSR_ADPSC0_3 | HRPWM_ADPSR_ADPSC0_2 | HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 14 */
+ HRPWM_ADCTRIG_PSC_15 = HRPWM_ADPSR_ADPSC0_3 | HRPWM_ADPSR_ADPSC0_2 | HRPWM_ADPSR_ADPSC0_1,
+ /*!< The PostScaler number of 15 */
+ HRPWM_ADCTRIG_PSC_16 = HRPWM_ADPSR_ADPSC0_3 | HRPWM_ADPSR_ADPSC0_2 | HRPWM_ADPSR_ADPSC0_1 | HRPWM_ADPSR_ADPSC0_0,
+ /*!< The PostScaler number of 16 */
+} HRPWM_AdcTrigPSCETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_ADC_Trigger_Update_Source HRPWM ADC Trigger Update Source
+ * @brief constants defining the source triggering the update of the
+ HRPWM_ADCxR register (transfer from preload to active register). 3bit
+ * @{
+ */
+typedef enum {
+ HRPWM_ADCTRIGUPDATE_MASTER = 0x0, /*!< Master timer */
+ HRPWM_ADCTRIGUPDATE_TIMER_0 = HRPWM_CR0_ADUSRC0_0, /*!< Slave Timer 0 */
+ HRPWM_ADCTRIGUPDATE_TIMER_1 = HRPWM_CR0_ADUSRC0_1, /*!< Slave Timer 1 */
+ HRPWM_ADCTRIGUPDATE_TIMER_2 = HRPWM_CR0_ADUSRC0_1 | HRPWM_CR0_ADUSRC0_0, /*!< Slave Timer 2 */
+ HRPWM_ADCTRIGUPDATE_TIMER_3 = HRPWM_CR0_ADUSRC0_2, /*!< Slave Timer 3 */
+ HRPWM_ADCTRIGUPDATE_TIMER_4 = HRPWM_CR0_ADUSRC0_2 | HRPWM_CR0_ADUSRC0_0, /*!< Slave Timer 4 */
+ HRPWM_ADCTRIGUPDATE_TIMER_5 = HRPWM_CR0_ADUSRC0_2 | HRPWM_CR0_ADUSRC0_1, /*!< Slave Timer 5 */
+} HRPWM_AdcTrigUpdateSrcETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_ADC_Trigger_Length HRPWM ADC Trigger Length
+ * @brief constants defining the events triggering length. (left x * 4bit)
+ * @{
+ */
+typedef enum {
+ HRPWM_ADCTRIG_LENGTH_1 = 0x0,
+ /*!< The length of ADC trigger time is 1 clock */
+ HRPWM_ADCTRIG_LENGTH_2 = HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 2 clock */
+ HRPWM_ADCTRIG_LENGTH_3 = HRPWM_CR2_TLEN0_1,
+ /*!< The length of ADC trigger time is 3 clock */
+ HRPWM_ADCTRIG_LENGTH_4 = HRPWM_CR2_TLEN0_1 | HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 4 clock */
+ HRPWM_ADCTRIG_LENGTH_5 = HRPWM_CR2_TLEN0_2,
+ /*!< The length of ADC trigger time is 5 clock */
+ HRPWM_ADCTRIG_LENGTH_6 = HRPWM_CR2_TLEN0_2 | HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 6 clock */
+ HRPWM_ADCTRIG_LENGTH_7 = HRPWM_CR2_TLEN0_2 | HRPWM_CR2_TLEN0_1,
+ /*!< The length of ADC trigger time is 7 clock */
+ HRPWM_ADCTRIG_LENGTH_8 = HRPWM_CR2_TLEN0_2 | HRPWM_CR2_TLEN0_1 | HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 8 clock */
+ HRPWM_ADCTRIG_LENGTH_9 = HRPWM_CR2_TLEN0_3,
+ /*!< The length of ADC trigger time is 9 clock */
+ HRPWM_ADCTRIG_LENGTH_10 = HRPWM_CR2_TLEN0_3 | HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 10 clock */
+ HRPWM_ADCTRIG_LENGTH_11 = HRPWM_CR2_TLEN0_3 | HRPWM_CR2_TLEN0_1,
+ /*!< The length of ADC trigger time is 11 clock */
+ HRPWM_ADCTRIG_LENGTH_12 = HRPWM_CR2_TLEN0_3 | HRPWM_CR2_TLEN0_1 | HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 12 clock */
+ HRPWM_ADCTRIG_LENGTH_13 = HRPWM_CR2_TLEN0_3 | HRPWM_CR2_TLEN0_2,
+ /*!< The length of ADC trigger time is 13 clock */
+ HRPWM_ADCTRIG_LENGTH_14 = HRPWM_CR2_TLEN0_3 | HRPWM_CR2_TLEN0_2 | HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 14 clock */
+ HRPWM_ADCTRIG_LENGTH_15 = HRPWM_CR2_TLEN0_3 | HRPWM_CR2_TLEN0_2 | HRPWM_CR2_TLEN0_1,
+ /*!< The length of ADC trigger time is 15 clock */
+ HRPWM_ADCTRIG_LENGTH_16 = HRPWM_CR2_TLEN0_3 | HRPWM_CR2_TLEN0_2 | HRPWM_CR2_TLEN0_1 | HRPWM_CR2_TLEN0_0,
+ /*!< The length of ADC trigger time is 16 clock */
+} HRPWM_AdcTrigLengthETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Prescaler HRPWM External Event Prescaler
+ * @brief Constants defining division ratio between the timer clock frequency
+ * fHRPWM) and the external event signal sampling clock (fEEVS)
+ * used by the digital filters
+ * @{
+ */
+typedef enum {
+ HRPWM_EEVSD_DIV1 = 0x0, /*!< fEEVS=fHRPWM */
+ HRPWM_EEVSD_DIV2 = HRPWM_EECR2_EEVSD_0, /*!< fEEVS=fHRPWM / 2U */
+ HRPWM_EEVSD_DIV4 = (int32_t)HRPWM_EECR2_EEVSD_1, /*!< fEEVS=fHRPWM / 4U */
+ HRPWM_EEVSD_DIV8 = (int32_t)(HRPWM_EECR2_EEVSD_1 | HRPWM_EECR2_EEVSD_0), /*!< fEEVS=fHRPWM / 8U */
+} HRPWM_EventPrescalerETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Filter HRPWM External Event Filter
+ * @brief Constants defining the frequency used to sample an external event 6
+ * input and the length (N) of the digital filter applied
+ * @{
+ */
+typedef enum {
+ HRPWM_EVENTFILTER_NONE = 0x0,
+ /*!< Filter disabled */
+ HRPWM_EVENTFILTER_1 = HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fHRPWM, N=2U */
+ HRPWM_EVENTFILTER_2 = HRPWM_EECR2_EE0F_1,
+ /*!< fSAMPLING= fHRPWM, N=4U */
+ HRPWM_EVENTFILTER_3 = HRPWM_EECR2_EE0F_1 | HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fHRPWM, N=8U */
+ HRPWM_EVENTFILTER_4 = HRPWM_EECR2_EE0F_2,
+ /*!< fSAMPLING= fEEVS/2U, N=6U */
+ HRPWM_EVENTFILTER_5 = HRPWM_EECR2_EE0F_2 | HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fEEVS/2U, N=8U */
+ HRPWM_EVENTFILTER_6 = HRPWM_EECR2_EE0F_2 | HRPWM_EECR2_EE0F_1,
+ /*!< fSAMPLING= fEEVS/4U, N=6U */
+ HRPWM_EVENTFILTER_7 = HRPWM_EECR2_EE0F_2 | HRPWM_EECR2_EE0F_1 | HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fEEVS/4U, N=8U */
+ HRPWM_EVENTFILTER_8 = HRPWM_EECR2_EE0F_3,
+ /*!< fSAMPLING= fEEVS/8U, N=6U */
+ HRPWM_EVENTFILTER_9 = HRPWM_EECR2_EE0F_3 | HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fEEVS/8U, N=8U */
+ HRPWM_EVENTFILTER_10 = HRPWM_EECR2_EE0F_3 | HRPWM_EECR2_EE0F_1,
+ /*!< fSAMPLING= fEEVS/16U, N=5U */
+ HRPWM_EVENTFILTER_11 = HRPWM_EECR2_EE0F_3 | HRPWM_EECR2_EE0F_1 | HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fEEVS/16U, N=6U */
+ HRPWM_EVENTFILTER_12 = HRPWM_EECR2_EE0F_3 | HRPWM_EECR2_EE0F_2,
+ /*!< fSAMPLING= fEEVS/16U, N=8U */
+ HRPWM_EVENTFILTER_13 = HRPWM_EECR2_EE0F_3 | HRPWM_EECR2_EE0F_2 | HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fEEVS/32U, N=5U */
+ HRPWM_EVENTFILTER_14 = HRPWM_EECR2_EE0F_3 | HRPWM_EECR2_EE0F_2 | HRPWM_EECR2_EE0F_1,
+ /*!< fSAMPLING= fEEVS/32U, N=6U */
+ HRPWM_EVENTFILTER_15 = HRPWM_EECR2_EE0F_3 | HRPWM_EECR2_EE0F_2 | HRPWM_EECR2_EE0F_1 | HRPWM_EECR2_EE0F_0,
+ /*!< fSAMPLING= fEEVS/32U, N=8U */
+} HRPWM_EventFilterETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Fast_Mode HRPWM External Event Fast Mode
+ * @brief Constants defining whether or not an external event is programmed in fast mode
+ * @{
+ */
+typedef enum {
+ HRPWM_EVENTFASTMODE_DISABLE = 0x0,
+ /*!< External Event is re-synchronized by the HRPWM logic before acting on outputs */
+ HRPWM_EVENTFASTMODE_ENABLE = HRPWM_EECR0_EE0FAST,
+ /*!< External Event is acting asynchronously on outputs (low latency mode) */
+} HRPWM_EventFastModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Sensitivity HRPWM External Event Sensitivity
+ * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
+ * of an external event
+ * @{
+ */
+typedef enum {
+ HRPWM_EVENTSENS_LEVEL = 0x0,
+ /*!< External event is active on level */
+ HRPWM_EVENTSENS_RISINGEDGE = HRPWM_EECR0_EE0SNS_0,
+ /*!< External event is active on Rising edge */
+ HRPWM_EVENTSENS_FALLINGEDGE = HRPWM_EECR0_EE0SNS_1,
+ /*!< External event is active on Falling edge */
+ HRPWM_EVENTSENS_BOTHEDGES = HRPWM_EECR0_EE0SNS_1 | HRPWM_EECR0_EE0SNS_0,
+ /*!< External event is active on Rising and Falling edges */
+} HRPWM_EventSensETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Polarity HRPWM External Event Polarity
+ * @brief Constants defining the polarity of an external event
+ * @{
+ */
+typedef enum {
+ HRPWM_EVENTPOL_HIGH = 0x0, /*!< External event is active high */
+ HRPWM_EVENTPOL_LOW = HRPWM_EECR0_EE0POL, /*!< External event is active low */
+} HRPWM_EventPolETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Event_Sources HRPWM External Event Sources
+ * @brief Constants defining available sources associated to external events
+ * @{
+ */
+typedef enum {
+ HRPWM_EEVSRC_GPIO = 0x0, /*!< External event source 1U for External Event */
+ HRPWM_EEVSRC_COMP_OUT = HRPWM_EECR0_EE0SRC_0, /*!< External event source 2U for External Event */
+ HRPWM_EEVSRC_TIM_TRGO = HRPWM_EECR0_EE0SRC_1, /*!< External event source 3U for External Event */
+ HRPWM_EEVSRC_ADC_AWD = HRPWM_EECR0_EE0SRC_1 | HRPWM_EECR0_EE0SRC_0, /*!< External event source 4U for External Event */
+} HRPWM_EventSrcSelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Enable HRPWM Fault Enable
+ * @brief Constants defining the Enable of a fault event
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULT_DISABLE = 0x0, /*!< Fault input is disable */
+ HRPWM_FAULT_ENABLE = HRPWM_FLTINR0_FLT0E, /*!< Fault input is enable */
+} HRPWM_FaultEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Sources HRPWM Fault Sources
+ * @brief Constants defining whether a fault is triggered by any external or internal fault source
+ * @{
+ */
+typedef enum {
+ HRPWM_FLTSRC_GPIO = 0x0, /*!< The fault source 1U for External pin 0 */
+ HRPWM_FLTSRC_COMP_OUT = HRPWM_FLTINR0_FLT0SRC_0, /*!< The fault source 2U for External Event 0 */
+ HRPWM_FLTSRC_EVENT = HRPWM_FLTINR0_FLT0SRC_1, /*!< The fault source 3U for internal Event 0 */
+} HRPWM_FaultSrcSelETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Polarity HRPWM Fault Polarity
+ * @brief Constants defining the polarity of a fault event
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULTPOL_HIGH = 0x0, /*!< Fault input is active low */
+ HRPWM_FAULTPOL_LOW = HRPWM_FLTINR0_FLT0P, /*!< Fault input is active high */
+} HRPWM_FaultPolETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Blanking HRPWM Fault Blanking Source
+ * @brief Constants defining the blanking source of a fault event
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULTBLKS_RSTALIGNED = 0x0, /*!< Fault blanking source is Reset-aligned window */
+ HRPWM_FAULTBLKS_MOVING = HRPWM_FLTINR2_FLT0BLKS, /*!< Fault blanking source is Moving window */
+} HRPWM_FaultBlkWindowETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_ResetMode HRPWM Fault Reset Mode
+ * @brief Constants defining the Counter reset mode of a fault event
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULTRSTM_UNCONDITIONAL = 0x0,
+ /*!< Fault counter is reset on each reset / roll-over event */
+ HRPWM_FAULTRSTM_CONDITIONAL = HRPWM_FLTINR2_FLT0RSTM,
+ /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last countingperiod. */
+} HRPWM_FaultRstModeETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Blanking_Control HRPWM Fault Blanking Control
+ * @brief Constants used to enable or disable the blanking mode of a fault channel
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULTBLKEN_DISABLE = 0x0, /*!< No blanking on Fault */
+ HRPWM_FAULTBLKEN_ENABLE = HRPWM_FLTINR2_FLT0BLKE, /*!< Fault blanking mode */
+} HRPWM_FaultBlkEnETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_External_Fault_Prescaler HRPWM External Fault Prescaler
+ * @brief Constants defining the division ratio between the timer clock
+ * frequency (fHRPWM) and the fault signal sampling clock (fFLTS) used
+ * by the digital filters.
+ * @{
+ */
+typedef enum {
+ HRPWM_FLTSD_DIV1 = 0x0, /*!< fFLTS=fHRPWM */
+ HRPWM_FLTSD_DIV2 = HRPWM_FLTINR1_FLTSD_0, /*!< fFLTS=fHRPWM / 2U */
+ HRPWM_FLTSD_DIV4 = (int32_t)HRPWM_FLTINR1_FLTSD_1, /*!< fFLTS=fHRPWM / 4U */
+ HRPWM_FLTSD_DIV8 = (int32_t)(HRPWM_FLTINR1_FLTSD_1 | HRPWM_FLTINR1_FLTSD_0), /*!< fFLTS=fHRPWM / 8U */
+} HRPWM_FaultPrescalerETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Filter HRPWM Fault Filter
+ * @brief Constants defining the frequency used to sample the fault input and
+ * the length (N) of the digital filter applied
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULTFILTER_NONE = 0x0,
+ /*!< Filter disabled */
+ HRPWM_FAULTFILTER_1 = HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fHRPWM, N=2U */
+ HRPWM_FAULTFILTER_2 = HRPWM_FLTINR1_FLT0F_1,
+ /*!< fSAMPLING= fHRPWM, N=4U */
+ HRPWM_FAULTFILTER_3 = HRPWM_FLTINR1_FLT0F_1 | HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fHRPWM, N=8U */
+ HRPWM_FAULTFILTER_4 = HRPWM_FLTINR1_FLT0F_2,
+ /*!< fSAMPLING= fFLTS/2U, N=6U */
+ HRPWM_FAULTFILTER_5 = HRPWM_FLTINR1_FLT0F_2 | HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fFLTS/2U, N=8U */
+ HRPWM_FAULTFILTER_6 = HRPWM_FLTINR1_FLT0F_2 | HRPWM_FLTINR1_FLT0F_1,
+ /*!< fSAMPLING= fFLTS/4U, N=6U */
+ HRPWM_FAULTFILTER_7 = HRPWM_FLTINR1_FLT0F_2 | HRPWM_FLTINR1_FLT0F_1 | HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fFLTS/4U, N=8U */
+ HRPWM_FAULTFILTER_8 = HRPWM_FLTINR1_FLT0F_3,
+ /*!< fSAMPLING= fFLTS/8U, N=6U */
+ HRPWM_FAULTFILTER_9 = HRPWM_FLTINR1_FLT0F_3 | HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fFLTS/8U, N=8U */
+ HRPWM_FAULTFILTER_10 = HRPWM_FLTINR1_FLT0F_3 | HRPWM_FLTINR1_FLT0F_1,
+ /*!< fSAMPLING= fFLTS/16U, N=5U */
+ HRPWM_FAULTFILTER_11 = HRPWM_FLTINR1_FLT0F_3 | HRPWM_FLTINR1_FLT0F_1 | HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fFLTS/16U, N=6U */
+ HRPWM_FAULTFILTER_12 = HRPWM_FLTINR1_FLT0F_3 | HRPWM_FLTINR1_FLT0F_2,
+ /*!< fSAMPLING= fFLTS/16U, N=8U */
+ HRPWM_FAULTFILTER_13 = HRPWM_FLTINR1_FLT0F_3 | HRPWM_FLTINR1_FLT0F_2 | HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fFLTS/32U, N=5U */
+ HRPWM_FAULTFILTER_14 = HRPWM_FLTINR1_FLT0F_3 | HRPWM_FLTINR1_FLT0F_2 | HRPWM_FLTINR1_FLT0F_1,
+ /*!< fSAMPLING= fFLTS/32U, N=6U */
+ HRPWM_FAULTFILTER_15 = HRPWM_FLTINR1_FLT0F_3 | HRPWM_FLTINR1_FLT0F_2 | HRPWM_FLTINR1_FLT0F_1 | HRPWM_FLTINR1_FLT0F_0,
+ /*!< fSAMPLING= fFLTS/32U, N=8U */
+} HRPWM_FaultFilterETypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HRPWM_Fault_Counter HRPWM Fault counter threshold value
+ * @brief Constants defining the FAULT Counter threshold (FLTCNT + 1)
+ * @{
+ */
+typedef enum {
+ HRPWM_FAULTCOUNTER_NONE = 0x0,
+ /*!< Counter threshold = 0U */
+ HRPWM_FAULTCOUNTER_1 = HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 1U */
+ HRPWM_FAULTCOUNTER_2 = HRPWM_FLTINR3_FLT0CNT_1,
+ /*!< Counter threshold = 2U */
+ HRPWM_FAULTCOUNTER_3 = HRPWM_FLTINR3_FLT0CNT_1 | HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 3U */
+ HRPWM_FAULTCOUNTER_4 = HRPWM_FLTINR3_FLT0CNT_2,
+ /*!< Counter threshold = 4U */
+ HRPWM_FAULTCOUNTER_5 = HRPWM_FLTINR3_FLT0CNT_2 | HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 5U */
+ HRPWM_FAULTCOUNTER_6 = HRPWM_FLTINR3_FLT0CNT_2 | HRPWM_FLTINR3_FLT0CNT_1,
+ /*!< Counter threshold = 6U */
+ HRPWM_FAULTCOUNTER_7 = HRPWM_FLTINR3_FLT0CNT_2 | HRPWM_FLTINR3_FLT0CNT_1 | HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 7U */
+ HRPWM_FAULTCOUNTER_8 = HRPWM_FLTINR3_FLT0CNT_3,
+ /*!< Counter threshold = 8U */
+ HRPWM_FAULTCOUNTER_9 = HRPWM_FLTINR3_FLT0CNT_3 | HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 9U */
+ HRPWM_FAULTCOUNTER_10 = HRPWM_FLTINR3_FLT0CNT_3 | HRPWM_FLTINR3_FLT0CNT_1,
+ /*!< Counter threshold = 10U */
+ HRPWM_FAULTCOUNTER_11 = HRPWM_FLTINR3_FLT0CNT_3 | HRPWM_FLTINR3_FLT0CNT_1 | HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 11U */
+ HRPWM_FAULTCOUNTER_12 = HRPWM_FLTINR3_FLT0CNT_3 | HRPWM_FLTINR3_FLT0CNT_2,
+ /*!< Counter threshold = 12U */
+ HRPWM_FAULTCOUNTER_13 = HRPWM_FLTINR3_FLT0CNT_3 | HRPWM_FLTINR3_FLT0CNT_2 | HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 13U */
+ HRPWM_FAULTCOUNTER_14 = HRPWM_FLTINR3_FLT0CNT_3 | HRPWM_FLTINR3_FLT0CNT_2 | HRPWM_FLTINR3_FLT0CNT_1,
+ /*!< Counter threshold = 14U */
+ HRPWM_FAULTCOUNTER_15 = HRPWM_FLTINR3_FLT0CNT_3 | HRPWM_FLTINR3_FLT0CNT_2 | HRPWM_FLTINR3_FLT0CNT_1 | HRPWM_FLTINR3_FLT0CNT_0,
+ /*!< Counter threshold = 15U */
+} HRPWM_FaultCounterETypeDef;
+/**
+ * @}
+ */
+
+
+/**
+ * @brief HRPWM Master Timer Configuration Structure definition - Time base related parameters
+ */
+typedef struct __HRPWM_MasterSyncTypeDef {
+ uint32_t SyncOptions; /*!< Specifies how the HRPWM instance handles the external synchronization signals.
+ The HRPWM instance can be configured to act as a slave (waiting for a trigger
+ to be synchronized) or a master (generating a synchronization signal) or both.
+ This parameter can be a combination of @ref HRPWM_Synchronization_Options. */
+ HRPWM_SyncInputSrcETypeDef SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
+ the HRPWM instance is configured as a slave). */
+ HRPWM_SyncOutputSrcETypeDef SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
+ (significant only when the HRPWM instance is configured as a master). */
+ HRPWM_SyncOutputEnETypeDef SyncOutputEnable; /*!< Specifies the source and event to be sent on the external synchronization outputs
+ (significant only when the HRPWM is configured as a master).*/
+ HRPWM_SyncOutputPolETypeDef SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
+ outputs (significant only when the HRPWM instance is configured as a master). */
+} HRPWM_MasterSyncTypeDef;
+
+/**
+ * @brief Timer configuration definition -- Timerx (x=0...5) & Master timer
+ */
+typedef struct __HRPWM_TimerBaseCfgTypeDef {
+ uint32_t InterruptRequests; /*!< Relevant for all HRPWM timers, including the master.
+ Specifies which interrupts requests must enabled for the timer.
+ This parameter can be any combination of @ref HRPWM_Master_Interrupt_Enable
+ or @ref HRPWM_Timing_Unit_Interrupt_Enable */
+ uint32_t Period; /*!< Specifies the timer period.
+ The period value must be above 3 periods of the fHRPWM clock.
+ Maximum value is = 0xFFFDU */
+ uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ uint32_t ResetTrigger; /*!< Relevant for Timer0 to Timer5. no master timer.
+ Specifies source(s) triggering the timer counter reset.
+ This parameter can be a combination of @ref HRPWM_Timer_Reset_Trigger */
+ HRPWM_PrescalerRatioETypeDef PrescalerRatio;/*!< Specifies the timer clock prescaler ratio. */
+ HRPWM_ModeETypeDef Mode; /*!< Specifies the counter operating mode. continues or single */
+ HRPWM_SyncStartETypeDef StartOnSync; /*!< Relevant for all HRPWM timers, including the master.Specifies whether or
+ not timer is reset by a rising edge on the synchronization input (when enabled). */
+ HRPWM_SyncResetETypeDef ResetOnSync; /*!< Relevant for all HRPWM timers, including the master.Specifies whether or
+ not timer is reset by a rising edge on the synchronization input (when enabled). */
+ HRPWM_RsyncUpdateETypeDef ReSyncUpdate; /*!< Relevant for Timer0 to Timer5.Specifies whether update source is coming
+ from the timing unit @ref HRPWM_Timer_Resync_Update_Enable */
+
+} HRPWM_TimerBaseCfgTypeDef;
+
+/**
+ * @brief Simple output compare mode configuration definition -- Timerx (x=0...5) & Master timer
+ */
+typedef struct __HRPWM_TimerCompareCfgTypeDef {
+ HRPWM_PreloadEnETypeDef PreloadEnable; /*!< Relevant for all HRPWM timers, including the master.
+ Specifies whether or not register preload is enabled. */
+ uint32_t UpdateTrigger; /*!< Relevant for Timer0 to Timer5. no Master timer update source ;
+ Specifies source(s) triggering the timer registers update.
+ This parameter can be a combination of @ref HRPWM_Timer_Update_Trigger */
+ uint32_t CompareValueA; /*!< Specifies the compare A value of the timer compare unit.
+ The minimum value must be greater than or equal to 3 periods of the fHRPWM clock.
+ The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRPWM clock */
+ uint32_t CompareValueB; /*!< Specifies the compare B value of the timer compare unit.
+ The minimum value must be greater than or equal to 3 periods of the fHRPWM clock.
+ The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRPWM clock */
+ uint32_t CompareValueC; /*!< Specifies the compare C value of the timer compare unit.
+ The minimum value must be greater than or equal to 3 periods of the fHRPWM clock.
+ The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRPWM clock */
+ uint32_t CompareValueD; /*!< Specifies the compare D value of the timer compare unit.
+ The minimum value must be greater than or equal to 3 periods of the fHRPWM clock.
+ The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRPWM clock */
+} HRPWM_TimerCompareCfgTypeDef;
+
+/**
+ * @brief Timer RollOver definition -- Timerx (x=0...5)
+ */
+typedef struct __HRPWM_TimerRollOverCfgTypeDef {
+ HRPWM_CounterModeETypeDef UpDownMode; /*!< Relevant for Timer0 to Timer5.
+ Specifies whether or not counter is operating in up or up-down counting mode. */
+ HRPWM_RollOverETypeDef RollOverMode; /*!< Relevant for Timer0 to Timer5.
+ Roll over mode selection Settings are only valid in up-down counting mode. */
+ HRPWM_OutputRollOverETypeDef OutputRollOverMode;/*!< Relevant for Timer0 to Timer5.
+ Output roll over mode selection Settings, valid only in up-down counting mode. */
+ HRPWM_FltRollOverETypeDef FaultRollOverMode; /*!< Relevant for Timer0 to Timer5.
+ The fault roll over mode selection setting is only valid in up-down counting mode. */
+ HRPWM_EventRollOverETypeDef EeventRollOverMode;/*!< Relevant for Timer0 to Timer5.
+ The event roll over mode selection setting is only valid in up-down counting mode. */
+ HRPWM_AdcRollOverETypeDef AdcRollOverMode; /*!< Relevant for Timer0 to Timer5.
+ The ADDA trigger roll over mode selection setting is only valid in up-down counting mode. */
+} HRPWM_TimerRollOverCfgTypeDef;
+
+/**
+ * @brief Timer Daul Channel Dac definition -- Timerx (x=0...5)
+ */
+typedef struct __HRPWM_TimerDaulDacCfgTypeDef {
+ HRPWM_DacResetSelETypeDef DualChannelDacReset; /*!< Relevant for Timer0 to Timer5.
+ Specifies how the HRPWM_dac_reset_trgx trigger is generated. */
+ HRPWM_DacStepSelETypeDef DualChannelDacStep; /*!< Relevant for Timer0 to Timer5.
+ Specifies how the HRPWM_dac_step_trgx trigger is generated. */
+ HRPWM_DacTrigEnETypeDef DualChannelDacEnable; /*!< Relevant for Timer0 to Timer5.
+ Enables or not the dual channel DAC triggering mechanism. */
+} HRPWM_TimerDaulDacCfgTypeDef;
+
+/**
+ * @brief Output configuration definition -- Timerx (x=0...5)
+ */
+typedef struct __HRPWM_OutputCfgTypeDef {
+ HRPWM_OutputAPolETypeDef OutputAPolarity; /*!< Specifies the output polarity. */
+ HRPWM_IdelALevelETypeDef IdleALevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. */
+ HRPWM_FaultALevelETypeDef FaultALevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. */
+ HRPWM_ChopperAEnETypeDef ChopperAModeEnable; /*!< Indicates whether or not the chopper mode is enabled*/
+ HRPWM_OutputBPolETypeDef OutputBPolarity; /*!< Specifies the output polarity.*/
+ HRPWM_IdelBLevelETypeDef IdleBLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. */
+ HRPWM_FaultBLevelETypeDef FaultBLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. */
+ HRPWM_ChopperBEnETypeDef ChopperBModeEnable; /*!< Indicates whether or not the chopper mode is enabled */
+ uint32_t OutputASetSource; /*!< A channel output action set source event selection
+ This parameter can be combination value of @ref HRPWM_Timer_Set_Trigger */
+ uint32_t OutputAClearSource; /*!< A channel output action clear source event selection
+ This parameter can be combination value of @ref HRPWM_Timer_Clear_Trigger */
+ uint32_t OutputBSetSource; /*!< B channel output action set source event selection
+ This parameter can be combination value of @ref HRPWM_Timer_Set_Trigger */
+ uint32_t OutputBClearSource; /*!< B channel output action clear source event selection
+ This parameter can be combination value of @ref HRPWM_Timer_Clear_Trigger */
+} HRPWM_OutputCfgTypeDef;
+
+/**
+ * @brief Dead time feature configuration definition -- Timerx (x=0...5)
+ */
+typedef struct __HRPWM_DeadTimeCfgTypeDef {
+ LL_FuncStatusETypeDef DeadTimeEn; /*!< Specifies the dead-time output enable */
+
+ uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge.
+ This parameter can be a number between 0x0 and 0xFFFU */
+ HRPWM_DeadTimeRiseSignETypeDef RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge. */
+ uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge.
+ This parameter can be a number between 0x0 and 0xFFFU */
+ HRPWM_DeadTimeFallSignETypeDef FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge. */
+} HRPWM_DeadTimeCfgTypeDef;
+
+/**
+ * @brief Chopper mode configuration definition -- Timerx (x=0...5)
+ */
+typedef struct __HRPWM_ChopperModeCfgTypeDef {
+ HRPWM_ChopperAEnETypeDef ChopperAModeEnable; /*!< Indicates whether or not the chopper mode is enabled */
+ HRPWM_ChopperBEnETypeDef ChopperBModeEnable; /*!< Indicates whether or not the chopper mode is enabled */
+ HRPWM_ChopperCarfreqETypeDef CarrierFreq; /*!< Specifies the Timer carrier frequency value. */
+ HRPWM_ChopperDutyETypeDef DutyCycle; /*!< Specifies the Timer chopper duty cycle value. */
+ HRPWM_ChopperPulseWidthETypeDef StartPulse; /*!< Specifies the Timer pulse width value. */
+} HRPWM_ChopperModeCfgTypeDef;
+
+/**
+ * @brief External event filtering in timing units configuration definition -- Timerx (x=0...5)
+ */
+typedef struct __HRPWM_TimerEventFilteringCfgTypeDef {
+ HRPWM_EventAFilterWindowETypeDef Filter; /*!< Specifies the type of event filtering within the timing unit. */
+ HRPWM_EventALatchETypeDef Latch; /*!< Specifies whether or not the signal is latched. */
+} HRPWM_TimerEventFilteringCfgTypeDef;
+
+/**
+ * @brief External Event Counter A configuration definition -- Timerx (x=0...5)
+ */
+typedef struct __HRPWM_ExternalEventACfgTypeDef {
+ HRPWM_EventACouterEnETypeDef CounterEnable; /*!< Specifies the External Event A Counter enable. */
+ HRPWM_EventARstModeETypeDef ResetMode; /*!< Specifies the External Event A Counte Reset Mode. */
+ HRPWM_EventASourceSelETypeDef Source; /*!< Specifies the External Event A Counter source selection. */
+ uint32_t Counter; /*!< Specifies the External Event A Counter Threshold.
+ This parameter can be a number between 0x0 and 0x3F */
+} HRPWM_ExternalEventACfgTypeDef;
+
+/**
+ * @brief External event channel configuration definition -- common timer
+ */
+typedef struct __HRPWM_EventCfgTypeDef {
+ HRPWM_EventSrcSelETypeDef Source; /*!< Identifies the source of the external event. */
+ HRPWM_EventPolETypeDef Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). */
+ HRPWM_EventSensETypeDef Sensitivity; /*!< Specifies the sensitivity of the external event. */
+ HRPWM_EventPrescalerETypeDef SampClockDiv; /*!< External event sampling time frequency division ratio. */
+ HRPWM_EventFilterETypeDef Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. */
+ HRPWM_EventFastModeETypeDef FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event. */
+} HRPWM_EventCfgTypeDef;
+
+/**
+ * @brief Fault channel configuration definition -- common timer
+ */
+typedef struct __HRPWM_FaultCfgTypeDef {
+ uint32_t InterruptEn; /*!< Relevant for comon timer.
+ Specifies which interrupts requests must enabled for comon timer.
+ This parameter can be any combination of @ref HRPWM_Common_Interrupt_Enable */
+ HRPWM_FaultSrcSelETypeDef Source; /*!< Identifies the source of the fault. */
+ HRPWM_FaultPolETypeDef Polarity; /*!< Specifies the polarity of the fault event. */
+ HRPWM_FaultPrescalerETypeDef SampClockDiv; /*!< Fault signal sampling time frequency division ratio. */
+ HRPWM_FaultFilterETypeDef Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter. */
+ HRPWM_FaultEnETypeDef Enable; /*!< Corresponding fault sampling enablement. */
+} HRPWM_FaultCfgTypeDef;
+
+/**
+ * @brief Fault channel configuration blanking definition -- common timer
+ */
+typedef struct __HRPWM_FaultBlankingCfgTypeDef {
+ HRPWM_FaultCounterETypeDef Threshold; /*!< Specifies the Fault counter Threshold. */
+ HRPWM_FaultBlkEnETypeDef BlankingEnable; /*!< Specifies the Fault blanking enablement. */
+ HRPWM_FaultRstModeETypeDef ResetMode; /*!< Specifies the reset mode of a fault event counter. */
+ HRPWM_FaultBlkWindowETypeDef BlankingSource;/*!< Specifies the blanking source of a fault event. */
+} HRPWM_FaultBlankingCfgTypeDef;
+
+/**
+ * @brief ADC trigger configuration definition -- common timer
+ */
+typedef struct __HRPWM_ADCTriggerCfgTypeDef {
+ uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
+ This parameter can be a combination of @ref HRPWM_ADC_Trigger_Event */
+ HRPWM_AdcTrigGroupETypeDef TriggerGroup; /*!< Specifies the ADC trigger group 0~7. */
+ HRPWM_AdcTrigUpdateSrcETypeDef UpdateSource;/*!< Specifies the ADC trigger update source. */
+ HRPWM_AdcTrigLengthETypeDef TriggerLength; /*!< Specifies the event(s) triggering the ADC\DAC conversion.In practical use,
+ the length configuration should be greater than 3 clocks. For example,
+ under a 160M clock, the minimum configuration value is 0x3; */
+ HRPWM_AdcTrigPSCETypeDef TriggerPostScaler; /*!< Specifies the event(s) triggering the ADC\DAC conversion. */
+} HRPWM_ADCTriggerCfgTypeDef;
+
+/**
+ * @brief HRPWM DLL start configuration definition -- common timer
+ */
+typedef struct __HRPWM_DLLCfgTypedef {
+ HRPWM_DllCurrentETypeDef CurrentSel;/*!< Configure DLL current selection. */
+ uint32_t ClockDelayThres0; /*!< DLL Clock Delay Threshold. CLKPHASE = PULPHASE - DLLTHRES0. range : 0~0x1F */
+ uint32_t ClockDelayThres1; /*!< DLL Clock Delay Threshold. CLKPHASE <= DLLTHRES1 :
+ Sample hrpwm_clk Pulse CLKPHASE > DLLTHRES1 : Sample hrpwm_dly_clk Pulse. range : 0~0x1F */
+} HRPWM_DLLCfgTypedef;
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HRPWM_LL_Exported_Macros HRPWM LL Exported Macros
+ * @brief HRPWM LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief swap the output of the timer
+ * HRPWM_SETA1R and HRPWM_RSTAR are coding for the output B,
+ * HRPWM_SETA2R and HRPWM_RSTAR are coding for the output B
+ * @note Push pull mode setting is invalid
+ * @param __TIMER__ : Timer index
+ * This parameter can be a combination of the following values:
+ * @arg HRPWM_SWAP_SLAVE_0
+ * @arg HRPWM_SWAP_SLAVE_1
+ * @arg HRPWM_SWAP_SLAVE_2
+ * @arg HRPWM_SWAP_SLAVE_3
+ * @arg HRPWM_SWAP_SLAVE_4
+ * @arg HRPWM_SWAP_SLAVE_5
+ * @retval none
+ */
+#define __LL_HRPWM_OUTPUT_SWAP(__TIMER__) \
+ MODIFY_REG(HRPWM->Common.CR1, HRPWM_CR1_SWP5 | HRPWM_CR1_SWP5 | HRPWM_CR1_SWP5 | HRPWM_CR1_SWP5 | HRPWM_CR1_SWP5, __TIMER__)
+
+/**
+ * @brief swap the output of the timer
+ * HRPWM_SETAR and HRPWM_RSTAR are coding for the output B,
+ * HRPWM_SETAR and HRPWM_RSTAR are coding for the output B
+ * @note Push pull mode setting is invalid
+ * @param __TIMER__ : Timer index
+ * This parameter Only one of the values can be selected, not a combination:
+ * @arg HRPWM_SWAP_SLAVE_0
+ * @arg HRPWM_SWAP_SLAVE_1
+ * @arg HRPWM_SWAP_SLAVE_2
+ * @arg HRPWM_SWAP_SLAVE_3
+ * @arg HRPWM_SWAP_SLAVE_4
+ * @arg HRPWM_SWAP_SLAVE_5
+ * @retval none
+ */
+#define __LL_HRPWM_TIMER_OUTPUT_SWAP(__TIMER__) SET_BIT(HRPWM->Common.CR1, __TIMER__)
+
+/**
+ * @brief Un-swap the output of the timer
+ * HRPWM_SETAR and HRPWM_RSTAR are coding for the output A,
+ * HRPWM_SETAR and HRPWM_RSTAR are coding for the output A
+ * @note Push pull mode setting is invalid
+ * @param __TIMER__ : Timer index
+ * This parameter Only one of the values can be selected, not a combination:
+ * @arg HRPWM_SWAP_SLAVE_0
+ * @arg HRPWM_SWAP_SLAVE_1
+ * @arg HRPWM_SWAP_SLAVE_2
+ * @arg HRPWM_SWAP_SLAVE_3
+ * @arg HRPWM_SWAP_SLAVE_4
+ * @arg HRPWM_SWAP_SLAVE_5
+ * @retval none
+ */
+#define __LL_HRPWM_TIMER_OUTPUT_NOSWAP(__TIMER__) CLEAR_BIT(HRPWM->Common.CR1, __TIMER__)
+
+/** @brief Enables or disables the specified HRPWM common interrupts.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_IT_FLT0: Fault 0 interrupt enable
+ * @arg HRPWM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRPWM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRPWM_IT_FLT3: Fault 3 interrupt enable
+ * @arg HRPWM_IT_FLT4: Fault 4 interrupt enable
+ * @arg HRPWM_IT_FLT5: Fault 5 interrupt enable
+ * @arg HRPWM_IT_SYSFLT: System Fault interrupt enable
+ * @retval None
+ */
+#define __LL_HRPWM_ENABLE_IT(__INTERRUPT__) (HRPWM->Common.IER |= (__INTERRUPT__))
+#define __LL_HRPWM_DISABLE_IT(__INTERRUPT__) (HRPWM->Common.IER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRPWM Master timer interrupts.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_MASTER_IT_MPER: Master Period interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPA: Master compare A interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPB: Master compare B interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPC: Master compare C interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPD: Master compare D interrupt enable
+ * @arg HRPWM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRPWM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRPWM_MASTER_IT_MUPD: Master update interrupt enable
+ * @retval None
+ */
+#define __LL_HRPWM_MASTER_ENABLE_IT(__INTERRUPT__) (HRPWM->Master.MIER |= (__INTERRUPT__))
+#define __LL_HRPWM_MASTER_DISABLE_IT(__INTERRUPT__) (HRPWM->Master.MIER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRPWM Timerx interrupts.
+ * @param __TIMER__ specified the timing unit (Timer 0 to 5)
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_IT_PER: Timer Period interrupt enable
+ * @arg HRPWM_IT_CMPA: Timer compare 1 interrupt enable
+ * @arg HRPWM_IT_CMP2: Timer compare 2 interrupt enable
+ * @arg HRPWM_IT_CMP3: Timer compare 3 interrupt enable
+ * @arg HRPWM_IT_CMP4: Timer compare 4 interrupt enable
+ * @arg HRPWM_IT_SETA: Timer output 1 set interrupt enable
+ * @arg HRPWM_IT_RSTA: Timer output 1 reset interrupt enable
+ * @arg HRPWM_IT_SETB: Timer output 2 set interrupt enable
+ * @arg HRPWM_IT_RSTB: Timer output 2 reset interrupt enable
+ * @arg HRPWM_IT_RST: Timer reset interrupt enable
+ * @arg HRPWM_IT_REP: Timer repetition interrupt enable
+ * @arg HRPWM_IT_UPD: Timer update interrupt enable
+ * @arg HRPWM_IT_DLYPRT: Timer delay protection interrupt enable
+ * @retval None
+ */
+#define __LL_HRPWM_TIMER_ENABLE_IT(__TIMER__, __INTERRUPT__) (HRPWM->PWM[(__TIMER__)].IER |= (__INTERRUPT__))
+#define __LL_HRPWM_TIMER_DISABLE_IT(__TIMER__, __INTERRUPT__) (HRPWM->PWM[(__TIMER__)].IER &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified HRPWM common interrupt source is enabled or disabled.
+ * @param __INTERRUPT__ specifies the interrupt source to check.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_IT_FLT0: Fault 0 interrupt enable
+ * @arg HRPWM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRPWM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRPWM_IT_FLT3: Fault 3 interrupt enable
+ * @arg HRPWM_IT_FLT4: Fault 4 interrupt enable
+ * @arg HRPWM_IT_FLT5: Fault 5 interrupt enable
+ * @arg HRPWM_IT_SYSFLT: System Fault interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __LL_HRPWM_GET_IT(__INTERRUPT__) (((HRPWM->Common.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if the specified HRPWM Master interrupt source is enabled or disabled.
+ * @param __INTERRUPT__ specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_MASTER_IT_MPER: Master Period interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPA: Master compare A interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPB: Master compare B interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPC: Master compare C interrupt enable
+ * @arg HRPWM_MASTER_IT_MCMPD: Master compare D interrupt enable
+ * @arg HRPWM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRPWM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRPWM_MASTER_IT_MUPD: Master update interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __LL_HRPWM_MASTER_GET_IT(__INTERRUPT__) (((HRPWM->Master.MIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if the specified HRPWM Timerx interrupt source is enabled or disabled.
+ * @param __TIMER__ specified the timing unit (Timer 0 to 5)
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_IT_PER: Timer Period interrupt enable
+ * @arg HRPWM_IT_CMPA: Timer compare A interrupt enable
+ * @arg HRPWM_IT_CMPB: Timer compare B interrupt enable
+ * @arg HRPWM_IT_CMPC: Timer compare C interrupt enable
+ * @arg HRPWM_IT_CMPD: Timer compare D interrupt enable
+ * @arg HRPWM_IT_SETA: Timer output A set interrupt enable
+ * @arg HRPWM_IT_RSTA: Timer output A reset interrupt enable
+ * @arg HRPWM_IT_SETB: Timer output B set interrupt enable
+ * @arg HRPWM_IT_RSTB: Timer output B reset interrupt enable
+ * @arg HRPWM_IT_RST: Timer reset interrupt enable
+ * @arg HRPWM_IT_REP: Timer repetition interrupt enable
+ * @arg HRPWM_IT_UPD: Timer update interrupt enable
+ * @arg HRPWM_IT_DLYPRT: Timer delay protection interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __LL_HRPWM_TIMER_GET_IT(__TIMER__, __INTERRUPT__) \
+ (((HRPWM->PWM[(__TIMER__)].IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Get the specified HRPWM common pending flag.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FLAG_FLT0: Fault 0 flag
+ * @arg HRPWM_FLAG_FLT1: Fault 1 flag
+ * @arg HRPWM_FLAG_FLT2: Fault 2 flag
+ * @arg HRPWM_FLAG_FLT3: Fault 3 flag
+ * @arg HRPWM_FLAG_FLT4: Fault 4 flag
+ * @arg HRPWM_FLAG_FLT5: Fault 5 flag
+ * @arg HRPWM_FLAG_SYSFLT: System Fault interrupt flag
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __LL_HRPWM_GET_ITFLAG(__INTERRUPT__) (((HRPWM->Common.ISR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Get the specified HRPWM Master pending flag.
+ * @param __INTERRUPT__ specifies the interrupt pending bit.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_MASTER_FLAG_MPER: Master Period interrupt flag
+ * @arg HRPWM_MASTER_FLAG_MCMPA: Master compare A interrupt flag
+ * @arg HRPWM_MASTER_FLAG_MCMPB: Master compare B interrupt flag
+ * @arg HRPWM_MASTER_FLAG_MCMPC: Master compare C interrupt flag
+ * @arg HRPWM_MASTER_FLAG_MCMPD: Master compare D interrupt flag
+ * @arg HRPWM_MASTER_FLAG_MREP: Master Repetition interrupt flag
+ * @arg HRPWM_MASTER_FLAG_SYNC: Synchronization input interrupt flag
+ * @arg HRPWM_MASTER_FLAG_MUPD: Master update interrupt flag
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __LL_HRPWM_MASTER_GET_ITFLAG(__INTERRUPT__) \
+ (((HRPWM->Master.MISR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Get the specified HRPWM Timerx pending flag.
+ * @param __TIMER__ specified the timing unit (Timer 0 to 5)
+ * @param __INTERRUPT__ specifies the interrupt pending bit.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FLAG_PER: Timer Period interrupt flag
+ * @arg HRPWM_FLAG_CMPA: Timer compare A interrupt flag
+ * @arg HRPWM_FLAG_CMPB: Timer compare B interrupt flag
+ * @arg HRPWM_FLAG_CMPC: Timer compare C interrupt flag
+ * @arg HRPWM_FLAG_CMPD: Timer compare D interrupt flag
+ * @arg HRPWM_FLAG_SETA: Timer output A set interrupt flag
+ * @arg HRPWM_FLAG_RSTA: Timer output A reset interrupt flag
+ * @arg HRPWM_FLAG_SETB: Timer output B set interrupt flag
+ * @arg HRPWM_FLAG_RSTB: Timer output B reset interrupt flag
+ * @arg HRPWM_FLAG_RST: Timer reset interrupt flag
+ * @arg HRPWM_FLAG_REP: Timer repetition interrupt flag
+ * @arg HRPWM_FLAG_UPD: Timer update interrupt flag
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __LL_HRPWM_TIMER_GET_ITFLAG(__TIMER__, __INTERRUPT__) \
+ (((HRPWM->PWM[(__TIMER__)].ISR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+
+/** @brief Clears the specified HRPWM common pending flag.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FLAG_FLT0: Fault 0 clear flag
+ * @arg HRPWM_FLAG_FLT1: Fault 1 clear flag
+ * @arg HRPWM_FLAG_FLT2: Fault 2 clear flag
+ * @arg HRPWM_FLAG_FLT3: Fault 3 clear flag
+ * @arg HRPWM_FLAG_FLT4: Fault 4 clear flag
+ * @arg HRPWM_FLAG_FLT5: Fault 5 clear flag
+ * @arg HRPWM_FLAG_SYSFLT: System Fault interrupt clear flag
+ * @retval None
+ */
+#define __LL_HRPWM_CLEAR_ITFLAG(__INTERRUPT__) (HRPWM->Common.ISR = (__INTERRUPT__))
+
+/** @brief Clears the specified HRPWM Master pending flag.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_MASTER_FLAG_MPER: Master Period interrupt clear flag
+ * @arg HRPWM_MASTER_FLAG_MCMPA: Master compare A interrupt clear flag
+ * @arg HRPWM_MASTER_FLAG_MCMPB: Master compare B interrupt clear flag
+ * @arg HRPWM_MASTER_FLAG_MCMPC: Master compare C interrupt clear flag
+ * @arg HRPWM_MASTER_FLAG_MCMPD: Master compare D interrupt clear flag
+ * @arg HRPWM_MASTER_FLAG_MREP: Master Repetition interrupt clear flag
+ * @arg HRPWM_MASTER_FLAG_SYNC: Synchronization input interrupt clear flag
+ * @arg HRPWM_MASTER_FLAG_MUPD: Master update interrupt clear flag
+ * @retval None
+ */
+#define __LL_HRPWM_MASTER_CLEAR_ITFLAG(__INTERRUPT__) (HRPWM->Master.MISR = (__INTERRUPT__))
+
+/** @brief Clears the specified HRPWM Timerx pending flag.
+ * @param __TIMER__ specified the timing unit (Timer A to F)
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FLAG_PER: Timer Period interrupt clear flag
+ * @arg HRPWM_FLAG_CMPA: Timer compare A interrupt clear flag
+ * @arg HRPWM_FLAG_CMPB: Timer compare B interrupt clear flag
+ * @arg HRPWM_FLAG_CMPC: Timer compare C interrupt clear flag
+ * @arg HRPWM_FLAG_CMPD: Timer compare D interrupt clear flag
+ * @arg HRPWM_FLAG_SETA: Timer output A set interrupt clear flag
+ * @arg HRPWM_FLAG_RSTA: Timer output A reset interrupt clear flag
+ * @arg HRPWM_FLAG_SETB: Timer output B set interrupt clear flag
+ * @arg HRPWM_FLAG_RSTB: Timer output B reset interrupt clear flag
+ * @arg HRPWM_FLAG_RST: Timer reset interrupt clear flag
+ * @arg HRPWM_FLAG_REP: Timer repetition interrupt clear flag
+ * @arg HRPWM_FLAG_UPD: Timer update interrupt clear flag
+ * @retval None
+ */
+#define __LL_HRPWM_TIMER_CLEAR_ITFLAG(__TIMER__, __INTERRUPT__) (HRPWM->PWM[(__TIMER__)].ISR = (__INTERRUPT__))
+
+/** @brief Sets the HRPWM timer Period value on runtime
+ * @param __TIMER__ HRPWM timer
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __PERIOD__ specifies the Period Register new value.
+ * @retval None
+ */
+#define __LL_HRPWM_SETPERIOD(__TIMER__, __PERIOD__) \
+ (((__TIMER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MPER = (__PERIOD__)) :\
+ (HRPWM->PWM[(__TIMER__)].PERR = (__PERIOD__)))
+
+/** @brief Gets the HRPWM timer Period Register value on runtime
+ * @param __TIMER__ HRPWM timer
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @retval timer Period Register
+ */
+#define __LL_HRPWM_GETPERIOD(__TIMER__) \
+ (((__TIMER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MPER) : (HRPWM->PWM[(__TIMER__)].PERR))
+
+
+/** @brief Sets the HRPWM timer clock prescaler value on runtime
+ * @param __TIMER__ HRPWM timer
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __PRESCALER__ specifies the clock prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_PRESCALERRATIO_MUL32: fHRCK: fHRPWM x 32U = 5.12 GHz - Resolution: 195 ps (fHRPWM=144MHz)
+ * @arg HRPWM_PRESCALERRATIO_MUL16: fHRCK: fHRPWM x 16U = 2.56 GHz - Resolution: 390 ps (fHRPWM=144MHz)
+ * @arg HRPWM_PRESCALERRATIO_MUL8: fHRCK: fHRPWM x 8U = 1.28 GHz - Resolution: 781 ps (fHRPWM=144MHz)
+ * @arg HRPWM_PRESCALERRATIO_MUL4: fHRCK: fHRPWM x 4U = 640 MHz - Resolution: 1.56 ns (fHRPWM=144MHz)
+ * @arg HRPWM_PRESCALERRATIO_MUL2: fHRCK: fHRPWM x 2U = 320 MHz - Resolution: 3.125 ns (fHRPWM=144MHz)
+ * @arg HRPWM_PRESCALERRATIO_DIV1: fHRCK: fHRPWM = 160 MHz - Resolution: 6.25 ns (fHRPWM=144MHz)
+ * @arg HRPWM_PRESCALERRATIO_DIV2: fHRCK: fHRPWM / 2U = 80 MHz - Resolution: 12.5 ns (fHRPWM=144MHz)
+ * @arg HRPWM_PRESCALERRATIO_DIV4: fHRCK: fHRPWM / 4U = 40 MHz - Resolution: 25 ns (fHRPWM=144MHz)
+ * @retval None
+ */
+#define __LL_HRPWM_SETCLOCKPRESCALER(__TIMER__, __PRESCALER__) \
+ (((__TIMER__) == HRPWM_INDEX_MASTER) ? (MODIFY_REG(HRPWM->Master.MCR, HRPWM_MCR_CKPSC, (__PRESCALER__))) :\
+ (MODIFY_REG(HRPWM->PWM[(__TIMER__)].CR0, HRPWM_CR0_CKPSC, (__PRESCALER__))))
+
+/** @brief Gets the HRPWM timer clock prescaler value on runtime
+ * @param __TIMER__ HRPWM timer
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @retval timer clock prescaler value
+ */
+#define __LL_HRPWM_GETCLOCKPRESCALER(__TIMER__) \
+ (((__TIMER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCR & HRPWM_MCR_CKPSC) : \
+ (HRPWM->PWM[(__TIMER__)].CR0 & HRPWM_CR0_CKPSC))
+
+/** @brief Sets the HRPWM timer Compare Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __COMPAREUNIT__ timer compare unit
+ * This parameter can be one of the following values:
+ * @arg HRPWM_COMPAREUNIT_A: Compare A
+ * @arg HRPWM_COMPAREUNIT_B: Compare B
+ * @arg HRPWM_COMPAREUNIT_C: Compare C
+ * @arg HRPWM_COMPAREUNIT_D: Compare D
+ * @param __COMPARE__ specifies the Compare new value.
+ * @retval None
+ */
+#define __LL_HRPWM_SETCOMPARE(__TIMER__, __COMPAREUNIT__, __COMPARE__) \
+ (((__TIMER__) == HRPWM_INDEX_MASTER) ? \
+ (((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_A) ? (HRPWM->Master.MCMPAR = (__COMPARE__)) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_B) ? (HRPWM->Master.MCMPBR = (__COMPARE__)) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_C) ? (HRPWM->Master.MCMPCR = (__COMPARE__)) : \
+ (HRPWM->Master.MCMPDR = (__COMPARE__))) \
+ : \
+ (((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_A) ? (HRPWM->PWM[(__TIMER__)].CMPAR = (__COMPARE__)) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_B) ? (HRPWM->PWM[(__TIMER__)].CMPBR = (__COMPARE__)) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_C) ? (HRPWM->PWM[(__TIMER__)].CMPCR = (__COMPARE__)) : \
+ (HRPWM->PWM[(__TIMER__)].CMPDR = (__COMPARE__))))
+
+/** @brief Gets the HRPWM timer Compare Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __COMPAREUNIT__ timer compare unit
+ * This parameter can be one of the following values:
+ * @arg HRPWM_COMPAREUNIT_A: Compare A
+ * @arg HRPWM_COMPAREUNIT_B: Compare B
+ * @arg HRPWM_COMPAREUNIT_C: Compare C
+ * @arg HRPWM_COMPAREUNIT_D: Compare D
+ * @retval Compare value
+ */
+#define __LL_HRPWM_GETCOMPARE(__TIMER__, __COMPAREUNIT__) \
+ (((__TIMER__) == HRPWM_INDEX_MASTER) ? \
+ (((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_A) ? (HRPWM->Master.MCMPAR) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_B) ? (HRPWM->Master.MCMPBR) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_C) ? (HRPWM->Master.MCMPCR) : \
+ (HRPWM->Master.MCMPDR)) \
+ : \
+ (((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_A) ? (HRPWM->PWM[(__TIMER__)].CMPAR) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_B) ? (HRPWM->PWM[(__TIMER__)].CMPBR) : \
+ ((__COMPAREUNIT__) == HRPWM_COMPAREUNIT_C) ? (HRPWM->PWM[(__TIMER__)].CMPCR) : \
+ (HRPWM->PWM[(__TIMER__)].CMPDR)))
+
+/** @brief Sets the HRPWM timer Compare A Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __VALUE__ specifies the Compare new value.
+ * @retval None
+ */
+#define __LL_HRPWM_SETCOMPARE_A(__TINER__, __VALUE__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPAR = (__VALUE__)) : \
+ (HRPWM->PWM[(__TINER__)].CMPAR = (__VALUE__)))
+
+/** @brief Sets the HRPWM timer Compare B Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __VALUE__ specifies the Compare new value.
+ * @retval None
+ */
+#define __LL_HRPWM_SETCOMPARE_B(__TINER__, __VALUE__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPBR = (__VALUE__)) : \
+ (HRPWM->PWM[(__TINER__)].CMPBR = (__VALUE__)))
+
+/** @brief Sets the HRPWM timer Compare C Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __VALUE__ specifies the Compare new value.
+ * @retval None
+ */
+#define __LL_HRPWM_SETCOMPARE_C(__TINER__, __VALUE__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPCR = (__VALUE__)) : \
+ (HRPWM->PWM[(__TINER__)].CMPCR = (__VALUE__)))
+
+/** @brief Sets the HRPWM timer Compare A Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @param __VALUE__ specifies the Compare new value.
+ * @retval None
+ */
+#define __LL_HRPWM_SETCOMPARE_D(__TINER__, __VALUE__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPDR = (__VALUE__)) : \
+ (HRPWM->PWM[(__TINER__)].CMPDR = (__VALUE__)))
+
+
+/** @brief Gets the HRPWM timer Compare A Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @retval Compare value
+ */
+
+#define __LL_HRPWM_GETCOMPARE_A(__TINER__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPAR) :(HRPWM->PWM[(__TINER__)].CMPAR))
+
+/** @brief Gets the HRPWM timer Compare B Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @retval Compare value
+ */
+
+#define __LL_HRPWM_GETCOMPARE_B(__TINER__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPBR) : (HRPWM->PWM[(__TINER__)].CMPBR))
+
+/** @brief Gets the HRPWM timer Compare C Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @retval Compare value
+ */
+
+#define __LL_HRPWM_GETCOMPARE_C(__TINER__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPCR) : (HRPWM->PWM[(__TINER__)].CMPCR))
+
+/** @brief Gets the HRPWM timer Compare D Register value on runtime
+ * @param __TIMER__ HRPWM timer (not is commmon timer)
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @retval Compare value
+ */
+
+#define __LL_HRPWM_GETCOMPARE_D(__TINER__) \
+ (((__TINER__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCMPDR) : (HRPWM->PWM[(__TINER__)].CMPDR))
+
+
+/** @brief Enables or disables the timer counter(s)
+ * @param __TIMERS__ timers to enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Slave pwm 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Slave pwm 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Slave pwm 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Slave pwm 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Slave pwm 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Slave pwm 5 identifier
+ * @retval None
+ */
+#define __LL_HRPWM_TIMER_ENABLE(__TIMERS__) \
+ (((__TIMERS__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCR |= HRPWM_MCR_MCEN) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_0) ? (HRPWM->Master.MCR |= HRPWM_MCR_CEN0) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_1) ? (HRPWM->Master.MCR |= HRPWM_MCR_CEN1) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_2) ? (HRPWM->Master.MCR |= HRPWM_MCR_CEN2) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_3) ? (HRPWM->Master.MCR |= HRPWM_MCR_CEN3) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_4) ? (HRPWM->Master.MCR |= HRPWM_MCR_CEN4) : \
+ ((HRPWM->Master.MCR |= HRPWM_MCR_CEN5)))
+
+
+#define __LL_HRPWM_TIMER_DISABLE(__TIMERS__) \
+ (((__TIMERS__) == HRPWM_INDEX_MASTER) ? (HRPWM->Master.MCR &= ~(HRPWM_MCR_MCEN)) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_0) ? (HRPWM->Master.MCR &= ~(HRPWM_MCR_CEN0)) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_1) ? (HRPWM->Master.MCR &= ~(HRPWM_MCR_CEN1)) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_2) ? (HRPWM->Master.MCR &= ~(HRPWM_MCR_CEN2)) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_3) ? (HRPWM->Master.MCR &= ~(HRPWM_MCR_CEN3)) : \
+ ((__TIMERS__) == HRPWM_INDEX_SLAVE_4) ? (HRPWM->Master.MCR &= ~(HRPWM_MCR_CEN4)) : \
+ ((HRPWM->Master.MCR &= ~(HRPWM_MCR_CEN5))))
+
+/** @brief Enables ALL the timer counter(s)
+ * @param __INSTANCE__ HRPWM HANDLE
+ * @retval None
+ */
+#define __LL_HRPWM_ALL_TIMER_ENABLE(__INSTANCE__) \
+ (SET_BIT((__INSTANCE__)->Master.MCR, \
+ HRPWM_MCR_MCEN | HRPWM_MCR_CEN0 | HRPWM_MCR_CEN1 | HRPWM_MCR_CEN2 | HRPWM_MCR_CEN3 | HRPWM_MCR_CEN4 | HRPWM_MCR_CEN5))
+
+/** @brief Disables the timer counter(s)
+ * @param __INSTANCE__ HRPWM HANDLE
+ * @retval None
+ */
+#define __LL_HRPWM_ALL_TIMER_DISABLE(__INSTANCE__) \
+ (CLEAR_BIT((__INSTANCE__)->Master.MCR, \
+ HRPWM_MCR_MCEN | HRPWM_MCR_CEN0 | HRPWM_MCR_CEN1 | HRPWM_MCR_CEN2 | HRPWM_MCR_CEN3 | HRPWM_MCR_CEN4 | HRPWM_MCR_CEN5))
+
+
+/** @brief Modify the length of the dead zone
+ * @param __TIMERS__ timers to enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Timer 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Timer 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Timer 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Timer 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Timer 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Timer 5 identifier
+ * @param __VALUES__ timer dead timer value the range of value is 0 ~ 0xfff
+ * @retval None
+ */
+#define __LL_HRPWM_DEADTIME_RISE_VALUE(__TIMERS__, __VALUES__) \
+ MODIFY_REG(HRPWM->PWM[__TIMERS__].DTR, HRPWM_DTR_DTR, (__VALUES__))
+
+#define __LL_HRPWM_DEADTIME_FALL_VALUE(__TIMERS__, __VALUES__) \
+ MODIFY_REG(HRPWM->PWM[__TIMERS__].DTR, HRPWM_DTR_DTF, ((__VALUES__) << 16U))
+
+/** @brief Modify the length of the dead zone
+ * @param __TIMERS__ timers to enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Timer 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Timer 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Timer 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Timer 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Timer 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Timer 5 identifier
+ * @param __SIGN__ timer dead timer sign
+ * HRPWM_Deadtime_Rising_Sign: HRPWM_DEADTIME_RSIGN_NEGATIVE \ HRPWM_DEADTIME_RSIGN_POSITIVE
+ * HRPWM_Deadtime_Falling_Sign: HRPWM_DEADTIME_FSIGN_NEGATIVE \ HRPWM_DEADTIME_FSIGN_POSITIVE
+ * @retval None
+ */
+#define __LL_HRPWM_DEADTIME_RISE_SIGN(__TIMERS__, __SIGN__) MODIFY_REG(HRPWM->PWM[__TIMERS__].DTR, HRPWM_DTR_SDTR, (__SIGN__))
+
+#define __LL_HRPWM_DEADTIME_FALL_SIGN(__TIMERS__, __SIGN__) MODIFY_REG(HRPWM->PWM[__TIMERS__].DTR, HRPWM_DTR_SDTF, (__SIGN__))
+
+
+/** @brief Start output wave
+ * @param __OUTPUT__ timers start output wave @ HRPWM_Timer_Output_Start
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_OUTPUT_OEN0A
+ * @arg HRPWM_OUTPUT_OEN0B
+ * @arg HRPWM_OUTPUT_OEN1A
+ * @arg HRPWM_OUTPUT_OEN1B
+ * @arg HRPWM_OUTPUT_OEN2A
+ * @arg HRPWM_OUTPUT_OEN2B
+ * @arg HRPWM_OUTPUT_OEN3A
+ * @arg HRPWM_OUTPUT_OEN3B
+ * @arg HRPWM_OUTPUT_OEN4A
+ * @arg HRPWM_OUTPUT_OEN4B
+ * @arg HRPWM_OUTPUT_OEN5A
+ * @arg HRPWM_OUTPUT_OEN5B
+ * @retval None
+ */
+#define __LL_HRPWM_OUTPUT_START(__OUTPUT__) SET_BIT(HRPWM->Common.OENR, (__OUTPUT__))
+
+/** @brief Stop output wave
+ * @param __OUTPUT__ timers start output wave @ HRPWM_Timer_Output_Stop
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_OUTPUT_ODIS0A
+ * @arg HRPWM_OUTPUT_ODIS0B
+ * @arg HRPWM_OUTPUT_ODIS1A
+ * @arg HRPWM_OUTPUT_ODIS1B
+ * @arg HRPWM_OUTPUT_ODIS2A
+ * @arg HRPWM_OUTPUT_ODIS2B
+ * @arg HRPWM_OUTPUT_ODIS3A
+ * @arg HRPWM_OUTPUT_ODIS3B
+ * @arg HRPWM_OUTPUT_ODIS4A
+ * @arg HRPWM_OUTPUT_ODIS4B
+ * @arg HRPWM_OUTPUT_ODIS5A
+ * @arg HRPWM_OUTPUT_ODIS5B
+ * @retval None
+ */
+#define __LL_HRPWM_OUTPUT_STOP(__OUTPUT__) SET_BIT(HRPWM->Common.ODISR, (__OUTPUT__))
+
+/** @brief Multiple mode combination configuration
+ * @param __TIMERS__ timers to enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_INDEX_MASTER: Master timer identifier
+ * @arg HRPWM_INDEX_SLAVE_0: Timer 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Timer 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Timer 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Timer 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Timer 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Timer 5 identifier
+
+ * @param __MODE__ set output mode(half \ interleaved \ pushpull)
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_HALFMODE_DISABLE
+ * @arg HRPWM_HALFMODE_ENABLE
+ * @arg HRPWM_INTERLEAVED_MODE_DISABLE
+ * @arg HRPWM_INTERLEAVED_MODE_TRIPLE
+ * @arg HRPWM_INTERLEAVED_MODE_QUAD
+ * @arg HRPWM_PUSHPULLMODE_DISABLE
+ * @arg HRPWM_PUSHPULLMODE_ENABLE
+ * @retval None
+ */
+#define __LL_HRPWM_OUTPUTMODE_SET(__TIMERS__, __MODE__) \
+ (((__TIMERS__) == HRPWM_INDEX_MASTER) ? \
+ (MODIFY_REG(HRPWM->Master.MCR , HRPWM_MCR_HALF | HRPWM_MCR_INTLVD, __MODE__)) : \
+ (MODIFY_REG(HRPWM->PWM[__TIMERS__].CR0 , HRPWM_CR0_HALF | HRPWM_CR0_INTLVD | HRPWM_CR0_PSHPLL, __MODE__)))
+
+/** @brief Select which faults are effectively configured in each slave timer
+ * @param __TIMERS__ timers to enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0: Timer 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Timer 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Timer 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Timer 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Timer 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Timer 5 identifier
+ * @param __FAULT__ timers start output wave @ HRPWM_Timer_Fault_Enabling
+ * This parameter can be any combinations of the following values:
+ * @arg HRPWM_FAULTEN_NONE
+ * @arg HRPWM_FAULTEN_FAULT0
+ * @arg HRPWM_FAULTEN_FAULT1
+ * @arg HRPWM_FAULTEN_FAULT2
+ * @arg HRPWM_FAULTEN_FAULT3
+ * @arg HRPWM_FAULTEN_FAULT4
+ * @arg HRPWM_FAULTEN_FAULT5
+ * @retval None
+ */
+#define __LL_HRPWM_SLAVE_FAULT_VALID_SEL(__TIMERS__, __FAULT__) MODIFY_REG(HRPWM->PWM[__TIMERS__].FLTR, 0x3F, __FAULT__)
+
+/** @brief The software forces the corresponding output high or low
+ * @param __TIMERS__ timers to
+ * After configuring this bit, you must reconfigure the output event in order to reoutput
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0: Timer 0 identifier
+ * @arg HRPWM_INDEX_SLAVE_1: Timer 1 identifier
+ * @arg HRPWM_INDEX_SLAVE_2: Timer 2 identifier
+ * @arg HRPWM_INDEX_SLAVE_3: Timer 3 identifier
+ * @arg HRPWM_INDEX_SLAVE_4: Timer 4 identifier
+ * @arg HRPWM_INDEX_SLAVE_5: Timer 5 identifier
+ * @retval None
+ */
+
+#define __LL_HRPWM_OUTPUT_A_SET(__TIMERS__) \
+ do { \
+ CLEAR_REG(HRPWM->PWM[__TIMERS__].CLRAR); \
+ WRITE_REG(HRPWM->PWM[__TIMERS__].SETAR, HRPWM_SETAR_SST); \
+ } while(0)
+
+#define __LL_HRPWM_OUTPUT_A_CLEAR(__TIMERS__) \
+ do { \
+ CLEAR_REG(HRPWM->PWM[__TIMERS__].SETAR); \
+ WRITE_REG(HRPWM->PWM[__TIMERS__].CLRAR, HRPWM_CLRAR_SST); \
+ } while(0)
+
+#define __LL_HRPWM_OUTPUT_B_SET(__TIMERS__) \
+ do { \
+ CLEAR_REG(HRPWM->PWM[__TIMERS__].CLRBR); \
+ WRITE_REG(HRPWM->PWM[__TIMERS__].SETBR, HRPWM_SETBR_SST); \
+ } while(0)
+
+#define __LL_HRPWM_OUTPUT_B_CLEAR(__TIMERS__) \
+ do { \
+ CLEAR_REG(HRPWM->PWM[__TIMERS__].SETBR); \
+ WRITE_REG(HRPWM->PWM[__TIMERS__].CLRBR, HRPWM_CLRBR_SST); \
+ } while(0)
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HRPWM_LL_Exported_Functions
+* @{
+*/
+
+/** @addtogroup HRPWM_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_HRPWM_Init(HRPWM_TypeDef *Instance, HRPWM_MasterSyncTypeDef *pMasterSync);
+LL_StatusETypeDef LL_HRPWM_DeInit(HRPWM_TypeDef *Instance);
+void LL_HRPWM_MspInit(HRPWM_TypeDef *Instance);
+void LL_HRPWM_MspDeInit(HRPWM_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup HRPWM_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_HRPWM_DLLStartConfig(HRPWM_TypeDef *Instance, HRPWM_DLLCfgTypedef *DLLConfig);
+LL_StatusETypeDef LL_HRPWM_DLLStart(HRPWM_TypeDef *Instance);
+LL_StatusETypeDef LL_HRPWM_TimerBaseConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_TimerBaseCfgTypeDef *pTimeBaseCfg);
+LL_StatusETypeDef LL_HRPWM_TimerCompareConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerCompareCfgTypeDef *pTimerCompCfg);
+/**
+ * @}
+ */
+
+
+/** @addtogroup HRPWM_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_HRPWM_StopCounter(uint32_t TimerIdx);
+LL_StatusETypeDef LL_HRPWM_StartCounter(uint32_t TimerIdx);
+/**
+ * @}
+ */
+
+
+/** @addtogroup HRPWM_LL_Exported_Functions_Group4
+ * @{
+ */
+LL_StatusETypeDef LL_HRPWM_TimerUintRollOverContrl(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerRollOverCfgTypeDef *pTimerRollOverCfg);
+LL_StatusETypeDef LL_HRPWM_TimerDualChannelDacConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerDaulDacCfgTypeDef *pTimerDacCfg);
+LL_StatusETypeDef LL_HRPWM_TimerRollOverMode(HRPWM_TypeDef *Instance, uint32_t TimerIdx, uint32_t pRollOverMode);
+/**
+ * @}
+ */
+
+
+/** @addtogroup HRPWM_LL_Exported_Functions_Group5
+ * @{
+ */
+LL_StatusETypeDef LL_HRPWM_FaultConfig(HRPWM_TypeDef *Instance, uint32_t Fault, HRPWM_FaultCfgTypeDef *pFaultCfg,
+ HRPWM_FaultBlankingCfgTypeDef *pFaultBlkCfg);
+LL_StatusETypeDef LL_HRPWM_FaultBlankingConfig(HRPWM_TypeDef *Instance, uint32_t Fault,
+ HRPWM_FaultBlankingCfgTypeDef *pFaultBlkCfg);
+LL_StatusETypeDef LL_HRPWM_FaultCounterConfig(HRPWM_TypeDef *Instance, uint32_t Fault,
+ HRPWM_FaultBlankingCfgTypeDef *pFaultBlkCfg);
+LL_StatusETypeDef LL_HRPWM_FaultCounterReset(uint32_t Fault);
+LL_StatusETypeDef LL_HRPWM_ADDATriggerConfig(HRPWM_TypeDef *Instance, HRPWM_ADCTriggerCfgTypeDef *pADCTriggerCfg);
+LL_StatusETypeDef LL_HRPWM_OutputConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_OutputCfgTypeDef *pOutputCfg);
+LL_StatusETypeDef LL_HRPWM_DeadTimeConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_DeadTimeCfgTypeDef *pDeaTimedCfg);
+LL_StatusETypeDef LL_HRPWM_ChopperConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_ChopperModeCfgTypeDef *pChopperCfg);
+LL_StatusETypeDef LL_HRPWM_EventConfig(HRPWM_TypeDef *Instance, uint32_t Event, HRPWM_EventCfgTypeDef *pEventCfg);
+LL_StatusETypeDef LL_HRPWM_TimerEventAConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_ExternalEventACfgTypeDef *pEventCfg, HRPWM_TimerEventFilteringCfgTypeDef *pEventFilter);
+LL_StatusETypeDef LL_HRPWM_TimerEventAFilter(HRPWM_TypeDef *Instance, uint32_t TimerIdx, uint32_t Event,
+ HRPWM_TimerEventFilteringCfgTypeDef *pEventFilter);
+/**
+ * @}
+ */
+
+
+/** @addtogroup HRPWM_LL_Exported_Functions_Group6
+ * @{
+ */
+LL_StatusETypeDef LL_HRPWM_ForceRegistersUpdate(uint32_t TimerIdx);
+LL_StatusETypeDef LL_HRPWM_DisRegisterUpdate(uint32_t TimerIdx);
+LL_StatusETypeDef LL_HRPWM_EnRegUpdate(uint32_t TimerIdx);
+LL_StatusETypeDef LL_HRPWM_StartOutput(uint32_t TimerIdx);
+LL_StatusETypeDef LL_HRPWM_StopOutput(uint32_t TimerIdx);
+LL_StatusETypeDef LL_HRPWM_SwapOutput(uint32_t TimerIdx, uint32_t swap);
+LL_StatusETypeDef LL_HRPWM_ResetCounter(uint32_t TimerIdx);
+/**
+ * @}
+ */
+
+
+/** @addtogroup HRPWM_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_HRPWM_IRQHandler(uint32_t TimerIdx);
+
+void LL_HRPWM_FLT_IRQHandler(void);
+void LL_HRPWM_SLAVE_IRQHandler(uint32_t TimerIdx);
+void LL_HRPWM_MSTR_IRQHandler(void);
+
+void LL_HRPWM_Fault0Callback(void);
+void LL_HRPWM_Fault1Callback(void);
+void LL_HRPWM_Fault2Callback(void);
+void LL_HRPWM_Fault3Callback(void);
+void LL_HRPWM_Fault4Callback(void);
+void LL_HRPWM_Fault5Callback(void);
+void LL_HRPWM_SystemFaultCallback(void);
+void LL_HRPWM_SynchronizationEventCallback(void);
+void LL_HRPWM_RegistersUpdateCallback(uint32_t TimerIdx);
+void LL_HRPWM_RepetitionEventCallback(uint32_t TimerIdx);
+void LL_HRPWM_CompareAEventCallback(uint32_t TimerIdx);
+void LL_HRPWM_CompareBEventCallback(uint32_t TimerIdx);
+void LL_HRPWM_CompareCEventCallback(uint32_t TimerIdx);
+void LL_HRPWM_CompareDEventCallback(uint32_t TimerIdx);
+void LL_HRPWM_PeriodEventCallback(uint32_t TimerIdx);
+void LL_HRPWM_CounterResetCallback(uint32_t TimerIdx);
+void LL_HRPWM_OutputASetCallback(uint32_t TimerIdx);
+void LL_HRPWM_OutputBSetCallback(uint32_t TimerIdx);
+void LL_HRPWM_OutputAResetCallback(uint32_t TimerIdx);
+void LL_HRPWM_OutputBResetCallback(uint32_t TimerIdx);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HRPWM_LL_Private_Macros HRPWM LL Private Macros
+ * @brief HRPWM LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is HRPWM index all or not
+ * @param __INDEX__ index to judge
+ * @retval 0 isn't HRPWM index all
+ * @retval 1 is HRPWM index all
+ */
+#define IS_HRPWM_INDEX_ALL(__INDEX__) \
+ (((__INDEX__) == HRPWM_INDEX_SLAVE_0) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_1) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_2) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_3) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_4) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_5) || \
+ ((__INDEX__) == HRPWM_INDEX_MASTER) || \
+ ((__INDEX__) == HRPWM_INDEX_COMMON))
+
+/**
+ * @brief Judge is HRPWM index or not
+ * @param __INDEX__ index to judge
+ * @retval 0 isn't HRPWM index
+ * @retval 1 is HRPWM index
+ */
+#define IS_HRPWM_INDEX(__INDEX__) \
+ (((__INDEX__) == HRPWM_INDEX_SLAVE_0) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_1) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_2) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_3) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_4) || \
+ ((__INDEX__) == HRPWM_INDEX_SLAVE_5) || \
+ ((__INDEX__) == HRPWM_INDEX_MASTER))
+
+/**
+ * @brief Judge is HRPWM fault interrupt or not
+ * @param __INTERRUPT__ interrupt to judge
+ * @retval 0 isn't HRPWM fault interrupt
+ * @retval 1 is HRPWM fault interrupt
+ */
+#define IS_HRPWM_FAULT_IT(__INTERRUPT__) \
+ (((__INTERRUPT__) == HRPWM_IT_NONE) || \
+ (((__INTERRUPT__) & HRPWM_IT_SRC) != HRPWM_IT_NONE))
+
+/**
+ * @brief Judge is HRPWM master interrupt or not
+ * @param __INTERRUPT__ interrupt to judge
+ * @retval 0 isn't HRPWM master interrupt
+ * @retval 1 is HRPWM master interrupt
+ */
+#define IS_HRPWM_MASTER_IT(__INTERRUPT__) \
+ (((__INTERRUPT__) == HRPWM_MASTER_IT_NONE) || \
+ (((__INTERRUPT__) & HRPWM_MASTER_IT_SRC) != HRPWM_MASTER_IT_NONE))
+
+/**
+ * @brief Judge is HRPWM timer interrupt or not
+ * @param __INTERRUPT__ interrupt to judge
+ * @retval 0 isn't HRPWM timer interrupt
+ * @retval 1 is HRPWM timer interrupt
+ */
+#define IS_HRPWM_TIMER_IT(__INTERRUPT__) \
+ (((__INTERRUPT__) == HRPWM_IT_TIMER_NONE) || \
+ (((__INTERRUPT__) & HRPWM_IT_TIMER_SRC) != HRPWM_IT_TIMER_NONE))
+
+/**
+ * @brief Judge is HRPWM sync output source or not
+ * @param __OUTPUT__ output source to judge
+ * @retval 0 isn't HRPWM sync output source
+ * @retval 1 is HRPWM sync output source
+ */
+#define IS_HRPWM_SYNCOUTPUTSOURCE(__OUTPUT__) \
+ (((__OUTPUT__) == HRPWM_SYNCOUTPUTSOURCE_MASTER_START) || \
+ ((__OUTPUT__) == HRPWM_SYNCOUTPUTSOURCE_MASTER_CMPA) || \
+ ((__OUTPUT__) == HRPWM_SYNCOUTPUTSOURCE_SLAVE0_STARTRST) || \
+ ((__OUTPUT__) == HRPWM_SYNCOUTPUTSOURCE_SLAVE0_CMPA))
+
+/**
+ * @brief Judge is HRPWM sync output polarity or not
+ * @param __POLARITY__ output polarity to judge
+ * @retval 0 isn't HRPWM sync polarity source
+ * @retval 1 is HRPWM sync polarity source
+ */
+#define IS_HRPWM_SYNCOUTPUTPOLARITY(__POLARITY__) \
+ (((__POLARITY__) == HRPWM_SYNCOUTPUTPOLARITY_POSITIVE) || \
+ ((__POLARITY__) == HRPWM_SYNCOUTPUTPOLARITY_NEGATIVE))
+
+/**
+ * @brief Judge is HRPWM sync input source or not
+ * @param __SOURCE__ input source to judge
+ * @retval 0 isn't HRPWM sync input source
+ * @retval 1 is HRPWM sync input source
+ */
+#define IS_HRPWM_SYNINPUTSOURCE(__SOURCE__) \
+ (((__SOURCE__) == HRPWM_SYNCINPUTSOURCE_NONE) || \
+ ((__SOURCE__) == HRPWM_SYNCINPUTSOURCE_TIM0_TRGO_EVENT) || \
+ ((__SOURCE__) == HRPWM_SYNCINPUTSOURCE_EVENT))
+
+/**
+ * @brief Judge is HRPWM DLLGCP or not
+ * @param __CURRENT__ current to judge
+ * @retval 0 isn't HRPWM DLLGCP
+ * @retval 1 is HRPWM DLLGCP
+ */
+#define IS_HRPWM_DLLGCP(__CURRENT__) \
+ (((__CURRENT__) == HRPWM_DLLCR_DLLGCP_4) || \
+ ((__CURRENT__) == HRPWM_DLLCR_DLLGCP_6) || \
+ ((__CURRENT__) == HRPWM_DLLCR_DLLGCP_8))
+
+/**
+ * @brief Judge is HRPWM prescale ratio or not
+ * @param __CLKPSC__ ratio to judge
+ * @retval 0 isn't HRPWM prescale ratio
+ * @retval 1 is HRPWM prescale ratio
+ */
+#define IS_HRPWM_PRESCALERRATIO(__CLKPSC__) \
+ (((__CLKPSC__) == HRPWM_PRESCALERRATIO_MUL32) || \
+ ((__CLKPSC__) == HRPWM_PRESCALERRATIO_MUL16) || \
+ ((__CLKPSC__) == HRPWM_PRESCALERRATIO_MUL8) || \
+ ((__CLKPSC__) == HRPWM_PRESCALERRATIO_MUL4) || \
+ ((__CLKPSC__) == HRPWM_PRESCALERRATIO_MUL2) || \
+ ((__CLKPSC__) == HRPWM_PRESCALERRATIO_DIV1) || \
+ ((__CLKPSC__) == HRPWM_PRESCALERRATIO_DIV2) || \
+ ((__CLKPSC__) == HRPWM_PRESCALERRATIO_DIV4))
+
+/**
+ * @brief Judge is HRPWM preload or not
+ * @param __PREEN__ preload to judge
+ * @retval 0 isn't HRPWM preload
+ * @retval 1 is HRPWM preload
+ */
+#define IS_HRPWM_PRELOAD(__PREEN__) \
+ (((__PREEN__) == HRPWM_PRELOAD_DISABLE) || \
+ ((__PREEN__) == HRPWM_PRELOAD_ENABLE))
+
+
+/**
+ * @brief Judge is HRPWM half mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM half mode
+ * @retval 1 is HRPWM half mode
+ */
+#define IS_HRPWM_HALFMODE(__MODE__) \
+ (((__MODE__) == HRPWM_HALFMODE_DISABLE) || \
+ ((__MODE__) == HRPWM_HALFMODE_ENABLE))
+
+/**
+ * @brief Judge is HRPWM push pull mode or not
+ * @param __SYNC__ mode to judge
+ * @retval 0 isn't HRPWM push pull mode
+ * @retval 1 is HRPWM push pull mode
+ */
+#define IS_HRPWM_PUSHPULLMODE(__SYNC__) \
+ (((__SYNC__) == HRPWM_PUSHPULLMODE_DISABLE) || \
+ ((__SYNC__) == HRPWM_PUSHPULLMODE_ENABLE))
+
+/**
+ * @brief Judge is HRPWM sync start or not
+ * @param __SYNC__ sync start to judge
+ * @retval 0 isn't HRPWM sync start
+ * @retval 1 is HRPWM sync start
+ */
+#define IS_HRPWM_SYNCSTART(__SYNC__) \
+ (((__SYNC__) == HRPWM_SYNCSTART_DISABLE) || \
+ ((__SYNC__) == HRPWM_SYNCSTART_ENABLE))
+
+/**
+ * @brief Judge is HRPWM sync reset or not
+ * @param __SYNC__ sync reset to judge
+ * @retval 0 isn't HRPWM sync reset
+ * @retval 1 is HRPWM sync reset
+ */
+#define IS_HRPWM_SYNCRESET(__SYNC__) \
+ (((__SYNC__) == HRPWM_SYNCRESET_DISABLE) || \
+ ((__SYNC__) == HRPWM_SYNCRESET_ENABLE))
+
+/**
+ * @brief Judge is HRPWM Interleaved Mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM Interleaved Mode
+ * @retval 1 is HRPWM Interleaved Mode
+ */
+#define IS_HRPWM_INTERLEAVEDMODE(__MODE__) \
+ (((__MODE__) == HRPWM_INTERLEAVED_MODE_DISABLE) || \
+ ((__MODE__) == HRPWM_INTERLEAVED_MODE_TRIPLE) || \
+ ((__MODE__) == HRPWM_INTERLEAVED_MODE_QUAD))
+
+/**
+ * @brief Judge is HRPWM fault enable or not
+ * @param __FAULT__ fault to judge
+ * @retval 0 isn't HRPWM fault enable
+ * @retval 1 is HRPWM fault enable
+ */
+#define IS_HRPWM_FAULTENABLE(__FAULT__) \
+ (((__FAULT__) == HRPWM_FAULTEN_NONE) || \
+ (((__FAULT__) & 0x3f) != HRPWM_FAULTEN_NONE))
+
+/**
+ * @brief Judge is HRPWM resync update or not
+ * @param __RESYNC__ resync to judge
+ * @retval 0 isn't HRPWM resync update
+ * @retval 1 is HRPWM resync update
+ */
+#define IS_HRPWM_RESYNCUPDATE(__RESYNC__) \
+ (((__RESYNC__) == HRPWM_RSYNCUPDATE_DISABLE) || \
+ ((__RESYNC__) == HRPWM_RSYNCUPDATE_ENABLE))
+
+/**
+ * @brief Judge is HRPWM update trigger or not
+ * @param __UPDATE__ update trigger to judge
+ * @retval 0 isn't HRPWM update trigger
+ * @retval 1 is HRPWM update trigger
+ */
+#define IS_HRPWM_UPDATETRIGGER(__UPDATE__) \
+ (((__UPDATE__) == HRPWM_UPDATETRIGGER_NONE) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_MASTER) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_REP) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_RST) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_TIMER_0) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_TIMER_1) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_TIMER_2) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_TIMER_3) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_TIMER_4) || \
+ ((__UPDATE__) == HRPWM_UPDATETRIGGER_TIMER_5))
+
+/**
+ * @brief Judge is HRPWM mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM mode
+ * @retval 1 is HRPWM mode
+ */
+#define IS_HRPWM_MODE(__MODE__) \
+ (((__MODE__) == HRPWM_MODE_CONTINUOUS) || \
+ ((__MODE__) == HRPWM_MODE_SINGLESHOT) || \
+ ((__MODE__) == HRPWM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+/**
+ * @brief Judge is HRPWM dual DAC reset or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM dual DAC reset
+ * @retval 1 is HRPWM dual DAC reset
+ */
+#define IS_HRPWM_DUALDAC_RESET(__MODE__) \
+ (((__MODE__) == HRPWM_DAC_DCDR_RESET) || \
+ ((__MODE__) == HRPWM_DAC_DCDR_SETA))
+
+/**
+ * @brief Judge is HRPWM dual DAC step or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM dual DAC step
+ * @retval 1 is HRPWM dual DAC step
+ */
+#define IS_HRPWM_DUALDAC_STEP(__MODE__) \
+ (((__MODE__) == HRPWM_DAC_DCDS_CMPD) || \
+ ((__MODE__) == HRPWM_DAC_DCDS_CLEARA))
+
+/**
+ * @brief Judge is HRPWM dual DAC enable or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM dual DAC enable
+ * @retval 1 is HRPWM dual DAC enable
+ */
+#define IS_HRPWM_DUALDAC_ENABLE(__MODE__) \
+ (((__MODE__) == HRPWM_DAC_DCDE_DISABLE) || \
+ ((__MODE__) == HRPWM_DAC_DCDE_ENABLE))
+
+/**
+ * @brief Judge is HRPWM fault or not
+ * @param __FAULT__ fault to judge
+ * @retval 0 isn't HRPWM fault
+ * @retval 1 is HRPWM fault
+ */
+#define IS_HRPWM_FAULT(__FAULT__) \
+ (((__FAULT__) == HRPWM_FAULT_0) || \
+ ((__FAULT__) == HRPWM_FAULT_1) || \
+ ((__FAULT__) == HRPWM_FAULT_2) || \
+ ((__FAULT__) == HRPWM_FAULT_3) || \
+ ((__FAULT__) == HRPWM_FAULT_4) || \
+ ((__FAULT__) == HRPWM_FAULT_5))
+
+/**
+ * @brief Judge is HRPWM fault source or not
+ * @param __SOURCE__ source to judge
+ * @retval 0 isn't HRPWM fault source
+ * @retval 1 is HRPWM fault source
+ */
+#define IS_HRPWM_FAULTSOURCE(__SOURCE__) \
+ (((__SOURCE__) == HRPWM_FLTSRC_GPIO) || \
+ ((__SOURCE__) == HRPWM_FLTSRC_COMP_OUT) || \
+ ((__SOURCE__) == HRPWM_FLTSRC_EVENT))
+
+/**
+ * @brief Judge is HRPWM fault polarity or not
+ * @param __POLARITY__ polarity to judge
+ * @retval 0 isn't HRPWM fault polarity
+ * @retval 1 is HRPWM fault polarity
+ */
+#define IS_HRPWM_FAULTPOLARITY(__POLARITY__) \
+ (((__POLARITY__) == HRPWM_FAULTPOL_LOW) || \
+ ((__POLARITY__) == HRPWM_FAULTPOL_HIGH))
+
+/**
+ * @brief Judge is HRPWM fault filter or not
+ * @param __FILTER__ filter to judge
+ * @retval 0 isn't HRPWM fault filter
+ * @retval 1 is HRPWM fault filter
+ */
+#define IS_HRPWM_FAULTFILTER(__FILTER__) \
+ (((__FILTER__) == HRPWM_FAULTFILTER_NONE) || \
+ (((__FILTER__) & HRPWM_FLTINR1_FLT0F) != HRPWM_FAULTFILTER_NONE))
+
+/**
+ * @brief Judge is HRPWM fault sample clock div or not
+ * @param __CLKDIV__ clock div to judge
+ * @retval 0 isn't HRPWM fault sample clock div
+ * @retval 1 is HRPWM fault sample clock div
+ */
+#define IS_HRPWM_FAULTSAMPCLK(__CLKDIV__) \
+ (((__CLKDIV__) == HRPWM_FLTSD_DIV1) || \
+ ((__CLKDIV__) == HRPWM_FLTSD_DIV2) || \
+ ((__CLKDIV__) == HRPWM_FLTSD_DIV4) || \
+ ((__CLKDIV__) == HRPWM_FLTSD_DIV8))
+
+/**
+ * @brief Judge is HRPWM fault blanking enable or not
+ * @param __BLKEN__ blanking enable to judge
+ * @retval 0 isn't HRPWM fault blanking enable
+ * @retval 1 is HRPWM fault blanking enable
+ */
+#define IS_HRPWM_FAULTBLKEN(__BLKEN__) \
+ (((__BLKEN__) == HRPWM_FAULTBLKEN_DISABLE) || \
+ ((__BLKEN__) == HRPWM_FAULTBLKEN_ENABLE))
+
+/**
+ * @brief Judge is HRPWM fault blanking source or not
+ * @param __BLKSRC__ blanking source to judge
+ * @retval 0 isn't HRPWM fault blanking source
+ * @retval 1 is HRPWM fault blanking source
+ */
+#define IS_HRPWM_FAULTBLKSRC(__BLKSRC__) \
+ (((__BLKSRC__) == HRPWM_FAULTBLKS_RSTALIGNED) || \
+ ((__BLKSRC__) == HRPWM_FAULTBLKS_MOVING))
+
+/**
+ * @brief Judge is HRPWM fault reset mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM fault reset mode
+ * @retval 1 is HRPWM fault reset mode
+ */
+#define IS_HRPWM_FAULTRSTMODE(__MODE__) \
+ (((__MODE__) == HRPWM_FAULTRSTM_UNCONDITIONAL) || \
+ ((__MODE__) == HRPWM_FAULTRSTM_CONDITIONAL))
+
+/**
+ * @brief Judge is HRPWM ADC trigger or not
+ * @param __ADCTRIGGER__ trigger to judge
+ * @retval 0 isn't HRPWM ADC trigger
+ * @retval 1 is HRPWM ADC trigger
+ */
+#define IS_HRPWM_ADCTRIGGER(__ADCTRIGGER__) \
+ (((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_0) || \
+ ((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_1) || \
+ ((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_2) || \
+ ((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_3) || \
+ ((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_4) || \
+ ((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_5) || \
+ ((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_6) || \
+ ((__ADCTRIGGER__) == HRPWM_ADCTRIGGER_7))
+
+/**
+ * @brief Judge is HRPWM ADC trigger post scaler or not
+ * @param __PSC__ post scaler to judge
+ * @retval 0 isn't HRPWM ADC trigger post scaler
+ * @retval 1 is HRPWM ADC trigger post scaler
+ */
+#define IS_HRPWM_ADCTRIGGER_POSTSCALER(__PSC__) \
+ (((__PSC__) == HRPWM_ADCTRIG_PSC_1) || \
+ (((__PSC__) & HRPWM_ADPSR_ADPSC0) != HRPWM_ADCTRIG_PSC_1))
+
+/**
+ * @brief Judge is HRPWM ADC trigger length or not
+ * @param __LENGTH__ length to judge
+ * @retval 0 isn't HRPWM ADC trigger length
+ * @retval 1 is HRPWM ADC trigger length
+ */
+#define IS_HRPWM_ADCTRIGGER_LENGTH(__LENGTH__) \
+ (((__LENGTH__) == HRPWM_ADCTRIG_LENGTH_1) || \
+ (((__LENGTH__) & HRPWM_CR2_TLEN0) != HRPWM_ADCTRIG_LENGTH_1))
+
+/**
+ * @brief Judge is HRPWM ADC trigger update source or not
+ * @param __UPDSRC__ update source to judge
+ * @retval 0 isn't HRPWM ADC trigger update source
+ * @retval 1 is HRPWM ADC trigger update source
+ */
+#define IS_HRPWM_ADCTRIGGER_UPDATESRC(__UPDSRC__) \
+ (((__UPDSRC__) == HRPWM_ADCTRIGUPDATE_MASTER) || \
+ ((__UPDSRC__) == HRPWM_ADCTRIGUPDATE_TIMER_0) || \
+ ((__UPDSRC__) == HRPWM_ADCTRIGUPDATE_TIMER_1) || \
+ ((__UPDSRC__) == HRPWM_ADCTRIGUPDATE_TIMER_2) || \
+ ((__UPDSRC__) == HRPWM_ADCTRIGUPDATE_TIMER_3) || \
+ ((__UPDSRC__) == HRPWM_ADCTRIGUPDATE_TIMER_4) || \
+ ((__UPDSRC__) == HRPWM_ADCTRIGUPDATE_TIMER_5))
+
+/**
+ * @brief Judge is HRPWM output A active polarity or not
+ * @param __POLARITY__ polarity to judge
+ * @retval 0 isn't HRPWM output A active polarity
+ * @retval 1 is HRPWM output A active polarity
+ */
+#define IS_HRPWM_OUTPUTA_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == HRPWM_OUTPUT_POLA_POSITIVE) || \
+ ((__POLARITY__) == HRPWM_OUTPUT_POLA_NEGATIVE))
+
+/**
+ * @brief Judge is HRPWM output A idel level or not
+ * @param __IDEL__ idel level to judge
+ * @retval 0 isn't HRPWM output A idel level
+ * @retval 1 is HRPWM output A idel level
+ */
+#define IS_HRPWM_OUTPUTA_IDLELEVEL(__IDEL__) \
+ (((__IDEL__) == HRPWM_OUTPUTIDLEA_INACTIVE) || \
+ ((__IDEL__) == HRPWM_OUTPUTIDLEA_ACTIVE))
+
+/**
+ * @brief Judge is HRPWM output A fault level or not
+ * @param __LEVEL__ fault level to judge
+ * @retval 0 isn't HRPWM output A fault level
+ * @retval 1 is HRPWM output A fault level
+ */
+#define IS_HRPWM_OUTPUTA_FLTLEVEL(__LEVEL__) \
+ (((__LEVEL__) == HRPWM_OUTPUTFAULTA_NONE) || \
+ ((__LEVEL__) == HRPWM_OUTPUTFAULTA_ACTIVE) || \
+ ((__LEVEL__) == HRPWM_OUTPUTFAULTA_INACTIVE) || \
+ ((__LEVEL__) == HRPWM_OUTPUTFAULTA_HIGHZ))
+
+/**
+ * @brief Judge is HRPWM output A Chopper Mode enable or not
+ * @param __CHOPPER__ Chopper Mode enable to judge
+ * @retval 0 isn't HRPWM output A Chopper Mode enable
+ * @retval 1 is HRPWM output A Chopper Mode enable
+ */
+#define IS_HRPWM_OUTPUTA_CHOPPEREN(__CHOPPER__) \
+ (((__CHOPPER__) == HRPWM_OUTPUTCHOPPERA_ENABLE) || \
+ ((__CHOPPER__) == HRPWM_OUTPUTCHOPPERA_DISABLE))
+
+/**
+ * @brief Judge is HRPWM output B active polarity or not
+ * @param __POLARITY__ polarity to judge
+ * @retval 0 isn't HRPWM output B active polarity
+ * @retval 1 is HRPWM output B active polarity
+ */
+#define IS_HRPWM_OUTPUTB_POLARITY(__POLARITY__) \
+ (((__POLARITY__) == HRPWM_OUTPUT_POLB_POSITIVE) || \
+ ((__POLARITY__) == HRPWM_OUTPUT_POLB_NEGATIVE))
+
+/**
+ * @brief Judge is HRPWM output B idel level or not
+ * @param __IDEL__ idel level to judge
+ * @retval 0 isn't HRPWM output B idel level
+ * @retval 1 is HRPWM output B idel level
+ */
+#define IS_HRPWM_OUTPUTB_IDLELEVEL(__IDEL__) \
+ (((__IDEL__) == HRPWM_OUTPUTIDLEB_INACTIVE) || \
+ ((__IDEL__) == HRPWM_OUTPUTIDLEB_ACTIVE))
+
+/**
+ * @brief Judge is HRPWM output B fault level or not
+ * @param __LEVEL__ fault level to judge
+ * @retval 0 isn't HRPWM output B fault level
+ * @retval 1 is HRPWM output B fault level
+ */
+#define IS_HRPWM_OUTPUTB_FLTLEVEL(__LEVEL__) \
+ (((__LEVEL__) == HRPWM_OUTPUTFAULTB_NONE) || \
+ ((__LEVEL__) == HRPWM_OUTPUTFAULTB_ACTIVE) || \
+ ((__LEVEL__) == HRPWM_OUTPUTFAULTB_INACTIVE) || \
+ ((__LEVEL__) == HRPWM_OUTPUTFAULTB_HIGHZ))
+
+/**
+ * @brief Judge is HRPWM output B Chopper Mode enable or not
+ * @param __CHOPPER__ Chopper Mode enable to judge
+ * @retval 0 isn't HRPWM output B Chopper Mode enable
+ * @retval 1 is HRPWM output B Chopper Mode enable
+ */
+#define IS_HRPWM_OUTPUTB_CHOPPEREN(__CHOPPER__) \
+ (((__CHOPPER__) == HRPWM_OUTPUTCHOPPERB_ENABLE) || \
+ ((__CHOPPER__) == HRPWM_OUTPUTCHOPPERB_DISABLE))
+
+/**
+ * @brief Judge is HRPWM output event or not
+ * @param __INTERRUPT__ interrupt to judge
+ * @retval 0 isn't HRPWM output event
+ * @retval 1 is HRPWM output event
+ */
+#define IS_HRPWM_OUTPUT_SET_EVENT(__INTERRUPT__) \
+ (((__INTERRUPT__) == HRPWM_OUTPUT_SET_NONE) || \
+ (((__INTERRUPT__) & 0x7FFFFU) != HRPWM_OUTPUT_SET_NONE))
+/**
+ * @brief Judge is HRPWM output event or not
+ * @param __INTERRUPT__ interrupt to judge
+ * @retval 0 isn't HRPWM output event
+ * @retval 1 is HRPWM output event
+ */
+#define IS_HRPWM_OUTPUT_CLEAR_EVENT(__INTERRUPT__) \
+ (((__INTERRUPT__) == HRPWM_OUTPUT_CLEAR_NONE) || \
+ (((__INTERRUPT__) & 0x7FFFFU) != HRPWM_OUTPUT_CLEAR_NONE))
+
+/**
+ * @brief Judge is HRPWM dead time rising sign or not
+ * @param __SIGN__ sign to judge
+ * @retval 0 isn't HRPWM dead time rising sign
+ * @retval 1 is HRPWM dead time rising sign
+ */
+#define IS_HRPWM_DEADTIME_SDTR(__SIGN__) \
+ (((__SIGN__) == HRPWM_DEADTIME_RSIGN_NEGATIVE) || \
+ ((__SIGN__) == HRPWM_DEADTIME_RSIGN_POSITIVE))
+
+/**
+ * @brief Judge is HRPWM dead time falling sign or not
+ * @param __SIGN__ sign to judge
+ * @retval 0 isn't HRPWM dead time falling sign
+ * @retval 1 is HRPWM dead time falling sign
+ */
+#define IS_HRPWM_DEADTIME_SDTF(__SIGN__) \
+ (((__SIGN__) == HRPWM_DEADTIME_FSIGN_NEGATIVE) || \
+ ((__SIGN__) == HRPWM_DEADTIME_FSIGN_POSITIVE))
+
+/**
+ * @brief Judge is HRPWM chopper duty cycle or not
+ * @param __CARDTY__ chopper duty cycle to judge
+ * @retval 0 isn't HRPWM chopper duty cycle
+ * @retval 1 is HRPWM chopper duty cycle
+ */
+#define IS_HRPWM_CHOPPER_CARDTY(__CARDTY__) \
+ (((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_0) || \
+ ((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_1) || \
+ ((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_2) || \
+ ((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_3) || \
+ ((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_4) || \
+ ((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_5) || \
+ ((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_6) || \
+ ((__CARDTY__) == HRPWM_CHOPPER_DUTYCYCLE_7))
+
+/**
+ * @brief Judge is HRPWM chopper start pulse width or not
+ * @param __STRPW__ start pulse width to judge
+ * @retval 0 isn't HRPWM chopper start pulse width
+ * @retval 1 is HRPWM chopper start pulse width
+ */
+#define IS_HRPWM_CHOPPER_STRPW(__STRPW__) \
+ (((__STRPW__) == HRPWM_CHOPPER_PULSEWIDTH_16) || \
+ (((__STRPW__) & HRPWM_CHPR_STRPW) != HRPWM_CHOPPER_PULSEWIDTH_16))
+
+/**
+ * @brief Judge is HRPWM chopper frequency or not
+ * @param __CARFRQ__ chopper frequency to judge
+ * @retval 0 isn't HRPWM chopper frequency
+ * @retval 1 is HRPWM chopper frequency
+ */
+#define IS_HRPWM_CHOPPER_CARFRQ(__CARFRQ__) \
+ (((__CARFRQ__) == HRPWM_CHOPPER_CARFRQ_DIV16) || \
+ (((__CARFRQ__) & HRPWM_CHPR_CARFRQ) != HRPWM_CHOPPER_CARFRQ_DIV16))
+
+/**
+ * @brief Judge is HRPWM event or not
+ * @param __EVENT__ event to judge
+ * @retval 0 isn't HRPWM event
+ * @retval 1 is HRPWM event
+ */
+#define IS_HRPWM_EVENT(__EVENT__) \
+ (((__EVENT__) == HRPWM_EVENT_NONE) || \
+ ((__EVENT__) == HRPWM_EVENT_0) || \
+ ((__EVENT__) == HRPWM_EVENT_1) || \
+ ((__EVENT__) == HRPWM_EVENT_2) || \
+ ((__EVENT__) == HRPWM_EVENT_3) || \
+ ((__EVENT__) == HRPWM_EVENT_4) || \
+ ((__EVENT__) == HRPWM_EVENT_5))
+
+/**
+ * @brief Judge is HRPWM event source or not
+ * @param __SOURCE__ source to judge
+ * @retval 0 isn't HRPWM event source
+ * @retval 1 is HRPWM event source
+ */
+#define IS_HRPWM_EVENTSOURCE(__SOURCE__) \
+ (((__SOURCE__) == HRPWM_EEVSRC_GPIO) || \
+ ((__SOURCE__) == HRPWM_EEVSRC_COMP_OUT) || \
+ ((__SOURCE__) == HRPWM_EEVSRC_TIM_TRGO) || \
+ ((__SOURCE__) == HRPWM_EEVSRC_ADC_AWD))
+
+/**
+ * @brief Judge is HRPWM event polarity or not
+ * @param __POLARITY__ polarity to judge
+ * @retval 0 isn't HRPWM event polarity
+ * @retval 1 is HRPWM event polarity
+ */
+#define IS_HRPWM_EVENTPOLARITY(__POLARITY__) \
+ (((__POLARITY__) == HRPWM_EVENTPOL_HIGH) || \
+ ((__POLARITY__) == HRPWM_EVENTPOL_LOW))
+
+/**
+ * @brief Judge is HRPWM event filter or not
+ * @param __FILTER__ filter to judge
+ * @retval 0 isn't HRPWM event filter
+ * @retval 1 is HRPWM event filter
+ */
+#define IS_HRPWM_EVENTFILTER(__FILTER__) \
+ (((__FILTER__) == HRPWM_EVENTFILTER_NONE) || \
+ (((__FILTER__) & HRPWM_EECR2_EE0F) != HRPWM_EVENTFILTER_NONE))
+
+/**
+ * @brief Judge is HRPWM event prescaler div or not
+ * @param __CLKDIV__ prescaler div to judge
+ * @retval 0 isn't HRPWM event prescaler div
+ * @retval 1 is HRPWM event prescaler div
+ */
+#define IS_HRPWM_EVENTSAMPCLK(__CLKDIV__) \
+ (((__CLKDIV__) == HRPWM_EEVSD_DIV1) || \
+ ((__CLKDIV__) == HRPWM_EEVSD_DIV2) || \
+ ((__CLKDIV__) == HRPWM_EEVSD_DIV4) || \
+ ((__CLKDIV__) == HRPWM_EEVSD_DIV8))
+
+/**
+ * @brief Judge is HRPWM event fast mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM event fast mode
+ * @retval 1 is HRPWM event fast mode
+ */
+#define IS_HRPWM_EVENTFASTMODE(__MODE__) \
+ (((__MODE__) == HRPWM_EVENTFASTMODE_DISABLE) || \
+ ((__MODE__) == HRPWM_EVENTFASTMODE_ENABLE))
+
+/**
+ * @brief Judge is HRPWM event Sensitivity or not
+ * @param __SNS__ Sensitivity to judge
+ * @retval 0 isn't HRPWM event Sensitivity
+ * @retval 1 is HRPWM event Sensitivity
+ */
+#define IS_HRPWM_EVENTSNS(__SNS__) \
+ (((__SNS__) == HRPWM_EVENTSENS_LEVEL) || \
+ ((__SNS__) == HRPWM_EVENTSENS_RISINGEDGE) || \
+ ((__SNS__) == HRPWM_EVENTSENS_FALLINGEDGE) || \
+ ((__SNS__) == HRPWM_EVENTSENS_BOTHEDGES))
+
+/**
+ * @brief Judge is HRPWM event A filter or not
+ * @param __FILTER__ filter to judge
+ * @retval 0 isn't HRPWM event filter A
+ * @retval 1 is HRPWM event filter A
+ */
+#define IS_HRPWM_EVENTA_FILTER(__FILTER__) \
+ (((__FILTER__) == HRPWM_EEVFLT_NONE) || \
+ (((__FILTER__) & HRPWM_EEFR0_EE0FLTR) != HRPWM_EEVFLT_NONE))
+
+/**
+ * @brief Judge is HRPWM event A latch or not
+ * @param __LATCH__ latch to judge
+ * @retval 0 isn't HRPWM event A latch
+ * @retval 1 is HRPWM event A latch
+ */
+#define IS_HRPWM_EVENTA_LATCH(__LATCH__) \
+ (((__LATCH__) == HRPWM_EVENTLATCH_DISABLE) || \
+ ((__LATCH__) == HRPWM_EVENTLATCH_ENABLE))
+
+/**
+ * @brief Judge is HRPWM event A source or not
+ * @param __SOURCE__ source to judge
+ * @retval 0 isn't HRPWM event A source
+ * @retval 1 is HRPWM event A source
+ */
+#define IS_HRPWM_EVENTA_SOURCE(__SOURCE__) \
+ (((__SOURCE__) == HRPWM_EEVASEL_SOURCE_EEVENT0) || \
+ ((__SOURCE__) == HRPWM_EEVASEL_SOURCE_EEVENT1) || \
+ ((__SOURCE__) == HRPWM_EEVASEL_SOURCE_EEVENT2) || \
+ ((__SOURCE__) == HRPWM_EEVASEL_SOURCE_EEVENT3) || \
+ ((__SOURCE__) == HRPWM_EEVASEL_SOURCE_EEVENT4) || \
+ ((__SOURCE__) == HRPWM_EEVASEL_SOURCE_EEVENT5))
+
+/**
+ * @brief Judge is HRPWM event A reset mode or not
+ * @param __MODE__ mode to judge
+ * @retval 0 isn't HRPWM event A reset mode
+ * @retval 1 is HRPWM event A reset mode
+ */
+#define IS_HRPWM_EVENTA_RSTMODE(__MODE__) \
+ (((__MODE__) == HRPWM_EEVARSTM_CONDITIONAL) || \
+ ((__MODE__) == HRPWM_EEVARSTM_UNCONDITIONAL))
+
+/**
+ * @brief Judge is HRPWM event A counter enable or not
+ * @param __COUNTEREN__ counter enable to judge
+ * @retval 0 isn't HRPWM event A counter enable
+ * @retval 1 is HRPWM event A counter enable
+ */
+#define IS_HRPWM_EVENTA_COUNTEREN(__COUNTEREN__) \
+ (((__COUNTEREN__) == HRPWM_EEVACOUNTER_DISABLE) || \
+ ((__COUNTEREN__) == HRPWM_EEVACOUNTER_ENABLE))
+
+/**
+ * @brief Judge is HRPWM reset event or not
+ * @param __RESET__ reset event to judge
+ * @retval 0 isn't HRPWM reset event
+ * @retval 1 is HRPWM reset event
+ */
+#define IS_HRPWM_RST_EVENT(__RESET__) \
+ (((__RESET__) == HRPWM_RESET_TRIGGER_NONE) || \
+ (((__RESET__) & (0x1FFFFFFF)) != 0x0U))
+
+/**
+ * @brief Judge is HRPWM roll over mode or not
+ * @param __ROLLOVER__ mode to judge
+ * @retval 0 isn't HRPWM roll over mode
+ * @retval 1 is HRPWM roll over mode
+ */
+#define IS_HRPWM_ROLLOVERMODE(__ROLLOVER__) \
+ (((__ROLLOVER__) == HRPWM_ROM_BOTH) || \
+ ((__ROLLOVER__) == HRPWM_ROM_ZERO) || \
+ ((__ROLLOVER__) == HRPWM_ROM_PERIOD))
+
+/**
+ * @brief Judge is HRPWM roll over mode or not
+ * @param __ROLLOVER__ mode to judge
+ * @retval 0 isn't HRPWM roll over mode
+ * @retval 1 is HRPWM roll over mode
+ */
+#define IS_HRPWM_OUTPUTROLLOVERMODE(__ROLLOVER__) \
+ (((__ROLLOVER__) == HRPWM_OUTROM_BOTH) || \
+ ((__ROLLOVER__) == HRPWM_OUTROM_ZERO) || \
+ ((__ROLLOVER__) == HRPWM_OUTROM_PERIOD))
+
+/**
+ * @brief Judge is HRPWM roll over mode or not
+ * @param __ROLLOVER__ mode to judge
+ * @retval 0 isn't HRPWM roll over mode
+ * @retval 1 is HRPWM roll over mode
+ */
+#define IS_HRPWM_ADCROLLOVERMODE(__ROLLOVER__) \
+ (((__ROLLOVER__) == HRPWM_ADROM_BOTH) || \
+ ((__ROLLOVER__) == HRPWM_ADROM_ZERO) || \
+ ((__ROLLOVER__) == HRPWM_ADROM_PERIOD))
+
+/**
+ * @brief Judge is HRPWM roll over mode or not
+ * @param __ROLLOVER__ mode to judge
+ * @retval 0 isn't HRPWM roll over mode
+ * @retval 1 is HRPWM roll over mode
+ */
+#define IS_HRPWM_FLTROLLOVERMODE(__ROLLOVER__) \
+ (((__ROLLOVER__) == HRPWM_FLTROM_BOTH) || \
+ ((__ROLLOVER__) == HRPWM_FLTROM_ZERO) || \
+ ((__ROLLOVER__) == HRPWM_FLTROM_PERIOD))
+
+/**
+ * @brief Judge is HRPWM roll over mode or not
+ * @param __ROLLOVER__ mode to judge
+ * @retval 0 isn't HRPWM roll over mode
+ * @retval 1 is HRPWM roll over mode
+ */
+#define IS_HRPWM_EVTROLLOVERMODE(__ROLLOVER__) \
+ (((__ROLLOVER__) == HRPWM_EEVROM_BOTH) || \
+ ((__ROLLOVER__) == HRPWM_EEVROM_ZERO) || \
+ ((__ROLLOVER__) == HRPWM_EEVROM_PERIOD))
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_HRPWM_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_i2c.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_i2c.h
new file mode 100644
index 0000000000..6df60ace78
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_i2c.h
@@ -0,0 +1,2511 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_i2c.h
+ * @author MCD Application Team
+ * @brief Header file for I2C LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TMF5XXX_LL_I2C_H_
+#define _TMF5XXX_LL_I2C_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+#ifdef LL_DMA_MODULE_ENABLED
+#include "tae32f53xx_ll_dma.h"
+#endif
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C LL Exported Constants
+ * @brief I2C LL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief I2C SS SPEED Max Macro Define
+ */
+#define I2C_SS_SPEED_MAX (100000UL)
+
+/**
+ * @brief I2C FS SPEED Max Macro Define
+ */
+#define I2C_FS_SPEED_MAX (400000UL)
+
+/**
+ * @brief I2C FS PLUS SPEED Max Macro Define
+ */
+#define I2C_FS_PLUS_SPEED_MAX (1000000UL)
+
+/**
+ * @brief I2C HS SPEED Max Macro Define
+ */
+#define I2C_HS_SPEED_MAX (3400000UL)
+
+
+/**
+ * @brief I2C FIFO Depth Define
+ */
+#define I2C_FIFO_DEPTH (16)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C LL Exported Macros
+ * @brief I2C LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief I2C SMBUS Persistant Slave Address Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvPersistant_En(__I2C__) SET_BIT((__I2C__)->CON, I2C_SMBUS_PST_SLV_ADDR_EN_Msk)
+
+/**
+ * @brief I2C SMBUS Persistant Slave Address Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvPersistant_Dis(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_SMBUS_PST_SLV_ADDR_EN_Msk)
+
+/**
+ * @brief I2C SMBUS ARP Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARP_En(__I2C__) SET_BIT((__I2C__)->CON, I2C_SMBUS_ARP_EN_Msk)
+
+/**
+ * @brief I2C SMBUS ARP Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARP_Dis(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_SMBUS_ARP_EN_Msk)
+
+/**
+ * @brief I2C SMBUS Slave Quick Cmd Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvQuickCmd_En(__I2C__) SET_BIT((__I2C__)->CON, I2C_SMBUS_SLV_QUICK_CMD_EN_Msk)
+
+/**
+ * @brief I2C SMBUS Slave Quick Cmd Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvQuickCmd_Dis(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_SMBUS_SLV_QUICK_CMD_EN_Msk)
+
+/**
+ * @brief I2C Optional SAR Control Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_OptionalSarCtrl_Set(__I2C__) SET_BIT((__I2C__)->CON, I2C_OPTIONAL_SAR_CTRL_Msk)
+
+/**
+ * @brief I2C Master Bus Clear Feature Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_BusClrFeature_En(__I2C__) SET_BIT((__I2C__)->CON, I2C_BUS_CLEAR_FEATURE_CTRL_Msk)
+
+/**
+ * @brief I2C Master Bus Clear Feature Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_BusClrFeature_Dis(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_BUS_CLEAR_FEATURE_CTRL_Msk)
+
+/**
+ * @brief I2C Stop Detect If Master Active Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_StopDetIfActive_Set(__I2C__) SET_BIT((__I2C__)->CON, I2C_STOP_DET_IF_MASTER_ACT_Msk)
+
+/**
+ * @brief I2C Stop Detect If Master Active Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_StopDetIfActive_Clr(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_STOP_DET_IF_MASTER_ACT_Msk)
+
+/**
+ * @brief I2C RX FIFO Full Hold Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxFIFOFullHold_En(__I2C__) SET_BIT((__I2C__)->CON, I2C_RX_FIFO_FULL_HLD_CTRL_Msk)
+
+/**
+ * @brief I2C RX FIFO Full Hold Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxFIFOFullHold_Dis(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_RX_FIFO_FULL_HLD_CTRL_Msk)
+
+/**
+ * @brief I2C TX Empty Control Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxEmptyCtrl_Set(__I2C__) SET_BIT((__I2C__)->CON, I2C_TX_EMPTY_CTRL_Msk)
+
+/**
+ * @brief I2C TX Empty Control Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxEmptyCtrl_Clr(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_TX_EMPTY_CTRL_Msk)
+
+/**
+ * @brief I2C Slave Stop Detect If Addressed Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_StopDetIfAddressed_Set(__I2C__) SET_BIT((__I2C__)->CON, I2C_STOP_DET_IFADDRESSED_Msk)
+
+/**
+ * @brief I2C Slave Stop Detect If Addressed Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_StopDetIfAddressed_Clr(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_STOP_DET_IFADDRESSED_Msk)
+
+/**
+ * @brief I2C Slave Mode Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLAVE_Mode_En(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_SLAVE_DISABLE_Msk)
+
+/**
+ * @brief I2C Slave Mode Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLAVE_Mode_Dis(__I2C__) SET_BIT((__I2C__)->CON, I2C_SLAVE_DISABLE_Msk)
+
+/**
+ * @brief I2C Master Restart Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_Restart_En(__I2C__) SET_BIT((__I2C__)->CON, I2C_RESTART_EN_Msk)
+
+/**
+ * @brief I2C Master Restart Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_Restart_Dis(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_RESTART_EN_Msk)
+
+/**
+ * @brief I2C Master 7bit Address Mode Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_7bAddr_Set(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_10BITADDR_MASTER_Msk)
+
+/**
+ * @brief I2C Master 10bit Address Mode Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_10bAddr_Set(__I2C__) SET_BIT((__I2C__)->CON, I2C_10BITADDR_MASTER_Msk)
+
+/**
+ * @brief I2C Slave 7bit Address Mode Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_7bAddr_Set(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_10BITADDR_SLAVE_Msk)
+
+/**
+ * @brief I2C Slave 10bit Address Mode Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_10bAddr_Set(__I2C__) SET_BIT((__I2C__)->CON, I2C_10BITADDR_SLAVE_Msk)
+
+/**
+ * @brief I2C Speed Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param speed I2C Speed
+ * @return None
+ */
+#define __LL_I2C_Speed_Set(__I2C__, speed) MODIFY_REG((__I2C__)->CON, I2C_SPEED_Msk, speed)
+
+/**
+ * @brief I2C Master Mode Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MASTER_Mode_En(__I2C__) SET_BIT((__I2C__)->CON, I2C_MASTER_MODE_Msk)
+
+/**
+ * @brief I2C Master Mode Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MASTER_Mode_Dis(__I2C__) CLEAR_BIT((__I2C__)->CON, I2C_MASTER_MODE_Msk)
+
+/**
+ * @brief I2C Master Mode is Enable or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 I2C isn't Master Mode
+ * @retval 1 I2C is Master Mode
+ */
+#define __LL_I2C_IsMasterMode(__I2C__) READ_BIT((__I2C__)->CON, I2C_MASTER_MODE_Msk)
+
+/**
+ * @brief I2C TAR SMBUD Quick Cmd Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_SmbusQuickCmd_Set(__I2C__) SET_BIT((__I2C__)->TAR, I2C_SMBUS_QUICK_CMD_Msk)
+
+/**
+ * @brief I2C TAR SMBUD Quick Cmd Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_SmbusQuickCmd_Clr(__I2C__) CLEAR_BIT((__I2C__)->TAR, I2C_SMBUS_QUICK_CMD_Msk)
+
+/**
+ * @brief I2C TAR Device ID Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_DevID_Set(__I2C__) SET_BIT((__I2C__)->TAR, I2C_TAR_DEV_ID_Msk)
+
+/**
+ * @brief I2C TAR Device ID Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_DevID_Clr(__I2C__) CLEAR_BIT((__I2C__)->TAR, I2C_TAR_DEV_ID_Msk)
+
+/**
+ * @brief I2C TAR Master 7bit Address Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_MST_7bAddr_Set(__I2C__) CLEAR_BIT((__I2C__)->TAR, I2C_TAR_10BITADDR_MASTER_Msk)
+
+/**
+ * @brief I2C TAR Master 10bit Address Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_MST_10bAddr_Set(__I2C__) SET_BIT((__I2C__)->TAR, I2C_TAR_10BITADDR_MASTER_Msk)
+
+/**
+ * @brief I2C TAR Special Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_Special_Set(__I2C__) SET_BIT((__I2C__)->TAR, I2C_SPECIAL_Msk)
+
+/**
+ * @brief I2C TAR Special Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_Special_Clr(__I2C__) CLEAR_BIT((__I2C__)->TAR, I2C_SPECIAL_Msk)
+
+/**
+ * @brief I2C TAR GC OR Start Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_GcOrStart_Set(__I2C__) SET_BIT((__I2C__)->TAR, I2C_GC_OR_START_Msk)
+
+/**
+ * @brief I2C TAR GC OR Start Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TAR_GcOrStart_Clr(__I2C__) CLEAR_BIT((__I2C__)->TAR, I2C_GC_OR_START_Msk)
+
+/**
+ * @brief I2C Master TAR Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param tar I2C Master TAR
+ * @return None
+ */
+#define __LL_I2C_TAR_Set(__I2C__, tar) MODIFY_REG((__I2C__)->TAR, I2C_TAR_Msk, ((tar & 0x3ffUL) << I2C_TAR_Pos))
+
+
+/**
+ * @brief I2C Slave SAR Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param tar I2C Slave SAR
+ * @return None
+ */
+#define __LL_I2C_SAR_Set(__I2C__, sar) MODIFY_REG((__I2C__)->SAR, I2C_SAR_Msk, ((sar & 0x3ffUL) << I2C_SAR_Pos))
+
+
+/**
+ * @brief Judge Is First Data Byte or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't first data byte
+ * @retval 1 Is first data byte
+ */
+#define __LL_I2C_IsFirstDataByte(__I2C__) (READ_BIT((__I2C__)->DCMD, I2C_FIRST_DATA_BYTE_Msk) >> I2C_FIRST_DATA_BYTE_Pos)
+
+/**
+ * @brief I2C Restart Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Restart_Set(__I2C__) SET_BIT((__I2C__)->DCMD, I2C_RESTART_Msk)
+
+/**
+ * @brief I2C Restart Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Restart_Clr(__I2C__) CLEAR_BIT((__I2C__)->DCMD, I2C_RESTART_Msk)
+
+/**
+ * @brief I2C Stop Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Stop_Set(__I2C__) SET_BIT((__I2C__)->DCMD, I2C_STOP_Msk)
+
+/**
+ * @brief I2C Stop Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Stop_Clr(__I2C__) CLEAR_BIT((__I2C__)->DCMD, I2C_STOP_Msk)
+
+/**
+ * @brief I2C Master Cmd Read Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_CmdRead_Set(__I2C__) SET_BIT((__I2C__)->DCMD, I2C_CMD_Msk)
+
+/**
+ * @brief I2C Master Cmd Write Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_CmdWrite_Set(__I2C__) CLEAR_BIT((__I2C__)->DCMD, I2C_CMD_Msk)
+
+/**
+ * @brief I2C Data Write
+ * @param __I2C__ Specifies I2C peripheral
+ * @param dat data to write
+ * @return None
+ */
+#define __LL_I2C_DAT_Write(__I2C__, dat) MODIFY_REG((__I2C__)->DCMD, I2C_DAT_Msk, (((dat) & 0xffUL) << I2C_DAT_Pos))
+
+/**
+ * @brief I2C Data Read
+ * @param __I2C__ Specifies I2C peripheral
+ * @return read data
+ */
+#define __LL_I2C_DAT_Read(__I2C__) (READ_BIT((__I2C__)->DCMD, I2C_DAT_Msk) >> I2C_DAT_Pos)
+
+/**
+ * @brief I2C timing start and send 8b address
+ * @param __I2C__ Specifies I2C peripheral
+ * @param addr_8b 8b address
+ * @return None
+ */
+#define __LL_I2C_Timing_RestartAddr8b(__I2C__, addr_8b) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_RESTART_Msk | ((addr_8b & 0xffUL) << I2C_DAT_Pos)); \
+ } while(0)
+
+/**
+ * @brief I2C timing restart and send 16b address
+ * @param __I2C__ Specifies I2C peripheral
+ * @param addr_16b 16b address
+ * @return None
+ */
+#define __LL_I2C_Timing_RestartAddr16b(__I2C__, addr_16b) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_RESTART_Msk | (((addr_16b >> 8) & 0xffUL) << I2C_DAT_Pos)); \
+ WRITE_REG((__I2C__)->DCMD, ((addr_16b & 0xffUL) << I2C_DAT_Pos)); \
+ } while(0)
+
+/**
+ * @brief I2C timing restart and send 32b address
+ * @param __I2C__ Specifies I2C peripheral
+ * @param addr_32b 32b address
+ * @return None
+ */
+#define __LL_I2C_Timing_RestartAddr32b(__I2C__, addr_32b) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_RESTART_Msk | (((addr_32b >> 24) & 0xffUL) << I2C_DAT_Pos)); \
+ WRITE_REG((__I2C__)->DCMD, (((addr_32b >> 16) & 0xffUL) << I2C_DAT_Pos)); \
+ WRITE_REG((__I2C__)->DCMD, (((addr_32b >> 8) & 0xffUL) << I2C_DAT_Pos)); \
+ WRITE_REG((__I2C__)->DCMD, ((addr_32b & 0xffUL) << I2C_DAT_Pos)); \
+ } while(0)
+
+/**
+ * @brief I2C timing restart read stop
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Timing_RestartReadStop(__I2C__) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_RESTART_Msk | I2C_CMD_READ | I2C_STOP_Msk); \
+ } while(0)
+
+/**
+ * @brief I2C timing restart read
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Timing_RestartRead(__I2C__) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_RESTART_Msk | I2C_CMD_READ); \
+ } while(0)
+
+/**
+ * @brief I2C timing read
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Timing_Read(__I2C__) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_CMD_READ); \
+ } while(0)
+
+/**
+ * @brief I2C timing read stop
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Timing_ReadStop(__I2C__) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_CMD_READ | I2C_STOP_Msk); \
+ } while(0)
+
+/**
+ * @brief I2C timing write
+ * @param __I2C__ Specifies I2C peripheral
+ * @param dat write data
+ * @return None
+ */
+#define __LL_I2C_Timing_Write(__I2C__, dat) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, (((dat) & 0xffUL) << I2C_DAT_Pos)); \
+ } while(0)
+
+/**
+ * @brief I2C timing restart write
+ * @param __I2C__ Specifies I2C peripheral
+ * @param dat write data
+ * @return None
+ */
+#define __LL_I2C_Timing_RestartWrite(__I2C__, dat) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_RESTART_Msk | (((dat) & 0xffUL) << I2C_DAT_Pos)); \
+ } while(0)
+
+
+/**
+ * @brief I2C timing write stop
+ * @param __I2C__ Specifies I2C peripheral
+ * @param dat write data
+ * @return None
+ */
+#define __LL_I2C_Timing_WriteStop(__I2C__, dat) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_STOP_Msk | (((dat) & 0xffUL) << I2C_DAT_Pos)); \
+ } while(0)
+
+/**
+ * @brief I2C timing restart write stop
+ * @param __I2C__ Specifies I2C peripheral
+ * @param dat write data
+ * @return None
+ */
+#define __LL_I2C_Timing_RestartWriteStop(__I2C__, dat) \
+ do { \
+ WRITE_REG((__I2C__)->DCMD, I2C_RESTART_Msk | I2C_STOP_Msk | (((dat) & 0xffUL) << I2C_DAT_Pos)); \
+ } while(0)
+
+
+/**
+ * @brief I2C SS SCL High Count Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param cnt I2C SS SCL High Count
+ * @return None
+ */
+#define __LL_I2C_SS_SCLHcnt_Set(__I2C__, cnt) \
+ MODIFY_REG((__I2C__)->SSHCNT, I2C_SS_SCL_HCNT_Msk, ((cnt & 0xffffUL) << I2C_SS_SCL_HCNT_Pos))
+
+
+/**
+ * @brief I2C SS SCL Low Count Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param cnt I2C SS SCL Low Count
+ * @return None
+ */
+#define __LL_I2C_SS_SCLLcnt_Set(__I2C__, cnt) \
+ MODIFY_REG((__I2C__)->SSLCNT, I2C_SS_SCL_LCNT_Msk, ((cnt & 0xffffUL) << I2C_SS_SCL_LCNT_Pos))
+
+
+/**
+ * @brief I2C FS SCL High Count Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param cnt I2C FS SCL High Count
+ * @return None
+ */
+#define __LL_I2C_FS_SCLHcnt_Set(__I2C__, cnt) \
+ MODIFY_REG((__I2C__)->FSHCNT, I2C_FS_SCL_HCNT_Msk, ((cnt & 0xffffUL) << I2C_FS_SCL_HCNT_Pos))
+
+
+/**
+ * @brief I2C FS SCL Low Count Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param cnt I2C FS SCL Low Count
+ * @return None
+ */
+#define __LL_I2C_FS_SCLLcnt_Set(__I2C__, cnt) \
+ MODIFY_REG((__I2C__)->FSLCNT, I2C_FS_SCL_LCNT_Msk, ((cnt & 0xffffUL) << I2C_FS_SCL_LCNT_Pos))
+
+
+/**
+ * @brief Judge SCL Stuck at Low or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SCL isn't Stuck at Low
+ * @retval 1 SCL is Stuck at Low
+ */
+#define __LL_I2C_IsSCLStuckAtLow(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_SCL_STK_AT_LOW_INT_STA_Msk) >> I2C_SCL_STK_AT_LOW_INT_STA_Pos)
+
+/**
+ * @brief Judge Master On Hold or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Master isn't On Hold
+ * @retval 1 Master is On Hold
+ */
+#define __LL_I2C_MST_IsOnHold(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_MST_ON_HOLD_INT_STA_Msk) >> I2C_MST_ON_HOLD_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave is Restart Detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave isn't Restart Detect
+ * @retval 1 Slave is Restart Detect
+ */
+#define __LL_I2C_SLV_IsRestartDet(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_RESTART_DET_INT_STA_Msk) >> I2C_RESTART_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave Genaral Call or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't Genaral Call
+ * @retval 1 Is Genaral Call
+ */
+#define __LL_I2C_SLV_IsGenCall(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_GEN_CALL_INT_STA_Msk) >> I2C_GEN_CALL_INT_STA_Pos)
+
+/**
+ * @brief Judge Start Detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't start detect
+ * @retval 1 Is start detect
+ */
+#define __LL_I2C_IsStartDet(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_START_DET_INT_STA_Msk) >> I2C_START_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge Stop Detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't stop detect
+ * @retval 1 Is stop detect
+ */
+#define __LL_I2C_IsStopDet(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_STOP_DET_INT_STA_Msk) >> I2C_STOP_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge I2C Activity or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 I2C isn't activity
+ * @retval 1 I2C is activity
+ */
+#define __LL_I2C_IsActivityInt(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_ACTIVITY_INT_STA_Msk) >> I2C_ACTIVITY_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave RX Done or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave isn't RX Done
+ * @retval 1 Slave is RX Done
+ */
+#define __LL_I2C_SLV_IsRxDone(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_RX_DONE_INT_STA_Msk) >> I2C_RX_DONE_INT_STA_Pos)
+
+/**
+ * @brief Judge TX Abort or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't TX Abort
+ * @retval 1 Is TX Abort
+ */
+#define __LL_I2C_IsTxAbort(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_TX_ABRT_INT_STA_Msk) >> I2C_TX_ABRT_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave Read Request or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave isn't Read Request
+ * @retval 1 Slave is Read Request
+ */
+#define __LL_I2C_SLV_IsReadReq(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_RD_REQ_INT_STA_Msk) >> I2C_RD_REQ_INT_STA_Pos)
+
+/**
+ * @brief Judge TX Empty or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't TX Empty
+ * @retval 1 Is TX Empty
+ */
+#define __LL_I2C_IsTxEmpty(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_TX_EMPTY_INT_STA_Msk) >> I2C_TX_EMPTY_INT_STA_Pos)
+
+/**
+ * @brief Judge TX Over or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't TX Over
+ * @retval 1 Is TX Over
+ */
+#define __LL_I2C_IsTxOver(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_TX_OVER_INT_STA_Msk) >> I2C_TX_OVER_INT_STA_Pos)
+
+/**
+ * @brief Judge RX Full or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't RX Full
+ * @retval 1 Is RX Full
+ */
+#define __LL_I2C_IsRxFull(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_RX_FULL_INT_STA_Msk) >> I2C_RX_FULL_INT_STA_Pos)
+
+/**
+ * @brief Judge RX Over or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't RX Over
+ * @retval 1 Is RX Over
+ */
+#define __LL_I2C_IsRxOver(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_RX_OVER_INT_STA_Msk) >> I2C_RX_OVER_INT_STA_Pos)
+
+/**
+ * @brief Judge RX Under or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't RX Under
+ * @retval 1 Is RX Under
+ */
+#define __LL_I2C_IsRxUnder(__I2C__) \
+ (READ_BIT((__I2C__)->INTRST, I2C_RX_UNDER_INT_STA_Msk) >> I2C_RX_UNDER_INT_STA_Pos)
+
+/**
+ * @brief I2C interrupt status get
+ * @param __I2C__ Specifies I2C peripheral
+ * @return I2C interrupt status
+ */
+#define __LL_I2C_IntSta_Get(__I2C__) (READ_REG((__I2C__)->INTRST))
+
+/**
+ * @brief I2C SCL Stuck at low Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SCLStuckAtLow_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_SCL_STK_AT_LOW_INT_EN_Msk)
+
+/**
+ * @brief I2C SCL Stuck at low Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SCLStuckAtLow_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_SCL_STK_AT_LOW_INT_EN_Msk)
+
+/**
+ * @brief I2C Master on hold Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_OnHold_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_MST_ON_HOLD_INT_EN_Msk)
+
+/**
+ * @brief I2C Master on hold Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_OnHold_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_MST_ON_HOLD_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave Restart Detect Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_RestartDet_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_RESTART_DET_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave Restart Detect Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_RestartDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_RESTART_DET_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave Genaral Call Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_GenCall_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_GEN_CALL_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave Genaral Call Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_GenCall_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_GEN_CALL_INT_EN_Msk)
+
+/**
+ * @brief I2C Start Detect Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_StartDet_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_START_DET_INT_EN_Msk)
+
+/**
+ * @brief I2C Start Detect Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_StartDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_START_DET_INT_EN_Msk)
+
+/**
+ * @brief I2C Stop Detect Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_StopDet_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_STOP_DET_INT_EN_Msk)
+
+/**
+ * @brief I2C Stop Detect Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_StopDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_STOP_DET_INT_EN_Msk)
+
+/**
+ * @brief I2C Activity Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Activity_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_ACTIVITY_INT_EN_Msk)
+
+/**
+ * @brief I2C Activity Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Activity_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_ACTIVITY_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave RX Done Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_RxDone_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_RX_DONE_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave RX Done Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_RxDone_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_RX_DONE_INT_EN_Msk)
+
+/**
+ * @brief I2C TX Abort Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxAbort_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_TX_ABRT_INT_EN_Msk)
+
+/**
+ * @brief I2C TX Abort Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxAbort_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_TX_ABRT_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave Read Request Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_ReadReq_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_RD_REQ_INT_EN_Msk)
+
+/**
+ * @brief I2C Slave Read Request Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_ReadReq_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_RD_REQ_INT_EN_Msk)
+
+/**
+ * @brief I2C TX Empty Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxEmpty_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_TX_EMPTY_INT_EN_Msk)
+
+/**
+ * @brief I2C TX Empty Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxEmpty_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_TX_EMPTY_INT_EN_Msk)
+
+/**
+ * @brief I2C TX Over Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxOver_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_TX_OVER_INT_EN_Msk)
+
+/**
+ * @brief I2C TX Over Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxOver_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_TX_OVER_INT_EN_Msk)
+
+/**
+ * @brief I2C RX Full Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxFull_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_RX_FULL_INT_EN_Msk)
+
+/**
+ * @brief I2C RX Full Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxFull_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_RX_FULL_INT_EN_Msk)
+
+/**
+ * @brief I2C RX Over Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxOver_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_RX_OVER_INT_EN_Msk)
+
+/**
+ * @brief I2C RX Over Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxOver_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_RX_OVER_INT_EN_Msk)
+
+/**
+ * @brief I2C RX Under Interrupt Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxUnder_INT_En(__I2C__) SET_BIT((__I2C__)->INTRMS, I2C_RX_UNDER_INT_EN_Msk)
+
+/**
+ * @brief I2C RX Under Interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxUnder_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->INTRMS, I2C_RX_UNDER_INT_EN_Msk)
+
+
+/**
+ * @brief Judge SCL Stuck at Low Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SCL isn't Stuck at Low
+ * @retval 1 SCL is Stuck at Low
+ */
+#define __LL_I2C_IsSCLStuckAtLow_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_SCL_STK_AT_LOW_RAW_INT_STA_Msk) >> I2C_SCL_STK_AT_LOW_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge Master On Hold Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Master isn't On Hold
+ * @retval 1 Master is On Hold
+ */
+#define __LL_I2C_MST_IsOnHold_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_MST_ON_HOLD_RAW_INT_STA_Msk) >> I2C_MST_ON_HOLD_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave is Restart Detect Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave isn't Restart Detect
+ * @retval 1 Slave is Restart Detect
+ */
+#define __LL_I2C_SLV_IsRestartDet_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_RESTART_DET_RAW_INT_STA_Msk) >> I2C_RESTART_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave Genaral Call Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't Genaral Call
+ * @retval 1 Is Genaral Call
+ */
+#define __LL_I2C_SLV_IsGenCall_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_GEN_CALL_RAW_INT_STA_Msk) >> I2C_GEN_CALL_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge Start Detect Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't start detect
+ * @retval 1 Is start detect
+ */
+#define __LL_I2C_IsStartDet_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_START_DET_RAW_INT_STA_Msk) >> I2C_START_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge Stop Detect Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't stop detect
+ * @retval 1 Is stop detect
+ */
+#define __LL_I2C_IsStopDet_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_STOP_DET_RAW_INT_STA_Msk) >> I2C_STOP_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge I2C Activity Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 I2C isn't activity
+ * @retval 1 I2C is activity
+ */
+#define __LL_I2C_IsActivity_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_ACTIVITY_RAW_INT_STA_Msk) >> I2C_ACTIVITY_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave RX Done Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave isn't RX Done
+ * @retval 1 Slave is RX Done
+ */
+#define __LL_I2C_SLV_IsRxDone_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_RX_DONE_RAW_INT_STA_Msk) >> I2C_RX_DONE_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge TX Abort Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't TX Abort
+ * @retval 1 Is TX Abort
+ */
+#define __LL_I2C_IsTxAbort_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_TX_ABRT_RAW_INT_STA_Msk) >> I2C_TX_ABRT_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge Slave Read Request Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave isn't Read Request
+ * @retval 1 Slave is Read Request
+ */
+#define __LL_I2C_SLV_IsReadReq_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_RD_REQ_RAW_INT_STA_Msk) >> I2C_RD_REQ_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge TX Empty Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't TX Empty
+ * @retval 1 Is TX Empty
+ */
+#define __LL_I2C_IsTxEmpty_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_TX_EMPTY_RAW_INT_STA_Msk) >> I2C_TX_EMPTY_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge TX Over Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't TX Over
+ * @retval 1 Is TX Over
+ */
+#define __LL_I2C_IsTxOver_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_TX_OVER_RAW_INT_STA_Msk) >> I2C_TX_OVER_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge RX Full Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't RX Full
+ * @retval 1 Is RX Full
+ */
+#define __LL_I2C_IsRxFull_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_RX_FULL_RAW_INT_STA_Msk) >> I2C_RX_FULL_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge RX Over Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't RX Over
+ * @retval 1 Is RX Over
+ */
+#define __LL_I2C_IsRxOver_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_RX_OVER_RAW_INT_STA_Msk) >> I2C_RX_OVER_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge RX Under Raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't RX Under
+ * @retval 1 Is RX Under
+ */
+#define __LL_I2C_IsRxUnder_Raw(__I2C__) \
+ (READ_BIT((__I2C__)->RINTRST, I2C_RX_UNDER_RAW_INT_STA_Msk) >> I2C_RX_UNDER_RAW_INT_STA_Pos)
+
+
+/**
+ * @brief I2C RX Trigger Level Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param tl RX Trigger Level
+ * @return None
+ */
+#define __LL_I2C_RxTL_Set(__I2C__, tl) MODIFY_REG((__I2C__)->RXTL, I2C_RX_TL_Msk, (((tl-1) & 0xffUL) << I2C_RX_TL_Pos))
+
+/**
+ * @brief I2C TX Trigger Level Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param tl TX Trigger Level
+ * @return None
+ */
+#define __LL_I2C_TxTL_Set(__I2C__, tl) MODIFY_REG((__I2C__)->TXTL, I2C_TX_TL_Msk, (((tl-1) & 0xffUL) << I2C_TX_TL_Pos))
+
+
+/**
+ * @brief I2C Soft Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_SoftIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->INTRCR, I2C_CLR_INT_Msk) >> I2C_CLR_INT_Pos)
+
+
+/**
+ * @brief I2C RX Under Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_RxUnderRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->RXUNCR, I2C_CLR_RX_UNDER_Msk) >> I2C_CLR_RX_UNDER_Pos)
+
+
+/**
+ * @brief I2C RX Over Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_RxOverRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->RXOVCR, I2C_CLR_RX_OVER_Msk) >> I2C_CLR_RX_OVER_Pos)
+
+
+/**
+ * @brief I2C TX Over Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_TxOverRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->TXOVCR, I2C_CLR_TX_OVER_Msk) >> I2C_CLR_TX_OVER_Pos)
+
+
+/**
+ * @brief I2C Slave Read Request Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_SLV_ReadReqRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->RDREQCR, I2C_CLR_RD_REQ_Msk) >> I2C_CLR_RD_REQ_Pos)
+
+
+/**
+ * @brief I2C TX Abort Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_TxAbortRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->TXABCR, I2C_CLR_TX_ABRT_Msk) >> I2C_CLR_TX_ABRT_Pos)
+
+
+/**
+ * @brief I2C Slave RX Done Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_SLV_RxDoneRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->RXDOCR, I2C_CLR_RX_DONE_Msk) >> I2C_CLR_RX_DONE_Pos)
+
+
+/**
+ * @brief I2C Activity Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_ActivityRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->ACTICR, I2C_CLR_ACTIVITY_Msk) >> I2C_CLR_ACTIVITY_Pos)
+
+
+/**
+ * @brief I2C Stop Detect Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_StopDetRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->SPDETCR, I2C_CLR_STOP_DET_Msk) >> I2C_CLR_STOP_DET_Pos)
+
+
+/**
+ * @brief I2C Start Detect Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_StartDetRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->STDETCR, I2C_CLR_START_DET_Msk) >> I2C_CLR_START_DET_Pos)
+
+
+/**
+ * @brief I2C Slave Genaral Call Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_SLV_GenCallRawIntSta_Clr(__I2C__) (READ_BIT((__I2C__)->GCCR, I2C_CLR_GEN_CALL_Msk) >> I2C_CLR_GEN_CALL_Pos)
+
+
+/**
+ * @brief I2C SMBUS Alert Enable Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_AlertEn_Set(__I2C__) SET_BIT((__I2C__)->ENABLE, I2C_SMBUS_ALERT_EN_Msk)
+
+/**
+ * @brief I2C SMBUS Alert Enable Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_AlertEn_Clr(__I2C__) CLEAR_BIT((__I2C__)->ENABLE, I2C_SMBUS_ALERT_EN_Msk)
+
+/**
+ * @brief I2C SMBUS Suspend Enable Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SuspendEn_Set(__I2C__) SET_BIT((__I2C__)->ENABLE, I2C_SMBUS_SUSPEND_EN_Msk)
+
+/**
+ * @brief I2C SMBUS Suspend Enable Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SuspendEn_Clr(__I2C__) CLEAR_BIT((__I2C__)->ENABLE, I2C_SMBUS_SUSPEND_EN_Msk)
+
+/**
+ * @brief I2C SMBUS CLK Reset Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ClkReset_Set(__I2C__) SET_BIT((__I2C__)->ENABLE, I2C_SMBUS_CLK_RESET_Msk)
+
+/**
+ * @brief I2C SMBUS CLK Reset Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ClkReset_Clr(__I2C__) CLEAR_BIT((__I2C__)->ENABLE, I2C_SMBUS_CLK_RESET_Msk)
+
+/**
+ * @brief I2C SDA Stuck Recovery Enable Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SDAStuckRecoveryEn_Set(__I2C__) SET_BIT((__I2C__)->ENABLE, I2C_SDA_STK_RECOVERY_EN_Msk)
+
+/**
+ * @brief I2C Master TX Cmd Block Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_TxCmdBlock_Set(__I2C__) SET_BIT((__I2C__)->ENABLE, I2C_TX_CMD_BLOCK_Msk)
+
+/**
+ * @brief I2C Master TX Cmd Block Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_TxCmdBlock_Clr(__I2C__) CLEAR_BIT((__I2C__)->ENABLE, I2C_TX_CMD_BLOCK_Msk)
+
+/**
+ * @brief I2C Master Abort Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_MST_Abort_Set(__I2C__) SET_BIT((__I2C__)->ENABLE, I2C_ABORT_Msk)
+
+/**
+ * @brief I2C Module Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Enable(__I2C__) SET_BIT((__I2C__)->ENABLE, I2C_ENABLE_Msk)
+
+/**
+ * @brief I2C Module Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_Disable(__I2C__) CLEAR_BIT((__I2C__)->ENABLE, I2C_ENABLE_Msk)
+
+
+/**
+ * @brief Judge SMBUS Alert Status or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't alert status
+ * @retval 1 Is alert status
+ */
+#define __LL_I2C_SMBUS_IsAlertSta(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_SMBUS_ALERT_STATUS_Msk) >> I2C_SMBUS_ALERT_STATUS_Pos)
+
+/**
+ * @brief Judge SMBUS Suspend Status or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't Suspend status
+ * @retval 1 Is Suspend status
+ */
+#define __LL_I2C_SMBUS_IsSuspendSta(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_SMBUS_SUSPEND_STATUS_Msk) >> I2C_SMBUS_SUSPEND_STATUS_Pos)
+
+/**
+ * @brief Judge SMBUS Slave Address Resolved or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS Slave Address Isn't Resolved
+ * @retval 1 SMBUS Slave Address Is Resolved
+ */
+#define __LL_I2C_SMBUS_IsSlvAddrResolved(__I2C__) \
+ (READ_BIT((__I2C__)->STATUS, I2C_SMBUS_SLV_ADDR_RESOLVED_Msk) >> I2C_SMBUS_SLV_ADDR_RESOLVED_Pos)
+
+/**
+ * @brief Judge SMBUS Slave Address Valid or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS Slave Address Isn't Valid
+ * @retval 1 SMBUS Slave Address Is Valid
+ */
+#define __LL_I2C_SMBUS_IsSlvAddrValid(__I2C__) \
+ (READ_BIT((__I2C__)->STATUS, I2C_SMBUS_SLV_ADDR_VALID_Msk) >> I2C_SMBUS_SLV_ADDR_VALID_Pos)
+
+/**
+ * @brief I2C SMBUS Quick Cmd Bit
+ * @param __I2C__ Specifies I2C peripheral
+ * @return SMBUS Quick Cmd Bit(R/W)
+ */
+#define __LL_I2C_SMBUS_QuickCmdBit(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_SMBUS_QUICK_CMD_BIT_Msk) >> I2C_SMBUS_QUICK_CMD_BIT_Pos)
+
+/**
+ * @brief Judge SDA Stuck No Recovered or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SDA Stuck has Recovered
+ * @retval 1 SDA Stuck hasn't Recovered
+ */
+#define __LL_I2C_IsSDAStuckNoRecovered(__I2C__) \
+ (READ_BIT((__I2C__)->STATUS, I2C_SDA_STUCK_NOT_RECOVERED_Msk) >> I2C_SDA_STUCK_NOT_RECOVERED_Pos)
+
+/**
+ * @brief Judge Slave Hold RX FIFO Full or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave Isn't Holding RX FIFO Full
+ * @retval 1 Slave Is Holding RX FIFO Full
+ */
+#define __LL_I2C_SLV_IsHoldRxFIFOFull(__I2C__) \
+ (READ_BIT((__I2C__)->STATUS, I2C_SLV_HOLD_RX_FIFO_FULL_Msk) >> I2C_SLV_HOLD_RX_FIFO_FULL_Pos)
+
+/**
+ * @brief Judge Slave Hold Tx FIFO Empty or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave Isn't Holding Tx FIFO Empty
+ * @retval 1 Slave Is Holding Tx FIFO Empty
+ */
+#define __LL_I2C_SLV_IsHoldTxFIFOEmpty(__I2C__) \
+ (READ_BIT((__I2C__)->STATUS, I2C_SLV_HOLD_TX_FIFO_EMPTY_Msk) >> I2C_SLV_HOLD_TX_FIFO_EMPTY_Pos)
+
+/**
+ * @brief Judge Master Hold RX FIFO Full or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Master Isn't Holding RX FIFO Full
+ * @retval 1 Master Is Holding RX FIFO Full
+ */
+#define __LL_I2C_MST_IsHoldRxFIFOFull(__I2C__) \
+ (READ_BIT((__I2C__)->STATUS, I2C_MST_HOLD_RX_FIFO_FULL_Msk) >> I2C_MST_HOLD_RX_FIFO_FULL_Pos)
+
+/**
+ * @brief Judge Master Hold Tx FIFO Empty or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Master Isn't Holding Tx FIFO Empty
+ * @retval 1 Master Is Holding Tx FIFO Empty
+ */
+#define __LL_I2C_MST_IsHoldTxFIFOEmpty(__I2C__) \
+ (READ_BIT((__I2C__)->STATUS, I2C_MST_HOLD_TX_FIFO_EMPTY_Msk) >> I2C_MST_HOLD_TX_FIFO_EMPTY_Pos)
+
+/**
+ * @brief Judge Slave Activity or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave Isn't Activity
+ * @retval 1 Slave Is Activity
+ */
+#define __LL_I2C_SLV_IsActivity(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_SLV_ACTIVITY_Msk) >> I2C_SLV_ACTIVITY_Pos)
+
+/**
+ * @brief Judge Master Activity or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Master Isn't Activity
+ * @retval 1 Master Is Activity
+ */
+#define __LL_I2C_MST_IsActivity(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_MST_ACTIVITY_Msk) >> I2C_MST_ACTIVITY_Pos)
+
+/**
+ * @brief Judge RXFIFO Full Entirely or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 RXFIFO isn't full Entirely
+ * @retval 1 RXFIFO is full Entirely
+ */
+#define __LL_I2C_IsRxFIFOFull(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_RFF_Msk) >> I2C_RFF_Pos)
+
+/**
+ * @brief Judge RXFIFO Not Empty or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 RXFIO is empty
+ * @retval 1 RXFIO isn't empty
+ */
+#define __LL_I2C_IsRxFIFONotEmpty(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_RFNE_Msk) >> I2C_RFNE_Pos)
+
+/**
+ * @brief Judge TXFIFO Empty or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 TXFIFO isn't empty
+ * @retval 1 TXFIFO is empty
+ */
+#define __LL_I2C_IsTxFIFOEmpty(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_TFE_Msk) >> I2C_TFE_Pos)
+
+/**
+ * @brief Judge TXFIFO Not Full or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 TXFIFO is Full
+ * @retval 1 TXFIFO isn't Full
+ */
+#define __LL_I2C_IsTxFIFONotFull(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_TFNF_Msk) >> I2C_TFNF_Pos)
+
+/**
+ * @brief Judge I2C Activity or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 I2C isn't activity
+ * @retval 1 I2C is activity
+ */
+#define __LL_I2C_IsActivitySta(__I2C__) (READ_BIT((__I2C__)->STATUS, I2C_ACTIVITY_Msk) >> I2C_ACTIVITY_Pos)
+
+
+/**
+ * @brief I2C TXFIFO Level Get
+ * @param __I2C__ Specifies I2C peripheral
+ * @return TXFIFO Level
+ */
+#define __LL_I2C_TxFIFOLevel_Get(__I2C__) (READ_BIT((__I2C__)->TXFLR, I2C_TXFLR_Msk) >> I2C_TXFLR_Pos)
+
+
+/**
+ * @brief I2C RXFIFO Level Get
+ * @param __I2C__ Specifies I2C peripheral
+ * @return RXFIFO Level
+ */
+#define __LL_I2C_RxFIFOLevel_Get(__I2C__) (READ_BIT((__I2C__)->RXFLR, I2C_RXFLR_Msk) >> I2C_RXFLR_Pos)
+
+
+/**
+ * @brief I2C SDA RX Hold Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param hld SDA RX Hold
+ * @return None
+ */
+#define __LL_I2C_SDARxHold_Set(__I2C__, hld) \
+ MODIFY_REG((__I2C__)->SDA_HOLD, I2C_SDA_RX_HOLD_Msk, ((hld & 0xffUL) << I2C_SDA_RX_HOLD_Pos))
+
+/**
+ * @brief I2C SDA TX Hold Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param hld SDA TX Hold
+ * @return None
+ */
+#define __LL_I2C_SDATxHold_Set(__I2C__, hld) \
+ MODIFY_REG((__I2C__)->SDA_HOLD, I2C_SDA_TX_HOLD_Msk, ((hld & 0xffffUL) << I2C_SDA_TX_HOLD_Pos))
+
+
+/**
+ * @brief I2C TX Flush Count Get
+ * @param __I2C__ Specifies I2C peripheral
+ * @return TX Flush Count
+ */
+#define __LL_I2C_TxFlushCnt_Get(__I2C__) (READ_BIT((__I2C__)->TXABSR, I2C_TX_FLUSH_CNT_Msk) >> I2C_TX_FLUSH_CNT_Pos)
+
+/**
+ * @brief Judge Master Abort Source Device Write or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Device Write
+ * @retval 1 Abort Source Is Device Write
+ */
+#define __LL_I2C_MST_AbortSrc_IsDevWrite(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_DEV_WRITE_Msk) >> I2C_ABRT_DEV_WRITE_Pos)
+
+/**
+ * @brief Judge Master Abort Source Device Slave Address No ACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Device Slave Address No ACK
+ * @retval 1 Abort Source Is Device Slave Address No ACK
+ */
+#define __LL_I2C_MST_AbortSrc_IsDevSlvAddrNoAck(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_DEV_SLV_ADDR_NOACK_Msk) >> I2C_ABRT_DEV_SLV_ADDR_NOACK_Pos)
+
+/**
+ * @brief Judge Master Abort Source Device No ACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Device No ACK
+ * @retval 1 Abort Source Is Device No ACK
+ */
+#define __LL_I2C_MST_AbortSrc_IsDevNoAck(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_DEV_NOACK_Msk) >> I2C_ABRT_DEV_NOACK_Pos)
+
+/**
+ * @brief Judge Master Abort Source SDA Stuck at Low or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't SDA Stuck at Low
+ * @retval 1 Abort Source Is SDA Stuck at Low
+ */
+#define __LL_I2C_MST_AbortSrc_IsSDAStuckAtLow(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_SDA_STUCK_AT_LOW_Msk) >> I2C_ABRT_SDA_STUCK_AT_LOW_Pos)
+
+/**
+ * @brief Judge Master Abort Source User Abort or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't User Abort
+ * @retval 1 Abort Source Is User Abort
+ */
+#define __LL_I2C_MST_AbortSrc_IsUserAbort(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_USER_ABRT_Msk) >> I2C_ABRT_USER_ABRT_Pos)
+
+/**
+ * @brief Judge Slave Abort Source Slave Read In TX or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Slave Read In TX
+ * @retval 1 Abort Source Is Slave Read In TX
+ */
+#define __LL_I2C_SLV_AbortSrc_IsSlvReadInTx(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_SLVRD_INTX_Msk) >> I2C_ABRT_SLVRD_INTX_Pos)
+
+/**
+ * @brief Judge Slave Abort Source Slave Lost Bus or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Slave Lost Bus
+ * @retval 1 Abort Source Is Slave Lost Bus
+ */
+#define __LL_I2C_SLV_AbortSrc_IsSlvLostBus(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_SLV_ARBLOST_Msk) >> I2C_ABRT_SLV_ARBLOST_Pos)
+
+/**
+ * @brief Judge Slave Abort Source Slave Flush TXFIFO or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Slave Flush TXFIFO
+ * @retval 1 Abort Source Is Slave Flush TXFIFO
+ */
+#define __LL_I2C_SLV_AbortSrc_IsSlvFlushTxFIFO(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_SLVFLUSH_TXFIFO_Msk) >> I2C_ABRT_SLVFLUSH_TXFIFO_Pos)
+
+/**
+ * @brief Judge Abort Source ARB Lost or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't ARB Lost
+ * @retval 1 Abort Source Is ARB Lost
+ */
+#define __LL_I2C_AbortSrc_IsArbLost(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ARB_LOST_Msk) >> I2C_ARB_LOST_Pos)
+
+/**
+ * @brief Judge Abort Source Master Disable or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Master Disable
+ * @retval 1 Abort Source Is Master Disable
+ */
+#define __LL_I2C_AbortSrc_IsMasterDis(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_MASTER_DIS_Msk) >> I2C_ABRT_MASTER_DIS_Pos)
+
+/**
+ * @brief Judge Master Abort Source 10bit Read No Restart or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't 10bit Read No Restart
+ * @retval 1 Abort Source Is 10bit Read No Restart
+ */
+#define __LL_I2C_MST_AbortSrc_Is10bReadNoRestart(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_10B_RD_NORSTRT_Msk) >> I2C_ABRT_10B_RD_NORSTRT_Pos)
+
+/**
+ * @brief Judge Master Abort Source Send Start No Restart or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Send Start No Restart
+ * @retval 1 Abort Source Is Send Start No Restart
+ */
+#define __LL_I2C_MST_AbortSrc_IsSendStartNoRestart(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_SBYTE_NORSTRT_Msk) >> I2C_ABRT_SBYTE_NORSTRT_Pos)
+
+/**
+ * @brief Judge Master Abort Source HS No Restart or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't HS No Restart
+ * @retval 1 Abort Source Is HS No Restart
+ */
+#define __LL_I2C_MST_AbortSrc_IsHsNoRestart(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_HS_NORSTRT_Msk) >> I2C_ABRT_HS_NORSTRT_Pos)
+
+/**
+ * @brief Judge Master Abort Source Send Start ACK Detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Send Start ACK Detect
+ * @retval 1 Abort Source Is Send Start ACK Detect
+ */
+#define __LL_I2C_MST_AbortSrc_IsSendStartAckDet(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_SBYTE_ACKDET_Msk) >> I2C_ABRT_SBYTE_ACKDET_Pos)
+
+/**
+ * @brief Judge Master Abort Source HS ACK Detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't HS ACK Detect
+ * @retval 1 Abort Source Is HS ACK Detect
+ */
+#define __LL_I2C_MST_AbortSrc_IsHsAckDet(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_HS_ACKDET_Msk) >> I2C_ABRT_HS_ACKDET_Pos)
+
+/**
+ * @brief Judge Master Abort Source Genaral Call Read or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Genaral Call Read
+ * @retval 1 Abort Source Is Genaral Call Read
+ */
+#define __LL_I2C_MST_AbortSrc_IsGenCallRead(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_GCALL_READ_Msk) >> I2C_ABRT_GCALL_READ_Pos)
+
+/**
+ * @brief Judge Master Abort Source Genaral Call No ACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't Genaral Call No ACK
+ * @retval 1 Abort Source Is Genaral Call No ACK
+ */
+#define __LL_I2C_MST_AbortSrc_IsGenCallNoAck(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_GCALL_NOACK_Msk) >> I2C_ABRT_GCALL_NOACK_Pos)
+
+/**
+ * @brief Judge Master Abort Source TX Data No ACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't TX Data No ACK
+ * @retval 1 Abort Source Is TX Data No ACK
+ */
+#define __LL_I2C_MST_AbortSrc_IsTxDataNoAck(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_TXDATA_NOACK_Msk) >> I2C_ABRT_TXDATA_NOACK_Pos)
+
+/**
+ * @brief Judge Master Abort Source 10b Address 2 No ACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't 10b Address 2 No ACK
+ * @retval 1 Abort Source Is 10b Address 2 No ACK
+ */
+#define __LL_I2C_MST_AbortSrc_Is10bAddr2NoAck(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_10ADDR2_NOACK_Msk) >> I2C_ABRT_10ADDR2_NOACK_Pos)
+
+/**
+ * @brief Judge Master Abort Source 10b Address 1 No ACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't 10b Address 1 No ACK
+ * @retval 1 Abort Source Is 10b Address 1 No ACK
+ */
+#define __LL_I2C_MST_AbortSrc_Is10bAddr1NoAck(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_10ADDR1_NOACK_Msk) >> I2C_ABRT_10ADDR1_NOACK_Pos)
+
+/**
+ * @brief Judge Master Abort Source 7b Address No ACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Abort Source Isn't 7b Address No ACK
+ * @retval 1 Abort Source Is 7b Address No ACK
+ */
+#define __LL_I2C_MST_AbortSrc_Is7bAddrNoAck(__I2C__) \
+ (READ_BIT((__I2C__)->TXABSR, I2C_ABRT_7B_ADDR_NOACK_Msk) >> I2C_ABRT_7B_ADDR_NOACK_Pos)
+
+
+/**
+ * @brief I2C Slave Force Data No ACK Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_ForceDataNoAck_Set(__I2C__) SET_BIT((__I2C__)->NACKEN, I2C_SLV_DATA_NACK_Msk)
+
+/**
+ * @brief I2C Slave Force Data No ACK Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SLV_ForceDataNoAck_Clr(__I2C__) CLEAR_BIT((__I2C__)->NACKEN, I2C_SLV_DATA_NACK_Msk)
+
+
+/**
+ * @brief I2C TX DMA Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxDMA_En(__I2C__) SET_BIT((__I2C__)->DMACT, I2C_DMA_TDMAE_Msk)
+
+/**
+ * @brief I2C TX DMA Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_TxDMA_Dis(__I2C__) CLEAR_BIT((__I2C__)->DMACT, I2C_DMA_TDMAE_Msk)
+
+/**
+ * @brief I2C RX DMA Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxDMA_En(__I2C__) SET_BIT((__I2C__)->DMACT, I2C_DMA_RDMAE_Msk)
+
+/**
+ * @brief I2C RX DMA Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_RxDMA_Dis(__I2C__) CLEAR_BIT((__I2C__)->DMACT, I2C_DMA_RDMAE_Msk)
+
+
+/**
+ * @brief I2C TX DMA Trigger Level Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param tl TX DMA Trigger Level
+ * @return None
+ */
+#define __LL_I2C_TxDMATriggerLevel_Set(__I2C__, tl) \
+ MODIFY_REG((__I2C__)->DMATDLR, I2C_DMA_DMATDL_Msk, ((tl & 0xfUL) << I2C_DMA_DMATDL_Pos))
+
+
+/**
+ * @brief I2C RX DMA Trigger Level Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param tl RX DMA Trigger Level
+ * @return None
+ */
+#define __LL_I2C_RxDMATriggerLevel_Set(__I2C__, tl) \
+ MODIFY_REG((__I2C__)->DMARDLR, I2C_DMA_DMARDL_Msk, (((tl-1) & 0xfUL) << I2C_DMA_DMARDL_Pos))
+
+
+#define __LL_I2C_SDA_Setup_Set(__I2C__, val) \
+ MODIFY_REG((__I2C__)->SDA_SETUP, I2C_SDA_SETUP_Msk, ((val & 0xffUL) << I2C_SDA_SETUP_Pos))
+
+
+/**
+ * @brief I2C ACK Genaral Call Enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_AckGenCall_En(__I2C__) SET_BIT((__I2C__)->GCACK, I2C_ACK_GEN_CALL_Msk)
+
+/**
+ * @brief I2C ACK Genaral Call Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_AckGenCall_Dis(__I2C__) CLEAR_BIT((__I2C__)->GCACK, I2C_ACK_GEN_CALL_Msk)
+
+
+/**
+ * @brief Judge Slave RX Data Lost or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Slave Isn't RX Data Lost
+ * @retval 1 Slave Is RX Data Lost
+ */
+#define __LL_I2C_SLV_IsRxDataLost(__I2C__) \
+ (READ_BIT((__I2C__)->ENST, I2C_SLV_RX_DATA_LOST_Msk) >> I2C_SLV_RX_DATA_LOST_Pos)
+
+/**
+ * @brief Judge Slave Disable While Busy or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 Isn't Slave Disable While Busy
+ * @retval 1 Is Slave Disable While Busy
+ */
+#define __LL_I2C_SLV_IsSlvDisWhileBusy(__I2C__) \
+ (READ_BIT((__I2C__)->ENST, I2C_SLVDIS_WHILEBUSY_Msk) >> I2C_SLVDIS_WHILEBUSY_Pos)
+
+/**
+ * @brief Judge I2C Enable or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 I2C Isn't Enable
+ * @retval 1 I2C Is Enable
+ */
+#define __LL_I2C_IsEnable(__I2C__) (READ_BIT((__I2C__)->ENST, I2C_EN_Msk) >> I2C_EN_Pos)
+
+
+/**
+ * @brief I2C FS Spike Lengh Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param len FS Spike Lengh
+ * @return None
+ */
+#define __LL_I2C_FsSpkLen_Set(__I2C__, len) \
+ MODIFY_REG((__I2C__)->FS_SPKLEN, I2C_FS_SPKLEN_Msk, ((len & 0xffUL) << I2C_FS_SPKLEN_Pos))
+
+
+/**
+ * @brief I2C Restart Detect RAW Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_RestartDetRawIntSta_Clr(__I2C__) \
+ (READ_BIT((__I2C__)->RSDETCR, I2C_CLR_RESTART_DET_Msk) >> I2C_CLR_RESTART_DET_Pos)
+
+
+/**
+ * @brief I2C SCL Stuck at Low Timeout Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param val Timeout Value
+ * @return None
+ */
+#define __LL_I2C_SCLStuckAtLowTimeout_Set(__I2C__, val) MODIFY_REG((__I2C__)->SCLLTO,\
+ I2C_SCL_STK_LOW_TIMEOUT_Msk, ((val & 0xffffffffUL) << I2C_SCL_STK_LOW_TIMEOUT_Pos))
+
+
+/**
+ * @brief I2C SDA Stuck at Low Timeout Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param val Timeout Value
+ * @return None
+ */
+#define __LL_I2C_SDAStuckAtLowTimeout_Set(__I2C__, val) MODIFY_REG((__I2C__)->SDALTO,\
+ I2C_SDA_STK_LOW_TIMEOUT_Msk, ((val & 0xffffffffUL) << I2C_SDA_STK_LOW_TIMEOUT_Pos))
+
+
+/**
+ * @brief I2C SCL Stuck Detect RAW Interrupt Status Clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return Read Value, not use
+ */
+#define __LL_I2C_SCLStuckDetRawIntSta_Clr(__I2C__) \
+ (READ_BIT((__I2C__)->SSTDETCR, I2C_CLR_SCL_STK_Msk) >> I2C_CLR_SCL_STK_Pos)
+
+
+/**
+ * @brief I2C Device ID Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param id Device ID
+ * @return None
+ */
+#define __LL_I2C_DeviceID_Set(__I2C__, id) MODIFY_REG((__I2C__)->DEVICE_ID, I2C_DEV_ID_Msk, ((id & 0xffffffUL) << I2C_DEV_ID_Pos))
+
+
+/**
+ * @brief I2C SMBUS Clock Low Sext Timeout Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param val Timeout Value
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ClkLowSextTimeout_Set(__I2C__, val) MODIFY_REG((__I2C__)->TSEXT,\
+ I2C_SMBUS_CLK_LOW_SEXT_TIMEOUT_Msk, ((val & 0xffffffffUL) << I2C_SMBUS_CLK_LOW_SEXT_TIMEOUT_Pos))
+
+
+/**
+ * @brief I2C SMBUS Clock Low Mext Timeout Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param val Timeout Value
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ClkLowMextTimeout_Set(__I2C__, val) MODIFY_REG((__I2C__)->TMEXT,\
+ I2C_SMBUS_CLK_LOW_MEXT_TIMEOUT_Msk, ((val & 0xffffffffUL) << I2C_SMBUS_CLK_LOW_MEXT_TIMEOUT_Pos))
+
+
+/**
+ * @brief I2C SMBUS Thigh Max Bus Idle Count Set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param cnt Count
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ThighMaxBusIdleCnt_Set(__I2C__, cnt) MODIFY_REG((__I2C__)->IDCNT,\
+ I2C_SMBUS_THIGH_MAX_BUS_IDLE_CNT_Msk, ((cnt & 0xffffUL) << I2C_SMBUS_THIGH_MAX_BUS_IDLE_CNT_Pos))
+
+
+/**
+ * @brief Judge SMBUS is alert detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't alert detect
+ * @retval 1 SMBUS is alert detect
+ */
+#define __LL_I2C_SMBUS_IsAlertDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_SMBUS_ALERT_DET_INT_STA_Msk) << I2C_SMBUS_ALERT_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is suspend detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't suspend detect
+ * @retval 1 SMBUS is suspend detect
+ */
+#define __LL_I2C_SMBUS_IsSuspendDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_SMBUS_SUSPEND_DET_INT_STA_Msk) << I2C_SMBUS_SUSPEND_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is slave RX PEC NACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't slave RX PEC NACK
+ * @retval 1 SMBUS is slave RX PEC NACK
+ */
+#define __LL_I2C_SMBUS_IsSlvRxPecNack(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_SLV_RX_PEC_NACK_INT_STA_Msk) << I2C_SLV_RX_PEC_NACK_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP assgn address cmd detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP assgn address cmd detect
+ * @retval 1 SMBUS is ARP assgn address cmd detect
+ */
+#define __LL_I2C_SMBUS_IsARPAssgnAddrCmdDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_ARP_ASSGN_ADDR_CMD_DET_INT_STA_Msk) << I2C_ARP_ASSGN_ADDR_CMD_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP get UDID cmd detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP get UDID cmd detect
+ * @retval 1 SMBUS is ARP get UDID cmd detect
+ */
+#define __LL_I2C_SMBUS_IsARPGetUdidCmdDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_ARP_GET_UDID_CMD_DET_INT_STA_Msk) << I2C_ARP_GET_UDID_CMD_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP reset cmd detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP reset cmd detect
+ * @retval 1 SMBUS is ARP reset cmd detect
+ */
+#define __LL_I2C_SMBUS_IsARPRstCmdDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_ARP_RST_CMD_DET_INT_STA_Msk) << I2C_ARP_RST_CMD_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP prepare cmd detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP prepare cmd detect
+ * @retval 1 SMBUS is ARP prepare cmd detect
+ */
+#define __LL_I2C_SMBUS_IsARPPrepareCmdDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_ARP_PREPARE_CMD_DET_INT_STA_Msk) << I2C_ARP_PREPARE_CMD_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is host nofity mst detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't host nofity mst detect
+ * @retval 1 SMBUS is host nofity mst detect
+ */
+#define __LL_I2C_SMBUS_IsHostNotifyMstDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_HOST_NOTIFY_MST_DET_INT_STA_Msk) << I2C_HOST_NOTIFY_MST_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is quick cmd detect or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't quick cmd detect
+ * @retval 1 SMBUS is quick cmd detect
+ */
+#define __LL_I2C_SMBUS_IsQuickCmdDet(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_QUICK_CMD_DET_INT_STA_Msk) << I2C_QUICK_CMD_DET_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is mst clock extend timeout or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't mst clock extend timeout
+ * @retval 1 SMBUS is mst clock extend timeout
+ */
+#define __LL_I2C_SMBUS_IsMstClkExtendTimeout(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_MST_CLK_EXTND_TIMEOUT_INT_STA_Msk) << I2C_MST_CLK_EXTND_TIMEOUT_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is slave clock extend timeout or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't slave clock extend timeout
+ * @retval 1 SMBUS is slave clock extend timeout
+ */
+#define __LL_I2C_SMBUS_IsSlvClkExtendTimeout(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRST, I2C_SLV_CLK_EXTND_TIMEOUT_INT_STA_Msk) << I2C_SLV_CLK_EXTND_TIMEOUT_INT_STA_Pos)
+
+
+/**
+ * @brief SMBUS alert detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_AlertDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_SMBUS_ALERT_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS alert detect interrupt Disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_AlertDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_SMBUS_ALERT_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS Suspend detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SuspendDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_SMBUS_SUSPEND_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS Suspend detect interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SuspendDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_SMBUS_SUSPEND_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS slave RX PEC NACK interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvRxPecNack_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_SLV_RX_PEC_NACK_INT_EN_Msk)
+
+/**
+ * @brief SMBUS slave RX PEC NACK interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvRxPecNack_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_SLV_RX_PEC_NACK_INT_EN_Msk)
+
+/**
+ * @brief SBMUS ARP assgn addr cmd detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPAssgnAddrCmdDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_ARP_ASSGN_ADDR_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SBMUS ARP assgn addr cmd detect interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPAssgnAddrCmdDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_ARP_ASSGN_ADDR_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS ARP get UDID cmd detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPGetUdidCmdDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_ARP_GET_UDID_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS ARP get UDID cmd detect interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPGetUdidCmdDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_ARP_GET_UDID_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS ARP reset cmd detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPRstCmdDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_ARP_RST_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS ARP reset cmd detect interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPRstCmdDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_ARP_RST_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS ARP prepare cmd detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPPrepareCmdDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_ARP_PREPARE_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS ARP prepare cmd detect interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPPrepareCmdDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_ARP_PREPARE_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS host notify master detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_HostNotifyMstDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_HOST_NOTIFY_MST_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS host notify master detect interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_HostNotifyMstDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_HOST_NOTIFY_MST_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS quick cmd detect interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_QuickCmdDet_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_QUICK_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS quick cmd detect interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_QuickCmdDet_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_QUICK_CMD_DET_INT_EN_Msk)
+
+/**
+ * @brief SMBUS master clock extend timeout interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_MstClkExtendTimeout_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_MST_CLK_EXTND_TIMEOUT_INT_EN_Msk)
+
+/**
+ * @brief SMBUS master clock extend timeout interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_MstClkExtendTimeout_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_MST_CLK_EXTND_TIMEOUT_INT_EN_Msk)
+
+/**
+ * @brief SMBUS slave clock extend timeout interrupt enable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvClkExtendTimeout_INT_En(__I2C__) SET_BIT((__I2C__)->SMINTRMS, I2C_SLV_CLK_EXTND_TIMEOUT_INT_EN_Msk)
+
+/**
+ * @brief SMBUS slave clock extend timeout interrupt disable
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvClkExtendTimeout_INT_Dis(__I2C__) CLEAR_BIT((__I2C__)->SMINTRMS, I2C_SLV_CLK_EXTND_TIMEOUT_INT_EN_Msk)
+
+
+/**
+ * @brief Judge SMBUS is alert detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't alert detect raw
+ * @retval 1 SMBUS is alert detect raw
+ */
+#define __LL_I2C_SMBUS_IsAlertDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_SMBUS_ALERT_DET_RAW_INT_STA_Msk) << I2C_SMBUS_ALERT_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is suspend detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't suspend detect raw
+ * @retval 1 SMBUS is suspend detect raw
+ */
+#define __LL_I2C_SMBUS_IsSuspendDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_SMBUS_SUSPEND_DET_RAW_INT_STA_Msk) << I2C_SMBUS_SUSPEND_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is slave RX PEC NACK or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't slave RX PEC NACK
+ * @retval 1 SMBUS is slave RX PEC NACK
+ */
+#define __LL_I2C_SMBUS_IsSlvRxPecNackRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_SLV_RX_PEC_NACK_RAW_INT_STA_Msk) << I2C_SLV_RX_PEC_NACK_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP assgn address cmd detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP assgn address cmd detect raw
+ * @retval 1 SMBUS is ARP assgn address cmd detect raw
+ */
+#define __LL_I2C_SMBUS_IsARPAssgnAddrCmdDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_ARP_ASSGN_ADDR_CMD_DET_RAW_INT_STA_Msk) << I2C_ARP_ASSGN_ADDR_CMD_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP get UDID cmd detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP get UDID cmd detect raw
+ * @retval 1 SMBUS is ARP get UDID cmd detect raw
+ */
+#define __LL_I2C_SMBUS_IsARPGetUdidCmdDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_ARP_GET_UDID_CMD_DET_RAW_INT_STA_Msk) << I2C_ARP_GET_UDID_CMD_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP reset cmd detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP reset cmd detect raw
+ * @retval 1 SMBUS is ARP reset cmd detect raw
+ */
+#define __LL_I2C_SMBUS_IsARPRstCmdDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_ARP_RST_CMD_DET_RAW_INT_STA_Msk) << I2C_ARP_RST_CMD_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is ARP prepare cmd detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't ARP prepare cmd detect raw
+ * @retval 1 SMBUS is ARP prepare cmd detect raw
+ */
+#define __LL_I2C_SMBUS_IsARPPrepareCmdDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_ARP_PREPARE_CMD_DET_RAW_INT_STA_Msk) << I2C_ARP_PREPARE_CMD_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is host nofity mst detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't host nofity mst detect raw
+ * @retval 1 SMBUS is host nofity mst detect raw
+ */
+#define __LL_I2C_SMBUS_IsHostNotifyMstDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_HOST_NOTIFY_MST_DET_RAW_INT_STA_Msk) << I2C_HOST_NOTIFY_MST_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is quick cmd detect raw or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't quick cmd detect raw
+ * @retval 1 SMBUS is quick cmd detect raw
+ */
+#define __LL_I2C_SMBUS_IsQuickCmdDetRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_QUICK_CMD_DET_RAW_INT_STA_Msk) << I2C_QUICK_CMD_DET_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is mst clock extend timeout or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't mst clock extend timeout
+ * @retval 1 SMBUS is mst clock extend timeout
+ */
+#define __LL_I2C_SMBUS_IsMstClkExtendTimeoutRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_MST_CLK_EXTND_TIMEOUT_RAW_INT_STA_Msk) << I2C_MST_CLK_EXTND_TIMEOUT_RAW_INT_STA_Pos)
+
+/**
+ * @brief Judge SMBUS is slave clock extend timeout or not
+ * @param __I2C__ Specifies I2C peripheral
+ * @retval 0 SMBUS isn't slave clock extend timeout
+ * @retval 1 SMBUS is slave clock extend timeout
+ */
+#define __LL_I2C_SMBUS_IsSlvClkExtendTimeoutRaw(__I2C__) \
+ (READ_BIT((__I2C__)->SMINTRRST, I2C_SLV_CLK_EXTND_TIMEOUT_RAW_INT_STA_Msk) << I2C_SLV_CLK_EXTND_TIMEOUT_RAW_INT_STA_Pos)
+
+
+/**
+ * @brief SMBUS alert detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_AlertDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_SMBUS_ALERT_DET_Msk)
+
+/**
+ * @brief SMBUS suspend detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SuspendDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_SMBUS_SUSPEND_DET_Msk)
+
+/**
+ * @brief SMBUS slave RX PEC NACK raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvRxPecNackRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_SLV_RX_PEC_NACK_Msk)
+
+/**
+ * @brief SMBUS ARP assgn addredd cmd detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPAssgnAddrCmdDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_ARP_ASSGN_ADDR_CMD_DET_Msk)
+
+/**
+ * @brief SMBUS ARP get UDID cmd detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPUdidCmdDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_ARP_GET_UDID_CMD_DET_Msk)
+
+/**
+ * @brief SMBUS ARP reset cmd detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPRstCmdDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_ARP_RST_CMD_DET_Msk)
+
+/**
+ * @brief SMBUS ARP prepare cmd detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPPrepareCmdDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_ARP_PREPARE_CMD_DET_Msk)
+
+/**
+ * @brief SMBUS host notify master detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_HostNotifyMstDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_HOST_NOTIFY_MST_DET_Msk)
+
+/**
+ * @brief SMBUS quick cmd detect raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_QuickCmdDetRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_QUICK_CMD_DET_Msk)
+
+/**
+ * @brief SMBUS master clock extend timeout raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_MstClkExtendTimeoutRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_MST_CLOCK_EXTND_TIMEOUT_Msk)
+
+/**
+ * @brief SMBUS Slave clock extend timeout raw interrupt status clear
+ * @param __I2C__ Specifies I2C peripheral
+ * @return None
+ */
+#define __LL_I2C_SMBUS_SlvClkExtendTimeoutRawIntSta_Clr(__I2C__) SET_BIT((__I2C__)->SMINTRCR, I2C_CLR_SLV_CLOCK_EXTND_TIMEOUT_Msk)
+
+
+/**
+ * @brief SMBUS optional SAR set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param sar optional SAR
+ * @return None
+ */
+#define __LL_I2C_SMBUS_OptionalSAR_Set(__I2C__, sar) \
+ MODIFY_REG((__I2C__)->SAROP, I2C_OPTIONAL_SAR_Msk, ((sar & 0x7fUL) << I2C_OPTIONAL_SAR_Pos))
+
+
+/**
+ * @brief SMBUS ARP UDID LSB set
+ * @param __I2C__ Specifies I2C peripheral
+ * @param lsb SMBUS ARP UDID LSB
+ * @return None
+ */
+#define __LL_I2C_SMBUS_ARPUdidLsb_Set(__I2C__, lsb) \
+ MODIFY_REG((__I2C__)->UDIDLSB, I2C_SMBUS_ARP_UDID_LSB_Msk, ((lsb & 0xffffffffUL) << I2C_SMBUS_ARP_UDID_LSB_Pos))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Types I2C LL Exported Types
+ * @brief I2C LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2C role definition
+ */
+typedef enum {
+ I2C_ROLE_MASTER, /*!< I2C role master */
+ I2C_ROLE_SLAVE, /*!< I2C role slave */
+} I2C_RoleETypeDef;
+
+/**
+ * @brief I2C address bit definition
+ */
+typedef enum {
+ I2C_ADDR_7BIT, /*!< I2C address mode 7b */
+ I2C_ADDR_10BIT, /*!< I2C address mode 10b */
+} I2C_AddrModeETypeDef;
+
+/**
+ * @brief I2C memmory address size definition
+ */
+typedef enum {
+ I2C_MEMADDR_SIZE_INVALID = 0, /*!< memmory address size invalid */
+ I2C_MEMADDR_SIZE_8BIT = 1, /*!< memmory address size 8bit */
+ I2C_MEMADDR_SIZE_16BIT = 2, /*!< memmory address size 16bit */
+ I2C_MEMADDR_SIZE_32BIT = 4, /*!< memmory address size 32bit */
+} I2C_MemAddrSizeETypeDef;
+
+
+/**
+ * @brief I2C user config
+ */
+typedef struct __I2C_UserCfgTypeDef {
+ I2C_RoleETypeDef role; /*!< role */
+ I2C_AddrModeETypeDef addr_mode; /*!< address mode */
+ uint32_t baudrate; /*!< baudrate */
+ uint16_t slave_addr; /*!< slave address */
+ LL_FuncStatusETypeDef smbus_enable; /*!< smbus enable */
+ uint32_t smbus_master_extend_clk; /*!< smbus master extend clk */
+ uint32_t smbus_slaver_extend_clk; /*!< smbus slaver extend clk */
+} I2C_UserCfgTypeDef;
+
+/**
+ * @brief I2C DMA Status
+ */
+typedef enum {
+ IIC_DMA_STATE_RESET = 0, /*!< DMA State Reset: not yet initialized or disabled */
+ IIC_DMA_STATE_READY, /*!< DMA State Ready: initialized and ready for use */
+ IIC_DMA_STATE_BUSY, /*!< DMA State Busy: process is ongoing */
+ IIC_DMA_STATE_ERROR, /*!< DMA State Error: process is Error */
+ IIC_DMA_STATE_FINISH, /*!< DMA State Finish: process has been finished */
+} I2C_DMAStatusTypeDef;
+
+/**
+ * @brief I2C frame definition
+ */
+typedef struct __I2C_FrameTypeDef {
+ I2C_TypeDef *Instance; /*!< I2C Reg base address */
+ uint16_t target_addr; /*!< target address */
+ uint32_t mem_addr; /*!< memory address */
+ I2C_MemAddrSizeETypeDef mem_addr_size; /*!< memory address size */
+ uint8_t *buf; /*!< buffer pointer */
+ uint32_t buf_len; /*!< buffer length */
+ uint32_t command; /*!< smbus_command */
+ uint16_t XferCount; /*!< I2C transfer counter */
+ uint32_t clk_cnt; /*!< I2C sent clk to read */
+#ifdef LL_DMA_MODULE_ENABLED
+ DMA_ChannelETypeDef dma_tx_ch; /*!< I2C Tx DMA Channel */
+ DMA_ChannelETypeDef dma_rx_ch; /*!< I2C Rx DMA Channel */
+ I2C_DMAStatusTypeDef TXdma_status; /*!< I2C DMA status */
+ I2C_DMAStatusTypeDef RXdma_status; /*!< I2C DMA status */
+#endif
+} I2C_FrameTypeDef;
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_I2C_Init(I2C_TypeDef *Instance, I2C_UserCfgTypeDef *user_cfg);
+LL_StatusETypeDef LL_I2C_DeInit(I2C_TypeDef *Instance);
+void LL_I2C_MspInit(I2C_TypeDef *Instance);
+void LL_I2C_MspDeInit(I2C_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_LL_Exported_Functions_Group2
+ * @{
+ */
+
+uint32_t LL_I2C_MasterWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+uint32_t LL_I2C_MasterRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_I2C_SlaveWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_I2C_SlaveRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout);
+uint32_t LL_SMBUS_MasterWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+uint32_t LL_SMBUS_MasterRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_SMBUS_SlaveRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_I2C_MasterWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_I2C_SlaveWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_I2C_MasterRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_I2C_SlaveRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_SMBUS_MasterWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_SMBUS_MasterRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_SMBUS_SlaveRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame);
+
+#ifdef LL_DMA_MODULE_ENABLED
+LL_StatusETypeDef LL_I2C_MasterWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_I2C_MasterRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_I2C_SlaveRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_I2C_SlaveWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_SMBUS_MasterWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_SMBUS_MasterRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+LL_StatusETypeDef LL_SMBUS_SlaveRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout);
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_LL_Exported_Functions_Group3
+ * @{
+ */
+void LL_I2C_IRQHandler(I2C_TypeDef *Instance, I2C_FrameTypeDef *hi2c);
+void LL_I2C_SCLStuckAtLowCallback(I2C_TypeDef *Instance);
+void LL_I2C_MstOnHoldCallback(I2C_TypeDef *Instance);
+void LL_I2C_SlvRestartDetCallback(I2C_TypeDef *Instance);
+void LL_I2C_SlvGenCallCallback(I2C_TypeDef *Instance);
+void LL_I2C_StartDetCallback(I2C_TypeDef *Instance);
+void LL_I2C_StopDetCallback(I2C_TypeDef *Instance);
+void LL_I2C_ActivityCallback(I2C_TypeDef *Instance);
+void LL_I2C_SlvRxDoneCallback(I2C_TypeDef *Instance);
+void LL_I2C_TxAbortCallback(I2C_TypeDef *Instance);
+void LL_I2C_SlvReadReqCallback(I2C_TypeDef *Instance);
+void LL_I2C_TxEmptyCallback(I2C_TypeDef *Instance);
+void LL_I2C_TxOverCallback(I2C_TypeDef *Instance);
+void LL_I2C_RxFullCallback(I2C_TypeDef *Instance);
+void LL_I2C_RxOverCallback(I2C_TypeDef *Instance);
+void LL_I2C_RxUnderCallback(I2C_TypeDef *Instance);
+void LL_SMBUS_SlvClkExtTimeoutCallback(I2C_TypeDef *Instance);
+void LL_SMBUS_MstClkExtTimeoutCallback(I2C_TypeDef *Instance);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _TMF5XXX_LL_I2C_H_ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_iir.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_iir.h
new file mode 100644
index 0000000000..0c48070ce6
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_iir.h
@@ -0,0 +1,354 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_iir.h
+ * @author MCD Application Team
+ * @brief Header file of IIR LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_IIR_H_
+#define _TAE32F53XX_LL_IIR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup IIR_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IIR_LL_Exported_Types IIR LL Exported Types
+ * @brief IIR LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief IIR Order type definition
+ */
+typedef enum {
+ IIR_ORDER_1 = 0x00000000UL, /*!< Source Peripheral bus AHB Master1 */
+ IIR_ORDER_2 = IIR_CR0_ORD_0, /*!< IIR order 2 */
+ IIR_ORDER_3 = IIR_CR0_ORD_1, /*!< IIR order 3 */
+ IIR_ORDER_4 = (IIR_CR0_ORD_0 | IIR_CR0_ORD_1), /*!< IIR order 4 */
+} IIR_OrderETypeDef;
+
+/*
+ * @brief IIR internal data buffer reset or not
+ */
+typedef enum {
+ IIR_BUFFER_NO_RESET = 0x00000000UL, /*!< Do nothing to IIR Internal Data Buffer */
+ IIR_BUFFER_RESET = IIR_CR0_IBRST, /*!< IIR Internal Data Buffer should reset */
+} IIR_BufferETypeDef;
+
+
+/**
+ * @brief IIR Auto-Reload mode enable or disable
+ */
+typedef enum {
+ IIR_AUTORELOAD_DISABLE = 0x00000000UL, /*!< IIR Auto-Reload mode disable */
+ IIR_AUTORELOAD_ENABLE = IIR_CR1_AREN, /*!< IIR Auto-Reload mode enable */
+} IIR_ATReloadETypeDef;
+
+/**
+ * @brief IIR initialization structure definition
+ */
+typedef struct __IIR_InitTypeDef {
+ IIR_OrderETypeDef Order; /*!< Specifies the IIR order */
+ IIR_BufferETypeDef BufferReset; /*!< Indicate to reset the internal data buffer or not */
+} IIR_InitTypeDef;
+
+/**
+ * @brief IIR configuration structure definition
+ */
+typedef struct __IIR_ConfigTypeDef {
+ uint32_t InDataAddress; /*!< Specifies the input data address in memory area.
+ The address must be aligned to 16-bit boundary in specifies memory areas(For
+ more information, please see the documents of system architecture designs) */
+
+ uint32_t InDataScale; /*!< Specifies magnify scale for the input data.
+ This parameter can be a value between 0 to 16 which stand for the input data
+ magnified 2^0 to 2^16 times */
+
+ uint32_t FeedBackScale; /*!< Specifies the feekback narrow scale.
+ This parameter can be a value between 0 to 31 which stand for feedback
+ narrowed 2^0 to 2^31 times */
+
+ uint32_t OutDataScale; /*!< Specifies narrow scale for the output data.
+ This parameter can be a value between 0 to 31 which stand for the output data
+ narrowed 2^0 to 2^31 times */
+
+ int16_t AxCOEF[4]; /*!< Specifies the coefficient A.
+ This parameter can be a value between -32768 to +32767 */
+
+ int16_t BxCOEF[5]; /*!< Specifies the coefficient B.
+ This parameter can be a value between -32768 to +32767 */
+} IIR_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IIR_LL_Exported_Constants IIR LL Exported Constants
+ * @brief IIR LL Exported Constants
+ * @{
+ */
+
+/** @defgroup IIR_Flag_definition IIR Flag Definition
+ * @{
+ */
+#define IIR_FLAG_FDIF IIR_ISR_FDIF /*!< IIR Filter Done Interrupt Flag */
+/**
+ * @}
+ */
+
+/** @defgroup IIR_Interrupt_definition IIR Interrupt Definition
+ * @{
+ */
+#define IIR_IT_FDIE IIR_IER_IE /*!< IIR Filter Done Interrupt Enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IIR_LL_Exported_Macros IIR LL Exported Macros
+ * @brief IIR LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the specified IIR interrupt.
+ * @param __INSTANCE__ IIR peripheral
+ * @param __INTERRUPT__ specifies the IIR interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg IIR_IT_FDIE: Filiter Done Interrupt Enable
+ * @return None
+ */
+#define __LL_IIR_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->IER, __INTERRUPT__)
+
+
+/**
+ * @brief Disable the specified IIR interrupt.
+ * @param __INSTANCE__ IIR peripheral
+ * @param __INTERRUPT__ specifies the IIR interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg IIR_IT_FDIE: Filiter Done Interrupt Enable
+ * @return None
+ */
+#define __LL_IIR_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->IER, __INTERRUPT__)
+
+
+/**
+ * @brief Check whether the specified IIR interrupt source is enabled or not.
+ * @param __INSTANCE__ IIR peripheral
+ * @param __INTERRUPT__ specifies the IIR interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IIR_IT_FDIE: Filiter Done Interrupt Enable
+ * @return The state of __INTERRUPT__ (SET or RESET).
+ */
+#define __LL_IIR_IT_CHECK_SOURCE(__INSTANCE__, __INTERRUPT__) \
+ ((READ_BIT((__INSTANCE__)->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified IIR status or interrupt flag is set or not.
+ * @param __INSTANCE__ IIR peripheral
+ * @param __FLAG__ specifies the IIR flag to check.
+ * This parameter can be one of the following values:
+ * @arg IIR_FLAG_FDIF: Filiter Done Interrupt Flag
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_IIR_GET_FLAG(__INSTANCE__, __FLAG__) \
+ ((READ_BIT((__INSTANCE__)->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the specified IIR status or interrupt flag.
+ * @param __INSTANCE__ IIR peripheral
+ * @param __FLAG__ specifies the IIR flag to clear.
+ * This parameter can be one of the following values:
+ * @arg IIR_FLAG_FDIF: Filiter Done Interrupt Flag
+ * @return None
+ */
+#define __LL_IIR_CLEAR_FLAG(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->ISR, (__FLAG__))
+
+/**
+ * @brief Enable the IIR AutoReload feature.
+ * @param __INSTANCE__ IIR peripheral
+ * @return None
+ */
+#define __LL_IIR_AUTORELOAD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR1, IIR_CR1_AREN)
+
+/**
+ * @brief Enable the IIR peripheral.
+ * @param __INSTANCE__ IIR peripheral
+ * @return None
+ */
+#define __LL_IIR_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR0, IIR_CR0_IIREN)
+
+/**
+ * @brief Disable the IIR peripheral.
+ * @param __INSTANCE__ IIR peripheral
+ * @return None
+ */
+#define __LL_IIR_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR0, IIR_CR0_IIREN)
+
+/**
+ * @brief Start IIR filter
+ * @param __INSTANCE__ IIR peripheral
+ * @return None
+ */
+#define __LL_IIR_FILTER_START(__INSTANCE__) SET_BIT((__INSTANCE__)->CR1, IIR_CR1_START)
+
+
+/**
+ * @brief Reset the IIR internal data buffer.
+ * @param __INSTANCE__ IIR peripheral
+ * @return None
+ */
+#define __LL_IIR_FILTER_BUFFER_RESET(__INSTANCE__) SET_BIT((__INSTANCE__)->CR0, IIR_CR0_IBRST)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IIR_LL_Exported_functions
+ * @{
+ */
+
+/** @addtogroup IIR_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_IIR_Init(IIR_TypeDef *Instance, IIR_InitTypeDef *Init);
+LL_StatusETypeDef LL_IIR_DeInit(IIR_TypeDef *Instance);
+void LL_IIR_MspInit(IIR_TypeDef *Instance);
+void LL_IIR_MspDeInit(IIR_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup IIR_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_IIR_FilterConfig(IIR_TypeDef *Instance, IIR_ConfigTypeDef *Config);
+LL_StatusETypeDef LL_IIR_FilterConfig_Preload(IIR_TypeDef *Instance, IIR_ConfigTypeDef *Config);
+/**
+ * @}
+ */
+
+
+/** @addtogroup IIR_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_IIR_FilterStart(IIR_TypeDef *Instance, IIR_ATReloadETypeDef AutoReload);
+LL_StatusETypeDef LL_IIR_FilterStart_IT(IIR_TypeDef *Instance, IIR_ATReloadETypeDef AutoReload);
+LL_StatusETypeDef LL_IIR_FilterBufferReset(IIR_TypeDef *Instance);
+int16_t LL_IIR_FilterDataGet(IIR_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup IIR_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_IIR_IRQHandler(IIR_TypeDef *IIRx);
+void LL_IIR_FilterDoneCallBack(IIR_TypeDef *IIRx);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup IIR_LL_Private_Macros IIR LL Private Macros
+ * @brief IIR LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is IIR output data scale or not
+ * @param __SCALE__ scale to judge
+ * @retval 0 isn't IIR output data scale
+ * @retval 1 is IIR output data scale
+ */
+#define IS_IIR_OUTPUT_DATA_SCALE(__SCALE__) ((__SCALE__) <= 0x1FU)
+
+/**
+ * @brief Judge is IIR input data scale or not
+ * @param __SCALE__ scale to judge
+ * @retval 0 isn't IIR input data scale
+ * @retval 1 is IIR input data scale
+ */
+#define IS_IIR_INPUT_DATA_SCALE(__SCALE__) ((__SCALE__) <= 0x10U)
+
+/**
+ * @brief Judge is IIR feedback data scale or not
+ * @param __SCALE__ scale to judge
+ * @retval 0 isn't IIR feedback data scale
+ * @retval 1 is IIR feedback data scale
+ */
+#define IS_IIR_FEEDBACK_SCALE(__SCALE__) ((__SCALE__) <= 0x1FU)
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_IIR_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_iwdg.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_iwdg.h
new file mode 100644
index 0000000000..8b2c2d2385
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_iwdg.h
@@ -0,0 +1,321 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_iwdg.h
+ * @author MCD Application Team
+ * @brief Header file of IWDG LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_IWDG_H_
+#define _TAE32F53XX_LL_IWDG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Types IWDG LL Exported Types
+ * @brief IWDG LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG Prescaler enumeration
+ */
+typedef enum {
+ IWDG_PRESCALER_4 = IWDG_PSCR_PSC_0, /*!< IWDG prescaler set to 4 */
+ IWDG_PRESCALER_8 = IWDG_PSCR_PSC_1, /*!< IWDG prescaler set to 8 */
+ IWDG_PRESCALER_16 = IWDG_PSCR_PSC_2, /*!< IWDG prescaler set to 16 */
+ IWDG_PRESCALER_32 = IWDG_PSCR_PSC_3, /*!< IWDG prescaler set to 32 */
+ IWDG_PRESCALER_64 = IWDG_PSCR_PSC_4, /*!< IWDG prescaler set to 64 */
+ IWDG_PRESCALER_128 = IWDG_PSCR_PSC_5, /*!< IWDG prescaler set to 128 */
+ IWDG_PRESCALER_256 = IWDG_PSCR_PSC_6, /*!< IWDG prescaler set to 256 */
+ IWDG_PRESCALER_512 = IWDG_PSCR_PSC_7, /*!< IWDG prescaler set to 512 */
+} IWDG_PreScalerETypeDef;
+
+
+/**
+ @brief IWDG Mode enumeration
+ */
+typedef enum {
+ IWDG_MODE_RESET = IWDG_CR_MODE_RESET, /*!< IWDG Reset after timeout */
+ IWDG_MODE_INTERRUPT = IWDG_CR_MODE_INTERRUPT, /*!< IWDG Trigger a interrupt after timeout */
+} IWDG_ModeETypeDef;
+
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct __IWDG_InitTypeDef {
+ IWDG_PreScalerETypeDef Prescaler; /*!< Select the prescaler of the IWDG. */
+ uint32_t Reload_val; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+ IWDG_ModeETypeDef Mode; /*!< Specifies the IWDG bahavior after timeout.*/
+} IWDG_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG LL Exported Constants
+ * @brief IWDG LL Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Interrupt_definition IWDG interrupt Definition
+ * @{
+ */
+#define IWDG_IT_TOIE IWDG_CR_TOIE /*!< IWDG Timeout Interrupte Enable */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag_definition IWDG Flag Definition
+ * @{
+ */
+#define IWDG_FLAG_PSCUPD IWDG_SR_PSCUPD /*!< IWDG Prescaler Update flag */
+#define IWDG_FLAG_RLVUPD IWDG_SR_RLVUPD /*!< IWDG Reload Value Update flag */
+#define IWDG_FLAG_TOIF IWDG_SR_TOIF /*!< IWDG Timeout Interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Key_definition IWDG Key Definition
+ * @{
+ */
+#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_DISABLE 0x0000DDDDU /*!< IWDG Peripheral Disable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005003U /*!< IWDG Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG Write Access Disable */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG LL Exported Macros
+ * @brief IWDG LL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief Enable write access to IWDG_PSCR, IWDG_RLR and IWDG_CR registers.
+ * @param __INSTANCE__ IWDG peripheral
+ * @return None
+ */
+#define __LL_IWDG_ENABLE_WRITE_ACCESS(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disable write access to IWDG_PSCR, IWDG_RLR and IWDG_CR registers.
+ * @param __INSTANCE__ IWDG peripheral
+ * @return None
+ */
+#define __LL_IWDG_DISABLE_WRITE_ACCESS(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+
+/**
+ * @brief Enable the IWDG peripheral.
+ * @param __INSTANCE__ IWDG peripheral
+ * @return None
+ */
+#define __LL_IWDG_START(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief Disable the IWDG peripheral.
+ * @param __INSTANCE__ IWDG peripheral
+ * @return None
+ */
+#define __LL_IWDG_STOP(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWDG_KEY_DISABLE)
+
+/** @brief Enable the specified IWDG interrupt.
+ * @note __LL_IWDG_ENABLE_WRITE_ACCESS() must be called to enable write access before enable
+ * the IWDG interrupt.
+ * @param __INSTANCE__ IWDG peripheral
+ * @param __INTERRUPT__ specifies the IWDG interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg IWDG_IT_TOIE: Timeout interrupt flag
+ * @retrun None
+ */
+#define __LL_IWDG_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CR, (__INTERRUPT__))
+
+/** @brief Disable the specified TIM interrupt.
+ * @note __LL_IWDG_ENABLE_WRITE_ACCESS() must be called to enable write access before disable
+ * the IWDG interrupt.
+ * @param __INSTANCE__ IWDG peripheral
+ * @param __INTERRUPT__ specifies the IWDG interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg IWDG_IT_TOIE: Timeout interrupt flag
+ * @retval None
+ */
+#define __LL_IWDG_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CR, (__INTERRUPT__))
+
+
+/** @brief Check whether the specified IWDG status or interrupt flag is set or not.
+ * @param __INSTANCE__ IWDG peripheral
+ * @param __FLAG__ specifies the IWDG flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PSCUPD: Prescaler value update flag
+ * @arg IWDG_FLAG_RLVUPD: Reload value update flag
+ * @arg IWDG_FLAG_TOIF: Timeout interrupt flag
+ * @return The new state of __FLAG__ (SET or RESET).
+ */
+#define __LL_IWDG_GET_FLAG(__INSTANCE__, __FLAG__) \
+ ((READ_BIT((__INSTANCE__)->SR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the specified IWDG status or interrupt flag.
+ * @param __INSTANCE__ IWDG peripheral
+ * @param __FLAG__ specifies the IWDG flag to clear.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_TOIF: Timeout interrupt flag
+ * @return None
+ */
+#define __LL_IWDG_CLEAR_FLAG(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->SR, (__FLAG__))
+
+/**
+ * @brief Check whether the specified IWDG interrupt source is enabled or not.
+ * @param __INSTANCE__ IWDG peripheral
+ * @param __INTERRUPT__ specifies the IWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_IT_TOIE: Timeout interrupt
+ * @return The state of __INTERRUPT__ (SET or RESET).
+ */
+#define __LL_IWDG_IT_CHECK_SOURCE(__INSTANCE__, __INTERRUPT__) \
+ ((READ_BIT((__INSTANCE__)->CR, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Reload IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR & IWDG_RLR registers disabled).
+ * @note Flag RLVUPD and PSCUPD must be 0 before refreshing IWDG counter.
+ * @param __INSTANCE__ IWDG peripheral
+ * @return None
+ */
+#define __LL_IWDG_RELOAD_COUNTER(__INSTANCE__) WRITE_REG((__INSTANCE__)->KEYR, IWDG_KEY_RELOAD)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IWDG_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_IWDG_Init(IWDG_TypeDef *Instance, IWDG_InitTypeDef *Init);
+LL_StatusETypeDef LL_IWDG_DeInit(IWDG_TypeDef *Instance);
+void LL_IWDG_MspInit(IWDG_TypeDef *Instance);
+void LL_IWDG_MspDeInit(IWDG_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup IWDG_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_IWDG_Refresh(IWDG_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup IWDG_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_IWDG_IRQHandler(IWDG_TypeDef *Instance);
+void LL_IWDG_TimeOutCallBack(IWDG_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Macros IWDG LL Private Macros
+ * @brief IWDG LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__ IWDG prescaler value
+ * @return None
+ */
+
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__ IWDG reload value
+ * @return None
+ */
+#define IS_IWDG_RELOAD_Val(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RLV)
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_IWDG_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_lvdctrl.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_lvdctrl.h
new file mode 100644
index 0000000000..03c2f45a64
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_lvdctrl.h
@@ -0,0 +1,464 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_lvdctrl.h
+ * @author MCD Application Team
+ * @brief Head file for LVDCTRL LL Module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_LVDCTRL_H_
+#define _TAE32F53XX_LL_LVDCTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup LVDCTRL_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LVDCTRL_LL_Exported_Macros LVDCTRL LL Exported Macros
+ * @brief LVDCTRL LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Judge VDD Over Current or not
+ * @param __LVD__ Specifies LVD peripheral
+ * @retval 0 VDD isn't Over Current
+ * @retval 1 VDD is Over Current
+ */
+#define __LL_LVDCTRL_IsVDDOverCur(__LVD__) (READ_BIT((__LVD__)->LACR, LVDCTRL_VDDOC_ST_Msk) >> LVDCTRL_VDDOC_ST_Pos)
+
+/**
+ * @brief Judge VDD Low Voltage or not
+ * @param __LVD__ Specifies LVD peripheral
+ * @retval 0 VDD isn't Low Voltage
+ * @retval 1 VDD is Low Voltage
+ */
+#define __LL_LVDCTRL_IsVDDLowVol(__LVD__) (READ_BIT((__LVD__)->LACR, LVDCTRL_VDDLV_ST_Msk) >> LVDCTRL_VDDLV_ST_Pos)
+
+/**
+ * @brief Judge VCC Low Voltage or not
+ * @param __LVD__ Specifies LVD peripheral
+ * @retval 0 VCC isn't Low Voltage
+ * @retval 1 VCC is Low Voltage
+ */
+#define __LL_LVDCTRL_IsVCCLowVol(__LVD__) (READ_BIT((__LVD__)->LACR, LVDCTRL_VCCLV_ST_Msk) >> LVDCTRL_VCCLV_ST_Pos)
+
+/**
+ * @brief Judge AVCC Low Voltage or not
+ * @param __LVD__ Specifies LVD peripheral
+ * @retval 0 AVCC isn't Low Voltage
+ * @retval 1 AVCC is Low Voltage
+ */
+#define __LL_LVDCTRL_IsAVCCLowVol(__LVD__) (READ_BIT((__LVD__)->LACR, LVDCTRL_AVCCLV_ST_Msk) >> LVDCTRL_AVCCLV_ST_Pos)
+
+/**
+ * @brief VDD Over Current Bypass Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurByp_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_VDDOC_BYP_EN_Msk)
+
+/**
+ * @brief VDD Over Current Bypass Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurByp_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_VDDOC_BYP_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Bypass Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolByp_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_VDDLV_BYP_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Bypass Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolByp_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_VDDLV_BYP_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Bypass Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolByp_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_VCCLV_BYP_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Bypass Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolByp_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_VCCLV_BYP_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Bypass Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolByp_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_AVCCLV_BYP_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Bypass Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolByp_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_AVCCLV_BYP_EN_Msk)
+
+/**
+ * @brief Analog Input Signal Debounce Limit Set
+ * @param __LVD__ Specifies LVD peripheral
+ * @param limit Analog Input Signal Debounce Limit
+ * @return None
+ */
+#define __LL_LVDCTRL_AnalogInDbcLimit_Set(__LVD__, limit) \
+ MODIFY_REG((__LVD__)->LACR, LVDCTRL_ANAIN_DBC_LIMIT_Msk, ((limit & 0xffUL) << LVDCTRL_ANAIN_DBC_LIMIT_Pos))
+
+/**
+ * @brief VCC Low Voltage Threshold Set
+ * @param __LVD__ Specifies LVD peripheral
+ * @param thres VCC Low Voltage Threshold
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolThres_Set(__LVD__, thres) MODIFY_REG((__LVD__)->LACR, LVDCTRL_VCCLV_SET_Msk, thres)
+
+/**
+ * @brief AVCC Low Voltage Threshold Set
+ * @param __LVD__ Specifies LVD peripheral
+ * @param thres AVCC Low Voltage Threshold
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolThres_Set(__LVD__, thres) MODIFY_REG((__LVD__)->LACR, LVDCTRL_AVCCLV_SET_Msk, thres)
+
+/**
+ * @brief VDD Over Current Threshold Set
+ * @param __LVD__ Specifies LVD peripheral
+ * @param thres VDD Over Current Threshold
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurThres_Set(__LVD__, thres) MODIFY_REG((__LVD__)->LACR, LVDCTRL_VDDOC_SET_Msk, thres)
+
+/**
+ * @brief VDD Low Voltage Threshold Set
+ * @param __LVD__ Specifies LVD peripheral
+ * @param thres VDD Low Voltage Threshold
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolThres_Set(__LVD__, thres) MODIFY_REG((__LVD__)->LACR, LVDCTRL_VDDLV_SET_Msk, thres)
+
+/**
+ * @brief VCC Low Voltage Detect Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolDet_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_VCCLV_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Detect Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolDet_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_VCCLV_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Detect Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolDet_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_AVCCLV_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Detect Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolDet_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_AVCCLV_EN_Msk)
+
+/**
+ * @brief VDD Over Current Detect Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurDet_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_VDDOC_EN_Msk)
+
+/**
+ * @brief VDD Over Current Detect Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurDet_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_VDDOC_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Detect Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolDet_En(__LVD__) SET_BIT((__LVD__)->LACR, LVDCTRL_VDDLV_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Detect Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolDet_Dis(__LVD__) CLEAR_BIT((__LVD__)->LACR, LVDCTRL_VDDLV_EN_Msk)
+
+
+/**
+ * @brief VDD Over Current Braking Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurBrk_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VDDOC_BRK_EN_Msk)
+
+/**
+ * @brief VDD Over Current Braking Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurBrk_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VDDOC_BRK_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Braking Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolBrk_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VDDLV_BRK_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Braking Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolBrk_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VDDLV_BRK_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Braking Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolBrk_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VCCLV_BRK_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Braking Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolBrk_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VCCLV_BRK_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Braking Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolBrk_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_AVCCLV_BRK_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Braking Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolBrk_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_AVCCLV_BRK_EN_Msk)
+
+/**
+ * @brief VDD Over Current Interrupt Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurInt_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VDDOC_INT_EN_Msk)
+
+/**
+ * @brief VDD Over Current Interrupt Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurInt_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VDDOC_INT_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Interrupt Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolInt_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VDDLV_INT_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Interrupt Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolInt_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VDDLV_INT_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Interrupt Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolInt_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VCCLV_INT_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Interrupt Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolInt_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VCCLV_INT_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Interrupt Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolInt_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_AVCCLV_INT_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Interrupt Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolInt_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_AVCCLV_INT_EN_Msk)
+
+/**
+ * @brief VDD Over Current Reset Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurRst_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VDDOC_RST_EN_Msk)
+
+/**
+ * @brief VDD Over Current Reset Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_OverCurRst_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VDDOC_RST_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Reset Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolRst_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VDDLV_RST_EN_Msk)
+
+/**
+ * @brief VDD Low Voltage Reset Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VDD_LowVolRst_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VDDLV_RST_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Reset Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolRst_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_VCCLV_RST_EN_Msk)
+
+/**
+ * @brief VCC Low Voltage Reset Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_VCC_LowVolRst_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_VCCLV_RST_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Reset Enable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolRst_En(__LVD__) SET_BIT((__LVD__)->LCR, LVDCTRL_AVCCLV_RST_EN_Msk)
+
+/**
+ * @brief AVCC Low Voltage Reset Disable
+ * @param __LVD__ Specifies LVD peripheral
+ * @return None
+ */
+#define __LL_LVDCTRL_AVCC_LowVolRst_Dis(__LVD__) CLEAR_BIT((__LVD__)->LCR, LVDCTRL_AVCCLV_RST_EN_Msk)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LVDCTRL_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup LVDCTRL_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_LVD_Init(LVD_TypeDef *Instance);
+LL_StatusETypeDef LL_LVD_DeInit(LVD_TypeDef *Instance);
+void LL_LVD_MspInit(LVD_TypeDef *Instance);
+void LL_LVD_MspDeInit(LVD_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup LVDCTRL_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_LVD_CtrlIRQHandler(LVD_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_LVDCTRL_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_sysctrl.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_sysctrl.h
new file mode 100644
index 0000000000..adb916973e
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_sysctrl.h
@@ -0,0 +1,3025 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_sysctrl.h
+ * @author MCD Application Team
+ * @brief Header file for SYSCTRL LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_SYSCTRL_H_
+#define _TAE32F53XX_LL_SYSCTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup SYSCTRL_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SYSCTRL_LL_Exported_Macros SYSCTRL LL Exported Macros
+ * @brief SYSCTRL LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief PLL0 Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_EN_Msk)
+
+/**
+ * @brief PLL0 Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_EN_Msk)
+
+/**
+ * @brief Judge PLL0 has Locked or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 PLL0 hasn't Locked
+ * @retval 1 PLL0 has Locked
+ */
+#define __LL_SYSCTRL_PLL0_IsLocked(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_LOCKED_Msk) >> SYSCTRL_PLL0_LOCKED_Pos)
+
+/**
+ * @brief PLL0 LPF Select 8M
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_LPF_8M(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_LPF_Msk)
+
+/**
+ * @brief PLL0 LPF Select 26M
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_LPF_26M(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_LPF_Msk)
+
+/**
+ * @brief PLL0 Band Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param band PLL0 Band
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_Band_Set(__SYSCTRL__, band) \
+ MODIFY_REG((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_BAND_Msk, band)
+
+/**
+ * @brief PLL0 GVCO Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param vco PLL0 GVCO
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_GVCO_Set(__SYSCTRL__, vco) \
+ MODIFY_REG((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_GVCO_Msk, vco)
+
+/**
+ * @brief PLL0 DIV Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div PLL0 Div
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_DIV_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_DIV_Msk, (((div-1) & 0xfUL) << SYSCTRL_PLL0_DIV_Pos))
+
+/**
+ * @brief PLL0 Pre Div Set to 2
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_PreDiv_2(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_PREDIV_Msk)
+
+/**
+ * @brief PLL0 Pre Div Set to 1
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_PreDiv_1(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_PREDIV_Msk)
+
+/**
+ * @brief PLL0 Ref CLK Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param ref_clk PLL0 Ref CLK
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL0_RefClk_Set(__SYSCTRL__, ref_clk) \
+ MODIFY_REG((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_REFCLK_Msk, ref_clk)
+
+
+/**
+ * @brief PLL1 Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_EN_Msk)
+
+/**
+ * @brief PLL1 Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_EN_Msk)
+
+/**
+ * @brief Judge PLL1 has Locked or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 PLL1 hasn't Locked
+ * @retval 1 PLL1 has Locked
+ */
+#define __LL_SYSCTRL_PLL1_IsLocked(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_LOCKED_Msk) >> SYSCTRL_PLL1_LOCKED_Pos)
+
+/**
+ * @brief PLL1 LPF Select 8M
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_LPF_8M(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_LPF_Msk)
+
+/**
+ * @brief PLL1 LPF Select 26M
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_LPF_26M(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_LPF_Msk)
+
+/**
+ * @brief PLL1 Band Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param band PLL1 Band
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_Band_Set(__SYSCTRL__, band) \
+ MODIFY_REG((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_BAND_Msk, band)
+
+/**
+ * @brief PLL1 GVCO Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param vco PLL1 GVCO
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_GVCO_Set(__SYSCTRL__, vco) \
+ MODIFY_REG((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_GVCO_Msk, vco)
+
+/**
+ * @brief PLL1 DIV Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div PLL1 Div
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_DIV_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_DIV_Msk, (((div-1) & 0xfUL) << SYSCTRL_PLL1_DIV_Pos))
+
+/**
+ * @brief PLL1 Pre Div Set to 2
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_PreDiv_2(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_PREDIV_Msk)
+
+/**
+ * @brief PLL1 Pre Div Set to None
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_PreDiv_1(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_PREDIV_Msk)
+
+/**
+ * @brief PLL1 Ref CLK Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param ref_clk PLL1 Ref CLK
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL1_RefClk_Set(__SYSCTRL__, ref_clk) \
+ MODIFY_REG((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_REFCLK_Msk, ref_clk)
+
+
+/**
+ * @brief PLL2 Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_EN_Msk)
+
+/**
+ * @brief PLL2 Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_EN_Msk)
+
+/**
+ * @brief Judge PLL2 has Locked or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 PLL2 hasn't Locked
+ * @retval 1 PLL2 has Locked
+ */
+#define __LL_SYSCTRL_PLL2_IsLocked(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_LOCKED_Msk) >> SYSCTRL_PLL2_LOCKED_Pos)
+
+/**
+ * @brief PLL2 LPF Select 8M
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_LPF_8M(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_LPF_Msk)
+
+/**
+ * @brief PLL2 LPF Select 26M
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_LPF_26M(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_LPF_Msk)
+
+/**
+ * @brief PLL2 Band Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param band PLL2 Band
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_Band_Set(__SYSCTRL__, band) \
+ MODIFY_REG((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_BAND_Msk, band)
+
+/**
+ * @brief PLL2 GVCO Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param vco PLL2 GVCO
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_GVCO_Set(__SYSCTRL__, vco) \
+ MODIFY_REG((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_GVCO_Msk, vco)
+
+/**
+ * @brief PLL2 DIV Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div PLL2 Div
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_DIV_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_DIV_Msk, (((div-1) & 0xfUL) << SYSCTRL_PLL2_DIV_Pos))
+
+/**
+ * @brief PLL2 Pre Div Set to 2
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_PreDiv_2(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_PREDIV_Msk)
+
+/**
+ * @brief PLL2 Pre Div Set to None
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_PreDiv_1(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_PREDIV_Msk)
+
+/**
+ * @brief PLL2 Ref CLK Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param ref_clk PLL2 Ref CLK
+ * @return None
+ */
+#define __LL_SYSCTRL_PLL2_RefClk_Set(__SYSCTRL__, ref_clk) \
+ MODIFY_REG((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_REFCLK_Msk, ref_clk)
+
+
+/**
+ * @brief SYSCLK Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div SYSCLK Div
+ * @return None
+ */
+#define __LL_SYSCTRL_SysClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->SCLKCR, SYSCTRL_SYSCLK_DIV_Msk, (((div-1) & 0xffUL) << SYSCTRL_SYSCLK_DIV_Pos))
+
+/**
+ * @brief SYSCLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src SYSCLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_SysClkSrc_Set(__SYSCTRL__, src) \
+ MODIFY_REG((__SYSCTRL__)->SCLKCR, SYSCTRL_SYSCLK_SRC_Msk, src)
+
+
+/**
+ * @brief APB1 CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB1Clk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_APB1CLK_EN_Msk)
+
+/**
+ * @brief APB1 CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB1Clk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_APB1CLK_EN_Msk)
+
+/**
+ * @brief APB0 CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB0Clk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_APB0CLK_EN_Msk)
+
+/**
+ * @brief APB0 CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB0Clk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_APB0CLK_EN_Msk)
+
+/**
+ * @brief AHB CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AHBClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_AHBCLK_EN_Msk)
+
+/**
+ * @brief AHB CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AHBClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_AHBCLK_EN_Msk)
+
+/**
+ * @brief APB1 CLK Div SET
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div APB1 Div
+ * @return None
+ */
+#define __LL_SYSCTRL_APB1ClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->BCLKCR, SYSCTRL_APB1CLK_DIV_Msk, (((div-1) & 0xffUL) << SYSCTRL_APB1CLK_DIV_Pos))
+
+/**
+ * @brief APB1 CLK Div GET
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return APB1 Div
+ */
+#define __LL_SYSCTRL_APB1ClkDiv_Get(__SYSCTRL__) \
+ ((READ_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_APB1CLK_DIV_Msk) >> SYSCTRL_APB1CLK_DIV_Pos) + 1)
+
+/**
+ * @brief APB0 CLK Div SET
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div APB0 Div
+ * @return None
+ */
+#define __LL_SYSCTRL_APB0ClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->BCLKCR, SYSCTRL_APB0CLK_DIV_Msk, (((div-1) & 0xffUL) << SYSCTRL_APB0CLK_DIV_Pos))
+
+/**
+ * @brief APB0 CLK Div GET
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return APB0 Div
+ */
+#define __LL_SYSCTRL_APB0ClkDiv_Get(__SYSCTRL__) \
+ ((READ_BIT((__SYSCTRL__)->BCLKCR, SYSCTRL_APB0CLK_DIV_Msk) >> SYSCTRL_APB0CLK_DIV_Pos) + 1)
+
+
+/**
+ * @brief GPIOD Debounce CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src GPIOD Debounce CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODDbcSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_GPIOD_DBCCLK_SRC_Msk, src)
+
+/**
+ * @brief GPIOC Debounce CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src GPIOC Debounce CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCDbcSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_GPIOC_DBCCLK_SRC_Msk, src)
+
+/**
+ * @brief GPIOB Debounce CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src GPIOB Debounce CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBDbcSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_GPIOB_DBCCLK_SRC_Msk, src)
+
+/**
+ * @brief GPIOA Debounce CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src GPIOA Debounce CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOADbcSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_GPIOA_DBCCLK_SRC_Msk, src)
+
+/**
+ * @brief DFLASH Memory CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src DFLASH Memory CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHMemClkSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_DFLASH_MEMCLK_SRC_Msk, src)
+
+/**
+ * @brief EFLASH Memory CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src EFLASH Memory CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHMemClkSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_EFLASH_MEMCLK_SRC_Msk, src)
+
+/**
+ * @brief ADC Function CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src ADC Function CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCFunClkSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_ADC_FUNCLK_SRC_Msk, src)
+
+/**
+ * @brief HRPWM Function CLK Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src HRPWM Function CLK Source
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMFunClkSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->FSRCCR, SYSCTRL_HRPWM_FUNCLK_SRC_Msk, src)
+
+
+/**
+ * @brief DFLASH Memory Clk Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div DFLASH Memory Clk Div
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHMemClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD0CR, SYSCTRL_DFLASH_MEMCLK_DIV_Msk, (((div-1) & 0xfUL) << SYSCTRL_DFLASH_MEMCLK_DIV_Pos))
+
+/**
+ * @brief EFLASH Memory Clk Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div EFLASH Memory Clk Div
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHMemClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD0CR, SYSCTRL_EFLASH_MEMCLK_DIV_Msk, (((div-1) & 0xfUL) << SYSCTRL_EFLASH_MEMCLK_DIV_Pos))
+
+/**
+ * @brief ADC Function Clk Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div ADC Function Clk Div
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCFunClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD0CR, SYSCTRL_ADC_FUNCLK_DIV_Msk, (((div-1) & 0x3UL) << SYSCTRL_ADC_FUNCLK_DIV_Pos))
+
+/**
+ * @brief HRPWM Function Clk Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div HRPWM Function Clk Div
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMFunClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD0CR, SYSCTRL_HRPWM_FUNCLK_DIV_Msk, (((div-1) & 0x3UL) << SYSCTRL_HRPWM_FUNCLK_DIV_Pos))
+
+
+/**
+ * @brief GPIOD Debounce CLK Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div GPIOD Debounce CLK Div
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODDbcClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD1CR, SYSCTRL_GPIOD_DBCCLK_DIV_Msk, (((div-1) & 0xffUL) << SYSCTRL_GPIOD_DBCCLK_DIV_Pos))
+/**
+ * @brief GPIOC Debounce CLK Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div GPIOC Debounce CLK Div
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCDbcClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD1CR, SYSCTRL_GPIOC_DBCCLK_DIV_Msk, (((div-1) & 0xffUL) << SYSCTRL_GPIOC_DBCCLK_DIV_Pos))
+
+/**
+ * @brief GPIOB Debounce CLK Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div GPIOB Debounce CLK Div
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBDbcClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD1CR, SYSCTRL_GPIOB_DBCCLK_DIV_Msk, (((div-1) & 0xffUL) << SYSCTRL_GPIOB_DBCCLK_DIV_Pos))
+
+/**
+ * @brief GPIOA Debounce CLK Div Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param div GPIOA Debounce CLK Div
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOADbcClkDiv_Set(__SYSCTRL__, div) \
+ MODIFY_REG((__SYSCTRL__)->FCD1CR, SYSCTRL_GPIOA_DBCCLK_DIV_Msk, (((div-1) & 0xffUL) << SYSCTRL_GPIOA_DBCCLK_DIV_Pos))
+
+
+/**
+ * @brief LSTIMER Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_LSTIMERBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_LSTIMER_BUSCLK_EN_Msk)
+
+/**
+ * @brief LSTIMER Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_LSTIMERBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_LSTIMER_BUSCLK_EN_Msk)
+
+/**
+ * @brief UART1 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART1BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_UART1_BUSCLK_EN_Msk)
+
+/**
+ * @brief UART1 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART1BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_UART1_BUSCLK_EN_Msk)
+
+/**
+ * @brief UART0 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART0BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_UART0_BUSCLK_EN_Msk)
+
+/**
+ * @brief UART0 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART0BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_UART0_BUSCLK_EN_Msk)
+
+/**
+ * @brief I2C1 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C1BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_I2C1_BUSCLK_EN_Msk)
+
+/**
+ * @brief I2C1 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C1BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_I2C1_BUSCLK_EN_Msk)
+
+/**
+ * @brief I2C0 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C0BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_I2C0_BUSCLK_EN_Msk)
+
+/**
+ * @brief I2C0 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C0BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0CCR, SYSCTRL_I2C0_BUSCLK_EN_Msk)
+
+
+/**
+ * @brief ECU Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ECUBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_ECU_BUSCLK_EN_Msk)
+
+/**
+ * @brief ECU Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ECUBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_ECU_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR4 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR4BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR4_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR4 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR4BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR4_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR3 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR3BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR3_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR3 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR3BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR3_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR2 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR2BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR2_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR2 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR2BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR2_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR1 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR1BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR1_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR1 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR1BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR1_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR0 Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR0BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR0_BUSCLK_EN_Msk)
+
+/**
+ * @brief IIR0 Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR0BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_IIR0_BUSCLK_EN_Msk)
+
+/**
+ * @brief DALI Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DALIBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_DALI_BUSCLK_EN_Msk)
+
+/**
+ * @brief DALI Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DALIBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1CCR, SYSCTRL_DALI_BUSCLK_EN_Msk)
+
+
+
+/**
+ * @brief RAM2 Bus Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RAM2BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_RAM2_BUSCLK_EN_Msk)
+
+/**
+ * @brief RAM2 Bus Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RAM2BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_RAM2_BUSCLK_EN_Msk)
+
+/**
+ * @brief RAM1 Bus Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RAM1BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_RAM1_BUSCLK_EN_Msk)
+
+/**
+ * @brief RAM1 Bus Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RAM1BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_RAM1_BUSCLK_EN_Msk)
+
+/**
+ * @brief RAM0 Bus Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RAM0BusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_RAM0_BUSCLK_EN_Msk)
+
+/**
+ * @brief RAM0 Bus Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RAM0BusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_RAM0_BUSCLK_EN_Msk)
+
+/**
+ * @brief USB Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_USBBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_USB_BUSCLK_EN_Msk)
+
+/**
+ * @brief USB Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_USBBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_USB_BUSCLK_EN_Msk)
+
+/**
+ * @brief DFLASH Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_DFLASH_BUSCLK_EN_Msk)
+
+/**
+ * @brief DFLASH Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_DFLASH_BUSCLK_EN_Msk)
+
+/**
+ * @brief EFLASH Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_EFLASH_BUSCLK_EN_Msk)
+
+/**
+ * @brief EFLASH Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_EFLASH_BUSCLK_EN_Msk)
+
+/**
+ * @brief HRPWM Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_HRPWM_BUSCLK_EN_Msk)
+
+/**
+ * @brief HRPWM Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_HRPWM_BUSCLK_EN_Msk)
+
+/**
+ * @brief ADC Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_ADC_BUSCLK_EN_Msk)
+
+/**
+ * @brief ADC Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_ADC_BUSCLK_EN_Msk)
+
+/**
+ * @brief DAC Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DACBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_DAC_BUSCLK_EN_Msk)
+
+/**
+ * @brief DAC Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DACBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_DAC_BUSCLK_EN_Msk)
+
+/**
+ * @brief CMP Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CMPBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_CMP_BUSCLK_EN_Msk)
+
+/**
+ * @brief CMP Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CMPBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_CMP_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOD Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOD_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOD Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOD_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOC Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOC_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOC Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOC_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOB Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOB_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOB Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOB_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOA Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOABusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOA_BUSCLK_EN_Msk)
+
+/**
+ * @brief GPIOA Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOABusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_GPIOA_BUSCLK_EN_Msk)
+
+/**
+ * @brief HSTIMER Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HSTIMERBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_HSTIMER_BUSCLK_EN_Msk)
+
+/**
+ * @brief HSTIMER Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HSTIMERBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_HSTIMER_BUSCLK_EN_Msk)
+
+/**
+ * @brief CAN Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CANBusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_CAN_BUSCLK_EN_Msk)
+
+/**
+ * @brief CAN Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CANBusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_CAN_BUSCLK_EN_Msk)
+
+/**
+ * @brief DMA Bus CLK Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DMABusClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_DMA_BUSCLK_EN_Msk)
+
+/**
+ * @brief DMA Bus CLK Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DMABusClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBCCR, SYSCTRL_DMA_BUSCLK_EN_Msk)
+
+
+/**
+ * @brief HRPWM Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMFunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_HRPWM_FUNCLK_EN_Msk)
+
+/**
+ * @brief HRPWM Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMFunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_HRPWM_FUNCLK_EN_Msk)
+
+/**
+ * @brief ADC Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCFunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_ADC_FUNCLK_EN_Msk)
+
+/**
+ * @brief ADC Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCFunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_ADC_FUNCLK_EN_Msk)
+
+/**
+ * @brief CAN Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CANFunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_CAN_FUNCLK_EN_Msk)
+
+/**
+ * @brief CAN Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CANFunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_CAN_FUNCLK_EN_Msk)
+
+/**
+ * @brief ECU Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ECUFunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_ECU_FUNCLK_EN_Msk)
+
+/**
+ * @brief ECU Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ECUFunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_ECU_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR4 Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR4FunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR4_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR4 Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR4FunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR4_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR3 Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR3FunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR3_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR3 Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR3FunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR3_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR2 Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR2FunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR2_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR2 Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR2FunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR2_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR1 Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR1FunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR1_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR1 Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR1FunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR1_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR0 Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR0FunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR0_FUNCLK_EN_Msk)
+
+/**
+ * @brief IIR0 Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR0FunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_IIR0_FUNCLK_EN_Msk)
+
+/**
+ * @brief USB Function Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_USBFunClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_USB_FUNCLK_EN_Msk)
+
+/**
+ * @brief USB Function Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_USBFunClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_USB_FUNCLK_EN_Msk)
+
+/**
+ * @brief DFLASH Memory Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHMemClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_DFLASH_MEMCLK_EN_Msk)
+
+/**
+ * @brief DFLASH Memory Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHMemClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_DFLASH_MEMCLK_EN_Msk)
+
+/**
+ * @brief EFLASH Memory Clk Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHMemClk_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_EFLASH_MEMCLK_EN_Msk)
+
+/**
+ * @brief EFLASH Memory Clk Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHMemClk_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->FUNCCR, SYSCTRL_EFLASH_MEMCLK_EN_Msk)
+
+
+/**
+ * @brief GPIOD Debounce Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODDbcSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOD_DBC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOD Debounce Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODDbcSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOD_DBC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOC Debounce Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCDbcSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOC_DBC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOC Debounce Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCDbcSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOC_DBC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOB Debounce Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBDbcSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOB_DBC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOB Debounce Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBDbcSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOB_DBC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOA Debounce Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOADbcSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOA_DBC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOA Debounce Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOADbcSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_GPIOA_DBC_SOFTRST_Msk)
+
+/**
+ * @brief APB1 Bus Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB1BusSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_APB1BUS_SOFTRST_Msk)
+
+/**
+ * @brief APB1 Bus Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB1BusSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_APB1BUS_SOFTRST_Msk)
+
+/**
+ * @brief APB0 Bus Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB0BusSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_APB0BUS_SOFTRST_Msk)
+
+/**
+ * @brief APB0 Bus Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB0BusSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_APB0BUS_SOFTRST_Msk)
+
+/**
+ * @brief AHB Bus Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AHBBusSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_AHBBUS_SOFTRST_Msk)
+
+/**
+ * @brief AHB Bus Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AHBBusSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSRCR, SYSCTRL_AHBBUS_SOFTRST_Msk)
+
+/**
+ * @brief System Soft Reset all Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_SysSoftRstAll_Assert(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->SYSRCR, 0x0)
+
+/**
+ * @brief System Soft Reset all Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_SysSoftRstAll_Release(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->SYSRCR, 0xffffffffUL)
+
+
+/**
+ * @brief LSTIMER Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_LSTIMERSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_LSTIMER_SOFTRST_Msk)
+
+/**
+ * @brief LSTIMER Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_LSTIMERSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_LSTIMER_SOFTRST_Msk)
+
+/**
+ * @brief UART1 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART1SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_UART1_SOFTRST_Msk)
+
+/**
+ * @brief UART1 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART1SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_UART1_SOFTRST_Msk)
+
+/**
+ * @brief UART0 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART0SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_UART0_SOFTRST_Msk)
+
+/**
+ * @brief UART0 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_UART0SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_UART0_SOFTRST_Msk)
+
+/**
+ * @brief I2C1 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C1SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_I2C1_SOFTRST_Msk)
+
+/**
+ * @brief I2C1 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C1SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_I2C1_SOFTRST_Msk)
+
+/**
+ * @brief I2C0 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C0SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_I2C0_SOFTRST_Msk)
+
+/**
+ * @brief I2C0 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C0SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB0RCR, SYSCTRL_I2C0_SOFTRST_Msk)
+
+/**
+ * @brief APB0 Soft Reset all Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB0SoftRstAll_Assert(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->APB0RCR, 0x0)
+
+/**
+ * @brief APB0 Soft Reset all Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB0SoftRstAll_Release(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->APB0RCR, 0xffffffffUL)
+
+
+/**
+ * @brief ECU Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ECUSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_ECU_SOFTRST_Msk)
+
+/**
+ * @brief ECU Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ECUSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_ECU_SOFTRST_Msk)
+
+/**
+ * @brief IIR4 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR4SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR4_SOFTRST_Msk)
+
+/**
+ * @brief IIR4 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR4SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR4_SOFTRST_Msk)
+
+/**
+ * @brief IIR3 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR3SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR3_SOFTRST_Msk)
+
+/**
+ * @brief IIR3 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR3SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR3_SOFTRST_Msk)
+
+/**
+ * @brief IIR2 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR2SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR2_SOFTRST_Msk)
+
+/**
+ * @brief IIR2 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR2SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR2_SOFTRST_Msk)
+
+/**
+ * @brief IIR1 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR1SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR1_SOFTRST_Msk)
+
+/**
+ * @brief IIR1 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR1SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR1_SOFTRST_Msk)
+
+/**
+ * @brief IIR0 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR0SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR0_SOFTRST_Msk)
+
+/**
+ * @brief IIR0 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IIR0SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_IIR0_SOFTRST_Msk)
+
+/**
+ * @brief FPLL2 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_FPLL2SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_FPLL2_SOFTRST_Msk)
+
+/**
+ * @brief FPLL2 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_FPLL2SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_FPLL2_SOFTRST_Msk)
+
+/**
+ * @brief FPLL1 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_FPLL1SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_FPLL1_SOFTRST_Msk)
+
+/**
+ * @brief FPLL1 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_FPLL1SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_FPLL1_SOFTRST_Msk)
+
+/**
+ * @brief FPLL0 Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_FPLL0SoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_FPLL0_SOFTRST_Msk)
+
+/**
+ * @brief FPLL0 Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_FPLL0SoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_FPLL0_SOFTRST_Msk)
+
+/**
+ * @brief DALI Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DALISoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_DALI_SOFTRST_Msk)
+
+/**
+ * @brief DALI Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DALISoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->APB1RCR, SYSCTRL_DALI_SOFTRST_Msk)
+
+/**
+ * @brief APB1 Soft Reset all Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB1SoftRstAll_Assert(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->APB1RCR, 0x0)
+
+/**
+ * @brief APB1 Soft Reset all Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_APB1SoftRstAll_Release(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->APB1RCR, 0xffffffffUL)
+
+
+/**
+ * @brief DFLASH Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_DFLASH_SOFTRST_Msk)
+
+/**
+ * @brief DFLASH Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DFLASHSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_DFLASH_SOFTRST_Msk)
+
+/**
+ * @brief HSTIMER Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HSTIMERSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_HSTIMER_SOFTRST_Msk)
+
+/**
+ * @brief HSTIMER Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HSTIMERSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_HSTIMER_SOFTRST_Msk)
+
+/**
+ * @brief GPIOD Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOD_SOFTRST_Msk)
+
+/**
+ * @brief GPIOD Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIODSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOD_SOFTRST_Msk)
+
+/**
+ * @brief GPIOC Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOC Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOCSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOC_SOFTRST_Msk)
+
+/**
+ * @brief GPIOB Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOB_SOFTRST_Msk)
+
+/**
+ * @brief GPIOB Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOBSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOB_SOFTRST_Msk)
+
+/**
+ * @brief GPIOA Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOASoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOA_SOFTRST_Msk)
+
+/**
+ * @brief GPIOA Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIOASoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_GPIOA_SOFTRST_Msk)
+
+/**
+ * @brief USB Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_USBSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_USB_SOFTRST_Msk)
+
+/**
+ * @brief USB Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_USBSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_USB_SOFTRST_Msk)
+
+/**
+ * @brief HRPWM Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_HRPWM_SOFTRST_Msk)
+
+/**
+ * @brief HRPWM Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HRPWMSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_HRPWM_SOFTRST_Msk)
+
+/**
+ * @brief DAC Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DACSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_DAC_SOFTRST_Msk)
+
+/**
+ * @brief DAC Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DACSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_DAC_SOFTRST_Msk)
+
+/**
+ * @brief ADC Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_ADC_SOFTRST_Msk)
+
+/**
+ * @brief ADC Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_ADC_SOFTRST_Msk)
+
+/**
+ * @brief CMP Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CMPSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_CMP_SOFTRST_Msk)
+
+/**
+ * @brief CMP Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CMPSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_CMP_SOFTRST_Msk)
+
+/**
+ * @brief EFLASH Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_EFLASH_SOFTRST_Msk)
+
+/**
+ * @brief EFLASH Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_EFLASHSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_EFLASH_SOFTRST_Msk)
+
+/**
+ * @brief CAN Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CANSoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_CAN_SOFTRST_Msk)
+
+/**
+ * @brief CAN Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CANSoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_CAN_SOFTRST_Msk)
+
+/**
+ * @brief DMA Soft Reset Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DMASoftRst_Assert(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_DMA_SOFTRST_Msk)
+
+/**
+ * @brief DMA Soft Reset Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_DMASoftRst_Release(__SYSCTRL__) SET_BIT((__SYSCTRL__)->AHBRCR, SYSCTRL_DMA_SOFTRST_Msk)
+
+/**
+ * @brief AHB Soft Reset all Assert
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AHBSoftRstAll_Assert(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->AHBRCR, 0x0)
+
+/**
+ * @brief AHB Soft Reset all Release
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AHBSoftRstAll_Release(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->AHBRCR, 0xffffffffUL)
+
+
+/**
+ * @brief RC8M Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RC8M_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_RC8M_EN_Msk)
+
+/**
+ * @brief RC8M Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_RC8M_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_RC8M_EN_Msk)
+
+/**
+ * @brief XOSC Loss IRQ Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSCLossIRQ_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSCLOSS_IRQEN_Msk)
+
+/**
+ * @brief XOSC Loss IRQ Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSCLossIRQ_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSCLOSS_IRQEN_Msk)
+
+/**
+ * @brief XOSC HY Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_HY_EN(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_HYEN_Msk)
+
+/**
+ * @brief XOSC HY Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_HY_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_HYEN_Msk)
+
+/**
+ * @brief XOSC DR Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param cur Current
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_DR_Set(__SYSCTRL__, cur) MODIFY_REG((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_DR_Msk, cur)
+
+/**
+ * @brief XOSC CTO Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param cap capacitance Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_CTO_Set(__SYSCTRL__, cap) \
+ MODIFY_REG((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_CTO_Msk, ((cap & 0xfUL) << SYSCTRL_XOSC_CTO_Pos))
+
+/**
+ * @brief XOSC CTI Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param cap capacitance Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_CTI_Set(__SYSCTRL__, cap) \
+ MODIFY_REG((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_CTI_Msk, ((cap & 0xfUL) << SYSCTRL_XOSC_CTI_Pos))
+
+/**
+ * @brief XOSC CS Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param cap capacitance
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_CS_Set(__SYSCTRL__, cap) MODIFY_REG((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_CS_Msk, cap)
+
+/**
+ * @brief XOSC Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_EN_Msk)
+
+/**
+ * @brief XOSC Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->XOSCCR, SYSCTRL_XOSC_EN_Msk)
+
+
+/**
+ * @brief Judge XOSC Loss or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 XOSC hasn't loss
+ * @retval 1 XOSC has loss
+ */
+#define __LL_SYSCTRL_IsXOSCLossPending(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_LOSS_PENDING_Msk) >> SYSCTRL_XOSC_LOSS_PENDING_Pos)
+
+/**
+ * @brief Clear XOSC Loss Pending
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSCLossPending_Clr(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_LOSS_PENDING_Msk)
+
+/**
+ * @brief Enable SYSCLK Auto Switch to RC8M When XOSC Fault
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_SysclkSw_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_SYSCLK_SWEN_Msk)
+
+/**
+ * @brief Disable SYSCLK Auto Switch to RC8M When XOSC Fault
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_SysclkSw_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_SYSCLK_SWEN_Msk)
+
+/**
+ * @brief Enable PLL Ref Clk Auto Switch to RC8M When XOSC Fault
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_PLLRefClkSw_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_REFCLK_SWEN_Msk)
+
+/**
+ * @brief Disable PLL Ref Clk Auto Switch to RC8M When XOSC Fault
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_PLLRefClkSw_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_REFCLK_SWEN_Msk)
+
+/**
+ * @brief XOSC MNT Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_MNT_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_MNTEN_Msk)
+
+/**
+ * @brief XOSC MNT Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_MNT_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_MNTEN_Msk)
+
+/**
+ * @brief XOSC AutoSwitch Window Width Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param width Auto Switch Window Width Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_Width_Set(__SYSCTRL__, width) \
+ MODIFY_REG((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_WIDTH_Msk, ((width & 0xfUL) << SYSCTRL_XOSC_WIDTH_Pos))
+
+/**
+ * @brief XOSC AutoSwitch Function High Limit Value Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param limit High Limit Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_HighLimit_Set(__SYSCTRL__, limit) \
+ MODIFY_REG((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_HIGH_LIMIT_Msk, ((limit & 0x3ffUL) << SYSCTRL_XOSC_HIGH_LIMIT_Pos))
+
+/**
+ * @brief XOSC AutoSwitch Function Low Limit Value Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param limit Low Limit Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_XOSC_LowLimit_Set(__SYSCTRL__, limit) \
+ MODIFY_REG((__SYSCTRL__)->XASWCR, SYSCTRL_XOSC_LOW_LIMIT_Msk, ((limit & 0x3ffUL) << SYSCTRL_XOSC_LOW_LIMIT_Pos))
+
+
+/**
+ * @brief ADC Buffer Source Select
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src ADC Buffer Source
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCBufSrc_Sel(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->BUFCR, SYSCTRL_ADCBUF_SRCSEL_Msk, src)
+
+/**
+ * @brief ADC Buffer Bypass Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCBufBypass_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->BUFCR, SYSCTRL_ADCBUF_BYPASS_Msk)
+
+/**
+ * @brief ADC Buffer Bypass Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCBufBypass_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->BUFCR, SYSCTRL_ADCBUF_BYPASS_Msk)
+
+/**
+ * @brief ADC Buffer Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCBuf_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->BUFCR, SYSCTRL_ADCBUF_EN_Msk)
+
+/**
+ * @brief ADC Buffer Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCBuf_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->BUFCR, SYSCTRL_ADCBUF_EN_Msk)
+
+/**
+ * @brief TOUT Source Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src TOUT Source
+ * @return None
+ */
+#define __LL_SYSCTRL_TOUTSrc_Set(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->BUFCR, SYSCTRL_TOUT_SRC_Msk, src)
+
+
+/**
+ * @brief ADC Fan Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADC_Fan_Dis(__SYSCTRL__) \
+ MODIFY_REG((__SYSCTRL__)->SYSCCR, SYSCTRL_ADCCTRL_FANOUT_EN_Msk, (0x0 << SYSCTRL_ADCCTRL_FANOUT_EN_Pos))
+
+/**
+ * @brief ADC Fan Out Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADC_FanOut_En(__SYSCTRL__) \
+ MODIFY_REG((__SYSCTRL__)->SYSCCR, SYSCTRL_ADCCTRL_FANOUT_EN_Msk, (0x1 << SYSCTRL_ADCCTRL_FANOUT_EN_Pos))
+
+/**
+ * @brief ADC Fan In Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADC_FanIn_En(__SYSCTRL__) \
+ MODIFY_REG((__SYSCTRL__)->SYSCCR, SYSCTRL_ADCCTRL_FANOUT_EN_Msk, (0x2 << SYSCTRL_ADCCTRL_FANOUT_EN_Pos))
+
+/**
+ * @brief ADC Data Fan Out Source Select ADC0
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCDataFanOutSrc_ADC0(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_ADCDATA_FANOUT_SRC_Msk)
+
+/**
+ * @brief ADC Data Fan Out Source Select ADC1
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCDataFanOutSrc_ADC1(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_ADCDATA_FANOUT_SRC_Msk)
+
+/**
+ * @brief ADC Data Fan Out Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCDataFanOut_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_ADCDATA_FANOUT_EN_Msk)
+
+/**
+ * @brief ADC Data Fan Out Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_ADCDataFanOut_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_ADCDATA_FANOUT_EN_Msk)
+
+/**
+ * @brief I2C1 SMBUS Output Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C1_SMBUSOutput_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_I2C1_SMBUS_OE_Msk)
+
+/**
+ * @brief I2C1 SMBUS Output Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C1_SMBUSOutput_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_I2C1_SMBUS_OE_Msk)
+
+/**
+ * @brief I2C0 SMBUS Output Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C0_SMBUSOutput_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_I2C0_SMBUS_OE_Msk)
+
+/**
+ * @brief I2C0 SMBUS Output Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_I2C0_SMBUSOutput_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_I2C0_SMBUS_OE_Msk)
+
+/**
+ * @brief JTAG Bug Fix Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_JTAG_BugFix_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_JTAG_BUGFIX_EN_Msk)
+
+/**
+ * @brief JTAG Bug Fix Diaable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_JTAG_BugFix_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_JTAG_BUGFIX_EN_Msk)
+
+/**
+ * @brief CAN FD Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CAN_FD_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_CANFD_EN_Msk)
+
+/**
+ * @brief CAN FD Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CAN_FD_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_CANFD_EN_Msk)
+
+/**
+ * @brief CPU Lockup Reset Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CPU_LockupRst_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_CPU_LOCKUPRST_EN_Msk)
+
+/**
+ * @brief CPU Lockup Reset Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CPU_LockupRst_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_CPU_LOCKUPRST_EN_Msk)
+
+/**
+ * @brief WWDG Debug Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_WWDG_Debug_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_WWDG_DEBUG_EN_Msk)
+
+/**
+ * @brief WWDG Debug Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_WWDG_Debug_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_WWDG_DEBUG_EN_Msk)
+
+/**
+ * @brief WWDG Timeout Reset Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_WWDG_TimeoutRst_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_WWDG_TIMEOUTRST_EN_Msk)
+
+/**
+ * @brief WWDG Timeout Reset Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_WWDG_TimeoutRst_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_WWDG_TIMEOUTRST_EN_Msk)
+
+/**
+ * @brief IWDG Debug Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IWDG_Debug_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_IWDG_DEBUG_EN_Msk)
+
+/**
+ * @brief IWDG Debug Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IWDG_Debug_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_IWDG_DEBUG_EN_Msk)
+
+/**
+ * @brief IWDG Timeout Reset Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IWDG_TimeoutRst_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_IWDG_TIMEOUTRST_EN_Msk)
+
+/**
+ * @brief IWDG Timeout Reset Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IWDG_TimeoutRst_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_IWDG_TIMEOUTRST_EN_Msk)
+
+/**
+ * @brief HSTMR Debug Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HSTMR_Debug_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_HSTMR_DEBUG_EN_Msk)
+
+/**
+ * @brief HSTMR Debug Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_HSTMR_Debug_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_HSTMR_DEBUG_EN_Msk)
+
+/**
+ * @brief LSTMR Debug Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_LSTMR_Debug_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_LSTMR_DEBUG_EN_Msk)
+
+/**
+ * @brief LSTMR Debug Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_LSTMR_Debug_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_LSTMR_DEBUG_EN_Msk)
+
+/**
+ * @brief GPIO Input NMI Interrupt Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIO_InputNMI_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_GPIO_NMIEN_Msk)
+
+/**
+ * @brief GPIO Input NMI Interrupt Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_GPIO_InputNMI_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_GPIO_NMIEN_Msk)
+
+/**
+ * @brief CLK Test Source Select
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param src CLK Test Source
+ * @return None
+ */
+#define __LL_SYSCTRL_CLK_TestSrc_Sel(__SYSCTRL__, src) MODIFY_REG((__SYSCTRL__)->SYSCCR, SYSCTRL_CLK_TEST_SRC_Msk, src)
+
+/**
+ * @brief CLK Fan Out Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CLK_FanOut_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_CLK_FANOUT_EN_Msk)
+
+/**
+ * @brief CLK Fan Out Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CLK_FanOut_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_CLK_FANOUT_EN_Msk)
+
+/**
+ * @brief PMU Debug1 Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PMU_Debug1_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_PMU_DEBUG1_EN_Msk)
+
+/**
+ * @brief PMU Debug1 Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PMU_Debug1_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_PMU_DEBUG1_EN_Msk)
+
+/**
+ * @brief PMU Debug0 Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PMU_Debug0_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_PMU_DEBUG0_EN_Msk)
+
+/**
+ * @brief PMU Debug0 Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_PMU_Debug0_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_PMU_DEBUG0_EN_Msk)
+
+/**
+ * @brief TEST CLK In Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_TESTClkIn_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_TEST_CLKIN_EN_Msk)
+
+/**
+ * @brief TEST CLK In Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_TESTClkIn_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->SYSCCR, SYSCTRL_TEST_CLKIN_EN_Msk)
+
+
+/**
+ * @brief Judge SysReq Reset or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 Isn't SysReq Reset
+ * @retval 1 Is SysReq Reset
+ */
+#define __LL_SYSCTRL_IsSysReqRst(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_SYSREQ_RST_ST_Msk) >> SYSCTRL_SYSREQ_RST_ST_Pos)
+
+/**
+ * @brief Clear SysReq Reset Pending
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_SysReqRst_Clr(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_SYSREQ_RST_ST_Msk)
+
+/**
+ * @brief Judge MCLR Reset or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 Isn't MCLR Reset
+ * @retval 1 Is MCLR Reset
+ */
+#define __LL_SYSCTRL_IsMCLRRst(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_MCLR_RST_ST_Msk) >> SYSCTRL_MCLR_RST_ST_Pos)
+
+/**
+ * @brief Clear MCLR Reset Pending
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_MCLRRst_Clr(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_MCLR_RST_ST_Msk)
+
+/**
+ * @brief Judge LVD Reset or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 Isn't LVD Reset
+ * @retval 1 Is LVD Reset
+ */
+#define __LL_SYSCTRL_IsLVDRst(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_LVD_RST_ST_Msk) >> SYSCTRL_LVD_RST_ST_Pos)
+
+/**
+ * @brief Clear LVD Reset Pending
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_LVDRst_Clr(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_LVD_RST_ST_Msk)
+
+/**
+ * @brief Judge WWDG Reset or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 Isn't WWDG Reset
+ * @retval 1 Is WWDG Reset
+ */
+#define __LL_SYSCTRL_IsWWDGRst(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_WWDG_RST_ST_Msk) >> SYSCTRL_WWDG_RST_ST_Pos)
+
+/**
+ * @brief Clear WWDG Reset Pending
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_WWDGRst_Clr(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_WWDG_RST_ST_Msk)
+
+/**
+ * @brief Judge IWDG Reset or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 Isn't IWDG Reset
+ * @retval 1 Is IWDG Reset
+ */
+#define __LL_SYSCTRL_IsIWDGRst(__SYSCTRL__) \
+ (READ_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_IWDG_RST_ST_Msk) >> SYSCTRL_IWDG_RST_ST_Pos)
+
+/**
+ * @brief Clear IWDG Reset Pending
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_IWDGRst_Clr(__SYSCTRL__) SET_BIT((__SYSCTRL__)->SRSTSR, SYSCTRL_IWDG_RST_ST_Msk)
+
+
+/**
+ * @brief SYSCTRL Control Register Unlock
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CTRLReg_Unlock(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->KEY, 0x3fac87e4)
+
+/**
+ * @brief SYSCTRL FLS Register Unlock
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_FLSReg_Unlock(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->KEY, 0x1f2e3c4a)
+
+/**
+ * @brief SYSCTRL Reg Lock
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_Reg_Lock(__SYSCTRL__) WRITE_REG((__SYSCTRL__)->KEY, 0x00)
+
+/**
+ * @brief Judge SYSCTRL CTRL Register is unlock or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 SYSCTRL CTRL Register is lock
+ * @retval 1 SYSCTRL CTRL Register is unlock
+ */
+#define __LL_SYSCTRL_IsCTRLRegUnlock(__SYSCTRL__) (READ_REG((__SYSCTRL__)->KEY) == 0x3fac87e4)
+
+/**
+ * @brief Judge SYSCTRL FLS Register is unlock or not
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @retval 0 SYSCTRL FLS Register is lock
+ * @retval 1 SYSCTRL FLS Register is unlock
+ */
+#define __LL_SYSCTRL_IsFLSRegUnlock(__SYSCTRL__) (READ_REG((__SYSCTRL__)->KEY) == 0x1f2e3c4a)
+
+
+/**
+ * @brief PMU In Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param val Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_PMU_In_Set(__SYSCTRL__, val) \
+ MODIFY_REG((__SYSCTRL__)->PMUCR, SYSCTRL_PMU_IN_Msk, ((val & 0x3fUL) << SYSCTRL_PMU_IN_Pos))
+
+/**
+ * @brief CUR Resistance Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param res Resistance Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_CUR_RES_Set(__SYSCTRL__, res) \
+ MODIFY_REG((__SYSCTRL__)->PMUCR, SYSCTRL_CUR_RES_Msk, ((res & 0x3fUL) << SYSCTRL_CUR_RES_Pos))
+
+/**
+ * @brief CUR CAL Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param val Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_CUR_CAL_Set(__SYSCTRL__, val) \
+ MODIFY_REG((__SYSCTRL__)->PMUCR, SYSCTRL_CUR_CAL_Msk, ((val & 0x3UL) << SYSCTRL_CUR_CAL_Pos))
+
+/**
+ * @brief AVDD DRD Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AVDD_DRD_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_AVDD_DRD_Msk)
+
+/**
+ * @brief AVDD DRD Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AVDD_DRD_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_AVDD_DRD_Msk)
+
+/**
+ * @brief AVDD Voltage Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param vol AVDD Voltage
+ * @return None
+ */
+#define __LL_SYSCTRL_AVDD_VOL_Sel(__SYSCTRL__, vol) MODIFY_REG((__SYSCTRL__)->PMUCR, SYSCTRL_AVDD_SET_Msk, vol)
+
+/**
+ * @brief VDD Voltage Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param vol VDD Voltage
+ * @return None
+ */
+#define __LL_SYSCTRL_VDD_VOL_Sel(__SYSCTRL__, vol) MODIFY_REG((__SYSCTRL__)->PMUCR, SYSCTRL_VDD_SET_Msk, vol)
+
+/**
+ * @brief CUR Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CUR_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_CUR_ENABLE_Msk)
+
+/**
+ * @brief CUR Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_CUR_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_CUR_ENABLE_Msk)
+
+/**
+ * @brief AVDDLDO Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AVDDLDO_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_AVDDLDO_ENABLE_Msk)
+
+/**
+ * @brief AVDDLDO Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_AVDDLDO_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_AVDDLDO_ENABLE_Msk)
+
+/**
+ * @brief Temperature Sensor Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_TempSensor_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_TEMPSENSOR_ENABLE_Msk)
+
+/**
+ * @brief Temperature Sensor Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_TempSensor_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_TEMPSENSOR_ENABLE_Msk)
+
+/**
+ * @brief Band Gap Voltage Set
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @param vol Voltage Register Value
+ * @return None
+ */
+#define __LL_SYSCTRL_BandGapVol_Set(__SYSCTRL__, vol) \
+ MODIFY_REG((__SYSCTRL__)->PMUCR, SYSCTRL_BGR_VOL_Msk, ((vol & 0x1fUL) << SYSCTRL_BGR_VOL_Pos))
+
+/**
+ * @brief BGR DRD Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_BGR_DRD_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_BGR_DRD_Msk)
+
+/**
+ * @brief BGR DRD Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_BGR_DRD_Dis(__SYSCTRL__) CLEAR_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_BGR_DRD_Msk)
+
+/**
+ * @brief BGR Filter Enable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_BGR_Filter_En(__SYSCTRL__) SET_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_BGR_FILTER_Msk)
+
+/**
+ * @brief BGR Filter Disable
+ * @param __SYSCTRL__ Specifies SYSCTRL peripheral
+ * @return None
+ */
+#define __LL_SYSCTRL_BGR_Filter_Dis(__SYSCTRL__) \
+ __LL_SYSCTRL_CtrlREG_OPT(CLEAR_BIT((__SYSCTRL__)->PMUCR, SYSCTRL_BGR_FILTER_Msk))
+
+
+/**
+ * @brief SYSCTRL CTRL Register Operation
+ * @param expression SYSCTRL CTRL Register Read/Write Operation
+ * @note Only Write Operation need Unlock before Operation
+ * @return None
+ */
+#define __LL_SYSCTRL_CtrlREG_OPT(expression) \
+ do { \
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL); \
+ expression; \
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL); \
+ } while(0)
+
+/**
+ * @brief SYSCTRL FLS Register Operation
+ * @param expression SYSCTRL FLS Register Read/Write Operation
+ * @note Only Write Operation need Unlock before Operation
+ * @return None
+ */
+#define __LL_SYSCTRL_FlsREG_OPT(expression) \
+ do { \
+ __LL_SYSCTRL_FLSReg_Unlock(SYSCTRL); \
+ expression; \
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL); \
+ } while(0)
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SYSCTRL_LL_Exported_Types SYSCTRL LL Exported Types
+ * @brief SYSCTRL LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief SYSCTRL CLK Div Definition
+ */
+typedef enum {
+ SYSCTRL_CLK_DIV_IVD = 0,/*!< SYSCTRL CLK DIV IND */
+ SYSCTRL_CLK_DIV_1, /*!< SYSCTRL CLK DIV 1 */
+ SYSCTRL_CLK_DIV_2, /*!< SYSCTRL CLK DIV 2 */
+ SYSCTRL_CLK_DIV_3, /*!< SYSCTRL CLK DIV 3 */
+ SYSCTRL_CLK_DIV_4, /*!< SYSCTRL CLK DIV 4 */
+ SYSCTRL_CLK_DIV_5, /*!< SYSCTRL CLK DIV 5 */
+ SYSCTRL_CLK_DIV_6, /*!< SYSCTRL CLK DIV 6 */
+ SYSCTRL_CLK_DIV_7, /*!< SYSCTRL CLK DIV 7 */
+ SYSCTRL_CLK_DIV_8, /*!< SYSCTRL CLK DIV 8 */
+ SYSCTRL_CLK_DIV_9, /*!< SYSCTRL CLK DIV 9 */
+ SYSCTRL_CLK_DIV_10, /*!< SYSCTRL CLK DIV 10 */
+ SYSCTRL_CLK_DIV_11, /*!< SYSCTRL CLK DIV 11 */
+ SYSCTRL_CLK_DIV_12, /*!< SYSCTRL CLK DIV 12 */
+ SYSCTRL_CLK_DIV_13, /*!< SYSCTRL CLK DIV 13 */
+ SYSCTRL_CLK_DIV_14, /*!< SYSCTRL CLK DIV 14 */
+ SYSCTRL_CLK_DIV_15, /*!< SYSCTRL CLK DIV 15 */
+ SYSCTRL_CLK_DIV_16, /*!< SYSCTRL CLK DIV 16 */
+ SYSCTRL_CLK_DIV_17, /*!< SYSCTRL CLK DIV 17 */
+ SYSCTRL_CLK_DIV_18, /*!< SYSCTRL CLK DIV 18 */
+ SYSCTRL_CLK_DIV_19, /*!< SYSCTRL CLK DIV 19 */
+ SYSCTRL_CLK_DIV_20, /*!< SYSCTRL CLK DIV 20 */
+ SYSCTRL_CLK_DIV_21, /*!< SYSCTRL CLK DIV 21 */
+ SYSCTRL_CLK_DIV_22, /*!< SYSCTRL CLK DIV 22 */
+ SYSCTRL_CLK_DIV_23, /*!< SYSCTRL CLK DIV 23 */
+ SYSCTRL_CLK_DIV_24, /*!< SYSCTRL CLK DIV 24 */
+ SYSCTRL_CLK_DIV_25, /*!< SYSCTRL CLK DIV 25 */
+ SYSCTRL_CLK_DIV_26, /*!< SYSCTRL CLK DIV 26 */
+ SYSCTRL_CLK_DIV_27, /*!< SYSCTRL CLK DIV 27 */
+ SYSCTRL_CLK_DIV_28, /*!< SYSCTRL CLK DIV 28 */
+ SYSCTRL_CLK_DIV_29, /*!< SYSCTRL CLK DIV 29 */
+ SYSCTRL_CLK_DIV_30, /*!< SYSCTRL CLK DIV 30 */
+ SYSCTRL_CLK_DIV_31, /*!< SYSCTRL CLK DIV 31 */
+ SYSCTRL_CLK_DIV_32, /*!< SYSCTRL CLK DIV 32 */
+ SYSCTRL_CLK_DIV_33, /*!< SYSCTRL CLK DIV 33 */
+ SYSCTRL_CLK_DIV_34, /*!< SYSCTRL CLK DIV 34 */
+ SYSCTRL_CLK_DIV_35, /*!< SYSCTRL CLK DIV 35 */
+ SYSCTRL_CLK_DIV_36, /*!< SYSCTRL CLK DIV 36 */
+ SYSCTRL_CLK_DIV_37, /*!< SYSCTRL CLK DIV 37 */
+ SYSCTRL_CLK_DIV_38, /*!< SYSCTRL CLK DIV 38 */
+ SYSCTRL_CLK_DIV_39, /*!< SYSCTRL CLK DIV 39 */
+ SYSCTRL_CLK_DIV_40, /*!< SYSCTRL CLK DIV 40 */
+ SYSCTRL_CLK_DIV_41, /*!< SYSCTRL CLK DIV 41 */
+ SYSCTRL_CLK_DIV_42, /*!< SYSCTRL CLK DIV 42 */
+ SYSCTRL_CLK_DIV_43, /*!< SYSCTRL CLK DIV 43 */
+ SYSCTRL_CLK_DIV_44, /*!< SYSCTRL CLK DIV 44 */
+ SYSCTRL_CLK_DIV_45, /*!< SYSCTRL CLK DIV 45 */
+ SYSCTRL_CLK_DIV_46, /*!< SYSCTRL CLK DIV 46 */
+ SYSCTRL_CLK_DIV_47, /*!< SYSCTRL CLK DIV 47 */
+ SYSCTRL_CLK_DIV_48, /*!< SYSCTRL CLK DIV 48 */
+ SYSCTRL_CLK_DIV_49, /*!< SYSCTRL CLK DIV 49 */
+ SYSCTRL_CLK_DIV_50, /*!< SYSCTRL CLK DIV 50 */
+ SYSCTRL_CLK_DIV_51, /*!< SYSCTRL CLK DIV 51 */
+ SYSCTRL_CLK_DIV_52, /*!< SYSCTRL CLK DIV 52 */
+ SYSCTRL_CLK_DIV_53, /*!< SYSCTRL CLK DIV 53 */
+ SYSCTRL_CLK_DIV_54, /*!< SYSCTRL CLK DIV 54 */
+ SYSCTRL_CLK_DIV_55, /*!< SYSCTRL CLK DIV 55 */
+ SYSCTRL_CLK_DIV_56, /*!< SYSCTRL CLK DIV 56 */
+ SYSCTRL_CLK_DIV_57, /*!< SYSCTRL CLK DIV 57 */
+ SYSCTRL_CLK_DIV_58, /*!< SYSCTRL CLK DIV 58 */
+ SYSCTRL_CLK_DIV_59, /*!< SYSCTRL CLK DIV 59 */
+ SYSCTRL_CLK_DIV_60, /*!< SYSCTRL CLK DIV 60 */
+ SYSCTRL_CLK_DIV_61, /*!< SYSCTRL CLK DIV 61 */
+ SYSCTRL_CLK_DIV_62, /*!< SYSCTRL CLK DIV 62 */
+ SYSCTRL_CLK_DIV_63, /*!< SYSCTRL CLK DIV 63 */
+ SYSCTRL_CLK_DIV_64, /*!< SYSCTRL CLK DIV 64 */
+ SYSCTRL_CLK_DIV_65, /*!< SYSCTRL CLK DIV 65 */
+ SYSCTRL_CLK_DIV_66, /*!< SYSCTRL CLK DIV 66 */
+ SYSCTRL_CLK_DIV_67, /*!< SYSCTRL CLK DIV 67 */
+ SYSCTRL_CLK_DIV_68, /*!< SYSCTRL CLK DIV 68 */
+ SYSCTRL_CLK_DIV_69, /*!< SYSCTRL CLK DIV 69 */
+ SYSCTRL_CLK_DIV_70, /*!< SYSCTRL CLK DIV 70 */
+ SYSCTRL_CLK_DIV_71, /*!< SYSCTRL CLK DIV 71 */
+ SYSCTRL_CLK_DIV_72, /*!< SYSCTRL CLK DIV 72 */
+ SYSCTRL_CLK_DIV_73, /*!< SYSCTRL CLK DIV 73 */
+ SYSCTRL_CLK_DIV_74, /*!< SYSCTRL CLK DIV 74 */
+ SYSCTRL_CLK_DIV_75, /*!< SYSCTRL CLK DIV 75 */
+ SYSCTRL_CLK_DIV_76, /*!< SYSCTRL CLK DIV 76 */
+ SYSCTRL_CLK_DIV_77, /*!< SYSCTRL CLK DIV 77 */
+ SYSCTRL_CLK_DIV_78, /*!< SYSCTRL CLK DIV 78 */
+ SYSCTRL_CLK_DIV_79, /*!< SYSCTRL CLK DIV 79 */
+ SYSCTRL_CLK_DIV_80, /*!< SYSCTRL CLK DIV 80 */
+ SYSCTRL_CLK_DIV_81, /*!< SYSCTRL CLK DIV 81 */
+ SYSCTRL_CLK_DIV_82, /*!< SYSCTRL CLK DIV 82 */
+ SYSCTRL_CLK_DIV_83, /*!< SYSCTRL CLK DIV 83 */
+ SYSCTRL_CLK_DIV_84, /*!< SYSCTRL CLK DIV 84 */
+ SYSCTRL_CLK_DIV_85, /*!< SYSCTRL CLK DIV 85 */
+ SYSCTRL_CLK_DIV_86, /*!< SYSCTRL CLK DIV 86 */
+ SYSCTRL_CLK_DIV_87, /*!< SYSCTRL CLK DIV 87 */
+ SYSCTRL_CLK_DIV_88, /*!< SYSCTRL CLK DIV 88 */
+ SYSCTRL_CLK_DIV_89, /*!< SYSCTRL CLK DIV 89 */
+ SYSCTRL_CLK_DIV_90, /*!< SYSCTRL CLK DIV 90 */
+ SYSCTRL_CLK_DIV_91, /*!< SYSCTRL CLK DIV 91 */
+ SYSCTRL_CLK_DIV_92, /*!< SYSCTRL CLK DIV 92 */
+ SYSCTRL_CLK_DIV_93, /*!< SYSCTRL CLK DIV 93 */
+ SYSCTRL_CLK_DIV_94, /*!< SYSCTRL CLK DIV 94 */
+ SYSCTRL_CLK_DIV_95, /*!< SYSCTRL CLK DIV 95 */
+ SYSCTRL_CLK_DIV_96, /*!< SYSCTRL CLK DIV 96 */
+ SYSCTRL_CLK_DIV_97, /*!< SYSCTRL CLK DIV 97 */
+ SYSCTRL_CLK_DIV_98, /*!< SYSCTRL CLK DIV 98 */
+ SYSCTRL_CLK_DIV_99, /*!< SYSCTRL CLK DIV 99 */
+ SYSCTRL_CLK_DIV_100, /*!< SYSCTRL CLK DIV 100 */
+ SYSCTRL_CLK_DIV_101, /*!< SYSCTRL CLK DIV 101 */
+ SYSCTRL_CLK_DIV_102, /*!< SYSCTRL CLK DIV 102 */
+ SYSCTRL_CLK_DIV_103, /*!< SYSCTRL CLK DIV 103 */
+ SYSCTRL_CLK_DIV_104, /*!< SYSCTRL CLK DIV 104 */
+ SYSCTRL_CLK_DIV_105, /*!< SYSCTRL CLK DIV 105 */
+ SYSCTRL_CLK_DIV_106, /*!< SYSCTRL CLK DIV 106 */
+ SYSCTRL_CLK_DIV_107, /*!< SYSCTRL CLK DIV 107 */
+ SYSCTRL_CLK_DIV_108, /*!< SYSCTRL CLK DIV 108 */
+ SYSCTRL_CLK_DIV_109, /*!< SYSCTRL CLK DIV 109 */
+ SYSCTRL_CLK_DIV_110, /*!< SYSCTRL CLK DIV 110 */
+ SYSCTRL_CLK_DIV_111, /*!< SYSCTRL CLK DIV 111 */
+ SYSCTRL_CLK_DIV_112, /*!< SYSCTRL CLK DIV 112 */
+ SYSCTRL_CLK_DIV_113, /*!< SYSCTRL CLK DIV 113 */
+ SYSCTRL_CLK_DIV_114, /*!< SYSCTRL CLK DIV 114 */
+ SYSCTRL_CLK_DIV_115, /*!< SYSCTRL CLK DIV 115 */
+ SYSCTRL_CLK_DIV_116, /*!< SYSCTRL CLK DIV 116 */
+ SYSCTRL_CLK_DIV_117, /*!< SYSCTRL CLK DIV 117 */
+ SYSCTRL_CLK_DIV_118, /*!< SYSCTRL CLK DIV 118 */
+ SYSCTRL_CLK_DIV_119, /*!< SYSCTRL CLK DIV 119 */
+ SYSCTRL_CLK_DIV_120, /*!< SYSCTRL CLK DIV 120 */
+ SYSCTRL_CLK_DIV_121, /*!< SYSCTRL CLK DIV 121 */
+ SYSCTRL_CLK_DIV_122, /*!< SYSCTRL CLK DIV 122 */
+ SYSCTRL_CLK_DIV_123, /*!< SYSCTRL CLK DIV 123 */
+ SYSCTRL_CLK_DIV_124, /*!< SYSCTRL CLK DIV 124 */
+ SYSCTRL_CLK_DIV_125, /*!< SYSCTRL CLK DIV 125 */
+ SYSCTRL_CLK_DIV_126, /*!< SYSCTRL CLK DIV 126 */
+ SYSCTRL_CLK_DIV_127, /*!< SYSCTRL CLK DIV 127 */
+ SYSCTRL_CLK_DIV_128, /*!< SYSCTRL CLK DIV 128 */
+ SYSCTRL_CLK_DIV_129, /*!< SYSCTRL CLK DIV 129 */
+ SYSCTRL_CLK_DIV_130, /*!< SYSCTRL CLK DIV 130 */
+ SYSCTRL_CLK_DIV_131, /*!< SYSCTRL CLK DIV 131 */
+ SYSCTRL_CLK_DIV_132, /*!< SYSCTRL CLK DIV 132 */
+ SYSCTRL_CLK_DIV_133, /*!< SYSCTRL CLK DIV 133 */
+ SYSCTRL_CLK_DIV_134, /*!< SYSCTRL CLK DIV 134 */
+ SYSCTRL_CLK_DIV_135, /*!< SYSCTRL CLK DIV 135 */
+ SYSCTRL_CLK_DIV_136, /*!< SYSCTRL CLK DIV 136 */
+ SYSCTRL_CLK_DIV_137, /*!< SYSCTRL CLK DIV 137 */
+ SYSCTRL_CLK_DIV_138, /*!< SYSCTRL CLK DIV 138 */
+ SYSCTRL_CLK_DIV_139, /*!< SYSCTRL CLK DIV 139 */
+ SYSCTRL_CLK_DIV_140, /*!< SYSCTRL CLK DIV 140 */
+ SYSCTRL_CLK_DIV_141, /*!< SYSCTRL CLK DIV 141 */
+ SYSCTRL_CLK_DIV_142, /*!< SYSCTRL CLK DIV 142 */
+ SYSCTRL_CLK_DIV_143, /*!< SYSCTRL CLK DIV 143 */
+ SYSCTRL_CLK_DIV_144, /*!< SYSCTRL CLK DIV 144 */
+ SYSCTRL_CLK_DIV_145, /*!< SYSCTRL CLK DIV 145 */
+ SYSCTRL_CLK_DIV_146, /*!< SYSCTRL CLK DIV 146 */
+ SYSCTRL_CLK_DIV_147, /*!< SYSCTRL CLK DIV 147 */
+ SYSCTRL_CLK_DIV_148, /*!< SYSCTRL CLK DIV 148 */
+ SYSCTRL_CLK_DIV_149, /*!< SYSCTRL CLK DIV 149 */
+ SYSCTRL_CLK_DIV_150, /*!< SYSCTRL CLK DIV 150 */
+ SYSCTRL_CLK_DIV_151, /*!< SYSCTRL CLK DIV 151 */
+ SYSCTRL_CLK_DIV_152, /*!< SYSCTRL CLK DIV 152 */
+ SYSCTRL_CLK_DIV_153, /*!< SYSCTRL CLK DIV 153 */
+ SYSCTRL_CLK_DIV_154, /*!< SYSCTRL CLK DIV 154 */
+ SYSCTRL_CLK_DIV_155, /*!< SYSCTRL CLK DIV 155 */
+ SYSCTRL_CLK_DIV_156, /*!< SYSCTRL CLK DIV 156 */
+ SYSCTRL_CLK_DIV_157, /*!< SYSCTRL CLK DIV 157 */
+ SYSCTRL_CLK_DIV_158, /*!< SYSCTRL CLK DIV 158 */
+ SYSCTRL_CLK_DIV_159, /*!< SYSCTRL CLK DIV 159 */
+ SYSCTRL_CLK_DIV_160, /*!< SYSCTRL CLK DIV 160 */
+ SYSCTRL_CLK_DIV_161, /*!< SYSCTRL CLK DIV 161 */
+ SYSCTRL_CLK_DIV_162, /*!< SYSCTRL CLK DIV 162 */
+ SYSCTRL_CLK_DIV_163, /*!< SYSCTRL CLK DIV 163 */
+ SYSCTRL_CLK_DIV_164, /*!< SYSCTRL CLK DIV 164 */
+ SYSCTRL_CLK_DIV_165, /*!< SYSCTRL CLK DIV 165 */
+ SYSCTRL_CLK_DIV_166, /*!< SYSCTRL CLK DIV 166 */
+ SYSCTRL_CLK_DIV_167, /*!< SYSCTRL CLK DIV 167 */
+ SYSCTRL_CLK_DIV_168, /*!< SYSCTRL CLK DIV 168 */
+ SYSCTRL_CLK_DIV_169, /*!< SYSCTRL CLK DIV 169 */
+ SYSCTRL_CLK_DIV_170, /*!< SYSCTRL CLK DIV 170 */
+ SYSCTRL_CLK_DIV_171, /*!< SYSCTRL CLK DIV 171 */
+ SYSCTRL_CLK_DIV_172, /*!< SYSCTRL CLK DIV 172 */
+ SYSCTRL_CLK_DIV_173, /*!< SYSCTRL CLK DIV 173 */
+ SYSCTRL_CLK_DIV_174, /*!< SYSCTRL CLK DIV 174 */
+ SYSCTRL_CLK_DIV_175, /*!< SYSCTRL CLK DIV 175 */
+ SYSCTRL_CLK_DIV_176, /*!< SYSCTRL CLK DIV 176 */
+ SYSCTRL_CLK_DIV_177, /*!< SYSCTRL CLK DIV 177 */
+ SYSCTRL_CLK_DIV_178, /*!< SYSCTRL CLK DIV 178 */
+ SYSCTRL_CLK_DIV_179, /*!< SYSCTRL CLK DIV 179 */
+ SYSCTRL_CLK_DIV_180, /*!< SYSCTRL CLK DIV 180 */
+ SYSCTRL_CLK_DIV_181, /*!< SYSCTRL CLK DIV 181 */
+ SYSCTRL_CLK_DIV_182, /*!< SYSCTRL CLK DIV 182 */
+ SYSCTRL_CLK_DIV_183, /*!< SYSCTRL CLK DIV 183 */
+ SYSCTRL_CLK_DIV_184, /*!< SYSCTRL CLK DIV 184 */
+ SYSCTRL_CLK_DIV_185, /*!< SYSCTRL CLK DIV 185 */
+ SYSCTRL_CLK_DIV_186, /*!< SYSCTRL CLK DIV 186 */
+ SYSCTRL_CLK_DIV_187, /*!< SYSCTRL CLK DIV 187 */
+ SYSCTRL_CLK_DIV_188, /*!< SYSCTRL CLK DIV 188 */
+ SYSCTRL_CLK_DIV_189, /*!< SYSCTRL CLK DIV 189 */
+ SYSCTRL_CLK_DIV_190, /*!< SYSCTRL CLK DIV 190 */
+ SYSCTRL_CLK_DIV_191, /*!< SYSCTRL CLK DIV 191 */
+ SYSCTRL_CLK_DIV_192, /*!< SYSCTRL CLK DIV 192 */
+ SYSCTRL_CLK_DIV_193, /*!< SYSCTRL CLK DIV 193 */
+ SYSCTRL_CLK_DIV_194, /*!< SYSCTRL CLK DIV 194 */
+ SYSCTRL_CLK_DIV_195, /*!< SYSCTRL CLK DIV 195 */
+ SYSCTRL_CLK_DIV_196, /*!< SYSCTRL CLK DIV 196 */
+ SYSCTRL_CLK_DIV_197, /*!< SYSCTRL CLK DIV 197 */
+ SYSCTRL_CLK_DIV_198, /*!< SYSCTRL CLK DIV 198 */
+ SYSCTRL_CLK_DIV_199, /*!< SYSCTRL CLK DIV 199 */
+ SYSCTRL_CLK_DIV_200, /*!< SYSCTRL CLK DIV 200 */
+ SYSCTRL_CLK_DIV_201, /*!< SYSCTRL CLK DIV 201 */
+ SYSCTRL_CLK_DIV_202, /*!< SYSCTRL CLK DIV 202 */
+ SYSCTRL_CLK_DIV_203, /*!< SYSCTRL CLK DIV 203 */
+ SYSCTRL_CLK_DIV_204, /*!< SYSCTRL CLK DIV 204 */
+ SYSCTRL_CLK_DIV_205, /*!< SYSCTRL CLK DIV 205 */
+ SYSCTRL_CLK_DIV_206, /*!< SYSCTRL CLK DIV 206 */
+ SYSCTRL_CLK_DIV_207, /*!< SYSCTRL CLK DIV 207 */
+ SYSCTRL_CLK_DIV_208, /*!< SYSCTRL CLK DIV 208 */
+ SYSCTRL_CLK_DIV_209, /*!< SYSCTRL CLK DIV 209 */
+ SYSCTRL_CLK_DIV_210, /*!< SYSCTRL CLK DIV 210 */
+ SYSCTRL_CLK_DIV_211, /*!< SYSCTRL CLK DIV 211 */
+ SYSCTRL_CLK_DIV_212, /*!< SYSCTRL CLK DIV 212 */
+ SYSCTRL_CLK_DIV_213, /*!< SYSCTRL CLK DIV 213 */
+ SYSCTRL_CLK_DIV_214, /*!< SYSCTRL CLK DIV 214 */
+ SYSCTRL_CLK_DIV_215, /*!< SYSCTRL CLK DIV 215 */
+ SYSCTRL_CLK_DIV_216, /*!< SYSCTRL CLK DIV 216 */
+ SYSCTRL_CLK_DIV_217, /*!< SYSCTRL CLK DIV 217 */
+ SYSCTRL_CLK_DIV_218, /*!< SYSCTRL CLK DIV 218 */
+ SYSCTRL_CLK_DIV_219, /*!< SYSCTRL CLK DIV 219 */
+ SYSCTRL_CLK_DIV_220, /*!< SYSCTRL CLK DIV 220 */
+ SYSCTRL_CLK_DIV_221, /*!< SYSCTRL CLK DIV 221 */
+ SYSCTRL_CLK_DIV_222, /*!< SYSCTRL CLK DIV 222 */
+ SYSCTRL_CLK_DIV_223, /*!< SYSCTRL CLK DIV 223 */
+ SYSCTRL_CLK_DIV_224, /*!< SYSCTRL CLK DIV 224 */
+ SYSCTRL_CLK_DIV_225, /*!< SYSCTRL CLK DIV 225 */
+ SYSCTRL_CLK_DIV_226, /*!< SYSCTRL CLK DIV 226 */
+ SYSCTRL_CLK_DIV_227, /*!< SYSCTRL CLK DIV 227 */
+ SYSCTRL_CLK_DIV_228, /*!< SYSCTRL CLK DIV 228 */
+ SYSCTRL_CLK_DIV_229, /*!< SYSCTRL CLK DIV 229 */
+ SYSCTRL_CLK_DIV_230, /*!< SYSCTRL CLK DIV 230 */
+ SYSCTRL_CLK_DIV_231, /*!< SYSCTRL CLK DIV 231 */
+ SYSCTRL_CLK_DIV_232, /*!< SYSCTRL CLK DIV 232 */
+ SYSCTRL_CLK_DIV_233, /*!< SYSCTRL CLK DIV 233 */
+ SYSCTRL_CLK_DIV_234, /*!< SYSCTRL CLK DIV 234 */
+ SYSCTRL_CLK_DIV_235, /*!< SYSCTRL CLK DIV 235 */
+ SYSCTRL_CLK_DIV_236, /*!< SYSCTRL CLK DIV 236 */
+ SYSCTRL_CLK_DIV_237, /*!< SYSCTRL CLK DIV 237 */
+ SYSCTRL_CLK_DIV_238, /*!< SYSCTRL CLK DIV 238 */
+ SYSCTRL_CLK_DIV_239, /*!< SYSCTRL CLK DIV 239 */
+ SYSCTRL_CLK_DIV_240, /*!< SYSCTRL CLK DIV 240 */
+ SYSCTRL_CLK_DIV_241, /*!< SYSCTRL CLK DIV 241 */
+ SYSCTRL_CLK_DIV_242, /*!< SYSCTRL CLK DIV 242 */
+ SYSCTRL_CLK_DIV_243, /*!< SYSCTRL CLK DIV 243 */
+ SYSCTRL_CLK_DIV_244, /*!< SYSCTRL CLK DIV 244 */
+ SYSCTRL_CLK_DIV_245, /*!< SYSCTRL CLK DIV 245 */
+ SYSCTRL_CLK_DIV_246, /*!< SYSCTRL CLK DIV 246 */
+ SYSCTRL_CLK_DIV_247, /*!< SYSCTRL CLK DIV 247 */
+ SYSCTRL_CLK_DIV_248, /*!< SYSCTRL CLK DIV 248 */
+ SYSCTRL_CLK_DIV_249, /*!< SYSCTRL CLK DIV 249 */
+ SYSCTRL_CLK_DIV_250, /*!< SYSCTRL CLK DIV 250 */
+ SYSCTRL_CLK_DIV_251, /*!< SYSCTRL CLK DIV 251 */
+ SYSCTRL_CLK_DIV_252, /*!< SYSCTRL CLK DIV 252 */
+ SYSCTRL_CLK_DIV_253, /*!< SYSCTRL CLK DIV 253 */
+ SYSCTRL_CLK_DIV_254, /*!< SYSCTRL CLK DIV 254 */
+ SYSCTRL_CLK_DIV_255, /*!< SYSCTRL CLK DIV 255 */
+ SYSCTRL_CLK_DIV_256, /*!< SYSCTRL CLK DIV 256 */
+} SYSCTRL_ClkDivETypeDef;
+
+/**
+ * @brief SYSCTRL SYSCLK Source Definition
+ */
+typedef enum {
+ SYSCLK_SRC_RC32K = 0, /*!< SYSCLK Source RC32K */
+ SYSCLK_SRC_RC8M = 1, /*!< SYSCLK Source RC8M */
+ SYSCLK_SRC_PLL0DivClk = 2, /*!< SYSCLK Source PLL0 Div Clk */
+ SYSCLK_SRC_HOSC = 3, /*!< SYSCLK Source HOSC */
+} SYSCTRL_SysclkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL GPIOA Debounce Clock Source Definition
+ */
+typedef enum {
+ GPIOA_DBC_CLK_SRC_RC8M = SYSCTRL_GPIOA_DBCCLK_SRC_RC8M, /*!< GPIOA DBC CLK Source RC8M */
+ GPIOA_DBC_CLK_SRC_XOSC = SYSCTRL_GPIOA_DBCCLK_SRC_XOSC, /*!< GPIOA DBC CLK Source XOSC */
+ GPIOA_DBC_CLK_SRC_SYSCLK = SYSCTRL_GPIOA_DBCCLK_SRC_SYSCLK, /*!< GPIOA DBC CLK Source SYSCLK */
+ GPIOA_DBC_CLK_SRC_RC32K = SYSCTRL_GPIOA_DBCCLK_SRC_RC32K, /*!< GPIOA DBC CLK Source RC32K */
+} SYSCTRL_GPIOADbcClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL GPIOB Debounce Clock Source Definition
+ */
+typedef enum {
+ GPIOB_DBC_CLK_SRC_RC8M = SYSCTRL_GPIOB_DBCCLK_SRC_RC8M, /*!< GPIOB DBC CLK Source RC8M */
+ GPIOB_DBC_CLK_SRC_XOSC = SYSCTRL_GPIOB_DBCCLK_SRC_XOSC, /*!< GPIOB DBC CLK Source XOSC */
+ GPIOB_DBC_CLK_SRC_SYSCLK = SYSCTRL_GPIOB_DBCCLK_SRC_SYSCLK, /*!< GPIOB DBC CLK Source SYSCLK */
+ GPIOB_DBC_CLK_SRC_RC32K = SYSCTRL_GPIOB_DBCCLK_SRC_RC32K, /*!< GPIOB DBC CLK Source RC32K */
+} SYSCTRL_GPIOBDbcClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL GPIOC Debounce Clock Source Definition
+ */
+typedef enum {
+ GPIOC_DBC_CLK_SRC_RC8M = SYSCTRL_GPIOC_DBCCLK_SRC_RC8M, /*!< GPIOC DBC CLK Source RC8M */
+ GPIOC_DBC_CLK_SRC_XOSC = SYSCTRL_GPIOC_DBCCLK_SRC_XOSC, /*!< GPIOC DBC CLK Source XOSC */
+ GPIOC_DBC_CLK_SRC_SYSCLK = SYSCTRL_GPIOC_DBCCLK_SRC_SYSCLK, /*!< GPIOC DBC CLK Source SYSCLK */
+ GPIOC_DBC_CLK_SRC_RC32K = SYSCTRL_GPIOC_DBCCLK_SRC_RC32K, /*!< GPIOC DBC CLK Source RC32K */
+} SYSCTRL_GPIOCDbcClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL GPIOD Debounce Clock Source Definition
+ */
+typedef enum {
+ GPIOD_DBC_CLK_SRC_RC8M = SYSCTRL_GPIOD_DBCCLK_SRC_RC8M, /*!< GPIOD DBC CLK Source RC8M */
+ GPIOD_DBC_CLK_SRC_XOSC = SYSCTRL_GPIOD_DBCCLK_SRC_XOSC, /*!< GPIOD DBC CLK Source XOSC */
+ GPIOD_DBC_CLK_SRC_SYSCLK = SYSCTRL_GPIOD_DBCCLK_SRC_SYSCLK, /*!< GPIOD DBC CLK Source SYSCLK */
+ GPIOD_DBC_CLK_SRC_RC32K = SYSCTRL_GPIOD_DBCCLK_SRC_RC32K, /*!< GPIOD DBC CLK Source RC32K */
+} SYSCTRL_GPIODDbcClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL Dflash Clock Source Definition
+ */
+typedef enum {
+ DFLASH_CLK_SRC_RC8M = SYSCTRL_DFLASH_MEMCLK_SRC_RC8M, /*!< Dflash CLK Source RC8M */
+ DFLASH_CLK_SRC_PLL0DivClk = SYSCTRL_DFLASH_MEMCLK_SRC_PLL0DivClk, /*!< Dflash CLK Source PLL0 Div Clk */
+ DFLASH_CLK_SRC_PLL1DivClk = SYSCTRL_DFLASH_MEMCLK_SRC_PLL1DivClk, /*!< Dflash CLK Source PLL1 Div Clk */
+ DFLASH_CLK_SRC_PLL2DivClk = SYSCTRL_DFLASH_MEMCLK_SRC_PLL2DivClk, /*!< Dflash CLK Source PLL2 Div Clk */
+} SYSCTRL_DflashClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL Eflash Clock Source Definition
+ */
+typedef enum {
+ EFLASH_CLK_SRC_RC8M = SYSCTRL_EFLASH_MEMCLK_SRC_RC8M, /*!< Eflash CLK Source RC8M */
+ EFLASH_CLK_SRC_PLL0DivClk = SYSCTRL_EFLASH_MEMCLK_SRC_PLL0DivClk, /*!< Eflash CLK Source PLL0 Div Clk */
+ EFLASH_CLK_SRC_PLL1DivClk = SYSCTRL_EFLASH_MEMCLK_SRC_PLL1DivClk, /*!< Eflash CLK Source PLL1 Div Clk */
+ EFLASH_CLK_SRC_PLL2DivClk = SYSCTRL_EFLASH_MEMCLK_SRC_PLL2DivClk, /*!< Eflash CLK Source PLL2 Div Clk */
+} SYSCTRL_EflashClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL ADC Function Clock Source Definition
+ */
+typedef enum {
+ ADC_FUNC_CLK_SRC_RC8M = SYSCTRL_ADC_FUNCLK_SRC_RC8M, /*!< ADC Function CLK Source RC8M */
+ ADC_FUNC_CLK_SRC_HOSC = SYSCTRL_ADC_FUNCLK_SRC_HOSC, /*!< ADC Function CLK Source HOSC */
+ ADC_FUNC_CLK_SRC_PLL0 = SYSCTRL_ADC_FUNCLK_SRC_PLL0, /*!< ADC Function CLK Source PLL0 */
+ ADC_FUNC_CLK_SRC_PLL1 = SYSCTRL_ADC_FUNCLK_SRC_PLL1, /*!< ADC Function CLK Source PLL1 */
+} SYSCTRL_ADCFuncClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL HRPWM Function Clock Source Definition
+ */
+typedef enum {
+ HRPWM_FUNC_CLK_SRC_RC8M = SYSCTRL_HRPWM_FUNCLK_SRC_RC8M, /*!< HRPWM Function CLK Source RC8M */
+ HRPWM_FUNC_CLK_SRC_HOSC = SYSCTRL_HRPWM_FUNCLK_SRC_HOSC, /*!< HRPWM Function CLK Source HOSC */
+ HRPWM_FUNC_CLK_SRC_PLL0 = SYSCTRL_HRPWM_FUNCLK_SRC_PLL0, /*!< HRPWM Function CLK Source PLL0 */
+ HRPWM_FUNC_CLK_SRC_PLL1 = SYSCTRL_HRPWM_FUNCLK_SRC_PLL1, /*!< HRPWM Function CLK Source PLL1 */
+} SYSCTRL_HRPWMFuncClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL PLLCLK Source Definition
+ */
+typedef enum {
+ PLLCLK_SRC_XOSC = 0, /*!< PLLCLK Source XOSC */
+ PLLCLK_SRC_RC8M = 1, /*!< PLLCLK Source RC8M */
+ PLLCLK_SRC_DFT = 3, /*!< PLLCLK Source DFT */
+} SYSCTRL_PllClkSrcETypeDef;
+
+/**
+ * @brief SYSCTRL SYSCLK Config Definition
+ */
+typedef struct __SYSCTRL_SysclkUserCfgTypeDef {
+ SYSCTRL_SysclkSrcETypeDef sysclk_src; /*!< SYSCLK Source */
+ SYSCTRL_PllClkSrcETypeDef pll0clk_src; /*!< PLLCLK Source */
+ uint32_t sysclk_src_freq; /*!< SYSCLK Source Freq */
+ uint32_t pll0clk_src_freq; /*!< PLLCLK Source Freq */
+ uint32_t sysclk_freq; /*!< SYSCLK Freq */
+ SYSCTRL_ClkDivETypeDef apb0_clk_div; /*!< APB0 clock Div */
+ SYSCTRL_ClkDivETypeDef apb1_clk_div; /*!< APB1 clock Div */
+} SYSCTRL_SysclkUserCfgTypeDef;
+
+/**
+ * @brief SYSCTRL PLL1/2 Config Definition
+ */
+typedef struct __SYSCTRL_PLLUserCfgTypeDef {
+ SYSCTRL_PllClkSrcETypeDef pll_clk_src; /*!< PLLCLK Source */
+ uint32_t pll_in_freq; /*!< PLLCLK Input Freq */
+ uint32_t pll_user_freq; /*!< PLLCLK User Freq */
+} SYSCTRL_PLLUserCfgTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSCTRL_LL_Exported_Functions SYSCTRL LL Exported Functions
+ * @brief SYSCTRL LL Exported Functions
+ * @{
+ */
+
+/** @addtogroup SYSCTRL_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_SYSCTRL_SysclkInit(SYSCTRL_TypeDef *Instance, SYSCTRL_SysclkUserCfgTypeDef *sysclk_cfg);
+LL_StatusETypeDef LL_SYSCTRL_GPIOA_DbcClkCfg(SYSCTRL_GPIOADbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+LL_StatusETypeDef LL_SYSCTRL_GPIOB_DbcClkCfg(SYSCTRL_GPIOBDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+LL_StatusETypeDef LL_SYSCTRL_GPIOC_DbcClkCfg(SYSCTRL_GPIOCDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+LL_StatusETypeDef LL_SYSCTRL_GPIOD_DbcClkCfg(SYSCTRL_GPIODDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+LL_StatusETypeDef LL_SYSCTRL_DFLASH_ClkCfg(SYSCTRL_DflashClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+LL_StatusETypeDef LL_SYSCTRL_EFLASH_ClkCfg(SYSCTRL_EflashClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+LL_StatusETypeDef LL_SYSCTRL_ADC_FuncClkCfg(SYSCTRL_ADCFuncClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+LL_StatusETypeDef LL_SYSCTRL_HRPWM_FuncClkCfg(SYSCTRL_HRPWMFuncClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div);
+uint32_t LL_SYSCTRL_SysclkGet(void);
+uint32_t LL_SYSCTRL_AHBClkGet(void);
+uint32_t LL_SYSCTRL_APB0ClkGet(void);
+uint32_t LL_SYSCTRL_APB1ClkGet(void);
+/**
+ * @}
+ */
+
+
+/** @addtogroup SYSCTRL_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_SYSCTRL_Pll0Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll0_cfg);
+LL_StatusETypeDef LL_SYSCTRL_Pll1Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll1_cfg);
+LL_StatusETypeDef LL_SYSCTRL_Pll2Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll2_cfg);
+/**
+ * @}
+ */
+
+
+/** @addtogroup SYSCTRL_LL_Exported_Functions_Group3
+ * @{
+ */
+void LL_SYSCTRL_LSTMR_ClkEnRstRelease(void);
+void LL_SYSCTRL_LSTMR_ClkDisRstAssert(void);
+void LL_SYSCTRL_UART1_ClkEnRstRelease(void);
+void LL_SYSCTRL_UART1_ClkDisRstAssert(void);
+void LL_SYSCTRL_UART0_ClkEnRstRelease(void);
+void LL_SYSCTRL_UART0_ClkDisRstAssert(void);
+void LL_SYSCTRL_I2C1_ClkEnRstRelease(void);
+void LL_SYSCTRL_I2C1_ClkDisRstAssert(void);
+void LL_SYSCTRL_I2C0_ClkEnRstRelease(void);
+void LL_SYSCTRL_I2C0_ClkDisRstAssert(void);
+void LL_SYSCTRL_ECU_ClkEnRstRelease(void);
+void LL_SYSCTRL_ECU_ClkDisRstAssert(void);
+void LL_SYSCTRL_IIR4_ClkEnRstRelease(void);
+void LL_SYSCTRL_IIR4_ClkDisRstAssert(void);
+void LL_SYSCTRL_IIR3_ClkEnRstRelease(void);
+void LL_SYSCTRL_IIR3_ClkDisRstAssert(void);
+void LL_SYSCTRL_IIR2_ClkEnRstRelease(void);
+void LL_SYSCTRL_IIR2_ClkDisRstAssert(void);
+void LL_SYSCTRL_IIR1_ClkEnRstRelease(void);
+void LL_SYSCTRL_IIR1_ClkDisRstAssert(void);
+void LL_SYSCTRL_IIR0_ClkEnRstRelease(void);
+void LL_SYSCTRL_IIR0_ClkDisRstAssert(void);
+void LL_SYSCTRL_DALI_ClkEnRstRelease(void);
+void LL_SYSCTRL_DALI_ClkDisRstAssert(void);
+void LL_SYSCTRL_FPLL2_RstRelease(void);
+void LL_SYSCTRL_FPLL2_RstAssert(void);
+void LL_SYSCTRL_FPLL1_RstRelease(void);
+void LL_SYSCTRL_FPLL1_RstAssert(void);
+void LL_SYSCTRL_FPLL0_RstRelease(void);
+void LL_SYSCTRL_FPLL0_RstAssert(void);
+void LL_SYSCTRL_USB_ClkEnRstRelease(void);
+void LL_SYSCTRL_USB_ClkDisRstAssert(void);
+void LL_SYSCTRL_DFLASH_ClkEnRstRelease(void);
+void LL_SYSCTRL_DFLASH_ClkDisRstAssert(void);
+void LL_SYSCTRL_EFLASH_ClkEnRstRelease(void);
+void LL_SYSCTRL_EFLASH_ClkDisRstAssert(void);
+void LL_SYSCTRL_HRPWM_ClkEnRstRelease(void);
+void LL_SYSCTRL_HRPWM_ClkDisRstAssert(void);
+void LL_SYSCTRL_ADC_ClkEnRstRelease(void);
+void LL_SYSCTRL_ADC_ClkDisRstAssert(void);
+void LL_SYSCTRL_DAC_ClkEnRstRelease(void);
+void LL_SYSCTRL_DAC_ClkDisRstAssert(void);
+void LL_SYSCTRL_CMP_ClkEnRstRelease(void);
+void LL_SYSCTRL_CMP_ClkDisRstAssert(void);
+void LL_SYSCTRL_GPIOD_ClkEnRstRelease(void);
+void LL_SYSCTRL_GPIOD_ClkDisRstAssert(void);
+void LL_SYSCTRL_GPIOC_ClkEnRstRelease(void);
+void LL_SYSCTRL_GPIOC_ClkDisRstAssert(void);
+void LL_SYSCTRL_GPIOB_ClkEnRstRelease(void);
+void LL_SYSCTRL_GPIOB_ClkDisRstAssert(void);
+void LL_SYSCTRL_GPIOA_ClkEnRstRelease(void);
+void LL_SYSCTRL_GPIOA_ClkDisRstAssert(void);
+void LL_SYSCTRL_HSTMR_ClkEnRstRelease(void);
+void LL_SYSCTRL_HSTMR_ClkDisRstAssert(void);
+void LL_SYSCTRL_CAN_ClkEnRstRelease(void);
+void LL_SYSCTRL_CAN_ClkDisRstAssert(void);
+void LL_SYSCTRL_DMA_ClkEnRstRelease(void);
+void LL_SYSCTRL_DMA_ClkDisRstAssert(void);
+
+void LL_SYSCTRL_AllPeriphRstAssert(void);
+void LL_SYSCTRL_AllPeriphRstRelease(void);
+/**
+ * @}
+ */
+
+
+/** @addtogroup SYSCTRL_LL_Exported_Functions_Group4
+ * @{
+ */
+void LL_SYSCTRL_PMUCfg(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_SYSCTRL_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_tmr.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_tmr.h
new file mode 100644
index 0000000000..00aea7fab3
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_tmr.h
@@ -0,0 +1,847 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_tmr.h
+ * @author MCD Application Team
+ * @brief Header for TMR LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_TMR_H_
+#define _TAE32F53XX_LL_TMR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup TMR_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TMR_LL_Exported_Types TMR LL Exported Types
+ * @brief TMR LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief TMR Continuous Mode
+ */
+typedef enum {
+ TMR_CONTINUOUS_MODE_ENABLE = 0x00000000U, /*!< TMR performed in Continuous counting mode */
+ TMR_CONTINUOUS_MODE_DISABLE = TMR_CR_MS, /*!< TMR performed in Single counting mode */
+} TMR_ContinuousETypeDef;
+
+/**
+ * @brief TMR Update Event Enable
+ */
+typedef enum {
+ TMR_UPDATE_ENABLE = 0x00000000U, /*!< Update event generation enabled */
+ TMR_UPDATE_DISABLE = TMR_CR_UDIS, /*!< Update event generation disabled */
+} TMR_UpdateETypeDef;
+
+/**
+ * @brief TMR_Update_Request_Source TMR Update Request Source
+ */
+typedef enum {
+ TMR_UPDATE_SOURCE_REGULAR = 0x00000000U, /*!< Counter overflow or Setting the UG bit generates an update request */
+ TMR_UPDATE_SOURCE_COUNTER = TMR_CR_URS, /*!< Only counter overflow generates an update request */
+} TMR_UpdateSrcETypeDef;
+
+/**
+ * @brief TMR Auto-Reload Preload
+ */
+typedef enum {
+ TMR_AUTORELOAD_PRELOAD_DISABLE = 0x00000000U, /*!< Disable auto-reload preload feature */
+ TMR_AUTORELOAD_PRELOAD_ENABLE = TMR_CR_ARPE, /*!< Enable auto-reload preload feature */
+} TMR_AutoReloadETypeDef;
+
+/**
+ * @brief TMR Clock Souce
+ */
+typedef enum {
+ TMR_CLKSOURCE_INTERNAL = TMR_CR_CKSRC_0, /*!< Internal clock source */
+ TMR_CLKSOURCE_ETR_RISING = TMR_CR_CKSRC_1, /*!< External clock source rising edge */
+ TMR_CLKSOURCE_ETR_FALLING = TMR_CR_CKSRC_2, /*!< External clock source falling edge */
+ TMR_CLKSOURCE_ETR_BOTHEDGE = TMR_CR_CKSRC_3, /*!< External clock source both rising and falling edge */
+} TMR_ClkSrcETypeDef;
+
+/**
+ * @brief TMR PWM Wave Export
+ */
+typedef enum {
+ TMR_EXT_PWM_WAVE_DISABLE = 0x00000000U, /*!< Disable the export of the PWM Wave */
+ TMR_EXT_PWM_WAVE_ENABLE = TMR_ETER_PWMOE, /*!< Enable the export of the PWM Wave */
+} TMR_Ext_PWMETypeDef;
+
+/**
+ * @brief TMR Capture Compare Event Trigger Export
+ */
+typedef enum {
+ TMR_EXT_CC_TRIGGER_DISABLE = 0x00000000U, /*!< Disable the export of the Capture Compare Trigger */
+ TMR_EXT_CC_TRIGGER_ENABLE = TMR_ETER_CCTE, /*!< Enable the export of the Capture Compare Trigger */
+} TMR_Ext_CCETypeDef;
+
+/**
+ * @brief TMR TRGO Trigger Export
+ */
+typedef enum {
+ TMR_EXT_TRGO_TRIGGER_DISABLE = 0x00000000U, /*!< Disable the export of the TRGO signal (source from Update Event) Trigger */
+ TMR_EXT_TRGO_TRIGGER_ENABLE = TMR_ETER_UTE, /*!< Enable the export of the TRGO signal (source from Update Event) Trigger */
+} TMR_Ext_TRGOETypeDef;
+
+/**
+ * @brief TMR Event Source
+ */
+typedef enum {
+ TMR_EVENTSOURCE_UG = TMR_EGR_UG, /*!< Reinitialize the counter and generates an update of the registers */
+ TMR_EVENTSOURCE_CCG = TMR_EGR_CCG, /*!< A capture/compare event is generated */
+} TMR_EventSRCETypeDef;
+
+/** @brief TMR Input Capture Selection
+ */
+typedef enum {
+ TMR_ICSELECTION_TMR0 = TMR_CCCR_ICSRS_0, /*!< TMR input capture source TMR0 io (specific to (LS)TMR0/1/2/3). */
+ TMR_ICSELECTION_TMR4 = TMR_CCCR_ICSRS_0, /*!< TMR input capture source TMR4 io (specific to (HS)TMR4/5/6/7). */
+
+ TMR_ICSELECTION_TMR1 = TMR_CCCR_ICSRS_1, /*!< TMR input capture source TMR1 io (specific to (LS)TMR0/1/2/3). */
+ TMR_ICSELECTION_TMR5 = TMR_CCCR_ICSRS_1, /*!< TMR input capture source TMR5 io (specific to (HS)TMR4/5/6/7). */
+
+ TMR_ICSELECTION_TMR2 = TMR_CCCR_ICSRS_2, /*!< TMR input capture source TMR2 io (specific to (LS)TMR0/1/2/3). */
+ TMR_ICSELECTION_TMR6 = TMR_CCCR_ICSRS_2, /*!< TMR input capture source TMR6 io (specific to (HS)TMR4/5/6/7). */
+
+ TMR_ICSELECTION_TMR3 = TMR_CCCR_ICSRS_3, /*!< TMR input capture source TMR3 io (specific to (LS)TMR0/1/2/3). */
+ TMR_ICSELECTION_TMR7 = TMR_CCCR_ICSRS_3, /*!< TMR input capture source TMR7 io (specific to (HS)TMR4/5/6/7). */
+
+ TMR_ICSELECTION_CMP0 = TMR_CCCR_ICSRS_4, /*!< The internal CMP0 output single
+ will be selected as the input source of LSTMR or HSTMR */
+
+ TMR_ICSELECTION_CMP1 = TMR_CCCR_ICSRS_5, /*!< The internal CMP1 output single
+ will be selected as the input source of LSTMR or HSTMR */
+
+ TMR_ICSELECTION_CMP2 = TMR_CCCR_ICSRS_6, /*!< The internal CMP2 output single
+ will be selected as the input source of LSTMR or HSTMR */
+
+ TMR_ICSELECTION_CMP3 = TMR_CCCR_ICSRS_7, /*!< The internal CMP3 output single
+ will be selected as the input source of LSTMR or HSTMR */
+} TMR_ICSelETypeDef;
+
+/**
+ * @brief TMR Input Capture Polarity
+ */
+typedef enum {
+ TMR_ICPOLARITY_RISING = 0x00000000U, /*!< Capture triggered by rising edge on timer input */
+ TMR_ICPOLARITY_FALLING = TMR_CCCR_CCP_0, /*!< Capture triggered by falling edge on timer input */
+ TMR_ICPOLARITY_BOTHEDGE = TMR_CCCR_CCP_1, /*!< Capture triggered by both rising and falling edges on timer input */
+} TMR_ICPolarityETypeDef;
+
+/**
+ * @brief TMR Output Compare and PWM Modes
+ */
+typedef enum {
+ TMR_OCMODE_FROZEN = TMR_CCCR_OCM_0, /*!< Frozen */
+ TMR_OCMODE_ACTIVE = TMR_CCCR_OCM_1, /*!< active on match */
+ TMR_OCMODE_INACTIVE = TMR_CCCR_OCM_2, /*!< inactive on match */
+ TMR_OCMODE_TOGGLE = TMR_CCCR_OCM_3, /*!< Toggle */
+ TMR_OCMODE_FORCED_INACTIVE = TMR_CCCR_OCM_4, /*!< Force inactive */
+ TMR_OCMODE_FORCED_ACTIVE = TMR_CCCR_OCM_5, /*!< Force active */
+ TMR_OCMODE_PWM1 = TMR_CCCR_OCM_6, /*!< PWM mode 1 */
+ TMR_OCMODE_PWM2 = TMR_CCCR_OCM_7, /*!< PWM mode 2 */
+} TMR_OCModeETypeDef;
+
+/**
+ * @brief TMR_OCPreload_Enable TMR OCPreload Enable
+ */
+typedef enum {
+ TMR_OCPRELOAD_DISABLE = 0x00000000U, /*!< TMR OCPreload Disable */
+ TMR_OCPRELOAD_ENABLE = TMR_CCCR_OCPE, /*!< TMR OCPreload Enable */
+} TMR_OCPreloadETypeDef;
+
+/**
+ * @brief TMR Complementary Output Compare Polarity
+ */
+typedef enum {
+ TMR_OCPOLARITY_HIGH = 0x00000000U, /*!< Output Compare polarity active high */
+ TMR_OCPOLARITY_LOW = TMR_CCCR_CCP_0, /*!< Output Compare polarity active low */
+} TMR_OCPolarityETypeDef;
+
+/**
+ * @brief Timer Base Unit Initialization Structure definition
+ * @note Please notice that TMR can enable either Input Capture mode or Output Compare mode.
+ */
+typedef struct __TMR_TB_InitTypeDef {
+ TMR_ClkSrcETypeDef ClockSource; /*!< Specifies the Clock Source. */
+
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TMR clock.
+ This parameter can be a number in range of:
+ For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF
+ For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */
+
+ uint32_t StartValue; /*!< Specifies the timer counter start value.
+ This parameter can be a number in range of:
+ For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF
+ For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */
+
+ uint32_t EndValue; /*!< Specifies the timer counter end value.
+ This parameter can be a number in range of:
+ For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF
+ For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */
+
+ TMR_ContinuousETypeDef ContinuousMode; /*!< Specifies the timer continuous mode enable or disable. */
+
+ TMR_AutoReloadETypeDef AutoReloadPreload; /*!< Specifies the auto-reload preload. */
+
+ TMR_UpdateETypeDef UpdateEnable; /*!< Specifies the Update event enable or not. */
+
+ TMR_UpdateSrcETypeDef UpdateSource; /*!< Specifies the Update request Source */
+} TMR_TB_InitTypeDef;
+
+/**
+ * @brief Timer Input Capture Initialization Structure definition
+ * @note Please notice that TMR can enable either Input Capture mode or Output Compare mode.
+ */
+typedef struct __TMR_IC_InitTypeDef {
+ LL_FuncStatusETypeDef ICEnable; /*!< Specifies enable the Input Capture feature or not.
+ This parameter can be ENABLE or DISABLE */
+
+ TMR_ICPolarityETypeDef ICPolarity; /*!< Specifies the active edge of the input signal. */
+
+ TMR_ICSelETypeDef ICSelection; /*!< Specifies the input source to be used. */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xFF */
+} TMR_IC_InitTypeDef;
+
+/**
+ * @brief Timer Output Compare Initialization Structure definition
+ * @note Please notice that TMR can enable either Input Capture mode or Output Compare mode.
+ */
+typedef struct __TMR_OC_InitTypeDef {
+ LL_FuncStatusETypeDef OCEnable; /*!< Specifies enable the Output Compare feature or not.
+ This parameter can be ENABLE or DISABLE */
+
+ TMR_OCPolarityETypeDef OCPolarity; /*!< Specifies the output polarity. */
+
+ TMR_OCPreloadETypeDef OCPreload; /*!< Timer Output Compare Preload Enable */
+
+ TMR_OCModeETypeDef OCMode; /*!< Specifies the TMR mode. */
+
+ uint32_t OCValue; /*!< Specifies the compare value which loaded into Capture Compare Register.
+ This parameter can be a number in range of:
+ For low-speed timer(TMR0/1/2/3): from Min 0x0 to Max 0x0000FFFF
+ For high-speed timer(TMR4/5/6/7): from Min 0x0 to Max 0xFFFFFFFF */
+} TMR_OC_InitTypeDef;
+
+/**
+ * @brief Timer Export Trigger Initialization Structure definition
+ */
+typedef struct __TMR_EXT_InitTypeDef {
+ LL_FuncStatusETypeDef ExtEnable; /*!< Specifies enable the Export Event Trigger feature or not.
+ This parameter can be ENABLE or DISABLE */
+
+ TMR_Ext_PWMETypeDef ExtPWMWave; /*!< Specifies PWM Wave (output compare) export to internal signal or not. */
+
+ TMR_Ext_CCETypeDef ExtCCTrigger; /*!< Specifies Capture Compare Trigger Event export to internal signal or not. */
+
+ TMR_Ext_TRGOETypeDef ExtTRGOTrigger;/*!< Specifies TMR TRGO signal (source from Update Event) export to internal signal or not. */
+} TMR_EXT_InitTypeDef;
+
+/**
+ * @brief Timer Initialization Structure definition
+ * @note Please notice that TMR can be configured to either Input Capture mode or Output Compare mode.
+ * Witch means that either ICEnable or OCEnable in the Initialization Structure can be enable the feature.
+ */
+typedef struct __TMR_InitTypeDef {
+ TMR_TB_InitTypeDef TBInit; /*!< Timer Base Unit Initialization Structure definition */
+
+ TMR_IC_InitTypeDef ICInit; /*!< Timer Input Capture Initialization Structure definition */
+
+ TMR_OC_InitTypeDef OCInit; /*!< Timer Output Compare Initialization Structure */
+
+ TMR_EXT_InitTypeDef ExtInit; /*!< Timer Export Event Trigger feature Initialization Structure */
+} TMR_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TMR_LL_Exported_Constants TMR LL Exported Constants
+ * @brief TMR LL Exported Constants
+ * @{
+ */
+
+/** @defgroup TMR_Interrupt_definition TMR Interrupt Definition
+ * @{
+ */
+#define TMR_IT_UIE TMR_CR_UIE /*!< Update interrupt */
+#define TMR_IT_OVIE TMR_CR_OVIE /*!< Counter Overflow interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup TMR_CC_Interrupt_definition TMR Capture/Compare Interrupt Definition
+ * @{
+ */
+#define TMR_IT_ICIE TMR_CCCR_ICIE /*!< Input Capture interrupt */
+#define TMR_IT_ICOIE TMR_CCCR_ICOIE /*!< Input Capture OverCapture interrupt */
+#define TMR_IT_OCIE TMR_CCCR_OCIE /*!< Output Compare Match interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup TMR_Flag_definition TMR Flag Definition
+ * @{
+ */
+#define TMR_FLAG_OVIF TMR_ISR_OVIF /*!< Timer Counter Overflow Interrupt Flag */
+#define TMR_FLAG_ICOIF TMR_ISR_ICOIF /*!< Timer Input Capture OverCapture Interrupt Flag */
+#define TMR_FLAG_ICIF TMR_ISR_ICIF /*!< Timer Input Capture Interrupt Flag */
+#define TMR_FLAG_OCIF TMR_ISR_OCIF /*!< Timer Output Compare Interrupt Flag */
+#define TMR_FLAG_UIF TMR_ISR_UIF /*!< Timer Counter Update Interrupt Flag */
+/**
+ * @}
+ */
+
+/** @defgroup TMR_Sync_definition Timer Group synchronization Definition
+ * @{
+ */
+#define TMRGRP_SYNC_TMR0 TMRGRP_SYNC0EN /*!< Select TMR0(specific to TMRGRP0) */
+#define TMRGRP_SYNC_TMR4 TMRGRP_SYNC0EN /*!< Select TMR4(specific to TMRGRP1) */
+
+#define TMRGRP_SYNC_TMR1 TMRGRP_SYNC1EN /*!< Select TMR1(specific to TMRGRP0) */
+#define TMRGRP_SYNC_TMR5 TMRGRP_SYNC1EN /*!< Select TMR5(specific to TMRGRP1) */
+
+#define TMRGRP_SYNC_TMR2 TMRGRP_SYNC2EN /*!< Select TMR2(specific to TMRGRP0) */
+#define TMRGRP_SYNC_TMR6 TMRGRP_SYNC2EN /*!< Select TMR6(specific to TMRGRP1) */
+
+#define TMRGRP_SYNC_TMR3 TMRGRP_SYNC3EN /*!< Select TMR2(specific to TMRGRP0) */
+#define TMRGRP_SYNC_TMR7 TMRGRP_SYNC3EN /*!< Select TMR6(specific to TMRGRP1) */
+
+#define TMRGRP_SYNC_ALL TMRGRP_SYNCALLEN /*!< Select all TMRs in TMRGRPx(x = 0 or 1) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TMR_LL_Exported_Macros TMR LL Exported Macros
+ * @brief TMR LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable TMR Base Unit on runtime
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, TMR_CR_CEN)
+
+/**
+ * @brief Disable TMR Base Unit on runtime
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, TMR_CR_CEN)
+
+/**
+ * @brief Enable TMR Capture/Compare feature on runtime
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_CC_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CCCR, TMR_CCCR_CCE)
+
+/**
+ * @brief Disable TMR Capture/Compare feature on runtime
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_CC_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CCCR, TMR_CCCR_CCE)
+
+
+/**
+ * @brief Enable the specified TMR Basic Unit Interrupt
+ * @param __INSTANCE__ TMR peripheral
+ * @param __INTERRUPT__ specifies the TMR base unit interrupt source to enable.
+ * This parameter can be any combination of @ref TMR_Interrupt_definition:
+ * @arg TMR_IT_UIE: Update interrupt
+ * @arg TMR_IT_OVIE: Counter Overflow interrupt
+ * @return None
+ */
+#define __LL_TMR_IT_ENABLE(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CR, (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified TMR Basic Unit Interrupt
+ * @param __INSTANCE__ TMR peripheral
+ * @param __INTERRUPT__ specifies the TMR base unit interrupt source to disable.
+ * This parameter can be any combination of @ref TMR_Interrupt_definition:
+ * @arg TMR_IT_UIE: Update interrupt
+ * @arg TMR_IT_OVIE: Counter Overflow interrupt
+ * @return None
+ */
+#define __LL_TMR_IT_DISABLE(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CR, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified TMR Basic Unit interrupt source is set or not.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __INTERRUPT__ specifies the TMR interrupt source to check.
+ * This parameter can be any combination of @ref TMR_Interrupt_definition:
+ * @arg TMR_IT_UIE: Update interrupt
+ * @arg TMR_IT_OVIE: Counter Overflow interrupt
+ * @return The state of __INTERRUPT__ (SET or RESET).
+ */
+#define __LL_TMR_IT_CHECK_SOURCE(__INSTANCE__, __INTERRUPT__) ((READ_BIT((__INSTANCE__)->CR, (__INTERRUPT__)) \
+ == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Enable the specified Capture/Compare Interrupt
+ * @param __INSTANCE__ TMR peripheral
+ * @param __INTERRUPT__ specifies the TMR Capture/Compare interrupt source to enable.
+ * This parameter can be any combination of @ref TMR_CC_Interrupt_definition:
+ * @arg TMR_IT_ICIE: Input Capture interrupt
+ * @arg TMR_IT_ICOIE: Input Capture OverCapture interrupt
+ * @arg TMR_IT_OCIE: Output Compare Match interrupt
+ * @return None
+ */
+#define __LL_TMR_CC_IT_ENABLE(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CCCR, (__INTERRUPT__))
+
+/**
+ * @brief Disable Input Capture Interrupt
+ * @param __INSTANCE__ TMR peripheral
+ * @param __INTERRUPT__ specifies the TMR Capture/Compare interrupt source to disable.
+ * This parameter can be any combination of @ref TMR_CC_Interrupt_definition:
+ * @arg TMR_IT_ICIE: Input Capture interrupt
+ * @arg TMR_IT_ICOIE: Input Capture OverCapture interrupt
+ * @arg TMR_IT_OCIE: Output Compare Matched interrupt
+ * @return None
+ */
+#define __LL_TMR_CC_IT_DISABLE(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CCCR, (__INTERRUPT__))
+
+
+/**
+ * @brief Check whether the specified TMR Capture/Compare interrupt source is set or not.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __INTERRUPT__ specifies the TMR Capture/Compare interrupt source to check.
+ * This parameter can be any combination of @ref TMR_CC_Interrupt_definition:
+ * @arg TMR_IT_ICIE: Input Capture interrupt
+ * @arg TMR_IT_ICOIE: Input Capture OverCapture interrupt
+ * @arg TMR_IT_OCIE: Output Compare Matched interrupt
+ * @return he state of __INTERRUPT__ (SET or RESET).
+ */
+#define __LL_TMR_CC_IT_CHECK_SOURCE(__INSTANCE__, __INTERRUPT__) \
+ ((READ_BIT((__INSTANCE__)->CCCR, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified TMR interrupt flag is set or not.
+ * @param __INSTANCE__ TMR peripheral.
+ * @param __FLAG__ specifies the TMR flags to check.
+ * This parameter can be any combination of @ref TMR_Flag_definition:
+ * @arg TMR_FLAG_OVIF: Counter Overflow Interrupt Flag
+ * @arg TMR_FLAG_ICOIF: Input Capture OverCapture Interrupt Flag
+ * @arg TMR_FLAG_ICIF: Input Capture Interrupt Flag
+ * @arg TMR_FLAG_OCIF: Output Compare Interrupt Flag
+ * @arg TMR_FLAG_UIF: Counter Update Interrupt Flag
+ * @return The state of __FLAG__ (SET or RESET).
+ */
+#define __LL_TMR_GET_FLAG(__INSTANCE__, __FLAG__) \
+ ((READ_BIT((__INSTANCE__)->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the specified TMR interrupt flags
+ * @param __INSTANCE__ TMR peripheral
+ * @param __FLAG__ specifies the TMR flags to clear.
+ * This parameter can be any combination of @ref TMR_Flag_definition:
+ * @arg TMR_FLAG_OVIF: Counter Overflow Interrupt Flag
+ * @arg TMR_FLAG_ICOIF: Input Capture OverCapture Interrupt Flag
+ * @arg TMR_FLAG_ICIF: Input Capture Interrupt Flag
+ * @arg TMR_FLAG_OCIF: Output Compare Interrupt Flag
+ * @arg TMR_FLAG_UIF: Counter Update Interrupt Flag
+ * @return None
+ */
+#define __LL_TMR_CLEAR_FLAG(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->ISR, (__FLAG__))
+
+/**
+ * @brief Enable TMR Auto-Reload feature
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_AUTORELOAD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, TMR_CR_ARPE)
+
+/**
+ * @brief Disable TMR Auto-Reload feature
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_AUTORELOAD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, TMR_CR_ARPE)
+
+/**
+ * @brief Enable TMR Output Compare Preload feature
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_OC_PRELOAD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CCCR, TMR_CCCR_OCPE)
+
+/**
+ * @brief Disable TMR Output Compare Preload feature
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_OC_PRELOAD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CCCR, TMR_CCCR_OCPE)
+
+/**
+ * @brief Enable TMR Update event (UDIS)
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_UPDATE_ENABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, TMR_CR_UDIS)
+
+/**
+ * @brief Disable TMR Update event (UDIS)
+ * @param __INSTANCE__ TMR peripheral
+ * @return None
+ */
+#define __LL_TMR_UPDATE_DISABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, TMR_CR_UDIS)
+
+/**
+ * @brief Selection of the Update Request Source (URS) bit of the TMRx_CR register.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __SOURCE__ specifies the Update Request Source
+ * This parameter can be one of the following values in @ref TMR_Update_Request_Source:
+ * @arg TMR_UPDATE_SOURCE_REGULAR: Counter overflow or Setting the UG bit generates an update request
+ * @arg TMR_UPDATE_SOURCE_COUNTER: Only counter overflow generates an update request
+ * @note To generate the update request, Update event should be enabled(reset UDIS bit in TMRx_CR register).
+ * @return None
+ */
+#define __LL_TMR_UPDATE_SOURCE(__INSTANCE__, __SOURCE__) MODIFY_REG((__INSTANCE__)->CR, TMR_CR_URS_Msk, (__SOURCE__))
+
+/**
+ * @brief Set the TMR Prescaler on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __PRESC__ specifies the Prescaler new value.
+ * @retval None
+ */
+#define __LL_TMR_SET_PRESCALER(__INSTANCE__, __PRESC__) WRITE_REG((__INSTANCE__)->PSCR, (__PRESC__))
+
+/**
+ * @brief Get the TMR Prescaler on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @retval 16-bit or 32-bit value of the timer prescaler register (TMRx_PSCR)
+ */
+#define __LL_TMR_GET_PRESCALER(__INSTANCE__) READ_REG((__INSTANCE__)->PSCR)
+
+/**
+ * @brief Set the TMR Start value on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __START__ specifies the new starting value.
+ * @retval None
+ */
+#define __LL_TMR_SET_START_VAL(__INSTANCE__, __START__) WRITE_REG((__INSTANCE__)->CSVR, (__START__))
+
+/**
+ * @brief Get the TMR Start value on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @retval 16-bit or 32-bit value of the timer start value register (TMRx_CSVR)
+ */
+#define __LL_TMR_GET_START_VAL(__INSTANCE__) READ_REG((__INSTANCE__)->CSVR)
+
+/**
+ * @brief Set the TMR End value on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __END__ specifies the new ending value.
+ * @retval None
+ */
+#define __LL_TMR_SET_END_VAL(__INSTANCE__, __END__) WRITE_REG((__INSTANCE__)->CEVR, (__END__))
+
+/**
+ * @brief Get the TMR End value on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @retval 16-bit or 32-bit value of the timer end value register (TMRx_CEVR)
+ */
+#define __LL_TMR_GET_END_VAL(__INSTANCE__) READ_REG((__INSTANCE__)->CEVR)
+
+/**
+ * @brief Set the TMR Counter Register value on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __COUNTER__ specifies the Counter register new value.
+ * @return None
+ */
+#define __LL_TMR_SET_COUNTER(__INSTANCE__, __COUNTER__) WRITE_REG((__INSTANCE__)->CNTR, (__COUNTER__))
+
+/**
+ * @brief Get the TMR Counter Register value on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @return 16-bit or 32-bit value of the timer counter register (TMRx_CNTR)
+ */
+#define __LL_TMR_GET_COUNTER(__INSTANCE__) READ_REG((__INSTANCE__)->CNTR)
+
+/**
+ * @brief Set the TMR Capture Compare Register(TMRx_CCR) value on runtime.
+ * @note This macro normally used when the TMR is configured in Output Compare mode.
+ * User can use the macro to change the compare value on runtime without calling
+ * another time Config function.
+ * @note The new value will take effect immediately when Output Compare Preload (OCPE)
+ * is disabled. Otherwise it will take effect by following condition:
+ * - Update event generated by counter overflow only (if Update event enabled)
+ * - Compare Matching event with the older value.
+ * - Software generate by setting the CCG bit in TMRx_EGR register
+ * @param __INSTANCE__ TMR peripheral
+ * @param __COMPARE__ specifies the Counter register new value.
+ * @return None
+ */
+#define __LL_TMR_SET_COMPARE(__INSTANCE__, __COMPARE__) WRITE_REG((__INSTANCE__)->CCR, (__COMPARE__))
+
+/**
+ * @brief Get the TMR Capture Compare Register(TMRx_CCR) value on runtime.
+ * @note This macro normally used when the TMR is configured in Input Capture mode.
+ * User can use the macro to get the new capture value on runtime when a Capture event
+ * is generated by fllowing condition:
+ * - Input source trigger an edge matches the Input Capture Polarity edge configuration (CCP)
+ * - Software generate by setting the CCG bit in TMRx_EGR register
+ * @param __INSTANCE__ TMR peripheral
+ * @return 16-bit or 32-bit value of the timer capture compare register (TMRx_CCR)
+ */
+#define __LL_TMR_GET_CAPTURE(__INSTANCE__) READ_REG((__INSTANCE__)->CCR)
+
+/**
+ * @brief Set the input channel polarity.
+ * @param __INSTANCE__ Timer peripheral
+ * @param __POLARITY__ This parameter can be one of the following values in @ref TMR_Input_Capture_Polarity:
+ * @arg @ref TMR_ICPOLARITY_RISING :Capture triggered by rising edge on timer input
+ * @arg @ref TMR_ICPOLARITY_FALLING :Capture triggered by falling edge on timer input
+ * @arg @ref TMR_ICPOLARITY_BOTHEDGE :Capture triggered by both rising and falling edges on timer input
+ * @retval None
+ */
+#define __LL_TMR_POLARITY_SET(__INSTANCE__, __POLARITY__) MODIFY_REG((__INSTANCE__)->CCCR, TMR_CCCR_CCP_Msk, (__POLARITY__))
+
+/**
+ * @brief Set the TMR Ouput Compare Mode on runtime.
+ * @param __INSTANCE__ TMR peripheral
+ * @param __OCMODE__ TMR Output Compare and PWM Modes
+ * This parameter can be one of @ref TMR_Output_Compare_and_PWM_modes
+ * @return None
+ */
+#define __LL_TMR_SET_OCMODE(__INSTANCE__, __OCMODE__) MODIFY_REG((__INSTANCE__)->CCCR, TMR_CCCR_OCM_Msk, (__OCMODE__))
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TMR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TMR_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_TMR_Init(TMR_TypeDef *Instance, TMR_InitTypeDef *Init);
+LL_StatusETypeDef LL_TMR_DeInit(TMR_TypeDef *Instance);
+void LL_TMR_MspInit(TMR_TypeDef *Instance);
+void LL_TMR_MspDeInit(TMR_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup TMR_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_TMR_TB_Config(TMR_TypeDef *Instance, TMR_TB_InitTypeDef *sConfig);
+LL_StatusETypeDef LL_TMR_IC_Config(TMR_TypeDef *Instance, TMR_IC_InitTypeDef *sConfig);
+LL_StatusETypeDef LL_TMR_OC_Config(TMR_TypeDef *Instance, TMR_OC_InitTypeDef *sConfig);
+LL_StatusETypeDef LL_TMR_EXT_Config(TMR_TypeDef *Instance, TMR_EXT_InitTypeDef *sConfig);
+/**
+ * @}
+ */
+
+
+/** @addtogroup TMR_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_TMR_Start(TMR_TypeDef *Instance);
+LL_StatusETypeDef LL_TMR_Stop(TMR_TypeDef *Instance);
+LL_StatusETypeDef LL_TMR_Start_IT(TMR_TypeDef *Instance);
+LL_StatusETypeDef LL_TMR_Stop_IT(TMR_TypeDef *Instance);
+LL_StatusETypeDef LL_TMR_Start_Synchro(TMRGRP_TypeDef *TMRGRPx, uint32_t SynchroMask);
+LL_StatusETypeDef LL_TMR_Stop_Synchro(TMRGRP_TypeDef *TMRGRPx, uint32_t SynchroMask);
+LL_StatusETypeDef LL_TMR_EventGenerate(TMR_TypeDef *Instance, TMR_EventSRCETypeDef EventSource);
+/**
+ * @}
+ */
+
+
+/** @addtogroup TMR_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_TMR_IRQHandler(TMR_TypeDef *Instance);
+void LL_TMR_TB_UpdateCallback(TMR_TypeDef *Instance);
+void LL_TMR_TB_OverflowCallback(TMR_TypeDef *Instance);
+void LL_TMR_IC_CaptureCallback(TMR_TypeDef *Instance);
+void LL_TMR_IC_OverCaptureCallback(TMR_TypeDef *Instance);
+void LL_TMR_OC_CompareMatchedCallback(TMR_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TMR_LL_Private_Macros TMR LL Private Macros
+ * @brief TMR LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is LSTMR instance or not
+ * @param __INSTANCE__ instance to judge
+ * @retval 0 isn't LSTMR instance
+ * @retval 1 is LSTMR instance
+ */
+#define IS_TMR_LSTMR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TMR0) || \
+ ((__INSTANCE__) == TMR1) || \
+ ((__INSTANCE__) == TMR2) || \
+ ((__INSTANCE__) == TMR3))
+
+/**
+ * @brief Judge is HSTMR instance or not
+ * @param __INSTANCE__ instance to judge
+ * @retval 0 isn't HSTMR instance
+ * @retval 1 is HSTMR instance
+ */
+#define IS_TMR_HSTMR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TMR4) || \
+ ((__INSTANCE__) == TMR5) || \
+ ((__INSTANCE__) == TMR6) || \
+ ((__INSTANCE__) == TMR7))
+
+/**
+ * @brief Judge is LSTMR prescaler or not
+ * @param __PRESCALER__ prescaler to judge
+ * @retval 0 isn't LSTMR prescaler
+ * @retval 1 is LSTMR prescaler
+ */
+#define IS_TMR_LSTMR_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU )
+
+/**
+ * @brief Judge is HSTMR prescaler or not
+ * @param __PRESCALER__ prescaler to judge
+ * @retval 0 isn't HSTMR prescaler
+ * @retval 1 is HSTMR prescaler
+ */
+#define IS_TMR_HSTMR_PRSCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFFFFFU )
+
+/**
+ * @brief Judge is LSTMR start value or not
+ * @param __VAL__ value to judge
+ * @retval 0 is LSTMR start value
+ * @retval 1 is LSTMR start value
+ */
+#define IS_TMR_LSTMR_START_VAL(__VAL__) ((__VAL__) <= 0xFFFFUL)
+
+/**
+ * @brief Judge is HSTMR start value or not
+ * @param __VAL__ value to judge
+ * @retval 0 is HSTMR start value
+ * @retval 1 is HSTMR start value
+ */
+#define IS_TMR_HSTMR_START_VAL(__VAL__) ((__VAL__) <= 0xFFFFFFFFUL)
+
+/**
+ * @brief Judge is LSTMR end value or not
+ * @param __VAL__ value to judge
+ * @retval 0 is LSTMR end value
+ * @retval 1 is LSTMR end value
+ */
+#define IS_TMR_LSTMR_END_VAL(__VAL__) ((__VAL__) <= 0xFFFFUL)
+
+/**
+ * @brief Judge is HSTMR end value or not
+ * @param __VAL__ value to judge
+ * @retval 0 is HSTMR end value
+ * @retval 1 is HSTMR end value
+ */
+#define IS_TMR_HSTMR_END_VAL(__VAL__) ((__VAL__) <= 0xFFFFFFFFUL)
+
+/**
+ * @brief Judge is LSTMR compare value or not
+ * @param __VAL__ value to judge
+ * @retval 0 isn't LSTMR compare value
+ * @retval 1 is LSTMR compare value
+ */
+#define IS_TMR_LSTMR_COMPARE_VAL(__VAL__) ((__VAL__) <= 0xFFFFUL)
+
+/**
+ * @brief Judge is HSTMR compare value or not
+ * @param __VAL__ value to judge
+ * @retval 0 isn't HSTMR compare value
+ * @retval 1 is HSTMR compare value
+ */
+#define IS_TMR_HSTMR_COMPARE_VAL(__VAL__) ((__VAL__) <= 0xFFFFFFFFUL)
+
+
+/**
+ * @brief Judge is TMR input capture filter or not
+ * @param __FILTER__ filter to judge
+ * @retval 0 isn't TMR input capture filter
+ * @retval 1 is TMR input capture filter
+ */
+#define IS_TMR_ICFILTER(__FILTER__) ((__FILTER__) <= 0xFFUL)
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_TMR_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_uart.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_uart.h
new file mode 100644
index 0000000000..86a36aa297
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_uart.h
@@ -0,0 +1,873 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_uart.h
+ * @author MCD Application Team
+ * @brief Header file for UART LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_UART_H_
+#define _TAE32F53XX_LL_UART_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+#ifdef LL_DMA_MODULE_ENABLED
+#include "tae32f53xx_ll_dma.h"
+#endif
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UART_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_LL_Exported_Types UART LL Exported Types
+ * @brief UART LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART interrupt ID type definition
+ */
+typedef enum {
+ UART_INT_ID_MODEM_STA = 0x0, /*!< modem status */
+ UART_INT_ID_NO_INT_PENDING = 0x1, /*!< no interrupt pending */
+ UART_INT_ID_TX_EMPTY = 0x2, /*!< THR register empty */
+ UART_INT_ID_RX_AVL = 0x4, /*!< received data available */
+ UART_INT_ID_RX_LINE_STA = 0x6, /*!< receiver line status */
+ UART_INT_ID_BUSY_DET = 0x7, /*!< busy detect */
+ UART_INT_ID_CHAR_TIMEOUT = 0xc, /*!< character timeout */
+} UART_IntIdETypeDef;
+
+/**
+ * @brief UART data length type definition
+ */
+typedef enum {
+ UART_DAT_LEN_5b = 0, /*!< Data length 5bits */
+ UART_DAT_LEN_6b = 1, /*!< Data length 6bits */
+ UART_DAT_LEN_7b = 2, /*!< Data length 7bits */
+ UART_DAT_LEN_8b = 3, /*!< Data length 8bits */
+ UART_DAT_LEN_9b = 4, /*!< Data length 9bits */
+} UART_DatLenETypeDef;
+
+/**
+ * @brief UART stop length type definition
+ */
+typedef enum {
+ UART_STOP_LEN_1b, /*!< Stop length 1bit */
+ UART_STOP_LEN_1b5, /*!< Stop length 1.5bit */
+ UART_STOP_LEN_2b, /*!< Stop length 2bits */
+} UART_StopLenETypeDef;
+
+/**
+ * @brief UART parity type definition
+ */
+typedef enum {
+ UART_PARITY_NO, /*!< Parity no */
+ UART_PARITY_ODD, /*!< Parity odd */
+ UART_PARITY_EVEN, /*!< Parity even */
+} UART_ParityETypeDef;
+
+/**
+ * @brief UART tx empty trigger level type definition
+ */
+typedef enum {
+ UART_TX_EMPTY_TRI_LVL_EMPTY = UART_TX_FIFO_TRIG_EMPTY, /*!< tx empty trigger level empty */
+ UART_TX_EMPTY_TRI_LVL_2CAHR = UART_TX_FIFO_TRIG_2CHAR, /*!< tx empty trigger level 2char */
+ UART_TX_EMPTY_TRI_LVL_QUARTER = UART_TX_FIFO_TRIG_QUARTER, /*!< tx empty trigger level quarter */
+ UART_TX_EMPTY_TRI_LVL_HALF = UART_TX_FIFO_TRIG_HALF, /*!< tx empty trigger level half */
+} UART_TxEmptyTriLvlETypeDef;
+
+/**
+ * @brief UART rx available trigger level type definition
+ */
+typedef enum {
+ UART_RX_AVL_TRI_LVL_1CHAR = UART_RX_FIFO_TRIG_1CHAR, /*!< rx available trigger level 1char */
+ UART_RX_AVL_TRI_LVL_QUARTER = UART_RX_FIFO_TRIG_QUARTER, /*!< rx available trigger level quarter */
+ UART_RX_AVL_TRI_LVL_HALF = UART_RX_FIFO_TRIG_HALF, /*!< rx available trigger level half */
+ UART_RX_AVL_TRI_LVL_FULL_LESS_2 = UART_RX_FIFO_TRIG_2LESS_FULL, /*!< rx available trigger level full less 2 */
+} UART_RxAvlTriLvlETypeDef;
+
+/**
+ * @brief UART DE polarity type definition
+ */
+typedef enum {
+ UART_DE_POL_ACT_LOW, /*!< DE polarity active low */
+ UART_DE_POL_ACT_HIGH, /*!< DE polarity active high */
+} UART_DePolETypeDef;
+
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct __UART_InitTypeDef {
+ uint32_t baudrate; /*!< baudrate */
+ UART_DatLenETypeDef dat_len; /*!< data length */
+ UART_StopLenETypeDef stop_len; /*!< stop length */
+ UART_ParityETypeDef parity; /*!< parity */
+ UART_TxEmptyTriLvlETypeDef tx_tl; /*!< tx empty trigger level */
+ UART_RxAvlTriLvlETypeDef rx_tl; /*!< rx available trigger level */
+ bool U9BAddrMatchMode_Enable; /*!< 9_bit addr match enable */
+ uint8_t U9BRxAddress; /*!< 9_bit Receive addr */
+} UART_InitTypeDef;
+
+/**
+ * @brief UART RS485 Mode Config Structure definition
+ */
+typedef struct __UART_Rs485CfgTypeDef {
+ bool de_en; /*!< DE Singal Enable control */
+ uint8_t de_assert_time; /*!< Driver enable assertion time */
+ uint8_t de_deassert_time; /*!< Driver enable de-assertion time */
+ UART_DePolETypeDef de_polarity; /*!< DE Singal Polarity */
+} UART_Rs485CfgTypeDef;
+
+/**
+ * @brief UART DMA Status
+ */
+typedef enum {
+ UART_DMA_STATE_RESET = 0, /*!< DMA State Reset: not yet initialized or disabled */
+ UART_DMA_STATE_READY, /*!< DMA State Ready: initialized and ready for use */
+ UART_DMA_STATE_BUSY, /*!< DMA State Busy: process is ongoing */
+ UART_DMA_STATE_ERROR, /*!< DMA State Error: process is Error */
+ UART_DMA_STATE_FINISH, /*!< DMA State Finish: process has been finished */
+} UART_DMAStatusTypeDef;
+
+/**
+ * @brief I2C frame definition
+ */
+typedef struct __UART_FrameTypeDef {
+ UART_TypeDef *Instance; /*!< UART Reg base address */
+ uint8_t *buf; /*!< buffer pointer */
+ uint16_t buf_len; /*!< buffer length */
+#ifdef LL_DMA_MODULE_ENABLED
+ DMA_ChannelETypeDef dma_tx_ch; /*!< UART Tx DMA Channel */
+ DMA_ChannelETypeDef dma_rx_ch; /*!< UART Rx DMA Channel */
+#endif
+ UART_DMAStatusTypeDef TXdma_status; /*!< UART DMA status */
+ UART_DMAStatusTypeDef RXdma_status; /*!< UART DMA status */
+} UART_DMAHandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UART_LL_Exported_Macros UART LL Exported Macros
+ * @brief UART LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief RX buffer 8bits read
+ * @param __UART__ Specifies UART peripheral
+ * @return 8bits read value
+ */
+#define __LL_UART_RxBuf8bits_Read(__UART__) (READ_BIT((__UART__)->RBR, UART_RBR_LSB_8bits_Msk))
+
+/**
+ * @brief RX buffer 9bits read
+ * @param __UART__ Specifies UART peripheral
+ * @return 9bits read value
+ */
+#define __LL_UART_RxBuf9bits_Read(__UART__) (READ_BIT((__UART__)->RBR, UART_RBR_9bits_Msk))
+
+/**
+ * @brief TX buffer 8bits write
+ * @param __UART__ Specifies UART peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_UART_TxBuf8bits_Write(__UART__, val) \
+ MODIFY_REG((__UART__)->THR, UART_THR_LSB_8bits_Msk, (((val) & 0xffUL) << UART_THR_LSB_8bits_Pos))
+
+/**
+ * @brief TX buffer 9bits write
+ * @param __UART__ Specifies UART peripheral
+ * @param val write value
+ * @return None
+ */
+#define __LL_UART_TxBuf9bits_Write(__UART__, val) \
+ MODIFY_REG((__UART__)->THR, UART_THR_9bits_Msk, (((val) & 0x1ffUL) << UART_THR_LSB_8bits_Pos))
+
+/**
+ * @brief divisor latch low wirte
+ * @param __UART__ Specifies UART peripheral
+ * @param val wirte value
+ * @return None
+ */
+#define __LL_UART_DivLatchLow_Write(__UART__, val) WRITE_REG((__UART__)->DLL, (val & UART_DLL_DLL_Msk))
+
+/**
+ * @brief divisor latch high wirte
+ * @param __UART__ Specifies UART peripheral
+ * @param val wirte value
+ * @return None
+ */
+#define __LL_UART_DivLatchHigh_Write(__UART__, val) WRITE_REG((__UART__)->DLH, (val & UART_DLH_DLH_Msk))
+
+/**
+ * @brief programmable THRE interrupt enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_THRE_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_PTIME_Msk)
+
+/**
+ * @brief programmable THRE interrupt disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_THRE_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_PTIME_Msk)
+
+/**
+ * @brief modem status interrupt enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_ModemSta_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_EDSSI_Msk)
+
+/**
+ * @brief modem status interrupt disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_ModemSta_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_EDSSI_Msk)
+
+/**
+ * @brief RX line status interrupt enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RxLineSta_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_ELSI_Msk)
+
+/**
+ * @brief RX line status interrupt disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RxLineSta_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_ELSI_Msk)
+
+/**
+ * @brief TX holding register empty interrupt enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_TxHoldEmpyt_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_ETBEI_Msk)
+
+/**
+ * @brief TX holding register empty interrupt disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_TxHoldEmpyt_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_ETBEI_Msk)
+
+/**
+ * @brief RX data available interrupt enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RxDatAvl_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_ERBFI_Msk)
+
+/**
+ * @brief RX data available interrupt disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RxDatAvl_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_ERBFI_Msk)
+
+/**
+ * @brief Judge is FIFOs enable or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't FIFOs enable
+ * @retval 3 is FIFOs enable
+ */
+#define __LL_UART_IsFIFOsEn(__UART__) (READ_BIT((__UART__)->IIR, UART_IIR_FIFOSE_Msk) >> UART_IIR_FIFOSE_Pos)
+
+/**
+ * @brief Interrupt ID get
+ * @param __UART__ Specifies UART peripheral
+ * @return Interrupt ID
+ */
+#define __LL_UART_INT_ID_Get(__UART__) (READ_BIT((__UART__)->IIR, UART_IIR_IID_Msk) >> UART_IIR_IID_Pos)
+
+/**
+ * @brief FCR register write
+ * @param __UART__ Specifies UART peripheral
+ * @param val write val
+ * @return None
+ */
+#define __LL_UART_FCR_Write(__UART__, val) WRITE_REG((__UART__)->FCR, val)
+
+/**
+ * @brief Divisor latch access set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DivLatchAccess_Set(__UART__) SET_BIT((__UART__)->LCR, UART_LCR_DLAB_Msk)
+
+/**
+ * @brief Divisor latch access clear
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DivLatchAccess_Clr(__UART__) CLEAR_BIT((__UART__)->LCR, UART_LCR_DLAB_Msk)
+
+/**
+ * @brief Break control set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_BreakCtrl_Set(__UART__) SET_BIT((__UART__)->LCR, UART_LCR_BC_Msk)
+
+/**
+ * @brief Break control clear
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_BreakCtrl_Clr(__UART__) CLEAR_BIT((__UART__)->LCR, UART_LCR_BC_Msk)
+
+/**
+ * @brief Stick parity set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_StickParity_Set(__UART__) SET_BIT((__UART__)->LCR, UART_LCR_Stick_Parity_Msk)
+
+/**
+ * @brief Stick parity clear
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_StickParity_Clr(__UART__) CLEAR_BIT((__UART__)->LCR, UART_LCR_Stick_Parity_Msk)
+
+/**
+ * @brief Even parity set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_EvenParity_Set(__UART__) SET_BIT((__UART__)->LCR, UART_LCR_EPS_Msk)
+
+/**
+ * @brief Even parity clear
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_EvenParity_Clr(__UART__) CLEAR_BIT((__UART__)->LCR, UART_LCR_EPS_Msk)
+
+/**
+ * @brief Parity enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_Parity_En(__UART__) SET_BIT((__UART__)->LCR, UART_LCR_PEN_Msk)
+
+/**
+ * @brief Parity disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_Parity_Dis(__UART__) CLEAR_BIT((__UART__)->LCR, UART_LCR_PEN_Msk)
+
+/**
+ * @brief Judge parity is enable or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 Parity isn't enable
+ * @retval 1 Parity is enable
+ */
+#define __LL_UART_IsParityEn(__UART__) (READ_BIT((__UART__)->LCR, UART_LCR_PEN_Msk) >> UART_LCR_PEN_Pos)
+
+/**
+ * @brief Stop 1bit set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_Stop1Bit_Set(__UART__) CLEAR_BIT((__UART__)->LCR, UART_LCR_STOP_Msk)
+
+/**
+ * @brief Stop 2bits set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_Stop2bits_Set(__UART__) SET_BIT((__UART__)->LCR, UART_LCR_STOP_Msk)
+
+/**
+ * @brief Data length select
+ * @param __UART__ Specifies UART peripheral
+ * @param val select value
+ * @return None
+ */
+#define __LL_UART_DatLen_Sel(__UART__, val) MODIFY_REG((__UART__)->LCR, UART_LCR_DLS_Msk, ((val & 0x3UL) << UART_LCR_DLS_Pos))
+
+/**
+ * @brief Judge is character address or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't character address
+ * @retval 1 is character address
+ */
+#define __LL_UART_IsCharacterAddr(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_ADDR_RCVD_Msk) >> UART_LSR_ADDR_RCVD_Pos)
+
+/**
+ * @brief Judge is RX FIFO error or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't RX FIFO error
+ * @retval 1 is RX FIFO error
+ */
+#define __LL_UART_IsRxFIFOErr(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_RFE_Msk) >> UART_LSR_RFE_Pos)
+
+/**
+ * @brief Judge is TX empty or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't TX empty
+ * @retval 1 is TX empty
+ */
+#define __LL_UART_IsTxEmpty(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_TEMT_Msk) >> UART_LSR_TEMT_Pos)
+
+/**
+ * @brief Judge is TX hold register empty or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't TX hold register empty
+ * @retval 1 is TX hold register empty
+ */
+#define __LL_UART_IsTxHoldRegEmpty(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_THRE_Msk) >> UART_LSR_THRE_Pos)
+
+/**
+ * @brief Judge is break interrupt or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't break interrupt
+ * @retval 1 is break interrupt
+ */
+#define __LL_UART_IsBreakInt(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_BI_Msk) >> UART_LSR_BI_Pos)
+
+/**
+ * @brief Judge is frame error or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't frame error
+ * @retval 1 is frame error
+ */
+#define __LL_UART_IsFrameErr(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_FE_Msk) >> UART_LSR_FE_Pos)
+
+/**
+ * @brief Judge is parity error or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't parity error
+ * @retval 1 is parity error
+ */
+#define __LL_UART_IsParityErr(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_PE_Msk) >> UART_LSR_PE_Pos)
+
+/**
+ * @brief Judge is overrun error or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't overrun error
+ * @retval 1 is overrun error
+ */
+#define __LL_UART_IsOverrunErr(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_OE_Msk) >> UART_LSR_OE_Pos)
+
+/**
+ * @brief Judge is data ready or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't data ready
+ * @retval 1 is data ready
+ */
+#define __LL_UART_IsDatReady(__UART__) (READ_BIT((__UART__)->LSR, UART_LSR_DR_Msk) >> UART_LSR_DR_Pos)
+
+/**
+ * @brief Line status get
+ * @param __UART__ Specifies UART peripheral
+ * @return Line status
+ */
+#define __LL_UART_LineSta_Get(__UART__) READ_BIT((__UART__)->LSR, UART_LSR_ALL_BIT_Msk)
+
+/**
+ * @brief Judge is RXFIFO full or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 isn't RXFIFO full
+ * @retval 1 is RXFIFO full
+ */
+#define __LL_UART_IsRxFIFOFull(__UART__) (READ_BIT((__UART__)->USR, UART_USR_RFF_Msk) >> UART_USR_RFF_Pos)
+
+/**
+ * @brief Judge is RXFIFO not empty or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 RXFIFO is empty
+ * @retval 1 RXFIFO is not empty
+ */
+#define __LL_UART_IsRxFIFONotEmpty(__UART__) (READ_BIT((__UART__)->USR, UART_USR_RFNE_Msk) >> UART_USR_RFNE_Pos)
+
+/**
+ * @brief Judge is TXFIFO empty or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 TXFIFO is not empty
+ * @retval 1 TXFIFO is empty
+ */
+#define __LL_UART_IsTxFIFOEmpty(__UART__) (READ_BIT((__UART__)->USR, UART_USR_TFE_Msk) >> UART_USR_TFE_Pos)
+
+/**
+ * @brief Judge is TXFIFO not full or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 TXFIFO is full
+ * @retval 1 TXFIFO is not full
+ */
+#define __LL_UART_IsTxFIFONotFull(__UART__) (READ_BIT((__UART__)->USR, UART_USR_TFNF_Msk) >> UART_USR_TFNF_Pos)
+
+/**
+ * @brief TXFIFO level get
+ * @param __UART__ Specifies UART peripheral
+ * @return TXFIFO level
+ */
+#define __LL_UART_TxFIFOLevel_Get(__UART__) (READ_BIT((__UART__)->TFL, UART_TFL_TFL_Msk) >> UART_TFL_TFL_Pos)
+
+/**
+ * @brief RXFIFO level get
+ * @param __UART__ Specifies UART peripheral
+ * @return RXFIFO level
+ */
+#define __LL_UART_RxFIFOLevel_Get(__UART__) (READ_BIT((__UART__)->RFL, UART_RFL_RFL_Msk) >> UART_RFL_RFL_Pos)
+
+/**
+ * @brief TX halt enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_TxHalt_En(__UART__) SET_BIT((__UART__)->HTX, UART_HTX_HTX_Msk)
+
+/**
+ * @brief TX halt disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_TxHalt_Dis(__UART__) CLEAR_BIT((__UART__)->HTX, UART_HTX_HTX_Msk)
+
+/**
+ * @brief TX mode set
+ * @param __UART__ Specifies UART peripheral
+ * @param mode tx mode
+ * @return None
+ */
+#define __LL_UART_TxMode_Set(__UART__, mode) MODIFY_REG((__UART__)->TCR, UART_TCR_XFER_MODE_Msk, mode)
+
+/**
+ * @brief DE signal active high set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DE_ActHigh_Set(__UART__) SET_BIT((__UART__)->TCR, UART_TCR_DE_POL_Msk)
+
+/**
+ * @brief DE signal active low set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DE_ActLow_Set(__UART__) CLEAR_BIT((__UART__)->TCR, UART_TCR_DE_POL_Msk)
+
+/**
+ * @brief RE signal active high set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RE_ActHigh_Set(__UART__) SET_BIT((__UART__)->TCR, UART_TCR_RE_POL_Msk)
+
+/**
+ * @brief RE signal active low set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RE_ActLow_Set(__UART__) CLEAR_BIT((__UART__)->TCR, UART_TCR_RE_POL_Msk)
+
+/**
+ * @brief RS485 mode enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RS485Mode_En(__UART__) SET_BIT((__UART__)->TCR, UART_TCR_RS485_EN_Msk)
+
+/**
+ * @brief RS485 mode disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RS485Mode_Dis(__UART__) CLEAR_BIT((__UART__)->TCR, UART_TCR_RS485_EN_Msk)
+
+/**
+ * @brief DE enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DE_En(__UART__) SET_BIT((__UART__)->DE_EN, UART_DE_EN_DE_EN_Msk)
+
+/**
+ * @brief DE disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DE_Dis(__UART__) CLEAR_BIT((__UART__)->DE_EN, UART_DE_EN_DE_EN_Msk)
+
+/**
+ * @brief RE enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_RE_En(__UART__) SET_BIT((__UART__)->RE_EN, UART_RE_EN_RE_EN_Msk)
+
+/**
+ * @brief DE deassertion time set
+ * @param __UART__ Specifies UART peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_UART_DE_DeAssertTime_Set(__UART__, val) \
+ MODIFY_REG((__UART__)->DET, UART_DET_DE_DEASSERT_TIME_Msk, ((val & 0xffUL) << UART_DET_DE_DEASSERT_TIME_Pos))
+
+/**
+ * @brief DE assertion time set
+ * @param __UART__ Specifies UART peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_UART_DE_AssertTime_Set(__UART__, val) \
+ MODIFY_REG((__UART__)->DET, UART_DET_DE_ASSERT_TIME_Msk, ((val & 0xffUL) << UART_DET_DE_ASSERT_TIME_Pos))
+
+/**
+ * @brief RE to DE turn around time set
+ * @param __UART__ Specifies UART peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_UART_REtoDE_TurnAroundTime_Set(__UART__, val) \
+ MODIFY_REG((__UART__)->TAT, UART_TAT_RE_TO_DE_TIME_Msk, ((val & 0xffffUL) << UART_TAT_RE_TO_DE_TIME_Pos))
+
+/**
+ * @brief DE to RE turn around time set
+ * @param __UART__ Specifies UART peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_UART_DEtoRE_TurnAroundTime_Set(__UART__, val) \
+ MODIFY_REG((__UART__)->TAT, UART_TAT_DE_TO_RE_TIME_Msk, ((val & 0xffffUL) << UART_TAT_DE_TO_RE_TIME_Pos))
+
+/**
+ * @brief Divisor latch fraction set
+ * @param __UART__ Specifies UART peripheral
+ * @param val set value
+ * @return None
+ */
+#define __LL_UART_DivLatchFrac_Set(__UART__, val) MODIFY_REG((__UART__)->DLF, UART_DLF_DLF_Msk, ((val & 0xfUL) << UART_DLF_DLF_Pos))
+
+/**
+ * @brief RAR set
+ * @param __UART__ Specifies UART peripheral
+ * @param addr set address
+ * @return None
+ */
+#define __LL_UART_RAR_Set(__UART__, addr) MODIFY_REG((__UART__)->RAR, UART_RAR_RAR_Msk, ((addr & 0xffUL) << UART_RAR_RAR_Pos))
+
+/**
+ * @brief TAR set
+ * @param __UART__ Specifies UART peripheral
+ * @param addr set address
+ * @return None
+ */
+#define __LL_UART_TAR_Set(__UART__, addr) MODIFY_REG((__UART__)->TAR, UART_TAR_TAR_Msk, ((addr & 0xffUL) << UART_TAR_TAR_Pos))
+
+/**
+ * @brief TX mode 9bits set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_TxMode9bits_Set(__UART__) SET_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_TRANSMIT_MODE_Msk)
+
+/**
+ * @brief TX mode 8bits set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_TxMode8bits_Set(__UART__) CLEAR_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_TRANSMIT_MODE_Msk)
+
+/**
+ * @brief TX mode status get
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 TX mode is 8bits
+ * @retval 1 TX mode is 9bits
+ */
+#define __LL_UART_TxModeSta_Get(__UART__) \
+ (READ_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_TRANSMIT_MODE_Msk) >> UART_LCR_EXT_TRANSMIT_MODE_Pos)
+
+/**
+ * @brief Send address set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_SendAddr_Start(__UART__) SET_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_SEND_ADDR_Msk)
+
+/**
+ * @brief Send data set
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_SendDat_Start(__UART__) CLEAR_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_SEND_ADDR_Msk)
+
+/**
+ * @brief Address match mode enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_AddrMatchMode_En(__UART__) SET_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_ADDR_MATCH_Msk)
+
+/**
+ * @brief Address match mode disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_AddrMatchMode_Dis(__UART__) CLEAR_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_ADDR_MATCH_Msk)
+
+/**
+ * @brief Data length extension 9bits enable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DatLen9bitsExt_En(__UART__) SET_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_DLS_E_Msk)
+
+/**
+ * @brief Data length extension 9bits disable
+ * @param __UART__ Specifies UART peripheral
+ * @return None
+ */
+#define __LL_UART_DatLen9bitsExt_Dis(__UART__) CLEAR_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_DLS_E_Msk)
+
+/**
+ * @brief Judge data length extension 9bits is enable or not
+ * @param __UART__ Specifies UART peripheral
+ * @retval 0 Data length extension 9bits isn't enable
+ * @retval 1 Data length extension 9bits is enable
+ */
+#define __LL_UART_IsDatLen9bitsEn(__UART__) (READ_BIT((__UART__)->LCR_EXT, UART_LCR_EXT_DLS_E_Msk) >> UART_LCR_EXT_DLS_E_Pos)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UART_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_UART_Init(UART_TypeDef *Instance, UART_InitTypeDef *Init);
+LL_StatusETypeDef LL_UART_DeInit(UART_TypeDef *Instance);
+void LL_UART_MspInit(UART_TypeDef *Instance);
+void LL_UART_MspDeInit(UART_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_UART_Transmit_CPU(UART_TypeDef *Instance, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+LL_StatusETypeDef LL_UART_Receive_CPU(UART_TypeDef *Instance, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+LL_StatusETypeDef LL_UART_Transmit_IT(UART_TypeDef *Instance);
+LL_StatusETypeDef LL_UART_Receive_IT(UART_TypeDef *Instance);
+
+#ifdef LL_DMA_MODULE_ENABLED
+LL_StatusETypeDef LL_UART_Transmit_DMA(UART_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ UART_DMAHandleTypeDef *huart, uint32_t Timeout);
+LL_StatusETypeDef LL_UART_Receive_DMA(UART_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ UART_DMAHandleTypeDef *huart, uint32_t Timeout);
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_LL_Exported_Functions_Group3
+ * @{
+ */
+LL_StatusETypeDef LL_Uart_9bit_SendAddress(UART_TypeDef *Instance, uint8_t TxAddr);
+LL_StatusETypeDef LL_UART_RS485Cfg(UART_TypeDef *Instance, UART_Rs485CfgTypeDef *cfg);
+uint8_t LL_UART_TxFIFOLVL_GET(UART_TypeDef *Instance);
+uint8_t LL_UART_RxFIFOLVL_GET(UART_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_UART_IRQHandler(UART_TypeDef *Instance);
+
+void LL_UART_ModemStaCallback(UART_TypeDef *Instance);
+void LL_UART_TxEmptyCallback(UART_TypeDef *Instance);
+void LL_UART_RxAvailableCallback(UART_TypeDef *Instance);
+void LL_UART_RxLineStaCallback(UART_TypeDef *Instance);
+void LL_UART_BusyDetCallback(UART_TypeDef *Instance);
+void LL_UART_CharTimeOutCallback(UART_TypeDef *Instance);
+
+void LL_UART_BreakErrCallback(UART_TypeDef *Instance);
+void LL_UART_FrameErrCallback(UART_TypeDef *Instance);
+void LL_UART_ParityErrCallback(UART_TypeDef *Instance);
+void LL_UART_RxOverrunErrCallback(UART_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_UART_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_usb.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_usb.h
new file mode 100644
index 0000000000..aebd0eacfd
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_usb.h
@@ -0,0 +1,1234 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_usb.h
+ * @author MCD Application Team
+ * @brief Header file of USB LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_USB_H_
+#define _TAE32F53XX_LL_USB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup USB_LL
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB LL Exported Macros
+ * @brief USB LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set Function Address
+ * @param __USB__ Specifies USB peripheral
+ * @param func_addr Function Address
+ * @return None
+ */
+#define __LL_USB_FuncAddr_Set(__USB__, func_addr) \
+ MODIFY_REG((__USB__)->FADDR, USB_FUNC_ADDR_Msk, ((func_addr & 0x7FUL) << USB_FUNC_ADDR_Pos))
+
+
+/**
+ * @brief Enable the SUSPENDM output
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_SuspendDMOut_En(__USB__) SET_BIT((__USB__)->POWER, USB_SUSPEND_DM_EN_Msk)
+
+/**
+ * @brief Disable the SUSPENDM output
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_SuspendDMOut_Dis(__USB__) CLEAR_BIT((__USB__)->POWER, USB_SUSPEND_DM_EN_Msk)
+
+/**
+ * @brief Enable HighSpeed
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_HighSpeed_En(__USB__) SET_BIT((__USB__)->POWER, USB_HS_EN_Msk)
+
+/**
+ * @brief Disable HighSpeed
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_HighSpeed_Dis(__USB__) CLEAR_BIT((__USB__)->POWER, USB_HS_EN_Msk)
+
+/**
+ * @brief Enable Soft Connect
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_SoftConn_En(__USB__) SET_BIT((__USB__)->POWER, USB_SOFT_CONN_EN_Msk)
+
+/**
+ * @brief Disable Soft Connect
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_SoftConn_Dis(__USB__) CLEAR_BIT((__USB__)->POWER, USB_SOFT_CONN_EN_Msk)
+
+
+/**
+ * @brief Get Endpoint 0 and TX Endpoint Interrupt Status
+ * @param __USB__ Specifies USB peripheral
+ * @return Endpoint 0 and TX Endpoint Interrupt Status
+ */
+#define __LL_USB_EP0AndEPxTX_IntSta_Get(__USB__) ((__USB__)->INTRTX)
+
+
+/**
+ * @brief Get RX Endpoint Interrupt Status
+ * @param __USB__ Specifies USB peripheral
+ * @return RX Interrupt Status
+ */
+#define __LL_USB_EPx_RXIntSta_Get(__USB__) ((__USB__)->INTRRX)
+
+
+/**
+ * @brief Enable Endpoint 0 and TX Endpoint Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @param ep_num USB_EpNumETypeDef Type Endpoint Number
+ * @return None
+ */
+#define __LL_USB_EP0AndEPxTX_Int_EN(__USB__, ep_num) \
+ do { \
+ if(ep_num >= EP_NUMS){ \
+ break; \
+ } \
+ uint16_t ep0_and_epxtx_int_en_bitmask[] = {USB_EP0_INT_EN_Msk, USB_TX_EP1_INT_EN_Msk, USB_TX_EP2_INT_EN_Msk}; \
+ SET_BIT((__USB__)->INTRTXE, ep0_and_epxtx_int_en_bitmask[ep_num]); \
+ } while(0)
+
+/**
+ * @brief Disable Endpoint 0 and TX Endpoint Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @param ep_num USB_EpNumETypeDef Type Endpoint Number
+ * @return None
+ */
+#define __LL_USB_EP0AndEPxTX_Int_Dis(__USB__, ep_num) \
+ do { \
+ if(ep_num >= EP_NUMS){ \
+ break; \
+ } \
+ uint16_t ep0_and_epxtx_int_en_bitmask[] = {USB_EP0_INT_EN_Msk, USB_TX_EP1_INT_EN_Msk, USB_TX_EP2_INT_EN_Msk}; \
+ CLEAR_BIT((__USB__)->INTRTXE, ep0_and_epxtx_int_en_bitmask[ep_num]); \
+ } while(0)
+
+
+/**
+ * @brief Enable RX Endpoint Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @param ep_num USB_EpNumETypeDef Type Endpoint Number
+ * @return None
+ */
+#define __LL_USB_EPx_RXInt_En(__USB__, ep_num) \
+ do { \
+ if(ep_num >= EP_NUMS){ \
+ break; \
+ } \
+ uint16_t epxrx_int_en_bitmask[] = {0, USB_RX_EP1_INT_EN_Msk, USB_RX_EP2_INT_EN_Msk}; \
+ SET_BIT((__USB__)->INTRRXE, epxrx_int_en_bitmask[ep_num]); \
+ } while(0)
+
+/**
+ * @brief Disable RX Endpoint Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @param ep_num USB_EpNumETypeDef Type Endpoint Number
+ * @return None
+ */
+#define __LL_USB_EPx_RXInt_Dis(__USB__, ep_num) \
+ do { \
+ if(ep_num >= EP_NUMS){ \
+ break; \
+ } \
+ uint16_t epxrx_int_en_bitmask[] = {0, USB_RX_EP1_INT_EN_Msk, USB_RX_EP2_INT_EN_Msk}; \
+ CLEAR_BIT((__USB__)->INTRRXE, epxrx_int_en_bitmask[ep_num]); \
+ } while(0)
+
+
+/**
+ * @brief Get USB Controler Interrupt Status
+ * @param __USB__ Specifies USB peripheral
+ * @return USB Controler Interrupt Status
+ */
+#define __LL_USB_IntSta_Get(__USB__) (READ_BIT((__USB__)->INTRUSB, USB_CTRL_INT_ALL_Msk) >> USB_SUSPEND_INT_STA_Pos)
+
+
+/**
+ * @brief Enable USB Controler Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @param int_bit_mask Interrupt BitMask to Be Enable
+ * @return None
+ */
+#define __LL_USB_Int_EN(__USB__, int_bit_mask) SET_BIT((__USB__)->INTRUSBE, int_bit_mask)
+
+/**
+ * @brief Disable USB Controler Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @param int_bit_mask Interrupt BitMask to be Disable
+ * @return None
+ */
+#define __LL_USB_Int_Dis(__USB__, int_bit_mask) CLEAR_BIT((__USB__)->INTRUSBE, int_bit_mask)
+
+
+/**
+ * @brief Get Frame Number
+ * @param __USB__ Specifies USB peripheral
+ * @return Frame Number
+ */
+#define __LL_USB_FrameNum_Get(__USB__) (READ_BIT((__USB__)->FRAME, USB_FRAME_NUM_Msk) >> USB_FRAME_NUM_Pos)
+
+
+/**
+ * @brief Set Endpoint Index
+ * @param __USB__ Specifies USB peripheral
+ * @param idx Index to be Set
+ * @return None
+ */
+#define __LL_USB_EPIndex_Set(__USB__, idx) \
+ MODIFY_REG((__USB__)->INDEX, USB_EP_INDEX_Msk, ((idx & 0xFUL) << USB_EP_INDEX_Pos))
+
+
+/**
+ * @brief Set TX Max Payload
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @param max_payload Max Payload to be Set
+ * @return None
+ */
+#define __LL_USB_EPx_TXMaxPayload_Set(__USB__, max_payload) \
+ MODIFY_REG((__USB__)->TXMAXP, USB_EPX_TX_MAX_PAYLD_Msk, ((max_payload & 0xFFFFUL) << USB_EPX_TX_MAX_PAYLD_Pos))
+
+/**
+ * @brief Get TX Max Payload
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return TX Max Payload
+ */
+#define __LL_USB_EPx_TXMaxPayload_Get(__USB__) \
+ (READ_BIT((__USB__)->TXMAXP, USB_EPX_TX_MAX_PAYLD_Msk) >> USB_EPX_TX_MAX_PAYLD_Pos)
+
+
+/**
+ * @brief Judge Endpoint 0 RX Packet Ready or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 RX Packet Not Ready
+ * @retval 1 RX Packet Ready
+ */
+#define __LL_USB_EP0_IsRXPktRdy(__USB__) (READ_BIT((__USB__)->TX_CSR0, USB_EP0_RX_PKT_RDY_Msk) >> USB_EP0_RX_PKT_RDY_Pos)
+
+/**
+ * @brief Clear Endpoint 0 RX Packet Ready
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EP0_RXPktRdy_Clr(__USB__) SET_BIT((__USB__)->TX_CSR0, USB_EP0_CLR_RX_PKT_RDY_Msk)
+
+/**
+ * @brief Set Endpoint 0 TX Packet Ready
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EP0_TXPktRdy_Set(__USB__) SET_BIT((__USB__)->TX_CSR0, USB_EP0_TX_PKT_RDY_Msk)
+
+/**
+ * @brief Judge Endpoint 0 TX Packet Ready or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 TX Packet Not Ready
+ * @retval 1 TX Packet Ready
+ */
+#define __LL_USB_EP0_IsTXPktRdy(__USB__) (READ_BIT((__USB__)->TX_CSR0, USB_EP0_TX_PKT_RDY_Msk) >> USB_EP0_TX_PKT_RDY_Pos)
+
+/**
+ * @brief Set Endpoint 0 to Send Stall
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EP0_SendStall_Set(__USB__) SET_BIT((__USB__)->TX_CSR0, USB_EP0_SEND_STALL_Msk)
+
+/**
+ * @brief Judge Endpoint 0 has Sent Stall or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Hasn't Sent Stall
+ * @retval 1 Has Sent Stall
+ */
+#define __LL_USB_EP0_IsSentStall(__USB__) (READ_BIT((__USB__)->TX_CSR0, USB_EP0_SENT_STALL_Msk) >> USB_EP0_SENT_STALL_Pos)
+
+/**
+ * @brief Clear Endpoint 0 Sent Stall Status
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EP0_SentStall_Clr(__USB__) CLEAR_BIT((__USB__)->TX_CSR0, USB_EP0_SENT_STALL_Msk)
+
+/**
+ * @brief Set Endpoint 0 Data End
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EP0_DataEnd_Set(__USB__) SET_BIT((__USB__)->TX_CSR0, USB_EP0_DATA_END_Msk)
+
+/**
+ * @brief Judge Endpoint 0 has SetupEnd or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Hasn't Setup End
+ * @retval 1 Has Setup End
+ */
+#define __LL_USB_EP0_IsSetupEnd(__USB__) (READ_BIT((__USB__)->TX_CSR0, USB_EP0_SETUP_END_Msk) >> USB_EP0_SETUP_END_Pos)
+
+/**
+ * @brief Clear Endpoint 0 SetupEnd Status
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EP0_SetupEnd_Clr(__USB__) SET_BIT((__USB__)->TX_CSR0, USB_EP0_CLR_SETUP_END_Msk)
+
+/**
+ * @brief Flush Endpoint 0 FIFO
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EP0_FlushFIFO(__USB__) SET_BIT((__USB__)->TX_CSR0, USB_EP0_FLUSH_FIFO_Msk)
+
+
+/**
+ * @brief Enable TX Packet Ready Auto Set Function
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXPktRdyAutoSet_En(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_AUTO_SET_Msk)
+
+/**
+ * @brief Disable TX Packet Ready Auto Set Function
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXPktRdyAutoSet_Dis(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_AUTO_SET_Msk)
+
+/**
+ * @brief Enable Endpoint TX ISO
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXISO_En(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_ISO_EN_Msk)
+
+/**
+ * @brief Disable Endpoint TX ISO
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXISO_Dis(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_ISO_EN_Msk)
+
+/**
+ * @brief Enable Endpoint TX
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TX_En(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_DIR_MODE_Msk)
+
+/**
+ * @brief Enable Endpoint RX
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RX_En(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_DIR_MODE_Msk)
+
+/**
+ * @brief Enable Endpoint TX DMA Request
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXDMAReq_En(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_DMA_REQ_EN_Msk)
+
+/**
+ * @brief Disable Endpoint TX DMA Request
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXDMAReq_Dis(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_DMA_REQ_EN_Msk)
+
+/**
+ * @brief Set Endpoint TX to Force Data Toggle
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXForceDataTog_Set(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_FRC_DATA_TOG_Msk)
+
+/**
+ * @brief Clear Endpoint TX to Force Data Toggle
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXForceDataTog_Clr(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_FRC_DATA_TOG_Msk)
+
+/**
+ * @brief Set Endpoint TX DMA Request Mode to 0
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXDMAReqMode0_Set(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_DMA_REQ_MODE_Msk)
+
+/**
+ * @brief Set Endpoint TX DMA Request Mode to 1
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXDMAReqMode1_Set(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_DMA_REQ_MODE_Msk)
+
+/**
+ * @brief Judge TX ISO Endpoint Is Incomplete or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Complete
+ * @retval 1 Incomplete
+ */
+#define __LL_USB_EPx_IsTXISOInComp(__USB__) \
+ (READ_BIT((__USB__)->TX_CSRX, USB_EPX_TX_ISO_INCOMP_Msk) >> USB_EPX_TX_ISO_INCOMP_Pos)
+
+/**
+ * @brief Clear TX Endpoint Data Toggle
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXDataTog_Clr(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_CLR_DATA_TOG_Msk)
+
+/**
+ * @brief Judge TX Endpoint has Sent Stall or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Hasn't Sent Stall
+ * @retval 1 Has Sent Stall
+ */
+#define __LL_USB_EPx_IsTXSentStall(__USB__) \
+ (READ_BIT((__USB__)->TX_CSRX, USB_EPX_TX_SENT_STALL_Msk) >> USB_EPX_TX_SENT_STALL_Pos)
+
+/**
+ * @brief Clear TX Endpoint Sent Stall Status
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXSentStall_Clr(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_SENT_STALL_Msk)
+
+/**
+ * @brief Enable TX Endpoint to Send Stall
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXSendStall_En(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_SEND_STALL_Msk)
+
+/**
+ * @brief Disable TX Endpoint to Send Stall
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXSendStall_Dis(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_SEND_STALL_Msk)
+
+/**
+ * @brief Flush TX Endpoint FIFO
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXFlushFIFO(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_FLUSH_FIFO_Msk)
+
+/**
+ * @brief Judge TX Endpoint FIFO Is UnderRun or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't UnderRun
+ * @retval 1 Is UnderRun
+ */
+#define __LL_USB_EPx_IsTXFIFOUnderRun(__USB__) \
+ (READ_BIT((__USB__)->TX_CSRX, USB_EPX_TX_UNDER_RUN_Msk) >> USB_EPX_TX_UNDER_RUN_Pos)
+
+/**
+ * @brief Clear TX Endpoint UnderRun Status
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXFIFOUnderRun_Clr(__USB__) CLEAR_BIT((__USB__)->TX_CSRX, USB_EPX_TX_UNDER_RUN_Msk)
+
+/**
+ * @brief Judge TX Endpoint FIFO Is NoEmpty or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't NoEmpty
+ * @retval 1 Is NoEmpty
+ */
+#define __LL_USB_EPx_IsTXFIFONoEmpty(__USB__) \
+ (READ_BIT((__USB__)->TX_CSRX, USB_EPX_TX_FIFO_NOT_EPY_Msk) >> USB_EPX_TX_FIFO_NOT_EPY_Pos)
+
+/**
+ * @brief Set TX Endpoint Packet Ready
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_TXPktRdy_Set(__USB__) SET_BIT((__USB__)->TX_CSRX, USB_EPX_TX_PKT_RDY_Msk)
+
+/**
+ * @brief Judge Endpoint TX Packet Ready or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't Packet Ready
+ * @retval 1 Is Packet Ready
+ */
+#define __LL_USB_EPx_IsTXPktRdy(__USB__) \
+ (READ_BIT((__USB__)->TX_CSRX, USB_EPX_TX_PKT_RDY_Msk) >> USB_EPX_TX_PKT_RDY_Pos)
+
+
+/**
+ * @brief Set RX Max Payload
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @param max_payload Max Payload to be Set
+ * @return None
+ */
+#define __LL_USB_EPx_RXMaxPayload_Set(__USB__, max_payload) \
+ MODIFY_REG((__USB__)->RXMAXP, USB_EPX_RX_MAX_PAYLD_Msk, ((max_payload & 0xFFFFUL) << USB_EPX_RX_MAX_PAYLD_Pos))
+
+/**
+ * @brief Get RX Max Payload
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return RX Max Payload
+ */
+#define __LL_USB_EPx_RXMaxPayload_Get(__USB__) \
+ (READ_BIT((__USB__)->RXMAXP, USB_EPX_RX_MAX_PAYLD_Msk) >> USB_EPX_RX_MAX_PAYLD_Pos)
+
+
+/**
+ * @brief Enable RX Packet Ready Auto Clear Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXPktRdyAutoClr_En(__USB__) SET_BIT((__USB__)->RXCSRN, USB_EPX_RX_AUTO_CLR_Msk)
+
+/**
+ * @brief Disable RX Packet Ready Auto Clear Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXPktRdyAutoClr_Dis(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_AUTO_CLR_Msk)
+
+/**
+ * @brief Enable Endpoint RX ISO
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXISO_En(__USB__) SET_BIT((__USB__)->RXCSRN, USB_EPX_RX_ISO_EN_Msk)
+
+/**
+ * @brief Disable Endpoint RX ISO
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXISO_Dis(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_ISO_EN_Msk)
+
+/**
+ * @brief Enable Endpoint RX DMA Request
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXDMAReq_En(__USB__) SET_BIT((__USB__)->RXCSRN, USB_EPX_RX_DMQ_REQ_EN_Msk)
+
+/**
+ * @brief Disable Endpoint RX DMA Request
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXDMAReq_Dis(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_DMQ_REQ_EN_Msk)
+
+/**
+ * @brief Judge RX ISO Endpoint PID Error or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't PID Error
+ * @retval 1 Is PID Error
+ */
+#define __LL_USB_EPx_IsRXISOPIDErr(__USB__) \
+ (READ_BIT((__USB__)->RXCSRN, USB_EPX_RX_ISO_PID_ERR_Msk) >> USB_EPX_RX_ISO_PID_ERR_Pos)
+
+/**
+ * @brief Set Endpoint RX DMA Request Mode to 0
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXDMAReqMode0_Set(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_DMA_REQ_MODE_Msk)
+
+/**
+ * @brief Set Endpoint RX DMA Request Mode to 1
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXDMAReqMode1_Set(__USB__) SET_BIT((__USB__)->RXCSRN, USB_EPX_RX_DMA_REQ_MODE_Msk)
+
+/**
+ * @brief Judge RX ISO Endpoint Is Incomplete or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Complete
+ * @retval 1 Incomplete
+ */
+#define __LL_USB_EPx_IsRXISOInComp(__USB__) \
+ (READ_BIT((__USB__)->RXCSRN, USB_EPX_RX_ISO_INCOMP_Msk) >> USB_EPX_RX_ISO_INCOMP_Pos)
+
+/**
+ * @brief Clear RX Endpoint Data Toggle
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXDataTog_Clr(__USB__) SET_BIT((__USB__)->RXCSRN, USB_EPX_RX_CLR_DATA_TOG_Msk)
+
+/**
+ * @brief Judge RX Endpoint has Sent Stall or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Hasn't Sent Stall
+ * @retval 1 Has Sent Stall
+ */
+#define __LL_USB_EPx_IsRXSentStall(__USB__) \
+ (READ_BIT((__USB__)->RXCSRN, USB_EPX_RX_SENT_STALL_Msk) >> USB_EPX_RX_SENT_STALL_Pos)
+
+/**
+ * @brief Clear RX Endpoint Sent Stall Status
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXSentStall_Clr(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_SENT_STALL_Msk)
+
+/**
+ * @brief Enable RX Endpoint to Send Stall
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXSendStall_En(__USB__) SET_BIT((__USB__)->RXCSRN, USB_EPX_RX_SEND_STALL_Msk)
+
+/**
+ * @brief Disable RX Endpoint to Send Stall
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXSendStall_Dis(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_SEND_STALL_Msk)
+
+/**
+ * @brief Flush RX Endpoint FIFO
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXFlushFIFO(__USB__) SET_BIT((__USB__)->RXCSRN, USB_EPX_RX_FLUSH_FIFO_Msk)
+
+/**
+ * @brief Judge RX ISO Endpoint Data Error or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't Data Error
+ * @retval 1 Is Data Error
+ */
+#define __LL_USB_EPx_IsISORXDataErr(__USB__) \
+ (READ_BIT((__USB__)->RXCSRN, USB_EPX_RX_ISO_DATA_ERR_Msk) >> USB_EPX_RX_ISO_DATA_ERR_Pos)
+
+/**
+ * @brief Judge RX ISO Endpoint FIFO Is OverRun or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't OverRun
+ * @retval 1 Is OverRun
+ */
+#define __LL_USB_EPx_IsISORXFIFOOverRun(__USB__) \
+ (READ_BIT((__USB__)->RXCSRN, USB_EPX_RX_OVER_RUN_Msk) >> USB_EPX_RX_OVER_RUN_Pos)
+
+/**
+ * @brief Clear RX ISO Endpoint OverrRun Status
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_ISORXFIFOOverRun_Clr(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_OVER_RUN_Msk)
+
+/**
+ * @brief Judge RX FIFO Full or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't Full
+ * @retval 1 Is Full
+ */
+#define __LL_USB_EPx_IsRXFIFOFull(__USB__) \
+ (READ_BIT((__USB__)->RXCSRN, USB_EPX_RX_FIFO_FULL_Msk) >> USB_EPX_RX_FIFO_FULL_Pos)
+
+/**
+ * @brief Judge Endpoint RX Packet Ready or not
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't Packet Ready
+ * @retval 1 Is Packet Ready
+ */
+#define __LL_USB_EPx_IsRXPktRdy(__USB__) \
+ (READ_BIT((__USB__)->RXCSRN, USB_EPX_RX_PKT_RDY_Msk) >> USB_EPX_RX_PKT_RDY_Pos)
+
+/**
+ * @brief Clear RX Endpoint Packet Ready Status
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_EPx_RXPktRdy_Clr(__USB__) CLEAR_BIT((__USB__)->RXCSRN, USB_EPX_RX_PKT_RDY_Msk)
+
+
+/**
+ * @brief Get Endpoint RX Counter
+ * @note Must Set Endpoint Index first Before Call This Macro Function
+ * @param __USB__ Specifies USB peripheral
+ * @return RX Counter
+ */
+#define __LL_USB_RXCount_Get(__USB__) (READ_BIT((__USB__)->RXCOUNT, USB_RX_CNT_Msk) >> USB_RX_CNT_Pos)
+
+
+/**
+ * @brief Write Single Byte to Endpoint TX FIFO
+ * @param __USB__ Specifies USB peripheral
+ * @param ep_num USB_EpNumETypeDef Type Endpoint Number
+ * @param dat Data to be Written
+ * @return None
+ */
+#define __LL_USB_EPFIFOWriteByte(__USB__, ep_num, dat) do{ (__USB__)->EP_FIFO[ep_num][0] = dat; }while(0)
+
+/**
+ * @brief Read Single Byte form Endpoint RX FIFO
+ * @param __USB__ Specifies USB peripheral
+ * @param ep_num USB_EpNumETypeDef Type Endpoint Number
+ * @return Read Byte Data
+ */
+#define __LL_USB_EPFIFOReadByte(__USB__, ep_num) ((__USB__)->EP_FIFO[ep_num][0])
+
+
+/**
+ * @brief Config DM Output Hardware
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMOutputHardware(__USB__) CLEAR_BIT((__USB__)->UCFG0, USB_DM_OE_EN_Msk)
+
+/**
+ * @brief Config DM Output Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMOutputNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DM_OE_EN_Msk | USB_DM_OE_Msk)
+
+/**
+ * @brief Disable DM Output
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMOutputDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_DP_OE_EN_Msk)
+
+/**
+ * @brief Config DP Output Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPOutputNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DP_OE_EN_Msk | USB_DP_OE_Msk)
+
+/**
+ * @brief Disable DP Output
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPOutputDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_DM_IE_EN_Msk)
+
+/**
+ * @brief Config DM Input Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMInputNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DM_IE_EN_Msk | USB_DM_IE_Msk)
+
+/**
+ * @brief Disable DM Input
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMInputDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_DP_IE_EN_Msk)
+
+/**
+ * @brief Config DP Input Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPInputNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DP_IE_EN_Msk | USB_DP_IE_Msk)
+
+/**
+ * @brief Disable DP Input
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPInputDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_DM_PD_EN_Msk)
+
+/**
+ * @brief Config DM PullDown Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMPullDownNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DM_PD_EN_Msk | USB_DM_PD_Msk)
+
+/**
+ * @brief Disable DM PullDown
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMPullDownDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_DM_PU_EN_Msk)
+
+/**
+ * @brief Config DM PullUp Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMPullUpNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DM_PU_EN_Msk | USB_DM_PU_Msk)
+
+/**
+ * @brief Disable DM PullUp
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DMPullUpDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_DP_PD_EN_Msk)
+
+/**
+ * @brief Config DP PullDown Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPPullDownNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DP_PD_EN_Msk | USB_DP_PD_Msk)
+
+/**
+ * @brief Disable DP PullDown
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPPullDownDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_DP_PU_EN_Msk)
+
+/**
+ * @brief Config DP PullUp Normal
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPPullUpNormal(__USB__) SET_BIT((__USB__)->UCFG0, USB_DP_PU_EN_Msk | USB_DP_PU_Msk)
+
+/**
+ * @brief Disable DP PullUp
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_DPPullUpDisable(__USB__) MODIFY_REG((__USB__)->UCFG0, 0x3UL<UCFG0, USB_VBUS_VALID_THRES_Msk)
+
+/**
+ * @brief Clear Vbus Above VBusValid Threshold
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_VbusValidThreshold_Clr(__USB__) CLEAR_BIT((__USB__)->UCFG0, USB_VBUS_VALID_THRES_Msk)
+
+/**
+ * @brief Set Vbus Above Vbus A-device Session Threshold
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_VbusAboveAdevSessThres_Set(__USB__) SET_BIT((__USB__)->UCFG0, USB_VBUS_A_SESS_THRES_Msk)
+
+/**
+ * @brief Clear Vbus Above Vbus A-device Session Threshold
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_VbusAboveAdevSessThres_Clr(__USB__) CLEAR_BIT((__USB__)->UCFG0, USB_VBUS_A_SESS_THRES_Msk)
+
+/**
+ * @brief Set Vbus Above Session End Threshold
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_VbusAboveSessEndThres_Set(__USB__) SET_BIT((__USB__)->UCFG0, USB_VBUS_SESS_END_THRES_Msk)
+
+/**
+ * @brief Clear Vbus Above Session End Threshold
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_VbusAboveSessEndThres_Clr(__USB__) CLEAR_BIT((__USB__)->UCFG0, USB_VBUS_SESS_END_THRES_Msk)
+
+/**
+ * @brief Set Mini-AB Connector ID Pin
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_MiniABConnectorID_Set(__USB__) SET_BIT((__USB__)->UCFG0, USB_MINI_AB_CONN_ID_Msk)
+
+/**
+ * @brief Clear Mini-AB Connector ID Pin
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_MiniABConnectorID_Clr(__USB__) CLEAR_BIT((__USB__)->UCFG0, USB_MINI_AB_CONN_ID_Msk)
+
+/**
+ * @brief Enable USB PHY
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_PHY_En(__USB__) SET_BIT((__USB__)->UCFG0, USB_PHY_EN_Msk)
+
+/**
+ * @brief Disable USB PHY
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_PHY_Dis(__USB__) CLEAR_BIT((__USB__)->UCFG0, USB_PHY_EN_Msk)
+
+
+/**
+ * @brief Enable Interrupt Send to CPU
+ * @param __USB__ Specifies USB peripheral
+ * @param int_bit_mask Interrupt BitMask to be Enable
+ * @return None
+ */
+#define __LL_USB_INTSendToCPU_En(__USB__, int_bit_mask) SET_BIT((__USB__)->UCFG1, int_bit_mask)
+
+/**
+ * @brief Disable Interrupt Send to CPU
+ * @param __USB__ Specifies USB peripheral
+ * @param int_bit_mask Interrupt BitMask to be Disable
+ * @return None
+ */
+#define __LL_USB_INTSendToCPU_Dis(__USB__, int_bit_mask) CLEAR_BIT((__USB__)->UCFG1, int_bit_mask)
+
+
+/**
+ * @brief Get SendState
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Reserved
+ * @retval 1 Setup
+ * @retval 2 Out
+ * @retval 3 IN
+ */
+#define __LL_USB_SendState_Get(__USB__) (READ_BIT((__USB__)->UCFG2, USB_SEND_STATE_Msk) >> USB_SEND_STATE_Pos)
+
+/**
+ * @brief Judge Is IN Packet or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't IN Packet
+ * @retval 1 Is IN Packet
+ */
+#define __LL_USB_IsInPacket(__USB__) (READ_BIT((__USB__)->UCFG2, USB_IN_STATE_Msk) >> USB_IN_STATE_Pos)
+
+/**
+ * @brief Judge Is OUT Packet or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't OUT Packet
+ * @retval 1 Is OUT Packet
+ */
+#define __LL_USB_IsOutPacket(__USB__) (READ_BIT((__USB__)->UCFG2, USB_OUT_STATE_Msk) >> USB_OUT_STATE_Pos)
+
+/**
+ * @brief Judge Is Setup Packet or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't Setup Packet
+ * @retval 1 Is Setup Packet
+ */
+#define __LL_USB_IsSetupPacket(__USB__) (READ_BIT((__USB__)->UCFG2, USB_SETUP_STATE_Msk) >> USB_SETUP_STATE_Pos)
+
+/**
+ * @brief Set Debounce Max
+ * @param __USB__ Specifies USB peripheral
+ * @param debouce debouce to be set
+ * @return None
+ */
+#define __LL_USB_DebouceMax_Set(__USB__, debouce) \
+ MODIFY_REG((__USB__)->UCFG2, USB_DEBOUCE_MAX_Msk, ((debouce & 0x3FFFUL) << USB_DEBOUCE_MAX_Pos))
+
+/**
+ * @brief Enable Disconnect Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_Disconn_Int_En(__USB__) SET_BIT((__USB__)->UCFG2, USB_DISCONN_INT_EN_Msk)
+
+/**
+ * @brief Disable Disconnect Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_Disconn_Int_Dis(__USB__) CLEAR_BIT((__USB__)->UCFG2, USB_DISCONN_INT_EN_Msk)
+
+/**
+ * @brief Judge Is Disconnect Interrupt or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't Disconnect Interrupt
+ * @retval 1 Is Disconnect Interrupt
+ */
+#define __LL_USB_IsDisconn(__USB__) (READ_BIT((__USB__)->UCFG2, USB_DISCONN_INT_STA_Msk) >> USB_DISCONN_INT_STA_Pos)
+
+/**
+ * @brief Clear Disconnect Interrupt Pending
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_Disconn_Clr(__USB__) SET_BIT((__USB__)->UCFG2, USB_DISCONN_INT_STA_Msk)
+
+/**
+ * @brief Enable Connect Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_Conn_Int_En(__USB__) SET_BIT((__USB__)->UCFG2, USB_CONN_INT_EN_Msk)
+
+/**
+ * @brief Disable Connect Interrupt
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_Conn_Int_Dis(__USB__) CLEAR_BIT((__USB__)->UCFG2, USB_CONN_INT_EN_Msk)
+
+/**
+ * @brief Judge Is Connect Interrupt or not
+ * @param __USB__ Specifies USB peripheral
+ * @retval 0 Isn't Connect Interrupt
+ * @retval 1 Is Connect Interrupt
+ */
+#define __LL_USB_IsConn(__USB__) (READ_BIT((__USB__)->UCFG2, USB_CONN_INT_STA_Msk) >> USB_CONN_INT_STA_Pos)
+
+/**
+ * @brief Clear Connect Interrupt Pending
+ * @param __USB__ Specifies USB peripheral
+ * @return None
+ */
+#define __LL_USB_Conn_Clr(__USB__) SET_BIT((__USB__)->UCFG2, USB_CONN_INT_STA_Msk)
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Types USB LL Exported Types
+ * @brief USB LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief USB Endpoint Number
+ */
+typedef enum {
+ EP_NUM_0 = 0, /*!< Endpoint Number 0 */
+ EP_NUM_1 = 1, /*!< Endpoint Number 1 */
+ EP_NUM_2 = 2, /*!< Endpoint Number 2 */
+ EP_NUMS = 3, /*!< Endpoint Numbers */
+} USB_EpNumETypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USB_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_USB_Init(USB_TypeDef *Instance);
+LL_StatusETypeDef LL_USB_DeInit(USB_TypeDef *Instance);
+void LL_USB_MspInit(USB_TypeDef *Instance);
+void LL_USB_MspDeInit(USB_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup USB_LL_Exported_Functions_Group2
+ * @{
+ */
+void LL_USB_CtrlIRQHandler(USB_TypeDef *Instance);
+void LL_USB_CtrlSuspendCallback(USB_TypeDef *Instance);
+void LL_USB_CtrlResumeCallback(USB_TypeDef *Instance);
+void LL_USB_CtrlResetCallback(USB_TypeDef *Instance);
+void LL_USB_CtrlSofCallback(USB_TypeDef *Instance);
+void LL_USB_CtrlSessEndCallback(USB_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup USB_LL_Exported_Functions_Group3
+ * @{
+ */
+void LL_USB_DetIRQHandler(USB_TypeDef *Instance);
+void LL_USB_DetConnectCallback(USB_TypeDef *Instance);
+void LL_USB_DetDisonnectCallback(USB_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup USB_LL_Exported_Functions_Group4
+ * @{
+ */
+void LL_USB_EpIRQHandler(USB_TypeDef *Instance);
+void LL_USB_Ep0SetupCallback(USB_TypeDef *Instance);
+void LL_USB_Ep0InCallback(USB_TypeDef *Instance);
+void LL_USB_Ep0OutCallback(USB_TypeDef *Instance);
+void LL_USB_Ep1InCallback(USB_TypeDef *Instance);
+void LL_USB_Ep1OutCallback(USB_TypeDef *Instance);
+void LL_USB_Ep2InCallback(USB_TypeDef *Instance);
+void LL_USB_Ep2OutCallback(USB_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_USB_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_wwdg.h b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_wwdg.h
new file mode 100644
index 0000000000..b78da632f3
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/tae32f53xx_ll_wwdg.h
@@ -0,0 +1,296 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_wwdg.h
+ * @author MCD Application Team
+ * @brief Header file of WWDG LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_WWDG_H_
+#define _TAE32F53XX_LL_WWDG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll_def.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG_LL
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Types WWDG LL Exported Types
+ * @brief WWDG LL Exported Types
+ * @{
+ */
+
+/**
+ @brief WWDG Early Wakeup Interrupt Mode
+ */
+typedef enum {
+ WWDG_EWI_DISABLE = 0x00000000U, /*!< Rsest */
+ WWDG_EWI_ENABLE = WWDG_CR_EWIE, /*!< Early Wakeup Interrupt */
+} WWDG_EWIETypeDef;
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct __WWDG_InitTypeDef {
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter must be a number Min_Data = 0x00 and Max_Data = 0xFFFF */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number Min_Data = 0x40 and Max_Data = 0xFFFF */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0xFFFF */
+
+ WWDG_EWIETypeDef EWIMode; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. */
+} WWDG_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG LL Exported Constants
+ * @brief WWDG LL Exported Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+ * @{
+ */
+#define WWDG_IT_EWIE WWDG_CR_EWIE /*!< Early wakeup interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF WWDG_ISR_EWIF /*!< Early wakeup interrupt flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG LL Exported Macros
+ * @brief WWDG LL Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the WWDG peripheral.
+ * @param __INSTANCE__ WWDG peripheral
+ * @retval None
+ */
+#define __LL_WWDG_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->CR, WWDG_CR_WEN)
+
+/**
+ * @brief Disable the WWDG peripheral.
+ * @param __INSTANCE__ WWDG peripheral
+ * @retval None
+ */
+#define __LL_WWDG_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->CR, WWDG_CR_WEN)
+
+/**
+ * @brief Enable the specified WWDG interrupt.
+ * @param __INSTANCE__ WWDG peripheral
+ * @param __INTERRUPT__ specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWIE: Early wakeup interrupt
+ * @retval None
+ */
+#define __LL_WWDG_IT_ENABLE(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->CR, (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified WWDG interrupt.
+ * @param __INSTANCE__ WWDG peripheral
+ * @param __INTERRUPT__ specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWIE: Early wakeup interrupt
+ * @retval None
+ */
+#define __LL_WWDG_IT_DISABLE(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->CR, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified WWDG flag is set or not.
+ * @param __INSTANCE__ WWDG peripheral
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+
+#define __LL_WWDG_GET_FLAG(__INSTANCE__, __FLAG__) ((READ_BIT((__INSTANCE__)->ISR, (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+/**
+ * @brief Clears the WWDG's pending flags.
+ * @param __INSTANCE__ WWDG peripheral
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+
+#define __LL_WWDG_CLEAR_FLAG(__INSTANCE__, __FLAG__) WRITE_REG((__INSTANCE__)->ISR, (__FLAG__))
+
+/**
+ * @brief Checks if the specified WWDG interrupt source is enabled or disabled.
+ * @param __INSTANCE__ WWDG peripheral
+ * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWIE: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (SET or RESET).
+ */
+#define __LL_WWDG_CHECK_IT_SOURCE(__INSTANCE__, __INTERRUPT__) \
+ ((READ_BIT((__INSTANCE__)->CR, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Get the WWDG Counter Register value on runtime.
+ * @param __INSTANCE__ WWDG peripheral
+ * @retval 16-bit value of the WWDG counter register (WWDG_CVR)
+ */
+#define __LL_WWDG_GET_COUNTER(__INSTANCE__) (READ_REG((__INSTANCE__)->CVR))
+
+/**
+ * @brief Set the WWDG Counter Register value to refresh WWDG.
+ * @param __INSTANCE__ WWDG peripheral
+ * @param __COUNTER__ specifies WWDG counter value to refresh with
+ * @retval None
+ */
+#define __LL_WWDG_SET_COUNTER(__INSTANCE__, __COUNTER__) WRITE_REG((__INSTANCE__)->CVR, __COUNTER__)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup WWDG_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup WWDG_LL_Exported_Functions_Group1
+ * @{
+ */
+LL_StatusETypeDef LL_WWDG_Init(WWDG_TypeDef *Instance, WWDG_InitTypeDef *Init);
+LL_StatusETypeDef LL_WWDG_DeInit(WWDG_TypeDef *Instance);
+void LL_WWDG_MspInit(WWDG_TypeDef *Instance);
+void LL_WWDG_MspDeInit(WWDG_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/** @addtogroup WWDG_LL_Exported_Functions_Group2
+ * @{
+ */
+LL_StatusETypeDef LL_WWDG_Refresh(WWDG_TypeDef *Instance, uint16_t Counter);
+/**
+ * @}
+ */
+
+
+/** @addtogroup WWDG_LL_Exported_Functions_Interrupt
+ * @{
+ */
+void LL_WWDG_IRQHandler(WWDG_TypeDef *Instance);
+void LL_WWDG_EarlyWakeUpCallback(WWDG_TypeDef *Instance);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Private_Macros WWDG LL Private Macros
+ * @brief WWDG LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is WWDG prescaler or not
+ * @param __PRESCALER__ prescaler to judge
+ * @retval 0 isn't WWDG prescaler
+ * @retval 1 is WWDG prescaler
+ */
+#define IS_WWDG_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFUL)
+
+/**
+ * @brief Judge is WWDG window or not
+ * @param __WINDOW__ window to judge
+ * @retval 0 isn't WWDG window
+ * @retval 1 is WWDG window
+ */
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFFFUL)
+
+/**
+ * @brief Judge is WWDG counter or not
+ * @param __COUNTER__ counter to judge
+ * @retval 0 isn't WWDG counter
+ * @retval 1 is WWDG counter
+ */
+#define IS_WWDG_COUNTER(__COUNTER__) ((__COUNTER__) <= 0xFFFFUL)
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_WWDG_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll.c
new file mode 100644
index 0000000000..103398d152
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll.c
@@ -0,0 +1,529 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll.c
+ * @author MCD Application Team
+ * @brief LL module driver.
+ * This is the common part of the LL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common LL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the LL.
+ [..]
+ The LL contains two APIs' categories:
+ (+) Common LL APIs
+ (+) Services LL APIs
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "TAE32F53xx LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @defgroup TAE32F53xx_LL_Driver TAE32F53xx LL Driver
+ * @brief TAE32F53xx LL Driver
+ * @{
+ */
+
+/** @defgroup TAE32F53xx_LL TAE32F53xx LL
+ * @brief TAE32F53xx LL
+ * @{
+ */
+
+#ifdef LL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TAE32F53xx_LL_Private_Macros TAE32F53xx LL Private Macros
+ * @brief TAE32F53xx LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief Judge is Tick freq or not
+ * @param FREQ Freq to be judged
+ * @retval 0 isn't Tick freq
+ * @retval 1 is Tick freq
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == LL_TICK_FREQ_10HZ) || \
+ ((FREQ) == LL_TICK_FREQ_100HZ) || \
+ ((FREQ) == LL_TICK_FREQ_1KHZ))
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TAE32F53xx_LL_Private_Variables TAE32F53xx LL Private Variables
+ * @brief TAE32F53xx LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief SysTick counter
+ */
+__IO uint32_t uwTick;
+
+/**
+ * @brief SysTick interrupt priority
+ */
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS) - 1;
+
+/**
+ * @brief SysTick interrupt frequency
+ */
+LL_TickFreqETypeDef uwTickFreq = LL_TICK_FREQ_DEFAULT;
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TAE32F53xx_LL_Exported_Functions TAE32F53xx LL Exported Functions
+ * @brief TAE32F53xx LL Exported Functions
+ * @{
+ */
+
+/** @defgroup TAE32F53xx_LL_Exported_Functions_Group1 TAE32F53xx Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface, the NVIC allocation and initial clock
+ configuration. It initializes the systick also when timeout is needed
+ and the backup domain when enabled.
+ (+) de-Initializes common part of the LL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (LL_InitTick ()) is called automatically
+ at the beginning of the program after reset by LL_Init()
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if LL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __WEAK
+ to make override possible in case of other implementations in user file.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is used to initialize the LL Library; it must be the first
+ * instruction to be executed in the main program (before to call any other
+ * LL function), it performs the following:
+ * Configure the Flash prefetch.
+ * Configures the SysTick to generate an interrupt each 1 millisecond,
+ * which is clocked by the LSI (at this stage, the clock is not yet
+ * configured and thus the system is running from the internal LSI at 32 KHz).
+ * Set NVIC Group Priority to 4.
+ * Calls the LL_MspInit() callback function defined in user file
+ * "tae32f53xx_ll_msp.c" to do the global low level hardware initialization
+ *
+ * @note SysTick is used as time base for the LL_Delay() function, the application
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct LL operation.
+ * @param None
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_Init(void)
+{
+#ifdef LL_FLASH_MODULE_ENABLED
+ /* Configure Flash prefetch */
+#if PREFETCH_ENABLE
+ /* Prefetch enable */
+ __LL_FLASH_I_BUS_PREFETCH_ENABLE();
+ __LL_FLASH_D_BUS_PREFETCH_ENABLE();
+#else
+ /* Prefetch disable */
+ __LL_FLASH_I_BUS_PREFETCH_DISABLE();
+ __LL_FLASH_D_BUS_PREFETCH_DISABLE();
+#endif /* PREFETCH_ENABLE */
+#endif /* LL_FLASH_MODULE_ENABLED */
+
+ /* Set Interrupt Group Priority */
+ LL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_3);
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is LSI) */
+ LL_InitTick(TICK_INT_PRIORITY);
+
+ /* Init the low level hardware */
+ LL_MspInit();
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the LL and stops the systick of time base.
+ * @note This function is optional.
+ * @param None
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ LL_SYSCTRL_AllPeriphRstAssert();
+
+ /* De-Init the low level hardware */
+ LL_MspDeInit();
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Initialize the MSP.
+ * @param None
+ * @retval None
+ */
+__WEAK void LL_MspInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @param None
+ * @retval None
+ */
+__WEAK void LL_MspDeInit(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by LL_Init().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if LL_Delay() is called from a peripheral ISR process,
+ * The SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __WEAK to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval LL status
+ */
+__WEAK LL_StatusETypeDef LL_InitTick(uint32_t TickPriority)
+{
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (LL_SYSTICK_Config(LL_SYSCTRL_SysclkGet() / (1000U / uwTickFreq)) > 0U) {
+ return LL_ERROR;
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) {
+ LL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ } else {
+ return LL_ERROR;
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup TAE32F53xx_LL_Exported_Functions_Group2 TAE32F53xx LL Control functions
+ * @brief TAE32F53xx LL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### LL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the LL API driver version
+ (+) Get the unique device identifier
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in SysTick ISR.
+ * @note This function is declared as __WEAK to be overwritten in case of other
+ * implementations in user file.
+ * @param None
+ * @retval None
+ */
+__WEAK void LL_IncTick(void)
+{
+ uwTick += uwTickFreq;
+}
+
+/**
+ * @brief Provides a tick value in millisecond
+ * @note This function is declared as __WEAK to be overwritten in case of other
+ * implementations in user file.
+ * @param None
+ * @retval tick value
+ */
+__WEAK uint32_t LL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function returns a tick priority
+ * @param None
+ * @retval tick priority
+ */
+uint32_t LL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq
+ * @param Freq New tick freq
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_SetTickFreq(LL_TickFreqETypeDef Freq)
+{
+ LL_StatusETypeDef status = LL_OK;
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq) {
+ /* Apply the new tick Freq */
+ status = LL_InitTick(uwTickPrio);
+
+ if (status == LL_OK) {
+ uwTickFreq = Freq;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Get tick frequency
+ * @param None
+ * @retval tick period in Hz
+ */
+LL_TickFreqETypeDef LL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note This function is declared as __WEAK to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__WEAK void LL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = LL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < LL_MAX_DELAY) {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while ((LL_GetTick() - tickstart) < wait) {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once LL_SuspendTick()
+ * is called, the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __WEAK to be overwritten in case of other
+ * implementations in user file.
+ * @param None
+ * @retval None
+ */
+__WEAK void LL_SuspendTick(void)
+{
+ /* Disable SysTick Interrupt */
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once LL_ResumeTick()
+ * is called, the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __WEAK to be overwritten in case of other
+ * implementations in user file.
+ * @param None
+ * @retval None
+ */
+__WEAK void LL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Get the LL revision
+ * @param None
+ * @retval version 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t LL_GetHalVersion(void)
+{
+ return __TAE32F53xx_LL_VERSION;
+}
+
+/**
+ * @brief Returns words of the device unique identifier (UID based on 128 bits)
+ * @param UID[] device unique identifier store buffer
+ * @return None
+ */
+void LL_GetUID(uint32_t *UID[4])
+{
+ //:TODO: return the device UID
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup TAE32F53xx_LL_Exported_Functions_Group3 TAE32F53xx LL Misc Functions
+ * @brief TAE32F53xx LL Misc Functions
+ * @{
+ */
+
+/**
+ * @brief LL Show Platform Information
+ * @param None
+ * @return None
+ */
+void LL_ShowInfo(void)
+{
+ DBG_LogRaw("\n======================== Platform Information =======================\n");
+
+ DBG_LogRaw("Tai-Action TAE32F53xx SDK "SDK_STAGE_STR" V%d.%d.%d "__DATE__" "__TIME__"\n\n", \
+ __TAE32F53xx_LL_VERSION_MAIN, __TAE32F53xx_LL_VERSION_SUB1, __TAE32F53xx_LL_VERSION_SUB2);
+
+ DBG_LogRaw("CPU clock %9u Hz\n", LL_SYSCTRL_SysclkGet());
+ DBG_LogRaw("AHB clock %9u Hz\n", LL_SYSCTRL_AHBClkGet());
+ DBG_LogRaw("APB0 clock %9u Hz\n", LL_SYSCTRL_APB0ClkGet());
+ DBG_LogRaw("APB1 clock %9u Hz\n", LL_SYSCTRL_APB1ClkGet());
+
+ DBG_LogRaw("HSE clock %9u Hz\n", HSE_VALUE);
+ DBG_LogRaw("HSI clock %9u Hz\n", HSI_VALUE);
+ DBG_LogRaw("LSI clock %9u Hz\n", LSI_VALUE);
+
+ DBG_LogRaw("=====================================================================\n\n");
+}
+
+/**
+ * @brief Delay 1ms
+ * @param ms The time to delay in 1ms Unit
+ * @return None
+ */
+void delay_ms(uint32_t ms)
+{
+ LL_Delay(ms);
+}
+
+/**
+ * @brief printf array
+ * @param ptr printf array pointer
+ * @param len array len
+ * @retval None
+ */
+void printf_array(void *ptr, uint32_t len)
+{
+ uint32_t cnt = 0;
+ uint8_t *p_ptr = (uint8_t *)ptr;
+
+ while (len--) {
+ DBG_LogRaw("%02x ", *p_ptr);
+ cnt++;
+ p_ptr++;
+
+ if (!(cnt & 0x0f)) {
+ DBG_LogRaw("\r\n");
+ }
+ }
+
+ if ((cnt & 0x0f) != 0x0f) {
+ DBG_LogRaw("\r\n");
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_adc.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_adc.c
new file mode 100644
index 0000000000..48ff73d4f8
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_adc.c
@@ -0,0 +1,1390 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_adc.c
+ * @author MCD Application Team
+ * @brief ADC LL module driver.
+ *
+ ******************************************************************************
+ @verbatim
+ * ==============================================================================
+ * ##### ADC peripheral features #####
+ * ==============================================================================
+ * [..]
+ * (+) Interrupt generation at the end of regular conversion and in case of
+ * analog watchdog or overrun events.
+ *
+ * (+) Single and continuous conversion modes.
+ *
+ * (+) Scan mode for conversion of several channels sequentially.
+ *
+ * (+) Data alignment with in-built data coherency.
+ *
+ * (+) Programmable sampling time (channel wise)
+ *
+ * (+) External trigger (timer or EXTI) with configurable polarity
+ *
+ * (+) DMA request generation for transfer of conversions data of regular group.
+ *
+ * (+) Configurable delay between conversions in Dual interleaved mode.
+ *
+ * (+) ADC channels selectable single/differential input.
+ *
+ * (+) ADC calibration shared on 4 group offset & gain compensation instances.
+ *
+ * (+) ADC conversion of regular group.
+ *
+ * (+) ADC supply requirements: 1.62 V to 3.6 V.
+ *
+ * (+) ADC single input range: 0 to Vref. Vref is 3V
+ *
+ * (+) ADC Differential input range: from Vref- (connected to IN-) to Vref+ (connected to
+ * IN+ or to an external voltage reference).
+ @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+#include "string.h"
+#include "stdlib.h"
+
+
+#define DBG_TAG "ADC LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup ADC_LL ADC LL
+ * @brief ADC LL module driver
+ * @{
+ */
+
+#ifdef LL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Variables ADC LL Private Variables
+ * @brief ADC LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief ADC Calibration temp offset param
+ */
+volatile static int16_t temp_offset = 0;
+
+/**
+ * @brief ADC Calibration temp gain param
+ */
+volatile static uint16_t temp_gain = 0;
+
+/**
+ * @brief ADC Calibration Data struct param
+ */
+volatile ADC_CalibrationDataTypeDef pCoef = {0};
+
+/**
+ * @brief ADC Calibration Data static param
+ */
+static const uint32_t Calib_check_data[3] = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};
+
+/**
+ * @brief ADC Calibration read data array
+ */
+static uint32_t Calib_read_data[3] = {0};
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ADC_LL_Private_Functions ADC LL Private Functions
+ * @brief ADC LL Private Functions
+ * @{
+ */
+static void LL_ADC_ReadCoef(void);
+static void LL_ADC_OverSamp_Mode(ADC_TypeDef *Instance, int16_t offset);
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC LL Exported Functions
+ * @brief ADC LL Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * @param Instance ADC instance
+ * @param ADC_InitStruct Pointer to a @ref ADC_REG_InitTypeDef structure
+ * @retval An LL_StatusETypeDef enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+LL_StatusETypeDef LL_ADC_Init(ADC_TypeDef *Instance, ADC_InitTypeDef *ADC_InitStruct)
+{
+ LL_StatusETypeDef status = LL_OK;
+ /*hardware level Initialize*/
+ LL_ADC_MspInit(Instance);
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+ assert_param(IS_ADC_SYNCHRONIZATION(ADC_InitStruct->Synchronization));
+ assert_param(IS_ADC_ANOLOGSET(ADC_InitStruct->AnologCfg));
+ assert_param(IS_ADC_OVR_DATA_BEHAVIOR(ADC_InitStruct->Overrun));
+
+ /*Check whether the SOC has been calibrated*/
+ LL_ADC_ReadCoef();
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (__LL_ADC_REG_IsConversionOngoing(Instance) == 0UL) {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC Synchronization */
+ MODIFY_REG(Instance->CR1, ADC_CR1_SYNCEN, ADC_InitStruct->Synchronization);
+
+ //WRITE_REG(Instance->CR2, ADC_InitStruct->AnologCfg);
+ /*only ADC0 valid paramter*/
+ //WRITE_REG(ADC0->CR2, ADC_InitStruct->AnologCfg);
+
+ if (Instance == ADC0) {
+ WRITE_REG(Instance->CR2, ADC_InitStruct->AnologCfg);
+ } else if (Instance == ADC1) {
+ /*only ADC0 valid paramter*/
+ WRITE_REG(Instance->CR2, ADC_InitStruct->AnologCfg);
+ WRITE_REG(ADC0->CR2, ADC_InitStruct->AnologCfg);
+ }
+
+ while (!(Instance->ISR & BIT(8)));
+
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+
+ if (ADC_InitStruct->RegOversampMode && !(ADC_InitStruct->InjOversampMode)) {
+ SET_BIT(Instance->CR1, ADC_CR1_ROVSE);
+ } else if (ADC_InitStruct->InjOversampMode && !(ADC_InitStruct->RegOversampMode)) {
+ SET_BIT(Instance->CR1, ADC_CR1_JOVSE);
+ } else {
+ SET_BIT(Instance->CR1, ADC_CR1_ROVSE | ADC_CR1_JOVSE);
+ }
+
+ assert_param(IS_ADC_OVERSAMPMODE_SET(ADC_InitStruct->OverSampling.OverSampResetMode));
+ assert_param(IS_ADC_TRIGOVERSAMP(ADC_InitStruct->OverSampling.TrigOverSamp));
+ assert_param(IS_ADC_OVERSAMPSHIFT(ADC_InitStruct->OverSampling.OverSampShiftBit));
+ assert_param(IS_ADC_OVERSAMPRATIO(ADC_InitStruct->OverSampling.OverSampRatio));
+
+ MODIFY_REG(Instance->CR1,
+ ADC_CR1_ROVSM
+ | ADC_CR1_TROVS
+ | ADC_CR1_OVSS
+ | ADC_CR1_OVSR
+ | ADC_CR1_OVRMOD
+ ,
+ ADC_InitStruct->OverSampling.OverSampResetMode
+ | ADC_InitStruct->OverSampling.TrigOverSamp
+ | ADC_InitStruct->OverSampling.OverSampShiftBit
+ | ADC_InitStruct->OverSampling.OverSampRatio
+ | ADC_InitStruct->Overrun
+ );
+ /*Normal interrupt config*/
+ WRITE_REG(Instance->IER, ADC_InitStruct->NormInterrupt);
+
+ } else {
+ /* Initialization error: ADC instance is not disabled. */
+ status = LL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * @note If this functions returns error status, it means that ADC instance
+ * is in an unknown state.
+ * In this case, perform a hard reset using high level
+ * clock source RCC ADC reset.
+ * @param Instance ADC instance
+ * @retval An LL_StatusETypeDef enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+LL_StatusETypeDef LL_ADC_DeInit(ADC_TypeDef *Instance)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+
+ /* Disable ADC instance if not already disabled. */
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ __LL_ADC_REG_SetTriggerSource(Instance, ADC_REG_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group regular. */
+ if (__LL_ADC_REG_IsConversionOngoing(Instance) != 0UL) {
+ if (__LL_ADC_REG_IsStopConversionOngoing(Instance) == 0UL) {
+ __LL_ADC_REG_StopConversion(Instance);
+ }
+ }
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ __LL_ADC_INJ_SetTriggerSource(Instance, ADC_INJ_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group injected. */
+ if (__LL_ADC_INJ_IsConversionOngoing(Instance) != 0UL) {
+ if (__LL_ADC_INJ_IsStopConversionOngoing(Instance) == 0UL) {
+ __LL_ADC_INJ_StopConversion(Instance);
+ }
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ if (READ_BIT(Instance->CR0, (ADC_CR0_JADSTP | ADC_CR0_ADSTP | ADC_CR0_JADSTART | ADC_CR0_ADSTART)) == 0UL) {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ CLEAR_BIT(Instance->IER,
+ (ADC_IER_ADRDYIE
+ | ADC_IER_EOCIE
+ | ADC_IER_EOSIE
+ | ADC_IER_OVRIE
+ | ADC_IER_EOSMPIE
+ | ADC_IER_JEOCIE
+ | ADC_IER_JEOSIE
+ | ADC_IER_AWD0IE
+ | ADC_IER_AWD1IE
+ | ADC_IER_AWD2IE
+ )
+ );
+
+ /* Reset register ISR */
+ SET_BIT(Instance->ISR,
+ (ADC_ISR_ADRDY
+ | ADC_ISR_EOC
+ | ADC_ISR_EOS
+ | ADC_ISR_OVR
+ | ADC_ISR_EOSMP
+ | ADC_ISR_JEOC
+ | ADC_ISR_JEOS
+ | ADC_ISR_AWD0
+ | ADC_ISR_AWD1
+ | ADC_ISR_AWD2
+ )
+ );
+ /* Reset register SIER */
+ CLEAR_BIT(Instance->SIER, (ADC_SIER_CHANNEL));
+ /* Reset register SISR */
+ SET_BIT(Instance->SISR, (ADC_SISR_CHANNEL));
+
+ /* Reset register HIER */
+ CLEAR_BIT(Instance->HIER, (ADC_HIER_CHANNEL));
+ /* Reset register SISR */
+ SET_BIT(Instance->HISR, (ADC_HISR_CHANNEL));
+
+ /* Reset register SIER */
+ CLEAR_BIT(Instance->FIER, (ADC_FIER_CHANNEL));
+ /* Reset register SISR */
+ SET_BIT(Instance->FISR, (ADC_FISR_CHANNEL));
+
+ /* Reset register CR1 */
+ CLEAR_BIT(Instance->CR1,
+ (ADC_CR1_SYNCEN | ADC_CR1_JAUTO | ADC_CR1_JDISCEN
+ | ADC_CR1_DISCNUM | ADC_CR1_DISCEN | ADC_CR1_CONT
+ | ADC_CR1_OVRMOD | ADC_CR1_ROVSM | ADC_CR1_TROVS
+ | ADC_CR1_OVSS | ADC_CR1_OVSR | ADC_CR1_JOVSE
+ | ADC_CR1_ROVSE)
+ );
+
+ /* Reset register CR2 */
+ CLEAR_BIT(Instance->CR2,
+ (ADC_CR2_ISEL | ADC_CR2_TBOMOD | ADC_CR2_TBIMOD
+ | ADC_CR2_TB_EN | ADC_CR2_CH_EN | ADC_CR2_FADC_EN
+ | ADC_CR2_REF_EN | ADC_CR2_BIAS_EN)
+ );
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(Instance->DIFSEL, (ADC_DIFSEL_DIFSEL));
+
+ /* Reset register SMPR0 */
+ CLEAR_BIT(Instance->SMPR0,
+ (ADC_SMPR0_SMP7 | ADC_SMPR0_SMP6 | ADC_SMPR0_SMP5
+ | ADC_SMPR0_SMP4 | ADC_SMPR0_SMP3 | ADC_SMPR0_SMP2
+ | ADC_SMPR0_SMP1 | ADC_SMPR0_SMP0)
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(Instance->SMPR1, (ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 | ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8));
+
+ /* Reset register CALR0 */
+ CLEAR_BIT(Instance->SMPR0,
+ (ADC_CALR0_CAL7 | ADC_CALR0_CAL6 | ADC_CALR0_CAL5
+ | ADC_CALR0_CAL4 | ADC_CALR0_CAL3 | ADC_CALR0_CAL2
+ | ADC_CALR0_CAL1 | ADC_CALR0_CAL0)
+ );
+
+ /* Reset register CALR1 */
+ CLEAR_BIT(Instance->SMPR1, (ADC_CALR1_CAL11 | ADC_CALR1_CAL10 | ADC_CALR1_CAL9 | ADC_CALR1_CAL8));
+
+ /* Reset register AWD0CR TR0 */
+ CLEAR_BIT(Instance->AWDCR[0], ADC_AWD0CR_AWD0FILT | ADC_AWD0CR_AWD0CH);
+ CLEAR_BIT(Instance->TR[0], ADC_TR0_HT0 | ADC_TR0_LT0);
+
+ /* Reset register AWD1CR TR1 */
+ CLEAR_BIT(Instance->AWDCR[1], ADC_AWD1CR_AWD1FILT | ADC_AWD1CR_AWD1CH);
+ CLEAR_BIT(Instance->TR[1], ADC_TR1_HT1 | ADC_TR1_LT1);
+
+ /* Reset register AWD2CR TR2 */
+ CLEAR_BIT(Instance->AWDCR[2], ADC_AWD2CR_AWD2FILT | ADC_AWD2CR_AWD2CH);
+ CLEAR_BIT(Instance->TR[2], ADC_TR2_HT2 | ADC_TR2_LT2);
+
+ /* Reset register SQR0*/
+ CLEAR_BIT(Instance->SQR0,
+ (ADC_SQR0_SQ8 | ADC_SQR0_SQ7 | ADC_SQR0_SQ6
+ | ADC_SQR0_SQ5 | ADC_SQR0_SQ4 | ADC_SQR0_SQ3
+ | ADC_SQR0_SQ2 | ADC_SQR0_SQ1)
+ );
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(Instance->SQR1,
+ (ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14
+ | ADC_SQR1_SQ13 | ADC_SQR1_SQ12 | ADC_SQR1_SQ11
+ | ADC_SQR1_SQ10 | ADC_SQR1_SQ9)
+ );
+
+ /* Reset register LR */
+ CLEAR_BIT(Instance->LR, (ADC_LR_LEN | ADC_LR_EXTEN | ADC_LR_EXTSEL));
+
+ /* Reset register JSQR */
+ CLEAR_BIT(Instance->JSQR, ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1);
+
+ /* Reset register JLR */
+ CLEAR_BIT(Instance->JLR, (ADC_JLR_JLEN | ADC_JLR_JEXTSEL | ADC_JLR_JEXTEN));
+
+ /* Reset register DR */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register OFR0 */
+ CLEAR_BIT(Instance->OFR[0], ADC_OFR0_OFFSET);
+ /* Reset register OFR1 */
+ CLEAR_BIT(Instance->OFR[1], ADC_OFR1_OFFSET);
+ /* Reset register OFR2 */
+ CLEAR_BIT(Instance->OFR[2], ADC_OFR2_OFFSET);
+ /* Reset register OFR3 */
+ CLEAR_BIT(Instance->OFR[3], ADC_OFR3_OFFSET);
+
+ /* Reset register GCR0 */
+ CLEAR_BIT(Instance->GCR[0], ADC_GCR0_GAIN);
+ /* Reset register GCR1 */
+ CLEAR_BIT(Instance->GCR[1], ADC_GCR1_GAIN);
+ /* Reset register GCR2 */
+ CLEAR_BIT(Instance->GCR[2], ADC_GCR2_GAIN);
+ /* Reset register GCR3 */
+ CLEAR_BIT(Instance->GCR[3], ADC_GCR3_GAIN);
+
+ /* Reset register DOFR0 */
+ CLEAR_BIT(Instance->DOFR[0], ADC_DOFR0_OFFSET);
+ /* Reset register DOFR1 */
+ CLEAR_BIT(Instance->DOFR[1], ADC_DOFR1_OFFSET);
+ /* Reset register DOFR2 */
+ CLEAR_BIT(Instance->DOFR[2], ADC_DOFR2_OFFSET);
+ /* Reset register DOFR3 */
+ CLEAR_BIT(Instance->DOFR[3], ADC_DOFR3_OFFSET);
+
+ /* Reset register DGCR0 */
+ CLEAR_BIT(Instance->DGCR[0], ADC_DGCR0_GAIN);
+ /* Reset register DGCR1 */
+ CLEAR_BIT(Instance->DGCR[1], ADC_DGCR1_GAIN);
+ /* Reset register DGCR2 */
+ CLEAR_BIT(Instance->DGCR[2], ADC_DGCR2_GAIN);
+ /* Reset register DGCR3 */
+ CLEAR_BIT(Instance->DGCR[3], ADC_DGCR3_GAIN);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register ECR0 */
+ CLEAR_BIT(Instance->ECR[0], ADC_ECR0_ADSRC | ADC_ECR0_PSRCU | ADC_ECR0_PSRCD
+ | ADC_ECR0_AWD2SEL | ADC_ECR0_AWD1SEL | ADC_ECR0_AWD0SEL);
+
+ /* Reset register ECR1 */
+ CLEAR_BIT(Instance->ECR[1], ADC_ECR1_ADSRC | ADC_ECR1_PSRCU | ADC_ECR1_PSRCD
+ | ADC_ECR1_AWD2SEL | ADC_ECR1_AWD1SEL | ADC_ECR1_AWD0SEL);
+
+ /* Reset register ECR2 */
+ CLEAR_BIT(Instance->ECR[2], ADC_ECR2_ADSRC | ADC_ECR2_PSRCU | ADC_ECR2_PSRCD
+ | ADC_ECR2_AWD2SEL | ADC_ECR2_AWD1SEL | ADC_ECR2_AWD0SEL);
+
+ /* Reset register ECR3 */
+ CLEAR_BIT(Instance->ECR[3], ADC_ECR3_ADSRC | ADC_ECR3_PSRCU | ADC_ECR3_PSRCD
+ | ADC_ECR3_AWD2SEL | ADC_ECR3_AWD1SEL | ADC_ECR3_AWD0SEL);
+
+ /* Reset register DMA_CR */
+ for (uint8_t i = 0; i < 12; i++) {
+ CLEAR_BIT(Instance->DMA_CR[i].TCR, ADC_DMA_TCR_CIRC | ADC_DMA_TCR_STP | ADC_DMA_TCR_START);
+ CLEAR_BIT(Instance->DMA_CR[i].TAR, ADC_DMA_TAR_ADDR);
+ CLEAR_BIT(Instance->DMA_CR[i].TLR, ADC_DMA_TLR_LENG);
+ }
+
+ } else {
+ /* ADC instance is in an unknown state */
+ /* Need to performing a hard reset of ADC instance, using high level */
+ /* clock source RCC ADC reset. */
+ status = LL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @param Instance ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref ADC_REG_InitTypeDef structure
+ * @retval An StatusETypeDef enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+LL_StatusETypeDef LL_ADC_REG_Init(ADC_TypeDef *Instance, ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+ assert_param(IS_ADC_CHANNEL(ADC_REG_InitStruct->Channel));
+ assert_param(IS_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+ assert_param(IS_ADC_REG_SEQ_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ assert_param(IS_ADC_REG_SEQ_POS(ADC_REG_InitStruct->SequencerPos));
+
+ if (ADC_REG_InitStruct->SequencerLength != ADC_REG_SEQ_LENGTH_1) {
+ assert_param(IS_ADC_REG_SEQ_DISCONT(ADC_REG_InitStruct->SequencerDiscont));
+ }
+
+ if (ADC_REG_InitStruct->Channel == ADC_CHANNEL_TEMPSENSOR) {
+ /*Enable temperature sensor detection*/
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_ADCBuf_En(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+ }
+
+ assert_param(IS_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_ADC_REG_DIFFERSEL(ADC_REG_InitStruct->DifferSel));
+ assert_param(IS_ADC_REG_SAMPTIMCLK(ADC_REG_InitStruct->SampTimClk));
+
+ if (__LL_ADC_REG_IsConversionOngoing(Instance) == 0UL) {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular overrun behavior */
+ /* Note: ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ /* Set ADC group regular sequencer length */
+ if (ADC_REG_InitStruct->SequencerLength == ADC_REG_SEQ_LENGTH_1) {
+ MODIFY_REG(Instance->LR,
+ ADC_LR_EXTSEL
+ | ADC_LR_EXTEN
+ | ADC_LR_LEN
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerLength
+ );
+ MODIFY_REG(Instance->SQR0,
+ ADC_SQR0_SQ1,
+ ADC_REG_InitStruct->Channel
+ );
+ } else {
+ MODIFY_REG(Instance->LR,
+ ADC_LR_EXTSEL
+ | ADC_LR_EXTEN
+ | ADC_LR_LEN
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerLength
+ );
+
+ if (ADC_REG_InitStruct->SequencerPos > 7) {
+ MODIFY_REG(Instance->SQR1,
+ (ADC_SQR1_SQ9 << ((ADC_REG_InitStruct->SequencerPos - 8U) << 2U)),
+ (ADC_REG_InitStruct->Channel << ((ADC_REG_InitStruct->SequencerPos - 8U) << 2U))
+ );
+ } else {
+ MODIFY_REG(Instance->SQR0,
+ ADC_SQR0_SQ1 << (ADC_REG_InitStruct->SequencerPos << 2U),
+ (ADC_REG_InitStruct->Channel << (ADC_REG_InitStruct->SequencerPos << 2U))
+ );
+ }
+ }
+
+ /*Continuous mode and discontinuous mode cannot be set to 1 at the same time*/
+ CLEAR_BIT(Instance->CR1, ADC_CR1_CONT | ADC_CR1_DISCEN);
+
+ if (ADC_REG_InitStruct->ContinuousMode == ADC_REG_CONV_CONTINUOUS) {
+ SET_BIT(Instance->CR1, ADC_CR1_CONT);
+ } else {
+ MODIFY_REG(Instance->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ | ADC_CR1_CONT
+ ,
+ ADC_REG_InitStruct->SequencerDiscont
+ | ADC_REG_InitStruct->ContinuousMode
+ );
+ }
+
+ /*Sampling time and calibration parameter set selection*/
+ if (ADC_REG_InitStruct->Channel > 7) {
+ MODIFY_REG(Instance->SMPR1,
+ ADC_SMPR1_SMP8 << ((ADC_REG_InitStruct->Channel - 8U) << 2U),
+ ADC_REG_InitStruct->SampTimClk << ((ADC_REG_InitStruct->Channel - 8U) << 2U)
+ );
+ } else {
+ MODIFY_REG(Instance->SMPR0,
+ ADC_SMPR0_SMP0 << (ADC_REG_InitStruct->Channel << 2U),
+ ADC_REG_InitStruct->SampTimClk << (ADC_REG_InitStruct->Channel << 2U)
+ );
+ }
+
+ /*configure the channel sample interrupt*/
+ if (ADC_REG_InitStruct->SampInterrupt == ENABLE) {
+ __LL_ADC_ENABLE_IT_DONE(Instance, ADC_REG_InitStruct->Channel);
+ } else {
+ __LL_ADC_DISABLE_IT_DONE(Instance, ADC_REG_InitStruct->Channel);
+ }
+
+ /*Differential single-end Offset/Gain setting*/
+ SET_BIT(Instance->DIFSEL, (ADC_DIFSEL_DIFSEL & (ADC_REG_InitStruct->DifferSel << ADC_REG_InitStruct->Channel)));
+ } else {
+ /* Initialization error: ADC instance is not disabled. */
+ status = LL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * @param Instance ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref ADC_INJ_InitTypeDef structure
+ * @retval An LL_StatusETypeDef enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+LL_StatusETypeDef LL_ADC_INJ_Init(ADC_TypeDef *Instance, ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+ assert_param(IS_ADC_CHANNEL(ADC_INJ_InitStruct->Channel));
+ assert_param(IS_ADC_INJ_JSEQ_POS(ADC_INJ_InitStruct->SequencerPos));
+ assert_param(IS_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+ assert_param(IS_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ assert_param(IS_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ assert_param(IS_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (__LL_ADC_INJ_IsConversionOngoing(Instance) == 0UL) {
+ if (ADC_INJ_InitStruct->Channel == ADC_CHANNEL_TEMPSENSOR) {
+ /*Enable temperature sensor detection*/
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_ADCBuf_En(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+ }
+
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular (injected auto ) */
+ MODIFY_REG(Instance->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+
+ MODIFY_REG(Instance->JLR,
+ ADC_JLR_JEXTSEL
+ | ADC_JLR_JEXTEN
+ | ADC_JLR_JLEN
+ ,
+ ADC_INJ_InitStruct->TriggerSource
+ | ADC_INJ_InitStruct->SequencerLength
+ );
+ /*JSQR sequence position*/
+ MODIFY_REG(Instance->JSQR, (ADC_JSQR_JSQ1 << ADC_INJ_InitStruct->SequencerPos),
+ ADC_INJ_InitStruct->Channel << ADC_INJ_InitStruct->SequencerPos);
+ } else {
+ /* Initialization error: ADC instance is not disabled. */
+ status = LL_ERROR;
+ }
+
+
+ return status;
+}
+
+/**
+ * @brief Initializes the ADC MSP.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_MspInit(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the ADC MSP
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_MspDeInit(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_Exported_Functions_Group2 ADC Config Functions
+ * @brief ADC Config Functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the adc to ecu paramter
+ (+) Configure the analog watchdog
+ (+) Configure the DMA Transfer
+ (+) Configure the calibration paramter
+ (+) Configure the oversamping
+ @endverbatim
+ *
+ * @{
+ */
+
+
+/**
+ * @brief Initialize some features of ADC and ECU linkage related register.
+ * @note These parameters have an impact on ADC scope: ADC to ECU register ECR0~3.
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * @param Instance ADC instance
+ * @param ADC_ECU_Config Pointer to a @ref ADC_ECU_Config structure
+ * @retval An LL_StatusETypeDef enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+LL_StatusETypeDef LL_ADC_ECU_Config(ADC_TypeDef *Instance, ADC_ECUConfTypeDef *ADC_ECU_Config)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+ assert_param(IS_ADC_ECU_GROUPSEL(ADC_ECU_Config->GroupSel));
+ assert_param(IS_ADC_CHANNEL(ADC_ECU_Config->AddrDataSel));
+ assert_param(IS_ADC_CHANNEL(ADC_ECU_Config->AWD0SourceSel));
+ assert_param(IS_ADC_CHANNEL(ADC_ECU_Config->AWD1SourceSel));
+ assert_param(IS_ADC_CHANNEL(ADC_ECU_Config->AWD2SourceSel));
+ assert_param(IS_ADC_REG_AWD_SEL(ADC_ECU_Config->PingPongUpZero));
+ assert_param(IS_ADC_REG_AWD_SEL(ADC_ECU_Config->PingPongDownZero));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (__LL_ADC_REG_IsConversionOngoing(Instance) == 0UL) {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC to ECU control paramter */
+ /* - Set ADC address data flag */
+ /* - Set ADC ping pong up zero anolog watchdog */
+ /* - Set ADC ping pong down zero anolog watchdog */
+ /* - Set ADC anolog watchdog x detected channel */
+ MODIFY_REG(Instance->ECR[ADC_ECU_Config->GroupSel],
+ ADC_ECR0_ADSRC
+ | ADC_ECR0_PSRCU
+ | ADC_ECR0_PSRCD
+ | ADC_ECR0_AWD2SEL
+ | ADC_ECR0_AWD1SEL
+ | ADC_ECR0_AWD0SEL
+ ,
+ (ADC_ECU_Config->AddrDataSel << 16U)
+ | (ADC_ECU_Config->PingPongUpZero << 14U)
+ | (ADC_ECU_Config->PingPongDownZero << 12U)
+ | (ADC_ECU_Config->AWD2SourceSel << 8U)
+ | (ADC_ECU_Config->AWD1SourceSel << 4U)
+ | ADC_ECU_Config->AWD0SourceSel
+ );
+ } else {
+ /* Initialization error: ADC instance is not disabled. */
+ status = LL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, successive
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGCfgTypeDef" on the fly, without resetting
+ * the ADC.
+ * The same watchdog can monitor multiple channels simultaneously.
+ * @param Instance ADC instance
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_ADC_AnalogWDGConfig(ADC_TypeDef *Instance, ADC_AnalogWDGCfgTypeDef *AnalogWDGConfig)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+ assert_param(IS_ADC_REG_AWD_SEL(AnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_AWD_CHANNEL(AnalogWDGConfig->Channel));
+ assert_param(IS_ADC_REG_AWD_FILTER(AnalogWDGConfig->Filtering));
+
+ /* - Analog watchdog channels */
+ if ((__LL_ADC_REG_IsConversionOngoing(Instance) == 0UL) && (__LL_ADC_INJ_IsConversionOngoing(Instance) == 0UL)) {
+ /* Configuration of analog watchdog:*/
+ /* Set the filtering \ channel configuration */
+ MODIFY_REG(Instance->AWDCR[AnalogWDGConfig->WatchdogNumber],
+ ADC_AWD0CR_AWD0CH | ADC_AWD0CR_AWD0FILT,
+ (AnalogWDGConfig->Channel)
+ | (AnalogWDGConfig->Filtering)
+ );
+ /* Set the watchdog high and low threshold */
+ MODIFY_REG(Instance->TR[AnalogWDGConfig->WatchdogNumber],
+ ADC_TR0_HT0 | ADC_TR0_LT0,
+ (AnalogWDGConfig->LowThreshold & ADC_TR0_LT0)
+ | ((AnalogWDGConfig->HighThreshold & ADC_TR0_LT0) << ADC_TR0_HT0_Pos)
+ );
+ } else {
+ status = LL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the DMA transfer.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected channel,
+ * Only one channel can be configured at a time.
+ * You cannot use the same address for different channels.
+ * @param Instance ADC instance
+ * @param DMATransferConfig Structure of ADC DMA transfer configuration
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_ADC_DMATransferConfig(ADC_TypeDef *Instance, ADC_DMATransferCfgTypeDef *DMATransferConfig)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+ assert_param(IS_ADC_CHANNEL(DMATransferConfig->Channel));
+ assert_param(IS_ADC_REG_DMA_TRANSFER(DMATransferConfig->TransferMode));
+
+ /* - DMA Transfer channels */
+ if ((__LL_ADC_REG_IsConversionOngoing(Instance) == 0UL) && (__LL_ADC_INJ_IsConversionOngoing(Instance) == 0UL)) {
+ MODIFY_REG(Instance->DMA_CR[DMATransferConfig->Channel].TAR,
+ ADC_DMA_TAR_ADDR,
+ (DMATransferConfig->Address)
+ );
+ MODIFY_REG(Instance->DMA_CR[DMATransferConfig->Channel].TLR,
+ ADC_DMA_TLR_LENG,
+ (DMATransferConfig->Length)
+ );
+ MODIFY_REG(Instance->DMA_CR[DMATransferConfig->Channel].TCR,
+ ADC_DMA_TCR_START | ADC_DMA_TCR_CIRC,
+ (DMATransferConfig->TransferMode)
+ );
+
+ if (DMATransferConfig->HalfInterrupt == ENABLE) {
+ __LL_ADC_ENABLE_IT_HALF(Instance, DMATransferConfig->Channel);
+ } else {
+ __LL_ADC_DISABLE_IT_HALF(Instance, DMATransferConfig->Channel);
+ }
+
+ if (DMATransferConfig->FullInterrupt == ENABLE) {
+ __LL_ADC_ENABLE_IT_FULL(Instance, DMATransferConfig->Channel);
+ } else {
+ __LL_ADC_DISABLE_IT_FULL(Instance, DMATransferConfig->Channel);
+ }
+
+ } else {
+ status = LL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Configure the calibration parameters.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected channel,
+ * A total of four sets of calibration parameters can be selected for 12 channels.
+ * @param Instance ADC instance
+ * @param CalibrationConfig Structure of ADC DMA transfer configuration
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_ADC_CalibrationConfig(ADC_TypeDef *Instance, ADC_CalibrationTypeDef *CalibrationConfig)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ temp_offset = 0;
+ temp_gain = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(Instance));
+ assert_param(IS_ADC_CHANNEL(CalibrationConfig->Channel));
+ assert_param(IS_LL_ADC_CALCOEFSEL(CalibrationConfig->CalibrationGroup));
+
+ /* Determine if the ADC is started */
+ if ((__LL_ADC_REG_IsConversionOngoing(Instance) == 0UL) && (__LL_ADC_INJ_IsConversionOngoing(Instance) == 0UL)) {
+
+ __LL_ADC_SetCalGroup(Instance, CalibrationConfig->Channel, CalibrationConfig->CalibrationGroup);
+
+ /*Determines whether the selected channel is single-ended or differential*/
+ if (__LL_ADC_GetChannelSingleDiff(Instance, CalibrationConfig->Channel)) {
+
+ temp_offset = (int16_t)(pCoef.DiffOffset + (((int32_t)CalibrationConfig->Offset << 13) / pCoef.DiffGain));
+ temp_gain = (uint16_t)((uint32_t)(CalibrationConfig->Gain * pCoef.DiffGain) >> 13);
+
+ LL_ADC_OverSamp_Mode(Instance, temp_offset);
+
+ MODIFY_REG(Instance->DOFR[CalibrationConfig->CalibrationGroup],
+ ADC_DOFR0_OFFSET,
+ (temp_offset)
+ );
+ MODIFY_REG(Instance->DGCR[CalibrationConfig->CalibrationGroup],
+ ADC_DGCR0_GAIN,
+ (temp_gain)
+ );
+ } else {
+
+ temp_offset = (int16_t)(pCoef.SingleOffset + (((int32_t)CalibrationConfig->Offset << 13) / pCoef.SingleGain));
+ temp_gain = (uint16_t)((uint32_t)(CalibrationConfig->Gain * pCoef.SingleGain) >> 13);
+
+ LL_ADC_OverSamp_Mode(Instance, temp_offset);
+
+ MODIFY_REG(Instance->OFR[CalibrationConfig->CalibrationGroup],
+ ADC_OFR0_OFFSET,
+ (temp_offset)
+ );
+ MODIFY_REG(Instance->GCR[CalibrationConfig->CalibrationGroup],
+ ADC_GCR0_GAIN,
+ (temp_gain)
+ );
+ }
+
+ } else {
+ status = LL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Convert to actual degrees Celsius
+ * @note Temperature = (Vout - 1.34) / 0.005
+ * @retval LL status
+ */
+float LL_ADC_TemperatureCovert(uint16_t voltage_data)
+{
+ float voltage_realvalue = 0;
+ float temper_realvalue = 0;
+
+ voltage_realvalue = (3.0 * voltage_data * 1000) / 8192.0;
+
+ temper_realvalue = (voltage_realvalue - 1340) / 5;
+
+ return temper_realvalue;
+
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_Exported_Functions_Interrupt Interrupt handler and call back
+ * @brief Interrupt handler and call back
+ * @{
+ */
+
+/**
+ * @brief ADC Ready detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_AdRdyCallback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_AdRdyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC EoSmp detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_EosmpCallback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_EoSmpCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC Anolog WatchDog 2 detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_AnologWD2Callback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_AnologWD2Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC Anolog WatchDog 1 detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_AnologWD1Callback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_AnologWD1Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC Anolog WatchDog 0 detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_AnologWD0Callback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_AnologWD0Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC OverRun detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_OverRunCallback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_OverRunCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC injected end of sequencer detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_JeosCallback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_JeosCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC regular end of sequencer detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_EosCallback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_EosCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC injected end of conversion detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_JeocCallback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_JeocCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC regualr end of conversion detection callback.
+ * @param Instance ADC instance
+ * @return None
+ */
+__WEAK void LL_ADC_EocCallback(ADC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_EocCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC Sample done detection callback.
+ * @param Instance ADC instance
+ * @param Channel 0~11
+ * @return None
+ */
+__WEAK void LL_ADC_SampCallback(ADC_TypeDef *Instance, uint8_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_SampCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC DMA Half detection callback.
+ * @param Instance ADC instance
+ * @param Channel 0~11
+ * @return None
+ */
+__WEAK void LL_ADC_HalfCallback(ADC_TypeDef *Instance, uint8_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_HalfCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ADC DMA Full detection callback.
+ * @param Instance ADC instance
+ * @param Channel 0~11
+ * @return None
+ */
+__WEAK void LL_ADC_FullCallback(ADC_TypeDef *Instance, uint8_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ADC_FullCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief This function handles ADC Normal interrupts requests.
+ * @param Instance ADC instance
+ * @return None
+ */
+void LL_ADC_NORM_IRQHandler(ADC_TypeDef *Instance)
+{
+ if ((__LL_ADC_GET_IT_ADRDY(Instance)) && (__LL_ADC_GET_FLAG_ADRDY(Instance))) {
+ __LL_ADC_CLEAR_FLAG_ADRDY(Instance);
+
+ /*Handle something*/
+ LL_ADC_AdRdyCallback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_EOSMP(Instance)) && (__LL_ADC_GET_FLAG_EOSMP(Instance))) {
+ __LL_ADC_CLEAR_FLAG_EOSMP(Instance);
+
+ /*Handle something*/
+ LL_ADC_EosmpCallback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_AWD2(Instance)) && (__LL_ADC_GET_FLAG_AWD2(Instance))) {
+ __LL_ADC_CLEAR_FLAG_AWD2(Instance);
+
+ /*Handle something*/
+ LL_ADC_AnologWD2Callback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_AWD1(Instance)) && (__LL_ADC_GET_FLAG_AWD1(Instance))) {
+ __LL_ADC_CLEAR_FLAG_AWD1(Instance);
+
+ /*Handle something*/
+ LL_ADC_AnologWD1Callback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_AWD0(Instance)) && (__LL_ADC_GET_FLAG_AWD0(Instance))) {
+ __LL_ADC_CLEAR_FLAG_AWD0(Instance);
+
+ /*Handle something*/
+ LL_ADC_AnologWD0Callback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_OVR(Instance)) && (__LL_ADC_GET_FLAG_OVR(Instance))) {
+ __LL_ADC_CLEAR_FLAG_OVR(Instance);
+
+ /*Handle something*/
+ LL_ADC_OverRunCallback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_JEOS(Instance)) && (__LL_ADC_GET_FLAG_JEOS(Instance))) {
+ __LL_ADC_CLEAR_FLAG_JEOS(Instance);
+
+ /*Handle something*/
+ LL_ADC_JeosCallback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_JEOC(Instance)) && (__LL_ADC_GET_FLAG_JEOC(Instance))) {
+ __LL_ADC_CLEAR_FLAG_JEOC(Instance);
+
+ /*Handle something*/
+ LL_ADC_JeocCallback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_EOS(Instance)) && (__LL_ADC_GET_FLAG_EOS(Instance))) {
+ __LL_ADC_CLEAR_FLAG_EOS(Instance);
+
+ /*Handle something*/
+ LL_ADC_EosCallback(Instance);
+ }
+
+ if ((__LL_ADC_GET_IT_EOC(Instance)) && (__LL_ADC_GET_FLAG_EOC(Instance))) {
+ __LL_ADC_CLEAR_FLAG_EOC(Instance);
+
+ /*Handle something*/
+ LL_ADC_EocCallback(Instance);
+ }
+
+}
+
+/**
+ * @brief This function handles ADC Sample interrupts requests.
+ * @param Instance ADC instance
+ * @param Channel 0~11
+ * @return None
+ */
+void LL_ADC_SAMP_IRQHandler(ADC_TypeDef *Instance, uint8_t Channel)
+{
+ if ((__LL_ADC_GET_IT_DONE(Instance, Channel)) && (__LL_ADC_GET_FLAG_DONE(Instance, Channel))) {
+ __LL_ADC_CLEAR_FLAG_DONE(Instance, Channel);
+
+ /*Handle something*/
+ LL_ADC_SampCallback(Instance, Channel);
+ }
+}
+
+/**
+ * @brief This function handles ADC Dma Half interrupts requests.
+ * @param Instance ADC instance
+ * @param Channel 0~11
+ * @return None
+ */
+void LL_ADC_HALF_IRQHandler(ADC_TypeDef *Instance, uint8_t Channel)
+{
+ if ((__LL_ADC_GET_IT_HALF(Instance, Channel)) && (__LL_ADC_GET_FLAG_HALF(Instance, Channel))) {
+ __LL_ADC_CLEAR_FLAG_HALF(Instance, Channel);
+
+ /*Handle something*/
+ LL_ADC_HalfCallback(Instance, Channel);
+ }
+}
+
+/**
+ * @brief This function handles ADC Dma Full interrupts requests.
+ * @param Instance ADC instance
+ * @param Channel 0~11
+ * @return None
+ */
+void LL_ADC_FULL_IRQHandler(ADC_TypeDef *Instance, uint8_t Channel)
+{
+ if ((__LL_ADC_GET_IT_FULL(Instance, Channel)) && (__LL_ADC_GET_FLAG_FULL(Instance, Channel))) {
+ __LL_ADC_CLEAR_FLAG_FULL(Instance, Channel);
+
+ /*Handle something*/
+ LL_ADC_FullCallback(Instance, Channel);
+ }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Read ADC single-ended self-calibration data
+ * @note No external calls
+ * @return None
+ */
+static void LL_ADC_ReadCoef(void)
+{
+ Calib_read_data[0] = SYSCTRL->SINGLE;
+ Calib_read_data[1] = SYSCTRL->DIFFER;
+ Calib_read_data[2] = SYSCTRL->SINGLE_BUFF;
+
+ /* Determinate whether the SoC has been calibrated. If it has not been calibrated,
+ the standard register is written into the user configuration data;
+ if the calibration criterion reads the calibration data*/
+ if (memcmp(&Calib_check_data, &Calib_read_data, sizeof(Calib_read_data)) == 0) {
+ /* CALB_SE*/
+ pCoef.SingleGain = 8192;
+ /* CALA_SE*/
+ pCoef.SingleOffset = 0;
+ /* CALB_DF*/
+ pCoef.DiffGain = 8192;
+ /* CALA_DF*/
+ pCoef.DiffOffset = 0;
+ /* CALB_WB*/
+ pCoef.SingleBuffGain = 8192;
+ /* CALA_WB*/
+ pCoef.SingleBuffOffset = 0;
+ } else {
+ /* CALB_SE*/
+ pCoef.SingleGain = (uint16_t)Calib_read_data[0];
+ /* CALA_SE*/
+ pCoef.SingleOffset = (int16_t)(Calib_read_data[0] >> 16);
+ /* CALB_DF*/
+ pCoef.DiffGain = (uint16_t)Calib_read_data[1];
+ /* CALA_DF*/
+ pCoef.DiffOffset = (int16_t)(Calib_read_data[1] >> 16);
+ /* CALB_WB*/
+ pCoef.SingleBuffGain = (uint16_t)Calib_read_data[2];
+ /* CALA_WB*/
+ pCoef.SingleBuffOffset = (int16_t)(Calib_read_data[2] >> 16);
+ }
+
+}
+
+/**
+ * @brief The calibration coefficient varies with the change of oversampling
+ * @note No external calls
+ * @param Instance ADC instance
+ * @param offset ADC offset
+ * @return None
+ */
+static void LL_ADC_OverSamp_Mode(ADC_TypeDef *Instance, int16_t offset)
+{
+ int8_t temp_mode = 0;
+
+ temp_mode = (__LL_ADC_GetOverSamplingShift(Instance) >> ADC_CR1_OVSS_Pos) - \
+ (__LL_ADC_GetOverSamplingRatio(Instance) >> ADC_CR1_OVSR_Pos);
+
+ if ((temp_mode - 1) >= 0) {
+ temp_offset = offset >> (temp_mode - 1);
+ } else {
+ temp_offset = offset << (abs(temp_mode) + 1);
+ }
+}
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_ADC_MODULE_ENABLE */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_can.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_can.c
new file mode 100644
index 0000000000..9b678f2f3a
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_can.c
@@ -0,0 +1,565 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_can.c
+ * @author MCD Application Team
+ * @brief CAN LL Module Driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "CAN LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CAN_LL CAN LL
+ * @brief CAN LL Module Driver
+ * @{
+ */
+
+#ifdef LL_CAN_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CAN_LL_Private_Functions
+ * @{
+ */
+LL_StatusETypeDef LL_CAN_AcceptFilCfg(CAN_TypeDef *Instance, CAN_AcceptFilCfgTypeDef *fil_cfg);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CAN_LL_Exported_Functions CAN LL Exported Functions
+ * @brief CAN LL Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+
+/**
+ * @brief CAN LL Init
+ * @param Instance Specifies CAN peripheral
+ * @param user_cfg user config pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_CAN_Init(CAN_TypeDef *Instance, CAN_UserCfgTypeDef *user_cfg)
+{
+ assert_param(Instance);
+ assert_param(user_cfg);
+
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_CAN_MspInit(Instance);
+
+ /* Set reset status to config some register which can config in reset status only */
+ __LL_CAN_Reset_Set(Instance);
+
+ //Baudrate config
+ assert_param(user_cfg->baudrate);
+ __LL_CAN_SS_Prescaler_Set(Instance, (LL_SYSCTRL_AHBClkGet() / 10 / user_cfg->baudrate - 1));
+
+ //Bit timing config
+ __LL_CAN_SS_BitTimingSeg1_Set(Instance, user_cfg->bit_timing_seg1);
+ __LL_CAN_SS_BitTimingSeg2_Set(Instance, user_cfg->bit_timing_seg2);
+ __LL_CAN_SS_SyncJumpWidth_Set(Instance, user_cfg->bit_timing_sjw);
+
+ //Acceptance filter config
+ for (uint8_t i = 0; i < user_cfg->accept_fil_cfg_num; i++) {
+ LL_CAN_AcceptFilCfg(Instance, (CAN_AcceptFilCfgTypeDef *)&user_cfg->accept_fil_cfg_ptr[i]);
+ }
+
+ /*Clear reset status to config other register */
+ __LL_CAN_Reset_Clr(Instance);
+
+ //RX buffer almost full and error warning limit set
+ __LL_CAN_RxBufAlmostFullLimit_Set(Instance, user_cfg->rx_almost_full_limit);
+ __LL_CAN_ErrWarnLimit_Set(Instance, user_cfg->err_limit);
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN LL DeInit
+ * @param Instance Specifies CAN peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_CAN_DeInit(CAN_TypeDef *Instance)
+{
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_CAN_MspDeInit(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_MspInit(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_MspDeInit(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_LL_Exported_Functions_Group2 Send data functions
+ * @brief Send data functions
+ * @{
+ */
+
+/**
+ * @brief CAN LL send standard primary transmit buffer
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt buffer format pointer
+ * @param buf buffer pointer
+ * @return success send length in byte
+ */
+uint32_t LL_CAN_SendStandard_PTB(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ uint32_t i, j;
+
+ assert_param(Instance);
+ assert_param(buf_fmt);
+ assert_param(buf);
+
+ //TX buffer select PTB
+ __LL_CAN_TxBufSel_PTB(Instance);
+
+ //Write buffer format data to TX buffer
+ Instance->TXBUF[0] = *((uint32_t *)buf_fmt);
+ Instance->TXBUF[1] = *(((uint32_t *)buf_fmt) + 1);
+
+ //Write data to TX buffer
+ for (i = 0, j = 0; i < buf_fmt->data_len_code; i += 4, j++) {
+ Instance->TXBUF[2 + j] = *buf++;
+ }
+
+ //TX primary enable
+ __LL_CAN_TxPriEn_Set(Instance);
+
+ //Wait TX complete
+ while (__LL_CAN_TxPriEn_Get(Instance));
+
+ return buf_fmt->data_len_code;
+}
+
+/**
+ * @brief CAN LL send standard secondary transmit buffer
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt buffer format pointer
+ * @param buf buffer pointer
+ * @return success send length in byte
+ */
+uint32_t LL_CAN_SendStandard_STB(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ uint32_t i, j;
+
+ assert_param(Instance);
+ assert_param(buf_fmt);
+ assert_param(buf);
+
+ //TX buffer select STB
+ __LL_CAN_TxBufSel_STB(Instance);
+
+ //Write buffer format data to TX buffer
+ Instance->TXBUF[0] = *((uint32_t *)buf_fmt);
+ Instance->TXBUF[1] = *(((uint32_t *)buf_fmt) + 1);
+
+ //Write data to TX buffer
+ for (i = 0, j = 0; i < buf_fmt->data_len_code; i += 4, j++) {
+ Instance->TXBUF[2 + j] = *buf++;
+ }
+
+ //TX buffer Secondary next
+ __LL_CAN_TxSecNext_Set(Instance);
+
+ //TX secondary send one start
+ __LL_CAN_TxSecOne_Set(Instance);
+
+ //Wait TX complete
+ while (__LL_CAN_TxSecOne_Get(Instance));
+
+ return buf_fmt->data_len_code;
+}
+
+/**
+ * @brief CAN LL send a multi-package standard secondary transmit buffer
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt buffer format pointer
+ * @param buf buffer pointer
+ * @param send_cnt send packets count
+ * @return success send length in byte
+ */
+uint32_t LL_CAN_SendStandard_STB_Multi(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt,
+ uint32_t *buf, uint32_t send_cnt)
+{
+ uint32_t i, j, cnt;
+
+ assert_param(Instance);
+ assert_param(buf_fmt);
+ assert_param(buf);
+
+ //TX buffer select STB
+ __LL_CAN_TxBufSel_STB(Instance);
+
+ for (cnt = 0; cnt < send_cnt; cnt++) {
+ //Write buffer format data to TX buffer
+ Instance->TXBUF[0] = *((uint32_t *)buf_fmt);
+ Instance->TXBUF[1] = *(((uint32_t *)buf_fmt) + 1);
+
+ //Write data to TX buffer
+ for (i = 0, j = 0; i < buf_fmt->data_len_code; i += 4, j++) {
+ Instance->TXBUF[2 + j] = *buf++;
+ }
+
+ //TX buffer Secondary next
+ __LL_CAN_TxSecNext_Set(Instance);
+
+ //TX buffer Secondary full and send
+ if (__LL_CAN_IsTxSecBufFull(Instance)) {
+ //TX secondary send all start
+ __LL_CAN_TxSecAll_Set(Instance);
+
+ //Wait TX complete
+ while (__LL_CAN_TxSecAll_Get(Instance));
+ }
+ }
+
+ //TX secondary send all start
+ __LL_CAN_TxSecAll_Set(Instance);
+
+ //Wait TX complete
+ while (__LL_CAN_TxSecAll_Get(Instance));
+
+ return buf_fmt->data_len_code * send_cnt;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_LL_Exported_Functions_Interrupt CAN Interrupt handler and call back
+ * @brief CAN Interrupt handler and call back
+ * @{
+ */
+
+/**
+ * @brief CAN IRQ Handler
+ * @param Instance Specifies CAN peripheral
+ * @note All interrupt pending will be reset immediately after a read access
+ * @return None
+ */
+void LL_CAN_IRQHandler(CAN_TypeDef *Instance)
+{
+ uint8_t txrx_int_sta = __LL_CAN_IntSta_Get(Instance);
+ uint8_t err_int_sta = __LL_CAN_ErrIntSta_Get(Instance);
+
+ if (txrx_int_sta & CAN_RX_INT_STA_Msk) {
+ LL_CAN_RxCallback(Instance);
+ }
+
+ if (txrx_int_sta & CAN_RX_BUF_OVER_INT_STA_Msk) {
+ LL_CAN_RxOverCallback(Instance);
+ }
+
+ if (txrx_int_sta & CAN_RX_BUF_FULL_INT_STA_Msk) {
+ LL_CAN_RxFullCallback(Instance);
+ }
+
+ if (txrx_int_sta & CAN_RX_BUF_ALMOST_FULL_INT_STA_Msk) {
+ LL_CAN_RxAlmostFullCallback(Instance);
+ }
+
+ if (txrx_int_sta & CAN_TX_PRI_INT_STA_Msk) {
+ LL_CAN_TxPriCallback(Instance);
+ }
+
+ if (txrx_int_sta & CAN_TX_SEC_INT_STA_Msk) {
+ LL_CAN_TxSecCallback(Instance);
+ }
+
+ if (txrx_int_sta & CAN_ERR_INT_STA_Msk) {
+ LL_CAN_ErrCallback(Instance);
+ }
+
+ if (txrx_int_sta & CAN_ABORT_INT_STA_Msk) {
+ LL_CAN_AbortCallback(Instance);
+ }
+
+
+ if (err_int_sta & CAN_ERR_PASS_INT_STA_Msk) {
+ LL_CAN_ErrPassiveCallback(Instance);
+ }
+
+ if (err_int_sta & CAN_ARB_LOST_INT_STA_Msk) {
+ LL_CAN_ArbLostCallback(Instance);
+ }
+
+ if (err_int_sta & CAN_BUS_ERR_INT_STA_Msk) {
+ LL_CAN_BusErrCallback(Instance);
+ }
+}
+
+
+/**
+ * @brief CAN RX interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN RX over interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxOverCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxOverCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN RX full interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN RX almost full interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxAlmostFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxAlmostFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN TX primary interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_TxPriCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_TxPriCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN TX secondary interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_TxSecCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_TxSecCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN error interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ErrCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN abort interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_AbortCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_AbortCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN error passive interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ErrPassiveCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ErrPassiveCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN arbitration lost interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ArbLostCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ArbLostCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN bus error interrupt callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_BusErrCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_BusErrCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CAN_LL_Private_Functions CAN LL Private Functions
+ * @brief CAN LL Private Functions
+ * @{
+ */
+
+/**
+ * @brief CAN LL acceptance filter config
+ * @param Instance Specifies CAN peripheral
+ * @param fil_cfg filter config pointer
+ * @return Config result
+ */
+LL_StatusETypeDef LL_CAN_AcceptFilCfg(CAN_TypeDef *Instance, CAN_AcceptFilCfgTypeDef *fil_cfg)
+{
+ assert_param(Instance);
+ assert_param(fil_cfg);
+
+ //Check in reset status or not
+ if (!__LL_CAN_ResetSta_Get(Instance)) {
+ LOG_E("Acceptance filter register can config in reset status only!\n");
+ return LL_ERROR;
+ }
+
+ //CAN acceptance filter Code and Mask config
+ __LL_CAN_AcceptFilAddr_Set(Instance, fil_cfg->slot);
+ __LL_CAN_AcceptFilContentSel_Code(Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(Instance, fil_cfg->code_val);
+ __LL_CAN_AcceptFilContentSel_Mask(Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(Instance, fil_cfg->mask_val);
+
+ //CAN acceptance filter enable
+ __LL_CAN_AcceptFil_En(Instance, ((uint8_t)fil_cfg->slot));
+
+ return LL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* LL_CAN_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_cmp.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_cmp.c
new file mode 100644
index 0000000000..4a31133b57
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_cmp.c
@@ -0,0 +1,396 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_cmp.c
+ * @author MCD Application Team
+ * @brief Source file for CMP Moudle
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "CMP LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CMP_LL CMP LL
+ * @brief CMP LL module driver.
+ * @{
+ */
+
+#ifdef LL_CMP_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CMP_LL_Exported_Functions CMP LL Exported Functions
+ * @brief CMP LL Exported Functions
+ * @{
+ */
+
+/** @defgroup CMP_LL_Exported_Functions_Group1 Initialization and De-Initialization functions
+ * @brief Initialization and De-Initialization functions
+@verbatim
+ ==============================================================================
+ ##### Initialization and De-Initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize the CMP peripheral.
+ (+) De-initialize the CMP peripheral.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CMP peripheral
+ * @param Instance CMP peripheral instance
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_CMP_Init(CMP_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_CMP_ALL_INSTANCE(Instance));
+
+ /* Init the low level hardware */
+ LL_CMP_MspInit(Instance);
+
+ /* Clear interrupt pending flags */
+ __LL_CMP_PENDING_FLAG_CLEAR(Instance, CMP_FLAG_ALLIF);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Deinitialize the CMP peripheral
+ * @param Instance CMP peripheral instance
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_CMP_DeInit(CMP_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_CMP_ALL_INSTANCE(Instance));
+
+ for (uint8_t chnnum = 0; chnnum < CMP_CHN_NB; ++chnnum) {
+ /* Disable CMP channel FALIE/RISIE interrupts */
+ __LL_CMP_IT_DISABLE(Instance, chnnum, CMP_IT_FALIE | CMP_IT_RISIE);
+
+ /* Disable CMP channel */
+ __LL_CMP_DISABLE(Instance, chnnum);
+ }
+
+ /* DeInit the low level hardware */
+ LL_CMP_MspDeInit(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the CMP MSP.
+ * @param Instance CMP peripheral
+ * @return None
+ */
+__WEAK void LL_CMP_MspInit(CMP_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_CMP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CMP MSP
+ * @param Instance CMP peripheral
+ * @return None
+ */
+__WEAK void LL_CMP_MspDeInit(CMP_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CMP_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CMP_LL_Exported_Functions_Group2 CMP Peripheral Control functions
+ * @brief CMP Peripheral Control functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure CMP channels.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected CMP channel.
+ * @param Instance CMP peripheral
+ * @param Channel The selected CMP channel.
+ * This parameter can be one of the following values:
+ * @arg CMP_CHANNEL_0: CMP Channel0 selected
+ * @arg CMP_CHANNEL_1: CMP Channel1 selected
+ * @arg CMP_CHANNEL_2: CMP Channel2 selected
+ * @arg CMP_CHANNEL_3: CMP Channel3 selected
+ * @param sConfig CMP configuration structure.
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CMP_ChannelConfig(CMP_TypeDef *Instance, uint32_t Channel, CMP_ChannelConfTypeDef *sConfig)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the parameters */
+ assert_param(IS_CMP_ALL_INSTANCE(Instance));
+ assert_param(IS_CMP_CHANNEL(Channel));
+ assert_param(IS_CMP_NUMBER(chnnum));
+ assert_param(sConfig != NULL);
+ assert_param(IS_CMP_INPUT_MINUS(sConfig->InputMinus));
+ assert_param(IS_CMP_HYSTERESIS(sConfig->Hysteresis));
+ assert_param(IS_CMP_BLANKING_SOURCE(Channel, sConfig->BlankingSource));
+ assert_param(IS_CMP_OUTPUT_DEBOUNCE(sConfig->OutputDebounce));
+ assert_param(IS_CMP_OUTPUT_DEBOUNCE_VAL(sConfig->OutputDebounceValue));
+ assert_param(IS_CMP_OUTPUT_POLARITY(sConfig->OutputPolarity));
+ assert_param(IS_CMP_TRIGGER_IT(sConfig->TriggerInterrupt));
+
+ /* Set Debounce Vaule */
+ if (sConfig->OutputDebounceValue == CMP_OUTPUT_DEBOUNCE_ENABLE) {
+ __LL_CMP_DEBOUNCE_VALUE_SET(Instance, chnnum, sConfig->OutputDebounceValue);
+ }
+
+ /* Reset and Calculate CR register value depending on sConfig */
+ MODIFY_REG(Instance->CR[chnnum],
+ (CMP_CR_OPOL_Msk
+ | CMP_CR_ODEB_Msk
+ | CMP_CR_BLANKING_Msk
+ | CMP_CR_INM_Msk
+ | CMP_CR_HYST_Msk
+ | CMP_CR_FALIE_Msk
+ | CMP_CR_RISIE_Msk
+ ),
+ (sConfig->OutputPolarity
+ | sConfig->OutputDebounce
+ | sConfig->BlankingSource
+ | sConfig->InputMinus
+ | sConfig->Hysteresis
+ | sConfig->TriggerInterrupt));
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CMP_LL_Exported_Functions_Group3 CMP IO operation functions
+ * @brief CMP IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start/Stop CMP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables CMP Channel conversion
+ * @param Instance CMP peripheral instance
+ * @param Channel The selected CMP channel.
+ * This parameter can be one of the following values:
+ * @arg CMP_CHANNEL_0: CMP Channel0 selected
+ * @arg CMP_CHANNEL_1: CMP Channel1 selected
+ * @arg CMP_CHANNEL_2: CMP Channel2 selected
+ * @arg CMP_CHANNEL_3: CMP Channel3 selected
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CMP_Start(CMP_TypeDef *Instance, uint32_t Channel)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the parameters */
+ assert_param(IS_CMP_ALL_INSTANCE(Instance));
+ assert_param(IS_CMP_CHANNEL(Channel));
+ assert_param(IS_CMP_NUMBER(chnnum));
+
+ /* Enable the CMP channel */
+ __LL_CMP_ENABLE(Instance, chnnum);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Disable CMP Channel conversion
+ * @param Instance CMP peripheral instance
+ * @param Channel The selected CMP channel.
+ * This parameter can be one of the following values:
+ * @arg CMP_CHANNEL_0: CMP Channel0 selected
+ * @arg CMP_CHANNEL_1: CMP Channel1 selected
+ * @arg CMP_CHANNEL_2: CMP Channel2 selected
+ * @arg CMP_CHANNEL_3: CMP Channel3 selected
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CMP_Stop(CMP_TypeDef *Instance, uint32_t Channel)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the CMP parameters */
+ assert_param(IS_CMP_ALL_INSTANCE(Instance));
+ assert_param(IS_CMP_CHANNEL(Channel));
+ assert_param(IS_CMP_NUMBER(chnnum));
+
+ /* Enable CMP Channel */
+ __LL_CMP_DISABLE(Instance, chnnum);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CMP_LL_Exported_Functions_Interrupt CMP Interrupt management
+ * @brief CMP Interrupt management
+@verbatim
+ ===============================================================================
+ ##### Initerrupt management #####
+ ===============================================================================
+ [..]
+ This section provides CMP interrupt handler and callback functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles CMP interrupts requests.
+ * @param Instance CMP peripheral
+ * @return None
+ */
+void LL_CMP_IRQHandler(CMP_TypeDef *Instance)
+{
+ uint32_t irqtemp = READ_REG(Instance->SR);
+
+ /* Check the CMP parameters */
+ assert_param(IS_CMP_ALL_INSTANCE(Instance));
+
+ for (uint8_t chnnum = 0; chnnum < CMP_CHN_NB; ++chnnum) {
+ if ((__LL_CMP_IT_CHECK_SOURCE(Instance, chnnum, CMP_IT_FALIE) != RESET) &&
+ ((irqtemp & (CMP_SR_FALIF_0 << chnnum)) != RESET)) {
+ /* Chear the CMP_CHx FALIF pending flag */
+ __LL_CMP_PENDING_FLAG_CLEAR(Instance, (CMP_SR_FALIF_0 << chnnum));
+
+ /* CMP falling edge trigger user callback */
+ LL_CMP_FailingEdgeTrigCallback(Instance, (0x1UL << chnnum));
+ }
+
+ if ((__LL_CMP_IT_CHECK_SOURCE(Instance, chnnum, CMP_IT_RISIE) != RESET) &&
+ ((irqtemp & (CMP_SR_RISIF_0 << chnnum)) != RESET)) {
+ /* Chear the CMP_CHx RISIF pending flag */
+ __LL_CMP_PENDING_FLAG_CLEAR(Instance, (CMP_SR_RISIF_0 << chnnum));
+
+ /* CMP rising edge trigger user callback */
+ LL_CMP_RisingEdgeTrigCallback(Instance, (0x1UL << chnnum));
+ }
+ }
+}
+
+/**
+ * @brief CMP_CHx failing edge interrupt callback function
+ * @param Instance CMP peripheral
+ * @param Channel The handling CMP channel
+ * @return None
+ */
+__WEAK void LL_CMP_FailingEdgeTrigCallback(CMP_TypeDef *Instance, uint32_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ LL_UNUSED(Channel);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CMP_FailingEdgeTrigCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CMP_CHx rising edge interrupt callback function
+ * @param Instance CMP peripheral
+ * @param Channel The handling CMP channel
+ * @return None
+ */
+__WEAK void LL_CMP_RisingEdgeTrigCallback(CMP_TypeDef *Instance, uint32_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ LL_UNUSED(Channel);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CMP_RisingEdgeTrigCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+#endif /* LL_CMP_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_cortex.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_cortex.c
new file mode 100644
index 0000000000..8bf5ec6027
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_cortex.c
@@ -0,0 +1,448 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_cortex.c
+ * @author MCD Application Team
+ * @brief CORTEX LL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX LL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M3 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using LL_NVIC_SetPriorityGrouping()
+ function according to the following table.
+ (#) Configure the priority of the selected IRQ Channels using LL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using LL_NVIC_EnableIRQ().
+ (#) please refer to programming manual for details in how to configure priority.
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest preemption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure Systick using CORTEX LL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base.
+
+ (+) The LL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value 0x07.
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
+ LL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ LL_SYSTICK_Config() function call. The LL_SYSTICK_CLKSourceConfig() function is defined below.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ LL_NVIC_SetPriority(SysTick_IRQn,...) function just after the LL_SYSTICK_Config() function
+ call. The LL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for LL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "Cortex LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/**
+ * @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX LL
+ * @brief CORTEX LL module driver
+ * @{
+ */
+
+#ifdef LL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
+ * @brief CORTEX LL Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_Exported_Functions_Group1 NVIC Priority Config Functions
+ * @brief NVIC Priority Config Functions
+ * @{
+ */
+
+/** @brief Sets the priority grouping field (preemption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup: The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ * 0 bit for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @return None
+ */
+void LL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t LL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file tae32f53xx.h)
+ * @param PreemptPriority: The preemption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 7
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 7
+ * A lower priority value indicates a higher priority.
+ * @note The table below gives the allowed values of the pre-emption priority and subpriority according
+ * to the Priority Grouping configuration performed by LL_NVIC_SetPriorityGrouping() function.
+ * =========================================================================================
+ * NVIC_PriorityGroup | PreemptPriority | SubPriority | Description
+ * =========================================================================================
+ * NVIC_PRIORITYGROUP_0 | 0 | 0-7 | 0 bit for pre-emption priority
+ * | | | 3 bits for subpriority
+ * -----------------------------------------------------------------------------------------
+ * NVIC_PRIORITYGROUP_1 | 0-1 | 0-3 | 1 bit for pre-emption priority
+ * | | | 2 bits for subpriority
+ * -----------------------------------------------------------------------------------------
+ * NVIC_PRIORITYGROUP_2 | 0-3 | 0-1 | 2 bits for pre-emption priority
+ * | | | 1 bits for subpriority
+ * -----------------------------------------------------------------------------------------
+ * NVIC_PRIORITYGROUP_3 | 0-7 | 0 | 3 bits for pre-emption priority
+ * | | | 0 bit for subpriority
+ * =========================================================================================
+ * @return None
+ */
+void LL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ * 0 bits for subpriority
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @return None
+ */
+void LL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup CORTEX_LL_Exported_Functions_Group2 NVIC Enable and Pending Config Functions
+ * @brief NVIC Enable and Pending Config Functions
+ * @{
+ */
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
+ * @return None
+ */
+void LL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
+ * @return None
+ */
+void LL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
+ * @return None
+ */
+void LL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
+ * @return pending status
+ * @retval 0 Interrupt status is not pending.
+ * @retval 1 Interrupt status is pending.
+ */
+uint32_t LL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
+ * @return None
+ */
+void LL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
+ * @return status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t LL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @param None
+ * @return None
+ */
+void LL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup CORTEX_LL_Exported_Functions_Group3 SYSTICK Config Functions
+ * @brief SYSTICK Config Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @return None
+ */
+void LL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ } else {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t LL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup CORTEX_LL_Exported_Functions_Interrupt CORTEX Interrupt management
+ * @brief CORTEX Interrupt management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupt Management #####
+ ==============================================================================
+ [..]
+ This section provides CORTEX interrupt handler functions.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles SYSTICK interrupts requests.
+ * @param None
+ * @return None
+ */
+void LL_SYSTICK_IRQHandler(void)
+{
+ LL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @param None
+ * @retval None
+ */
+__WEAK void LL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the LL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_CORTEX_MODULE_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dac.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dac.c
new file mode 100644
index 0000000000..06af9b714e
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dac.c
@@ -0,0 +1,601 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dac.c
+ * @author MCD Application Team
+ * @brief Source file for DAC Module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "DAC LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup DAC_LL DAC LL
+ * @brief DAC LL module driver
+ * @{
+ */
+
+#ifdef LL_DAC_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC LL Exported Functions
+ * @brief DAC LL Exported Functions
+ * @{
+ */
+
+/** @defgroup DAC_LL_Exported_Functions_Group1 Initialization and De-Initialization functions
+ * @brief Initialization and De-Initialization functions
+
+@verbatim
+ ==============================================================================
+ ##### Initialization and De-Initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize the DAC peripheral.
+ (+) De-initialize the DAC peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DAC peripheral
+ * @param Instance DAC peripheral instance
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_DAC_Init(DAC_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+
+ /* Init the low level hardware */
+ LL_DAC_MspInit(Instance);
+
+ /* Clear interrupt pending flags */
+ __LL_DAC_PENDING_FLAG_CLEAR(Instance, DAC_FLAG_ALLIF);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Deinitialize the DAC peripheral
+ * @param Instance DAC peripheral instance
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_DAC_DeInit(DAC_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+
+ for (uint8_t chnnum = 0; chnnum < DAC_CHN_NB; ++chnnum) {
+ /* Disable DAC Channel wave */
+ CLEAR_BIT(Instance->CR[chnnum], DAC_CR_TGE_Msk | DAC_CR_STE_Msk);
+
+ /* Disable DONE/DONEB interrupts */
+ __LL_DAC_IT_DISABLE(Instance, chnnum, DAC_IT_DIE | DAC_IT_DBIE);
+
+ /* Disable DAC Channel Output */
+ __LL_DAC_OUTPUT_DISABLE(Instance, chnnum);
+
+ /* Disable DAC Channel */
+ __LL_DAC_DISABLE(Instance, chnnum);
+ }
+
+ /* DeInit the low level hardware */
+ LL_DAC_MspDeInit(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the DAC MSP.
+ * @param Instance DAC peripheral
+ * @return None
+ */
+__WEAK void LL_DAC_MspInit(DAC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DAC MSP
+ * @param Instance DAC peripheral
+ * @return None
+ */
+__WEAK void LL_DAC_MspDeInit(DAC_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_LL_Exported_Functions_Group2 DAC Peripheral Control functions
+ * @brief DAC Peripheral Control functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Sawtooth/Tranigle wave generate configure
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param Instance DAC peripheral
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @param sConfig DAC configuration structure.
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DAC_ChannelConfig(DAC_TypeDef *Instance, uint32_t Channel, DAC_ChannelConfTypeDef *sConfig)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NUMBER(chnnum));
+ assert_param(sConfig != NULL);
+ assert_param(IS_DAC_CHANNEL_OUTPUT_SEL(sConfig->Output));
+ assert_param(IS_DAC_CHANNEL_DONE_IT_PENDING_CFG(sConfig->DoneIntPending));
+ assert_param(IS_DAC_CHANNEL_DONEB_IT_PENDING_CFG(sConfig->DoneBIntPending));
+
+ /* Reset and Calculate CR register value depending on sConfig */
+ MODIFY_REG(Instance->CR[chnnum],
+ (DAC_CR_PEN_Msk | DAC_CR_OEN_Msk
+ | DAC_CR_TGE_Msk | DAC_CR_STE_Msk
+ | DAC_CR_DIE_Msk | DAC_CR_DBIE_Msk),
+ (sConfig->Output
+ | sConfig->DoneIntPending
+ | sConfig->DoneBIntPending));
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Enable the selected DAC channel sawtooth wave generation.
+ * @param Instance DAC peripheral
+ * @param Channel The selected DAC channel.
+ * @param sConfig DAC sawtooth configuration structure.
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DAC_SawtoothWaveGenerate(DAC_TypeDef *Instance, uint32_t Channel, DAC_SawtoothConfTypeDef *sConfig)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NUMBER(chnnum));
+ assert_param(sConfig != NULL);
+ assert_param(IS_DAC_SAWTOOTH_RESET_DATA(sConfig->ResetData));
+ assert_param(IS_DAC_SAWTOOTH_STEP_DATA(sConfig->StepData));
+ assert_param(IS_DAC_SAWTOOTH_POLARITY(sConfig->Polarity));
+ assert_param(IS_DAC_SAWTOOTH_RESET_TRIGGER(sConfig->ResetTrigger));
+ assert_param(IS_DAC_SAWTOOTH_STEP_TRIGGER(sConfig->StepTrigger));
+ assert_param(sConfig->StepTrigger != sConfig->ResetTrigger);
+
+ /* Configure the sawtooth wave */
+ MODIFY_REG(Instance->CR[chnnum],
+ (DAC_CR_TGE_Msk
+ | DAC_CR_STE_Msk
+ | DAC_CR_STDIR_Msk
+ | DAC_CR_STINCTRIG_Msk
+ | DAC_CR_STRSTTRIG_Msk),
+ (sConfig->Polarity
+ | (sConfig->StepTrigger << DAC_CR_STINCTRIG_Pos)
+ | (sConfig->ResetTrigger << DAC_CR_STRSTTRIG_Pos)));
+
+ /* Configure the sawtooth wave generation data parameters */
+ WRITE_REG(Instance->SIDR[chnnum], sConfig->StepData);
+ WRITE_REG(Instance->SRDR[chnnum], sConfig->ResetData << 4);
+
+ /* Enable sawtooth wave */
+ SET_BIT(Instance->CR[chnnum], DAC_CR_STE);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Enable the selected DAC channel triangle wave generation.
+ * @param Instance DAC peripheral
+ * @param Channel The selected DAC channel.
+ * @param sConfig DAC triangle configuration structure.
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DAC_TriangleWaveGenerate(DAC_TypeDef *Instance, uint32_t Channel, DAC_TriangleConfTypeDef *sConfig)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NUMBER(chnnum));
+ assert_param(sConfig != NULL);
+ assert_param(IS_DAC_TRIANGLE_INITIALDIRECTION(sConfig->InitialDirection));
+ assert_param(IS_DAC_TRIANGLE_AMPLITUDE(sConfig->Amplitude));
+ assert_param(IS_DAC_TRIANGLE_STEP_TRIGGER(sConfig->StepTrigger));
+
+ /* Configure the triangle wave */
+ MODIFY_REG(Instance->CR[chnnum],
+ (DAC_CR_TGE_Msk
+ | DAC_CR_STE_Msk
+ | DAC_CR_TGDIR_Msk
+ | DAC_CR_TGAMP_Msk
+ | DAC_CR_TGTRIG_Msk),
+ (sConfig->InitialDirection
+ | sConfig->Amplitude
+ | (sConfig->StepTrigger << DAC_CR_TGTRIG_Pos)));
+
+ /* Enable triangle wave */
+ SET_BIT(Instance->CR[chnnum], DAC_CR_TGE);
+
+ /* Return function status */
+ return LL_OK;
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_LL_Exported_Functions_Group3 DAC IO operation functions
+ * @brief DAC IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start/Stop DAC Output.
+ (+) Simple value conversion.
+ (+) Singles conversion.
+ (+) Get result of conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC Channel conversion
+ * @param Instance DAC peripheral instance
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DAC_Start(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NUMBER(chnnum));
+
+ /* Enable DAC Channel */
+ __LL_DAC_ENABLE(Instance, chnnum);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Disable DAC Channel conversion
+ * @param Instance DAC peripheral instance
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DAC_Stop(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NUMBER(chnnum));
+
+ /* Enable DAC Channel */
+ __LL_DAC_DISABLE(Instance, chnnum);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Set the specified data value for DAC channel.
+ * @param Instance DAC peripheral instance
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @param Data Data to be loaded.
+ * This parameter can be a number in range from 0 to DAC full range 4095(0xFFF),
+ * witch will be converse to 0 - VCC
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DAC_SetValue(DAC_TypeDef *Instance, uint32_t Channel, uint16_t Data)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NUMBER(chnnum));
+
+ /* Set the data for DAC channel conversion */
+ __LL_DAC_SET_VALUE(Instance, chnnum, Data & 0xFFFUL);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Get the specified DAC channel conversion value on runtime.
+ * @param Instance DAC peripheral instance
+ * @param Channel The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @return Current conversion value
+ */
+uint16_t LL_DAC_GetValue(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Get the channel number */
+ uint8_t chnnum = POSITION_VAL(Channel);
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_NUMBER(chnnum));
+
+ return __LL_DAC_GET_VALUE(Instance, chnnum) & 0xFFFUL;
+}
+
+/**
+ * @brief Trig sawtooth wave step
+ * @param Instance DAC peripheral instance
+ * @param Channel The selected DAC channel[s].
+ * This parameter can be any combination of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DAC_SawtoothWaveDataStep(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNELS_MASK(Channel));
+
+ /* Trigger the selected DAC channel software conversion */
+ SET_BIT(Instance->SWTR, (Channel << DAC_SWTR_SWTB0_Pos));
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Trig sawtooth wave reset
+ * @param Instance DAC peripheral instance
+ * @param Channel The selected DAC channel[s].
+ * This parameter can be any combination of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DAC_SawtoothWaveDataReset(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNELS_MASK(Channel));
+
+ /* Trigger the selected DAC channel software conversion */
+ SET_BIT(Instance->SWTR, (Channel << DAC_SWTR_SWT0_Pos));
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Trig triangle wave step
+ * @param Instance DAC peripheral instance
+ * @param Channel The selected DAC channel[s].
+ * This parameter can be any combination of the following values:
+ * @arg DAC_CHANNEL_0: DAC Channel0 selected
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @arg DAC_CHANNEL_3: DAC Channel3 selected
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DAC_TriangleWaveStep(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+ assert_param(IS_DAC_CHANNELS_MASK(Channel));
+
+ /* Trigger the selected DAC channel software conversion */
+ SET_BIT(Instance->SWTR, (Channel << DAC_SWTR_SWT0_Pos));
+
+ /* Return function status */
+ return LL_OK;
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_LL_Exported_Functions_Interrupt DAC Initerrupt management
+ * @brief DAC Initerrupt management
+@verbatim
+ ===============================================================================
+ ##### Initerrupt management #####
+ ===============================================================================
+ [..]
+ This section provides DAC interrupt handler and callback functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles DAC interrupts requests.
+ * @param Instance DAC peripheral
+ * @return None
+ */
+void LL_DAC_IRQHandler(DAC_TypeDef *Instance)
+{
+ uint32_t irqtemp = READ_REG(Instance->ISR);
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(Instance));
+
+ for (uint8_t chnnum = 0; chnnum < DAC_CHN_NB; ++chnnum) {
+ if ((__LL_DAC_IT_CHECK_SOURCE(Instance, chnnum, DAC_IT_DIE) != RESET) &&
+ ((irqtemp & (DAC_ISR_D0IF << chnnum)) != RESET)) {
+ /* Chear the DAC_CHx DONE pending flag */
+ __LL_DAC_PENDING_FLAG_CLEAR(Instance, (DAC_ISR_D0IF << chnnum));
+
+ /* DACx DONE interrupt callback function */
+ LL_DAC_ConvDoneCallback(Instance, 0x1UL << chnnum);
+ }
+
+ if ((__LL_DAC_IT_CHECK_SOURCE(Instance, chnnum, DAC_IT_DBIE) != RESET) &&
+ ((irqtemp & (DAC_ISR_DB0IF << chnnum)) != RESET)) {
+ /* Chear the DAC_CHx DONEB pending flag */
+ __LL_DAC_PENDING_FLAG_CLEAR(Instance, (DAC_ISR_DB0IF << chnnum));
+
+ /* DACx DONEB interrupt callback function */
+ LL_DAC_ConvDoneBCallback(Instance, 0x1UL << chnnum);
+
+ }
+ }
+}
+
+/**
+ * @brief DAC_CHx DONE interrupt callback function
+ * @param Instance DAC peripheral
+ * @param Channel The handling DAC channel
+ * @return None
+ */
+__WEAK void LL_DAC_ConvDoneCallback(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DAC_ConvDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DAC_CHx DONE interrupt callback function
+ * @param Instance DAC peripheral
+ * @param Channel The handling DAC channel
+ * @return None
+ */
+__WEAK void LL_DAC_ConvDoneBCallback(DAC_TypeDef *Instance, uint32_t Channel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DAC_ConvDoneBCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_DAC_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dali.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dali.c
new file mode 100644
index 0000000000..26175b6dd1
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dali.c
@@ -0,0 +1,717 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dali.c
+ * @author MCD Application Team
+ * @brief Source file for DALI module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "DALI LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup DALI_LL DALI LL
+ * @brief DALI LL module driver.
+ * @{
+ */
+
+#ifdef LL_DALI_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DALI_LL_Exported_Functions DALI LL Exported Functions
+ * @brief DALI LL Exported Functions
+ * @{
+ */
+
+/** @defgroup DALI_LL_Exported_Functions_Group1 Initialization and De-Initialization functions
+ * @brief Initialization and De-Initialization functions
+@verbatim
+ ==============================================================================
+ ##### Initialization and De-Initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the DALI Module.
+ (+) De-initialize the DALI Module.
+@endverbatim
+* @{
+*/
+
+/**
+ * @brief Initialize the DALI peripheral
+ * @param Instance DALI peripheral instance
+ * @param Init pointer to a DALI_InitTypeDef structure that contains the configuration
+ * information for the specified DALI peripheral.
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_DALI_Init(DALI_TypeDef *Instance, DALI_InitTypeDef *Init)
+{
+ uint32_t prescaler = LL_SYSCTRL_APB1ClkGet() / 16 / Init->Baudrate;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+ assert_param(Init != NULL);
+ assert_param(IS_DALI_MODE(Init->Mode));
+ assert_param(IS_DALI_MESSAGE_LEN(Init->MessageLen));
+ assert_param(IS_DALI_POLARITY(Init->Polarity));
+ assert_param(IS_DALI_FILTER_ENABLE(Init->Filter));
+ assert_param(IS_DALI_FORWARD_DELAY(Init->ForwardDelay));
+ assert_param(IS_DALI_BACKWARD_DELAY(Init->BackwardDelay));
+ assert_param(IS_DALI_BAUDRATE(Init->Baudrate));
+ assert_param(IS_DALI_PRESCALE(prescaler));
+
+ /* Handle Something */
+ LL_DALI_MspInit(Instance);
+
+ /* Disable DALI before configuration */
+ __LL_DALI_DISABLE(Instance);
+
+ /* Clear all pending flags */
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, (DALI_FLAG_BEIF
+ | DALI_FLAG_FEIF
+ | DALI_FLAG_BDIF
+ | DALI_FLAG_FDIF));
+
+ /* Configures: Forward frame message length, Polarity, Working mode */
+ WRITE_REG(Instance->CR, (Init->MessageLen | Init->Polarity | Init->Mode));
+
+ /* Configures: Filter feature enable, Filter counter value */
+ if (Init->Filter == DALI_FILTER_ENABLE) {
+ assert_param(IS_DALI_FILTER_COUNTER(Init->FilterCounter));
+
+ WRITE_REG(Instance->FCR, (Init->Filter | Init->FilterCounter));
+ } else {
+ WRITE_REG(Instance->FCR, 0);
+ }
+
+ /* Configures: Prescaler */
+ WRITE_REG(Instance->PSCR, (DALI_PSCR_FTR_Msk | (prescaler & DALI_PSCR_PSC_Msk)));
+
+ /* Configures: Timing control */
+ WRITE_REG(Instance->TCR, ((Init->BackwardDelay << 16)
+ | (Init->ForwardDelay)));
+
+ /* Enable DALI module */
+ __LL_DALI_ENABLE(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief DeInitializes the DALI
+ * @param Instance DALI peripheral instance
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_DALI_DeInit(DALI_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+
+ /* Disable DALI before configuration */
+ __LL_DALI_DISABLE(Instance);
+
+ /* Handle Something */
+ LL_DALI_MspDeInit(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the DALI MSP.
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_MspInit(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DALI MSP
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_MspDeInit(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DALI_LL_Exported_Functions_Group2 DALI Peripheral State functions
+ * @brief DALI Peripheral State functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Peripheral State functions
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wait for a DALI operation to complete.
+ * @param Timeout Maximum DALI operation timeout
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DALI_WaitForLastOperation(DALI_TypeDef *Instance, uint32_t Timeout)
+{
+ uint32_t tickstart = LL_GetTick();
+
+ /* Wait for the DALI operation to complete by polling on BUSY flag to be reset.
+ Even if the DALI operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+ while (__LL_DALI_STATUS_FLAG_GET(Instance, DALI_FLAG_BSY) != RESET) {
+ if (Timeout != LL_WAIT_FOREVER) {
+ if ((Timeout == 0U) || ((LL_GetTick() - tickstart) > Timeout)) {
+ return LL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if any errors occurred */
+ if ((__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_FEIF) != RESET) ||
+ (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_BEIF) != RESET)) {
+ return LL_ERROR;
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DALI_LL_Exported_Functions_Group3 DALI IO operation functions
+ * @brief DALI IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) DALI Master Transmit forward frame (with or without interruption).
+ (+) DALI Master Receive backward frame (with or without interruption).
+ (+) DALI Slave Transmit backward frame (with or without interruption).
+ (+) DALI Slave Receive forward frame (with or without interruption).
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief DALI Master transmit forward data
+ * @note This function can only be used when DALI working in MASTER mode
+ * @param Instance DALI peripheral
+ * @param ForwardData forward frame data
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DALI_Master_Transmit(DALI_TypeDef *Instance, uint32_t ForwardData)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Write Data to Forward Data Register */
+ WRITE_REG(Instance->FDR, ForwardData & 0xFFFFFFUL);
+
+ /* Start transmission */
+ SET_BIT(Instance->CR, DALI_CR_TS);
+
+ /* Wait until operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ if (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_FDIF) != SET) {
+ status = LL_FAILED;
+ }
+
+ /* Clear forward done flag */
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_FDIF);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DALI Master transmit forward data with interrupt
+ * @note This function can only be used when DALI working in MASTER mode
+ * @param Instance DALI peripheral
+ * @param ForwardData forward frame data
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DALI_Master_Transmit_IT(DALI_TypeDef *Instance, uint32_t ForwardData)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Write Data to Forward Data Register */
+ WRITE_REG(Instance->FDR, ForwardData & 0xFFFFFFUL);
+
+ /* Enable FDIE interrupts */
+ __LL_DALI_IT_ENABLE(Instance, DALI_IT_FDIE);
+
+ /* Start transmission */
+ SET_BIT(Instance->CR, DALI_CR_TS);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DALI Master receive backward data
+ * @note This function can only be used when DALI working in MASTER mode
+ * @param Instance DALI peripheral
+ * @param BackwardData Specifies the data pointer to read in.
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DALI_Master_Receive(DALI_TypeDef *Instance, uint8_t *BackwardData)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+ assert_param(BackwardData != NULL);
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+
+ /* Check and clear BDIF flag */
+ if (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_BDIF) != RESET) {
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_BDIF);
+
+ *BackwardData = READ_REG(Instance->BDR) & 0xFFUL;
+ } else {
+ status = LL_FAILED;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DALI Master receive backward data with interrupt
+ * @note This function can only be used when DALI working in MASTER mode
+ * @param Instance DALI peripheral
+ * @note Use __LL_DALI_MSTR_READ_BACKWARD_DATA() to get the backword data in IRQ callbacks
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DALI_Master_Receive_IT(DALI_TypeDef *Instance)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Enable BDIE interrupts */
+ __LL_DALI_IT_ENABLE(Instance, DALI_IT_BDIE);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DALI Slave transmit backward data
+ * @note This function can only be used when DALI working in SLAVE mode
+ * @param Instance DALI peripheral
+ * @param BackwardData backward frame data
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DALI_Slave_Transmit(DALI_TypeDef *Instance, uint8_t BackwardData)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Write Data to Forward Data Register */
+ WRITE_REG(Instance->BDR, BackwardData);
+
+ /* Start transmission */
+ SET_BIT(Instance->CR, DALI_CR_TS);
+
+ /* Wait until operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ if (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_BDIF) != SET) {
+ status = LL_FAILED;
+ }
+
+ /* Clear forward done flag */
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_BDIF);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DALI Slave transmit backward data with interrupt
+ * @note This function can only be used when DALI working in SLAVE mode
+ * @param Instance DALI peripheral
+ * @param BackwardData backward frame data
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DALI_Slave_Transmit_IT(DALI_TypeDef *Instance, uint8_t BackwardData)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Write Data to Forward Data Register */
+ WRITE_REG(Instance->BDR, BackwardData);
+
+ /* Enable BDIE interrupts */
+ __LL_DALI_IT_ENABLE(Instance, DALI_IT_BDIE);
+
+ /* Start transmission */
+ SET_BIT(Instance->CR, DALI_CR_TS);
+
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DALI Slave receive forward data
+ * @note This function can only be used when DALI working in SLAVE mode
+ * @param Instance DALI peripheral
+ * @param ForwardData Specifies the data pointer to read in.
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DALI_Slave_Receive(DALI_TypeDef *Instance, uint32_t *ForwardData)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+ assert_param(ForwardData != NULL);
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+
+ /* Check and clear FDIF flag */
+ if (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_FDIF) != RESET) {
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_FDIF);
+
+ *ForwardData = READ_REG(Instance->FDR) & 0xFFFFFFUL;
+ } else {
+ status = LL_FAILED;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DALI Slave receive forward data with interrupt
+ * @note This function can only be used when DALI working in SLAVE mode
+ * @param Instance DALI peripheral
+ * @note Use __LL_DALI_SLV_READ_FORWARD_DATA() to get the forward data in IRQ callbacks
+ * @return LL status
+ */
+LL_StatusETypeDef LL_DALI_Slave_Receive_IT(DALI_TypeDef *Instance)
+{
+ LL_StatusETypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DALI_ALL_INSTANCE(Instance));
+
+ /* Wait until last operation complete */
+ if ((status = LL_DALI_WaitForLastOperation(Instance, DALI_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Enable FDIE interrupts */
+ __LL_DALI_IT_ENABLE(Instance, DALI_IT_FDIE);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DALI_LL_Exported_Functions_Interrupt DALI Initerrupt management
+ * @brief DALI Initerrupt management
+@verbatim
+ ===============================================================================
+ ##### Initerrupt management #####
+ ===============================================================================
+ [..]
+ This section provides DALI interrupt handler and callback functions.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles DALI interrupts requests.
+ * @param Instance DALI peripheral
+ * @return None
+ */
+void LL_DALI_IRQHandler(DALI_TypeDef *Instance)
+{
+ if ((__LL_DALI_IT_SOURCE_CHECK(Instance, DALI_IT_FDIE) != RESET) &&
+ (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_FDIF) != RESET)) {
+
+ /* Disable and clear interrupt */
+ __LL_DALI_IT_DISABLE(Instance, DALI_IT_FDIE);
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_FDIF);
+
+ if (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_FEIF) != RESET) {
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_FEIF);
+
+ /* Error detected */
+ if (READ_BIT(Instance->CR, DALI_CR_MODE_Msk) != DALI_MODE_SLAVE) {
+ LL_DALI_MstrTransmitErrorCallback(Instance);
+ } else {
+ LL_DALI_SlvReceiveErrorCallback(Instance);
+ }
+ } else {
+
+ /* Transmission complete */
+ if (READ_BIT(Instance->CR, DALI_CR_MODE_Msk) != DALI_MODE_SLAVE) {
+ LL_DALI_MstrTransmitDoneCallback(Instance);
+ } else {
+ LL_DALI_SlvReceiveDoneCallback(Instance);
+ }
+ }
+ }
+
+ if ((__LL_DALI_IT_SOURCE_CHECK(Instance, DALI_IT_BDIE) != RESET) &&
+ (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_BDIF) != RESET)) {
+
+ /* Disable and clear interrupt */
+ __LL_DALI_IT_DISABLE(Instance, DALI_IT_BDIE);
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_BDIF);
+
+ if (__LL_DALI_PENDING_FLAG_GET(Instance, DALI_FLAG_BEIF) != RESET) {
+ __LL_DALI_PENDING_FLAG_CLEAR(Instance, DALI_FLAG_BEIF);
+
+ /* Error detected */
+ if (READ_BIT(Instance->CR, DALI_CR_MODE_Msk) != DALI_MODE_SLAVE) {
+ LL_DALI_MstrRecviveErrorCallback(Instance);
+ } else {
+ LL_DALI_SlvTransmitErrorCallback(Instance);
+ }
+ } else {
+ /* Transmission complete */
+ if (READ_BIT(Instance->CR, DALI_CR_MODE_Msk) != DALI_MODE_SLAVE) {
+ LL_DALI_MstrRecviveDoneCallback(Instance);
+ } else {
+ LL_DALI_SlvTransmitDoneCallback(Instance);
+ }
+ }
+ }
+}
+
+/**
+ * @brief DALI Master receive backward frame done callback
+ * Use __LL_DALI_MSTR_READ_BACKWARD_DATA() to get the backword data
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_MstrRecviveDoneCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_MstrRecviveDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DALI Master receive backward frame failed callback
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_MstrRecviveErrorCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_MstrRecviveErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DALI Master transmit forward frame done callback
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_MstrTransmitDoneCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_MstrTransmitDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DALI Master transmit forward frame failed callback
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_MstrTransmitErrorCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_MstrTransmitErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DALI Slave receive forward frame done callback
+ * Use __LL_DALI_SLV_READ_FORWARD_DATA() to get the forward data
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_SlvReceiveDoneCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_SlvReceiveDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DALI Slave receive forward frame failed callback
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_SlvReceiveErrorCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_SlvReceiveErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DALI Slave transmit backward frame done callback
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_SlvTransmitDoneCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_SlvTransmitDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DALI Slave transmit backward frame failed callback
+ * @param Instance DALI peripheral
+ * @return None
+ */
+__WEAK void LL_DALI_SlvTransmitErrorCallback(DALI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_DALI_SlvTransmitErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_DALI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dflash.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dflash.c
new file mode 100644
index 0000000000..fb3afceb30
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dflash.c
@@ -0,0 +1,431 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dflash.c
+ * @author MCD Application Team
+ * @brief Source file for DFLASH module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "DFLASH LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup DFLASH_LL DFLASH LL
+ * @brief DFLASH LL module driver
+ * @{
+ */
+
+#ifdef LL_DFLASH_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DFLASH_LL_Exported_Functions DFLASH LL Exported Functions
+ * @brief DFLASH LL Exported Functions
+ * @{
+ */
+
+/** @defgroup DFLASH_LL_Exported_Functions_Group1 DFLASH Peripheral State functions
+ * @brief DFLASH Peripheral State functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Peripheral State functions
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wait for a DFLASH operation to complete.
+ * @param Timeout Maximum DataFlash operation timeout
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DFLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ uint32_t tickstart = LL_GetTick();
+
+ /* Wait for the DFLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the DFLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+ while (__LL_DFLASH_STATUS_FLAG_GET(DFLASH_FLAG_BSY) != RESET) {
+ if (Timeout != LL_WAIT_FOREVER) {
+ if ((Timeout == 0U) || ((LL_GetTick() - tickstart) > Timeout)) {
+ return LL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check and clear DIF flag */
+ if (__LL_DFLASH_PENDING_FLAG_GET(DFLASH_FLAG_DIF) != RESET) {
+ __LL_DFLASH_PENDING_FLAG_CLEAR(DFLASH_FLAG_DIF);
+ }
+
+ /* Check if any errors occurred */
+ if (__LL_DFLASH_PENDING_FLAG_GET(DFLASH_FLAG_EIF) != RESET) {
+ return LL_ERROR;
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DFLASH_LL_Exported_Functions_Group2 DFLASH Input and Output operation functions
+ * @brief DFLASH Input and Output operation functions
+@verbatim
+ ===============================================================================
+ ##### Input and Output operation functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Byte/Word Program operations functions
+ (+) Byte/Word Read operations functions
+ (+) Erase operations functions
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program one byte at a specified address.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @note LL_DFLASH_Unlock() should be called before to unlock the DFLASH interface
+ * LL_DFLASH_Lock() should be called after to lock the DFLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DFLASH_Program_Byte(uint32_t Address, uint8_t Data)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DFLASH_ADDRESS_MASK(Address));
+
+ /* Address mask */
+ Address &= DFLASH_PROGRAM_ADDRESS_MASK;
+
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Byte Program mode */
+ CLEAR_BIT(DFLASH->CR, DFLASH_CR_DS);
+
+ /* Fill the data into DFLASH_DR register */
+ WRITE_REG(DFLASH->DR, Data);
+
+ /* Set Address */
+ WRITE_REG(DFLASH->ADDR, Address);
+
+ /* Ignore full 0xFF data programming */
+ if ((DFLASH->DR & 0xFF) != 0xFFU) {
+ /* Pragram Start */
+ SET_BIT(DFLASH->CR, DFLASH_CR_PS);
+
+ /* Wait until operation complete */
+ status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Program one word at a specified address.
+ * @param Address specifies the address to be programmed.
+ * Notice that address must align to a word
+ * @param Data specifies the data to be programmed.
+ * @note LL_DFLASH_Unlock() should be called before to unlock the DFLASH interface
+ * LL_DFLASH_Lock() should be called after to lock the DFLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DFLASH_Program_Word(uint32_t Address, uint32_t Data)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DFLASH_ADDRESS_MASK(Address));
+ assert_param(IS_DFLASH_ADDRESS_CHECK_ALIGN(Address));
+
+ /* Address mask */
+ Address &= DFLASH_PROGRAM_ADDRESS_MASK;
+
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Byte Program mode */
+ SET_BIT(DFLASH->CR, DFLASH_CR_DS);
+
+ /* Fill the data into DFLASH_DR register */
+ WRITE_REG(DFLASH->DR, Data);
+
+ /* Set Address */
+ WRITE_REG(DFLASH->ADDR, Address);
+
+ /* Ignore full 0xFF data programming */
+ if (DFLASH->DR != 0xFFFFFFFFU) {
+ /* Pragram Start */
+ SET_BIT(DFLASH->CR, DFLASH_CR_PS);
+
+ /* Wait until operation complete */
+ status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Read one byte from a specified address.
+ * @param Address specifies the address to read.
+ * @param Data specifies the data pointer to read in.
+ * @note LL_DFLASH_Unlock() should be called before to unlock the DFLASH interface
+ * LL_DFLASH_Lock() should be called after to lock the DFLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DFLASH_Read_Byte(uint32_t Address, uint8_t *Data)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DFLASH_ADDRESS_MASK(Address));
+
+ /* Address mask */
+ Address &= DFLASH_PROGRAM_ADDRESS_MASK;
+ /* Initialize the value of Data */
+ *Data = 0;
+
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Byte Read mode */
+ CLEAR_BIT(DFLASH->CR, DFLASH_CR_DS);
+
+ /* Set Address */
+ WRITE_REG(DFLASH->ADDR, Address);
+
+ /* Read Start */
+ SET_BIT(DFLASH->CR, DFLASH_CR_RS);
+
+ /* Wait until operation complete */
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Read the data from DFLASH->DR Registers */
+ *Data = READ_REG(DFLASH->DR) & 0xFFU;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Read one wrod from a specified address.
+ * @param Address specifies the address to read.
+ * Notice that address must align to a word
+ * @param Data specifies the data pointer to read in.
+ * @note LL_DFLASH_Unlock() should be called before to unlock the DFLASH interface
+ * LL_DFLASH_Lock() should be called after to lock the DFLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DFLASH_Read_Word(uint32_t Address, uint32_t *Data)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DFLASH_ADDRESS_MASK(Address));
+ assert_param(IS_DFLASH_ADDRESS_CHECK_ALIGN(Address));
+
+ /* Address mask */
+ Address &= DFLASH_PROGRAM_ADDRESS_MASK;
+ /* Initialize the value of Data */
+ *Data = 0;
+
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Byte Read mode */
+ CLEAR_BIT(DFLASH->CR, DFLASH_CR_DS);
+
+ /* Set Address */
+ WRITE_REG(DFLASH->ADDR, Address);
+
+ /* Read Start */
+ SET_BIT(DFLASH->CR, DFLASH_CR_RS);
+
+ /* Wait until operation complete */
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Read the data from DFLASH->DR Registers */
+ *Data = READ_REG(DFLASH->DR);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief DFLASH mass erase. This will mass erase the Main-Memory area.
+ * @note Please Notice this function has no effect to the Secondary-Memory.
+ * @note LL_DFLASH_Unlock() should be called before to unlock the DFLASH interface
+ * LL_DFLASH_Lock() should be called after to lock the DFLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DFLASH_MassErase(void)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Set to Mass Erase mode */
+ SET_BIT(DFLASH->ECR, DFLASH_ECR_EMODE);
+
+ /* Erase Start */
+ SET_BIT(DFLASH->CR, DFLASH_CR_ES);
+
+ /* Wait until operation complete */
+ status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Erase one specified DFLASH memory sector. This function is effective for both
+ * Main-Memory and Secondary-Memory areas.
+ * @param sector The start sector number of the specified sectors to erase.
+ * This parameter must be a value between 0 and (NB of sectors - 1)
+ * @note LL_DFLASH_Unlock() should be called before to unlock the DFLASH interface
+ * LL_DFLASH_Lock() should be called after to lock the DFLASH interface
+ * @return Status
+ */
+LL_StatusETypeDef LL_DFLASH_SectorErase(uint16_t Sector)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DFLASH_NB_SECTORS(Sector));
+
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Set to Sector Erase mode */
+ CLEAR_BIT(DFLASH->ECR, DFLASH_ECR_EMODE);
+
+ /* Set Sector to erase */
+ MODIFY_REG(DFLASH->ECR, DFLASH_ECR_ESNB_Msk, Sector);
+
+ /* Erase Start */
+ SET_BIT(DFLASH->CR, DFLASH_CR_ES);
+
+ /* Wait until operation complete */
+ status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Erase the specified DFLASH memory multiple sectors.
+ * @param sector The start sector number of the specified sectors to erase.
+ * This parameter must be a value between 0 and (NB of sectors - 1)
+ * @param num Number of sectors to be erased.
+ * This parameter must be a value between 1 and NB of sectors
+ * @note Please notice that all specified sectors number must between 0 and (NB of sectors - 1)
+ * @param *SectorError Pointer to variable that contains the configuration information on faulty
+ * sector in case of error (0xFFFF means that all the sectors have been correctly erased).
+ * Set this pointer to NULL if you do not need it.
+ * @note LL_DFLASH_Unlock() should be called before to unlock the DFLASH interface
+ * LL_DFLASH_Lock() should be called after to lock the DFLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_DFLASH_MultiSectorsErase(uint16_t Sector, uint16_t Num, uint16_t *SectorError)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ assert_param(Num != 0);
+ assert_param(IS_DFLASH_NB_SECTORS(Sector));
+ assert_param(IS_DFLASH_NB_SECTORS(Sector + Num - 1));
+
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /*Initialization of SectorError variable*/
+ if (SectorError != NULL) {
+ *SectorError = 0xFFFF;
+ }
+
+ /* Set to Sector Erase mode */
+ CLEAR_BIT(DFLASH->ECR, DFLASH_ECR_EMODE);
+
+ /* Erase the specified sectors */
+ for (uint16_t index = Sector; index < (Sector + Num); index++) {
+ /* Set current Sector to erase */
+ MODIFY_REG(DFLASH->ECR, DFLASH_ECR_ESNB_Msk, index);
+
+ /* Erase Start */
+ SET_BIT(DFLASH->CR, DFLASH_CR_ES);
+
+ /* Wait until operation complete */
+ if ((status = LL_DFLASH_WaitForLastOperation(DFLASH_TIMEOUT_MAX_VALUE)) != LL_OK) {
+ /* In case of error, stop erase procedure and return the faulty Sector */
+ if (SectorError != NULL) {
+ *SectorError = index;
+ }
+
+ break;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_DFLASH_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dma.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dma.c
new file mode 100644
index 0000000000..50b63e09ae
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_dma.c
@@ -0,0 +1,702 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_dma.c
+ * @author MCD Application Team
+ * @brief DMA LL Module Driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "DMA LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup DMA_LL DMA LL
+ * @brief DMA LL module driver
+ * @{
+ */
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Types DMA LL Private Types
+ * @brief DMA LL Private Types
+ * @{
+ */
+
+/**
+ * @brief DMA LL config type definition
+ */
+typedef struct __DMA_LLCfgTypeDef {
+ DMA_SrcBurstLenETypeDef src_burst; /*!< source burst length */
+ DMA_DstBurstLenETypeDef dst_burst; /*!< destinationd burst length */
+ uint16_t max_burst;
+} DMA_LLCfgTypeDef;
+
+/**
+ * @brief DMA channel control type definition
+ */
+typedef struct __DMA_ChCtrlTypeDef {
+ DMA_StateETypeDef state; /*!< channel state */
+ void *end_arg; /*!< argument of transfer complete callback fucntion */
+ DMA_IRQCallback end_callback; /*!< transfer complete callback fucntion */
+ void *err_arg; /*!< argument of transfer error callback fucntion */
+ DMA_IRQCallback err_callback; /*!< transfer error callback fucntion */
+} DMA_ChCtrlTypeDef;
+
+/**
+ * @brief DMA Private control type definition
+ */
+typedef struct __DMA_PriCtrlTypeDef {
+ uint8_t ch_used; /*!< channel used variable */
+ DMA_ChCtrlTypeDef ch_ctrl[DMA_CHN_NB]; /*!< channel control params */
+} DMA_PriCtrlTypeDef;
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA LL Private Variables
+ * @brief DMA LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief DMA LL config default
+ */
+static const DMA_LLCfgTypeDef dma_ll_cfg_def = {
+ .src_burst = DMA_SRC_BURST_LEN_1, /*!< source burst default 1 */
+ .dst_burst = DMA_DST_BURST_LEN_1, /*!< destination burst default 1 */
+ .max_burst = 0x0, /*!< max burst defalut 0x0 (no limit) */
+};
+
+
+/**
+ * @brief DMA private control global variable
+ */
+static DMA_PriCtrlTypeDef dma_pri_ctrl;
+
+/**
+ * @}
+ */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA LL Exported Functions
+ * @brief DMA LL Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_Exported_Functions_Group1 DMA Init Function
+ * @brief DMA Init function
+ * @{
+ */
+
+/**
+ * @brief DMA LL init
+ * @param Instance Specifies DMA peripheral
+ * @param ch channel to init
+ * @param user_cfg user config pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_DMA_Init(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, DMA_UserCfgTypeDef *user_cfg)
+{
+ DMA_LLCfgTypeDef *ll_cfg = (DMA_LLCfgTypeDef *)&dma_ll_cfg_def;
+
+ //Check config params to be valid
+ if (Instance == NULL || ch >= DMA_CHANNEL_NUM || user_cfg == NULL) {
+ LOG_E("Init Params config error!\n");
+ return LL_ERROR;
+ }
+
+ //Burst config
+ __LL_DMA_SrcBurstLen_Set(Instance, ch, ll_cfg->src_burst);
+ __LL_DMA_DstBurstLen_Set(Instance, ch, ll_cfg->dst_burst);
+ __LL_DMA_BurstLenMax_Set(Instance, ch, ll_cfg->max_burst);
+
+ //User config
+ __LL_DMA_TransType_Set(Instance, ch, user_cfg->trans_type);
+ __LL_DMA_SrcAddrMode_Set(Instance, ch, user_cfg->src_addr_mode);
+ __LL_DMA_DstAddrMode_Set(Instance, ch, user_cfg->dst_addr_mode);
+ __LL_DMA_SrcTransWidth_Set(Instance, ch, user_cfg->src_data_width);
+ __LL_DMA_DstTransWidth_Set(Instance, ch, user_cfg->dst_data_width);
+
+ //Source and destination handshake mode config
+ if (user_cfg->trans_type == DMA_TRANS_TYPE_P2M || user_cfg->trans_type == DMA_TRANS_TYPE_P2P) {
+ __LL_DMA_SrcHandshakeMode_Clr(Instance, ch);
+ } else {
+ __LL_DMA_SrcHandshakeMode_Set(Instance, ch);
+ }
+
+ if (user_cfg->trans_type == DMA_TRANS_TYPE_M2P || user_cfg->trans_type == DMA_TRANS_TYPE_P2P) {
+ __LL_DMA_DstHandshakeMode_Clr(Instance, ch);
+ } else {
+ __LL_DMA_DstHandshakeMode_Set(Instance, ch);
+ }
+
+ //Channel priority config to default
+ if (ch == DMA_CHANNEL_0) {
+ __LL_DMA_ChannelPriLow_Set(Instance, ch);
+ } else if (ch == DMA_CHANNEL_1) {
+ __LL_DMA_ChannelPriHigh_Set(Instance, ch);
+ }
+
+ //Source and destination handshake interface config
+ if (user_cfg->src_hs_ifc != DMA_SRC_HANDSHAKE_IFC_MEMORY) {
+ __LL_DMA_SrcHandshakeIfc_Set(Instance, ch, user_cfg->src_hs_ifc);
+ }
+
+ if (user_cfg->dst_hs_ifc != DMA_DST_HANDSHAKE_IFC_MEMORY) {
+ __LL_DMA_DstHandshakeIfc_Set(Instance, ch, user_cfg->dst_hs_ifc);
+ }
+
+ //Peripheral enable
+ __LL_DMA_Periph_En(Instance);
+
+ //IRQ callback config
+ dma_pri_ctrl.ch_ctrl[ch].end_callback = user_cfg->end_callback;
+ dma_pri_ctrl.ch_ctrl[ch].end_arg = user_cfg->end_arg;
+ dma_pri_ctrl.ch_ctrl[ch].err_callback = user_cfg->err_callback;
+ dma_pri_ctrl.ch_ctrl[ch].err_arg = user_cfg->err_arg;
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief DMA LL deinit
+ * @param Instance Specifies DMA peripheral
+ * @param ch channel to deinit
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_DMA_DeInit(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch)
+{
+ uint8_t i;
+
+ //Check config params to be valid
+ if (Instance == NULL || ch >= DMA_CHANNEL_NUM) {
+ LOG_E("Deinit Params config error!\n");
+ return LL_ERROR;
+ }
+
+ //IRQ callback deinit
+ dma_pri_ctrl.ch_ctrl[ch].end_callback = NULL;
+ dma_pri_ctrl.ch_ctrl[ch].end_arg = NULL;
+ dma_pri_ctrl.ch_ctrl[ch].err_callback = NULL;
+ dma_pri_ctrl.ch_ctrl[ch].err_arg = NULL;
+
+ //Update channel state to Reset
+ dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_RESET;
+
+ //Peripheral disable when all channels close
+ for (i = 0; i < DMA_CHANNEL_NUM; i++) {
+ if (dma_pri_ctrl.ch_ctrl[i].state != DMA_STATE_RESET) {
+ break;
+ }
+ }
+
+ if (i == DMA_CHANNEL_NUM) {
+ __LL_DMA_Periph_Dis(Instance);
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_LL_Exported_Functions_Group2 DMA Channel Management Functions
+ * @brief DMA Channel Management Functions
+ * @{
+ */
+
+/**
+ * @brief DMA LL channel request
+ * @param None
+ * @return DMA_ChannelETypeDef
+ */
+DMA_ChannelETypeDef LL_DMA_ChannelRequest(void)
+{
+ uint8_t i;
+ DMA_ChannelETypeDef avl_ch = DMA_CHANNEL_INVALID;
+
+ //Search available channel
+ for (i = 0; i < DMA_CHANNEL_NUM; i++) {
+ if (!READ_BIT(dma_pri_ctrl.ch_used, BIT(i)) && (dma_pri_ctrl.ch_ctrl[i].state == DMA_STATE_RESET)) {
+ SET_BIT(dma_pri_ctrl.ch_used, BIT(i));
+ avl_ch = (DMA_ChannelETypeDef)i;
+ break;
+ }
+ }
+
+ return avl_ch;
+}
+
+/**
+ * @brief DMA LL request specific channel
+ * @param ch specific channel to request
+ * @return DMA_ChannelETypeDef
+ */
+DMA_ChannelETypeDef LL_DMA_ChReqSpecific(DMA_ChannelETypeDef ch)
+{
+ if (ch < DMA_CHANNEL_NUM && !READ_BIT(dma_pri_ctrl.ch_used, BIT(ch)) && (dma_pri_ctrl.ch_ctrl[ch].state == DMA_STATE_RESET)) {
+ SET_BIT(dma_pri_ctrl.ch_used, BIT(ch));
+ } else {
+ ch = DMA_CHANNEL_INVALID;
+ }
+
+ return ch;
+}
+
+/**
+ * @brief DMA LL channel release
+ * @param ch channel to release
+ * @return None
+ */
+void LL_DMA_ChannelRelease(DMA_ChannelETypeDef ch)
+{
+ if (dma_pri_ctrl.ch_ctrl[ch].state == DMA_STATE_RESET) {
+ CLEAR_BIT(dma_pri_ctrl.ch_used, BIT(ch));
+ }
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_LL_Exported_Functions_Group3 DMA Start and Stop Functions
+ * @brief DMA Start and Stop Functions
+ * @{
+ */
+
+/**
+ * @brief DMA LL start in CPU mode
+ * @param Instance Specifies DMA peripheral
+ * @param ch channel to start
+ * @param src_addr source address
+ * @param dst_addr destination address
+ * @param data_len transfer data length
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_DMA_Start_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch,
+ uint32_t src_addr, uint32_t dst_addr, uint32_t data_len)
+{
+ uint8_t src_data_width;
+ uint32_t block_size;
+
+ if (ch >= DMA_CHANNEL_NUM) {
+ LOG_E("Invalid ch-[%d]!\n", ch);
+ return LL_ERROR;
+ }
+
+ //Config block size, which is associate to data length
+ src_data_width = __LL_DMA_SrcTransWidth_Get(Instance, ch);
+
+ if (src_data_width > 2) {
+ LOG_E("Source data width config error-[%d]!\n", src_data_width);
+ return LL_ERROR;
+ }
+
+ src_data_width = BIT(src_data_width);
+ block_size = data_len / src_data_width;
+
+ if (block_size > LL_DMA_BLOCK_SIZE_MAX) {
+ LOG_E("Block size max is %d, while now is %d!\n", LL_DMA_BLOCK_SIZE_MAX, block_size);
+ return LL_ERROR;
+ }
+
+ __LL_DMA_BlockTransCnt_Set(Instance, ch, block_size);
+
+ //Check and update channel state
+ if (dma_pri_ctrl.ch_ctrl[ch].state != DMA_STATE_READY) {
+ LOG_E("Channel state-[%d] isn't in Ready!\n", dma_pri_ctrl.ch_ctrl[ch].state);
+ return LL_ERROR;
+ }
+
+ dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_BUSY;
+
+ //Config source and destination peripheral bus master 1/2
+ if (src_addr >= LL_DMA_SRMBC_ADDR_START && src_addr <= LL_DMA_SRMBC_ADDR_END) { //SRAMB & SRAMC
+ __LL_DMA_SrcPeriphBus_Set(Instance, ch, DMA_SRC_PERIPH_BUS_AHB_MST2);
+ } else { //SRAMA & Peripheral & Flash
+ __LL_DMA_SrcPeriphBus_Set(Instance, ch, DMA_SRC_PERIPH_BUS_AHB_MST1);
+ }
+
+ if (dst_addr >= LL_DMA_SRMBC_ADDR_START && dst_addr <= LL_DMA_SRMBC_ADDR_END) { //SRAMB & SRAMC
+ __LL_DMA_DstPeriphBus_Set(Instance, ch, DMA_DST_PERIPH_BUS_AHB_MST2);
+ } else { //SRAMA & Peripheral & Flash
+ __LL_DMA_DstPeriphBus_Set(Instance, ch, DMA_DST_PERIPH_BUS_AHB_MST1);
+ }
+
+ //source and destination address config
+ __LL_DMA_SrcAddr_Set(Instance, ch, src_addr);
+ __LL_DMA_DstAddr_Set(Instance, ch, dst_addr);
+
+ //Channel enable
+ if (ch == DMA_CHANNEL_0) {
+ __LL_DMA_Ch0_En(Instance);
+ } else if (ch == DMA_CHANNEL_1) {
+ __LL_DMA_Ch1_En(Instance);
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief DMA LL start in interrupt mode
+ * @param Instance Specifies DMA peripheral
+ * @param ch channel to start
+ * @param src_addr source address
+ * @param dst_addr destination address
+ * @param data_len transfer data length
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_DMA_Start_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch,
+ uint32_t src_addr, uint32_t dst_addr, uint32_t data_len)
+{
+ //Channel interrupt enable
+ __LL_DMA_Channel_Int_En(Instance, ch);
+
+ //Channel transfer complete and error interrupt enable
+ if (ch == DMA_CHANNEL_0) {
+ __LL_DMA_Ch0TransCom_Int_En(Instance);
+ __LL_DMA_Ch0TransErr_Int_En(Instance);
+ } else if (ch == DMA_CHANNEL_1) {
+ __LL_DMA_Ch1TransCom_Int_En(Instance);
+ __LL_DMA_Ch1TransErr_Int_En(Instance);
+ }
+
+ return LL_DMA_Start_CPU(Instance, ch, src_addr, dst_addr, data_len);
+}
+
+/**
+ * @brief DMA LL Stop in CPU mode
+ * @param Instance Specifies DMA peripheral
+ * @param ch channel to stop
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_DMA_Stop_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch)
+{
+ //Check and update channel state
+ if (dma_pri_ctrl.ch_ctrl[ch].state == DMA_STATE_RESET) {
+ LOG_E("Channel state is in RESET!\n");
+ return LL_ERROR;
+ }
+
+ dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
+
+ //Channel disable
+ if (ch == DMA_CHANNEL_0) {
+ __LL_DMA_Ch0_Dis(Instance);
+ } else if (ch == DMA_CHANNEL_1) {
+ __LL_DMA_Ch1_Dis(Instance);
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief DMA LL Stop in interrupt mode
+ * @param Instance Specifies DMA peripheral
+ * @param ch channel to stop
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_DMA_Stop_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch)
+{
+ LL_StatusETypeDef ret;
+
+ ret = LL_DMA_Stop_CPU(Instance, ch);
+
+ if (ret != LL_OK) {
+ return ret;
+ }
+
+ //Channel interrupt disable
+ __LL_DMA_Channel_Int_Dis(Instance, ch);
+
+ //Channel transfer complete and error interrupt disable
+ if (ch == DMA_CHANNEL_0) {
+ __LL_DMA_Ch0TransCom_Int_Dis(Instance);
+ __LL_DMA_Ch0TransErr_Int_Dis(Instance);
+ } else if (ch == DMA_CHANNEL_1) {
+ __LL_DMA_Ch1TransCom_Int_Dis(Instance);
+ __LL_DMA_Ch1TransErr_Int_Dis(Instance);
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief DMA LL wait for transfer complete in CPU mode
+ * @param Instance Specifies DMA peripheral
+ * @param ch channel to wait for transfer complete
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_DMA_WaitComplete_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret = LL_ERROR;
+
+ //Check channel state
+ if (dma_pri_ctrl.ch_ctrl[ch].state != DMA_STATE_BUSY) {
+ LOG_E("Channel state-[%d] isn't in Busy!\n", dma_pri_ctrl.ch_ctrl[ch].state);
+ return LL_ERROR;
+ }
+
+ tickstart = LL_GetTick();
+
+ switch (ch) {
+ case DMA_CHANNEL_0:
+ while (!__LL_DMA_Ch0TransErrSta_Get(Instance)) { //transfer normal, no error
+ if (__LL_DMA_Ch0TransComSta_Get(Instance)) { //transfer complete
+ //Clear complete status
+ __LL_DMA_Ch0TransComSta_Clr(Instance);
+ ret = LL_OK;
+ break;
+ }
+
+ if ((LL_GetTick() - tickstart) > timeout) { //transfer timeout
+ ret = LL_TIMEOUT;
+ break;
+ }
+ }
+
+ //Clear error status
+ __LL_DMA_Ch0TransErrSta_Clr(Instance);
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
+
+ break;
+
+ case DMA_CHANNEL_1:
+ while (!__LL_DMA_Ch1TransErrSta_Get(Instance)) { //transfer normal, no error
+ if (__LL_DMA_Ch1TransComSta_Get(Instance)) { //transfer complete
+ //Clear complete status
+ __LL_DMA_Ch1TransComSta_Clr(Instance);
+ ret = LL_OK;
+ break;
+ }
+
+ if ((LL_GetTick() - tickstart) > timeout) { //transfer timeout
+ ret = LL_TIMEOUT;
+ break;
+ }
+ }
+
+ //Clear error status
+ __LL_DMA_Ch1TransErrSta_Clr(Instance);
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[ch].state = DMA_STATE_READY;
+
+ break;
+
+ default:
+ break;;
+ }
+
+ return ret;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_LL_Exported_Functions_Interrupt DMA Interrupt handler and call back
+ * @brief DMA Interrupt handler and call back
+ * @{
+ */
+
+/**
+ * @brief DMA IRQ Handler
+ * @param Instance Specifies DMA peripheral
+ * @return None
+ */
+void LL_DMA_IRQHandler(DMA_TypeDef *Instance)
+{
+ //Transfer complete interrupt handler
+ if (__LL_DMA_Ch0TransComIntSta_Get(Instance)) { //Channel 0 transfer complete interrupt
+ //Disable interrupt in single mode
+ __LL_DMA_Ch0TransCom_Int_Dis(Instance);
+ __LL_DMA_Ch0TransErr_Int_Dis(Instance);
+
+ //Clear pending
+ __LL_DMA_Ch0TransComSta_Clr(Instance);
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
+
+ //Interrupt callback
+ if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].end_callback) {
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].end_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].end_arg);
+ }
+
+ }
+
+ if (__LL_DMA_Ch1TransComIntSta_Get(Instance)) { //Channel 1 transfer complete interrupt
+ //Disable interrupt in single mode
+ __LL_DMA_Ch1TransCom_Int_Dis(Instance);
+ __LL_DMA_Ch1TransErr_Int_Dis(Instance);
+
+ //Clear pending
+ __LL_DMA_Ch1TransComSta_Clr(Instance);
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
+
+ //Interrupt callback
+ if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].end_callback) {
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].end_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].end_arg);
+ }
+
+ }
+
+
+ //Transfer error interrupt handler
+ if (__LL_DMA_Ch0TransErrIntSta_Get(Instance)) { //Channel 0 transfer error interrupt
+ //Disable interrupt in single mode
+ __LL_DMA_Ch0TransCom_Int_Dis(Instance);
+ __LL_DMA_Ch0TransErr_Int_Dis(Instance);
+
+ //Clear pending
+ __LL_DMA_Ch0TransErrSta_Clr(Instance);
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
+
+ //Interrupt callback
+ if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].err_callback) {
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].err_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].err_arg);
+ }
+
+ }
+
+ if (__LL_DMA_Ch1TransErrIntSta_Get(Instance)) { //Channel 1 transfer error interrupt
+ //Disable interrupt in single mode
+ __LL_DMA_Ch1TransCom_Int_Dis(Instance);
+ __LL_DMA_Ch1TransErr_Int_Dis(Instance);
+
+ //Clear pending
+ __LL_DMA_Ch1TransErrSta_Clr(Instance);
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
+
+ //Interrupt callback
+ if (dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].err_callback) {
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].err_callback(dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].err_arg);
+ }
+
+ }
+
+
+ //Block transfer complete interrupt handler
+ if (__LL_DMA_Ch0BlockTransComIntSta_Get(Instance)) { //Channel 0 block transfer complete interrupt
+ __LL_DMA_Ch0BlockTransComSta_Clr(Instance);
+ //:TODO: according to need
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
+ }
+
+ if (__LL_DMA_Ch1BlockTransComIntSta_Get(Instance)) { //Channel 1 block transfer complete interrupt
+ __LL_DMA_Ch1BlockTransComSta_Clr(Instance);
+ //:TODO: according to need
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
+ }
+
+
+ //Source transfer complete interrupt handler
+ if (__LL_DMA_Ch0SrcTransComIntSta_Get(Instance)) { //Channel 0 source transfer complete interrupt
+ __LL_DMA_Ch0SrcTransComSta_Clr(Instance);
+ //:TODO: according to need
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
+ }
+
+ if (__LL_DMA_Ch1SrcTransComIntSta_Get(Instance)) { //Channel 1 source transfer complete interrupt
+ __LL_DMA_Ch1SrcTransComSta_Clr(Instance);
+ //:TODO: according to need
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
+ }
+
+
+ //Destination transfer complete interrupt handler
+ if (__LL_DMA_Ch0DstTransComIntSta_Get(Instance)) { //Channel 0 destination transfer complete interrupt
+ __LL_DMA_Ch0DstTransComSta_Clr(Instance);
+ //:TODO: according to need
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_0].state = DMA_STATE_READY;
+ }
+
+ if (__LL_DMA_Ch1DstTransComIntSta_Get(Instance)) { //Channel 1 destination transfer complete interrupt
+ __LL_DMA_Ch1DstTransComSta_Clr(Instance);
+ //:TODO: according to need
+
+ //Update channel state to Ready
+ dma_pri_ctrl.ch_ctrl[DMA_CHANNEL_1].state = DMA_STATE_READY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_DMA_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_ecu.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_ecu.c
new file mode 100644
index 0000000000..a8c6c162ab
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_ecu.c
@@ -0,0 +1,318 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_ecu.c
+ * @author MCD Application Team
+ * @brief ECU LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "ECU LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup ECU_LL ECU LL
+ * @brief ECU LL module driver
+ * @{
+ */
+
+#ifdef LL_ECU_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ECU_LL_Exported_Functions ECU LL Exported Functions
+ * @brief ECU LL Exported Functions
+ * @{
+ */
+
+/** @defgroup ECU_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the ECU
+ to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the ECU peripheral according to the specified parameters in the ECU_Init.
+ * @param ECU_Init: pointer to a ECU_InitTypeDef structure that contains
+ * the configuration information for the specified ECU peripheral.
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_ECU_Init(ECU_TypeDef *Instance, ECU_InitTypeDef *ECU_Init)
+{
+ /*hardware level Initializes*/
+ LL_ECU_MspInit(Instance);
+ /*check paramter*/
+ assert_param(IS_ECU_MODULE(ECU_Init->ModuleEnable));
+ assert_param(IS_ECU_AVERAGE(ECU_Init->AverageSel));
+ assert_param(IS_ECU_ACSFT(ECU_Init->ACLeftShift));
+ assert_param(IS_ECU_APSFT(ECU_Init->APRightShift));
+ assert_param(IS_ECU_DATSEL(ECU_Init->DataSel));
+ assert_param(IS_ECU_CRSSEL(ECU_Init->CrossZeroSel));
+
+ if (ECU_Init->ModuleEnable == ENABLE) {
+ /*ECU control register, enable mdule */
+ if (ECU_Init->InterruptEn == ENABLE) {
+ SET_BIT(Instance->CON, ECU_CON_ENABLE | ECU_CON_INTEN);
+ } else {
+ SET_BIT(Instance->CON, ECU_CON_ENABLE);
+ }
+
+ /*Configure averages the data results*/
+ /*Configure The right shift number of power results and
+ *the left shift number of active power results are configured.*/
+ MODIFY_REG(Instance->CON,
+ ECU_CON_AVGSEL
+ | ECU_CON_APSFT
+ | ECU_CON_ACSFT,
+ ECU_Init->AverageSel
+ | ECU_Init->APRightShift
+ | ECU_Init->ACLeftShift
+ );
+ /*Configure the corresponding event selection bits*/
+ MODIFY_REG(Instance->PRC,
+ ECU_PRC_CRSSEL
+ | ECU_PRC_ADRSEL
+ | ECU_PRC_DATSEL,
+ ECU_Init->CrossZeroSel
+ | ECU_Init->AddressSel
+ | ECU_Init->DataSel
+ );
+ /*Configure cache voltage and current data storage addresses and offset addresses*/
+ /*Configure voltage start address*/
+ MODIFY_REG(Instance->V_ADDR1, ECU_V_ADDR1_STADDR, ECU_Init->VStartAddr);
+ /*Configure voltage offset address*/
+ MODIFY_REG(Instance->V_ADDR2, ECU_V_ADDR2_OFADDR, ECU_Init->VOffsetAddr);
+ /*Configure current start address*/
+ MODIFY_REG(Instance->I_ADDR1, ECU_I_ADDR1_STADDR, ECU_Init->IStartAddr);
+ /*Configure current offset address*/
+ MODIFY_REG(Instance->I_ADDR2, ECU_I_ADDR2_OFADDR, ECU_Init->IOffsetAddr);
+
+ return LL_OK;
+ } else {
+ return LL_ERROR;
+ }
+}
+
+/**
+ * @brief De-initializes the ECU peripheral registers to their default reset values.
+ * @return status of the de-initialization
+ */
+LL_StatusETypeDef LL_ECU_DeInit(ECU_TypeDef *Instance)
+{
+ /*Get the current working status of the ECU*/
+ if (__LL_ECU_GET_STA(Instance)) {
+ /*Disable the module*/
+ __LL_ECU_MODULE_DISABLE(Instance);
+ }
+
+ /*Reset configuration register,Sets the value of the register to restore the default value */
+ MODIFY_REG(Instance->CON,
+ ECU_CON_INTEN | ECU_CON_INT | ECU_CON_AVGSEL | ECU_CON_APSFT | ECU_CON_ACSFT,
+ (0x8U << ECU_CON_APSFT_Pos) | (0x8U << ECU_CON_ACSFT_Pos)
+ );
+ /*Reset the event selection register*/
+ CLEAR_BIT(Instance->PRC, ECU_PRC_DATSEL | ECU_PRC_ADRSEL | ECU_PRC_CRSSEL);
+ /*Clears the input square root data*/
+ CLEAR_REG(Instance->SQRT_IN);
+ /*Clear the starting address of the voltage buffer*/
+ CLEAR_BIT(Instance->V_ADDR1, ECU_V_ADDR1_STADDR);
+ /*Clear the offset address of the voltage buffer*/
+ CLEAR_BIT(Instance->V_ADDR2, ECU_V_ADDR2_OFADDR);
+ /*Clear the starting address of the current buffer*/
+ CLEAR_BIT(Instance->I_ADDR1, ECU_I_ADDR1_STADDR);
+ /*Clear the offset address of the current buffer*/
+ CLEAR_BIT(Instance->I_ADDR2, ECU_I_ADDR2_OFADDR);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the ECU MSP.
+ * @param ECU ECU instance
+ * @return None
+ */
+__WEAK void LL_ECU_MspInit(ECU_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ECU_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the ECU MSP
+ * @param ECU ECU instance
+ * @return None
+ */
+__WEAK void LL_ECU_MspDeInit(ECU_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ECU_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup ECU_LL_Exported_Functions_Group2 ECU Read calulate result operation functions
+ * @brief ECU Read calulate result operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Read result value functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the ECUs:
+ (+) Read the ECU SQRT_OUT value
+ (+) Write the ECU SQRT_IN value
+ @note For the above operation of reading registers, please determine whether the mark of completion of calculation
+ is set before reading, or try to read data in the interrupt
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the data input that you want to take the square root of
+ * @param __VALUE__ input data
+ * @return None
+ */
+void LL_ECU_WriteSqrtInData(ECU_TypeDef *Instance, uint32_t SqrtValue)
+{
+ /*Check whether the last square root calculation was completed.*/
+ if (__LL_ECU_SQRT_DONE_FLAG(Instance)) {
+ /*If not, wait for the flag to clear*/
+ while (__LL_ECU_SQRT_DONE_FLAG(Instance));
+ }
+
+ /*If complete, write the data you need to take the square root of*/
+ MODIFY_REG(Instance->SQRT_IN, ECU_SQRT_INDATA, SqrtValue);
+ /*Square root enable*/
+ __LL_ECU_SQRT_ENABLE(Instance);
+}
+
+/**
+ * @brief Get the result of square root data
+ * @param Instance ECU instance
+ * @return The result of the square root of the input data
+ */
+uint32_t LL_ECU_ReadSqrtOutData(ECU_TypeDef *Instance)
+{
+ /*Check whether the last square root calculation was completed.*/
+ if (__LL_ECU_SQRT_DONE_FLAG(Instance)) {
+ /*If not, wait for the flag to clear*/
+ while (__LL_ECU_SQRT_DONE_FLAG(Instance));
+ }
+
+ /*If completed, the result of the operation is read*/
+ return (uint32_t)READ_REG(Instance->SQRT_OUT);
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup ECU_LL_Exported_Functions_Interrupt ECU IRQ handler management
+ * @brief ECU IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides ECU IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles ECU interrupts requests.
+ * @param ECU ECU instance
+ * @return None
+ */
+void LL_ECU_IRQHandler(ECU_TypeDef *Instance)
+{
+ if (__LL_ECU_DONE_GET_IT(Instance) && __LL_ECU_DONE_GET_FLAG(Instance)) {
+ __LL_ECU_DONE_CLEAR_FLAG(Instance);
+
+ /*Handle something*/
+ LL_ECU_CalDoneCallback(Instance);
+ }
+}
+
+/**
+ * @brief ECU parameters calculate completed detection callback.
+ * @return None
+ */
+__WEAK void LL_ECU_CalDoneCallback(ECU_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_ECU_CalDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_ECU_MODULE_ENABLE */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_flash.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_flash.c
new file mode 100644
index 0000000000..56f525677f
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_flash.c
@@ -0,0 +1,491 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_flash.c
+ * @author MCD Application Team
+ * @brief FLASH LL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Erase operations functions
+ * + Peripheral State functions
+ * + Write Protection Area configure functions
+ * + Read Protection Level configure functions
+ * + Interrupt and Callback functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "FLASH LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH_LL FLASH LL
+ * @brief Flash LL module driver.
+ * @{
+ */
+
+#ifdef LL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_LL_Private_Variables FLASH LL Private Variables
+ * @brief FLASH LL Private Variables
+ * @{
+ */
+
+/** @brief Variable whitch recorded the error codes.
+ * This parameter can be any combination of @ref FLASH_Error_Codes
+ */
+static uint32_t FlashErrorCode = FLASH_ERROR_NONE;
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_LL_Private_Functions FLASH LL Private Functions
+ * @brief FLASH LL Private Functions
+ * @{
+ */
+static void FLASH_SetErrorCode(void);
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_LL_Exported_Functions FLASH LL Exported Functions
+ * @brief FLASH LL Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_LL_Exported_Functions_Group1 FLASH Peripheral Control functions
+ * @brief FLASH Peripheral Control functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Read Protection Level configure
+ (+) Write Protection Area configure
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read Protection Level configuration.
+ * @param RDPLevel specifies the read protection level
+ * This parameter can be a value of @ref FLASH_Read_Protection_Level:
+ * @arg FLASH_RDP_LEVEL_0 : No protection
+ * @arg FLASH_RDP_LEVEL_1 : Memory Read protection
+ * @arg FLASH_RDP_LEVEL_2 : Full chip protection
+ * @note When enabling read protection level 2, it's no more possible to
+ * go back to level 1 or level 0.
+ * @note The function @ref LL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref LL_FLASH_PF_Unlock() should be called before to unlock the protection feature
+ * The function @ref LL_FLASH_PF_Launch() should be called after to force the reload of the new configuration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_FLASH_ReadProtectLevelConfig(FLASH_RDPLVETypeDef RDPLevel)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ if ((status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Clear error code before operation */
+ FlashErrorCode = FLASH_ERROR_NONE;
+
+ /* Configure the RDP level in the userdata register */
+ MODIFY_REG(FLASH->RDPR, FLASH_RDPR_RDP_Msk, RDPLevel);
+
+ /* Wait until operation complete */
+ status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Write Protection configuration.
+ * @param WRPAreas specifies the area to configure Write Protection.
+ * This parameter can be any combination value of @ref FLASH_Write_Protection_Area.
+ * @param WRPState Enable/Disable WRP state for the specifies WPRAreas.
+ * This parameter can be a value of @ref FLASH_WRP_State:
+ * @arg FLASH_WRPSTATE_DISABLE: Disable specifies areas WRP
+ * @arg FLASH_WRPSTATE_ENABLE: Enable specifies areas WRP
+ * @note Once memory area Write Protection is enabled, user must not program the memory area
+ * until the protection is disabled.
+ * @note The function @ref LL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref LL_FLASH_PF_Unlock() should be called before to unlock the protection feature
+ * The function @ref LL_FLASH_PF_Launch() should be called after to force the reload of the new configuration
+ * @return Status
+ */
+LL_StatusETypeDef LL_FLASH_WriteProtectConfig(FLASH_WRPAREAETypeDef WRPAreas, FLASH_WRPSTETypeDef WRPState)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ if ((status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Clear error code before operation */
+ FlashErrorCode = FLASH_ERROR_NONE;
+
+ if (WRPState == FLASH_WRPSTATE_ENABLE) {
+ /* Enable the Write Protection */
+ CLEAR_BIT(FLASH->WRPR, WRPAreas);
+ } else {
+ /* Disable the Write Protection */
+ SET_BIT(FLASH->WRPR, WRPAreas);
+ }
+
+ /* Wait until operation complete */
+ status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASH_LL_Exported_Functions_Group2 FLASH Peripheral State functions
+ * @brief FLASH Peripheral State functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Peripheral State functions
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout Maximum flash operation timeout
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ uint32_t tickstart = LL_GetTick();
+
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+ while (__LL_FLASH_GET_STATUS_FLAG(FLASH_FLAG_BSY) != RESET) {
+ if (Timeout != LL_WAIT_FOREVER) {
+ if ((Timeout == 0U) || ((LL_GetTick() - tickstart) > Timeout)) {
+ return LL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check and clear DIF flag */
+ if (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_DIF) != RESET) {
+ __LL_FLASH_CLEAR_PENDING_FLAG(FLASH_FLAG_DIF);
+ }
+
+ /* Check if any errors occurred */
+ if ((__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_RPEIF) != RESET) ||
+ (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_WPEIF) != RESET) ||
+ (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_OPTEIF) != RESET) ||
+ (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_ECCEIF) != RESET)) {
+ /* Save the error code */
+ FLASH_SetErrorCode();
+ return LL_ERROR;
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Get the specific FLASH error flags.
+ * @return The returned value can be any combination of @ref FLASH_Error_Codes
+ */
+uint32_t LL_FLASH_GetError(void)
+{
+ return FlashErrorCode;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASH_LL_Exported_Functions_Group3 FLASH Input and Output operation functions
+ * @brief FLASH Input and Output operation functions
+@verbatim
+ ===============================================================================
+ ##### Input and Output operation functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Program operations functions
+ (+) Erase operations functions
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program 16 bytes (128 bit) at a specified address.
+ * @param Address specifies the address to be programmed.
+ * Notice that address must align to 128 bit
+ * @param Data[] specifies the data to be programmed.
+ * FLASH_PROG_DATA_WIDTH bytes will be programmed in a single operation.
+ * @note LL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * LL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_FLASH_Program(uint32_t Address, uint8_t Data[FLASH_PROG_DATA_WIDTH])
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(Data != NULL);
+ assert_param(IS_FLASH_PROGRAM_ADDRESS_ALIGN_128BIT(Address));
+
+ /* Address mask */
+ Address &= FLASH_PROGRAM_ADDRESS_MASK;
+
+ if ((status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Clear error code before operation */
+ FlashErrorCode = FLASH_ERROR_NONE;
+
+ /* Fill the data into FLASH Program Control Registers */
+ FLASH->DR0 = *((__IO uint32_t *)(Data + 0));
+ FLASH->DR1 = *((__IO uint32_t *)(Data + 4));
+ FLASH->DR2 = *((__IO uint32_t *)(Data + 8));
+ FLASH->DR3 = *((__IO uint32_t *)(Data + 12));
+
+ /* Set Address */
+ FLASH->ADDR = Address;
+
+ /* Ignore full 0xFF data programming */
+ if ((FLASH->DR0 != 0xFFFFFFFFU) &&
+ (FLASH->DR1 != 0xFFFFFFFFU) &&
+ (FLASH->DR2 != 0xFFFFFFFFU) &&
+ (FLASH->DR3 != 0xFFFFFFFFU)) {
+
+ /* Pragram Start */
+ SET_BIT(FLASH->CR, FLASH_CR_PS);
+
+ /* Wait until operation complete */
+ status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE);
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Erase one specified FLASH memory sector.
+ * @param sector The start sector number of the specified sectors to erase.
+ * This parameter must be a value between 0 and (NB of sectors - 1)
+ * @note LL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * LL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @return Status
+ */
+LL_StatusETypeDef LL_FLASH_SectorErase(uint16_t Sector)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_NB_SECTORS(Sector));
+
+ if ((status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Clear error code before operation */
+ FlashErrorCode = FLASH_ERROR_NONE;
+
+ /* Set to Sector Erase mode */
+ CLEAR_BIT(FLASH->ECR, FLASH_ECR_EMODE);
+
+ /* Set Sector to erase */
+ MODIFY_REG(FLASH->ECR, FLASH_ECR_ESNB_Msk, Sector);
+
+ /* Erase Start */
+ SET_BIT(FLASH->CR, FLASH_CR_ES);
+
+ /* Wait until operation complete */
+ status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Erase the specified FLASH memory multiple sectors.
+ * @param sector The start sector number of the specified sectors to erase.
+ * This parameter must be a value between 0 and (NB of sectors - 1)
+ * @param num Number of sectors to be erased.
+ * This parameter must be a value between 1 and NB of sectors
+ * @note Please notice that all specified sectors number must between 0 and (NB of sectors - 1)
+ * @param *SectorError Pointer to variable that contains the configuration information on faulty
+ * sector in case of error (0xFFFF means that all the sectors have been correctly erased).
+ * Set this pointer to NULL if you do not need it.
+ * @note LL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * LL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_FLASH_MultiSectorsErase(uint16_t Sector, uint16_t Num, uint16_t *SectorError)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ assert_param(Num != 0);
+ assert_param(IS_FLASH_NB_SECTORS(Sector));
+ assert_param(IS_FLASH_NB_SECTORS(Sector + Num - 1));
+
+ if ((status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Clear error code before operation */
+ FlashErrorCode = FLASH_ERROR_NONE;
+
+ /*Initialization of SectorError variable*/
+ if (SectorError != NULL) {
+ *SectorError = 0xFFFF;
+ }
+
+ /* Set to Sector Erase mode */
+ CLEAR_BIT(FLASH->ECR, FLASH_ECR_EMODE);
+
+ /* Erase the specified sectors */
+ for (uint16_t index = Sector; index < (Sector + Num); index++) {
+ /* Set current Sector to erase */
+ MODIFY_REG(FLASH->ECR, FLASH_ECR_ESNB_Msk, index);
+
+ /* Erase Start */
+ SET_BIT(FLASH->CR, FLASH_CR_ES);
+
+ /* Wait until operation complete */
+ if ((status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE)) != LL_OK) {
+ /* In case of error, stop erase procedure and return the faulty Sector */
+ if (SectorError != NULL) {
+ *SectorError = index;
+ }
+
+ break;
+ }
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief FLASH memory mass erase. This will erase the entire FLASH memory.
+ * @note LL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * LL_FLASH_Lock() should be called after to lock the FLASH interface
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_FLASH_ChipErase(void)
+{
+ LL_StatusETypeDef status = LL_OK;
+
+ if ((status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE)) == LL_OK) {
+ /* Clear error code before operation */
+ FlashErrorCode = FLASH_ERROR_NONE;
+
+ /* Set to Chip Erase mode */
+ SET_BIT(FLASH->ECR, FLASH_ECR_EMODE);
+
+ /* Erase Start */
+ SET_BIT(FLASH->CR, FLASH_CR_ES);
+
+ /* Wait until operation complete */
+ status = LL_FLASH_WaitForLastOperation(FLASH_TIMEOUT_MAX_VALUE);
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup FLASH_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @return None
+ */
+static void FLASH_SetErrorCode(void)
+{
+ if (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_RPEIF) != RESET) {
+ FlashErrorCode |= FLASH_ERROR_RDP;
+ __LL_FLASH_CLEAR_PENDING_FLAG(FLASH_FLAG_RPEIF);
+ }
+
+ if (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_WPEIF) != RESET) {
+ FlashErrorCode |= FLASH_ERROR_WRP;
+ __LL_FLASH_CLEAR_PENDING_FLAG(FLASH_FLAG_WPEIF);
+ }
+
+ if (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_OPTEIF) != RESET) {
+ FlashErrorCode |= FLASH_ERROR_OPT;
+ __LL_FLASH_CLEAR_PENDING_FLAG(FLASH_FLAG_OPTEIF);
+ }
+
+ if (__LL_FLASH_GET_PENDING_FLAG(FLASH_FLAG_ECCEIF) != RESET) {
+ FlashErrorCode |= FLASH_ERROR_ECC;
+ __LL_FLASH_CLEAR_PENDING_FLAG(FLASH_FLAG_ECCEIF);
+ }
+}
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_FLASH_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_fpll.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_fpll.c
new file mode 100644
index 0000000000..389621e922
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_fpll.c
@@ -0,0 +1,166 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_fpll.c
+ * @author MCD Application Team
+ * @brief FPLL LL Module Driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "FPLL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup FPLL_LL FPLL LL
+ * @brief FPLL LL Module Driver
+ * @{
+ */
+
+#ifdef LL_FPLL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FPLL_LL_Exported_Functions FPLL LL Exported Functions
+ * @brief FPLL LL Exported Functions
+ * @{
+ */
+
+/** @defgroup FPLL_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the FPLL peripheral
+ * @param Instance Specifies FPLL peripheral
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_FPLL_Init(FPLL_TypeDef *Instance)
+{
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_FPLL_MspInit(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief DeInitializes the FPLL peripheral
+ * @param Instance Specifies FPLL peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_FPLL_DeInit(FPLL_TypeDef *Instance)
+{
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_FPLL_MspDeInit(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the FPLL MSP
+ * @param Instance Specifies FPLL peripheral
+ * @retval None
+ */
+__WEAK void LL_FPLL_MspInit(FPLL_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_FPLL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the FPLL MSP
+ * @param Instance Specifies FPLL peripheral
+ * @retval None
+ */
+__WEAK void LL_FPLL_MspDeInit(FPLL_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_FPLL_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup FPLL_LL_Exported_Functions_Group2 FPLL Config Fucntions
+ * @brief FPLL Config Fucntions
+ * @{
+ */
+
+/**
+ * @brief FPLL LL Start
+ * @param Instance Specifies FPLL peripheral
+ * @param integer FPLL Div integer
+ * @param frac FPLL Div Fraction
+ * @return FPLL Start Result
+ */
+LL_StatusETypeDef LL_FPLL_DivStart(FPLL_TypeDef *Instance, uint16_t integer, uint16_t frac)
+{
+ if (Instance == NULL) {
+ LOG_E("FPLL Div config params error!\n");
+ return LL_ERROR;
+ }
+
+ __LL_FPLL_DivInt_Set(Instance, integer);
+ __LL_FPLL_DivFrac_Set(Instance, frac);
+ __LL_FPLL_En(Instance);
+ __LL_FPLL_Start(Instance);
+
+ return LL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_FPLL_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_gpio.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_gpio.c
new file mode 100644
index 0000000000..f70d6e6221
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_gpio.c
@@ -0,0 +1,471 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO LL module driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "GPIO LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO_LL GPIO LL
+ * @brief GPIO LL module driver
+ * @{
+ */
+
+#ifdef LL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO LL Exported Functions
+ * @brief GPIO LL Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the GPIOs
+ to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx: where x can be (A, B, ... depending on device used) to select the GPIO peripheral
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position = 0x00U;
+ uint32_t iocurrent;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+
+
+ /* Configure the port pins */
+ while (((GPIO_Init->Pin) >> position) != 0x00U) {
+ /* Get current io position */
+ iocurrent = (GPIO_Init->Pin) & (1UL << position);
+
+ if (iocurrent != 0x00U) {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ switch (GPIO_Init->Mode & 0x03U) {
+ /*In case of Alternate function mode selection*/
+ case GPIO_MODE_AF:
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ MODIFY_REG(GPIOx->PMUXR[position >> 3U], 0x0FU << ((position & 0x07U) * 4U),
+ (GPIO_Init->Alternate & 0x0FU) << ((position & 0x07U) * 4U));
+
+ /* Configure the IO Output Type */
+ MODIFY_REG(GPIOx->OTYPR, 0x01U << position, (GPIO_Init->OType & 0x01U) << position);
+
+ /* Configure the IO Speed */
+ MODIFY_REG(GPIOx->OSRR, 0x01U << position, (GPIO_Init->Speed & 0x01U) << position);
+ break;
+
+ /* In case of Input function mode selection */
+ case GPIO_MODE_INPUT:
+ /* Configure IO Direction mode (Input) */
+ MODIFY_REG(GPIOx->PMUXR[position >> 3U], 0x0FU << ((position & 0x07U) * 4U),
+ GPIO_AF0_INPUT << ((position & 0x07U) * 4U));
+
+ /* Interrupt Eanble */
+ MODIFY_REG(GPIOx->ITER, 0x01U << position, ((GPIO_Init->Mode >> 28U) & 0x01U) << position);
+
+ /* Rising/Falling Edge */
+ MODIFY_REG(GPIOx->RFTSR, 0x01U << position, ((GPIO_Init->Mode >> 20U) & 0x01U) << position);
+ MODIFY_REG(GPIOx->RFTSR, 0x01U << (position + 16U), ((GPIO_Init->Mode >> 21U) & 0x01U) << (position + 16U));
+
+ /* GPIO Port Interrupt Enable */
+ WRITE_REG(GPIOx->IER, (READ_REG(GPIOx->ITER) == 0x00UL) ? 0x00UL : 0x01UL);
+
+ /* Clear Pending */
+ WRITE_REG(GPIOx->PR, 0x01U << position);
+ break;
+
+ /* In case of Output function mode selection */
+ case GPIO_MODE_OUTPUT:
+
+ /* Configure the IO Output Type */
+ MODIFY_REG(GPIOx->PMUXR[position >> 3U], 0x0FU << ((position & 0x07U) * 4U),
+ GPIO_AF1_OUTPUT << ((position & 0x07U) * 4U));
+
+ /* Configure the IO Output Type */
+ MODIFY_REG(GPIOx->OTYPR, 0x01U << position, (GPIO_Init->OType & 0x01U) << position);
+
+ /* Configure the IO Speed */
+ MODIFY_REG(GPIOx->OSRR, 0x01U << position, (GPIO_Init->Speed & 0x01U) << position);
+ break;
+ }
+
+
+ /* Activate the Pull-up resistor for the current IO */
+ if (GPIO_Init->Pull == GPIO_PULLUP) {
+ SET_BIT(GPIOx->PUR, 0x01U << position);
+ CLEAR_BIT(GPIOx->PDR, 0x01U << position);
+ }
+
+ /* Activate the Pull-dowm resistor for the current IO */
+ if (GPIO_Init->Pull == GPIO_PULLDOWN) {
+ CLEAR_BIT(GPIOx->PUR, 0x01U << position);
+ SET_BIT(GPIOx->PDR, 0x01U << position);
+ }
+
+ /* Unactivate the Pull-up or Pull down resistor for the current IO */
+ if (GPIO_Init->Pull == GPIO_NOPULL) {
+ CLEAR_BIT(GPIOx->PUR, 0x01U << position);
+ CLEAR_BIT(GPIOx->PDR, 0x01U << position);
+ }
+ }
+
+ position++;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A, B, ... depending on device used) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of @ref GPIO_pins_define
+ * @return status of the de-initialization
+ */
+LL_StatusETypeDef LL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position = 0x00U;
+ uint32_t iocurrent;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while ((GPIO_Pin >> position) != 0x00U) {
+ /* Get current io position */
+ iocurrent = GPIO_Pin & (0x1U << position);
+
+ if (iocurrent != 0x00U) {
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure the default Alternate Function in current IO */
+ MODIFY_REG(GPIOx->PMUXR[position >> 3U], (0x0FU << ((uint32_t)(position & 0x07U) * 4U)),
+ (GPIO_AF15_ANALOG << ((uint32_t)(position & 0x07U) * 4U)));
+
+ /* Configure the default value for IO Speed */
+ CLEAR_BIT(GPIOx->OSRR, 0x01U << position);
+
+ /* Configure the default value IO Output Type */
+ CLEAR_BIT(GPIOx->OTYPR, 0x01U << position);
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ CLEAR_BIT(GPIOx->PDR, 0x01U << position);
+ CLEAR_BIT(GPIOx->PUR, 0x01U << position);
+
+ /* Disable Interrupt Mask */
+ CLEAR_BIT(GPIOx->ITER, 0x01U << position);
+
+ /* Clear Rising Falling edge configuration */
+ CLEAR_BIT(GPIOx->RFTSR, 0x01U << position);
+ CLEAR_BIT(GPIOx->RFTSR, 0x01U << (position + 16U));
+
+ /* Disable Interrupt */
+ WRITE_REG(GPIOx->IER, (READ_REG(GPIOx->ITER) == 0) ? 0x00 : 0x01);
+
+ /* Clear Pending */
+ WRITE_REG(GPIOx->PR, 0x01U << position);
+
+ /* Defalut value of data */
+ CLEAR_BIT(GPIOx->DR, 0x01U << position);
+ }
+
+ position++;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_LL_Exported_Functions_Group2 GPIO Peripheral Control functions
+ * @brief GPIO Peripheral Control functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) GPIO configure functions
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Config the alternate function on runtime.
+ * @param GPIOx where x can be (A, B, ...) to select the GPIO peripheral for TXF53xx
+ * @param GPIO_Pin specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @param Alternate Peripheral to be connected to the selected pins.
+ * This parameter can be a value of @ref GPIO_Alternate_function_selection
+ * @return None
+ */
+void LL_GPIO_AF_Config(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_AFETypeDef Alternate)
+{
+ uint32_t position = 0x00U;
+ uint32_t iocurrent;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while (((GPIO_Pin) >> position) != 0x00U) {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & (1UL << position);
+
+ if (iocurrent != 0x00U) {
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ MODIFY_REG(GPIOx->PMUXR[position >> 3U], 0x0FU << ((position & 0x07U) * 4U),
+ (Alternate) << ((position & 0x07U) * 4U));
+ }
+
+ /* Next pin */
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_LL_Exported_Functions_Group3 GPIO IO operation functions
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the GPIOs:
+ (+) Read the GPIOx Pins
+ (+) Write the GPIOx Pins
+ (+) Toggle the GPIOx Pins
+ (+) Write the GPIOx Port
+ (+) Read the GPIOx Port
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the specified input port pin
+ * @param GPIOx where x can be (A, B, ...) to select the GPIO peripheral for TXF53xx
+ * @param GPIO_Pin specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @return The input port pin value.
+ */
+GPIO_PinStateETypeDef LL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinStateETypeDef bitstatus;
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->DR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) {
+ bitstatus = GPIO_PIN_SET;
+ } else {
+ bitstatus = GPIO_PIN_RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Set or clear the selected data port bit.
+ * @param GPIOx: where x can be (A, B, ...) to select the GPIO peripheral.
+ * @param bit_field: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @param PinState specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @return None
+ */
+void LL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinStateETypeDef PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if (PinState != GPIO_PIN_RESET) {
+ GPIOx->BSRR = GPIO_Pin;
+ } else {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
+ }
+}
+
+/**
+ * @brief Toggle the specified GPIO pin.
+ * @param GPIOx where x can be (A, B, ...) to select the GPIO peripheral.
+ * @param GPIO_Pin specifies the pin to be toggled.
+ * @return None
+ */
+void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->DR ^= (GPIO_Pin & GPIO_PIN_All);
+}
+
+/**
+ * @brief Write data to the specified GPIO port.
+ * @param GPIOx where x can be (A, B, ...) to select the GPIO peripheral.
+ * @param Data data to write.
+ * @return None
+ */
+void LL_GPIO_WriteData(GPIO_TypeDef *GPIOx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ WRITE_REG(GPIOx->DR, Data);
+}
+
+
+/**
+ * @brief Read data from the specified GPIO port.
+ * @param GPIOx where x can be (A, B, ...) to select the GPIO peripheral.
+ * @return GPIO port data
+ */
+uint16_t LL_GPIO_ReadData(GPIO_TypeDef *GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ return READ_REG(GPIOx->DR) & 0xFFFFUL;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup GPIO_LL_Exported_Functions_Interrupt GPIO Initerrupt management
+ * @brief GPIO Initerrupt management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides GPIO IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles GPIO interrupts requests.
+ * @param GPIOx GPIO Port
+ * @return None
+ */
+void LL_GPIO_IRQHandler(GPIO_TypeDef *GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ for (uint8_t position = 0x00U; position < GPIO_NUMBER; position++) {
+ if ((__LL_GPIO_IT_CHECK_SOURCE(GPIOx, 0x01U << position) != RESET) &&
+ (__LL_GPIO_GET_IT(GPIOx, 0x01U << position)) != RESET) {
+
+ __LL_GPIO_CLEAR_IT(GPIOx, 0x01U << position);
+
+ /*Handle something*/
+ LL_GPIO_ExtTrigCallback(GPIOx, 0x01U << position);
+ }
+ }
+}
+
+/**
+ * @brief GPIO External Trigger detection callback.
+ * @param GPIOx GPIO Port
+ * @param GPIO_Pin witch trigger the interruption.
+ * @return None
+ */
+__WEAK void LL_GPIO_ExtTrigCallback(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(GPIOx);
+ LL_UNUSED(GPIO_Pin);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_GPIO_ExtTrigCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_GPIO_MODULE_ENABLE */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_hrpwm.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_hrpwm.c
new file mode 100644
index 0000000000..75ae37ec11
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_hrpwm.c
@@ -0,0 +1,2961 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_hrpwm.c
+ * @author MCD Application Team
+ * @brief HRPWM LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "HRPWM LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup HRPWM_LL HRPWM LL
+ * @brief HRPWM LL module driver
+ * @{
+ */
+
+#ifdef LL_HRPWM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HRPWM_LL_Private_Functions HRPWM LL Private Functions
+ * @brief HRPWM LL Private Functions
+ * @{
+ */
+static void HRPWM_MasterBase_Config(HRPWM_TypeDef *Instance, HRPWM_TimerBaseCfgTypeDef *pTimeBaseCfg);
+static void HRPWM_TimingUnitBase_Config(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_TimerBaseCfgTypeDef *pTimeBaseCfg);
+static void HRPWM_MasterCompare_Config(HRPWM_TypeDef *Instance, HRPWM_TimerCompareCfgTypeDef *pTimerCompCfg);
+static void HRPWM_TimingUnitCompare_Config(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerCompareCfgTypeDef *pTimerCompCfg);
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HRPWM_LL_Exported_Functions HRPWM LL Exported Functions
+ * @brief HRPWM LL Exported Functions
+ * @{
+ */
+
+/** @defgroup HRPWM_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+@verbatim
+ ===============================================================================
+ ##### Initialization and Time Base Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize a HRPWM instance
+ (+) De-initialize a HRPWM instance
+ (+) Initialize the HRPWM MSP
+ (+) De-initialize the HRPWM MSP
+ (+) Start the high-resolution unit and configure relevant paramter (start DLL calibration)
+ (+) Only Start the high-resolution (start DLL calibration)
+ (+) Configure the time base unit of a HRPWM timer
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize a HRPWM instance
+ * @param pSync pointer to HRPWM_MasterSyncTypeDef
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_Init(HRPWM_TypeDef *Instance, HRPWM_MasterSyncTypeDef *pMasterSync)
+{
+
+ uint32_t hrpwm_mcr;
+
+ /* Init the low level hardware */
+ LL_HRPWM_MspInit(Instance);
+
+ /* HRPWM output synchronization configuration (if required) */
+ if ((pMasterSync->SyncOptions & HRPWM_SYNCOPTION_MASTER) != (uint32_t)RESET) {
+ /* Check parameters */
+ assert_param(IS_HRPWM_SYNCOUTPUTSOURCE(pMasterSync->SyncOutputSource));
+ assert_param(IS_HRPWM_SYNCOUTPUTPOLARITY(pMasterSync->SyncOutputPolarity));
+
+ /* The synchronization output initialization procedure must be done prior
+ to the configuration of the MCU outputs (done within LL_HRPWM_MspInit)
+ */
+
+ hrpwm_mcr = Instance->Master.MCR;
+
+ /* Set the event to be sent on the synchronization output */
+ hrpwm_mcr &= ~(HRPWM_MCR_SYNCOUT_SRC);
+ hrpwm_mcr |= (pMasterSync->SyncOutputSource & HRPWM_MCR_SYNCOUT_SRC);
+
+ /* Set the polarity of the synchronization output */
+ hrpwm_mcr &= ~(HRPWM_MCR_SYNCOUT_POL);
+ hrpwm_mcr |= (pMasterSync->SyncOutputPolarity & HRPWM_MCR_SYNCOUT_POL);
+
+ /* Set the polarity of the synchronization output */
+ hrpwm_mcr &= ~(HRPWM_MCR_SYNCOUT_EN);
+ hrpwm_mcr |= (pMasterSync->SyncOutputEnable & HRPWM_MCR_SYNCOUT_EN);
+
+ /* Update the HRPWM registers */
+ Instance->Master.MCR = hrpwm_mcr;
+ }
+
+ /* HRPWM input synchronization configuration (if required) MultiplePWM*/
+ if ((pMasterSync->SyncOptions & HRPWM_SYNCOPTION_SLAVE) != (uint32_t)RESET) {
+ /* Check parameters */
+ assert_param(IS_HRPWM_SYNINPUTSOURCE(pMasterSync->SyncInputSource));
+
+ hrpwm_mcr = Instance->Master.MCR;
+
+ /* Set the synchronization input */
+ hrpwm_mcr &= ~(HRPWM_MCR_SYNCIN_EN | HRPWM_MCR_SYNCIN_SRC);
+ hrpwm_mcr |= (pMasterSync->SyncInputSource & (HRPWM_MCR_SYNCIN_EN | HRPWM_MCR_SYNCIN_SRC));
+
+ /* Update the HRPWM registers */
+ Instance->Master.MCR = hrpwm_mcr;
+ }
+
+
+ return LL_OK;
+}
+
+/**
+ * @brief De-initialize a HRPWM instance
+ * @param hhrpwm pointer to LL HRPWM handle
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_DeInit(HRPWM_TypeDef *Instance)
+{
+ /*stop all counter and output*/
+ __LL_HRPWM_ALL_TIMER_DISABLE(Instance);
+ __LL_HRPWM_OUTPUT_STOP(HRPWM_OUTPUT_ODIS0A | HRPWM_OUTPUT_ODIS0B |
+ HRPWM_OUTPUT_ODIS1A | HRPWM_OUTPUT_ODIS1B |
+ HRPWM_OUTPUT_ODIS2A | HRPWM_OUTPUT_ODIS2B |
+ HRPWM_OUTPUT_ODIS3A | HRPWM_OUTPUT_ODIS3B |
+ HRPWM_OUTPUT_ODIS4A | HRPWM_OUTPUT_ODIS4B |
+ HRPWM_OUTPUT_ODIS5A | HRPWM_OUTPUT_ODIS5B
+ );
+ /* DeInit the low level hardware */
+ LL_HRPWM_MspDeInit(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief MSP initialization for a HRPWM instance
+ * @retval None
+ */
+__WEAK void LL_HRPWM_MspInit(HRPWM_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_HRPWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief MSP de-initialization of a HRPWM instance
+ * @retval None
+ */
+__WEAK void LL_HRPWM_MspDeInit(HRPWM_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_HRPWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HRPWM_LL_Exported_Functions_Group2 HRPWM Config Functions
+ * @brief HRPWM Config Functions
+ * @{
+ */
+
+/**
+ * @brief Start the DLL configuration
+ * @param CalibrationRate DLL calibration period
+ * This parameter can be one of the following values:
+ * @arg HRPWM_DLLCR_DLLGCP
+ * @retval LL status
+ * @note LL_HRPWM_DLLCalibration function, just before exiting the function.
+ */
+LL_StatusETypeDef LL_HRPWM_DLLStartConfig(HRPWM_TypeDef *Instance, HRPWM_DLLCfgTypedef *DLLConfig)
+{
+ uint32_t temp_dllcr;
+ /* Check the parameters */
+ assert_param(IS_HRPWM_DLLGCP(DLLConfig->CurrentSel));
+
+ temp_dllcr = Instance->Common.DLLCR;
+
+ /*config dll paramter*/
+ temp_dllcr &= ~(HRPWM_DLLCR_DLLGCP | HRPWM_DLLCR_DLLTHRES1 | HRPWM_DLLCR_DLLTHRES0);
+ temp_dllcr |= (DLLConfig->CurrentSel & HRPWM_DLLCR_DLLGCP) |
+ ((DLLConfig->ClockDelayThres0 << 11U) & HRPWM_DLLCR_DLLTHRES0) |
+ ((DLLConfig->ClockDelayThres1 << 6U) & HRPWM_DLLCR_DLLTHRES1);
+
+ /*enable dll and start*/
+ temp_dllcr |= (HRPWM_DLLCR_DLLEN | HRPWM_DLLCR_DLLSTART);
+
+ /*configuration current*/
+ Instance->Common.DLLCR = temp_dllcr;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Start the DLL
+ * @retval LL status
+ * @note Only enable and start DLL, do not do other related parameter configuration, use the default value.
+ */
+LL_StatusETypeDef LL_HRPWM_DLLStart(HRPWM_TypeDef *Instance)
+{
+ /*enable dll and start*/
+ Instance->Common.DLLCR |= (HRPWM_DLLCR_DLLEN | HRPWM_DLLCR_DLLSTART);
+ /*Start 20us after DLL is started, wait for 1ms to stabilize*/
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the time base unit of a timer
+ * @param hhrpwm pointer to LL HRPWM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @param pTimeBaseCfg pointer to the time base configuration structure
+ * @note This function must be called prior starting the timer
+ * @note The time-base unit initialization parameters specify:
+ * The timer counter operating mode (continuous, one shot),
+ * The timer clock prescaler,
+ * The timer period,
+ * The timer repetition counter.
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_TimerBaseConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_TimerBaseCfgTypeDef *pTimeBaseCfg)
+{
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_SYNCSTART(pTimeBaseCfg->StartOnSync));
+ assert_param(IS_HRPWM_SYNCRESET(pTimeBaseCfg->ResetOnSync));
+ assert_param(IS_HRPWM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
+ assert_param(IS_HRPWM_MODE(pTimeBaseCfg->Mode));
+
+ if (TimerIdx == HRPWM_INDEX_MASTER) {
+ assert_param(IS_HRPWM_MASTER_IT(pTimeBaseCfg->InterruptRequests));
+ /* Configure master timer time base unit */
+ HRPWM_MasterBase_Config(Instance, pTimeBaseCfg);
+ } else {
+ /* Check parameters */
+ assert_param(IS_HRPWM_TIMER_IT(pTimeBaseCfg->InterruptRequests));
+ assert_param(IS_HRPWM_RST_EVENT(pTimeBaseCfg->ResetTrigger));
+ assert_param(IS_HRPWM_RESYNCUPDATE(pTimeBaseCfg->ReSyncUpdate));
+ /* Configure timing unit time base unit */
+ HRPWM_TimingUnitBase_Config(Instance, TimerIdx, pTimeBaseCfg);
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the general behavior of a timer operating in waveform mode
+ * @param hhrpwm pointer to LL HRPWM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @param TimeBaseCfg pointer to the time base configuration structure
+ * @note This function must be called prior starting the timer
+ * @note The time-base unit initialization parameters specify:
+ * The timer counter operating mode (continuous, one shot),
+ * The timer clock prescaler,
+ * The timer period,
+ * The timer repetition counter.
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_TimerCompareConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerCompareCfgTypeDef *pTimerCompCfg)
+{
+ /* Check the parameters, Relevant for all HRPWM timers, including the master*/
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_PRELOAD(pTimerCompCfg->PreloadEnable));
+
+
+ if (TimerIdx == HRPWM_INDEX_MASTER) {
+ /* Configure master timer time base unit */
+ HRPWM_MasterCompare_Config(Instance, pTimerCompCfg);
+ } else {
+ assert_param(IS_HRPWM_UPDATETRIGGER(pTimerCompCfg->UpdateTrigger));
+ /* Configure timing unit time base unit */
+ HRPWM_TimingUnitCompare_Config(Instance, TimerIdx, pTimerCompCfg);
+ }
+
+ return LL_OK;
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup HRPWM_LL_Exported_Functions_Group3 HRPWM Simple time base mode functions
+ * @brief HRPWM Simple time base mode functions
+@verbatim
+ ===============================================================================
+ ##### Simple time base mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start simple time base counter
+ (+) Stop simple time base counter
+ -@- When a HRPWM timer operates in simple time base mode, the timer
+ counter counts from 0 to the period value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the counter of a timer operating in simple time base mode.
+ * @param hhrpwm pointer to HAL HRPWM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval HAL status
+ */
+LL_StatusETypeDef LL_HRPWM_StartCounter(uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ /* Enable the timer counter */
+ __LL_HRPWM_TIMER_ENABLE(TimerIdx);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Stop the counter of a timer operating in simple time base mode.
+ * @param hhrpwm pointer to HAL HRPWM handle
+ * @param TimerIdx Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval HAL status
+ */
+LL_StatusETypeDef LL_HRPWM_StopCounter(uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ /* Disable the timer counter */
+ __LL_HRPWM_TIMER_DISABLE(TimerIdx);
+
+ return LL_OK;
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup HRPWM_LL_Exported_Functions_Group4 HRPWM Simple PWM output mode functions
+ * @brief HRPWM Simple PWM output functions
+@verbatim
+ ===============================================================================
+ ##### Simple PWM output functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the contrl refister - rollover mode
+ (+) Configure the Dual Channel Dac behavior
+ (+) Configure updown counter rollover mode
+ -@- When a HRPWM timer operates in simple output compare mode
+ the output level is set to a programmable value when a match
+ is found between the compare register and the counter.
+ Compare unit A is automatically associated to output A
+ Compare unit B is automatically associated to output B
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the Dual Channel Dac behavior and updown count rollover mode
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @param pTimerRollOverCfg pointer to the timer RollOver configuration structure
+ * @note When the timer operates in waveform mode, all the features supported by
+ * the HRPWM are available without any limitation.
+ * @retval LL status
+ * @note This function must be called before starting the timer
+ */
+LL_StatusETypeDef LL_HRPWM_TimerUintRollOverContrl(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerRollOverCfgTypeDef *pTimerRollOverCfg)
+{
+ if (TimerIdx == HRPWM_INDEX_MASTER) {
+ return LL_ERROR;
+ }
+
+ uint32_t hrpwm_cr1;
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_ROLLOVERMODE(pTimerRollOverCfg->RollOverMode));
+ assert_param(IS_HRPWM_OUTPUTROLLOVERMODE(pTimerRollOverCfg->OutputRollOverMode));
+ assert_param(IS_HRPWM_ADCROLLOVERMODE(pTimerRollOverCfg->AdcRollOverMode));
+ assert_param(IS_HRPWM_FLTROLLOVERMODE(pTimerRollOverCfg->FaultRollOverMode));
+ assert_param(IS_HRPWM_EVTROLLOVERMODE(pTimerRollOverCfg->EeventRollOverMode));
+
+ /* Configure timing unit (Timer 0 to Timer 5) */
+ hrpwm_cr1 = Instance->PWM[TimerIdx].CR1;
+
+ if (pTimerRollOverCfg->UpDownMode == HRPWM_CR1_UDM) {
+ /* Set the UpDown counting Mode */
+ hrpwm_cr1 &= ~(HRPWM_CR1_UDM | HRPWM_CR1_ROM | HRPWM_CR1_OUTROM | HRPWM_CR1_ADROM | HRPWM_CR1_FLTROM |
+ HRPWM_CR1_EEVROM);
+ hrpwm_cr1 |= ((pTimerRollOverCfg->OutputRollOverMode & HRPWM_CR1_OUTROM) |
+ (pTimerRollOverCfg->UpDownMode & HRPWM_CR1_UDM) |
+ (pTimerRollOverCfg->RollOverMode & HRPWM_CR1_ROM) |
+ (pTimerRollOverCfg->AdcRollOverMode & HRPWM_CR1_ADROM) |
+ (pTimerRollOverCfg->FaultRollOverMode & HRPWM_CR1_FLTROM) |
+ (pTimerRollOverCfg->EeventRollOverMode & HRPWM_CR1_EEVROM));
+ }
+
+ /* Update the HRPWM registers */
+ Instance->PWM[TimerIdx].CR1 |= hrpwm_cr1;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the Dual Channel Dac behavior of a timer operating in waveform mode
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @param pTimerDacCfg pointer to the timer DualChannel Dac configuration structure
+ * @note When the timer operates in waveform mode, all the features supported by
+ * the HRPWM are available without any limitation.
+ * @retval LL status
+ * @note This function must be called before starting the timer
+ */
+LL_StatusETypeDef LL_HRPWM_TimerDualChannelDacConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerDaulDacCfgTypeDef *pTimerDacCfg)
+{
+ if (TimerIdx == HRPWM_INDEX_MASTER) {
+ return LL_ERROR;
+ }
+
+ uint32_t hrpwm_cr1;
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_DUALDAC_RESET(pTimerDacCfg->DualChannelDacReset));
+ assert_param(IS_HRPWM_DUALDAC_STEP(pTimerDacCfg->DualChannelDacStep));
+ assert_param(IS_HRPWM_DUALDAC_ENABLE(pTimerDacCfg->DualChannelDacEnable));
+
+
+ /* Configure timing unit (Timer 0 to Timer 5) */
+ hrpwm_cr1 = Instance->PWM[TimerIdx].CR1;
+
+ if (pTimerDacCfg->DualChannelDacEnable == HRPWM_DAC_DCDE_ENABLE) {
+ /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */
+ hrpwm_cr1 &= ~(HRPWM_CR1_DCDR);
+ hrpwm_cr1 |= pTimerDacCfg->DualChannelDacReset;
+
+ /* Set the DualChannel DAC Step trigger : requires DCDE enabled */
+ hrpwm_cr1 &= ~(HRPWM_CR1_DCDS);
+ hrpwm_cr1 |= pTimerDacCfg->DualChannelDacStep;
+
+ /* Enable the DualChannel DAC trigger */
+ hrpwm_cr1 &= ~(HRPWM_CR1_DCDE);
+ hrpwm_cr1 |= pTimerDacCfg->DualChannelDacEnable;
+ }
+
+ /* Update the HRPWM registers */
+ Instance->PWM[TimerIdx].CR1 |= hrpwm_cr1;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure timing RollOver Mode (Timer 0 to Timer 5)
+ * @param TimerIdx Timer index
+ * @param pRollOverMode: a combination of the timer RollOver Mode configuration
+ * @arg HRPWM_Timer_RollOver_Mode relevant paramter
+ * @arg HRPWM_Timer_Output_RollOver_Mode relevant paramter
+ * @arg HRPWM_Timer_ADTrig_RollOver_Mode relevant paramter
+ * @arg HRPWM_Timer_Event_RollOver_Mode relevant paramter
+ * @arg HRPWM_Timer_Fault_RollOver_Mode relevant paramter
+ * @arg HRPWM_Timer_UpDown_Mode relevant paramter
+ * eg: HRPWM_FLTROM_ZERO | HRPWM_ADROM_BOTH
+ * Rollover can be configured in several modes or together, Only valid in updowm counting mode
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_TimerRollOverMode(HRPWM_TypeDef *Instance, uint32_t TimerIdx, uint32_t pRollOverMode)
+{
+ if (TimerIdx == HRPWM_INDEX_MASTER) {
+ return LL_ERROR;
+ }
+
+ uint32_t hrpwm_cr1;
+
+ /* Configure timing unit (Timer 0 to Timer 5) */
+ hrpwm_cr1 = Instance->PWM[TimerIdx].CR1;
+
+ /*The following modes are only valid in updown counting mode, so first determine if they are in updown counting mode*/
+ if (((hrpwm_cr1 & HRPWM_CR1_UDM) != 0U) || ((pRollOverMode & HRPWM_CR1_UDM) != 0U)) {
+ /* xxROM bitfield must be reset before programming a new value */
+ hrpwm_cr1 &= ~(HRPWM_CR1_ROM | HRPWM_CR1_OUTROM | HRPWM_CR1_ADROM | HRPWM_CR1_FLTROM | HRPWM_CR1_EEVROM);
+
+ /* Update the HRPWM TIMER CR1 register , start updown counter mode*/
+ hrpwm_cr1 |= (pRollOverMode & (HRPWM_CR1_ROM | HRPWM_CR1_OUTROM | HRPWM_CR1_ADROM | HRPWM_CR1_FLTROM | HRPWM_CR1_EEVROM)) |
+ HRPWM_CR1_UDM;
+
+ Instance->PWM[TimerIdx].CR1 |= hrpwm_cr1;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HRPWM_LL_Exported_Functions_Group5 HRPWM Configuration functions
+ * @brief HRPWM Configuration functions
+@verbatim
+ ===============================================================================
+ ##### HRPWM configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the HRPWM
+ resources shared by all the HRPWM timers operating in waveform mode:
+ (+) Configure a fault inputs conditioning
+ (+) Configure the faults blanking
+ (+) Configure the faults counter
+ (+) Configure the faults counter Reset
+ (+) Configure an ADC trigger
+ (+) Configure an output level & polarity
+ (+) Configure dead-time value
+ (+) Configure chopper output & freq\duty
+ (+) Configure an external event conditioning
+ (+) Configure the external events A conditioning
+ (+) Configure the external events A filter windows and latch
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the conditioning of fault input
+ * @param Fault fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FAULT_0: Fault input 0
+ * @arg HRPWM_FAULT_1: Fault input 1
+ * @arg HRPWM_FAULT_2: Fault input 2
+ * @arg HRPWM_FAULT_3: Fault input 3
+ * @arg HRPWM_FAULT_4: Fault input 4
+ * @arg HRPWM_FAULT_5: Fault input 5
+ * @param pFaultCfg pointer to the fault conditioning configuration structure
+ * @param pFaultBlkCfg pointer to the fault blanking conditioning configuration structure
+ * @note This function must be called before starting the timer and before
+ * enabling faults inputs
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_FaultConfig(HRPWM_TypeDef *Instance, uint32_t Fault,
+ HRPWM_FaultCfgTypeDef *pFaultCfg,
+ HRPWM_FaultBlankingCfgTypeDef *pFaultBlkCfg)
+{
+ uint32_t hrpwm_fltinr0;
+ uint32_t hrpwm_fltinr1;
+ uint32_t hrpwm_fltinr2;
+ uint32_t hrpwm_fltinr3;
+
+ /* Check parameters */
+ assert_param(IS_HRPWM_FAULT(Fault));
+ assert_param(IS_HRPWM_FAULT_IT(pFaultCfg->InterruptEn));
+ assert_param(IS_HRPWM_FAULTSOURCE(pFaultCfg->Source));
+ assert_param(IS_HRPWM_FAULTPOLARITY(pFaultCfg->Polarity));
+ assert_param(IS_HRPWM_FAULTFILTER(pFaultCfg->Filter));
+ assert_param(IS_HRPWM_FAULTSAMPCLK(pFaultCfg->SampClockDiv));
+ assert_param(IS_HRPWM_FAULTBLKEN(pFaultBlkCfg->BlankingEnable));
+ assert_param(IS_HRPWM_FAULTBLKSRC(pFaultBlkCfg->BlankingSource));
+ assert_param(IS_HRPWM_FAULTRSTMODE(pFaultBlkCfg->ResetMode));
+
+
+ /* Configure fault channel */
+ hrpwm_fltinr0 = Instance->Common.FLTINR0;
+ hrpwm_fltinr1 = Instance->Common.FLTINR1;
+ hrpwm_fltinr2 = Instance->Common.FLTINR2;
+ hrpwm_fltinr3 = Instance->Common.FLTINR3;
+
+ switch (Fault) {
+ case HRPWM_FAULT_0: {
+ /*clear relevant register bit */
+ hrpwm_fltinr0 &= ~(HRPWM_FLTINR0_FLT0SRC | HRPWM_FLTINR0_FLT0P | HRPWM_FLTINR0_FLT0E);
+ /*Configure fault enable */
+ hrpwm_fltinr0 |= (pFaultCfg->Enable & HRPWM_FLTINR0_FLT0E);
+ /*Configure fault polarity */
+ hrpwm_fltinr0 |= (pFaultCfg->Polarity & HRPWM_FLTINR0_FLT0P);
+ /*Configure fault source */
+ hrpwm_fltinr0 |= (pFaultCfg->Source & HRPWM_FLTINR0_FLT0SRC);
+ /*Configure fault filter counter */
+ hrpwm_fltinr1 &= ~(HRPWM_FLTINR1_FLT0F);
+ hrpwm_fltinr1 |= (pFaultCfg->Filter & HRPWM_FLTINR1_FLT0F);
+ /*Configure fault blanking function */
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT0BLKE | HRPWM_FLTINR2_FLT0BLKS | HRPWM_FLTINR2_FLT0RSTM);
+ hrpwm_fltinr2 |= (pFaultBlkCfg->BlankingEnable & HRPWM_FLTINR2_FLT0BLKE) |
+ (pFaultBlkCfg->BlankingSource & HRPWM_FLTINR2_FLT0BLKS) |
+ (pFaultBlkCfg->ResetMode & HRPWM_FLTINR2_FLT0RSTM);
+ /*Configure fault count the number of edges */
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT0CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT0CNT);
+
+ /*enable interrupt*/
+ SET_BIT(Instance->Common.IER, (pFaultCfg->InterruptEn & HRPWM_IT_FLT0));
+ }
+ break;
+
+ case HRPWM_FAULT_1: {
+ /*clear relevant register bit */
+ hrpwm_fltinr0 &= ~(HRPWM_FLTINR0_FLT1SRC | HRPWM_FLTINR0_FLT1P | HRPWM_FLTINR0_FLT1E);
+ /*Configure fault enable */
+ hrpwm_fltinr0 |= ((pFaultCfg->Enable << 4U) & HRPWM_FLTINR0_FLT1E);
+ /*Configure fault polarity */
+ hrpwm_fltinr0 |= ((pFaultCfg->Polarity << 4U) & HRPWM_FLTINR0_FLT1P);
+ /*Configure fault source */
+ hrpwm_fltinr0 |= ((pFaultCfg->Source << 4U) & HRPWM_FLTINR0_FLT1SRC);
+ /*Configure fault filter counter */
+ hrpwm_fltinr1 &= ~(HRPWM_FLTINR1_FLT1F);
+ hrpwm_fltinr1 |= ((pFaultCfg->Filter << 4U) & HRPWM_FLTINR1_FLT1F);
+ /*Configure fault blanking function */
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT1BLKE | HRPWM_FLTINR2_FLT1BLKS | HRPWM_FLTINR2_FLT1RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 4U) & HRPWM_FLTINR2_FLT1BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 4U) & HRPWM_FLTINR2_FLT1BLKS) |
+ ((pFaultBlkCfg->ResetMode << 4U) & HRPWM_FLTINR2_FLT1RSTM);
+ /*Configure fault count the number of edges */
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT1CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT1CNT);
+
+ /*enable interrupt*/
+ SET_BIT(Instance->Common.IER, (pFaultCfg->InterruptEn & HRPWM_IT_FLT1));
+ }
+ break;
+
+ case HRPWM_FAULT_2: {
+ /*clear relevant register bit */
+ hrpwm_fltinr0 &= ~(HRPWM_FLTINR0_FLT2SRC | HRPWM_FLTINR0_FLT2P | HRPWM_FLTINR0_FLT2E);
+ /*Configure fault enable */
+ hrpwm_fltinr0 |= ((pFaultCfg->Enable << 8U) & HRPWM_FLTINR0_FLT2E);
+ /*Configure fault polarity */
+ hrpwm_fltinr0 |= ((pFaultCfg->Polarity << 8U) & HRPWM_FLTINR0_FLT2P);
+ /*Configure fault source */
+ hrpwm_fltinr0 |= ((pFaultCfg->Source << 8U) & HRPWM_FLTINR0_FLT2SRC);
+ /*Configure fault filter counter */
+ hrpwm_fltinr1 &= ~(HRPWM_FLTINR1_FLT2F);
+ hrpwm_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRPWM_FLTINR1_FLT2F);
+ /*Configure fault blanking function */
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT2BLKE | HRPWM_FLTINR2_FLT2BLKS | HRPWM_FLTINR2_FLT2RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 8U) & HRPWM_FLTINR2_FLT2BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 8U) & HRPWM_FLTINR2_FLT2BLKS) |
+ ((pFaultBlkCfg->ResetMode << 8U) & HRPWM_FLTINR2_FLT2RSTM);
+ /*Configure fault count the number of edges */
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT2CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT2CNT);
+
+ /*enable interrupt*/
+ SET_BIT(Instance->Common.IER, (pFaultCfg->InterruptEn & HRPWM_IT_FLT2));
+ }
+ break;
+
+ case HRPWM_FAULT_3: {
+ /*clear relevant register bit */
+ hrpwm_fltinr0 &= ~(HRPWM_FLTINR0_FLT3SRC | HRPWM_FLTINR0_FLT3P | HRPWM_FLTINR0_FLT3E);
+ /*Configure fault enable */
+ hrpwm_fltinr0 |= ((pFaultCfg->Enable << 12U) & HRPWM_FLTINR0_FLT3E);
+ /*Configure fault polarity */
+ hrpwm_fltinr0 |= ((pFaultCfg->Polarity << 12U) & HRPWM_FLTINR0_FLT3P);
+ /*Configure fault source */
+ hrpwm_fltinr0 |= ((pFaultCfg->Source << 12U) & HRPWM_FLTINR0_FLT3SRC);
+ /*Configure fault filter counter */
+ hrpwm_fltinr1 &= ~(HRPWM_FLTINR1_FLT3F);
+ hrpwm_fltinr1 |= ((pFaultCfg->Filter << 12U) & HRPWM_FLTINR1_FLT3F);
+ /*Configure fault blanking function */
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT3BLKE | HRPWM_FLTINR2_FLT3BLKS | HRPWM_FLTINR2_FLT3RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 12U) & HRPWM_FLTINR2_FLT3BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 12U) & HRPWM_FLTINR2_FLT3BLKS) |
+ ((pFaultBlkCfg->ResetMode << 12U) & HRPWM_FLTINR2_FLT3RSTM);
+ /*Configure fault count the number of edges */
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT3CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT3CNT);
+
+ /*enable interrupt*/
+ SET_BIT(Instance->Common.IER, (pFaultCfg->InterruptEn & HRPWM_IT_FLT3));
+ }
+ break;
+
+ case HRPWM_FAULT_4: {
+ /*clear relevant register bit */
+ hrpwm_fltinr0 &= ~(HRPWM_FLTINR0_FLT4SRC | HRPWM_FLTINR0_FLT4P | HRPWM_FLTINR0_FLT4E);
+ /*Configure fault enable */
+ hrpwm_fltinr0 |= ((pFaultCfg->Enable << 16U) & HRPWM_FLTINR0_FLT4E);
+ /*Configure fault polarity */
+ hrpwm_fltinr0 |= ((pFaultCfg->Polarity << 16U) & HRPWM_FLTINR0_FLT4P);
+ /*Configure fault source */
+ hrpwm_fltinr0 |= ((pFaultCfg->Source << 16U) & HRPWM_FLTINR0_FLT4SRC);
+ /*Configure fault filter counter */
+ hrpwm_fltinr1 &= ~(HRPWM_FLTINR1_FLT4F);
+ hrpwm_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRPWM_FLTINR1_FLT4F);
+ /*Configure fault blanking function */
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT4BLKE | HRPWM_FLTINR2_FLT4BLKS | HRPWM_FLTINR2_FLT4RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 16U) & HRPWM_FLTINR2_FLT4BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 16U) & HRPWM_FLTINR2_FLT4BLKS) |
+ ((pFaultBlkCfg->ResetMode << 16U) & HRPWM_FLTINR2_FLT4RSTM);
+ /*Configure fault count the number of edges */
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT4CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT4CNT);
+
+ /*enable interrupt*/
+ SET_BIT(Instance->Common.IER, (pFaultCfg->InterruptEn & HRPWM_IT_FLT4));
+ }
+ break;
+
+ case HRPWM_FAULT_5: {
+ /*clear relevant register bit */
+ hrpwm_fltinr0 &= ~(HRPWM_FLTINR0_FLT5SRC | HRPWM_FLTINR0_FLT5P | HRPWM_FLTINR0_FLT5E);
+ /*Configure fault enable */
+ hrpwm_fltinr0 |= ((pFaultCfg->Enable << 20U) & HRPWM_FLTINR0_FLT5E);
+ /*Configure fault polarity */
+ hrpwm_fltinr0 |= ((pFaultCfg->Polarity << 20U) & HRPWM_FLTINR0_FLT5P);
+ /*Configure fault source */
+ hrpwm_fltinr0 |= ((pFaultCfg->Source << 20U) & HRPWM_FLTINR0_FLT5SRC);
+ /*Configure fault filter counter */
+ hrpwm_fltinr1 &= ~(HRPWM_FLTINR1_FLT5F);
+ hrpwm_fltinr1 |= ((pFaultCfg->Filter << 20U) & HRPWM_FLTINR1_FLT5F);
+ /*Configure fault blanking function */
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT5BLKE | HRPWM_FLTINR2_FLT5BLKS | HRPWM_FLTINR2_FLT5RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 20U) & HRPWM_FLTINR2_FLT5BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 20U) & HRPWM_FLTINR2_FLT5BLKS) |
+ ((pFaultBlkCfg->ResetMode << 20U) & HRPWM_FLTINR2_FLT5RSTM);
+ /*Configure fault count the number of edges */
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT5CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT5CNT);
+
+ /*enable interrupt*/
+ SET_BIT(Instance->Common.IER, (pFaultCfg->InterruptEn & HRPWM_IT_FLT5));
+ }
+ break;
+
+ case HRPWM_SYSFAULT: {
+ /*enable interrupt*/
+ SET_BIT(Instance->Common.IER, (pFaultCfg->InterruptEn & HRPWM_IT_SYSFLT));
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ Instance->Common.FLTINR0 = hrpwm_fltinr0;
+ /* Configure the fault conditioning block prescaler */
+ Instance->Common.FLTINR1 &= (~(HRPWM_FLTINR1_FLTSD));
+ Instance->Common.FLTINR1 |= hrpwm_fltinr1 | (pFaultCfg->SampClockDiv & HRPWM_FLTINR1_FLTSD);
+
+ Instance->Common.FLTINR2 = hrpwm_fltinr2;
+ Instance->Common.FLTINR3 = hrpwm_fltinr3;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the conditioning of fault blanking
+ * @param Fault fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FAULT_0: Fault input 0
+ * @arg HRPWM_FAULT_1: Fault input 1
+ * @arg HRPWM_FAULT_2: Fault input 2
+ * @arg HRPWM_FAULT_3: Fault input 3
+ * @arg HRPWM_FAULT_4: Fault input 4
+ * @arg HRPWM_FAULT_5: Fault input 5
+ * @param pFaultBlkCfg pointer to the fault blanking conditioning configuration structure
+ * @note This function must be called before starting the timer and before
+ * enabling faults inputs, Configure blanking only without enabling;
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_FaultBlankingConfig(HRPWM_TypeDef *Instance, uint32_t Fault,
+ HRPWM_FaultBlankingCfgTypeDef *pFaultBlkCfg)
+{
+ uint32_t hrpwm_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRPWM_FAULT(Fault));
+ assert_param(IS_HRPWM_FAULTBLKEN(pFaultBlkCfg->BlankingEnable));
+ assert_param(IS_HRPWM_FAULTBLKSRC(pFaultBlkCfg->BlankingSource));
+ assert_param(IS_HRPWM_FAULTRSTMODE(pFaultBlkCfg->ResetMode));
+
+ /* Configure fault blanking channel */
+ hrpwm_fltinr2 = Instance->Common.FLTINR2;
+
+ switch (Fault) {
+ case HRPWM_FAULT_0: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT0BLKE | HRPWM_FLTINR2_FLT0BLKS | HRPWM_FLTINR2_FLT0RSTM);
+ hrpwm_fltinr2 |= (pFaultBlkCfg->BlankingEnable & HRPWM_FLTINR2_FLT0BLKE) |
+ (pFaultBlkCfg->BlankingSource & HRPWM_FLTINR2_FLT0BLKS) |
+ (pFaultBlkCfg->ResetMode & HRPWM_FLTINR2_FLT0RSTM);
+ }
+ break;
+
+ case HRPWM_FAULT_1: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT1BLKE | HRPWM_FLTINR2_FLT1BLKS | HRPWM_FLTINR2_FLT1RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 4U) & HRPWM_FLTINR2_FLT1BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 4U) & HRPWM_FLTINR2_FLT1BLKS) |
+ ((pFaultBlkCfg->ResetMode << 4U) & HRPWM_FLTINR2_FLT1RSTM);
+ }
+ break;
+
+ case HRPWM_FAULT_2: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT2BLKE | HRPWM_FLTINR2_FLT2BLKS | HRPWM_FLTINR2_FLT2RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 8U) & HRPWM_FLTINR2_FLT2BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 8U) & HRPWM_FLTINR2_FLT2BLKS) |
+ ((pFaultBlkCfg->ResetMode << 8U) & HRPWM_FLTINR2_FLT2RSTM);
+
+ }
+ break;
+
+ case HRPWM_FAULT_3: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT3BLKE | HRPWM_FLTINR2_FLT3BLKS | HRPWM_FLTINR2_FLT3RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 12U) & HRPWM_FLTINR2_FLT3BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 12U) & HRPWM_FLTINR2_FLT3BLKS) |
+ ((pFaultBlkCfg->ResetMode << 12U) & HRPWM_FLTINR2_FLT3RSTM);
+ }
+ break;
+
+ case HRPWM_FAULT_4: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT4BLKE | HRPWM_FLTINR2_FLT4BLKS | HRPWM_FLTINR2_FLT4RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 16U) & HRPWM_FLTINR2_FLT4BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 16U) & HRPWM_FLTINR2_FLT4BLKS) |
+ ((pFaultBlkCfg->ResetMode << 16U) & HRPWM_FLTINR2_FLT4RSTM);
+
+ }
+ break;
+
+ case HRPWM_FAULT_5: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT5BLKE | HRPWM_FLTINR2_FLT5BLKS | HRPWM_FLTINR2_FLT5RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->BlankingEnable << 20U) & HRPWM_FLTINR2_FLT5BLKE) |
+ ((pFaultBlkCfg->BlankingSource << 20U) & HRPWM_FLTINR2_FLT5BLKS) |
+ ((pFaultBlkCfg->ResetMode << 20U) & HRPWM_FLTINR2_FLT5RSTM);
+
+ }
+ break;
+
+ default:
+ break;
+ }
+
+
+ Instance->Common.FLTINR2 = hrpwm_fltinr2;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the Fault Counter (Threshold and Reset Mode)
+ * @param Fault fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FAULT_0: Fault input 0
+ * @arg HRPWM_FAULT_1: Fault input 1
+ * @arg HRPWM_FAULT_2: Fault input 2
+ * @arg HRPWM_FAULT_3: Fault input 3
+ * @arg HRPWM_FAULT_4: Fault input 4
+ * @arg HRPWM_FAULT_5: Fault input 5
+ * @param pFaultBlkCfg: pointer to the fault conditioning configuration structure
+ * @retval LL status
+ * @note A fault is considered valid when the number of
+ * events is equal to the (FLTxCNT[3:0]+1) value
+ *
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_FaultCounterConfig(HRPWM_TypeDef *Instance, uint32_t Fault,
+ HRPWM_FaultBlankingCfgTypeDef *pFaultBlkCfg)
+{
+ uint32_t hrpwm_fltinr2;
+ uint32_t hrpwm_fltinr3;
+
+ /* Check parameters */
+ assert_param(IS_HRPWM_FAULT(Fault));
+ assert_param(IS_HRPWM_FAULTRSTMODE(pFaultBlkCfg->ResetMode));
+
+
+ /* Configure fault channel */
+ hrpwm_fltinr2 = Instance->Common.FLTINR2;
+ hrpwm_fltinr3 = Instance->Common.FLTINR3;
+
+ switch (Fault) {
+ case HRPWM_FAULT_0: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT0RSTM);
+ hrpwm_fltinr2 |= (pFaultBlkCfg->ResetMode & HRPWM_FLTINR2_FLT0RSTM);
+ /*The number of effective edges. How many edges are collected is considered as a fault*/
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT0CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT0CNT);
+ }
+ break;
+
+ case HRPWM_FAULT_1: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT1RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->ResetMode << 4U) & HRPWM_FLTINR2_FLT1RSTM);
+ /*The number of effective edges. How many edges are collected is considered as a fault*/
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT1CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT1CNT);
+ }
+ break;
+
+ case HRPWM_FAULT_2: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT2RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->ResetMode << 8U) & HRPWM_FLTINR2_FLT2RSTM);
+ /*The number of effective edges. How many edges are collected is considered as a fault*/
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT2CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT2CNT);
+ }
+ break;
+
+ case HRPWM_FAULT_3: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT3RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->ResetMode << 12U) & HRPWM_FLTINR2_FLT3RSTM);
+ /*The number of effective edges. How many edges are collected is considered as a fault*/
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT3CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT3CNT);
+ }
+ break;
+
+ case HRPWM_FAULT_4: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT4RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->ResetMode << 16U) & HRPWM_FLTINR2_FLT4RSTM);
+ /*The number of effective edges. How many edges are collected is considered as a fault*/
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT4CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT4CNT);
+ }
+ break;
+
+ case HRPWM_FAULT_5: {
+ hrpwm_fltinr2 &= ~(HRPWM_FLTINR2_FLT5RSTM);
+ hrpwm_fltinr2 |= ((pFaultBlkCfg->ResetMode << 20U) & HRPWM_FLTINR2_FLT5RSTM);
+ /*The number of effective edges. How many edges are collected is considered as a fault*/
+ hrpwm_fltinr3 &= ~(HRPWM_FLTINR3_FLT5CNT);
+ hrpwm_fltinr3 |= (pFaultBlkCfg->Threshold & HRPWM_FLTINR3_FLT5CNT);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ Instance->Common.FLTINR2 = hrpwm_fltinr2;
+ Instance->Common.FLTINR3 = hrpwm_fltinr3;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Reset the fault Counter Reset
+ * @param Fault fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRPWM_FAULT_0: Fault input 0
+ * @arg HRPWM_FAULT_1: Fault input 1
+ * @arg HRPWM_FAULT_2: Fault input 2
+ * @arg HRPWM_FAULT_3: Fault input 3
+ * @arg HRPWM_FAULT_4: Fault input 4
+ * @arg HRPWM_FAULT_5: Fault input 5
+ * @retval LL status
+ */
+LL_StatusETypeDef LL_HRPWM_FaultCounterReset(uint32_t Fault)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_FAULT(Fault));
+
+ /* Configure fault channel */
+ switch (Fault) {
+ case HRPWM_FAULT_0: {
+ MODIFY_REG(HRPWM->Common.FLTINR2, HRPWM_FLTINR2_FLT0CRES, HRPWM_FLTINR2_FLT0CRES);
+ }
+ break;
+
+ case HRPWM_FAULT_1: {
+ MODIFY_REG(HRPWM->Common.FLTINR2, HRPWM_FLTINR2_FLT1CRES, HRPWM_FLTINR2_FLT1CRES);
+ }
+ break;
+
+ case HRPWM_FAULT_2: {
+ MODIFY_REG(HRPWM->Common.FLTINR2, HRPWM_FLTINR2_FLT2CRES, HRPWM_FLTINR2_FLT2CRES);
+ }
+ break;
+
+ case HRPWM_FAULT_3: {
+ MODIFY_REG(HRPWM->Common.FLTINR2, HRPWM_FLTINR2_FLT3CRES, HRPWM_FLTINR2_FLT3CRES);
+ }
+ break;
+
+ case HRPWM_FAULT_4: {
+ MODIFY_REG(HRPWM->Common.FLTINR2, HRPWM_FLTINR2_FLT4CRES, HRPWM_FLTINR2_FLT4CRES);
+ }
+ break;
+
+ case HRPWM_FAULT_5: {
+ MODIFY_REG(HRPWM->Common.FLTINR2, HRPWM_FLTINR2_FLT5CRES, HRPWM_FLTINR2_FLT5CRES);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure both the ADC trigger register update source and the ADC
+ * trigger source.
+ * @param ADCTrigger group ADC trigger to configure
+ * This parameter can be one of the following values:
+ * @arg HRPWM_ADCTRIGGER_0: ADC trigger 0
+ * @arg HRPWM_ADCTRIGGER_1: ADC trigger 1
+ * @arg HRPWM_ADCTRIGGER_2: ADC trigger 2
+ * @arg HRPWM_ADCTRIGGER_3: ADC trigger 3
+ * @arg HRPWM_ADCTRIGGER_4: ADC trigger 4
+ * @arg HRPWM_ADCTRIGGER_5: ADC trigger 5
+ * @arg HRPWM_ADCTRIGGER_6: ADC trigger 6
+ * @arg HRPWM_ADCTRIGGER_7: ADC trigger 7
+ * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
+ * for Trigger nb (0/2/4/6): pADCTriggerCfg->Trigger parameter
+ * can be a combination of the following values
+ * @arg HRPWM_ADCTRIGGEREVENT02_...
+ * @arg HRPWM_ADCTRIGGEREVENT46_...
+ * for Trigger nb (1/3/5/7): pADCTriggerCfg->Trigger parameter
+ * can be one of the following values
+ * @arg HRPWM_ADCTRIGGEREVENT13_...
+ * @arg HRPWM_ADCTRIGGEREVENT57...
+ * @retval LL status
+ * @note This function must be called before starting the timer
+ */
+LL_StatusETypeDef LL_HRPWM_ADDATriggerConfig(HRPWM_TypeDef *Instance, HRPWM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
+{
+ uint32_t hrpwm_cr0;
+ uint32_t hrpwm_cr2;
+ uint32_t hrpwm_adpsr;
+
+ /* Check parameters */
+ assert_param(IS_HRPWM_ADCTRIGGER(pADCTriggerCfg->TriggerGroup));
+ assert_param(IS_HRPWM_ADCTRIGGER_UPDATESRC(pADCTriggerCfg->UpdateSource));
+ assert_param(IS_HRPWM_ADCTRIGGER_LENGTH(pADCTriggerCfg->TriggerLength));
+ assert_param(IS_HRPWM_ADCTRIGGER_POSTSCALER(pADCTriggerCfg->TriggerPostScaler));
+
+ /* Set the ADC trigger update source */
+ hrpwm_cr0 = Instance->Common.CR0;
+ hrpwm_cr2 = Instance->Common.CR2;
+ hrpwm_adpsr = Instance->Common.ADPSR;
+
+ switch (pADCTriggerCfg->TriggerGroup) {
+ case HRPWM_ADCTRIGGER_0: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC0);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 8U) & HRPWM_CR0_ADUSRC0);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN0);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 0U) & HRPWM_CR2_TLEN0);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC0);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 0U) & HRPWM_ADPSR_ADPSC0);
+ /* Set the ADC trigger 0 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;
+ }
+
+ case HRPWM_ADCTRIGGER_1: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC1);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 11U) & HRPWM_CR0_ADUSRC1);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN1);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 4U) & HRPWM_CR2_TLEN1);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC1);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 4U) & HRPWM_ADPSR_ADPSC1);
+ /* Set the ADC trigger 1 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;
+ }
+
+ case HRPWM_ADCTRIGGER_2: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC2);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 14U) & HRPWM_CR0_ADUSRC2);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN2);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 8U) & HRPWM_CR2_TLEN2);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC2);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 8U) & HRPWM_ADPSR_ADPSC2);
+ /* Set the ADC trigger 2 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;
+ }
+
+ case HRPWM_ADCTRIGGER_3: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC3);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 17U) & HRPWM_CR0_ADUSRC3);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN3);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 12U) & HRPWM_CR2_TLEN3);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC3);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 12U) & HRPWM_ADPSR_ADPSC3);
+ /* Set the ADC trigger 3 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;
+ }
+
+ case HRPWM_ADCTRIGGER_4: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC4);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 20U) & HRPWM_CR0_ADUSRC4);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN4);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 16U) & HRPWM_CR2_TLEN4);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC4);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 16U) & HRPWM_ADPSR_ADPSC4);
+ /* Set the ADC trigger 4 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;
+ }
+
+ case HRPWM_ADCTRIGGER_5: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC5);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 23U) & HRPWM_CR0_ADUSRC5);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN5);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 20U) & HRPWM_CR2_TLEN5);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC5);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 20U) & HRPWM_ADPSR_ADPSC5);
+ /* Set the ADC trigger 5 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;
+ }
+
+ case HRPWM_ADCTRIGGER_6: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC6);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 26U) & HRPWM_CR0_ADUSRC6);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN6);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 24U) & HRPWM_CR2_TLEN6);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC6);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 24U) & HRPWM_ADPSR_ADPSC6);
+ /* Set the ADC trigger 6 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;
+ }
+
+ case HRPWM_ADCTRIGGER_7: {
+ hrpwm_cr0 &= ~(HRPWM_CR0_ADUSRC7);
+ hrpwm_cr0 |= ((pADCTriggerCfg->UpdateSource << 29U) & HRPWM_CR0_ADUSRC7);
+ /*Set trigger pulse length*/
+ hrpwm_cr2 &= ~(HRPWM_CR2_TLEN7);
+ hrpwm_cr2 |= ((pADCTriggerCfg->TriggerLength << 28U) & HRPWM_CR2_TLEN7);
+ /* Set the ADC trigger postcaler */
+ hrpwm_adpsr &= ~(HRPWM_ADPSR_ADPSC7);
+ hrpwm_adpsr |= ((pADCTriggerCfg->TriggerPostScaler << 28U) & HRPWM_ADPSR_ADPSC7);
+ /* Set the ADC trigger 7 source */
+ Instance->Common.ADTR[pADCTriggerCfg->TriggerGroup] = pADCTriggerCfg->Trigger;
+ break;;
+ }
+
+ default:
+ break;
+ }
+
+ /* Update the HRPWM registers */
+ Instance->Common.CR0 = hrpwm_cr0;
+ Instance->Common.CR2 = hrpwm_cr2;
+ Instance->Common.ADPSR = hrpwm_adpsr;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the output of a timing unit
+ * @param TimerIdx Timer index
+ * @param Output timing unit output identifier
+ * @param pOutputCfg pointer to the output configuration data structure
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_OutputConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_OutputCfgTypeDef *pOutputCfg)
+{
+ if (TimerIdx == HRPWM_INDEX_MASTER) {
+ return LL_ERROR;
+ }
+
+ uint32_t hrpwm_outr;
+
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_OUTPUTA_POLARITY(pOutputCfg->OutputAPolarity));
+ assert_param(IS_HRPWM_OUTPUTA_IDLELEVEL(pOutputCfg->IdleALevel));
+ assert_param(IS_HRPWM_OUTPUTA_FLTLEVEL(pOutputCfg->FaultALevel));
+ assert_param(IS_HRPWM_OUTPUTA_CHOPPEREN(pOutputCfg->ChopperAModeEnable));
+ assert_param(IS_HRPWM_OUTPUTB_POLARITY(pOutputCfg->OutputBPolarity));
+ assert_param(IS_HRPWM_OUTPUTB_IDLELEVEL(pOutputCfg->IdleBLevel));
+ assert_param(IS_HRPWM_OUTPUTB_FLTLEVEL(pOutputCfg->FaultBLevel));
+ assert_param(IS_HRPWM_OUTPUTB_CHOPPEREN(pOutputCfg->ChopperBModeEnable));
+
+ assert_param(IS_HRPWM_OUTPUT_CLEAR_EVENT(pOutputCfg->OutputAClearSource));
+ assert_param(IS_HRPWM_OUTPUT_CLEAR_EVENT(pOutputCfg->OutputBClearSource));
+ assert_param(IS_HRPWM_OUTPUT_SET_EVENT(pOutputCfg->OutputASetSource));
+ assert_param(IS_HRPWM_OUTPUT_SET_EVENT(pOutputCfg->OutputBSetSource));
+
+ hrpwm_outr = Instance->PWM[TimerIdx].OUTR;
+
+ /* Set the output set/reset crossbar */
+ Instance->PWM[TimerIdx].SETAR = pOutputCfg->OutputASetSource;
+ Instance->PWM[TimerIdx].CLRAR = pOutputCfg->OutputAClearSource;
+
+ /* Set the output set/reset crossbar */
+ Instance->PWM[TimerIdx].SETBR = pOutputCfg->OutputBSetSource;
+ Instance->PWM[TimerIdx].CLRBR = pOutputCfg->OutputBClearSource;
+
+ /* Clear output config */
+ hrpwm_outr &= ~(HRPWM_OUTR_POLA |
+ HRPWM_OUTR_IDLESA |
+ HRPWM_OUTR_FAULTA |
+ HRPWM_OUTR_CHPA |
+ HRPWM_OUTR_POLB |
+ HRPWM_OUTR_IDLESB |
+ HRPWM_OUTR_FAULTB |
+ HRPWM_OUTR_CHPB);
+
+ /* Set the polarity */
+ hrpwm_outr |= (pOutputCfg->OutputAPolarity) | (pOutputCfg->OutputBPolarity);
+
+ /* Set the IDLE state */
+ hrpwm_outr |= (pOutputCfg->IdleALevel) | (pOutputCfg->IdleBLevel);
+
+ /* Set the FAULT state */
+ hrpwm_outr |= (pOutputCfg->FaultALevel) | (pOutputCfg->FaultBLevel);
+
+ /* Set the chopper mode */
+ hrpwm_outr |= (pOutputCfg->ChopperAModeEnable) | (pOutputCfg->ChopperBModeEnable);
+
+ /* Update HRPWM register */
+ Instance->PWM[TimerIdx].OUTR |= hrpwm_outr;
+
+ return LL_OK;
+
+}
+
+/**
+ * @brief Configure the dead-time output of a timing unit
+ * @param TimerIdx Timer index
+ * @param Output timing unit output identifier
+ * @param pOutputCfg pointer to the output configuration data structure
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_DeadTimeConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_DeadTimeCfgTypeDef *pDeaTimedCfg)
+{
+ uint32_t hrpwm_outr;
+ uint32_t hrpwm_dtr;
+
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_DEADTIME_SDTF(pDeaTimedCfg->FallingSign));
+ assert_param(IS_HRPWM_DEADTIME_SDTR(pDeaTimedCfg->RisingSign));
+
+ hrpwm_outr = Instance->PWM[TimerIdx].OUTR;
+ hrpwm_dtr = Instance->PWM[TimerIdx].DTR;
+
+ /* Clear deadtime register config */
+ hrpwm_outr &= (~HRPWM_OUTR_DTEN);
+ hrpwm_dtr &= ~(HRPWM_DTR_SDTF | HRPWM_DTR_DTF | HRPWM_DTR_SDTR | HRPWM_DTR_DTR);
+
+ /* Set the fall dead time sign and value */
+ hrpwm_dtr |= (pDeaTimedCfg->FallingSign) | ((pDeaTimedCfg->FallingValue << 16U) & HRPWM_DTR_DTF);
+
+ /* Set Set the rise dead time sign and value */
+ hrpwm_dtr |= (pDeaTimedCfg->RisingSign) | (pDeaTimedCfg->RisingValue & HRPWM_DTR_DTR);
+
+ /* Eanble dead-time output */
+ hrpwm_outr |= (pDeaTimedCfg->DeadTimeEn << 31U);
+
+ /* Update HRPWM register */
+ Instance->PWM[TimerIdx].OUTR |= hrpwm_outr;
+ Instance->PWM[TimerIdx].DTR = hrpwm_dtr;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the Chopper output of a timing unit
+ * @param TimerIdx Timer index
+ * @param Output timing unit output identifier
+ * @param pOutputCfg pointer to the output configuration data structure
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_ChopperConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_ChopperModeCfgTypeDef *pChopperCfg)
+{
+ uint32_t hrpwm_outr;
+ uint32_t hrpwm_chpr;
+
+ /* Check the parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_OUTPUTA_CHOPPEREN(pChopperCfg->ChopperAModeEnable));
+ assert_param(IS_HRPWM_OUTPUTB_CHOPPEREN(pChopperCfg->ChopperBModeEnable));
+ assert_param(IS_HRPWM_CHOPPER_CARDTY(pChopperCfg->DutyCycle));
+ assert_param(IS_HRPWM_CHOPPER_STRPW(pChopperCfg->StartPulse));
+ assert_param(IS_HRPWM_CHOPPER_CARFRQ(pChopperCfg->CarrierFreq));
+
+
+ hrpwm_outr = Instance->PWM[TimerIdx].OUTR;
+ hrpwm_chpr = Instance->PWM[TimerIdx].CHPR;
+
+ /* Clear chopper register config */
+ hrpwm_outr &= (~HRPWM_OUTR_CHPB | HRPWM_OUTR_CHPA);
+ hrpwm_chpr &= ~(HRPWM_CHPR_STRPW | HRPWM_CHPR_CARDTY | HRPWM_CHPR_CARFRQ);
+
+ /* Set the start pulse width */
+ hrpwm_chpr |= (pChopperCfg->StartPulse & HRPWM_CHPR_STRPW);
+
+ /* Set the carrier freq */
+ hrpwm_chpr |= (pChopperCfg->CarrierFreq & HRPWM_CHPR_CARFRQ);
+
+ /* Set the chopper duty */
+ hrpwm_chpr |= (pChopperCfg->DutyCycle & HRPWM_CHPR_CARDTY);
+
+ /* Eanble chopper A\B output */
+ hrpwm_outr |= ((pChopperCfg->ChopperAModeEnable & HRPWM_OUTR_CHPA) |
+ (pChopperCfg->ChopperBModeEnable & HRPWM_OUTR_CHPB));
+
+ /* Update HRPWM register */
+ Instance->PWM[TimerIdx].OUTR |= hrpwm_outr;
+ Instance->PWM[TimerIdx].CHPR = hrpwm_chpr;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure an external event channel
+ * @param Event Event channel identifier
+ * @param pEventCfg pointer to the event channel configuration data structure
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_EventConfig(HRPWM_TypeDef *Instance, uint32_t Event, HRPWM_EventCfgTypeDef *pEventCfg)
+{
+
+ /* Check parameters */
+ assert_param(IS_HRPWM_EVENT(Event));
+ assert_param(IS_HRPWM_EVENTSOURCE(pEventCfg->Source));
+ assert_param(IS_HRPWM_EVENTPOLARITY(pEventCfg->Polarity));
+ assert_param(IS_HRPWM_EVENTFILTER(pEventCfg->Filter));
+ assert_param(IS_HRPWM_EVENTSAMPCLK(pEventCfg->SampClockDiv));
+ assert_param(IS_HRPWM_EVENTFASTMODE(pEventCfg->FastMode));
+ assert_param(IS_HRPWM_EVENTSNS(pEventCfg->Sensitivity));
+
+
+ uint32_t hrpwm_eecr0;
+ uint32_t hrpwm_eecr1;
+ uint32_t hrpwm_eecr2;
+
+ /* Configure external event channel */
+ hrpwm_eecr0 = Instance->Common.EECR0;
+ hrpwm_eecr1 = Instance->Common.EECR1;
+ hrpwm_eecr2 = Instance->Common.EECR2;
+
+ hrpwm_eecr2 &= ~(HRPWM_EECR2_EEVSD);
+ hrpwm_eecr2 |= (pEventCfg->SampClockDiv & HRPWM_EECR2_EEVSD);
+
+
+ switch (Event) {
+ case HRPWM_EVENT_NONE: {
+ /* Update the HRPWM registers */
+ Instance->Common.EECR0 = 0U;
+ Instance->Common.EECR1 = 0U;
+ Instance->Common.EECR2 = 0U;
+ break;
+ }
+
+ case HRPWM_EVENT_0: {
+ hrpwm_eecr0 &= ~(HRPWM_EECR0_EE0SRC | HRPWM_EECR0_EE0POL | HRPWM_EECR0_EE0SNS | HRPWM_EECR0_EE0FAST);
+ hrpwm_eecr0 |= (pEventCfg->Source & HRPWM_EECR0_EE0SRC);
+ hrpwm_eecr0 |= (pEventCfg->Polarity & HRPWM_EECR0_EE0POL);
+ hrpwm_eecr0 |= (pEventCfg->Sensitivity & HRPWM_EECR0_EE0SNS);
+ /* Update the HRPWM registers (all bitfields but EE1FAST bit) */
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /* Update the HRPWM registers (EE1FAST bit) */
+ hrpwm_eecr0 |= (pEventCfg->FastMode & HRPWM_EECR0_EE0FAST);
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /*HRPWM EVENT0 filter*/
+ hrpwm_eecr2 &= ~(HRPWM_EECR2_EE0F);
+ hrpwm_eecr2 |= (pEventCfg->Filter & HRPWM_EECR2_EE0F);
+ Instance->Common.EECR2 = hrpwm_eecr2;
+ break;
+ }
+
+ case HRPWM_EVENT_1: {
+ hrpwm_eecr0 &= ~(HRPWM_EECR0_EE1SRC | HRPWM_EECR0_EE1POL | HRPWM_EECR0_EE1SNS | HRPWM_EECR0_EE1FAST);
+ hrpwm_eecr0 |= ((pEventCfg->Source << 6U) & HRPWM_EECR0_EE1SRC);
+ hrpwm_eecr0 |= ((pEventCfg->Polarity << 6U) & HRPWM_EECR0_EE1POL);
+ hrpwm_eecr0 |= ((pEventCfg->Sensitivity << 6U) & HRPWM_EECR0_EE1SNS);
+ /* Update the HRPWM registers (all bitfields but EE1FAST bit) */
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /* Update the HRPWM registers (EE1FAST bit) */
+ hrpwm_eecr0 |= ((pEventCfg->FastMode << 6U) & HRPWM_EECR0_EE1FAST);
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /*HRPWM EVENT1 filter*/
+ hrpwm_eecr2 &= ~(HRPWM_EECR2_EE1F);
+ hrpwm_eecr2 |= ((pEventCfg->Filter << HRPWM_EECR2_EE1F_Pos) & HRPWM_EECR2_EE1F);
+ Instance->Common.EECR2 = hrpwm_eecr2;
+ break;
+ }
+
+ case HRPWM_EVENT_2: {
+ hrpwm_eecr0 &= ~(HRPWM_EECR0_EE2SRC | HRPWM_EECR0_EE2POL | HRPWM_EECR0_EE2SNS | HRPWM_EECR0_EE2FAST);
+ hrpwm_eecr0 |= ((pEventCfg->Source << 12U) & HRPWM_EECR0_EE2SRC);
+ hrpwm_eecr0 |= ((pEventCfg->Polarity << 12U) & HRPWM_EECR0_EE2POL);
+ hrpwm_eecr0 |= ((pEventCfg->Sensitivity << 12U) & HRPWM_EECR0_EE2SNS);
+ /* Update the HRPWM registers (all bitfields but EE2FAST bit) */
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /* Update the HRPWM registers (EE2FAST bit) */
+ hrpwm_eecr0 |= ((pEventCfg->FastMode << 12U) & HRPWM_EECR0_EE2FAST);
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /*HRPWM EVENT2 filter*/
+ hrpwm_eecr2 &= ~(HRPWM_EECR2_EE2F);
+ hrpwm_eecr2 |= ((pEventCfg->Filter << HRPWM_EECR2_EE2F_Pos) & HRPWM_EECR2_EE2F);
+ Instance->Common.EECR2 = hrpwm_eecr2;
+ break;
+ }
+
+ case HRPWM_EVENT_3: {
+ hrpwm_eecr0 &= ~(HRPWM_EECR0_EE3SRC | HRPWM_EECR0_EE3POL | HRPWM_EECR0_EE3SNS | HRPWM_EECR0_EE3FAST);
+ hrpwm_eecr0 |= ((pEventCfg->Source << 18U) & HRPWM_EECR0_EE3SRC);
+ hrpwm_eecr0 |= ((pEventCfg->Polarity << 18U) & HRPWM_EECR0_EE3POL);
+ hrpwm_eecr0 |= ((pEventCfg->Sensitivity << 18U) & HRPWM_EECR0_EE3SNS);
+ /* Update the HRPWM registers (all bitfields but EE3FAST bit) */
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /* Update the HRPWM registers (EE3FAST bit) */
+ hrpwm_eecr0 |= ((pEventCfg->FastMode << 18U) & HRPWM_EECR0_EE3FAST);
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /*HRPWM EVENT3 filter*/
+ hrpwm_eecr2 &= ~(HRPWM_EECR2_EE3F);
+ hrpwm_eecr2 |= ((pEventCfg->Filter << HRPWM_EECR2_EE3F_Pos) & HRPWM_EECR2_EE3F);
+ Instance->Common.EECR2 = hrpwm_eecr2;
+ break;
+ }
+
+ case HRPWM_EVENT_4: {
+ hrpwm_eecr0 &= ~(HRPWM_EECR0_EE4SRC | HRPWM_EECR0_EE4POL | HRPWM_EECR0_EE4SNS | HRPWM_EECR0_EE4FAST);
+ hrpwm_eecr0 |= ((pEventCfg->Source << 24U) & HRPWM_EECR0_EE4SRC);
+ hrpwm_eecr0 |= ((pEventCfg->Polarity << 24U) & HRPWM_EECR0_EE4POL);
+ hrpwm_eecr0 |= ((pEventCfg->Sensitivity << 24U) & HRPWM_EECR0_EE4SNS);
+ /* Update the HRPWM registers (all bitfields but EE4FAST bit) */
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /* Update the HRPWM registers (EE4FAST bit) */
+ hrpwm_eecr0 |= ((pEventCfg->FastMode << 24U) & HRPWM_EECR0_EE4FAST);
+ Instance->Common.EECR0 = hrpwm_eecr0;
+ /*HRPWM EVENT4 filter*/
+ hrpwm_eecr2 &= ~(HRPWM_EECR2_EE4F);
+ hrpwm_eecr2 |= ((pEventCfg->Filter << HRPWM_EECR2_EE4F_Pos) & HRPWM_EECR2_EE4F);
+ Instance->Common.EECR2 = hrpwm_eecr2;
+ break;
+ }
+
+ case HRPWM_EVENT_5: {
+ hrpwm_eecr1 &= ~(HRPWM_EECR1_EE5SRC | HRPWM_EECR1_EE5POL | HRPWM_EECR1_EE5SNS | HRPWM_EECR1_EE5FAST);
+ hrpwm_eecr1 |= (pEventCfg->Source & HRPWM_EECR1_EE5SRC);
+ hrpwm_eecr1 |= (pEventCfg->Polarity & HRPWM_EECR1_EE5POL);
+ hrpwm_eecr1 |= (pEventCfg->Sensitivity & HRPWM_EECR1_EE5SNS);
+ /* Update the HRPWM registers (all bitfields but EE5FAST bit) */
+ Instance->Common.EECR1 = hrpwm_eecr1;
+ /* Update the HRPWM registers (EE5FAST bit) */
+ hrpwm_eecr1 |= (pEventCfg->FastMode & HRPWM_EECR1_EE5FAST);
+ Instance->Common.EECR1 = hrpwm_eecr1;
+ /*HRPWM EVENT5 filter*/
+ hrpwm_eecr2 &= ~(HRPWM_EECR2_EE5F);
+ hrpwm_eecr2 |= ((pEventCfg->Filter << HRPWM_EECR2_EE5F_Pos) & HRPWM_EECR2_EE5F);
+ Instance->Common.EECR2 = hrpwm_eecr2;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+
+}
+
+/**
+ * @brief Configure the timer select event A config
+ * @param TimerIdx Timer index
+ * @param Event Event channel identifier
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_TimerEventAConfig(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_ExternalEventACfgTypeDef *pEventCfg,
+ HRPWM_TimerEventFilteringCfgTypeDef *pEventFilter)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_EVENTA_FILTER(pEventFilter->Filter));
+ assert_param(IS_HRPWM_EVENTA_LATCH(pEventFilter->Latch));
+ assert_param(IS_HRPWM_EVENTA_SOURCE(pEventCfg->Source));
+ assert_param(IS_HRPWM_EVENTA_RSTMODE(pEventCfg->ResetMode));
+ assert_param(IS_HRPWM_EVENTA_COUNTEREN(pEventCfg->CounterEnable));
+
+
+ uint32_t hrpwm_eefr0 = 0;
+ uint32_t hrpwm_eefr1 = 0;
+
+ hrpwm_eefr0 = Instance->PWM[TimerIdx].EEFR0;
+ hrpwm_eefr1 = Instance->PWM[TimerIdx].EEFR1;
+
+ switch (pEventCfg->Source) {
+ case HRPWM_EEVASEL_SOURCE_EEVENT0:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE0LTCH | HRPWM_EEFR0_EE0FLTR);
+ hrpwm_eefr0 |= (pEventFilter->Filter & HRPWM_EEFR0_EE0FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EEVASEL_SOURCE_EEVENT1:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE1LTCH | HRPWM_EEFR0_EE1FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 5U) & HRPWM_EEFR0_EE1FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EEVASEL_SOURCE_EEVENT2:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE2LTCH | HRPWM_EEFR0_EE2FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 10U) & HRPWM_EEFR0_EE2FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EEVASEL_SOURCE_EEVENT3:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE3LTCH | HRPWM_EEFR0_EE3FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 15U) & HRPWM_EEFR0_EE3FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EEVASEL_SOURCE_EEVENT4:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE4LTCH | HRPWM_EEFR0_EE4FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 20U) & HRPWM_EEFR0_EE4FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EEVASEL_SOURCE_EEVENT5:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE5LTCH | HRPWM_EEFR0_EE5FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 25U) & HRPWM_EEFR0_EE5FLTR) | (pEventFilter->Latch);
+ break;
+
+ default :
+ hrpwm_eefr0 = 0;
+ break;
+ }
+
+ Instance->PWM[TimerIdx].EEFR0 = hrpwm_eefr0;
+
+ if (pEventCfg->CounterEnable != 0x0U) {
+ /*clear event A register */
+ hrpwm_eefr1 &= ~(HRPWM_EEFR1_EEVACE |
+ HRPWM_EEFR1_EEVARSTM |
+ HRPWM_EEFR1_EEVASEL |
+ HRPWM_EEFR1_EEVACNT);
+ /*config event A register */
+ hrpwm_eefr1 |= pEventCfg->CounterEnable |
+ pEventCfg->Source |
+ pEventCfg->ResetMode |
+ (pEventCfg->Counter << 8U);
+ }
+
+ Instance->PWM[TimerIdx].EEFR1 = hrpwm_eefr1;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure the timer select event A config latch or windows
+ * @param TimerIdx Timer index
+ * @param Event A filter windows select or latch identifier
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_TimerEventAFilter(HRPWM_TypeDef *Instance, uint32_t TimerIdx, uint32_t Event,
+ HRPWM_TimerEventFilteringCfgTypeDef *pEventFilter)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+ assert_param(IS_HRPWM_EVENT(Event));
+ assert_param(IS_HRPWM_EVENTA_FILTER(pEventFilter->Filter));
+ assert_param(IS_HRPWM_EVENTA_LATCH(pEventFilter->Latch));
+
+
+ uint32_t hrpwm_eefr0 = 0;
+
+ hrpwm_eefr0 = Instance->PWM[TimerIdx].EEFR0;
+
+ switch (Event) {
+ case HRPWM_EVENT_0:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE0LTCH | HRPWM_EEFR0_EE0FLTR);
+ hrpwm_eefr0 |= (pEventFilter->Filter & HRPWM_EEFR0_EE0FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EVENT_1:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE1LTCH | HRPWM_EEFR0_EE1FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 5U) & HRPWM_EEFR0_EE1FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EVENT_2:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE2LTCH | HRPWM_EEFR0_EE2FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 10U) & HRPWM_EEFR0_EE2FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EVENT_3:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE3LTCH | HRPWM_EEFR0_EE3FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 15U) & HRPWM_EEFR0_EE3FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EVENT_4:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE4LTCH | HRPWM_EEFR0_EE4FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 20U) & HRPWM_EEFR0_EE4FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EVENT_5:
+ hrpwm_eefr0 &= ~(HRPWM_EEFR0_EE5LTCH | HRPWM_EEFR0_EE5FLTR);
+ hrpwm_eefr0 |= ((pEventFilter->Filter << 25U) & HRPWM_EEFR0_EE5FLTR) | (pEventFilter->Latch);
+ break;
+
+ case HRPWM_EVENT_NONE:
+ Instance->PWM[TimerIdx].EEFR0 = 0;
+ break;
+
+ default :
+ break;
+ }
+
+ Instance->PWM[TimerIdx].EEFR0 = hrpwm_eefr0;
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HRPWM_LL_Exported_Functions_Group6 HRPWM Timer waveform configuration and functions
+ * @brief HRPWM timer configuration and control functions
+@verbatim
+ ===============================================================================
+ ##### HRPWM timer configuration and control functions #####
+ ===============================================================================
+ [..] This section provides functions used to configure and control a
+ HRPWM timer operating in waveform mode:
+ (+) software force timer register update
+ (+) Disable timer register update
+ (+) Enable timer register update
+ (+) Enable timer Output start
+ (+) Enable timer Output stop
+ (+) Timer Start output
+ (+) Timer stop output
+ (+) timer output swap
+ (+) Software reset counter
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Force an immediate transfer from the preload to the active registers.
+ * @param TimerIdx Timer index
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_ForceRegistersUpdate(uint32_t TimerIdx)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ switch (TimerIdx) {
+ case HRPWM_INDEX_MASTER: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_MSWU;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_0: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_SWU0;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_1: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_SWU1;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_2: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_SWU2;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_3: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_SWU3;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_4: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_SWU4;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_5: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_SWU5;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Disable transfer from the preload to the active registers.
+ * @param TimerIdx Timer index
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_DisRegisterUpdate(uint32_t TimerIdx)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ switch (TimerIdx) {
+ case HRPWM_INDEX_MASTER: {
+ HRPWM->Common.CR0 |= HRPWM_CR0_MUDIS;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_0: {
+ HRPWM->Common.CR0 |= HRPWM_CR0_UDIS0;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_1: {
+ HRPWM->Common.CR0 |= HRPWM_CR0_UDIS1;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_2: {
+ HRPWM->Common.CR0 |= HRPWM_CR0_UDIS2;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_3: {
+ HRPWM->Common.CR0 |= HRPWM_CR0_UDIS3;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_4: {
+ HRPWM->Common.CR0 |= HRPWM_CR0_UDIS4;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_5: {
+ HRPWM->Common.CR0 |= HRPWM_CR0_UDIS5;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Enable transfer from the preload to the active registers.
+ * @param TimerIdx Timer index
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_EnRegUpdate(uint32_t TimerIdx)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ switch (TimerIdx) {
+ case HRPWM_INDEX_MASTER: {
+ HRPWM->Common.CR0 &= ~(HRPWM_CR0_MUDIS);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_0: {
+ HRPWM->Common.CR0 &= ~(HRPWM_CR0_UDIS0);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_1: {
+ HRPWM->Common.CR0 &= ~(HRPWM_CR0_UDIS1);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_2: {
+ HRPWM->Common.CR0 &= ~(HRPWM_CR0_UDIS2);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_3: {
+ HRPWM->Common.CR0 &= ~(HRPWM_CR0_UDIS3);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_4: {
+ HRPWM->Common.CR0 &= ~(HRPWM_CR0_UDIS4);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_5: {
+ HRPWM->Common.CR0 &= ~(HRPWM_CR0_UDIS5);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Enable output start ,this bit only write 1, can read.
+ * @param TimerIdx Timer index
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_StartOutput(uint32_t TimerIdx)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ switch (TimerIdx) {
+ case HRPWM_INDEX_SLAVE_0: {
+ HRPWM->Common.OENR |= HRPWM_OENR_OEN0A | HRPWM_OENR_OEN0B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_1: {
+ HRPWM->Common.OENR |= HRPWM_OENR_OEN1A | HRPWM_OENR_OEN1B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_2: {
+ HRPWM->Common.OENR |= HRPWM_OENR_OEN2A | HRPWM_OENR_OEN2B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_3: {
+ HRPWM->Common.OENR |= HRPWM_OENR_OEN3A | HRPWM_OENR_OEN3B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_4: {
+ HRPWM->Common.OENR |= HRPWM_OENR_OEN4A | HRPWM_OENR_OEN4B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_5: {
+ HRPWM->Common.OENR |= HRPWM_OENR_OEN5A | HRPWM_OENR_OEN5B;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Enable output stop, stop putput , this bit only write 1, can read.
+ * @param TimerIdx Timer index
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_StopOutput(uint32_t TimerIdx)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ switch (TimerIdx) {
+ case HRPWM_INDEX_SLAVE_0: {
+ HRPWM->Common.ODISR |= HRPWM_ODISR_ODIS0A | HRPWM_ODISR_ODIS0B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_1: {
+ HRPWM->Common.ODISR |= HRPWM_ODISR_ODIS1A | HRPWM_ODISR_ODIS1B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_2: {
+ HRPWM->Common.ODISR |= HRPWM_ODISR_ODIS2A | HRPWM_ODISR_ODIS2B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_3: {
+ HRPWM->Common.ODISR |= HRPWM_ODISR_ODIS3A | HRPWM_ODISR_ODIS3B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_4: {
+ HRPWM->Common.ODISR |= HRPWM_ODISR_ODIS4A | HRPWM_ODISR_ODIS4B;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_5: {
+ HRPWM->Common.ODISR |= HRPWM_ODISR_ODIS5A | HRPWM_ODISR_ODIS5B;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Configure swap output
+ * @param TimerIdx Timer index
+ * @param swap: 0: no swap; 1:swap ;So you can exchange the output with each other
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_SwapOutput(uint32_t TimerIdx, uint32_t swap)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ switch (TimerIdx) {
+ case HRPWM_INDEX_SLAVE_0: {
+ HRPWM->Common.CR1 &= ~(HRPWM_CR1_SWP0);
+ HRPWM->Common.CR1 |= ((swap << 16U) & HRPWM_CR1_SWP0);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_1: {
+ HRPWM->Common.CR1 &= ~(HRPWM_CR1_SWP1);
+ HRPWM->Common.CR1 |= ((swap << 17U) & HRPWM_CR1_SWP1);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_2: {
+ HRPWM->Common.CR1 &= ~(HRPWM_CR1_SWP2);
+ HRPWM->Common.CR1 |= ((swap << 18U) & HRPWM_CR1_SWP2);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_3: {
+ HRPWM->Common.CR1 &= ~(HRPWM_CR1_SWP3);
+ HRPWM->Common.CR1 |= ((swap << 19U) & HRPWM_CR1_SWP3);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_4: {
+ HRPWM->Common.CR1 &= ~(HRPWM_CR1_SWP4);
+ HRPWM->Common.CR1 |= ((swap << 20U) & HRPWM_CR1_SWP4);
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_5: {
+ HRPWM->Common.CR1 &= ~(HRPWM_CR1_SWP5);
+ HRPWM->Common.CR1 |= ((swap << 21U) & HRPWM_CR1_SWP5);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Software reset timer counter.
+ * @param TimerIdx Timer index
+ * @retval None
+ */
+LL_StatusETypeDef LL_HRPWM_ResetCounter(uint32_t TimerIdx)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX(TimerIdx));
+
+ switch (TimerIdx) {
+ case HRPWM_INDEX_MASTER: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_MRST;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_0: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_RST0;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_1: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_RST1;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_2: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_RST2;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_3: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_RST3;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_4: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_RST4;
+ break;
+ }
+
+ case HRPWM_INDEX_SLAVE_5: {
+ HRPWM->Common.CR1 |= HRPWM_CR1_RST5;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HRPWM_LL_Exported_Functions_Interrupt HRPWM Initerrupt management
+ * @brief HRPWM Initerrupt management
+ * @note Functions called when HRPWM generates an interrupt
+ * 8 interrupts can be generated by the master timer:
+ * - Master timer registers update
+ * - Synchronization event received
+ * - Master timer repetition event
+ * - Master Compare a to d event and period event
+ * 11 interrupts can be generated by each timing unit:
+ * - Counter reset or roll-over event
+ * - Output A and output B reset (transition active to inactive)
+ * - Output A and output B set (transition inactive to active)
+ * - Timing unit registers update
+ * - Repetition event
+ * - Compare 1 to 4 event and period event
+ * 7 global interrupts are generated for the whole HRPWM:
+ * - System fault and Fault 0 to 5 (regardless of the timing unit attribution)
+@verbatim
+ ===============================================================================
+ ##### HRPWM interrupts handling #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the HRPWM
+ interrupts:
+ (+) HRPWM interrupt handler
+ (+) Callback function called when Fault0 interrupt occurs
+ (+) Callback function called when Fault1 interrupt occurs
+ (+) Callback function called when Fault2 interrupt occurs
+ (+) Callback function called when Fault3 interrupt occurs
+ (+) Callback function called when Fault4 interrupt occurs
+ (+) Callback function called when Fault5 interrupt occurs
+ (+) Callback function called when system Fault interrupt occurs
+ (+) Callback function called when synchronization input interrupt occurs
+ (+) Callback function called when a timer register update interrupt occurs
+ (+) Callback function called when a timer repetition interrupt occurs
+ (+) Callback function called when a compare A match interrupt occurs
+ (+) Callback function called when a compare B match interrupt occurs
+ (+) Callback function called when a compare C match interrupt occurs
+ (+) Callback function called when a compare D match interrupt occurs
+ (+) Callback function called when a timer period interrupt occurs
+ (+) Callback function called when a timer counter reset interrupt occurs
+ (+) Callback function called when a timer output A set interrupt occurs
+ (+) Callback function called when a timer output A reset interrupt occurs
+ (+) Callback function called when a timer output B set interrupt occurs
+ (+) Callback function called when a timer output B reset interrupt occurs
+ (+) HRPWM callback function registration
+ (+) HRPWM callback function unregistration
+ (+) HRPWM Timer x callback function registration
+ (+) HRPWM Timer x callback function unregistration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles HRPWM interrupt request.
+ * @param TimerIdx Timer index
+ * This parameter can be any value of HRPWM_Timer_Index
+ * @retval None
+ */
+void LL_HRPWM_IRQHandler(uint32_t TimerIdx)
+{
+ /* Check parameters */
+ assert_param(IS_HRPWM_INDEX_ALL(TimerIdx));
+
+ /* HRPWM interrupts handling */
+ if (TimerIdx == HRPWM_INDEX_COMMON) {
+ LL_HRPWM_FLT_IRQHandler();
+ } else if (TimerIdx == HRPWM_INDEX_MASTER) {
+ /* Master related interrupts handling */
+ LL_HRPWM_MSTR_IRQHandler();
+ } else {
+ /* Timing unit related interrupts handling */
+ LL_HRPWM_SLAVE_IRQHandler(TimerIdx);
+ }
+
+}
+
+/**
+ * @brief Callback function invoked when a fault 0 interrupt occurred
+ * @retval None
+ */
+__WEAK void LL_HRPWM_Fault0Callback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Fault0Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 1 interrupt occurred
+ * @retval None
+ */
+__WEAK void LL_HRPWM_Fault1Callback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Fault1Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 2 interrupt occurred
+ * @retval None
+ */
+__WEAK void LL_HRPWM_Fault2Callback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Fault2Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 3 interrupt occurred
+ * @retval None
+ */
+__WEAK void LL_HRPWM_Fault3Callback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Fault3Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 4 interrupt occurred
+ * @retval None
+ */
+__WEAK void LL_HRPWM_Fault4Callback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Fault4Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 5 interrupt occurred
+ * @retval None
+ */
+__WEAK void LL_HRPWM_Fault5Callback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Fault5Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a system fault interrupt occurred
+ * @retval None
+ */
+__WEAK void LL_HRPWM_SystemFaultCallback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_SystemFaultCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a synchronization input event is received
+ * @retval None
+ */
+__WEAK void LL_HRPWM_SynchronizationEventCallback(void)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(HRPWM);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_SynchronizationEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when timer registers are updated
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_RegistersUpdateCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Master_RegistersUpdateCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when timer repetition period has elapsed
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_RepetitionEventCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Master_RepetitionEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare A register
+ * @param hhrpwm pointer to LL HRPWM handle
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_CompareAEventCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Master_CompareAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare B register
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_CompareBEventCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Master_CompareBEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare C register
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_CompareCEventCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Master_CompareCEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare D register
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_CompareDEventCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Master_CompareDEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value programmed in the period register
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_MASTER for master timer
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_PeriodEventCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Master_PeriodEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x counter reset/roll-over event occurs.
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_CounterResetCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Timer_CounterResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output A is set
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_OutputASetCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Timer_OutputASetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output B is set
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_OutputBSetCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Timer_OutputBSetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output A is reset
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_OutputAResetCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Timer_OutputAResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output B is reset
+ * @param TimerIdx Timer index
+ * This parameter can be one of the following values:
+ * @arg HRPWM_INDEX_SLAVE_0 for timer 0
+ * @arg HRPWM_INDEX_SLAVE_1 for timer 1
+ * @arg HRPWM_INDEX_SLAVE_2 for timer 2
+ * @arg HRPWM_INDEX_SLAVE_3 for timer 3
+ * @arg HRPWM_INDEX_SLAVE_4 for timer 4
+ * @arg HRPWM_INDEX_SLAVE_5 for timer 5
+ * @retval None
+ */
+__WEAK void LL_HRPWM_OutputBResetCallback(uint32_t TimerIdx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(TimerIdx);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the LL_HRPWM_Timer_OutputBResetCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function handles HRPWM Master interrupts requests.
+ * @return None
+ */
+void LL_HRPWM_MSTR_IRQHandler(void)
+{
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_MREP) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_MREP)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_MREP);
+
+ /*Handle something*/
+ LL_HRPWM_RepetitionEventCallback(HRPWM_INDEX_MASTER);
+ }
+
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_MUPD) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_MUPD)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_MUPD);
+
+ /*Handle something*/
+ LL_HRPWM_RegistersUpdateCallback(HRPWM_INDEX_MASTER);
+ }
+
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_SYNC) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_SYNC)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_SYNC);
+
+ /*Handle something*/
+ LL_HRPWM_SynchronizationEventCallback();
+ }
+
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_MPER) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_MPER)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_MPER);
+
+ /*Handle something*/
+ LL_HRPWM_PeriodEventCallback(HRPWM_INDEX_MASTER);
+ }
+
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_MCMPD) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_MCMPD)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_MCMPD);
+
+ /*Handle something*/
+ LL_HRPWM_CompareDEventCallback(HRPWM_INDEX_MASTER);
+ }
+
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_MCMPC) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_MCMPC)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_MCMPC);
+
+ /*Handle something*/
+ LL_HRPWM_CompareCEventCallback(HRPWM_INDEX_MASTER);
+ }
+
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_MCMPB) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_MCMPB)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_MCMPB);
+
+ /*Handle something*/
+ LL_HRPWM_CompareBEventCallback(HRPWM_INDEX_MASTER);
+ }
+
+ if (__LL_HRPWM_MASTER_GET_IT(HRPWM_MASTER_IT_MCMPA) && __LL_HRPWM_MASTER_GET_ITFLAG(HRPWM_MASTER_FLAG_MCMPA)) {
+ __LL_HRPWM_MASTER_CLEAR_ITFLAG(HRPWM_MASTER_FLAG_MCMPA);
+
+ /*Handle something*/
+ LL_HRPWM_CompareAEventCallback(HRPWM_INDEX_MASTER);
+ }
+}
+
+/**
+ * @brief This function handles HRPWM Slave interrupts requests.
+ * @return None
+ */
+void LL_HRPWM_SLAVE_IRQHandler(uint32_t TimerIdx)
+{
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_REP) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_REP)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_REP);
+
+ /*Handle something*/
+ LL_HRPWM_RepetitionEventCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_RST) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_RST)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_RST);
+
+ /*Handle something*/
+ LL_HRPWM_CounterResetCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_CLRB) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_CLRB)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_CLRB);
+
+ /*Handle something*/
+ LL_HRPWM_OutputBResetCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_SETB) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_SETB)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_SETB);
+
+ /*Handle something*/
+ LL_HRPWM_OutputBSetCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_CLRA) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_CLRA)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_CLRA);
+
+ /*Handle something*/
+ LL_HRPWM_OutputAResetCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_SETA) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_SETA)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_SETA);
+
+ /*Handle something*/
+ LL_HRPWM_OutputASetCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_UPD) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_UPD)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_UPD);
+
+ /*Handle something*/
+ LL_HRPWM_RegistersUpdateCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_PER) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_PER)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_PER);
+
+ /*Handle something*/
+ LL_HRPWM_PeriodEventCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_CMPD) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_CMPD)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_CMPD);
+
+ /*Handle something*/
+ LL_HRPWM_CompareDEventCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_CMPC) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_CMPC)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_CMPC);
+
+ /*Handle something*/
+ LL_HRPWM_CompareCEventCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_CMPB) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_CMPB)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_CMPB);
+
+ /*Handle something*/
+ LL_HRPWM_CompareBEventCallback(TimerIdx);
+ }
+
+ if (__LL_HRPWM_TIMER_GET_IT(TimerIdx, HRPWM_IT_CMPA) &&
+ __LL_HRPWM_TIMER_GET_ITFLAG(TimerIdx, HRPWM_FLAG_CMPA)) {
+
+ __LL_HRPWM_TIMER_CLEAR_ITFLAG(TimerIdx, HRPWM_FLAG_CMPA);
+
+ /*Handle something*/
+ LL_HRPWM_CompareAEventCallback(TimerIdx);
+ }
+}
+
+/**
+ * @brief This function handles HRPWM Common fault interrupts requests.
+ * @return None
+ */
+void LL_HRPWM_FLT_IRQHandler(void)
+{
+ if (__LL_HRPWM_GET_IT(HRPWM_IT_SYSFLT) && __LL_HRPWM_GET_ITFLAG(HRPWM_FLAG_SYSFLT)) {
+
+ __LL_HRPWM_CLEAR_ITFLAG(HRPWM_FLAG_SYSFLT);
+
+ /*Handle something*/
+ LL_HRPWM_SystemFaultCallback();
+ }
+
+ if (__LL_HRPWM_GET_IT(HRPWM_IT_FLT5) && __LL_HRPWM_GET_ITFLAG(HRPWM_FLAG_FLT5)) {
+
+ __LL_HRPWM_CLEAR_ITFLAG(HRPWM_FLAG_FLT5);
+
+ /*Handle something*/
+ LL_HRPWM_Fault5Callback();
+ }
+
+ if (__LL_HRPWM_GET_IT(HRPWM_IT_FLT4) && __LL_HRPWM_GET_ITFLAG(HRPWM_FLAG_FLT4)) {
+
+ __LL_HRPWM_CLEAR_ITFLAG(HRPWM_FLAG_FLT4);
+
+ /*Handle something*/
+ LL_HRPWM_Fault4Callback();
+ }
+
+ if (__LL_HRPWM_GET_IT(HRPWM_IT_FLT3) && __LL_HRPWM_GET_ITFLAG(HRPWM_FLAG_FLT3)) {
+
+ __LL_HRPWM_CLEAR_ITFLAG(HRPWM_FLAG_FLT3);
+
+ /*Handle something*/
+ LL_HRPWM_Fault3Callback();
+ }
+
+ if (__LL_HRPWM_GET_IT(HRPWM_IT_FLT2) && __LL_HRPWM_GET_ITFLAG(HRPWM_FLAG_FLT2)) {
+
+ __LL_HRPWM_CLEAR_ITFLAG(HRPWM_FLAG_FLT2);
+
+ /*Handle something*/
+ LL_HRPWM_Fault2Callback();
+ }
+
+ if (__LL_HRPWM_GET_IT(HRPWM_IT_FLT1) && __LL_HRPWM_GET_ITFLAG(HRPWM_FLAG_FLT1)) {
+
+ __LL_HRPWM_CLEAR_ITFLAG(HRPWM_FLAG_FLT1);
+
+ /*Handle something*/
+ LL_HRPWM_Fault1Callback();
+ }
+
+ if (__LL_HRPWM_GET_IT(HRPWM_IT_FLT0) && __LL_HRPWM_GET_ITFLAG(HRPWM_FLAG_FLT0)) {
+
+ __LL_HRPWM_CLEAR_ITFLAG(HRPWM_FLAG_FLT0);
+
+ /*Handle something*/
+ LL_HRPWM_Fault0Callback();
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup HRPWM_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Configure the master timer in waveform mode
+ * @param pTimerCompCfg pointer to the timer configuration data structure
+ * @retval None
+ */
+static void HRPWM_MasterCompare_Config(HRPWM_TypeDef *Instance, HRPWM_TimerCompareCfgTypeDef *pTimerCompCfg)
+{
+ uint32_t hrpwm_mcr;
+
+ /* Configure master timer */
+ hrpwm_mcr = Instance->Master.MCR;
+ /* Enable/Disable preload meachanism for timer registers */
+ hrpwm_mcr &= ~(HRPWM_MCR_PREEN);
+ hrpwm_mcr |= pTimerCompCfg->PreloadEnable;
+
+ /* Update the HRPWM registers */
+ Instance->Master.MCR |= hrpwm_mcr;
+ /*Update Compare Value*/
+ Instance->Master.MCMPAR = pTimerCompCfg->CompareValueA;
+ Instance->Master.MCMPBR = pTimerCompCfg->CompareValueB;
+ Instance->Master.MCMPCR = pTimerCompCfg->CompareValueC;
+ Instance->Master.MCMPDR = pTimerCompCfg->CompareValueD;
+}
+
+/**
+ * @brief Configure timing unit (Timer 0 to Timer 5) in waveform mode
+ * @param TimerIdx Timer index
+ * @param pTimerCompCfg pointer to the timer configuration data structure
+ * @retval None
+ */
+static void HRPWM_TimingUnitCompare_Config(HRPWM_TypeDef *Instance, uint32_t TimerIdx,
+ HRPWM_TimerCompareCfgTypeDef *pTimerCompCfg)
+{
+ uint32_t hrpwm_cr0;
+
+ /* Configure master timing unit */
+ hrpwm_cr0 = Instance->PWM[TimerIdx].CR0;
+
+ /* UPDGAT bitfield must be reset before programming a new value */
+ hrpwm_cr0 &= ~(HRPWM_CR0_MUPD | HRPWM_CR0_UPD0 | HRPWM_CR0_UPD1 | HRPWM_CR0_UPD2 | HRPWM_CR0_UPD3 |
+ HRPWM_CR0_UPD4 | HRPWM_CR0_UPD5 | HRPWM_UPDATETRIGGER_REP | HRPWM_UPDATETRIGGER_RST);
+ /* Set the timer update trigger */
+ hrpwm_cr0 |= pTimerCompCfg->UpdateTrigger;
+
+ /* Enable/Disable preload meachanism for timer registers */
+ hrpwm_cr0 &= ~(HRPWM_CR0_PREEN);
+ hrpwm_cr0 |= pTimerCompCfg->PreloadEnable;
+
+ /* Update the HRPWM registers */
+ Instance->PWM[TimerIdx].CR0 |= hrpwm_cr0;
+ /* Update Compare Value */
+ Instance->PWM[TimerIdx].CMPAR = pTimerCompCfg->CompareValueA;
+ Instance->PWM[TimerIdx].CMPBR = pTimerCompCfg->CompareValueB;
+ Instance->PWM[TimerIdx].CMPCR = pTimerCompCfg->CompareValueC;
+ Instance->PWM[TimerIdx].CMPDR = pTimerCompCfg->CompareValueD;
+}
+
+/**
+ * @brief Configure the master timer time base
+ * @param pTimeBaseCfg pointer to the time base configuration structure
+ * @retval None
+ */
+static void HRPWM_MasterBase_Config(HRPWM_TypeDef *Instance, HRPWM_TimerBaseCfgTypeDef *pTimeBaseCfg)
+{
+ uint32_t hrpwm_mcr;
+
+ /* Configure master timer */
+ hrpwm_mcr = Instance->Master.MCR;
+
+ /* Set the prescaler ratio */
+ hrpwm_mcr &= ~(HRPWM_MCR_CKPSC);
+ hrpwm_mcr |= pTimeBaseCfg->PrescalerRatio;
+
+ /* Set the operating mode */
+ hrpwm_mcr &= ~(HRPWM_MCR_CONT | HRPWM_MCR_RETRIG);
+ hrpwm_mcr |= pTimeBaseCfg->Mode;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ hrpwm_mcr &= ~(HRPWM_MCR_SYNCSTRTM);
+ hrpwm_mcr |= pTimeBaseCfg->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ hrpwm_mcr &= ~(HRPWM_MCR_SYNCRSTM);
+ hrpwm_mcr |= pTimeBaseCfg->ResetOnSync;
+
+ /*Enable Master interrupt*/
+ Instance->Master.MIER = pTimeBaseCfg->InterruptRequests;
+
+ /* Update the HRPWM registers */
+ Instance->Master.MCR |= hrpwm_mcr;
+ Instance->Master.MPER = pTimeBaseCfg->Period;
+ Instance->Master.MCNTR = (pTimeBaseCfg->RepetitionCounter) << HRPWM_MCNTR_MREP_Pos;
+}
+
+/**
+ * @brief Configure timing unit (Timer 0 to Timer 5) time base
+ * @param TimerIdx Timer index
+ * @param pTimeBaseCfg pointer to the time base configuration structure
+ * @retval None
+ */
+static void HRPWM_TimingUnitBase_Config(HRPWM_TypeDef *Instance, uint32_t TimerIdx, HRPWM_TimerBaseCfgTypeDef *pTimeBaseCfg)
+{
+ uint32_t hrpwm_cr0;
+ uint32_t hrpwm_rstr;
+
+ /* Configure timing unit (Timer 0 to Timer 5) */
+ hrpwm_cr0 = Instance->PWM[TimerIdx].CR0;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ hrpwm_cr0 &= ~(HRPWM_CR0_SYNCSTRT);
+ hrpwm_cr0 |= pTimeBaseCfg->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ hrpwm_cr0 &= ~(HRPWM_CR0_SYNCRST);
+ hrpwm_cr0 |= pTimeBaseCfg->ResetOnSync;
+
+ /* Timing unit Re-Synchronized Update */
+ hrpwm_cr0 &= ~(HRPWM_CR0_RSYNCU);
+ hrpwm_cr0 |= (pTimeBaseCfg->ReSyncUpdate & HRPWM_CR0_RSYNCU);
+
+ /* Set the prescaler ratio */
+ hrpwm_cr0 &= ~(HRPWM_CR0_CKPSC);
+ hrpwm_cr0 |= pTimeBaseCfg->PrescalerRatio;
+
+ /* Set the operating mode */
+ hrpwm_cr0 &= ~(HRPWM_CR0_CONT | HRPWM_CR0_RETRIG);
+ hrpwm_cr0 |= pTimeBaseCfg->Mode;
+
+ /* Set the timer counter reset trigger */
+ hrpwm_rstr = pTimeBaseCfg->ResetTrigger;
+
+ /* Update the HRPWM registers */
+ Instance->PWM[TimerIdx].CR0 |= hrpwm_cr0;
+ Instance->PWM[TimerIdx].RSTR = hrpwm_rstr;
+ Instance->PWM[TimerIdx].PERR = pTimeBaseCfg->Period;
+ Instance->PWM[TimerIdx].CNTR = (pTimeBaseCfg->RepetitionCounter) << HRPWM_CNTR_REP_Pos;
+
+ /*Enable timer uint interrupt*/
+ Instance->PWM[TimerIdx].IER = pTimeBaseCfg->InterruptRequests;
+}
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_HRPWM_MODULE_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_i2c.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_i2c.c
new file mode 100644
index 0000000000..401c7cd980
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_i2c.c
@@ -0,0 +1,2202 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_i2c.c
+ * @author MCD Application Team
+ * @brief I2C LL Module Driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+#define DBG_TAG "I2C"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup I2C_LL I2C LL
+ * @brief I2C LL Module Driver
+ * @{
+ */
+
+#ifdef LL_I2C_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Types I2C LL Private Types
+ * @brief I2C LL Private Types
+ * @{
+ */
+
+/**
+ * @brief I2C LL Config Type Definition
+ */
+
+typedef struct __I2C_LLCfgTypeDef {
+ bool restart_en; /*!< Restart enable */
+ bool rxfifo_full_hold_en; /*!< RXFIFO full hold enable */
+ bool slv_nack_en; /*!< Slave NACK enable */
+ bool ack_gen_call_en; /*!< ACK genaral call enable */
+ uint8_t sda_setup; /*!< SDA setup time */
+} I2C_LLCfgTypeDef;
+
+
+/**
+ * @}
+ */
+
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Macros I2C LL Private Macros
+ * @brief I2C LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief I2C Function Alternative
+ * @param flag Condition Flag
+ * @param func_t True Funciton
+ * @param func_f False Function
+ * @return None
+ */
+#define I2C_FUNC_ALTER(flag, func_t, func_f) \
+ do{ \
+ if((flag)) { \
+ func_t; \
+ } else { \
+ func_f; \
+ } \
+ } while(0)
+
+/**
+ * @}
+ */
+
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Variables I2C LL Private Variables
+ * @brief I2C LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief Default I2C Hardware Config
+ */
+static const I2C_LLCfgTypeDef i2c_ll_cfg_def = {
+ .restart_en = true,
+ .rxfifo_full_hold_en = false,
+ .slv_nack_en = false,
+ .ack_gen_call_en = true,
+ .sda_setup = 0x64,
+};
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Functions I2C LL Private function
+ * @brief I2C LL Private function
+ * @{
+ */
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+ static DMA_ChannelETypeDef LL_I2C_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg);
+ static LL_StatusETypeDef LL_I2C_DMA_Deinit(DMA_ChannelETypeDef ch);
+ static void LL_I2C_DMA_TXCHEndCallback(void *arg);
+ static void LL_I2C_DMA_RXCHEndCallback(void *arg);
+ static void LL_I2C_DMA_TXCHErrorCallBck(void *arg);
+ static void LL_I2C_DMA_RXCHErrorCallBck(void *arg);
+
+#endif
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C LL Exported Functions
+ * @brief I2C LL Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+
+/**
+ * @brief I2C LL Init
+ * @param Instance Specifies I2C peripheral
+ * @param user_cfg user config pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_I2C_Init(I2C_TypeDef *Instance, I2C_UserCfgTypeDef *user_cfg)
+{
+ uint32_t baudrate_cnt;
+ I2C_LLCfgTypeDef *ll_cfg = (I2C_LLCfgTypeDef *)&i2c_ll_cfg_def;
+
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_I2C_MspInit(Instance);
+
+ /* Disable all interrupt*/
+ CLEAR_REG(Instance->INTRMS);
+
+ /* I2C LL Config */
+ //I2C Restart Enable/Disable
+ I2C_FUNC_ALTER(ll_cfg->restart_en, __LL_I2C_MST_Restart_En(Instance), __LL_I2C_MST_Restart_Dis(Instance));
+
+ //I2C RXFIFO Full Hold Control
+ I2C_FUNC_ALTER(ll_cfg->rxfifo_full_hold_en, __LL_I2C_RxFIFOFullHold_En(Instance), __LL_I2C_RxFIFOFullHold_Dis(Instance));
+
+ //I2C Slave NACK Config
+ I2C_FUNC_ALTER(ll_cfg->slv_nack_en, __LL_I2C_SLV_ForceDataNoAck_Set(Instance), __LL_I2C_SLV_ForceDataNoAck_Clr(Instance));
+
+ //I2C ACK Gen Call Config
+ I2C_FUNC_ALTER(ll_cfg->ack_gen_call_en, __LL_I2C_AckGenCall_En(Instance), __LL_I2C_AckGenCall_Dis(Instance));
+
+ //I2C Spike Filtered Cnt Config
+ __LL_I2C_FsSpkLen_Set(Instance, (uint32_t)50000000 / LL_SYSCTRL_SysclkGet());
+
+ //I2C SDA Timing Config
+ __LL_I2C_SDATxHold_Set(Instance, READ_REG(Instance->SSLCNT) >> 1);
+ __LL_I2C_SDARxHold_Set(Instance, READ_REG(Instance->SSLCNT) >> 1);
+ __LL_I2C_SDA_Setup_Set(Instance, ll_cfg->sda_setup);
+
+
+ /* I2C user config */
+ //I2C Role Mode Config
+ I2C_FUNC_ALTER(user_cfg->role == I2C_ROLE_MASTER, __LL_I2C_MASTER_Mode_En(Instance), __LL_I2C_MASTER_Mode_Dis(Instance));
+ I2C_FUNC_ALTER(user_cfg->role == I2C_ROLE_MASTER, __LL_I2C_SLAVE_Mode_Dis(Instance), __LL_I2C_SLAVE_Mode_En(Instance));
+
+ //I2C Address Mode Config
+ if (user_cfg->role == I2C_ROLE_SLAVE) {
+ I2C_FUNC_ALTER(user_cfg->addr_mode == I2C_ADDR_7BIT, __LL_I2C_SLV_7bAddr_Set(Instance), __LL_I2C_SLV_10bAddr_Set(Instance));
+ }
+
+ //I2C Speed Mode and Baudrate Config
+ assert_param(user_cfg->baudrate);
+ baudrate_cnt = LL_SYSCTRL_APB0ClkGet() / user_cfg->baudrate / 2;
+
+ if (user_cfg->baudrate <= I2C_SS_SPEED_MAX) { //standard speed
+ __LL_I2C_Speed_Set(Instance, I2C_SPEED_STD);
+ __LL_I2C_SS_SCLHcnt_Set(Instance, baudrate_cnt);
+ __LL_I2C_SS_SCLLcnt_Set(Instance, baudrate_cnt);
+ } else if (user_cfg->baudrate <= I2C_FS_SPEED_MAX) { //fast speed
+ __LL_I2C_Speed_Set(Instance, I2C_SPEED_FAST);
+ __LL_I2C_FS_SCLHcnt_Set(Instance, baudrate_cnt);
+ __LL_I2C_FS_SCLLcnt_Set(Instance, baudrate_cnt);
+ } else if (user_cfg->baudrate <= I2C_FS_PLUS_SPEED_MAX) { //fast plus speed
+ __LL_I2C_Speed_Set(Instance, I2C_SPEED_FAST);
+ __LL_I2C_FS_SCLHcnt_Set(Instance, baudrate_cnt);
+ __LL_I2C_FS_SCLLcnt_Set(Instance, baudrate_cnt);
+ } else if (user_cfg->baudrate <= I2C_HS_SPEED_MAX) { //high speed
+ LOG_E("Don't support High Speed mode!\n");
+ return LL_ERROR;
+ } else {
+ LOG_E("Invalid baudrate params: %d\n", user_cfg->baudrate);
+ return LL_ERROR;
+ }
+
+ //I2C Slave Address Config
+ __LL_I2C_SAR_Set(Instance, user_cfg->slave_addr);
+
+ //I2C TXFIFO Transmit Data Enable
+ __LL_I2C_MST_TxCmdBlock_Clr(Instance);
+
+ if (user_cfg->smbus_enable == ENABLE) {
+ __LL_I2C_SMBUS_ClkLowMextTimeout_Set(Instance, user_cfg->smbus_master_extend_clk);
+ __LL_I2C_SMBUS_ClkLowSextTimeout_Set(Instance, user_cfg->smbus_slaver_extend_clk);
+ }
+
+ //I2C Module Enable
+ __LL_I2C_Enable(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL DeInit
+ * @param Instance Specifies I2C peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_I2C_DeInit(I2C_TypeDef *Instance)
+{
+ //I2C Module Disable
+ __LL_I2C_Disable(Instance);
+
+ //I2C TXFIFO Transmit Data Disable
+ __LL_I2C_MST_TxCmdBlock_Set(Instance);
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_I2C_MspDeInit(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the I2C MSP.
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MspInit(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the I2C MSP
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MspDeInit(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_LL_Exported_Functions_Group2 Read Write Functions
+ * @brief Read Write Functions
+ * @{
+ */
+
+/**
+ * @brief I2C LL Master Read by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return success read length
+ */
+uint32_t LL_I2C_MasterRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t w_cnt = 0, r_cnt = 0;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_RestartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_RestartAddr32b(Instance, frame->mem_addr);
+ }
+
+ if (frame->buf_len == 1) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read, then stop
+ __LL_I2C_Timing_RestartReadStop(Instance);
+ } else {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read
+ __LL_I2C_Timing_RestartRead(Instance);
+
+ //read data loop
+ for (w_cnt = 0; w_cnt < frame->buf_len - 2; w_cnt++) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //Read, send the read signal actually acts as ii_clk
+ __LL_I2C_Timing_Read(Instance);
+
+ /* wait RXFIFO not empty */
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance));
+
+ *frame->buf++ = __LL_I2C_DAT_Read(Instance);
+ r_cnt++;
+ }
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //read last byte, then stop
+ __LL_I2C_Timing_ReadStop(Instance);
+ }
+
+ //read remain data
+ for (; r_cnt < frame->buf_len; r_cnt++) {
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance));
+
+ *frame->buf++ = __LL_I2C_DAT_Read(Instance);
+ }
+
+ /* wait for last data sent */
+ while (!__LL_I2C_IsStopDet_Raw(Instance));
+
+ return r_cnt;
+}
+
+
+/**
+ * @brief I2C LL Slave Read by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ @param Timeout Limited operation time
+ @note The slave cannot initiate a read operation, it can only respond to the read request of the master
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_I2C_SlaveRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ while (frame->buf_len > 0U) {
+ /* Wait until ReadReq flag is set */
+ tickstart = LL_GetTick();
+
+ /* wait RXFIFO not empty */
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Clear ReadReq bit */
+ __LL_I2C_SLV_ReadReqRawIntSta_Clr(Instance);
+
+ *frame->buf++ = __LL_I2C_DAT_Read(Instance);
+ frame->buf_len--;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL Master Write by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return success write length
+ */
+uint32_t LL_I2C_MasterWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t w_cnt = 0;
+ bool need_start = false;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_RestartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_RestartAddr32b(Instance, frame->mem_addr);
+ } else {
+ need_start = true;
+ }
+
+ //write data loop
+ for (w_cnt = 0; w_cnt < frame->buf_len - 1; w_cnt++) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //write data
+ if (need_start == true) {
+ need_start = false;
+ __LL_I2C_Timing_RestartWrite(Instance, *frame->buf++);
+ } else {
+ __LL_I2C_Timing_Write(Instance, *frame->buf++);
+ }
+ }
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //write last byte, then stop
+ if (need_start == true) {
+ need_start = false;
+ __LL_I2C_Timing_RestartWriteStop(Instance, *frame->buf++);
+ } else {
+ __LL_I2C_Timing_WriteStop(Instance, *frame->buf++);
+ }
+
+ w_cnt++;
+
+ /* wait for last data sent */
+ while (__LL_I2C_SLV_IsActivity(Instance));
+
+ return w_cnt;
+}
+
+
+/**
+ * @brief I2C LL Slave Write by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ @note The slave cannot initiate a write request actively, and can only write after the master sends a read command
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_I2C_SlaveWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ while (frame->buf_len > 0U) {
+ /* Wait until ReadReq flag is set */
+ tickstart = LL_GetTick();
+
+ while (!__LL_I2C_SLV_IsReadReq_Raw(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* I2C Slave Read Request Interrupt Status Clear */
+ __LL_I2C_SLV_ReadReqRawIntSta_Clr(Instance);
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ __LL_I2C_DAT_Write(Instance, *frame->buf++);
+ frame->buf_len--;
+ }
+
+ //wait slave is not active,to sure data has been sent
+ while (__LL_I2C_SLV_IsActivity(Instance));
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL Smbus Write by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return success write length
+ */
+uint32_t LL_SMBUS_MasterWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t w_cnt = 0;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send Smbus Command
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->command & 0xffUL));
+
+ //write data loop
+ for (w_cnt = 0; w_cnt < frame->buf_len - 1; w_cnt++) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ __LL_I2C_Timing_Write(Instance, *frame->buf++);
+ }
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //write last byte, then stop
+ __LL_I2C_Timing_WriteStop(Instance, *frame->buf++);
+ w_cnt++;
+
+ /* wait for last data to be sent */
+ while (!__LL_I2C_IsStopDet_Raw(Instance));
+
+ return w_cnt;
+}
+
+
+/**
+ * @brief I2C LL Slave Read by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ @param Timeout Limited operation time
+ @note The first command received by the slave is the command sent by the master, not the actual information
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ while (frame->buf_len > 0U) {
+ /* Wait until RxFIFO is not empty */
+ tickstart = LL_GetTick();
+
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ *frame->buf++ = __LL_I2C_DAT_Read(Instance);
+ frame->buf_len--;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL Smbus Read by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return success read length
+ */
+uint32_t LL_SMBUS_MasterRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t w_cnt = 0, r_cnt = 0;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->command & 0xffUL));
+
+ if (frame->buf_len == 1) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read, then stop
+ __LL_I2C_Timing_RestartReadStop(Instance);
+ } else {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read
+ __LL_I2C_Timing_RestartRead(Instance);
+
+ //read data loop
+ for (w_cnt = 0; w_cnt < frame->buf_len - 2; w_cnt++) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //Read, send the read signal actually acts as ii_clk
+ __LL_I2C_Timing_Read(Instance);
+
+ /* wait RXFIFO not empty */
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance));
+
+ *frame->buf++ = __LL_I2C_DAT_Read(Instance);
+ r_cnt++;
+ }
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //read last byte, then stop
+ __LL_I2C_Timing_ReadStop(Instance);
+ }
+
+ //read remain data
+ for (; r_cnt < frame->buf_len; r_cnt++) {
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance));
+
+ *frame->buf++ = __LL_I2C_DAT_Read(Instance);
+ }
+
+ /* wait for last data sent */
+ while (!__LL_I2C_IsStopDet_Raw(Instance));
+
+ return r_cnt;
+}
+
+
+/**
+ * @brief I2C LL Smbus Write by CPU
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @param Timeout Limited operation time
+ @note The slave cannot initiate a write operation, it can only respond to the read request of the master
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ while (frame->buf_len > 0U) {
+ /* Wait until ReadReq flag is set */
+ tickstart = LL_GetTick();
+
+ while (!__LL_I2C_SLV_IsReadReq_Raw(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* I2C Slave Read Request Interrupt Status Clear */
+ __LL_I2C_SLV_ReadReqRawIntSta_Clr(Instance);
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ __LL_I2C_DAT_Write(Instance, *frame->buf++);
+ frame->buf_len--;
+ }
+
+ //wait slave is not active,to sure data has been sent
+ while (__LL_I2C_SLV_IsActivity(Instance));
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL Master Write by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note Put the user code in LL_I2C_TxEmptyCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_SMBUS_MasterWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ __LL_I2C_TxEmpty_INT_Dis(Instance);
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+ //start and send Smbus Command
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->command & 0xffUL));
+
+ if (frame->buf_len > 1) {
+ //write data
+ frame->XferCount = frame->buf_len - 1;
+
+ /* I2C TX Empty Interrupt Enable */
+ __LL_I2C_TxEmpty_INT_En(Instance);
+ } else {
+ __LL_I2C_Timing_WriteStop(Instance, *frame->buf);
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL Master Read by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note Put the user code in LL_I2C_RxFullCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_SMBUS_MasterRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ __LL_I2C_TxEmpty_INT_Dis(Instance);
+
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+ //start and send read memory address if has memory address to send
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->command & 0xffUL));
+
+ frame->XferCount = frame->buf_len;
+
+ /* I2C RX Full Interrupt Enable */
+ __LL_I2C_RxFull_INT_En(Instance);
+
+ if (frame->buf_len == 1) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read, then stop
+ __LL_I2C_Timing_RestartReadStop(Instance);
+ } else {
+ //start+TAR, read
+ __LL_I2C_Timing_RestartRead(Instance);
+ frame->clk_cnt = frame->buf_len - 2;
+ frame->XferCount = frame->buf_len;
+ /* I2C TX Empty Interrupt Enable */
+ __LL_I2C_TxEmpty_INT_En(Instance);
+ }
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL Slave Write by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note The read operation of the corresponding Master from the Slave, and the data is sent to the Master
+ Put the user code in LL_I2C_SlvReadReqCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->XferCount = frame->buf_len;
+ /* I2C Slave Read Request Interrupt Enable */
+ __LL_I2C_SLV_ReadReq_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL Slave Write by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note Write operation of the corresponding Master from the slave to save the data
+ Put the user code in LL_I2C_SlvReadReqCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->XferCount = frame->buf_len;
+ /* I2C RX Full Interrupt Enable */
+ __LL_I2C_RxFull_INT_En(Instance);
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL Master Write by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note Put the user code in LL_I2C_TxEmptyCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_I2C_MasterWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ bool need_start = false;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ __LL_I2C_TxEmpty_INT_Dis(Instance);
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_RestartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_RestartAddr32b(Instance, frame->mem_addr);
+ } else {
+ need_start = true;
+ }
+
+ if (frame->buf_len > 1) {
+ //write data
+ if (need_start == true) {
+ need_start = false;
+ __LL_I2C_Timing_RestartWrite(Instance, *frame->buf++);
+ frame->XferCount = frame->buf_len - 2;
+ } else {
+ frame->XferCount = frame->buf_len - 1;
+ }
+ }
+
+ //write last byte, then stop
+ if (need_start == true) {
+ need_start = false;
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ __LL_I2C_Timing_RestartWriteStop(Instance, *frame->buf);
+ } else {
+ /* I2C TX Empty Interrupt Enable */
+ __LL_I2C_TxEmpty_INT_En(Instance);
+ }
+
+ return LL_OK;
+}
+
+
+
+/**
+ * @brief I2C LL Slave Write by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note The read operation of the corresponding Master from the Slave, and the data is sent to the Master
+ Put the user code in LL_I2C_SlvReadReqCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_I2C_SlaveWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->XferCount = frame->buf_len;
+
+ /* I2C Slave Read Request Interrupt Enable */
+ __LL_I2C_SLV_ReadReq_INT_En(Instance);
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL Master Read by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note Put the user code in LL_I2C_RxFullCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_I2C_MasterRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ __LL_I2C_TxEmpty_INT_Dis(Instance);
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+ /* I2C RX Full Interrupt Enable */
+ __LL_I2C_RxFull_INT_En(Instance);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_RestartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_RestartAddr32b(Instance, frame->mem_addr);
+ }
+
+ if (frame->buf_len == 1) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read, then stop
+ __LL_I2C_Timing_RestartReadStop(Instance);
+ } else {
+ //start+TAR, read
+ __LL_I2C_Timing_RestartRead(Instance);
+ frame->clk_cnt = frame->buf_len - 2;
+ frame->XferCount = frame->buf_len;
+ /* I2C TX Empty Interrupt Enable */
+ __LL_I2C_TxEmpty_INT_En(Instance);
+ }
+
+ return LL_OK;
+
+}
+
+/**
+ * @brief I2C LL Slave Write by interrupt
+ * @param Instance Specifies I2C peripheral
+ @note Write operation of the corresponding Master from the slave to save the data
+ Put the user code in LL_I2C_SlvReadReqCallback
+ * @return None
+ */
+LL_StatusETypeDef LL_I2C_SlaveRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->XferCount = frame->buf_len;
+ /* I2C RX Full Interrupt Enable */
+ __LL_I2C_RxFull_INT_En(Instance);
+
+ return LL_OK;
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief I2C LL Slave Write by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param dma_user_cfg user dma config pointer
+ * @param frame write frame pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_I2C_MasterWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ bool need_start = false;
+ frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+ uint32_t tickstart;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->Instance = Instance;
+ frame->TXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_TXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_TXCHErrorCallBck;
+
+ /* Wait until I2C DMA Init ok */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_tx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ frame->TXdma_status = IIC_DMA_STATE_READY;
+
+ /* TAR config */
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ /* Send read memory address wiht start singal if user has memory address to send */
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_RestartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_RestartAddr32b(Instance, frame->mem_addr);
+ } else {
+ need_start = true;
+ }
+
+ /* Enable Transmit DMA func */
+ __LL_I2C_TxDMA_En(Instance);
+
+ /* The first data must sent with start singal and the last data should sent with stop singal,
+ Remaining data can sent by DMA*/
+ if (need_start == true) {
+ need_start = false;
+
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ __LL_I2C_Timing_RestartWrite(Instance, *frame->buf++);
+
+ if (frame->buf_len > 2) {
+ LL_DMA_Start_IT(DMA, frame->dma_tx_ch, (uint32_t)frame->buf, (uint32_t)&Instance->DCMD, frame->buf_len - 1);
+ frame->TXdma_status = IIC_DMA_STATE_BUSY;
+ } else {
+ __LL_I2C_Timing_RestartWriteStop(Instance, *(frame->buf + frame->buf_len - 1));
+ }
+
+ } else {
+ if (frame->buf_len >= 2) {
+ LL_DMA_Start_IT(DMA, frame->dma_tx_ch, (uint32_t)frame->buf, (uint32_t)&Instance->DCMD, frame->buf_len - 1);
+ frame->TXdma_status = IIC_DMA_STATE_BUSY;
+ } else {
+ __LL_I2C_Timing_WriteStop(Instance, *(frame->buf + frame->buf_len - 1));
+ }
+ }
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL Master Read by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param dma_user_cfg user dma config pointer
+ * @param frame Read frame pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_I2C_MasterRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t clk_cmd = I2C_CMD_READ;
+ DMA_UserCfgTypeDef dma_masterclk_cfg;
+ frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+ frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->Instance = Instance;
+ frame->TXdma_status = IIC_DMA_STATE_RESET;
+ frame->RXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_RXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_RXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_rx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_rx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ frame->TXdma_status = IIC_DMA_STATE_READY;
+
+ /* Need a DMA chanl send clock singal to Keep communication with slave */
+ dma_masterclk_cfg.trans_type = DMA_TRANS_TYPE_M2P;
+ dma_masterclk_cfg.src_addr_mode = DMA_SRC_ADDR_MODE_FIX;
+ dma_masterclk_cfg.dst_addr_mode = DMA_DST_ADDR_MODE_FIX;
+ dma_masterclk_cfg.src_data_width = DMA_SRC_TRANS_WIDTH_16b;
+ dma_masterclk_cfg.dst_data_width = DMA_DST_TRANS_WIDTH_16b;
+ dma_masterclk_cfg.src_hs_ifc = DMA_SRC_HANDSHAKE_IFC_MEMORY;
+
+ if (Instance == I2C0) {
+ dma_masterclk_cfg.dst_hs_ifc = DMA_DST_HANDSHAKE_IFC_I2C0_TX;
+ } else {
+ dma_masterclk_cfg.dst_hs_ifc = DMA_DST_HANDSHAKE_IFC_I2C1_TX;
+ }
+
+ dma_masterclk_cfg.end_arg = (void *)frame;
+ dma_masterclk_cfg.end_callback = LL_I2C_DMA_TXCHEndCallback;
+ dma_masterclk_cfg.err_arg = (void *)frame;
+ dma_masterclk_cfg.err_callback = LL_I2C_DMA_TXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_tx_ch = LL_I2C_DMA_Init(&dma_masterclk_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ frame->RXdma_status = IIC_DMA_STATE_READY;
+
+ /* TAR config */
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_RestartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_RestartAddr32b(Instance, frame->mem_addr);
+ }
+
+ /* Enable Transmit/Receive DMA func */
+ __LL_I2C_RxDMA_En(Instance);
+ __LL_I2C_TxDMA_En(Instance);
+
+ if (frame->buf_len == 1) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read, then stop
+ __LL_I2C_Timing_RestartReadStop(Instance);
+
+ /* Get the last data */
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance));
+
+ *(frame->buf + frame->buf_len - 1) = __LL_I2C_DAT_Read(Instance);
+
+ /* wait for last data sent */
+ while (!__LL_I2C_IsStopDet_Raw(Instance));
+
+ } else {
+
+ //start+TAR, read
+ __LL_I2C_Timing_RestartRead(Instance);
+ /* Indicates how many clk needs to be sent */
+ frame->clk_cnt = frame->buf_len - 1;
+ /* Master should sent clk to Keep communication with slave,and READ_CMD is U16,means U8 Multiply 2,
+ The first data has not save yet,but the clock has been sent. And the last read command need sent
+ with Stop Command,so that the length of ch1 is 2*(buf_len -2),and chn0 is buf_len */
+ LL_DMA_Start_IT(DMA, frame->dma_tx_ch, (uint32_t)&clk_cmd, (uint32_t)&Instance->DCMD, 2 * (frame->buf_len - 2));
+ LL_DMA_Start_IT(DMA, frame->dma_rx_ch, (uint32_t)&Instance->DCMD, (uint32_t)frame->buf, frame->buf_len);
+
+ frame->TXdma_status = IIC_DMA_STATE_BUSY;
+ frame->RXdma_status = IIC_DMA_STATE_BUSY;
+ }
+
+ /* Return Status */
+ return LL_OK;
+
+
+}
+
+
+/**
+ * @brief I2C LL Slave Read by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame Read frame pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_I2C_SlaveWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->Instance = Instance;
+ frame->TXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_TXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_TXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_tx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Wait for I2C Slave Read Request Interrupt Status Set */
+ tickstart = LL_GetTick();
+
+ while (!__LL_I2C_SLV_IsReadReq_Raw(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Enable Transmit DMA func */
+ __LL_I2C_TxDMA_En(Instance);
+ /* DMA work */
+ LL_DMA_Start_IT(DMA, frame->dma_tx_ch, (uint32_t)frame->buf, (uint32_t)&Instance->DCMD, frame->buf_len);
+ frame->TXdma_status = IIC_DMA_STATE_BUSY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL Slave Write by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame Write frame pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_I2C_SlaveRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ frame->Instance = Instance;
+ frame->RXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_RXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_RXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_rx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_rx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Wait until ReadFIFO is full */
+ tickstart = LL_GetTick();
+
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Enable Receive DMA func */
+ __LL_I2C_RxDMA_En(Instance);
+ /* DMA work */
+ LL_DMA_Start_IT(DMA, frame->dma_rx_ch, (uint32_t)&Instance->DCMD, (uint32_t)frame->buf, frame->buf_len);
+ frame->RXdma_status = IIC_DMA_STATE_BUSY;
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL SMBUS Master Write by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame Write frame pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SMBUS_MasterWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->Instance = Instance;
+ frame->TXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_TXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_TXCHErrorCallBck;
+
+ /* Wait until ReadReq flag is set */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_tx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ frame->TXdma_status = IIC_DMA_STATE_READY;
+
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send Smbus Command
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->command & 0xffUL));
+
+ /* Enable Transmit DMA func */
+ __LL_I2C_TxDMA_En(Instance);
+ /* DMA work */
+ LL_DMA_Start_IT(DMA, frame->dma_tx_ch, (uint32_t)frame->buf, (uint32_t)&Instance->DCMD, frame->buf_len - 1);
+ frame->TXdma_status = IIC_DMA_STATE_BUSY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL SMBUS Master Write by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame Read frame pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SMBUS_MasterRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t clk_cmd = I2C_CMD_READ;
+ DMA_UserCfgTypeDef dma_masterclk_cfg;
+ frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+ frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->Instance = Instance;
+ frame->TXdma_status = IIC_DMA_STATE_RESET;
+ frame->RXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_RXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_RXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_rx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_rx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ frame->TXdma_status = IIC_DMA_STATE_READY;
+ /* Need a DMA chanl send clock singal to Keep communication with slave */
+ dma_masterclk_cfg.trans_type = DMA_TRANS_TYPE_M2P;
+ dma_masterclk_cfg.src_addr_mode = DMA_SRC_ADDR_MODE_FIX;
+ dma_masterclk_cfg.dst_addr_mode = DMA_DST_ADDR_MODE_FIX;
+ dma_masterclk_cfg.src_data_width = DMA_SRC_TRANS_WIDTH_16b;
+ dma_masterclk_cfg.dst_data_width = DMA_DST_TRANS_WIDTH_16b;
+ dma_masterclk_cfg.src_hs_ifc = DMA_SRC_HANDSHAKE_IFC_MEMORY;
+
+ if (Instance == I2C0) {
+ dma_masterclk_cfg.dst_hs_ifc = DMA_DST_HANDSHAKE_IFC_I2C0_TX;
+ } else {
+ dma_masterclk_cfg.dst_hs_ifc = DMA_DST_HANDSHAKE_IFC_I2C1_TX;
+ }
+
+ dma_masterclk_cfg.end_arg = (void *)frame;
+ dma_masterclk_cfg.end_callback = LL_I2C_DMA_TXCHEndCallback;
+ dma_masterclk_cfg.err_arg = (void *)frame;
+ dma_masterclk_cfg.err_callback = LL_I2C_DMA_TXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_tx_ch = LL_I2C_DMA_Init(&dma_masterclk_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ frame->RXdma_status = IIC_DMA_STATE_READY;
+ //TAR config
+ __LL_I2C_TAR_Set(Instance, frame->target_addr);
+
+ //start and send Smbus command
+ __LL_I2C_Timing_RestartAddr8b(Instance, (frame->command & 0xffUL));
+
+ /* Enable Transmit/Receive DMA func */
+ __LL_I2C_RxDMA_En(Instance);
+ __LL_I2C_TxDMA_En(Instance);
+
+ if (frame->buf_len == 1) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ //start+TAR, read, then stop
+ __LL_I2C_Timing_RestartReadStop(Instance);
+
+ /* Get the last data */
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance));
+
+ *(frame->buf + frame->buf_len - 1) = __LL_I2C_DAT_Read(Instance);
+
+ /* wait for last data sent */
+ while (!__LL_I2C_IsStopDet_Raw(Instance));
+
+ } else {
+ //start+TAR, read
+ __LL_I2C_Timing_RestartRead(Instance);
+ /* Indicates how many clk needs to be sent */
+ frame->clk_cnt = frame->buf_len - 1;
+
+ /* Master should sent clk to Keep communication with slave,and READ_CMD is U16,means U8 Multiply 2,
+ The first data has not save yet,but the clock has been sent. And the last read command need sent
+ with Stop Command,so that the length of ch1 is 2*(buf_len -2),and chn0 is buf_len */
+ LL_DMA_Start_IT(DMA, frame->dma_tx_ch, (uint32_t)&clk_cmd, (uint32_t)&Instance->DCMD, 2 * (frame->buf_len - 2));
+ LL_DMA_Start_IT(DMA, frame->dma_rx_ch, (uint32_t)&Instance->DCMD, (uint32_t)frame->buf, frame->buf_len);
+ frame->TXdma_status = IIC_DMA_STATE_BUSY;
+ frame->RXdma_status = IIC_DMA_STATE_BUSY;
+ }
+
+ /* Return Status */
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL Slave Write by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ @param Timeout Limited operation time
+ @note The first command received by the slave is the command sent by the master, not the actual information
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->Instance = Instance;
+ frame->TXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_TXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_TXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_tx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Wait until ReadReq flag is set */
+ tickstart = LL_GetTick();
+
+ /* Make sure slave readreq flag is set, it can't be clear when transmit by DMA */
+ while (!__LL_I2C_SLV_IsReadReq_Raw(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Enable Transmit DMA func */
+ __LL_I2C_TxDMA_En(Instance);
+
+ /* DMA work */
+ LL_DMA_Start_IT(DMA, frame->dma_tx_ch, (uint32_t)frame->buf, (uint32_t)&Instance->DCMD, frame->buf_len);
+ frame->TXdma_status = IIC_DMA_STATE_BUSY;
+ /* Return Status */
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C LL SMBUS Slave Read by DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame Wrute frame pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveRead_DMA(I2C_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ I2C_FrameTypeDef *frame, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+ /* Check the I2C initiation struct allocation */
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if ((frame->buf == NULL) || (frame->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ frame->Instance = Instance;
+ frame->RXdma_status = IIC_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)frame;
+ dma_user_cfg->end_callback = LL_I2C_DMA_TXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)frame;
+ dma_user_cfg->err_callback = LL_I2C_DMA_TXCHErrorCallBck;
+
+ /* Wait for DMA chn init successful */
+ tickstart = LL_GetTick();
+
+ while (frame->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ frame->dma_tx_ch = LL_I2C_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Wait until ReadReq flag is set */
+ tickstart = LL_GetTick();
+
+ while (!__LL_I2C_SLV_IsReadReq_Raw(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* I2C Slave Read Request Interrupt Status Clear */
+ __LL_I2C_SLV_ReadReqRawIntSta_Clr(Instance);
+
+ /* Enable Receive DMA func */
+ __LL_I2C_RxDMA_En(Instance);
+ /* DMA work */
+ LL_DMA_Start_IT(DMA, frame->dma_rx_ch, (uint32_t)&Instance->DCMD, (uint32_t)frame->buf, frame->buf_len);
+ frame->RXdma_status = IIC_DMA_STATE_BUSY;
+
+ /* Return Status */
+ return LL_OK;
+}
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_Exported_Functions_Group3 Interrupt handler and call back
+ * @brief Interrupt handler and call back
+ * @{
+ */
+
+/**
+ * @brief I2C IRQ Handler
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+void LL_I2C_IRQHandler(I2C_TypeDef *Instance, I2C_FrameTypeDef *irq_frame)
+{
+ uint32_t i2c_int_sta = __LL_I2C_IntSta_Get(Instance);
+
+ if (i2c_int_sta & I2C_SCL_STK_AT_LOW_INT_STA_Msk) {
+ LL_I2C_SCLStuckAtLowCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_MST_ON_HOLD_INT_STA_Msk) {
+ LL_I2C_MstOnHoldCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_RESTART_DET_INT_STA_Msk) {
+ LL_I2C_SlvRestartDetCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_GEN_CALL_INT_STA_Msk) {
+ __LL_I2C_SLV_GenCallRawIntSta_Clr(Instance);
+ LL_I2C_SlvGenCallCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_START_DET_INT_STA_Msk) {
+ __LL_I2C_StartDetRawIntSta_Clr(Instance);
+ LL_I2C_StartDetCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_STOP_DET_INT_STA_Msk) {
+ __LL_I2C_StopDetRawIntSta_Clr(Instance);
+ LL_I2C_StopDetCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_ACTIVITY_INT_STA_Msk) {
+ __LL_I2C_ActivityRawIntSta_Clr(Instance);
+ LL_I2C_ActivityCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_RX_DONE_INT_STA_Msk) {
+ __LL_I2C_SLV_RxDoneRawIntSta_Clr(Instance);
+ LL_I2C_SlvRxDoneCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_TX_ABRT_INT_STA_Msk) {
+ __LL_I2C_TxAbortRawIntSta_Clr(Instance);
+ LL_I2C_TxAbortCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_RD_REQ_INT_STA_Msk) {
+ __LL_I2C_SLV_ReadReqRawIntSta_Clr(Instance);
+
+ if ((irq_frame != NULL) && (irq_frame->buf_len != NULL)) {
+
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ __LL_I2C_DAT_Write(Instance, *irq_frame->buf++);
+ irq_frame->XferCount--;
+
+ if (irq_frame->XferCount == 0x0UL) {
+ /* I2C Slave Read Request Interrupt Disable */
+ __LL_I2C_SLV_ReadReq_INT_Dis(Instance);
+ irq_frame->buf = NULL;
+ }
+
+ }
+
+ LL_I2C_SlvReadReqCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_TX_EMPTY_INT_STA_Msk) {
+ //Auto clear according to TXFIFO status
+ if ((irq_frame != NULL) && (irq_frame->buf_len != NULL)) {
+ //wait TXFIFO not full
+ while (!__LL_I2C_IsTxFIFONotFull(Instance));
+
+ if (irq_frame->clk_cnt == 0x0UL) {
+ /* Write data to DCMD */
+ __LL_I2C_DAT_Write(Instance, *irq_frame->buf++);
+
+ irq_frame->XferCount--;
+
+ /* wait for transmit finish by interrupt */
+ if (irq_frame->XferCount == 0x0UL) {
+ __LL_I2C_Timing_WriteStop(Instance, *irq_frame->buf);
+ /* I2C TX Empty Interrupt Disable */
+ __LL_I2C_TxEmpty_INT_Dis(Instance);
+ irq_frame->buf = NULL;
+ }
+ } else {
+ //Read, send the read signal actually acts as ii_clk
+ __LL_I2C_Timing_Read(Instance);
+ irq_frame->clk_cnt --;
+
+ if (irq_frame->clk_cnt == 0) {
+ //read last byte, then stop
+ __LL_I2C_Timing_ReadStop(Instance);
+ /* I2C TX Empty Interrupt Disable */
+ __LL_I2C_TxEmpty_INT_Dis(Instance);
+
+ }
+ }
+ }
+
+ LL_I2C_TxEmptyCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_TX_OVER_INT_STA_Msk) {
+ __LL_I2C_TxOverRawIntSta_Clr(Instance);
+ LL_I2C_TxOverCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_RX_FULL_INT_STA_Msk) {
+ //Auto clear according to RXFIFO status
+ if ((irq_frame != NULL) && (irq_frame->buf_len != NULL)) {
+ /* wait RXFIFO not empty */
+ while (!__LL_I2C_IsRxFIFONotEmpty(Instance));
+
+ /* Read data from DCMD */
+ *irq_frame->buf++ = __LL_I2C_DAT_Read(Instance);
+ irq_frame->XferCount--;
+
+ if (irq_frame->XferCount == 0) {
+ /* I2C RX Full Interrupt Disable */
+ __LL_I2C_RxFull_INT_Dis(Instance);
+ irq_frame->buf = NULL;
+ }
+ }
+
+ LL_I2C_RxFullCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_RX_OVER_INT_STA_Msk) {
+ __LL_I2C_RxOverRawIntSta_Clr(Instance);
+ LL_I2C_RxOverCallback(Instance);
+ }
+
+ if (i2c_int_sta & I2C_RX_UNDER_INT_STA_Msk) {
+ __LL_I2C_RxUnderRawIntSta_Clr(Instance);
+ LL_I2C_RxUnderCallback(Instance);
+ }
+
+ if (__LL_I2C_SMBUS_IsMstClkExtendTimeout(Instance)) {
+ __LL_I2C_SMBUS_MstClkExtendTimeoutRawIntSta_Clr(Instance);
+ LL_SMBUS_MstClkExtTimeoutCallback(Instance);
+ }
+
+ if (__LL_I2C_SMBUS_IsSlvClkExtendTimeout(Instance)) {
+ __LL_I2C_SMBUS_SlvClkExtendTimeoutRawIntSta_Clr(Instance);
+ LL_SMBUS_SlvClkExtTimeoutCallback(Instance);
+ }
+}
+
+/**
+ * @brief I2C SCL stuck at low interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SCLStuckAtLowCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SCLStuckAtLowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C master on hold interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MstOnHoldCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MstOnHoldCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C slave restart detect interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SlvRestartDetCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SlvRestartDetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C slave genaral call interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SlvGenCallCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SlvGenCallCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C start detect interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_StartDetCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_StartDetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C stop detect interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_StopDetCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_StopDetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C activity interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_ActivityCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_ActivityCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C slave rx done interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SlvRxDoneCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SlvRxDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C tx abort interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_TxAbortCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_TxAbortCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C slave read request interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SlvReadReqCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SlvReadReqCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C tx empty interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_TxEmptyCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_TxEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C tx over interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_TxOverCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_TxOverCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C rx full interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxFullCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C rx over interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxOverCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxOverCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C rx under interrupt callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxUnderCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxUnderCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @brief SMBUS SlvClkExtendTimeout Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_SMBUS_SlvClkExtTimeoutCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SMBUS_SlvClkExtTimeoutCallback could be implemented in the user file
+ */
+
+}
+
+/**
+ * @brief SMBUS MstClkExtendTimeout Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_SMBUS_MstClkExtTimeoutCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SMBUS_MstClkExtTimeoutCallback could be implemented in the user file
+ */
+
+}
+
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Functions I2C LL Private function
+ * @brief I2C LL Private function
+ * @{
+ */
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief I2C LL DMA Init
+ * @param dma_user_cfg user dma config pointer
+ * @param Timeout Limited operation time
+ * @return DMA_ChannelETypeDef
+ */
+static DMA_ChannelETypeDef LL_I2C_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg)
+{
+ DMA_ChannelETypeDef ch = DMA_CHANNEL_INVALID;
+ int ret;
+
+ /* User DAM channel request */
+ ch = LL_DMA_ChannelRequest();
+
+ if (ch == DMA_CHANNEL_INVALID) {
+ LOG_E("Requset DMA channel Fail!\n");
+ return DMA_CHANNEL_INVALID;
+ }
+
+ /* User DMA init */
+ ret = LL_DMA_Init(DMA, ch, dma_user_cfg);
+
+ if (ret) {
+ LOG_E("DMA LL init fail!\n");
+ LL_DMA_ChannelRelease(ch);
+ ch = DMA_CHANNEL_INVALID;
+ return DMA_CHANNEL_INVALID;
+ }
+
+ return ch;
+}
+
+
+/**
+ * @brief I2C LL DMA Deinit
+ * @param Instance Specifies I2C peripheral
+ * @param frame frame pointer
+ * @return LL_StatusETypeDef
+ */
+static LL_StatusETypeDef LL_I2C_DMA_Deinit(DMA_ChannelETypeDef ch)
+{
+ /* DMA stop work */
+ LL_DMA_Stop_IT(DMA, ch);
+
+ /* Deinit DMA after tranfer completed */
+ LL_DMA_DeInit(DMA, ch);
+
+ /* DMA LL channel release */
+ LL_DMA_ChannelRelease(ch);
+
+ return LL_OK;
+}
+
+
+/**
+ * @brief I2C DMA TX Channel complete callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+static void LL_I2C_DMA_TXCHEndCallback(void *arg)
+{
+ I2C_FrameTypeDef *p_frame = ((I2C_FrameTypeDef *)arg);
+
+ /* The last frame of the Master needs to be sent with stop */
+ if (__LL_I2C_IsMasterMode(p_frame->Instance) == ENABLE) {
+ if (p_frame->clk_cnt != 0) {
+ __LL_I2C_Timing_ReadStop(p_frame->Instance);
+ } else {
+ __LL_I2C_Timing_WriteStop(p_frame->Instance, *(p_frame->buf + p_frame->buf_len - 1));
+ }
+
+ /* wait for last data sent */
+ while (!__LL_I2C_IsStopDet_Raw(p_frame->Instance));
+ } else {
+ /* Clear ReadReqRaw Status*/
+ __LL_I2C_SLV_ReadReqRawIntSta_Clr(p_frame->Instance);
+ p_frame->clk_cnt = 0;
+
+ /* wait for last data sent */
+ while (!__LL_I2C_MST_IsOnHold_Raw(p_frame->Instance));
+ }
+
+ /* I2C LL DMA Deinit */
+ LL_I2C_DMA_Deinit(p_frame->dma_tx_ch);
+
+ /* Disable Transmit DMA func */
+ p_frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been finished */
+ p_frame->TXdma_status = IIC_DMA_STATE_FINISH;
+
+ /* Disable Transmit DMA func */
+ __LL_I2C_TxDMA_Dis(p_frame->Instance);
+}
+
+/**
+ * @brief I2C DMA RX Channel complete callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+static void LL_I2C_DMA_RXCHEndCallback(void *arg)
+{
+ I2C_FrameTypeDef *p_frame = ((I2C_FrameTypeDef *)arg);
+
+ /* wait for last data sent */
+ while (!__LL_I2C_IsStopDet_Raw(p_frame->Instance));
+
+ /* I2C LL DMA Deinit */
+ LL_I2C_DMA_Deinit(p_frame->dma_rx_ch);
+
+ p_frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been finished */
+ p_frame->RXdma_status = IIC_DMA_STATE_FINISH;
+
+ /* Disable Receive DMA func */
+ __LL_I2C_RxDMA_Dis(p_frame->Instance);
+
+}
+
+/**
+ * @brief I2C DMA TX Channel Error callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+static void LL_I2C_DMA_TXCHErrorCallBck(void *arg)
+{
+ I2C_FrameTypeDef *p_frame = ((I2C_FrameTypeDef *)arg);
+
+ /* I2C LL DMA Deinit */
+ LL_I2C_DMA_Deinit(p_frame->dma_tx_ch);
+ p_frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been Error */
+ p_frame->TXdma_status = IIC_DMA_STATE_ERROR;
+
+ /* Disable Transmit DMA func */
+ __LL_I2C_TxDMA_Dis(p_frame->Instance);
+}
+
+/**
+ * @brief I2C DMA RX Channel Error callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+static void LL_I2C_DMA_RXCHErrorCallBck(void *arg)
+{
+ I2C_FrameTypeDef *p_frame = ((I2C_FrameTypeDef *)arg);
+
+ /* I2C LL DMA Deinit */
+ LL_I2C_DMA_Deinit(p_frame->dma_rx_ch);
+ p_frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been Error */
+ p_frame->RXdma_status = IIC_DMA_STATE_ERROR;
+
+ /* Disable Transmit DMA func */
+ __LL_I2C_RxDMA_Dis(p_frame->Instance);
+}
+
+
+#endif /*!< LL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+
+#endif /* LL_I2C_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iir.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iir.c
new file mode 100644
index 0000000000..87ddf1beaf
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iir.c
@@ -0,0 +1,428 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_iir.c
+ * @author MCD Application Team
+ * @brief IIR LL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IIR peripheral:
+ * + Initialization and De-Initialization functions
+ * + Start and Stop functions
+ * + Get output data function
+ * + Reset internal buffer function
+ * + Interrupt and Callback functions
+
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "IIR LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup IIR_LL IIR LL
+ * @brief IIR LL module driver
+ * @{
+ */
+
+#ifdef LL_IIR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IIR_LL_Exported_functions IIR LL Exported functions
+ * @brief IIR LL Exported functions
+ * @{
+ */
+
+/** @defgroup IIR_LL_Exported_Functions_Group1 Initialization and De-Initialization functions
+ * @brief Initialization and De-Initialization functions
+@verbatim
+ ===============================================================================
+ ##### Initialization and De-Initialization functions #####
+ ===============================================================================
+ [..] This section provides a set of functions allowing to initialize and
+ deinitialize the IIR peripheral
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the IIR peripheral.
+ * @param Instance Specifies IIR peripheral.
+ * @param Init pointer to a IIR_InitTypeDef structure that contains the
+ * configuration information for the specified IIR peripheral.
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_IIR_Init(IIR_TypeDef *Instance, IIR_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+
+ /* Handle Something */
+ LL_IIR_MspInit(Instance);
+
+ /* IIRx_CR0 Configure : IIR Order select, Internal buffer reset and
+ enable IIR peripheral */
+ WRITE_REG(Instance->CR0, (Init->Order | Init->BufferReset));
+
+ /* Enable the IIR peripheral */
+ __LL_IIR_ENABLE(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief De-initializes the IIR peripheral registers to their default reset values.
+ * @param IIRx where x can be (0, 1, ...) to select the IIR peripheral.
+ * @retval status of the de-initialization
+ */
+LL_StatusETypeDef LL_IIR_DeInit(IIR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+
+ /* Disable IIR */
+ __LL_IIR_DISABLE(Instance);
+
+ /* Handle Something */
+ LL_IIR_MspDeInit(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the IIR MSP.
+ * @param Instance IIR peripheral
+ * @return None
+ */
+__WEAK void LL_IIR_MspInit(IIR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_IIR_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the IIR MSP
+ * @param Instance IIR peripheral
+ * @return None
+ */
+__WEAK void LL_IIR_MspDeInit(IIR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_IIR_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup IIR_LL_Exported_Functions_Group2 IIR Peripheral Control functions
+ * @brief IIR Peripheral Control functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the IIR control registers
+ (+) Configure the IIR preload control registers
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the IIR filter
+ * @param Instance IIR peripheral.
+ * @param Config pointer to a IIR_ConfigTypeDef structure that contains
+ * the configuration information for the specified IIR peripheral.
+ * @return status of the configuration
+ */
+LL_StatusETypeDef LL_IIR_FilterConfig(IIR_TypeDef *Instance, IIR_ConfigTypeDef *Config)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+ assert_param(IS_IIR_INPUT_DATA_SCALE(Config->InDataScale));
+ assert_param(IS_IIR_OUTPUT_DATA_SCALE(Config->OutDataScale));
+ assert_param(IS_IIR_FEEDBACK_SCALE(Config->FeedBackScale));
+
+ /* IIR Scale configure : Output data scale, Input data scale and Feedback scale */
+ WRITE_REG(Instance->SCALR, (((uint32_t)(Config->InDataScale << IIR_SCALR_DISCAL_Pos)) |
+ ((uint32_t)(Config->FeedBackScale << IIR_SCALR_FBSCAL_Pos)) |
+ ((uint32_t)(Config->OutDataScale << IIR_SCALR_DOSCAL_Pos))));
+
+ /* IIR Data Input Address */
+ WRITE_REG(Instance->DIAR, Config->InDataAddress);
+
+ /* fill the coefficients */
+ for (int idx = 0; idx < ARRAY_SIZE(Config->AxCOEF); idx++) {
+ WRITE_REG(Instance->AxCOEFR[idx], ((uint32_t)(Config->AxCOEF[idx]) & IIR_AxCOEFR_AxCOEF_Msk));
+ }
+
+ for (int idx = 0; idx < ARRAY_SIZE(Config->BxCOEF); idx++) {
+ WRITE_REG(Instance->BxCOEFR[idx], ((uint32_t)(Config->BxCOEF[idx]) & IIR_BxCOEFR_BxCOEF_Msk));
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Configures the IIR filter preload registers
+ * @note This function is related to IIR Auto-Reload feature.
+ * Using __LL_IIR_AUTORELAOD_ENABLE() will auto-reload this configures.
+ * Using LL_IIR_FilterStart[_IT]() will auto-reload this configures(with AutoReload enabled) then start an IIR filter.
+ * @param Instance IIR peripheral.
+ * @param Config pointer to a IIR_ConfigTypeDef structure that contains
+ * the configuration information for the specified IIR peripheral.
+ * @return status of the configuration
+ */
+LL_StatusETypeDef LL_IIR_FilterConfig_Preload(IIR_TypeDef *Instance, IIR_ConfigTypeDef *Config)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+ assert_param(IS_IIR_INPUT_DATA_SCALE(Config->InDataScale));
+ assert_param(IS_IIR_OUTPUT_DATA_SCALE(Config->OutDataScale));
+ assert_param(IS_IIR_FEEDBACK_SCALE(Config->FeedBackScale));
+
+ /* IIR Scale configure : Output data scale, Input data scale and Feedback scale */
+ WRITE_REG(Instance->SCALSR, (((uint32_t)(Config->InDataScale << IIR_SCALSR_DISCALS_Pos)) |
+ ((uint32_t)(Config->FeedBackScale << IIR_SCALSR_FBSCALS_Pos)) |
+ ((uint32_t)(Config->OutDataScale << IIR_SCALSR_DOSCALS_Pos))));
+
+ /* IIR Data Input Address */
+ WRITE_REG(Instance->DIASR, Config->InDataAddress);
+
+ /* fill the coefficients */
+ for (int idx = 0; idx < ARRAY_SIZE(Config->AxCOEF); idx++) {
+ WRITE_REG(Instance->AxCOEFSR[idx], ((uint32_t)(Config->AxCOEF[idx]) & IIR_AxCOEFSR_AxCOEFS_Msk));
+ }
+
+ for (int idx = 0; idx < ARRAY_SIZE(Config->BxCOEF); idx++) {
+ WRITE_REG(Instance->BxCOEFSR[idx], ((uint32_t)(Config->BxCOEF[idx]) & IIR_BxCOEFSR_BxCOEFS_Msk));
+ }
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup IIR_LL_Exported_Functions_Group3 IIR Input and Output operation functions
+ * @brief IIR Input and Output operation functions
+@verbatim
+ ===============================================================================
+ ##### Input and Output operation functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) start and stop functions.
+ (+) start and stop with interrupt functions.
+ (+) get output data function.
+ (+) reset internal buffer function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start an IIR Filter for current input data
+ * @param Instance IIR peripheral.
+ * @param AutoReload specifies IIR Auto-Reload the preloaded configures or not.
+ * This parameter can be one of the following values:
+ * @arg IIR_AUTORELOAD_DISABLE: Disable Auto-Reload feature.
+ * @arg IIR_AUTORELOAD_ENABLE: Auto-Reload the preload configures before starting IIR filter.
+ * @note The preloaded configures should be configured by calling LL_IIR_FilterConfig_Preload() function,
+ * before enable Auto-Reload feature.
+ * @return LL status
+ */
+LL_StatusETypeDef LL_IIR_FilterStart(IIR_TypeDef *Instance, IIR_ATReloadETypeDef AutoReload)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+
+ /* Configure the Auto-Reload feature before start the IIR filter */
+ if (AutoReload != IIR_AUTORELOAD_DISABLE) {
+ __LL_IIR_AUTORELOAD_ENABLE(Instance);
+ }
+
+ /* Start the IIR filter */
+ __LL_IIR_FILTER_START(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Start an IIR Filter for current input data with interrupt
+ * @param Instance IIR peripheral.
+ * @param AutoReload specifies IIR Auto-Reload the preloaded configures or not.
+ * This parameter can be one of the following values:
+ * @arg IIR_AUTORELOAD_DISABLE: Disable Auto-Reload feature.
+ * @arg IIR_AUTORELOAD_ENABLE: Auto-Reload the preload configures before starting IIR filter.
+ * @note The preloaded configures should be configured by calling LL_IIR_FilterConfig_Preload() function,
+ * before enable Auto-Reload feature
+ * @return LL status
+ */
+LL_StatusETypeDef LL_IIR_FilterStart_IT(IIR_TypeDef *Instance, IIR_ATReloadETypeDef AutoReload)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+
+ /* Enable IIR interrupt */
+ __LL_IIR_ENABLE_IT(Instance, IIR_IT_FDIE);
+
+ /* Configure the Auto-Reload feature before start the IIR filter */
+ if (AutoReload != IIR_AUTORELOAD_DISABLE) {
+ __LL_IIR_AUTORELOAD_ENABLE(Instance);
+ }
+
+ /* Start the IIR filter */
+ __LL_IIR_FILTER_START(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Get the latest IIR filter output data
+ * @param Instance IIR peripheral.
+ * @return IIR filter output data
+ */
+int16_t LL_IIR_FilterDataGet(IIR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+
+ /* Return the IIR filter output data */
+ return (int16_t)(READ_REG(Instance->DOR) & 0xFFFFUL);
+}
+
+/**
+ * @brief Reset the IIR internal data buffer.
+ * @param Instance IIR peripheral.
+ * @return LL status
+ */
+LL_StatusETypeDef LL_IIR_FilterBufferReset(IIR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+
+ /* IIR Internal Buffer Reset control */
+ __LL_IIR_FILTER_BUFFER_RESET(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup IIR_LL_Exported_Functions_Interrupt IIR Initerrupt management
+ * @brief IIR Initerrupt management
+@verbatim
+ ===============================================================================
+ ##### Initerrupt management #####
+ ===============================================================================
+ [..]
+ This section provides IIR interrupt handler and callback functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles IIR interrupts requests.
+ * @param Instance IIR peripheral
+ * @return None
+ */
+void LL_IIR_IRQHandler(IIR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_IIR_ALL_INSTANCE(Instance));
+
+ if ((__LL_IIR_IT_CHECK_SOURCE(Instance, IIR_IT_FDIE) != RESET) && (__LL_IIR_GET_FLAG(Instance, IIR_FLAG_FDIF) != RESET)) {
+ /* Clear the FDIF interrupt flag */
+ __LL_IIR_CLEAR_FLAG(Instance, IIR_FLAG_FDIF);
+
+ /* IIR Fliter done callback */
+ LL_IIR_FilterDoneCallBack(Instance);
+ }
+}
+/**
+ * @brief IIR Fliter done callback
+ * @param Instance IIR peripheral
+ * @return None
+ */
+__WEAK void LL_IIR_FilterDoneCallBack(IIR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_IIR_FilterDoneCallBack could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_GPIO_MODULE_ENABLE */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iwdg.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iwdg.c
new file mode 100644
index 0000000000..c42be7d7ec
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iwdg.c
@@ -0,0 +1,329 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_iwdg.c
+ * @author MCD Application Team
+ * @brief IWDG LL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and De-Initialization functions
+ * + Refresh function
+ * + Interrupt and Callback functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "IWDG LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG_LL IWDG LL
+ * @brief IWDG LL module driver.
+ * @{
+ */
+
+#ifdef LL_IWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Defines IWDG LL Private Defines
+ * @brief IWDG LL Private Defines
+ * @{
+ */
+
+/**
+ * @brief Max delay time for IWDG status register update
+ */
+#define IWDG_TIMEOUT_VALUE 100U
+/**
+ * @}
+ */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG LL Exported Functions
+ * @brief IWDG LL Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_LL_Exported_Functions_Group1 Initialization and De-Initialization functions
+ * @brief Initialization and De-Initialization functions
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides a set of functions allowing to initialize and
+ deinitialize the IWDG peripheral
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the IWDG peripheral according to the specified parameters in the Init.
+ * @param Instance IWDG peripheral instance
+ * @param Init pointer to a IWDG_InitTypeDef structure that contains the configuration information
+ * for the specified IWDG peripheral.
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_IWDG_Init(IWDG_TypeDef *Instance, IWDG_InitTypeDef *Init)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the IWDG initiation struct allocation */
+ if (Init == NULL) {
+ return LL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(Instance));
+ assert_param(IS_IWDG_RELOAD_Val(Init->Reload_val));
+
+ /* Handle Something */
+ LL_IWDG_MspInit(Instance);
+
+ /* Start IWDG to work */
+ __LL_IWDG_START(Instance);
+
+ /* Enable write access to IWDG_PSCR, IWDG_RLR and IWDG_CR registers */
+ __LL_IWDG_ENABLE_WRITE_ACCESS(Instance);
+
+ /* PSCUPD must be 0 before writting prescaler settings to IWDG_PSCR register */
+ tickstart = LL_GetTick();
+
+ while (__LL_IWDG_GET_FLAG(Instance, IWDG_FLAG_PSCUPD) != RESET) {
+ if ((LL_GetTick() - tickstart) > IWDG_TIMEOUT_VALUE) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Write to IWDG registers the Prescaler to work with */
+ WRITE_REG(Instance->PSCR, Init->Prescaler);
+
+ /* RLVUPD must be 0 before writting reload values to IWDG_RLR register */
+ tickstart = LL_GetTick();
+
+ while (__LL_IWDG_GET_FLAG(Instance, IWDG_FLAG_RLVUPD) != RESET) {
+ if ((LL_GetTick() - tickstart) > IWDG_TIMEOUT_VALUE) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Write to IWDG registers the Reload values to work with */
+ WRITE_REG(Instance->RLR, Init->Reload_val);
+
+ /* Configure the IWDG bahavior after timeout */
+ MODIFY_REG(Instance->CR, IWDG_CR_MODE, Init->Mode);
+
+ /* Enable IWDG interrupt when using interrupt mode */
+ if (Init->Mode == IWDG_MODE_INTERRUPT) {
+ __LL_IWDG_ENABLE_IT(Instance, IWDG_IT_TOIE);
+ }
+
+ /* Disable write access to IWDG_PSCR, IWDG_RLR and IWDG_CR registers */
+ __LL_IWDG_DISABLE_WRITE_ACCESS(Instance);
+
+ /* Reload IWDG counter with value defined in the reload register */
+ __LL_IWDG_RELOAD_COUNTER(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief De-initializes the IWDG peripheral.
+ * @param Instance IWDG peripheral
+ * @return status of the de-initialization
+ */
+LL_StatusETypeDef LL_IWDG_DeInit(IWDG_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(Instance));
+
+ /* Enable write access to IWDG_PSCR, IWDG_RLR and IWDG_CR registers */
+ __LL_IWDG_ENABLE_WRITE_ACCESS(Instance);
+
+ /* Disable the IWDG peripheral. */
+ __LL_IWDG_STOP(Instance);
+
+ /* Disable write access to IWDG_PSCR, IWDG_RLR and IWDG_CR registers */
+ __LL_IWDG_DISABLE_WRITE_ACCESS(Instance);
+
+ /* Handle Something */
+ LL_IWDG_MspDeInit(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the IWDG MSP.
+ * @param Instance IWDG peripheral
+ * @return None
+ */
+__WEAK void LL_IWDG_MspInit(IWDG_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_IWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the IWDG MSP
+ * @param Instance IWDG peripheral
+ * @return None
+ */
+__WEAK void LL_IWDG_MspDeInit(IWDG_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_IWDG_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup IWDG_LL_Exported_Functions_Group2 IWDG Input and Output operation functions
+ * @brief IWDG Input and Output operation functions
+@verbatim
+ ===============================================================================
+ ##### Input and Output operation functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the IWDG.
+ * @param Instance: IWDG peripheral
+ * @return LL_Status
+ */
+LL_StatusETypeDef LL_IWDG_Refresh(IWDG_TypeDef *Instance)
+{
+ uint32_t tickstart = 0;
+ /* Check the parameters */
+ assert_param(IS_IWDG_ALL_INSTANCE(Instance));
+
+ /* Notice that RLVUPD and PSCUPD must be 0 before refreshing IWDG counter */
+ while ((__LL_IWDG_GET_FLAG(Instance, IWDG_FLAG_RLVUPD) != RESET) || (__LL_IWDG_GET_FLAG(Instance, IWDG_FLAG_PSCUPD) != RESET)) {
+ if ((LL_GetTick() - tickstart) > IWDG_TIMEOUT_VALUE) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ /* Reload IWDG counter with value defined in the IWDG_RLR register */
+ __LL_IWDG_RELOAD_COUNTER(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup IWDG_LL_Exported_Functions_Interrupt IWDG Initerrupt management
+ * @brief IWDG Initerrupt management
+@verbatim
+ ===============================================================================
+ ##### Initerrupt management #####
+ ===============================================================================
+ [..]
+ This section provides IWDG interrupt handler and callback functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles IWDG interrupts requests.
+ * @param Instance: IWDG peripheral
+ * @return None
+ */
+void LL_IWDG_IRQHandler(IWDG_TypeDef *Instance)
+{
+ if ((__LL_IWDG_IT_CHECK_SOURCE(Instance, IWDG_IT_TOIE) != RESET) && (__LL_IWDG_GET_FLAG(Instance, IWDG_FLAG_TOIF) != RESET)) {
+ /* Clear the TOIF interrupt flag */
+ __LL_IWDG_CLEAR_FLAG(Instance, IWDG_FLAG_TOIF);
+
+ /* IWDG timeout callback */
+ LL_IWDG_TimeOutCallBack(Instance);
+ }
+}
+
+/**
+ * @brief Timeout callback
+ * @param Instance IWDG peripheral
+ * @return None
+ */
+__WEAK void LL_IWDG_TimeOutCallBack(IWDG_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_IWDG_TimeOutCallBack could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_IWDG_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_lvdctrl.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_lvdctrl.c
new file mode 100644
index 0000000000..6437d49311
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_lvdctrl.c
@@ -0,0 +1,185 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_lvdctrl.c
+ * @author MCD Application Team
+ * @brief LVDCTRL LL Module Driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "LVD"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup LVDCTRL_LL LVDCTRL LL
+ * @brief LVDCTRL LL Module Driver
+ * @{
+ */
+
+#ifdef LL_LVD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LVDCTRL_LL_Exported_Functions LVDCTRL LL Exported Functions
+ * @brief LVDCTRL LL Exported Functions
+ * @{
+ */
+
+/** @defgroup LVDCTRL_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the LVD peripheral
+ * @param Instance Specifies LVD peripheral
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_LVD_Init(LVD_TypeDef *Instance)
+{
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_LVD_MspInit(Instance);
+
+ //Enable LVD Module according to need
+ __LL_LVDCTRL_VCC_LowVolDet_En(Instance);
+ __LL_LVDCTRL_AVCC_LowVolDet_En(Instance);
+ __LL_LVDCTRL_VDD_OverCurDet_En(Instance);
+ __LL_LVDCTRL_VDD_LowVolDet_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief DeInitializes the LVD peripheral
+ * @param Instance Specifies LVD peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_LVD_DeInit(LVD_TypeDef *Instance)
+{
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_LVD_MspDeInit(Instance);
+
+ //Disable LVD Module according to need
+ __LL_LVDCTRL_VCC_LowVolDet_Dis(Instance);
+ __LL_LVDCTRL_AVCC_LowVolDet_Dis(Instance);
+ __LL_LVDCTRL_VDD_OverCurDet_Dis(Instance);
+ __LL_LVDCTRL_VDD_LowVolDet_Dis(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the LVD MSP
+ * @param Instance Specifies LVD peripheral
+ * @retval None
+ */
+__WEAK void LL_LVD_MspInit(LVD_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_LVD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the LVD MSP
+ * @param Instance Specifies LVD peripheral
+ * @retval None
+ */
+__WEAK void LL_LVD_MspDeInit(LVD_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_LVD_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup LVDCTRL_LL_Exported_Functions_Interrupt LVDCTRL Interrupt Management
+ * @brief LVDCTRL Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief LL LVDCTRL IRQ Handler
+ * @param Instance Specifies LVD peripheral
+ * @retval None
+ */
+void LL_LVD_CtrlIRQHandler(LVD_TypeDef *Instance)
+{
+ if (__LL_LVDCTRL_IsVDDOverCur(Instance)) {
+ LOG_D("VDD Over Current INT.\n");
+ //:TODO: add process code according to need
+ }
+
+ if (__LL_LVDCTRL_IsVDDLowVol(Instance)) {
+ LOG_D("VDD Low Voltage INT.\n");
+ //:TODO: add process code according to need
+ }
+
+ if (__LL_LVDCTRL_IsVCCLowVol(Instance)) {
+ LOG_D("VCC Low Voltage INT.\n");
+ //:TODO: add process code according to need
+ }
+
+ if (__LL_LVDCTRL_IsAVCCLowVol(Instance)) {
+ LOG_D("AVCC Low Voltage INT.\n");
+ //:TODO: add process code according to need
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_LVD_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_sysctrl.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_sysctrl.c
new file mode 100644
index 0000000000..8819f98703
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_sysctrl.c
@@ -0,0 +1,1658 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_sysctrl.c
+ * @author MCD Application Team
+ * @brief SYSCTRL LL Module Driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "SYSCTRL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup SYSCTRL_LL SYSCTRL LL
+ * @brief SYSCTRL LL Module Driver
+ * @{
+ */
+
+
+/* Private define ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup SYSCTRL_LL_Private_Types SYSCTRL LL Private Types
+ * @brief SYSCTRL LL Private Types
+ * @{
+ */
+
+/**
+ * @brief SYSCTRL PLL0/1/2 Config Type Define
+ * @note pll_out_freq is before PLL Post Div
+ */
+typedef struct __SYSCTRL_PLLCfgTypedef {
+ uint32_t pll_in_freq; /*!< PLL Input Freq */
+ uint32_t pll_out_freq; /*!< PLL Output Freq */
+ uint8_t pll_pre_div; /*!< PLL Pre-Div */
+ uint16_t fpll_int; /*!< FPLL Integer */
+ uint16_t fpll_frac; /*!< FPLL Fraction */
+ uint32_t pll_vco_band; /*!< PLL VCO Band */
+ uint32_t pll_vco_gain; /*!< PLL VCO Gain */
+} SYSCTRL_PLLCfgTypedef;
+
+/**
+ * @}
+ */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SYSCTRL_LL_Private_Variables SYSCTRL LL Private Variables
+ * @brief SYSCTRL LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief SYSCLK PLL Config Const Array Definition
+ * @note VCO band&gain config are the same to PLL0/1/2
+ */
+static const SYSCTRL_PLLCfgTypedef sysctrl_pll_cfg[] = {
+ {8000000, 100000000, 1, 6, 0x4000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->100M */
+ {8000000, 110000000, 1, 6, 0xe000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->110M */
+ {8000000, 120000000, 1, 7, 0x8000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->120M */
+ {8000000, 130000000, 1, 8, 0x2000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->130M */
+
+ {8000000, 140000000, 1, 8, 0xc000, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->140M */
+ {8000000, 150000000, 1, 9, 0x6000, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->150M */
+ {8000000, 160000000, 1, 10, 0, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->160M */
+ {8000000, 170000000, 1, 10, 0xa000, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->170M */
+
+ {8000000, 180000000, 1, 11, 0x4000, SYSCTRL_PLL0_BAND_466M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->180M */
+ {8000000, 190000000, 1, 11, 0xe000, SYSCTRL_PLL0_BAND_466M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->190M */
+ {8000000, 200000000, 1, 12, 0x8000, SYSCTRL_PLL0_BAND_466M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->200M */
+
+ {8000000, 210000000, 1, 13, 0x2000, SYSCTRL_PLL0_BAND_520M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->210M */
+ {8000000, 220000000, 1, 13, 0xc000, SYSCTRL_PLL0_BAND_520M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->220M */
+ {8000000, 230000000, 1, 14, 0x6000, SYSCTRL_PLL0_BAND_520M, SYSCTRL_PLL0_GVCO_2}, /*!8M,PLL0Out->230M */
+};
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SYSCTRL_LL_Private_Functions SYSCTRL LL Private Functions
+ * @brief SYSCTRL LL Private Functions
+ * @{
+ */
+static void LL_SYSCTRL_XOSCCfg(SYSCTRL_TypeDef *Instance);
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSCTRL_LL_Exported_Functions SYSCTRL LL Exported Functions
+ * @brief SYSCTRL LL Exported Functions
+ * @{
+ */
+
+/** @defgroup SYSCTRL_LL_Exported_Functions_Group1 SYSCTRL Clock Config Functions
+ * @brief SYSCTRL Clock Config Functions
+ * @{
+ */
+
+/**
+ * @brief SYSCTRL LL SYSCLK Init
+ * @param Instance Specifies SYSCTRL peripheral
+ * @param sysclk_cfg SYSCLK Config Pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_SYSCTRL_SysclkInit(SYSCTRL_TypeDef *Instance, SYSCTRL_SysclkUserCfgTypeDef *sysclk_cfg)
+{
+ uint16_t sysclk_div, remain;
+ SYSCTRL_PLLUserCfgTypeDef pll0_cfg;
+ LL_StatusETypeDef ret = LL_ERROR;
+
+ //Check params to be valid
+ if (Instance == NULL || sysclk_cfg == NULL) {
+ LOG_E("SYSCLK init params error!\n");
+ return LL_ERROR;
+ }
+
+ assert_param(sysclk_cfg->sysclk_freq);
+
+ //Auto Freq Config
+ if (sysclk_cfg->sysclk_src == SYSCLK_SRC_RC32K) { //SYSCLK Source RC32K
+ sysclk_cfg->sysclk_src_freq = LSI_VALUE;
+ } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_RC8M) { //SYSCLK Source RC8M
+ sysclk_cfg->sysclk_src_freq = HSI_VALUE;
+ } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_HOSC) { //SYSCLK Source HOSC
+ if (!sysclk_cfg->sysclk_src_freq) { //Hardware can AutoSwitch
+ sysclk_cfg->sysclk_src_freq = HSE_VALUE;
+ }
+ } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_PLL0DivClk) { //SYSCLK Source PLL0DivClk
+ if (sysclk_cfg->pll0clk_src == PLLCLK_SRC_XOSC) { //PLL0 CLK Source HOSC
+ if (!sysclk_cfg->pll0clk_src_freq) { //Hardware can AutoSwitch
+ sysclk_cfg->pll0clk_src_freq = HSE_VALUE;
+ }
+ } else if (sysclk_cfg->pll0clk_src == PLLCLK_SRC_RC8M) { //PLL0 CLK Source RC8M
+ sysclk_cfg->pll0clk_src_freq = HSI_VALUE;
+ }
+ }
+
+ //Check APB0/APB1 Clock Div to be valid
+ if (sysclk_cfg->apb0_clk_div == SYSCTRL_CLK_DIV_IVD) {
+ sysclk_cfg->apb0_clk_div = SYSCTRL_CLK_DIV_1;
+ }
+
+ if (sysclk_cfg->apb1_clk_div == SYSCTRL_CLK_DIV_IVD) {
+ sysclk_cfg->apb1_clk_div = SYSCTRL_CLK_DIV_1;
+ }
+
+ //Calculate SYSCLK division
+ if (sysclk_cfg->sysclk_src != SYSCLK_SRC_PLL0DivClk) {
+ sysclk_div = sysclk_cfg->sysclk_src_freq / sysclk_cfg->sysclk_freq;
+ remain = sysclk_cfg->sysclk_src_freq % sysclk_cfg->sysclk_freq;
+
+ if (!sysclk_div || remain) {
+ LOG_E("Can't division %d SYSCLK from %d Source CLK!\n", sysclk_cfg->sysclk_freq, sysclk_cfg->sysclk_src_freq);
+ return LL_ERROR;
+ }
+ }
+
+ //SYSCTRL CTRL Register Unlock
+ __LL_SYSCTRL_CTRLReg_Unlock(Instance);
+
+ //Config SYSCLK
+ switch (sysclk_cfg->sysclk_src) {
+ case SYSCLK_SRC_RC32K:
+ LOG_I("SYSCLK-[%d] source select RC32K.\n", sysclk_cfg->sysclk_freq);
+ __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_RC32K);
+ __LL_SYSCTRL_SysClkDiv_Set(Instance, sysclk_div);
+ ret = LL_OK;
+ break;
+
+ case SYSCLK_SRC_RC8M:
+ LOG_I("SYSCLK-[%d] source select RC8M.\n", sysclk_cfg->sysclk_freq);
+ __LL_SYSCTRL_RC8M_En(Instance);
+ __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_RC8M);
+ __LL_SYSCTRL_SysClkDiv_Set(Instance, sysclk_div);
+ ret = LL_OK;
+ break;
+
+ case SYSCLK_SRC_PLL0DivClk:
+ //SYSCLK PLL0 Config
+ pll0_cfg.pll_clk_src = sysclk_cfg->pll0clk_src;
+ pll0_cfg.pll_in_freq = sysclk_cfg->pll0clk_src_freq;
+ pll0_cfg.pll_user_freq = sysclk_cfg->sysclk_freq;
+ ret = LL_SYSCTRL_Pll0Cfg(Instance, &pll0_cfg);
+
+ //SYCTRL CTRL Reg Unlock because Pll0Cfg function has lock before return
+ __LL_SYSCTRL_CTRLReg_Unlock(Instance);
+
+ //SYSCLK Source Select PLL0DivClk, and SYSCLK Div set to default 1
+ if (ret == LL_OK) {
+ LOG_I("SYSCLK-[%d] source select PLL0DivClk.\n", sysclk_cfg->sysclk_freq);
+ __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_PLLDivClk);
+ __LL_SYSCTRL_SysClkDiv_Set(Instance, SYSCTRL_CLK_DIV_1);
+ }
+
+ break;
+
+ case SYSCLK_SRC_HOSC:
+ LOG_I("SYSCLK-[%d] source select HOSC-[%d].\n", sysclk_cfg->sysclk_freq, sysclk_cfg->sysclk_src_freq);
+ LL_SYSCTRL_XOSCCfg(Instance);
+ __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_HOSC);
+ __LL_SYSCTRL_SysClkDiv_Set(Instance, sysclk_div);
+ ret = LL_OK;
+ break;
+
+ default:
+ LOG_E("SYSCLK Source Select-[%d] Error!\n", sysclk_cfg->sysclk_src);
+ ret = LL_ERROR;
+ break;
+ }
+
+ if (ret == LL_OK) {
+ //APB0/APB1 Clock Div Config
+ __LL_SYSCTRL_APB0ClkDiv_Set(Instance, sysclk_cfg->apb0_clk_div);
+ __LL_SYSCTRL_APB1ClkDiv_Set(Instance, sysclk_cfg->apb1_clk_div);
+
+ //APB0/APB1/ABH0 Bus Clock Enable
+ __LL_SYSCTRL_APB0Clk_En(Instance);
+ __LL_SYSCTRL_APB1Clk_En(Instance);
+ __LL_SYSCTRL_AHBClk_En(Instance);
+
+ //APB0/APB1/ABH0 Soft Reset Release
+ __LL_SYSCTRL_APB0BusSoftRst_Release(Instance);
+ __LL_SYSCTRL_APB1BusSoftRst_Release(Instance);
+ __LL_SYSCTRL_AHBBusSoftRst_Release(Instance);
+
+ //RAM2/RAM1/RAM0 Bus Clock Enable
+ __LL_SYSCTRL_RAM2BusClk_En(Instance);
+ __LL_SYSCTRL_RAM1BusClk_En(Instance);
+ __LL_SYSCTRL_RAM0BusClk_En(Instance);
+ }
+
+ //SYSCTRL Register Lock
+ __LL_SYSCTRL_Reg_Lock(Instance);
+
+ return ret;
+}
+
+/**
+ * @brief SYSCTRL LL GPIOA Debounce Clock Config
+ * @param src GPIOA Debounce Clock Source
+ * @param div GPIOA Debounce Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_GPIOA_DbcClkCfg(SYSCTRL_GPIOADbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
+ LOG_E("GPIOA Debounce CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOADbcSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_GPIOADbcClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL GPIOB Debounce Clock Config
+ * @param src GPIOB Debounce Clock Source
+ * @param div GPIOB Debounce Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_GPIOB_DbcClkCfg(SYSCTRL_GPIOBDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
+ LOG_E("GPIOB Debounce CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOBDbcSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_GPIOBDbcClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL GPIOC Debounce Clock Config
+ * @param src GPIOC Debounce Clock Source
+ * @param div GPIOC Debounce Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_GPIOC_DbcClkCfg(SYSCTRL_GPIOCDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
+ LOG_E("GPIOC Debounce CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOCDbcSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_GPIOCDbcClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL GPIOD Debounce Clock Config
+ * @param src GPIOD Debounce Clock Source
+ * @param div GPIOD Debounce Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_GPIOD_DbcClkCfg(SYSCTRL_GPIODDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
+ LOG_E("GPIOD Debounce CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIODDbcSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_GPIODDbcClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL DFLASH Clock Config
+ * @param src DFLASH Clock Source
+ * @param div DFLASH Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_DFLASH_ClkCfg(SYSCTRL_DflashClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_16) {
+ LOG_E("DFLASH CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DFLASHMemClkSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_DFLASHMemClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL EFLASH Clock Config
+ * @param src EFLASH Clock Source
+ * @param div EFLASH Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_EFLASH_ClkCfg(SYSCTRL_EflashClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_16) {
+ LOG_E("EFLASH CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_EFLASHMemClkSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_EFLASHMemClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL ADC Function Clock Config
+ * @param src ADC Function Clock Source
+ * @param div ADC Function Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_ADC_FuncClkCfg(SYSCTRL_ADCFuncClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_4) {
+ LOG_E("ADC Function CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_ADCFunClkSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_ADCFunClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL HRPWM Function Clock Config
+ * @param src HRPWM Function Clock Source
+ * @param div HRPWM Function Clock Div
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_SYSCTRL_HRPWM_FuncClkCfg(SYSCTRL_HRPWMFuncClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
+{
+ if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_4) {
+ LOG_E("HRPWM Function CLK div-[%d] config error!\n", div);
+ return LL_ERROR;
+ }
+
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_HRPWMFunClkSrc_Set(SYSCTRL, src);
+ __LL_SYSCTRL_HRPWMFunClkDiv_Set(SYSCTRL, div);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL LL SYSCLK freq get
+ * @param None
+ * @return SYSCLK freq
+ */
+uint32_t LL_SYSCTRL_SysclkGet(void)
+{
+ return SystemCoreClock;
+}
+
+/**
+ * @brief SYSCTRL LL AHB Clock freq get
+ * @note AHB Clock is equal to SYSCLK
+ * @param None
+ * @return AHB Clock freq
+ */
+uint32_t LL_SYSCTRL_AHBClkGet(void)
+{
+ return LL_SYSCTRL_SysclkGet();
+}
+
+/**
+ * @brief SYSCTRL LL APB0 Clock freq get
+ * @note APB0 Clock is Div from AHB
+ * @param None
+ * @return APB0 Clock freq
+ */
+uint32_t LL_SYSCTRL_APB0ClkGet(void)
+{
+ return LL_SYSCTRL_AHBClkGet() / __LL_SYSCTRL_APB0ClkDiv_Get(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL LL APB1 Clock freq get
+ * @note APB1 Clock is Div from AHB
+ * @param None
+ * @return APB1 Clock freq
+ */
+uint32_t LL_SYSCTRL_APB1ClkGet(void)
+{
+ return LL_SYSCTRL_AHBClkGet() / __LL_SYSCTRL_APB1ClkDiv_Get(SYSCTRL);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SYSCTRL_LL_Exported_Functions_Group2 SYSCTRL PLL Config Functions
+ * @brief SYSCTRL PLL Config Functions
+ * @{
+ */
+
+/**
+ * @brief SYSCTRL ll PLL0 Config
+ * @param Instance Specifies SYSCTRL peripheral
+ * @param pll0_cfg PLL0 Config Pointer
+ * @return LL_StatusETypeDef Config Result
+ */
+LL_StatusETypeDef LL_SYSCTRL_Pll0Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll0_cfg)
+{
+ uint8_t i, j;
+ SYSCTRL_ClkDivETypeDef post_div = SYSCTRL_CLK_DIV_IVD;
+
+ if (Instance == NULL || pll0_cfg == NULL) {
+ LOG_E("PLL0 config params error!\n");
+ return LL_ERROR;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sysctrl_pll_cfg); i++) {
+ if (sysctrl_pll_cfg[i].pll_in_freq == pll0_cfg->pll_in_freq) {
+ for (j = 2; j <= 16; j++) {
+ if ((sysctrl_pll_cfg[i].pll_out_freq / j) == pll0_cfg->pll_user_freq && \
+ !(sysctrl_pll_cfg[i].pll_out_freq % j)) {
+ post_div = (SYSCTRL_ClkDivETypeDef)j;
+ break;
+ }
+ }
+
+ if (post_div != SYSCTRL_CLK_DIV_IVD) {
+ break;
+ }
+ }
+ }
+
+ if (i == ARRAY_SIZE(sysctrl_pll_cfg)) {
+ LOG_E("Don't match pll0_in_freq-[%d] to generate pll0_out_freq-[%d], please add the config to sysctrl_pll_cfg array!\n", \
+ pll0_cfg->pll_in_freq, pll0_cfg->pll_user_freq);
+ return LL_ERROR;
+ }
+
+ //SYSCTRL CTRL Register Unlock
+ __LL_SYSCTRL_CTRLReg_Unlock(Instance);
+
+ switch (pll0_cfg->pll_clk_src) {
+ case PLLCLK_SRC_XOSC:
+ LL_SYSCTRL_XOSCCfg(Instance);
+
+ LOG_I("PLL0 CLK Source Select XOSC.\n");
+ __LL_SYSCTRL_PLL0_RefClk_Set(Instance, SYSCTRL_PLL0_REFCLK_XOSC);
+ break;
+
+ case PLLCLK_SRC_RC8M:
+ __LL_SYSCTRL_RC8M_En(Instance);
+
+ LOG_I("PLL0 CLK Source Select RC8M.\n");
+ __LL_SYSCTRL_PLL0_RefClk_Set(Instance, SYSCTRL_PLL0_REFCLK_RC8M);
+ break;
+
+ case PLLCLK_SRC_DFT:
+ LOG_I("PLL0 CLK Source Select DFT.\n");
+ __LL_SYSCTRL_PLL0_RefClk_Set(Instance, SYSCTRL_PLL0_REFCLK_DFT);
+ break;
+
+ default:
+ LOG_E("PLL0 CLK Source Select-[%d] Error!\n", pll0_cfg->pll_clk_src);
+ return LL_ERROR;
+ }
+
+ //PLL0 Pre-Div Config
+ if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_1) {
+ __LL_SYSCTRL_PLL0_PreDiv_1(Instance);
+ } else if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_2) {
+ __LL_SYSCTRL_PLL0_PreDiv_2(Instance);
+ } else {
+ LOG_E("PLL0 Pre-Div Config-[%d] Error!\n", sysctrl_pll_cfg[i].pll_pre_div);
+ }
+
+ //PLL0 Div Config
+ if (post_div >= SYSCTRL_CLK_DIV_2 && post_div <= SYSCTRL_CLK_DIV_16) {
+ __LL_SYSCTRL_PLL0_DIV_Set(Instance, post_div);
+ } else {
+ LOG_E("PLL0 Post Div Config-[%d] Error!\n", post_div);
+ }
+
+ //FPLL0 integer/fraction Config & Enable & Start
+ LL_FPLL_DivStart(FPLL0, sysctrl_pll_cfg[i].fpll_int, sysctrl_pll_cfg[i].fpll_frac);
+
+ //PLL0 VCO Band and Gain Config and Enable
+ __LL_SYSCTRL_PLL0_Band_Set(Instance, sysctrl_pll_cfg[i].pll_vco_band);
+ __LL_SYSCTRL_PLL0_GVCO_Set(Instance, sysctrl_pll_cfg[i].pll_vco_gain);
+ __LL_SYSCTRL_PLL0_En(Instance);
+
+ //Wait for PLL0 Lock
+ LOG_D("Wait for PLL0 lock output\n");
+
+ while (!__LL_SYSCTRL_PLL0_IsLocked(Instance))
+ ;
+
+ LOG_D("PLL0 lock Success\n");
+
+ //SYSCTRL Register Lock
+ __LL_SYSCTRL_Reg_Lock(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL ll PLL1 Config
+ * @note PLL1 don't config post-div, which is used for ADC/HRPWM module generally
+ * @param Instance Specifies SYSCTRL peripheral
+ * @param pll1_cfg PLL1 Config Pointer
+ * @return LL_StatusETypeDef Config Result
+ */
+LL_StatusETypeDef LL_SYSCTRL_Pll1Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll1_cfg)
+{
+ uint8_t i;
+
+ if (Instance == NULL || pll1_cfg == NULL) {
+ LOG_E("PLL1 config params error!\n");
+ return LL_ERROR;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sysctrl_pll_cfg); i++) {
+ if (sysctrl_pll_cfg[i].pll_in_freq == pll1_cfg->pll_in_freq && \
+ sysctrl_pll_cfg[i].pll_out_freq == pll1_cfg->pll_user_freq) {
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(sysctrl_pll_cfg)) {
+ LOG_E("Don't match pll1_in_freq-[%d] to generate pll1_out_freq-[%d], please add the config to sysctrl_pll_cfg array!\n", \
+ pll1_cfg->pll_in_freq, pll1_cfg->pll_user_freq);
+ return LL_ERROR;
+ }
+
+ //SYSCTRL CTRL Register Unlock
+ __LL_SYSCTRL_CTRLReg_Unlock(Instance);
+
+ switch (pll1_cfg->pll_clk_src) {
+ case PLLCLK_SRC_XOSC:
+ LL_SYSCTRL_XOSCCfg(Instance);
+
+ LOG_I("PLL1 CLK Source Select XOSC.\n");
+ __LL_SYSCTRL_PLL1_RefClk_Set(Instance, SYSCTRL_PLL1_REFCLK_XOSC);
+ break;
+
+ case PLLCLK_SRC_RC8M:
+ __LL_SYSCTRL_RC8M_En(Instance);
+
+ LOG_I("PLL1 CLK Source Select RC8M.\n");
+ __LL_SYSCTRL_PLL1_RefClk_Set(Instance, SYSCTRL_PLL1_REFCLK_RC8M);
+ break;
+
+ case PLLCLK_SRC_DFT:
+ LOG_I("PLL1 CLK Source Select DFT.\n");
+ __LL_SYSCTRL_PLL1_RefClk_Set(Instance, SYSCTRL_PLL1_REFCLK_DFT);
+ break;
+
+ default:
+ LOG_E("PLL1 CLK Source Select-[%d] Error!\n", pll1_cfg->pll_clk_src);
+ return LL_ERROR;
+ }
+
+ //PLL1 Pre-Div Config
+ if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_1) {
+ __LL_SYSCTRL_PLL1_PreDiv_1(Instance);
+ } else if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_2) {
+ __LL_SYSCTRL_PLL1_PreDiv_2(Instance);
+ } else {
+ LOG_E("PLL1 Pre-Div Config-[%d] Error!\n", sysctrl_pll_cfg[i].pll_pre_div);
+ }
+
+ //FPLL1 integer/fraction Config & Enable & Start
+ LL_FPLL_DivStart(FPLL1, sysctrl_pll_cfg[i].fpll_int, sysctrl_pll_cfg[i].fpll_frac);
+
+ //PLL1 VCO Band and Gain Config and Enable
+ __LL_SYSCTRL_PLL1_Band_Set(Instance, sysctrl_pll_cfg[i].pll_vco_band);
+ __LL_SYSCTRL_PLL1_GVCO_Set(Instance, sysctrl_pll_cfg[i].pll_vco_gain);
+ __LL_SYSCTRL_PLL1_En(Instance);
+
+ //Wait for PLL1 Lock
+ LOG_D("Wait for PLL1 lock output\n");
+
+ while (!__LL_SYSCTRL_PLL1_IsLocked(Instance))
+ ;
+
+ LOG_D("PLL1 lock Success\n");
+
+ //SYSCTRL Register Lock
+ __LL_SYSCTRL_Reg_Lock(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SYSCTRL ll PLL2 Config
+ * @param Instance Specifies SYSCTRL peripheral
+ * @param pll2_cfg PLL2 Config Pointer
+ * @return LL_StatusETypeDef Config Result
+ */
+LL_StatusETypeDef LL_SYSCTRL_Pll2Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll2_cfg)
+{
+ uint8_t i, j;
+ SYSCTRL_ClkDivETypeDef post_div = SYSCTRL_CLK_DIV_IVD;
+
+ if (Instance == NULL || pll2_cfg == NULL) {
+ LOG_E("PLL2 config params error!\n");
+ return LL_ERROR;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sysctrl_pll_cfg); i++) {
+ if (sysctrl_pll_cfg[i].pll_in_freq == pll2_cfg->pll_in_freq) {
+ for (j = 2; j <= 16; j++) {
+ if ((sysctrl_pll_cfg[i].pll_out_freq / j) == pll2_cfg->pll_user_freq && !(sysctrl_pll_cfg[i].pll_out_freq % j)) {
+ post_div = (SYSCTRL_ClkDivETypeDef)j;
+ break;
+ }
+ }
+
+ if (post_div != SYSCTRL_CLK_DIV_IVD) {
+ break;
+ }
+ }
+ }
+
+ if (i == ARRAY_SIZE(sysctrl_pll_cfg)) {
+ LOG_E("Don't match pll2_in_freq-[%d] to generate pll2_out_freq-[%d], please add the config to sysctrl_pll_cfg array!\n", \
+ pll2_cfg->pll_in_freq, pll2_cfg->pll_user_freq);
+ return LL_ERROR;
+ }
+
+ //SYSCTRL CTRL Register Unlock
+ __LL_SYSCTRL_CTRLReg_Unlock(Instance);
+
+ switch (pll2_cfg->pll_clk_src) {
+ case PLLCLK_SRC_XOSC:
+ LL_SYSCTRL_XOSCCfg(Instance);
+
+ LOG_I("PLL2 CLK Source Select XOSC.\n");
+ __LL_SYSCTRL_PLL2_RefClk_Set(Instance, SYSCTRL_PLL2_REFCLK_XOSC);
+ break;
+
+ case PLLCLK_SRC_RC8M:
+ __LL_SYSCTRL_RC8M_En(Instance);
+
+ LOG_I("PLL2 CLK Source Select RC8M.\n");
+ __LL_SYSCTRL_PLL2_RefClk_Set(Instance, SYSCTRL_PLL2_REFCLK_RC8M);
+ break;
+
+ case PLLCLK_SRC_DFT:
+ LOG_I("PLL2 CLK Source Select DFT.\n");
+ __LL_SYSCTRL_PLL2_RefClk_Set(Instance, SYSCTRL_PLL2_REFCLK_DFT);
+ break;
+
+ default:
+ LOG_E("PLL2 CLK Source Select-[%d] Error!\n", pll2_cfg->pll_clk_src);
+ return LL_ERROR;
+ }
+
+ //PLL2 Pre-Div Config
+ if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_1) {
+ __LL_SYSCTRL_PLL2_PreDiv_1(Instance);
+ } else if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_2) {
+ __LL_SYSCTRL_PLL2_PreDiv_2(Instance);
+ } else {
+ LOG_E("PLL2 Pre-Div Config-[%d] Error!\n", sysctrl_pll_cfg[i].pll_pre_div);
+ }
+
+ //PLL2 Div Config
+ if (post_div >= SYSCTRL_CLK_DIV_2 && post_div <= SYSCTRL_CLK_DIV_16) {
+ __LL_SYSCTRL_PLL2_DIV_Set(Instance, post_div);
+ } else {
+ LOG_E("PLL2 Post Div Config-[%d] Error!\n", post_div);
+ }
+
+ //FPLL2 integer/fraction Config & Enable & Start
+ LL_FPLL_DivStart(FPLL2, sysctrl_pll_cfg[i].fpll_int, sysctrl_pll_cfg[i].fpll_frac);
+
+ //PLL2 VCO Band and Gain Config and Enable
+ __LL_SYSCTRL_PLL2_Band_Set(Instance, sysctrl_pll_cfg[i].pll_vco_band);
+ __LL_SYSCTRL_PLL2_GVCO_Set(Instance, sysctrl_pll_cfg[i].pll_vco_gain);
+ __LL_SYSCTRL_PLL2_En(Instance);
+
+ //Wait for PLL2 Lock
+ LOG_D("Wait for PLL2 lock output\n");
+
+ while (!__LL_SYSCTRL_PLL2_IsLocked(Instance))
+ ;
+
+ LOG_D("PLL2 lock Success\n");
+
+ //SYSCTRL Register Lock
+ __LL_SYSCTRL_Reg_Lock(Instance);
+
+ return LL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup SYSCTRL_LL_Exported_Functions_Group3 SYSCTRL Peripherals Clock and Reset control Functions
+ * @brief SYSCTRL Peripherals Clock and Reset control Functions
+ * @{
+ */
+
+/**
+ * @brief SYSCTRL LSTIMER Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_LSTMR_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_LSTIMERBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_LSTIMERSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL LSTIMER Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_LSTMR_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_LSTIMERBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_LSTIMERSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL Uart1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_UART1_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_UART1BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_UART1SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL Uart1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_UART1_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_UART1BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_UART1SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL Uart0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_UART0_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_UART0BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_UART0SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL Uart0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_UART0_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_UART0BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_UART0SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL I2C1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_I2C1_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_I2C1BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_I2C1SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL I2C1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_I2C1_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_I2C1BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_I2C1SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL I2C0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_I2C0_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_I2C0BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_I2C0SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL I2C0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_I2C0_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_I2C0BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_I2C0SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL ECU Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_ECU_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_ECUBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_ECUFunClk_En(SYSCTRL);
+ __LL_SYSCTRL_ECUSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL ECU Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_ECU_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_ECUBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_ECUFunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_ECUSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR4 Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR4_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR4BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR4FunClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR4SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR4 Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR4_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR4BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR4FunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR4SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR3 Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR3_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR3BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR3FunClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR3SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR3 Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR3_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR3BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR3FunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR3SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR2 Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR2_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR2BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR2FunClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR2SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR2 Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR2_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR2BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR2FunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR2SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR1 Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR1_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR1BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR1FunClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR1SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR1 Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR1_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR1BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR1FunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR1SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR0 Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR0_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR0BusClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR0FunClk_En(SYSCTRL);
+ __LL_SYSCTRL_IIR0SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL IIR0 Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_IIR0_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_IIR0BusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR0FunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_IIR0SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DALI Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DALI_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DALIBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_DALISoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DALI Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DALI_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DALIBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_DALISoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL FPLL2 Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_FPLL2_RstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_FPLL2SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL FPLL2 Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_FPLL2_RstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_FPLL2SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL FPLL1 Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_FPLL1_RstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_FPLL1SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL FPLL1 Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_FPLL1_RstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_FPLL1SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL FPLL0 Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_FPLL0_RstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_FPLL0SoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL FPLL0 Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_FPLL0_RstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_FPLL0SoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL USB Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_USB_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_USBBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_USBFunClk_En(SYSCTRL);
+ __LL_SYSCTRL_USBSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL USB Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_USB_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_USBBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_USBFunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_USBSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DFLASH Bus&Memory Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DFLASH_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DFLASHBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_DFLASHMemClk_En(SYSCTRL);
+ __LL_SYSCTRL_DFLASHSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DFLASH Bus&Memory Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DFLASH_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DFLASHBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_DFLASHMemClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_DFLASHSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL EFLASH Bus&Memory Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_EFLASH_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_EFLASHBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_EFLASHMemClk_En(SYSCTRL);
+ __LL_SYSCTRL_EFLASHSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL EFLASH Bus&Memory Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_EFLASH_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_EFLASHBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_EFLASHMemClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_EFLASHSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL HRPWM Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_HRPWM_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_HRPWMBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_HRPWMFunClk_En(SYSCTRL);
+ __LL_SYSCTRL_HRPWMSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL HRPWM Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_HRPWM_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_HRPWMBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_HRPWMFunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_HRPWMSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL ADC Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_ADC_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_ADCBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_ADCFunClk_En(SYSCTRL);
+ __LL_SYSCTRL_ADCSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL ADC Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_ADC_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_ADCBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_ADCFunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_ADCSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DAC Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DAC_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DACBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_DACSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DAC Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DAC_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DACBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_DACSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL CMP Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_CMP_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_CMPBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_CMPSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL CMP Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_CMP_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_CMPBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_CMPSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOD Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOD_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIODBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_GPIODSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOD Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOD_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIODBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_GPIODSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOC Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOC_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOCBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_GPIOCSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOC Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOC_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOCBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_GPIOCSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOB Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOB_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOBBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_GPIOBSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOB Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOB_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOBBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_GPIOBSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOA Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOA_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOABusClk_En(SYSCTRL);
+ __LL_SYSCTRL_GPIOASoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL GPIOA Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_GPIOA_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_GPIOABusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_GPIOASoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL HSTIMER Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_HSTMR_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_HSTIMERBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_HSTIMERSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL HSTIMER Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_HSTMR_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_HSTIMERBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_HSTIMERSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL CAN Bus&Function Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_CAN_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_CANBusClk_En(SYSCTRL);
+ __LL_SYSCTRL_CANFunClk_En(SYSCTRL);
+ __LL_SYSCTRL_CANSoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL CAN Bus&Function Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_CAN_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_CANBusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_CANFunClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_CANSoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DMA Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DMA_ClkEnRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DMABusClk_En(SYSCTRL);
+ __LL_SYSCTRL_DMASoftRst_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL DMA Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_DMA_ClkDisRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_DMABusClk_Dis(SYSCTRL);
+ __LL_SYSCTRL_DMASoftRst_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+
+/**
+ * @brief SYSCTRL LL all peripheral reset assert
+ * @note All peripheral include system bus(AHB/APB0/APB1)
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_AllPeriphRstAssert(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_SysSoftRstAll_Assert(SYSCTRL);
+ __LL_SYSCTRL_APB0SoftRstAll_Assert(SYSCTRL);
+ __LL_SYSCTRL_APB1SoftRstAll_Assert(SYSCTRL);
+ __LL_SYSCTRL_AHBSoftRstAll_Assert(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @brief SYSCTRL LL all peripheral reset release
+ * @note All peripheral include system bus(AHB/APB0/APB1)
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_AllPeriphRstRelease(void)
+{
+ __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_SysSoftRstAll_Release(SYSCTRL);
+ __LL_SYSCTRL_APB0SoftRstAll_Release(SYSCTRL);
+ __LL_SYSCTRL_APB1SoftRstAll_Release(SYSCTRL);
+ __LL_SYSCTRL_AHBSoftRstAll_Release(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+/**
+ * @}
+ */
+
+/** @defgroup SYSCTRL_LL_Exported_Functions_Group4 SYSCTRL Misc Config Functions
+ * @brief SYSCTRL Misc Config Functions
+ * @{
+ */
+
+/**
+ * @brief SYSCTRL LL PMU Config
+ * @param None
+ * @return None
+ */
+void LL_SYSCTRL_PMUCfg(void)
+{
+ __LL_SYSCTRL_FLSReg_Unlock(SYSCTRL);
+ __LL_SYSCTRL_CUR_RES_Set(SYSCTRL, 0);
+ __LL_SYSCTRL_BGR_DRD_Dis(SYSCTRL);
+ __LL_SYSCTRL_BGR_Filter_En(SYSCTRL);
+ __LL_SYSCTRL_Reg_Lock(SYSCTRL);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup SYSCTRL_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief SYSCTRL LL XOSC Config
+ * @param Instance Specifies SYSCTRL peripheral
+ * @note Must unlock SYSCTRL CTRL Reg before call this function
+ * @return None
+ */
+static void LL_SYSCTRL_XOSCCfg(SYSCTRL_TypeDef *Instance)
+{
+ //Check SYSCTRL CTRL Reg unlock or not
+ if (!__LL_SYSCTRL_IsCTRLRegUnlock(Instance)) {
+ LOG_E("SYSCTRL CTRL Reg is Lock, please unlock it before call this function!\n");
+ return;
+ }
+
+ __LL_SYSCTRL_XOSC_En(Instance);
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_tmr.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_tmr.c
new file mode 100644
index 0000000000..45c138dd21
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_tmr.c
@@ -0,0 +1,820 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_tmr.c
+ * @author MCD Application Team
+ * @brief TMR LL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TMR) peripheral:
+ * + TMR Time Initialization and De-Initialization function
+ * + TMR Input Capture and Output Compare configure functions
+ * + TMR Start and Stop functions
+ * + TMR event software generate function
+ * + TMR internal trigger signal configure function
+ * + TMR interrupt handler and callback functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "TMR LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup TMR_LL TMR LL
+ * @brief TMR LL module driver.
+ * @{
+ */
+
+#ifdef LL_TMR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TMR_LL_Private_Functions TMR LL Private Functions
+ * @brief TMR LL Private Functions
+ * @{
+ */
+static void TMR_TB_SetConfig(TMR_TypeDef *Instance, TMR_TB_InitTypeDef *Config);
+static void TMR_IC_SetConfig(TMR_TypeDef *Instance, TMR_IC_InitTypeDef *Config);
+static void TMR_OC_SetConfig(TMR_TypeDef *Instance, TMR_OC_InitTypeDef *Config);
+static void TMR_EXT_SetConfig(TMR_TypeDef *Instance, TMR_EXT_InitTypeDef *Config);
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TMR_LL_Exported_Functions TMR LL Exported Functions
+ * @brief TMR LL Exported Functions
+ * @{
+ */
+
+/** @defgroup TMR_LL_Exported_Functions_Group1 Initialization and De-Initialization functions
+ * @brief Initialization and De-Initialization functions
+@verbatim
+ ==============================================================================
+ ##### Initialization and De-Initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TMR base unit.
+ (+) De-initialize the TMR base unit.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the TMR peripheral
+ * @param Instance TMR peripheral instance
+ * @param Init pointer to a TMR_InitTypeDef structure that contains the configuration
+ * information for the specified TMR peripheral.
+ * @note InputCapture and OutputCompare feature must NOT be enabled at the same time
+ * in one single TMR peripheral.
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_TMR_Init(TMR_TypeDef *Instance, TMR_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+ assert_param(Init != NULL);
+ /* Input Capture and Output Compare can not be enabled in one TMR at the same time */
+ assert_param(!((Init->ICInit.ICEnable == ENABLE) && (Init->OCInit.OCEnable == ENABLE)));
+
+ /* Handle Something */
+ LL_TMR_MspInit(Instance);
+
+ /* Disable Capture/Compare before initialization */
+ __LL_TMR_CC_DISABLE(Instance);
+
+ /* Stop Counter before initialization */
+ __LL_TMR_DISABLE(Instance);
+
+ /* Set configuration to TimeBase unit */
+ TMR_TB_SetConfig(Instance, &Init->TBInit);
+
+ /* Set configuration for Input Capture feature */
+ TMR_IC_SetConfig(Instance, &Init->ICInit);
+
+ /* Set configuration for Output Compare feature */
+ TMR_OC_SetConfig(Instance, &Init->OCInit);
+
+ /* Set configuration for Export Trigger Event feature */
+ TMR_EXT_SetConfig(Instance, &Init->ExtInit);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief DeInitializes the timer
+ * @param Instance TMR peripheral instance
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_TMR_DeInit(TMR_TypeDef *Instance)
+{
+ /* Check the TMR initiation struct allocation */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ /* Stop Counter */
+ __LL_TMR_DISABLE(Instance);
+
+ /* Disable Capture Compare feature */
+ __LL_TMR_CC_DISABLE(Instance);
+
+ /* Disable TMR export trigger event feature */
+ WRITE_REG(Instance->ETER, 0);
+
+ /* Handle Something */
+ LL_TMR_MspDeInit(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the TMR MSP.
+ * @param Instance TMR peripheral
+ * @return None
+ */
+__WEAK void LL_TMR_MspInit(TMR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_TMR_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the TMR MSP
+ * @param Instance TMR peripheral
+ * @return None
+ */
+__WEAK void LL_TMR_MspDeInit(TMR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_TMR_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup TMR_LL_Exported_Functions_Group2 TMR Peripheral Control functions
+ * @brief TMR Peripheral Control functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) TMR Input-Capture configure functions
+ (+) TMR Output-Compare configure functions
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief User can use this function to reconfigure the TMR TimeBase unit
+ * according to the specified parameters in the TMR_TB_InitTypeDef on runtime.
+ * @param Instance TMR peripheral instance
+ * @param Config TMR TimeBase Unit configuration structure
+ * @return status of the initialization
+ */
+LL_StatusETypeDef LL_TMR_TB_Config(TMR_TypeDef *Instance, TMR_TB_InitTypeDef *Config)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+ assert_param(Config != NULL);
+
+ /* Set configuration to TimeBase unit */
+ TMR_TB_SetConfig(Instance, Config);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+
+/**
+ * @brief User can use this function to reconfigure the TMR Input Capture feature
+ * according to the specified parameters in the TMR_IC_InitTypeDef on runtime.
+ * @note Use LL_TMR_CC_ENABLE() or LL_TMR_CC_DISABLE() macros to enable or disable
+ * the Capture Compare feature.
+ * @param Instance TMR peripheral
+ * @param Config TMR Input Capture configuration structure
+ * @return status of the configuration
+ */
+LL_StatusETypeDef LL_TMR_IC_Config(TMR_TypeDef *Instance, TMR_IC_InitTypeDef *Config)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+ assert_param(Config != NULL);
+
+ /* Disable CCE before configuration */
+ CLEAR_BIT(Instance->CCCR, TMR_CCCR_CCE);
+
+ /* Set configuration for Input Capture feature */
+ TMR_IC_SetConfig(Instance, Config);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief User can use this function to reconfigure the TMR Output Compare feature
+ * according to the specified parameters in the TMR_OC_InitTypeDef on runtime.
+ * @note Use LL_TMR_CC_ENABLE() or LL_TMR_CC_DISABLE() macros to enable or disable
+ * the Capture Compare feature.
+ * @param Instance TMR peripheral
+ * @param Config TMR Output Compare configuration structure.
+ * @return status of the configuration
+ */
+LL_StatusETypeDef LL_TMR_OC_Config(TMR_TypeDef *Instance, TMR_OC_InitTypeDef *Config)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+ assert_param(Config != NULL);
+
+ /* Disable CCE before configuration */
+ CLEAR_BIT(Instance->CCCR, TMR_CCCR_CCE);
+
+ /* Set configuration for Output Compare feature */
+ TMR_OC_SetConfig(Instance, Config);
+
+ /* Return function status */
+ return LL_OK;
+
+}
+
+/**
+ * @brief User can use this function to reconfigure the TMR Export Trigger Event feature
+ * according to the specified parameters in the TMR_EXT_InitTypeDef on runtime.
+ * @param Instance TMR peripheral
+ * @param Config TMR Export Trigger configuration structure.
+ * @note Please notice if user want to enable or disable the TMR events as the internal signal,
+ * this configuration function should be called to config the specified events.
+ * @return status of the configuration
+ */
+LL_StatusETypeDef LL_TMR_EXT_Config(TMR_TypeDef *Instance, TMR_EXT_InitTypeDef *Config)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+ assert_param(Config != NULL);
+
+ /* Set configuration for Export Trigger Event feature */
+ TMR_EXT_SetConfig(Instance, Config);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup TMR_LL_Exported_Functions_Group3 TMR Input and Output operation functions
+ * @brief TMR Input and Output operation functions
+@verbatim
+ ===============================================================================
+ ##### Input and Output operation functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) TMR Start and Stop functions
+ (+) TMR Synchro start function
+ (+) TMR event software generate function
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the Timer.
+ * @param Instance TMR peripheral
+ * @return LL status
+ */
+LL_StatusETypeDef LL_TMR_Start(TMR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ /* Start Counter*/
+ __LL_TMR_ENABLE(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Stop the Timer.
+ * @param Instance TMR peripheral
+ * @return LL status
+ */
+LL_StatusETypeDef LL_TMR_Stop(TMR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ /* Stop Counter */
+ __LL_TMR_DISABLE(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Start the timer with interrupt enabled
+ * @param Instance TMR peripheral
+ * @return LL status
+ */
+LL_StatusETypeDef LL_TMR_Start_IT(TMR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ if ((Instance->CR & TMR_CR_UDIS_Msk) != TMR_CR_UDIS) {
+ /* TMR Update Interrupt Enable if Update event is enabled */
+ __LL_TMR_IT_ENABLE(Instance, TMR_IT_UIE);
+ }
+
+ /* Check if Capture Compare mode is enabled */
+ if ((Instance->CCCR & TMR_CCCR_CCE_Msk) == TMR_CCCR_CCE) {
+ if ((Instance->CCCR & TMR_CCCR_CCS_Msk) == TMR_CCCR_CCS) {
+ /* Enable Input Capture interrupt source */
+ __LL_TMR_CC_IT_ENABLE(Instance, TMR_IT_ICIE | TMR_IT_ICOIE);
+ } else {
+ /* Enable Output Compare interrupt source */
+ __LL_TMR_CC_IT_ENABLE(Instance, TMR_IT_OCIE);
+ }
+ }
+
+ /* TMR Counter Overflow Interrupt Enable */
+ __LL_TMR_IT_ENABLE(Instance, TMR_IT_OVIE);
+
+ /* Start Counter */
+ __LL_TMR_ENABLE(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Stop the timer with interrupt disabled
+ * @param Instance TMR peripheral
+ * @return LL status
+ */
+LL_StatusETypeDef LL_TMR_Stop_IT(TMR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ /* TMR Update and Counter Overflow Interrupt Disable */
+ __LL_TMR_IT_DISABLE(Instance, TMR_IT_UIE | TMR_IT_OVIE);
+
+ /* Capture Compare interrupt disable */
+ __LL_TMR_CC_IT_DISABLE(Instance, (TMR_IT_ICIE |
+ TMR_IT_ICOIE |
+ TMR_IT_OCIE));
+
+ /* Stop Counter */
+ __LL_TMR_DISABLE(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Synchro Start the specifies timers.
+ * @param TMRGRPx TMRGRP peripheral
+ * @arg TMRGRP0: Group of LSTMRs(TMR0/1/2/3)
+ * @arg TMRGRP1: Group of HSTMRs(TMR4/5/6/7)
+ * @param SynchroMask Specifies timer masks to start synchronously. This parameter can be
+ * any combination of @ref TMRGRP_Sync_definition :
+ * @arg TMRGRP_SYNC_TMR0 : Select TMR0(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR1 : Select TMR1(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR2 : Select TMR2(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR3 : Select TMR3(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR4 : Select TMR4(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_TMR5 : Select TMR5(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_TMR6 : Select TMR6(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_TMR7 : Select TMR7(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_ALL : Select all TMRs in TMRGRPx(x = 0 or 1)
+ * @note Please notice that only timers in same group can be started synchronously.
+ * For example for TMRGRP0, SynchroMask of the TMR0/1/2/3 will be started synchronously.
+ * @note If user wants to use it with specifies timers' interrupt enabled, use __LL_TMR_IT_ENABLE()
+ * and __LL_TMR_CC_IT_ENABLE() to enable the necessary interrupt sources before starting them.
+ * @return LL status
+ */
+LL_StatusETypeDef LL_TMR_Start_Synchro(TMRGRP_TypeDef *TMRGRPx, uint32_t SynchroMask)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_TMRGRP_INSTANCE(TMRGRPx));
+
+ /* Start specifies timers synchronously */
+ WRITE_REG(TMRGRPx->SYNCR, SynchroMask);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Synchro Stop the specifies timers.
+ * @param TMRGRPx TMRGRP peripheral
+ * @arg TMRGRP0: Group of LSTMRs(TMR0/1/2/3)
+ * @arg TMRGRP1: Group of HSTMRs(TMR4/5/6/7)
+ * @param SynchroMask Specifies timer masks to stop synchronously. This parameter can be
+ * any combination of @ref TMRGRP_Sync_definition :
+ * @arg TMRGRP_SYNC_TMR0 : Select TMR0(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR1 : Select TMR1(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR2 : Select TMR2(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR3 : Select TMR3(specific to TMRGRP0)
+ * @arg TMRGRP_SYNC_TMR4 : Select TMR4(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_TMR5 : Select TMR5(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_TMR6 : Select TMR6(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_TMR7 : Select TMR7(specific to TMRGRP1)
+ * @arg TMRGRP_SYNC_ALL : Select all TMRs in TMRGRPx(x = 0 or 1)
+ * @note Please notice that only timers in same group can be stopped synchronously.
+ * For example for TMRGRP0, SynchroMask of the TMR0/1/2/3 will be stopped synchronously.
+ * @return LL status
+ */
+LL_StatusETypeDef LL_TMR_Stop_Synchro(TMRGRP_TypeDef *TMRGRPx, uint32_t SynchroMask)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_TMRGRP_INSTANCE(TMRGRPx));
+
+ /* Stop specifies timers synchronously */
+ WRITE_REG(TMRGRPx->SYNCR, SynchroMask << 4);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief Generate a software event
+ * @param Instance TMR peripheral
+ * @param EventSource specifies the event source.
+ * This parameter can be one of the following values in @ref TMR_Event_Source:
+ * @arg TMR_EVENTSOURCE_UG: Reinitialize the counter and generates an update of the registers
+ * @arg TMR_EVENTSOURCE_CCG: Generate a capture/compare event
+ * @return LL status
+ */
+LL_StatusETypeDef LL_TMR_EventGenerate(TMR_TypeDef *Instance, TMR_EventSRCETypeDef EventSource)
+{
+ /* Check the TMR initiation struct allocation */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ /* Generation Timer Counter Update Event */
+ WRITE_REG(Instance->EGR, EventSource);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup TMR_LL_Exported_Functions_Interrupt TMR Interrupt management
+ * @brief TMR Initerrupt management
+@verbatim
+ ===============================================================================
+ ##### Initerrupt management #####
+ ===============================================================================
+ [..]
+ This section provides TMR interrupt handler and callback functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles TMR interrupts requests.
+ * @param Instance TMR peripheral
+ * @return None
+ */
+void LL_TMR_IRQHandler(TMR_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ if ((__LL_TMR_IT_CHECK_SOURCE(Instance, TMR_IT_UIE) != RESET) &&
+ (__LL_TMR_GET_FLAG(Instance, TMR_FLAG_UIF) != RESET)) {
+ /* Clear the Update interrupt flag */
+ __LL_TMR_CLEAR_FLAG(Instance, TMR_FLAG_UIF);
+
+ /* TMR Update Interrupt Callback */
+ LL_TMR_TB_UpdateCallback(Instance);
+ }
+
+ if ((__LL_TMR_IT_CHECK_SOURCE(Instance, TMR_IT_OVIE) != RESET) &&
+ (__LL_TMR_GET_FLAG(Instance, TMR_FLAG_OVIF) != RESET)) {
+ /* Claer the OverFlow interrupt flag */
+ __LL_TMR_CLEAR_FLAG(Instance, TMR_FLAG_OVIF);
+
+ /* TMR Counter Overflow Interrupt Callback */
+ LL_TMR_TB_OverflowCallback(Instance);
+ }
+
+ if ((__LL_TMR_CC_IT_CHECK_SOURCE(Instance, TMR_IT_ICIE) != RESET) &&
+ (__LL_TMR_GET_FLAG(Instance, TMR_FLAG_ICIF) != RESET)) {
+ /* Claer the Capture interrupt flag */
+ __LL_TMR_CLEAR_FLAG(Instance, TMR_FLAG_ICIF);
+
+ /* TMR Input Capture Captured Interrupt Callback */
+ LL_TMR_IC_CaptureCallback(Instance);
+ }
+
+ if ((__LL_TMR_CC_IT_CHECK_SOURCE(Instance, TMR_IT_ICOIE) != RESET) &&
+ (__LL_TMR_GET_FLAG(Instance, TMR_FLAG_ICOIF) != RESET)) {
+ /* Claer the OverCapture interrupt flag */
+ __LL_TMR_CLEAR_FLAG(Instance, TMR_FLAG_ICOIF);
+
+ /* Handle Something */
+ LL_TMR_IC_OverCaptureCallback(Instance);
+ }
+
+ if ((__LL_TMR_CC_IT_CHECK_SOURCE(Instance, TMR_IT_OCIE) != RESET) &&
+ (__LL_TMR_GET_FLAG(Instance, TMR_FLAG_OCIF) != RESET)) {
+
+ /* Claer the Compare interrupt flag */
+ __LL_TMR_CLEAR_FLAG(Instance, TMR_FLAG_OCIF);
+
+ /* Handle Something*/
+ LL_TMR_OC_CompareMatchedCallback(Instance);
+ }
+}
+
+/**
+ * @brief TMR TimeBase unit (Counter) update interrupt callback function
+ * @param Instance TMR peripheral
+ * @return None
+ */
+__WEAK void LL_TMR_TB_UpdateCallback(TMR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_TMR_TB_UpdateCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TMR TimeBase unit (Counter) overflow interrupt callback function
+ * @param Instance TMR peripheral
+ * @return None
+ */
+__WEAK void LL_TMR_TB_OverflowCallback(TMR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_TMR_TB_OverflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TMR input capture interrupt callback function
+ * @param Instance TMR peripheral
+ * @return None
+ */
+__WEAK void LL_TMR_IC_CaptureCallback(TMR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_TMR_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TMR input capture over-capture interrupt callback function
+ * @param Instance TMR peripheral
+ * @return None
+ */
+__WEAK void LL_TMR_IC_OverCaptureCallback(TMR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_TMR_IC_OverCaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TMR output compare matched interrupt callback function
+ * @param Instance TMR peripheral
+ * @return None
+ */
+__WEAK void LL_TMR_OC_CompareMatchedCallback(TMR_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_TMR_OC_CompareMatchedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup TMR_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Set Configuration to TimeBase Unit.
+ * @param Instance TMR peripheral instance
+ * @param Config TMR TimeBase Unit configuration structure
+ * @return None
+ */
+static void TMR_TB_SetConfig(TMR_TypeDef *Instance, TMR_TB_InitTypeDef *Config)
+{
+ if (IS_TMR_LSTMR_INSTANCE(Instance)) { /* Check if Low-Speed Timer instance */
+ assert_param(IS_TMR_LSTMR_PRESCALER(Config->Prescaler));
+ assert_param(IS_TMR_LSTMR_END_VAL(Config->EndValue));
+ assert_param(IS_TMR_LSTMR_START_VAL(Config->StartValue));
+ } else { /* High-Speed Timer instance */
+ assert_param(IS_TMR_HSTMR_PRSCALER(Config->Prescaler));
+ assert_param(IS_TMR_HSTMR_END_VAL(Config->EndValue));
+ assert_param(IS_TMR_HSTMR_START_VAL(Config->StartValue));
+ }
+
+ /* Set the Counter Start value*/
+ WRITE_REG(Instance->CSVR, Config->StartValue);
+
+ /* Set the Counter End value*/
+ WRITE_REG(Instance->CEVR, Config->EndValue);
+
+ /* Set the Prescaler value*/
+ WRITE_REG(Instance->PSCR, Config->Prescaler);
+
+ /* Configures: Clock source, Auto-Reload preload, Continuous mode, Update enable and
+ Update request source */
+ WRITE_REG(Instance->CR, (Config->ClockSource | Config->AutoReloadPreload | Config->ContinuousMode |
+ Config->UpdateSource | Config->UpdateEnable));
+}
+
+/**
+ * @brief Set Configuration for Input Capture feature.
+ * @param Instance TMR peripheral instance
+ * @param sConfig TMR Input Capture configuration structure
+ * @return None
+ */
+static void TMR_IC_SetConfig(TMR_TypeDef *Instance, TMR_IC_InitTypeDef *sConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ /* Check if enable the input capture feature.
+ Note: To do that TMR clock source must be configured to internal source */
+ if ((sConfig->ICEnable == ENABLE) && (READ_BIT(Instance->CR, TMR_CR_CKSRC_Msk) == TMR_CLKSOURCE_INTERNAL)) {
+ assert_param(IS_TMR_ICFILTER(sConfig->ICFilter));
+
+ /* Set Input Capture filter */
+ WRITE_REG(Instance->ICFR, sConfig->ICFilter);
+
+ /* Configurate the TMRx_CCCR register */
+ MODIFY_REG(Instance->CCCR,
+ (TMR_CCCR_ICSRC_Msk
+ | TMR_CCCR_CCP_Msk),
+ (TMR_CCCR_CCS
+ | sConfig->ICSelection
+ | sConfig->ICPolarity));
+
+ /* Set CCE to enable the input-capture feature */
+ SET_BIT(Instance->CCCR, TMR_CCCR_CCE);
+ }
+}
+
+/**
+ * @brief Set Configuration for Output Compare feature.
+ * @param Instance TMR peripheral instance
+ * @param sConfig TMR Output Compare configuration structure
+ * @return None
+ */
+static void TMR_OC_SetConfig(TMR_TypeDef *Instance, TMR_OC_InitTypeDef *sConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ /* Check if enable the output compare feature.
+ Note: To do that TMR clock source must be configured to internal source */
+ if ((sConfig->OCEnable == ENABLE) && (READ_BIT(Instance->CR, TMR_CR_CKSRC_Msk) == TMR_CLKSOURCE_INTERNAL)) {
+ if (IS_TMR_LSTMR_INSTANCE(Instance)) {
+ assert_param(IS_TMR_LSTMR_COMPARE_VAL(sConfig->OCValue));
+ } else {
+ assert_param(IS_TMR_HSTMR_COMPARE_VAL(sConfig->OCValue));
+ }
+
+ /* Disable Output Preload feature before configuration */
+ CLEAR_BIT(Instance->CCCR, TMR_CCCR_OCPE);
+
+ /* Set Compare Value */
+ WRITE_REG(Instance->CCR, sConfig->OCValue);
+
+ /* Configurate the TMRx_CCCR register */
+ MODIFY_REG(Instance->CCCR,
+ (TMR_CCCR_OCPE_Msk
+ | TMR_CCCR_CCS_Msk
+ | TMR_CCCR_OCM_Msk
+ | TMR_CCCR_CCP_Msk),
+ (sConfig->OCMode
+ | sConfig->OCPolarity
+ | sConfig->OCPreload));
+
+ /* Set CCE to enable the input-capture feature */
+ SET_BIT(Instance->CCCR, TMR_CCCR_CCE);
+ }
+}
+
+/**
+ * @brief Set Configuration for TMR Export Trigger Event feature.
+ * @param Instance TMR peripheral
+ * @param Config TMR Export Trigger configuration structure.
+ * @return None
+ */
+static void TMR_EXT_SetConfig(TMR_TypeDef *Instance, TMR_EXT_InitTypeDef *sConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TMR_ALL_INSTANCE(Instance));
+
+ if (sConfig->ExtEnable == ENABLE) {
+ /* Configure the events */
+ MODIFY_REG(Instance->ETER,
+ (TMR_ETER_CCTPW_Msk
+ | TMR_ETER_UTPW_Msk
+ | TMR_ETER_PWMOE_Msk
+ | TMR_ETER_CCTE_Msk
+ | TMR_ETER_UTE_Msk),
+ ((0xFU << TMR_ETER_CCTPW_Pos) |
+ (0xFU << TMR_ETER_UTPW_Pos)
+ | sConfig->ExtPWMWave
+ | sConfig->ExtCCTrigger
+ | sConfig->ExtTRGOTrigger));
+ } else {
+ WRITE_REG(Instance->ETER, 0);
+ }
+}
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_TMR_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_uart.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_uart.c
new file mode 100644
index 0000000000..c0aa9ec980
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_uart.c
@@ -0,0 +1,955 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_uart.c
+ * @author MCD Application Team
+ * @brief UART LL Module Driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "UART"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UART_LL UART LL
+ * @brief UART LL module driver.
+ * @{
+ */
+
+#ifdef LL_UART_MODULE_ENABLED
+
+/* Private variables ---------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup UART_LL_Private_Macros UART LL Private Macros
+ * @brief UART LL Private Macros
+ * @{
+ */
+
+/**
+ * @brief UART Function Alternative
+ * @param flag Condition Flag
+ * @param func_t True Funciton
+ * @param func_f False Function
+ * @return None
+ */
+#define UART_FUNC_ALTER(flag, func_t, func_f) \
+ do{ \
+ if((flag)) { \
+ func_t; \
+ } else { \
+ func_f; \
+ } \
+ } while(0)
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_LL_Exported_Functions UART LL Exported Functions
+ * @brief UART LL Exported Functions
+ * @{
+ */
+#ifdef LL_DMA_MODULE_ENABLED
+
+ DMA_ChannelETypeDef LL_UART_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg);
+ LL_StatusETypeDef LL_UART_DMA_Deinit(DMA_ChannelETypeDef ch);
+ void LL_UART_DMA_TXCHEndCallback(void *arg);
+ void LL_UART_DMA_RXCHEndCallback(void *arg);
+ void LL_UART_DMA_TXCHErrorCallBck(void *arg);
+ void LL_UART_DMA_RXCHErrorCallBck(void *arg);
+
+#endif /*!< LL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UART_LL_Exported_Functions UART LL Exported Functions
+ * @brief UART LL Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+
+/**
+ * @brief UART LL init
+ * @param Instance Specifies UART peripheral
+ * @param Init init pointer
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_Init(UART_TypeDef *Instance, UART_InitTypeDef *Init)
+{
+ uint32_t baud_rate;
+
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_UART_MspInit(Instance);
+
+ //Parity config
+ if (Init->parity == UART_PARITY_NO) {
+ __LL_UART_Parity_Dis(Instance);
+ } else {
+ __LL_UART_Parity_En(Instance);
+ UART_FUNC_ALTER(Init->parity == UART_PARITY_ODD, __LL_UART_EvenParity_Clr(Instance), __LL_UART_EvenParity_Set(Instance));
+ }
+
+ //Stop bit config
+ UART_FUNC_ALTER(Init->stop_len == UART_STOP_LEN_1b, __LL_UART_Stop1Bit_Set(Instance), __LL_UART_Stop2bits_Set(Instance));
+
+ //Data length config
+ if (Init->dat_len == UART_DAT_LEN_9b) {
+ __LL_UART_DatLen9bitsExt_En(Instance);
+ __LL_UART_RAR_Set(Instance, Init->U9BRxAddress);
+
+ if (Init->U9BAddrMatchMode_Enable == ENABLE) {
+ __LL_UART_AddrMatchMode_En(Instance);
+ __LL_UART_TxMode8bits_Set(Instance);
+ } else {
+ __LL_UART_AddrMatchMode_Dis(Instance);
+ __LL_UART_TxMode9bits_Set(Instance);
+ }
+ } else {
+ __LL_UART_DatLen9bitsExt_Dis(Instance);
+ __LL_UART_DatLen_Sel(Instance, (uint8_t)Init->dat_len);
+ }
+
+ //FIFO config, FCR register can write only
+ __LL_UART_FCR_Write(Instance, Init->rx_tl | Init->tx_tl | UART_FCR_XFIFOR_Msk | UART_FCR_RFIFOR_Msk | UART_FCR_FIFOE_Msk);
+
+ //Baudrate config
+ __LL_UART_DivLatchAccess_Set(Instance);
+
+ baud_rate = (LL_SYSCTRL_APB0ClkGet() + Init->baudrate / 2) / Init->baudrate;
+ __LL_UART_DivLatchLow_Write(Instance, (uint8_t)(baud_rate >> 4));
+ __LL_UART_DivLatchHigh_Write(Instance, (uint8_t)(baud_rate >> 12));
+ __LL_UART_DivLatchFrac_Set(Instance, (baud_rate & 0xFUL));
+
+ __LL_UART_DivLatchAccess_Clr(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART LL deinit
+ * @param Instance Specifies UART peripheral
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_DeInit(UART_TypeDef *Instance)
+{
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_UART_MspDeInit(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the UART MSP.
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_MspInit(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the UART MSP
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_MspDeInit(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_LL_Exported_Functions_Group2 UART Transmit and Recieve Function
+ * @brief UART Transmit Function
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled, and Word Length is configured to 9 bits,
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @param Instance Specifies UART peripheral
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_Transmit_CPU(UART_TypeDef *Instance, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
+ uint32_t TxXferCount = Size;
+
+ /* Check the UART initiation struct allocation */
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ /* In case of 9bits, pRxData needs to be handled as a uint16_t pointer */
+ if (__LL_UART_IsDatLen9bitsEn(Instance) && __LL_UART_TxModeSta_Get(Instance)) {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ } else {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ //Transmit data loop
+ while (TxXferCount) {
+ //Wait TxFIFO to be not full
+ tickstart = LL_GetTick();
+
+ while (!__LL_UART_IsTxFIFONotFull(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ if (pdata16bits) {
+ __LL_UART_TxBuf9bits_Write(Instance, *pdata16bits++);
+ } else {
+ __LL_UART_TxBuf8bits_Write(Instance, *pdata8bits++);
+ }
+
+ /* Wait for UART Transmit completed */
+ while (!__LL_UART_IsTxEmpty(Instance));
+
+ TxXferCount--;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled, and Word Length is configured to 9 bits ,
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param Instance Specifies UART peripheral
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_Receive_CPU(UART_TypeDef *Instance, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
+ uint32_t RxXferCount = Size;
+
+ //Check the UART initiation struct allocation
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ //In case of 9bits, pRxData needs to be handled as a uint16_t pointer
+ if (__LL_UART_IsDatLen9bitsEn(Instance)) {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ } else {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ //Receive data loop
+ while (RxXferCount) {
+ //Wait RxFIFO to be not empty
+ tickstart = LL_GetTick();
+
+ while (!__LL_UART_IsRxFIFONotEmpty(Instance)) {
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ //Read data from RxFIFO
+ if (pdata16bits) {
+ *pdata16bits++ = (uint16_t)(__LL_UART_RxBuf9bits_Read(Instance));
+ } else {
+ *pdata8bits++ = (uint8_t)(__LL_UART_RxBuf8bits_Read(Instance));
+ }
+
+ RxXferCount--;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param Instance Specifies UART peripheral
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_Transmit_IT(UART_TypeDef *Instance)
+{
+ /* Check the UART initiation struct allocation */
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ /* Enable Transmit Holding Register Empty Interrupt */
+ __LL_UART_TxHoldEmpyt_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param Instance Specifies UART peripheral
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_Receive_IT(UART_TypeDef *Instance)
+{
+ /* Check the UART initiation struct allocation */
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ /* RX data available interrupt */
+ __LL_UART_RxDatAvl_INT_En(Instance);
+
+ return LL_OK;
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+/**
+ * @brief UART LL Transmit by DMA
+ * @param Instance Specifies UART peripheral
+ * @param dma_user_cfg user dma config pointer
+ * @param huart uart transmit by DMA handle pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_Transmit_DMA(UART_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ UART_DMAHandleTypeDef *huart, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ huart->dma_tx_ch = DMA_CHANNEL_INVALID;
+ uint32_t tickstart;
+
+ /* Check the UART initiation struct allocation */
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if ((huart->buf == NULL) || (huart->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ //In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer
+ if (__LL_UART_IsDatLen9bitsEn(Instance) && __LL_UART_TxModeSta_Get(Instance)) {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) huart->buf;
+ } else {
+ pdata8bits = huart->buf;
+ pdata16bits = NULL;
+ }
+
+ if (pdata16bits) {
+ dma_user_cfg->dst_data_width = DMA_DST_TRANS_WIDTH_16b;
+ } else {
+ dma_user_cfg->dst_data_width = DMA_DST_TRANS_WIDTH_8b;
+ }
+
+ huart->Instance = Instance;
+ huart->TXdma_status = UART_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)huart;
+ dma_user_cfg->end_callback = LL_UART_DMA_TXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)huart;
+ dma_user_cfg->err_callback = LL_UART_DMA_TXCHErrorCallBck;
+
+ tickstart = LL_GetTick();
+
+ while (huart->dma_tx_ch == DMA_CHANNEL_INVALID) {
+ huart->dma_tx_ch = LL_UART_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ huart->TXdma_status = UART_DMA_STATE_READY;
+
+ if (pdata16bits) {
+ LL_DMA_Start_IT(DMA, huart->dma_tx_ch, (uint32_t)pdata16bits, (uint32_t)&Instance->THR, huart->buf_len);
+ } else {
+ LL_DMA_Start_IT(DMA, huart->dma_tx_ch, (uint32_t)pdata8bits, (uint32_t)&Instance->THR, huart->buf_len);
+ }
+
+ huart->TXdma_status = UART_DMA_STATE_BUSY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART LL Receive through DMA
+ * @param Instance Specifies UART peripheral
+ * @param huart uart transmit by DMA handle pointer
+ * @param dma_user_cfg user dma config pointer
+ * @param Timeout Limited operation time
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_Receive_DMA(UART_TypeDef *Instance, DMA_UserCfgTypeDef *dma_user_cfg,
+ UART_DMAHandleTypeDef *huart, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ huart->dma_rx_ch = DMA_CHANNEL_INVALID;
+ uint32_t tickstart;
+
+ /* Check the UART initiation struct allocation */
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if ((huart->buf == NULL) || (huart->buf_len == 0U)) {
+ return LL_ERROR;
+ }
+
+ //In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer
+ if (__LL_UART_IsDatLen9bitsEn(Instance)) {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) huart->buf;
+ } else {
+ pdata8bits = huart->buf;
+ pdata16bits = NULL;
+ }
+
+ if (pdata16bits) {
+ dma_user_cfg->src_data_width = DMA_SRC_TRANS_WIDTH_16b;
+ } else {
+ dma_user_cfg->src_data_width = DMA_SRC_TRANS_WIDTH_8b;
+ }
+
+ huart->Instance = Instance;
+ huart->RXdma_status = UART_DMA_STATE_RESET;
+
+ dma_user_cfg->end_arg = (void *)huart;
+ dma_user_cfg->end_callback = LL_UART_DMA_RXCHEndCallback;
+ dma_user_cfg->err_arg = (void *)huart;
+ dma_user_cfg->err_callback = LL_UART_DMA_RXCHErrorCallBck;
+
+ tickstart = LL_GetTick();
+
+ while (huart->dma_rx_ch == DMA_CHANNEL_INVALID) {
+ huart->dma_rx_ch = LL_UART_DMA_Init(dma_user_cfg);
+
+ if ((LL_GetTick() - tickstart) > Timeout) {
+ return LL_TIMEOUT;
+ }
+ }
+
+ huart->RXdma_status = UART_DMA_STATE_READY;
+
+ if (pdata16bits) {
+ LL_DMA_Start_IT(DMA, huart->dma_rx_ch, (uint32_t)&Instance->RBR, (uint32_t)pdata16bits, huart->buf_len);
+ } else {
+ LL_DMA_Start_IT(DMA, huart->dma_rx_ch, (uint32_t)&Instance->RBR, (uint32_t)pdata8bits, huart->buf_len);
+ }
+
+ huart->RXdma_status = UART_DMA_STATE_BUSY;
+
+ return LL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_LL_Exported_Functions_Group3 UART Misc Functions
+ * @brief UART Misc Functions
+ * @{
+ */
+
+/**
+ * @brief UART LL 9BIT Transmit Addr Send
+ * @param Instance Specifies UART peripheral
+ * @param TxAddr 9BIT Transmit Addr Send
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_Uart_9bit_SendAddress(UART_TypeDef *Instance, uint8_t TxAddr)
+{
+ /* Check the UART initiation struct allocation */
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (__LL_UART_IsDatLen9bitsEn(Instance)) {
+ if (!(__LL_UART_TxModeSta_Get(Instance))) {
+ /* Transmit Address set */
+ __LL_UART_TAR_Set(Instance, TxAddr);
+ /* Send address */
+ __LL_UART_SendAddr_Start(Instance);
+ return LL_OK;
+ } else {
+ __LL_UART_TxBuf9bits_Write(Instance, TxAddr | UART_THR_MSB_9thbit);
+ __LL_UART_SendDat_Start(Instance);
+ return LL_OK;
+ }
+
+ } else {
+ return LL_ERROR;
+ }
+}
+
+
+/**
+ * @brief UART LL RS485 Config
+ * @param Instance Specifies UART peripheral
+ * @param Cfg RS485 config pointer
+ @note The receive funtion is Enable by default
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_RS485Cfg(UART_TypeDef *Instance, UART_Rs485CfgTypeDef *Cfg)
+{
+ /* Check the UART initiation struct allocation */
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ //RS485 mode enable
+ __LL_UART_RS485Mode_En(Instance);
+
+ //DE signal enable and palarity config
+ UART_FUNC_ALTER(Cfg->de_en == ENABLE, __LL_UART_DE_En(Instance), __LL_UART_DE_Dis(Instance));
+
+ /* The receive funtion is Enable by default*/
+ __LL_UART_RE_En(Instance);
+
+ UART_FUNC_ALTER(Cfg->de_polarity == UART_DE_POL_ACT_LOW, __LL_UART_DE_ActLow_Set(Instance), __LL_UART_DE_ActHigh_Set(Instance));
+
+ //DE assert/deassert time config
+ __LL_UART_DE_AssertTime_Set(Instance, Cfg->de_assert_time);
+ __LL_UART_DE_DeAssertTime_Set(Instance, Cfg->de_deassert_time);
+
+ return LL_OK;
+}
+
+/**
+ * @brief This indicates the number of data entries in the transmit FIFO
+ * @param Instance UART peripheral
+ * @return the number of data entries in the transmit FIFO
+ */
+uint8_t LL_UART_TxFIFOLVL_GET(UART_TypeDef *Instance)
+{
+ return __LL_UART_TxFIFOLevel_Get(Instance);
+}
+
+/**
+ * @brief This indicates the number of data entries in the receive FIFO.
+ * @param Instance UART peripheral
+ * @return the number of data entries in the receive FIFO.
+ */
+uint8_t LL_UART_RxFIFOLVL_GET(UART_TypeDef *Instance)
+{
+ return __LL_UART_RxFIFOLevel_Get(Instance);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_LL_Exported_Functions_Interrupt UART Interrupt handler and callback
+ * @brief UART Interrupt handler and callback
+ * @{
+ */
+
+/**
+ * @brief UART LL IRQ Handler
+ * @param Instance &#&
+ * @return None
+ */
+void LL_UART_IRQHandler(UART_TypeDef *Instance)
+{
+ uint8_t int_id = __LL_UART_INT_ID_Get(Instance);
+
+ switch (int_id) {
+ case UART_INT_ID_MODEM_STA:
+ LL_UART_ModemStaCallback(Instance);
+ break;
+
+ case UART_INT_ID_TX_EMPTY:
+ LL_UART_TxEmptyCallback(Instance);
+ break;
+
+ case UART_INT_ID_RX_AVL:
+ LL_UART_RxAvailableCallback(Instance);
+ break;
+
+ case UART_INT_ID_RX_LINE_STA:
+ LL_UART_RxLineStaCallback(Instance);
+ break;
+
+ case UART_INT_ID_BUSY_DET:
+ LL_UART_BusyDetCallback(Instance);
+ break;
+
+ case UART_INT_ID_CHAR_TIMEOUT:
+ LL_UART_CharTimeOutCallback(Instance);
+ break;
+
+ default:
+ LOG_E("Error interrupt ID!\n");
+ break;
+ }
+}
+
+
+/**
+ * @brief UART LL Modem Status Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_ModemStaCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_ModemStaCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Tx Empty Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_TxEmptyCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_TxEmptyCallback could be implemented in the user file
+ */
+
+}
+
+/**
+ * @brief UART LL Rx Available Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxAvailableCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxAvailableCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL RX Line Status Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxLineStaCallback(UART_TypeDef *Instance)
+{
+ uint32_t line_sta = __LL_UART_LineSta_Get(Instance);
+
+ if (line_sta & UART_LSR_RFE_Msk) {
+ if (line_sta & UART_LSR_BI_Msk) {
+ LL_UART_BreakErrCallback(Instance);
+ }
+
+ if (line_sta & UART_LSR_FE_Msk) {
+ LL_UART_FrameErrCallback(Instance);
+ }
+
+ if (line_sta & UART_LSR_PE_Msk) {
+ LL_UART_ParityErrCallback(Instance);
+ }
+
+ if (line_sta & UART_LSR_OE_Msk) {
+ LL_UART_RxOverrunErrCallback(Instance);
+ }
+ }
+}
+
+/**
+ * @brief UART LL Busy Detect Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_BusyDetCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_BusyDetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Character Timeout Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_CharTimeOutCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_CharTimeOutCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief UART LL Break Error Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_BreakErrCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_BreakErrCallback could be implemented in the user file
+ */
+
+}
+
+/**
+ * @brief UART LL Frame Error Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_FrameErrCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_FrameErrCallback could be implemented in the user file
+ */
+
+}
+
+/**
+ * @brief UART LL Parity Error Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_ParityErrCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_ParityErrCallback could be implemented in the user file
+ */
+
+}
+
+/**
+ * @brief UART LL RX Overrun Error Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxOverrunErrCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxOverrunErrCallback could be implemented in the user file
+ */
+
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_LL_Private_Functions UART LL Private function
+ * @brief UART LL Private function
+ * @{
+ */
+
+
+#ifdef LL_DMA_MODULE_ENABLED
+/**
+ * @brief UART LL DMA Init
+ * @param dma_user_cfg user dma config pointer
+ * @param Timeout Limited operation time
+ * @return DMA_ChannelETypeDef
+ */
+DMA_ChannelETypeDef LL_UART_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg)
+{
+ DMA_ChannelETypeDef ch = DMA_CHANNEL_INVALID;
+ int ret;
+
+ /* User DAM channel request */
+ ch = LL_DMA_ChannelRequest();
+
+ if (ch == DMA_CHANNEL_INVALID) {
+ LOG_E("Requset DMA channel Fail!\n");
+ return DMA_CHANNEL_INVALID;
+ }
+
+ /* User DMA init */
+ ret = LL_DMA_Init(DMA, ch, dma_user_cfg);
+
+ if (ret) {
+ LOG_E("DMA LL init fail!\n");
+ LL_DMA_ChannelRelease(ch);
+ ch = DMA_CHANNEL_INVALID;
+ return DMA_CHANNEL_INVALID;
+ }
+
+ return ch;
+}
+
+/**
+ * @brief UART LL DMA Deinit
+ * @param Instance Specifies UART peripheral
+ * @param frame frame pointer
+ * @return LL_StatusETypeDef
+ */
+LL_StatusETypeDef LL_UART_DMA_Deinit(DMA_ChannelETypeDef ch)
+{
+ /* Deinit DMA after tranfer completed */
+ LL_DMA_DeInit(DMA, ch);
+
+ /* DMA LL channel release */
+ LL_DMA_ChannelRelease(ch);
+
+ /* DMA stop work */
+ LL_DMA_Stop_IT(DMA, ch);
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART DMA TX Channel complete callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+void LL_UART_DMA_TXCHEndCallback(void *arg)
+{
+ UART_DMAHandleTypeDef *p_frame = ((UART_DMAHandleTypeDef *)arg);
+
+ /* Wait for UART Transmit completed */
+ while (!__LL_UART_IsTxEmpty(p_frame->Instance));
+
+ /* UART LL DMA Deinit */
+ LL_UART_DMA_Deinit(p_frame->dma_tx_ch);
+
+ /* Disable Transmit DMA func */
+ p_frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been finished */
+ p_frame->TXdma_status = UART_DMA_STATE_FINISH;
+}
+
+/**
+ * @brief UART DMA RX Channel complete callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+void LL_UART_DMA_RXCHEndCallback(void *arg)
+{
+ UART_DMAHandleTypeDef *p_frame = ((UART_DMAHandleTypeDef *)arg);
+
+ /* UART LL DMA Deinit */
+ LL_UART_DMA_Deinit(p_frame->dma_rx_ch);
+
+ p_frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been finished */
+ p_frame->RXdma_status = UART_DMA_STATE_FINISH;
+}
+
+/**
+ * @brief UART DMA TX Channel Error callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+void LL_UART_DMA_TXCHErrorCallBck(void *arg)
+{
+ UART_DMAHandleTypeDef *p_frame = ((UART_DMAHandleTypeDef *)arg);
+
+ /* UART LL DMA Deinit */
+ LL_UART_DMA_Deinit(p_frame->dma_tx_ch);
+
+ p_frame->dma_tx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been Error */
+ p_frame->TXdma_status = UART_DMA_STATE_ERROR;
+}
+
+/**
+ * @brief UART DMA RX Channel Error callback
+ * @param arg Unlimited parameter
+ * @return None
+ */
+void LL_UART_DMA_RXCHErrorCallBck(void *arg)
+{
+ UART_DMAHandleTypeDef *p_frame = ((UART_DMAHandleTypeDef *)arg);
+
+ /* UART LL DMA Deinit */
+ LL_UART_DMA_Deinit(p_frame->dma_rx_ch);
+
+ p_frame->dma_rx_ch = DMA_CHANNEL_INVALID;
+
+ /* process has been Error */
+ p_frame->RXdma_status = UART_DMA_STATE_ERROR;
+}
+
+#endif /* LL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+
+#endif /* LL_UART_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_usb.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_usb.c
new file mode 100644
index 0000000000..a3248f562a
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_usb.c
@@ -0,0 +1,558 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_usb.c
+ * @author MCD Application Team
+ * @brief USB LL Module Driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "USB LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup USB_LL USB LL
+ * @brief USB LL Module Driver.
+ * @{
+ */
+
+
+#ifdef LL_USB_MODULE_ENABLED
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Functions USB LL Exported Functions
+ * @brief USB LL Exported Functions
+ * @{
+ */
+
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the USB
+ to be ready for use.
+
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the USB peripheral
+ * @param Instance Specifies USB peripheral
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_USB_Init(USB_TypeDef *Instance)
+{
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_USB_MspInit(Instance);
+
+ //USB Hardware Config
+ __LL_USB_DMOutputHardware(Instance);
+ __LL_USB_DPOutputHardware(Instance);
+ __LL_USB_DMInputHardware(Instance);
+ __LL_USB_DPInputHardware(Instance);
+
+ __LL_USB_DMPullDownDisable(Instance);
+ __LL_USB_DMPullUpNormal(Instance);
+ __LL_USB_DPPullDownDisable(Instance);
+ __LL_USB_DPPullUpNormal(Instance);
+
+ __LL_USB_VbusValidThreshold_Set(Instance);
+ __LL_USB_VbusAboveAdevSessThres_Set(Instance);
+ __LL_USB_VbusAboveSessEndThres_Set(Instance);
+ __LL_USB_MiniABConnectorID_Set(Instance);
+ __LL_USB_PHY_En(Instance);
+
+ //USB Power Control
+ __LL_USB_SoftConn_En(Instance);
+ __LL_USB_HighSpeed_Dis(Instance);
+ __LL_USB_SuspendDMOut_En(Instance);
+
+ //USB Detect Interrupt Config
+ __LL_USB_DebouceMax_Set(Instance, 0x80);
+ __LL_USB_Conn_Clr(Instance);
+ __LL_USB_Conn_Int_En(Instance);
+ __LL_USB_Disconn_Clr(Instance);
+ __LL_USB_Disconn_Int_En(Instance);
+
+ //USB Interrupt Enable
+ __LL_USB_Int_EN(Instance, USB_CTRL_INT_ALL_Msk);
+ __LL_USB_EP0AndEPxTX_Int_EN(Instance, EP_NUM_0);
+
+ //USB INT Send To CPU Config
+ __LL_USB_INTSendToCPU_En(Instance, USB_CTRL_INT_TO_CPU_Msk);
+ __LL_USB_INTSendToCPU_En(Instance, USB_EP_INT_TO_CPU_Msk);
+ __LL_USB_INTSendToCPU_En(Instance, USB_LPM_INT_TO_CPU_Msk);
+
+ return LL_OK;
+}
+
+/**
+ * @brief DeInitializes the USB peripheral
+ * @param Instance Specifies USB peripheral
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_USB_DeInit(USB_TypeDef *Instance)
+{
+ //USB INT Send To CPU Config
+ __LL_USB_INTSendToCPU_Dis(Instance, USB_CTRL_INT_TO_CPU_Msk);
+ __LL_USB_INTSendToCPU_Dis(Instance, USB_EP_INT_TO_CPU_Msk);
+ __LL_USB_INTSendToCPU_Dis(Instance, USB_LPM_INT_TO_CPU_Msk);
+
+ //USB Interrupt Disable
+ __LL_USB_Int_Dis(Instance, USB_CTRL_INT_ALL_Msk);
+ __LL_USB_EP0AndEPxTX_Int_Dis(Instance, EP_NUM_0);
+
+ //USB Detect Interrupt Config
+ __LL_USB_Conn_Clr(Instance);
+ __LL_USB_Conn_Int_Dis(Instance);
+ __LL_USB_Disconn_Clr(Instance);
+ __LL_USB_Disconn_Int_Dis(Instance);
+
+ //USB Power Control
+ __LL_USB_SoftConn_Dis(Instance);
+ __LL_USB_SuspendDMOut_Dis(Instance);
+
+ //USB Hardware Config
+ __LL_USB_DMOutputNormal(Instance);
+ __LL_USB_DPOutputNormal(Instance);
+ __LL_USB_DMInputNormal(Instance);
+ __LL_USB_DPInputNormal(Instance);
+ __LL_USB_DMPullDownNormal(Instance);
+ __LL_USB_DMPullUpNormal(Instance);
+ __LL_USB_DPPullDownNormal(Instance);
+ __LL_USB_DPPullUpNormal(Instance);
+
+ __LL_USB_VbusValidThreshold_Clr(Instance);
+ __LL_USB_VbusAboveAdevSessThres_Clr(Instance);
+ __LL_USB_VbusAboveSessEndThres_Clr(Instance);
+ __LL_USB_MiniABConnectorID_Clr(Instance);
+ __LL_USB_PHY_Dis(Instance);
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_USB_MspDeInit(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the USB MSP.
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_MspInit(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the USB MSP
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_MspDeInit(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_MspDeInit could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_LL_Exported_Functions_Group2 USB Controler Initerrupt Management
+ * @brief USB Controler Initerrupt Management
+ *
+ @verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides USB Controler IRQ handler function.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief LL USB Controler IRQ Handler
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+void LL_USB_CtrlIRQHandler(USB_TypeDef *Instance)
+{
+ uint8_t usb_ctrl_int_sta = __LL_USB_IntSta_Get(Instance);
+
+ if (usb_ctrl_int_sta & USB_SUSPEND_INT_STA_Msk) {
+ LL_USB_CtrlSuspendCallback(Instance);
+ }
+
+ if (usb_ctrl_int_sta & USB_RESUME_INT_STA_Msk) {
+ LL_USB_CtrlResumeCallback(Instance);
+ }
+
+ if (usb_ctrl_int_sta & USB_RST_INT_STA_Msk) {
+ LL_USB_CtrlResetCallback(Instance);
+ }
+
+ if (usb_ctrl_int_sta & USB_SOF_INT_STA_Msk) {
+ LL_USB_CtrlSofCallback(Instance);
+ }
+
+ if (usb_ctrl_int_sta & USB_SESS_END_INT_STA_Msk) {
+ LL_USB_CtrlSessEndCallback(Instance);
+ }
+}
+
+/**
+ * @brief USB Controler Suspend Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_CtrlSuspendCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_CtrlSuspendCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Controler Resume Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_CtrlResumeCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_CtrlResumeCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Controler Reset Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_CtrlResetCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_CtrlResetCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Controler SOF Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_CtrlSofCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_CtrlSofCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Controler Session End Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_CtrlSessEndCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_CtrlSessEndCallback could be implemented in the USB Middleware file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_LL_Exported_Functions_Group3 USB Detect Initerrupt Management
+ * @brief USB Detect Initerrupt Management
+ *
+ @verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides USB Detect IRQ handler function.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief LL USB Detect IRQ Handler
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+void LL_USB_DetIRQHandler(USB_TypeDef *Instance)
+{
+ if (__LL_USB_IsConn(Instance)) {
+ __LL_USB_Conn_Clr(Instance);
+ LL_USB_DetConnectCallback(Instance);
+ }
+
+ if (__LL_USB_IsDisconn(Instance)) {
+ __LL_USB_Disconn_Clr(Instance);
+ LL_USB_DetDisonnectCallback(Instance);
+ }
+}
+
+/**
+ * @brief USB Detect Connect Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_DetConnectCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_DetConnectCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Detect Disconnect Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_DetDisonnectCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_DetDisonnectCallback could be implemented in the USB Middleware file
+ */
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_LL_Exported_Functions_Group4 USB Endpoint Initerrupt Management
+ * @brief USB Endpoint Initerrupt Management
+ *
+ @verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides USB Endpoint IRQ handler function.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief LL USB Endpoint IRQ Handler
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+void LL_USB_EpIRQHandler(USB_TypeDef *Instance)
+{
+ uint8_t ep0_epxtx_int_sta, epx_rx_int_sta;
+
+ //Get all endpoint interrupt status
+ epx_rx_int_sta = __LL_USB_EPx_RXIntSta_Get(Instance);
+ ep0_epxtx_int_sta = __LL_USB_EP0AndEPxTX_IntSta_Get(Instance);
+
+ if (ep0_epxtx_int_sta & USB_EP0_INT_STA_Msk) { /* Endpoint 0 Interrupt */
+ //USB Endpoint Index Set
+ __LL_USB_EPIndex_Set(Instance, EP_NUM_0);
+
+ if (__LL_USB_IsSetupPacket(Instance) && __LL_USB_EP0_IsRXPktRdy(Instance)) { //Endpoint 0 Setup
+ LL_USB_Ep0SetupCallback(Instance);
+ } else if (__LL_USB_IsInPacket(Instance)) { //Endpoint 0 IN
+ LL_USB_Ep0InCallback(Instance);
+ } else if (__LL_USB_IsOutPacket(Instance) && __LL_USB_EP0_IsRXPktRdy(Instance)) { //Endpoint 0 OUT
+ LL_USB_Ep0OutCallback(Instance);
+ }
+ } else if (ep0_epxtx_int_sta & USB_TX_EP1_INT_STA_Msk) { /* Endpoint 1 IN Interrupt */
+ //USB Endpoint Index Set
+ __LL_USB_EPIndex_Set(Instance, EP_NUM_1);
+ LL_USB_Ep1InCallback(Instance);
+ } else if (ep0_epxtx_int_sta & USB_TX_EP2_INT_STA_Msk) { /* Endpoint 2 IN Interrupt */
+ //USB Endpoint Index Set
+ __LL_USB_EPIndex_Set(Instance, EP_NUM_2);
+ LL_USB_Ep2InCallback(Instance);
+ } else if (epx_rx_int_sta & USB_RX_EP1_INT_STA_Msk) { /* Endpoint 1 OUT Interrupt */
+ //USB Endpoint Index Set
+ __LL_USB_EPIndex_Set(Instance, EP_NUM_1);
+ LL_USB_Ep1OutCallback(Instance);
+ } else if (epx_rx_int_sta & USB_RX_EP2_INT_STA_Msk) { /* Endpoint 2 OUT Interrupt */
+ //USB Endpoint Index Set
+ __LL_USB_EPIndex_Set(Instance, EP_NUM_2);
+ LL_USB_Ep2OutCallback(Instance);
+ }
+}
+
+/**
+ * @brief USB Endpoint 0 Setup Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_Ep0SetupCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_Ep0SetupCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Endpoint 0 In Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_Ep0InCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_Ep0InCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Endpoint 0 Out Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_Ep0OutCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_Ep0OutCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Endpoint 1 In Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_Ep1InCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_Ep1InCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Endpoint 1 Out Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_Ep1OutCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_Ep1OutCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Endpoint 2 In Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_Ep2InCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_Ep2InCallback could be implemented in the USB Middleware file
+ */
+}
+
+/**
+ * @brief USB Endpoint 2 Out Callback
+ * @param Instance Specifies USB peripheral
+ * @return None
+ */
+__WEAK void LL_USB_Ep2OutCallback(USB_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_USB_Ep2OutCallback could be implemented in the USB Middleware file
+ */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_USB_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_wwdg.c b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_wwdg.c
new file mode 100644
index 0000000000..5f95852d46
--- /dev/null
+++ b/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_wwdg.c
@@ -0,0 +1,268 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_wwdg.c
+ * @author MCD Application Team
+ * @brief WWDG LL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Window Watchdog (WWDG) peripheral:
+ * + Initialization and de-initialization functions
+ * + Refresh function
+ * + Interrupt and Callback functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+
+
+#define DBG_TAG "WWDG LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup WWDG_LL WWDG LL
+ * @brief WWDG LL module driver
+ * @{
+ */
+
+#ifdef LL_WWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG LL Exported Functions
+ * @brief WWDG LL Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_LL_Exported_Functions_Group1 Initialization and De-Initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and De-Initialization functions #####
+ ==============================================================================
+ [..] This section provides a set of functions allowing to initialize and
+ deinitialize the WWDG peripheral
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the WWDG according to the specified.
+ * parameters in the WWDG_InitTypeDef of associated handle.
+ * @param Instance WWDG peripheral
+ * @param Init pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @return LL status
+ */
+LL_StatusETypeDef LL_WWDG_Init(WWDG_TypeDef *Instance, WWDG_InitTypeDef *Init)
+{
+ /* Check the WWDG handle allocation */
+ if (Init == NULL) {
+ return LL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(Instance));
+ assert_param(IS_WWDG_PRESCALER(Init->Prescaler));
+ assert_param(IS_WWDG_WINDOW(Init->Window));
+ assert_param(IS_WWDG_COUNTER(Init->Counter));
+
+ /* Handle Something */
+ LL_WWDG_MspInit(Instance);
+
+ /* Set WWDG Counter */
+ WRITE_REG(Instance->CVR, Init->Counter);
+
+ /* Set WWDG Prescaler */
+ WRITE_REG(Instance->PSCR, Init->Prescaler);
+
+ /* Set WWDG Window Val */
+ WRITE_REG(Instance->WVR, Init->Window);
+
+ /* SET Early Interrupt */
+ MODIFY_REG(Instance->CR, WWDG_CR_EWIE, Init->EWIMode);
+
+ /* Start WWDG Counter */
+ __LL_WWDG_ENABLE(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @brief De-initializes the WWDG peripheral.
+ * @param Instance WWDG peripheral
+ * @return status of the de-initialization
+ */
+LL_StatusETypeDef LL_WWDG_DeInit(WWDG_TypeDef *Instance)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(Instance));
+
+ /*Disable WWDG*/
+ __LL_WWDG_DISABLE(Instance);
+
+ /* Handle Something */
+ LL_WWDG_MspDeInit(Instance);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+__WEAK void LL_WWDG_MspInit(WWDG_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_WWDG_MspInit could be implemented in the user file
+ */
+}
+
+__WEAK void LL_WWDG_MspDeInit(WWDG_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_WWDG_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup WWDG_LL_Exported_Functions_Group2 WWDG Input and Output operation functions
+ * @brief WWDG Input and Output operation functions
+@verbatim
+ ===============================================================================
+ ##### Input and Output operation functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Refresh the WWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Refresh the WWDG.
+ * @param Instance WWDG peripheral
+ * @param Counter Counter value to refresh with
+ * @return LL status
+ */
+LL_StatusETypeDef LL_WWDG_Refresh(WWDG_TypeDef *Instance, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(Instance));
+ assert_param(IS_WWDG_COUNTER(Counter));
+
+ /* Write to WWDG CR the WWDG Counter value to refresh with */
+ __LL_WWDG_SET_COUNTER(Instance, Counter);
+
+ /* Return function status */
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup WWDG_LL_Exported_Functions_Interrupt WWDG Interrupt management
+ * @brief WWDG Initerrupt management
+@verbatim
+ ===============================================================================
+ ##### Initerrupt management #####
+ ===============================================================================
+ [..]
+ This section provides WWDG interrupt handler and callback functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle WWDG interrupt request.
+ * @param Instance: WWDG peripheral
+ * @return None
+ */
+void LL_WWDG_IRQHandler(WWDG_TypeDef *Instance)
+{
+ /* Check if Early Wakeup Interrupt is enable */
+ if ((__LL_WWDG_CHECK_IT_SOURCE(Instance, WWDG_IT_EWIE) != RESET) && (__LL_WWDG_GET_FLAG(Instance, WWDG_FLAG_EWIF) != RESET)) {
+
+ /* Clear Flag */
+ __LL_WWDG_CLEAR_FLAG(Instance, WWDG_FLAG_EWIF);
+
+ /* Early Wakeup callback */
+ LL_WWDG_EarlyWakeUpCallback(Instance);
+ }
+}
+
+/**
+ * @brief WWDG Early Wakeup callback.
+ * @param Instance WWDG peripheral
+ * @return None
+ */
+__WEAK void LL_WWDG_EarlyWakeUpCallback(WWDG_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_WWDG_EarlyWakeupCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+
+#endif /* LL_WWDG_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/README.md b/bsp/tae32f5300/README.md
new file mode 100644
index 0000000000..3dd03d29a2
--- /dev/null
+++ b/bsp/tae32f5300/README.md
@@ -0,0 +1,127 @@
+# 珠海泰为 TAE32F5300_EVAL_BOARD 开发板 BSP 说明
+
+## 简介
+
+本文档为 TAE32F5300_EVAL_BOARD 开发板的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+
+
+TAE32F5300_EVAL_BOARD 是珠海泰为官方推出的开发板，搭载 TAE32F5300 芯片，基于 ARM Cortex-M3 内核，最高主频 90 MHz，内置硬件加速器（ERPU），具有丰富的板载资源，包括 can 收发电路、485 收发电路，音频输入接口、USB 接口、LED、按键等。
+
+TAE32F5300_EVAL_BOARD 开发板常用 ** 板载资源 ** 如下：
+
+- MCU：TAE32F5300，主频 90MHz，75KBFLASH ，内置 16KB 容量数据 FLASH 存储器, 内置 16KB 系统 SRAM+8KB 算法 SRAM（两块 SRAM 4KB+4KB）
+- 板载资源
+ - 蜂鸣器
+ - USB
+ - LED
+ - 按键
+ - 音频输入口
+ - 可调电阻
+ - 温湿度传感器接口
+ - EEPROM
+ - 蓝牙模块接口
+ - RS485
+ - CAN
+ - uart lcd
+- 调试接口：标准 JTAG/SWD。
+
+开发板更多详细信息请参考珠海泰为 [TAE32F5300_EVAL_BOARD](http://www.tai-action.com/)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| ** 板载外设 ** | ** 支持情况 ** | ** 备注 ** |
+| :------------ | :-----------: | :-----------------------------------: |
+| LED | 支持 | LED |
+| ** 片上外设 ** | ** 支持情况 ** | ** 备注 ** |
+| :------------ | :-----------: | :-----------------------------------: |
+| GPIO | 支持 | PA0, PA1... PI15 ---> PIN: 0, 1...144 |
+| UART | 支持 | UART0~1 |
+| I2C | 支持 | 软件 I2C |
+| LED | 支持 | LED1~3 |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 工程，暂不支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+#### CMSIS-DAP 接线
+
+| TAE32 开发板 | CMSIS-DAP |
+| :---------- | :-------: |
+| SWDIO | SWDIO |
+| SWCLK | SWCLK |
+| VCC | 3.3v |
+| GND | GND |
+
+串口转 USB 接线
+
+| TAE32 开发板 | 串口转 USB |
+| :---------- | :-------: |
+| RXD(PA10) | TXD |
+| TXD(PA11) | RXD |
+| GND | GND |
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 CMSIS-DAP 下载程序，点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，PB6 每 500ms 闪烁一次。
+```
+ \ | /
+- RT - Thread Operating System
+ / | \ 4.0.4 build Aug 29 2021
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 0 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
+
+3. 输入 `pkgs --update` 命令更新软件包。
+
+4. 输入 `scons --target=mdk5` 命令重新生成工程。
+
+## 注意事项
+
+## 联系人信息
+
+维护人:
+
+- qinweizhong 邮箱：<369247354@qq.com>
\ No newline at end of file
diff --git a/bsp/tae32f5300/SConscript b/bsp/tae32f5300/SConscript
new file mode 100644
index 0000000000..24bb4646ab
--- /dev/null
+++ b/bsp/tae32f5300/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/tae32f5300/SConstruct b/bsp/tae32f5300/SConstruct
new file mode 100644
index 0000000000..64fb270f47
--- /dev/null
+++ b/bsp/tae32f5300/SConstruct
@@ -0,0 +1,43 @@
+import os
+import sys
+import rtconfig
+
+print("############sconstruct##############")
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print("Cannot found RT-Thread root directory, please check RTT_ROOT")
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'TAE32F53xx.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+print("######################env:")
+print(env)
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/tae32f5300/application/SConscript b/bsp/tae32f5300/application/SConscript
new file mode 100644
index 0000000000..6f66f7ab73
--- /dev/null
+++ b/bsp/tae32f5300/application/SConscript
@@ -0,0 +1,12 @@
+import rtconfig
+from building import *
+
+cwd = GetCurrentDir()
+CPPPATH = [cwd, str(Dir('#'))]
+src = Split("""
+main.c
+""")
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/tae32f5300/application/main.c b/bsp/tae32f5300/application/main.c
new file mode 100644
index 0000000000..f86f07e29b
--- /dev/null
+++ b/bsp/tae32f5300/application/main.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-05 qinweizhong add support for tae32
+ */
+#include "rtthread.h"
+#include "board.h"
+
+#define LED_PIN 42
+
+int main(void)
+{
+ int count = 1;
+ rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+ while (count++)
+ {
+ rt_pin_write(LED_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+
+ rt_kprintf("count %d\r\n", count);
+ }
+}
diff --git a/bsp/tae32f5300/application/main.h b/bsp/tae32f5300/application/main.h
new file mode 100644
index 0000000000..059031647f
--- /dev/null
+++ b/bsp/tae32f5300/application/main.h
@@ -0,0 +1,73 @@
+/**
+ ******************************************************************************
+ * @file main.h
+ * @author MCD Application Team
+ * @brief Header for main.c module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_ll.h"
+//#include "dbg/user_debug.h"
+#include
+
+
+/** @addtogroup TAE32F53xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32F53xx_Template
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _MAIN_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/board/SConscript b/bsp/tae32f5300/board/SConscript
new file mode 100644
index 0000000000..6b3f27dfb0
--- /dev/null
+++ b/bsp/tae32f5300/board/SConscript
@@ -0,0 +1,17 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general board.
+src = Split("""
+board.c
+tae32f53xx_ll_msp.c
+""")
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/tae32f5300/board/board.c b/bsp/tae32f5300/board/board.c
new file mode 100644
index 0000000000..8bec0168d2
--- /dev/null
+++ b/bsp/tae32f5300/board/board.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-05 qinweizhong add support for tae32
+ */
+#include "board.h"
+
+#define _SCB_BASE (0xE000E010UL)
+#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0))
+#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4))
+#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8))
+#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC))
+#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL))
+
+static uint32_t _SysTick_Config(rt_uint32_t ticks)
+{
+ if ((ticks - 1) > 0xFFFFFF)
+ {
+ return 1;
+ }
+
+ _SYSTICK_LOAD = ticks - 1;
+ _SYSTICK_PRI = 0x01;
+ _SYSTICK_VAL = 0;
+ _SYSTICK_CTRL = 0x07;
+
+ return 0;
+}
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+#define RT_HEAP_SIZE 2048
+static uint32_t rt_heap[RT_HEAP_SIZE];/* heap default size: 4K(1024 * 4)*/
+RT_WEAK void *rt_heap_begin_get(void)
+{
+ return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+ return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init()
+{
+ /* System Clock Update */
+ SystemClock_Config();
+ /* System Tick Configuration */
+ LL_Init();
+ _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+ /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+ rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+
+void rt_hw_console_output(const char *str)
+{
+ rt_size_t i = 0, size = 0;
+ char a = '\r';
+
+ size = rt_strlen(str);
+ for (i = 0; i < size; i++)
+ {
+ if (*(str + i) == '\n')
+ {
+ /*Wait TXFIFO to be no full*/
+ while (!__LL_UART_IsTxFIFONotFull(UART0)) {};
+
+ /*Send data to UART*/
+ __LL_UART_TxBuf9bits_Write(UART0, (uint16_t)a);
+ }
+ while (!__LL_UART_IsTxFIFONotFull(UART0)) {};
+
+ /*Send data to UART*/
+ __LL_UART_TxBuf9bits_Write(UART0, (uint16_t)(*(str + i)));
+ }
+}
+
+char rt_hw_console_getchar(void)
+{
+ /* note: ch default value < 0 */
+ int ch = -1;
+ if (__LL_UART_IsDatReady(UART0))
+ {
+ /* receive data */
+ ch = __LL_UART_RxBuf9bits_Read(UART0);
+ }
+ else
+ {
+ rt_thread_mdelay(10);
+ }
+ return ch;
+}
+
+void SystemClock_Config(void)
+{
+ LL_StatusETypeDef ret;
+ SYSCTRL_SysclkUserCfgTypeDef sysclk_cfg;
+
+ /*FPLL0 Init*/
+ LL_FPLL_Init(FPLL0);
+
+ /*SYSCLK Clock Config*/
+ sysclk_cfg.sysclk_src = SYSCLK_SRC_PLL0DivClk;
+ sysclk_cfg.sysclk_freq = 90000000UL;
+ sysclk_cfg.pll0clk_src = PLLCLK_SRC_XOSC;
+ sysclk_cfg.pll0clk_src_freq = HSE_VALUE;
+ sysclk_cfg.apb0_clk_div = SYSCTRL_CLK_DIV_1;
+ sysclk_cfg.apb1_clk_div = SYSCTRL_CLK_DIV_1;
+ ret = LL_SYSCTRL_SysclkInit(SYSCTRL, &sysclk_cfg);
+
+ if (ret == LL_OK)
+ {
+ SystemCoreClockUpdate(sysclk_cfg.sysclk_freq);
+ }
+
+ /*eFlash Memory CLK Source and Div Config*/
+ LL_SYSCTRL_EFLASH_ClkCfg(EFLASH_CLK_SRC_PLL0DivClk, SYSCTRL_CLK_DIV_9);
+}
diff --git a/bsp/tae32f5300/board/board.h b/bsp/tae32f5300/board/board.h
new file mode 100644
index 0000000000..cf06e44330
--- /dev/null
+++ b/bsp/tae32f5300/board/board.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-05 qinweizhong add support for tae32
+ */
+
+#include
+#include
+#include
+#include
+
+#include "main.h"
+#include "tae32f53xx.h"
+
+void SystemClock_Config(void);
diff --git a/bsp/tae32f5300/board/dbg/tae32f53xx_dbg.h b/bsp/tae32f5300/board/dbg/tae32f53xx_dbg.h
new file mode 100644
index 0000000000..5358f8076e
--- /dev/null
+++ b/bsp/tae32f5300/board/dbg/tae32f53xx_dbg.h
@@ -0,0 +1,258 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_dbg.h
+ * @author MCD Application Team
+ * @brief The macro definitions for dbg
+ *
+ ==============================================================================
+ ##### How to use #####
+ ==============================================================================
+ *
+ * If you want to use debug macro, you can use as following steps:
+ *
+ * Step 1: Macros in "tae32f53xx_dbg_conf.h"
+ * a. Define the TAE_USING_DBG to enable the feature
+ * #define TAE_USING_DBG
+ *
+ * b. Define the print interface for dbg
+ * #define TAE_DBG_PRINT(...) printf(__VA_ARGS__)
+ *
+ * c. Other optional macros define, such as TAE_USING_DBG_COLOR
+ *
+ * Step 2: Macros in your C/C++ file
+ * a. Define the debug tag and level for dbg. If you did not define this,
+ default definition will be used.
+ * #define DBG_TAG "TAG" // must be string
+ * #define DBG_LVL DBG_INFO // others DBG_ERROR, DBG_WARNING, DBG_LOG.
+ * DBG_LOG > DBG_INFO > DBG_WARNING > DBG_ERROR
+ *
+ * b. Include this header file
+ * #include "tae32f53xx_dbg.h" // this must after of DBG_LVL, DBG_TAG or other options
+ *
+ * Step 3: LOG_X macro to print out logs in your C/C++ file
+ * PLEASE NOTE: LOG_X is related to the DBG_LVL that defined in Step 2. Using LOG_X
+ * witch higher then DBG_LVL will be ignored.
+ * LOG_D("this is a debug log!");
+ * LOG_I("this is a info log!")
+ * LOG_W("this is a warning log!")
+ * LOG_E("this is a error log!");
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_DBG_H_
+#define _TAE32F53XX_DBG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tae32f53xx_dbg_conf.h"
+
+
+/** @addtogroup TAE_Utilities
+ * @{
+ */
+
+/** @defgroup TAE_Debug TAE Debug
+ * @brief TAE Debug
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TAE_Debug_Exported_Constants TAE Debug Exported Constants
+ * @brief TAE Debug Exported Constants
+ * @{
+ */
+
+#ifdef TAE_USING_DBG
+
+/* DEBUG level */
+#define DBG_NONE 0
+#define DBG_ERROR 1
+#define DBG_WARNING 2
+#define DBG_INFO 3
+#define DBG_LOG 4
+
+/* The color for terminal (foreground) */
+#define BLACK 30
+#define RED 31
+#define GREEN 32
+#define YELLOW 33
+#define BLUE 34
+#define PURPLE 35
+#define CYAN 36
+#define WHITE 37
+#define CLEAR_ALL 0
+
+#ifndef DBG_TAG
+#define DBG_TAG "DBG"
+#endif
+
+#ifndef DBG_LVL
+#define DBG_LVL DBG_WARNING
+#endif
+
+#ifndef TAE_DBG_PRINT
+#define TAE_DBG_PRINT(fmt, ...)
+#endif
+
+#endif /* TAE_USING_DBG */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TAE_Debug_Exported_Macros TAE Debug Exported Macros
+ * @brief TAE Debug Exported Macros
+ * @{
+ */
+
+#ifdef TAE_USING_DBG
+
+#ifdef TAE_USING_DBG_COLOR
+#define _DBG_COLOR(color) TAE_DBG_PRINT("\033["#color"m")
+#define _DBG_LOG_HEAD(lvl_name, color) TAE_DBG_PRINT("\033["#color"m[" lvl_name "@" DBG_TAG "] ")
+#define _DBG_LOG_END() TAE_DBG_PRINT("\033[0m")
+#else
+#define _DBG_COLOR(color)
+#define _DBG_LOG_HEAD(lvl_name, color) TAE_DBG_PRINT("[" lvl_name "@" DBG_TAG "] ")
+#define _DBG_LOG_END() TAE_DBG_PRINT("")
+#endif /* TAE_USING_DBG_COLOR */
+
+
+#define DBG_LogRaw(...) TAE_DBG_PRINT(__VA_ARGS__)
+
+#define DBG_Log(lvl_name, color, fmt, ...) \
+ do { \
+ _DBG_LOG_HEAD(lvl_name, color); \
+ TAE_DBG_PRINT(fmt, ##__VA_ARGS__); \
+ _DBG_COLOR(0); \
+ } while (0)
+
+#define DBG_LogLine(lvl_name, color, fmt, ...) \
+ do { \
+ _DBG_LOG_HEAD(lvl_name, color); \
+ TAE_DBG_PRINT(fmt, ##__VA_ARGS__); \
+ _DBG_COLOR(0); \
+ _DBG_LOG_END(); \
+ } while (0)
+
+#define DBG_Here() \
+ if ((DBG_LVL) >= DBG_INFO) { \
+ _DBG_LOG_HEAD("I", 32); \
+ TAE_DBG_PRINT("Here is %s:%d", __FUNCTION__, \
+ __LINE__); \
+ _DBG_COLOR(0); \
+ _DBG_LOG_END(); \
+ }
+
+#define DBG_Enter() \
+ if ((DBG_LVL) >= DBG_INFO) { \
+ _DBG_LOG_HEAD("I", 32); \
+ TAE_DBG_PRINT("Enter function %s", __FUNCTION__); \
+ _DBG_COLOR(0); \
+ _DBG_LOG_END(); \
+ }
+
+#define DBG_Exit() \
+ if ((DBG_LVL) >= DBG_INFO) { \
+ _DBG_LOG_HEAD("I", 32); \
+ TAE_DBG_PRINT("Exit function %s", __FUNCTION__); \
+ _DBG_COLOR(0); \
+ _DBG_LOG_END(); \
+ }
+
+#else
+
+#define DBG_Log(level, fmt, ...)
+#define DBG_LogLine(lvl_name, color, fmt, ...)
+#define DBG_LogRaw(...)
+#define DBG_Here()
+#define DBG_Enter()
+#define DBG_Exit()
+
+#endif /* TAE_USING_DBG */
+
+
+#if (DBG_LVL >= DBG_LOG)
+#define LOG_D(fmt, ...) DBG_LogLine("D", CLEAR_ALL, fmt, ##__VA_ARGS__)
+#else
+#define LOG_D(fmt, ...)
+#endif
+
+#if (DBG_LVL >= DBG_INFO)
+#define LOG_I(fmt, ...) DBG_LogLine("I", GREEN, fmt, ##__VA_ARGS__)
+#else
+#define LOG_I(fmt, ...)
+#endif
+
+#if (DBG_LVL >= DBG_WARNING)
+#define LOG_W(fmt, ...) DBG_LogLine("W", YELLOW, fmt, ##__VA_ARGS__)
+#else
+#define LOG_W(fmt, ...)
+#endif
+
+#if (DBG_LVL >= DBG_ERROR)
+#define LOG_E(fmt, ...) DBG_LogLine("E", RED, fmt, ##__VA_ARGS__)
+#else
+#define LOG_E(fmt, ...)
+#endif
+
+#define LOG_R(...) DBG_LogRaw(__VA_ARGS__)
+
+#define LOG_Enter() DBG_Enter()
+
+#define LOG_Exit() DBG_Exit()
+
+#define LOG_Here() DBG_Here()
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_DBG_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/board/linker_scripts/link.icf b/bsp/tae32f5300/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..3a80cf803b
--- /dev/null
+++ b/bsp/tae32f5300/board/linker_scripts/link.icf
@@ -0,0 +1,65 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x1FFFFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_IRAM3_start__ = 0x20020000;
+define symbol __ICFEDIT_region_IRAM3_end__ = 0x2003FFFF;
+define symbol __ICFEDIT_region_IRAM4_start__ = 0x20040000;
+define symbol __ICFEDIT_region_IRAM4_end__ = 0x20057FFF;
+define symbol __ICFEDIT_region_IRAM5_start__ = 0x20058000;
+define symbol __ICFEDIT_region_IRAM5_end__ = 0x2005FFFF;
+define symbol __ICFEDIT_region_IRAM6_start__ = 0x200F0000;
+define symbol __ICFEDIT_region_IRAM6_end__ = 0x200F0FFF;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+
+define symbol __ICFEDIT_region_RAM_end__ = __ICFEDIT_region_IRAM6_end__;
+export symbol __ICFEDIT_region_RAM_end__;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2100;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__ = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]
+ | mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__]
+ | mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__]
+ | mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__]
+ | mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, last block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/tae32f5300/board/linker_scripts/link.lds b/bsp/tae32f5300/board/linker_scripts/link.lds
new file mode 100644
index 0000000000..af109a6da6
--- /dev/null
+++ b/bsp/tae32f5300/board/linker_scripts/link.lds
@@ -0,0 +1,203 @@
+ /**
+ *******************************************************************************
+ * @file hc32f4a0_flash.lds
+ * @brief Linker script for HC32F4A0 Device with 2MByte FLASH, 512KByte RAM.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2020-09-15 Chengy First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by HDSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/* Use contiguous memory regions for simple. */
+MEMORY
+{
+ FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M
+ OTP (rx): ORIGIN = 0x03000000, LENGTH = 6876
+ RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
+ RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .vectors :
+ {
+ . = ALIGN(4);
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ } >FLASH
+
+ .icg_sec 0x00000400 :
+ {
+ KEEP(*(.icg_sec))
+ } >FLASH
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text)
+ *(.text*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.eh_frame)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+ . = ALIGN(4);
+ } >FLASH
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } >FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >FLASH
+ __exidx_end = .;
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ __etext = ALIGN(4);
+
+ .otp_sec :
+ {
+ KEEP(*(.otp_sec))
+ } >OTP
+
+ .otp_lock_sec 0x03001800 :
+ {
+ KEEP(*(.otp_lock_sec))
+ } >OTP
+
+ .data : AT (__etext)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data*)
+ . = ALIGN(4);
+ *(.ramfunc)
+ *(.ramfunc*)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } >RAM
+
+ __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
+ .ramb_data : AT (__etext_ramb)
+ {
+ . = ALIGN(4);
+ __data_start_ramb__ = .;
+ *(.ramb_data)
+ *(.ramb_data*)
+ . = ALIGN(4);
+ __data_end_ramb__ = .;
+ } >RAMB
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ __bss_end__ = _ebss;
+ } >RAM
+
+ .ramb_bss :
+ {
+ . = ALIGN(4);
+ __bss_start_ramb__ = .;
+ *(.ramb_bss)
+ *(.ramb_bss*)
+ . = ALIGN(4);
+ __bss_end_ramb__ = .;
+ } >RAMB
+
+ .heap_stack (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ PROVIDE(_end = .);
+ *(.heap*)
+ . = ALIGN(8);
+ __HeapLimit = .;
+
+ __StackLimit = .;
+ *(.stack*)
+ . = ALIGN(8);
+ __StackTop = .;
+ } >RAM
+
+ /DISCARD/ :
+ {
+ libc.a (*)
+ libm.a (*)
+ libgcc.a (*)
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ PROVIDE(_stack = __StackTop);
+ PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
+ PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
+
+ __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
+ ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
+}
diff --git a/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct b/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct
new file mode 100644
index 0000000000..b41d86675c
--- /dev/null
+++ b/bsp/tae32f5300/board/linker_scripts/tae32f53xx_ac5_flash.sct
@@ -0,0 +1,127 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; Flash Configuration
+; Flash Base Address <0x0-0xFFFFFFFF:8>
+; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x08000000
+#define __ROM_SIZE 0x00012C00
+
+/*--------------------- RAMCODE Section Configuration ------------------------
+; RAMCODE Configuration
+; RAMCODE in which MCU
+; <3=> TAE32F5300
+; <2=> TAE32F5600
+; RAMCODE Base Address is different in different MCUs
+; Unsupported if your MCU is not in the list
+; RAMCODE Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMCODE_BASE 0x18000000
+#define __RAMCODE_SIZE 0x00000000
+
+/*--------------------- Embedded RAMA Configuration --------------------------
+; RAMA Configuration
+; RAMA Base Address <0x0-0xFFFFFFFF:8>
+; RAMA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMA_BASE 0x20000000
+#define __RAMA_SIZE 0x00004000
+
+/*--------------------- Embedded RAMB Configuration --------------------------
+; RAMB Configuration
+; RAMB Base Address <0x0-0xFFFFFFFF:8>
+; RAMB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMB_BASE 0x20004000
+#define __RAMB_SIZE 0x00001000
+
+/*--------------------- Embedded RAMC Configuration --------------------------
+; RAMC Configuration
+; RAMC Base Address <0x0-0xFFFFFFFF:8>
+; RAMC Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMC_BASE 0x20005000
+#define __RAMC_SIZE 0x00001000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; Stack / Heap Configuration
+; Stack and Heap will be placed in RAMA
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000000
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAMA_BASE + __RAMA_SIZE) /* starts at end of RAMA */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAMA section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_CODE_BASE __RAMCODE_BASE
+#define __RW_CODE_SIZE __RAMCODE_SIZE
+
+#define __RW_BASE (__RAMA_BASE + __RAMCODE_SIZE)
+#define __RW_SIZE (__RAMA_SIZE - __RAMCODE_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+#if __RW_CODE_SIZE > 0
+ RW_CODE __RW_CODE_BASE __RW_CODE_SIZE {
+ *.o (RAMCODE)
+ }
+#endif
+
+ RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
+ *.o (SECTION_RAMA)
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+ RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
+ *.o (SECTION_RAMB)
+ }
+
+ RW_RAMC __RAMC_BASE __RAMC_SIZE { ; RWC region
+ *.o (SECTION_RAMC)
+ }
+}
+
diff --git a/bsp/tae32f5300/board/tae32f53xx_dbg_conf.h b/bsp/tae32f5300/board/tae32f53xx_dbg_conf.h
new file mode 100644
index 0000000000..f02e6b8f97
--- /dev/null
+++ b/bsp/tae32f5300/board/tae32f53xx_dbg_conf.h
@@ -0,0 +1,110 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_dbg_conf.h
+ * @author MCD Application Team
+ * @brief Configuration for dbg
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_DBG_CONF_H_
+#define _TAE32F53XX_DBG_CONF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include
+
+
+/** @addtogroup TAE32F53xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32F53xx_Template
+ * @{
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TAE32F53xx_Debug_Conf_Exported_Constants TAE32F53xx Debug Conf Exported Constants
+ * @brief TAE32F53xx Debug Conf Exported Constants
+ * @{
+ */
+
+/**
+ * @brief Define TAE_USING_DBG to enable dbg
+ */
+#define TAE_USING_DBG
+
+/**
+ * @brief Define TAE_USING_DBG_COLOR to enable dbg color mode
+ */
+//#define TAE_USING_DBG_COLOR
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TAE32F53xx_Debug_Conf_Exported_Macros TAE32F53xx Debug Conf Exported Macros
+ * @brief TAE32F53xx Debug Conf Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Define your own print interface here
+ */
+#ifdef TAE_USING_DBG
+#define TAE_DBG_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define TAE_DBG_PRINT(fmt, ...)
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_DBG_CONF_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/board/tae32f53xx_ll_conf.h b/bsp/tae32f5300/board/tae32f53xx_ll_conf.h
new file mode 100644
index 0000000000..2453f74d44
--- /dev/null
+++ b/bsp/tae32f5300/board/tae32f53xx_ll_conf.h
@@ -0,0 +1,305 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_conf.h
+ * @author MCD Application Team
+ * @brief LL configuration file.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _TAE32F53XX_LL_CONF_H_
+#define _TAE32F53XX_LL_CONF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup TAE32F53xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32F53xx_Template
+ * @{
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CONFIG_LL_Exported_Constants CONFIG LL Exported Constants
+ * @brief CONFIG LL Exported Constants
+ * @{
+ */
+
+/** @defgroup CONFIG_LL_Module_Selection CONFIG LL Module Selection
+ * @brief CONFIG LL Module Selection
+ * @note This is the list of modules to be used in the LL driver
+ * @{
+ */
+
+/* Internal Class Peripheral */
+#define LL_MODULE_ENABLED /*!< LL Module Enable */
+#define LL_CORTEX_MODULE_ENABLED /*!< Cortex Module Enable */
+#define LL_FPLL_MODULE_ENABLED /*!< FPLL Module Enable */
+#define LL_LVD_MODULE_ENABLED /*!< LVD Module Enable */
+#define LL_DMA_MODULE_ENABLED /*!< DMA Module Enable */
+#define LL_FLASH_MODULE_ENABLED /*!< FLASH Module Enable */
+#define LL_DFLASH_MODULE_ENABLED /*!< DFLASH Module Enable */
+#define LL_WWDG_MODULE_ENABLED /*!< WWDG Module Enable */
+#define LL_IWDG_MODULE_ENABLED /*!< IWDG Module Enable */
+#define LL_TMR_MODULE_ENABLED /*!< TMR Module Enable */
+#define LL_IIR_MODULE_ENABLED /*!< IIR Module Enable */
+
+/* Interface Class Peripheral */
+#define LL_GPIO_MODULE_ENABLED /*!< GPIO Module Enable */
+#define LL_UART_MODULE_ENABLED /*!< UART Module Enable */
+#define LL_I2C_MODULE_ENABLED /*!< I2C Module Enable */
+#define LL_CAN_MODULE_ENABLED /*!< CAN Module Enable */
+#define LL_DALI_MODULE_ENABLED /*!< DALI Module Enable */
+#define LL_USB_MODULE_ENABLED /*!< USB Module Enable */
+
+/* Analog Class Peripheral */
+#define LL_ADC_MODULE_ENABLED /*!< ADC Module Enable */
+#define LL_DAC_MODULE_ENABLED /*!< DAC Module Enable */
+#define LL_CMP_MODULE_ENABLED /*!< CMP Module Enable */
+#define LL_ECU_MODULE_ENABLED /*!< ECU Module Enable */
+#define LL_HRPWM_MODULE_ENABLED /*!< HRPWM Module Enable */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CONFIG_LL_Oscillator_Values_Adaptation CONFIG LL Oscillator Values Adaptation
+ * @brief CONFIG LL Oscillator Values Adaptation
+ * @{
+ */
+
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the FPLL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
+#endif
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the FPLL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
+#endif
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ * Defines the value of the Internal Low Speed oscillator in Hz.
+ * @note The real value may vary depending on the variations in voltage and temperature.
+ */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CONFIG_LL_System_Configuration CONFIG LL System Configuration
+ * @brief CONFIG LL System Configuration
+ * @note This is the LL system configuration section
+ * @{
+ */
+
+#define TICK_INT_PRIORITY 0x07U /*!< tick interrupt priority, set to lowest */
+#define USE_RTOS 0U /*!< Support for RTOS (Unsupported in current version) */
+#define PREFETCH_ENABLE 1U /*!< Flash prefetch feature */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stdbool.h"
+#include "tae32f53xx_ll_sysctrl.h"
+
+
+/* Internal Class Peripheral */
+#ifdef LL_CORTEX_MODULE_ENABLED
+#include "tae32f53xx_ll_cortex.h"
+#endif
+
+#ifdef LL_FPLL_MODULE_ENABLED
+#include "tae32f53xx_ll_fpll.h"
+#endif
+
+#ifdef LL_LVD_MODULE_ENABLED
+#include "tae32f53xx_ll_lvdctrl.h"
+#endif
+
+#ifdef LL_DMA_MODULE_ENABLED
+#include "tae32f53xx_ll_dma.h"
+#endif
+
+#ifdef LL_FLASH_MODULE_ENABLED
+#include "tae32f53xx_ll_flash.h"
+#endif
+
+#ifdef LL_DFLASH_MODULE_ENABLED
+#include "tae32f53xx_ll_dflash.h"
+#endif
+
+#ifdef LL_WWDG_MODULE_ENABLED
+#include "tae32f53xx_ll_wwdg.h"
+#endif
+
+#ifdef LL_IWDG_MODULE_ENABLED
+#include "tae32f53xx_ll_iwdg.h"
+#endif
+
+#ifdef LL_TMR_MODULE_ENABLED
+#include "tae32f53xx_ll_tmr.h"
+#endif
+
+#ifdef LL_IIR_MODULE_ENABLED
+#include "tae32f53xx_ll_iir.h"
+#endif
+
+
+/* Interface Class Peripheral */
+#ifdef LL_GPIO_MODULE_ENABLED
+#include "tae32f53xx_ll_gpio.h"
+#endif
+
+#ifdef LL_UART_MODULE_ENABLED
+#include "tae32f53xx_ll_uart.h"
+#endif
+
+#ifdef LL_I2C_MODULE_ENABLED
+#include "tae32f53xx_ll_i2c.h"
+#endif
+
+#ifdef LL_CAN_MODULE_ENABLED
+#include "tae32f53xx_ll_can.h"
+#endif
+
+#ifdef LL_DALI_MODULE_ENABLED
+#include "tae32f53xx_ll_dali.h"
+#endif
+
+#ifdef LL_USB_MODULE_ENABLED
+#include "tae32f53xx_ll_usb.h"
+#endif
+
+
+/* Analog Class Peripheral */
+#ifdef LL_ADC_MODULE_ENABLED
+#include "tae32f53xx_ll_adc.h"
+#endif
+
+#ifdef LL_DAC_MODULE_ENABLED
+#include "tae32f53xx_ll_dac.h"
+#endif
+
+#ifdef LL_CMP_MODULE_ENABLED
+#include "tae32f53xx_ll_cmp.h"
+#endif
+
+#ifdef LL_ECU_MODULE_ENABLED
+#include "tae32f53xx_ll_ecu.h"
+#endif
+
+#ifdef LL_HRPWM_MODULE_ENABLED
+#include "tae32f53xx_ll_hrpwm.h"
+#endif
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CONFIG_LL_Exported_Macros CONFIG LL Exported Macros
+ * @brief CONFIG LL Exported Macros
+ * @{
+ */
+
+/** @defgroup CONFIG_LL_Assert_Selection CONFIG LL Assert Selection
+ * @brief CONFIG LL Assert Selection
+ * @{
+ */
+
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the LL drivers code
+ */
+//#define USE_FULL_ASSERT
+
+
+#ifdef USE_FULL_ASSERT
+
+void assert_failed(uint8_t *file, uint32_t line);
+
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions ------------------------------------------------------- */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32F53XX_LL_CONF_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/board/tae32f53xx_ll_msp.c b/bsp/tae32f5300/board/tae32f53xx_ll_msp.c
new file mode 100644
index 0000000000..2e5ffea7d1
--- /dev/null
+++ b/bsp/tae32f5300/board/tae32f53xx_ll_msp.c
@@ -0,0 +1,266 @@
+/**
+ ******************************************************************************
+ * @file tae32f53xx_ll_msp.c
+ * @author MCD Application Team
+ * @brief LL MSP module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+ *
+ * This software is licensed by Tai-Action under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+
+#define DBG_TAG "MSP LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae32f53xx_dbg.h"
+
+
+/** @addtogroup TAE32F53xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32F53xx_UART_TxPolling_RxIT_Example
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_TxPolling_RxIT_MSP_LL_Private_Functions UART_TxPolling_RxIT MSP LL Private Functions
+ * @brief UART_TxPolling_RxIT MSP LL Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the Global MSP.
+ * @param None
+ * @retval None
+ */
+void LL_MspInit(void)
+{
+ //SYSCTRL PMU Config
+ LL_SYSCTRL_PMUCfg();
+
+#ifdef LL_GPIO_MODULE_ENABLED
+ //GPIO Msp Init
+ LL_SYSCTRL_GPIOA_ClkEnRstRelease();
+ LL_SYSCTRL_GPIOB_ClkEnRstRelease();
+ LL_SYSCTRL_GPIOC_ClkEnRstRelease();
+ LL_SYSCTRL_GPIOD_ClkEnRstRelease();
+#endif
+
+#ifdef LL_DMA_MODULE_ENABLED
+ //DMA Msp Init
+ LL_SYSCTRL_DMA_ClkEnRstRelease();
+
+ //NVIC DMA Interrupt Enable
+ LL_NVIC_EnableIRQ(DMA_IRQn);
+#endif
+}
+
+/**
+ * @brief DeInitializes the Global MSP.
+ * @param None
+ * @retval None
+ */
+void LL_MspDeInit(void)
+{
+#ifdef LL_GPIO_MODULE_ENABLED
+ //GPIO Msp DeInit
+ LL_SYSCTRL_GPIOA_ClkDisRstAssert();
+ LL_SYSCTRL_GPIOB_ClkDisRstAssert();
+ LL_SYSCTRL_GPIOC_ClkDisRstAssert();
+ LL_SYSCTRL_GPIOD_ClkDisRstAssert();
+#endif
+
+#ifdef LL_DMA_MODULE_ENABLED
+ //DMA Msp DeInit
+ LL_SYSCTRL_DMA_ClkDisRstAssert();
+
+ //NVIC DMA Interrupt Disable
+ LL_NVIC_DisableIRQ(DMA_IRQn);
+#endif
+}
+
+/**
+ * @brief Initializes the FPLL MSP.
+ * @param Instance Specifies FPLL peripheral
+ * @retval None
+ */
+void LL_FPLL_MspInit(FPLL_TypeDef *Instance)
+{
+ //Check FPLL Instance to be Valid
+ if (!IS_FPLL_ALL_INSTANCE(Instance))
+ {
+ return;
+ }
+
+ //FPLL Soft Reset Release
+ if (Instance == FPLL0)
+ {
+ LL_SYSCTRL_FPLL0_RstRelease();
+ }
+ else if (Instance == FPLL1)
+ {
+ LL_SYSCTRL_FPLL1_RstRelease();
+ }
+ else if (Instance == FPLL2)
+ {
+ LL_SYSCTRL_FPLL2_RstRelease();
+ }
+}
+
+/**
+ * @brief DeInitializes the FPLL MSP.
+ * @param Instance Specifies FPLL peripheral
+ * @retval None
+ */
+void LL_FPLL_MspDeInit(FPLL_TypeDef *Instance)
+{
+ //Check FPLL Instance to be Valid
+ if (!IS_FPLL_ALL_INSTANCE(Instance))
+ {
+ return;
+ }
+
+ //FPLL Soft Reset Assert
+ if (Instance == FPLL0)
+ {
+ LL_SYSCTRL_FPLL0_RstAssert();
+ }
+ else if (Instance == FPLL1)
+ {
+ LL_SYSCTRL_FPLL1_RstAssert();
+ }
+ else if (Instance == FPLL2)
+ {
+ LL_SYSCTRL_FPLL2_RstAssert();
+ }
+}
+
+/**
+ * @brief Initializes the UART MSP.
+ * @param Instance Specifies UART peripheral
+ * @retval None
+ */
+void LL_UART_MspInit(UART_TypeDef *Instance)
+{
+ GPIO_InitTypeDef UART_GPIO_Init;
+
+ //Check UART Instance to be Valid
+ if (!IS_UART_ALL_INSTANCE(Instance))
+ {
+ return;
+ }
+
+ if (Instance == UART0)
+ {
+ //UART0 Pinmux Config: PA10 & PA11
+ UART_GPIO_Init.Pin = GPIO_PIN_7;
+ UART_GPIO_Init.Mode = GPIO_MODE_AF;
+ UART_GPIO_Init.Alternate = GPIO_AF10_UART0;
+ LL_GPIO_Init(GPIOC, &UART_GPIO_Init);
+
+ UART_GPIO_Init.Pin = GPIO_PIN_10 | GPIO_PIN_11;
+ UART_GPIO_Init.Mode = GPIO_MODE_AF;
+ UART_GPIO_Init.OType = GPIO_OTYPE_PP;
+ UART_GPIO_Init.Pull = GPIO_NOPULL;
+ UART_GPIO_Init.Speed = GPIO_SPEED_FREQ_LOW;
+ UART_GPIO_Init.Alternate = GPIO_AF10_UART0;
+ LL_GPIO_Init(GPIOA, &UART_GPIO_Init);
+
+ //UART0 Bus Clock Enable and Soft Reset Release
+ LL_SYSCTRL_UART0_ClkEnRstRelease();
+
+ //NVIC UART0 Interrupt Enable
+ LL_NVIC_EnableIRQ(UART0_IRQn);
+ }
+ else if (Instance == UART1)
+ {
+ //UART1 Pinmux Config: PB8 & PB9
+ UART_GPIO_Init.Pin = GPIO_PIN_8 | GPIO_PIN_9;
+ UART_GPIO_Init.Mode = GPIO_MODE_AF;
+ UART_GPIO_Init.OType = GPIO_OTYPE_PP;
+ UART_GPIO_Init.Pull = GPIO_NOPULL;
+ UART_GPIO_Init.Speed = GPIO_SPEED_FREQ_LOW;
+ UART_GPIO_Init.Alternate = GPIO_AF10_UART1;
+ LL_GPIO_Init(GPIOB, &UART_GPIO_Init);
+
+ //UART1 Bus Clock Enable and Soft Reset Release
+ LL_SYSCTRL_UART1_ClkEnRstRelease();
+
+ //NVIC UART1 Interrupt Enable
+ LL_NVIC_EnableIRQ(UART1_IRQn);
+ }
+}
+
+/**
+ * @brief DeInitializes the UART MSP.
+ * @param Instance Specifies UART peripheral
+ * @retval None
+ */
+void LL_UART_MspDeInit(UART_TypeDef *Instance)
+{
+ //Check UART Instance to be Valid
+ if (!IS_UART_ALL_INSTANCE(Instance))
+ {
+ return;
+ }
+
+ if (Instance == UART0)
+ {
+ //NVIC UART0 Interrupt Disable
+ LL_NVIC_DisableIRQ(UART0_IRQn);
+
+ //UART0 Bus Clock Disable and Soft Reset Assert
+ LL_SYSCTRL_UART0_ClkDisRstAssert();
+
+ //UART0 Pinmux DeInit
+ LL_GPIO_DeInit(GPIOA, GPIO_PIN_10 | GPIO_PIN_11);
+ }
+ else if (Instance == UART1)
+ {
+ //NVIC UART1 Interrupt Disable
+ LL_NVIC_DisableIRQ(UART1_IRQn);
+
+ //UART1 Bus Clock Disable and Soft Reset Assert
+ LL_SYSCTRL_UART1_ClkDisRstAssert();
+
+ //UART1 Pinmux DeInit
+ LL_GPIO_DeInit(GPIOB, GPIO_PIN_8 | GPIO_PIN_9);
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32f5300/drivers/Kconfig b/bsp/tae32f5300/drivers/Kconfig
new file mode 100644
index 0000000000..46e8ed25ec
--- /dev/null
+++ b/bsp/tae32f5300/drivers/Kconfig
@@ -0,0 +1,285 @@
+menu "Hardware Drivers Config"
+
+config MCU_TAE32F53xx
+ bool
+ select ARCH_ARM_CORTEX_M3
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART0
+ bool "Enable UART0"
+ default y
+
+ config BSP_UART0_RX_USING_DMA
+ bool "Enable UART0 RX DMA"
+ depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART0_TX_USING_DMA
+ bool "Enable UART0 TX DMA"
+ depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default n
+
+ config BSP_UART1_RX_USING_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART1_TX_USING_DMA
+ bool "Enable UART1 TX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS (software simulation)"
+ default y
+ select RT_USING_I2C
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C1
+ config BSP_I2C1_SCL_PIN
+ int "i2c1 scl pin number"
+ range 1 176
+ default 51
+ config BSP_I2C1_SDA_PIN
+ int "I2C1 sda pin number"
+ range 1 176
+ default 90
+ endif
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
+ default n
+
+ config BSP_SPI1_TX_USING_DMA
+ bool "Enable SPI1 TX DMA"
+ depends on BSP_USING_SPI1
+ default n
+
+ config BSP_SPI1_RX_USING_DMA
+ bool "Enable SPI1 RX DMA"
+ depends on BSP_USING_SPI1
+ select BSP_SPI1_TX_USING_DMA
+ default n
+
+ config BSP_USING_SPI2
+ bool "Enable SPI2 BUS"
+ default n
+
+ config BSP_SPI2_TX_USING_DMA
+ bool "Enable SPI2 TX DMA"
+ depends on BSP_USING_SPI2
+ default n
+
+ config BSP_SPI2_RX_USING_DMA
+ bool "Enable SPI2 RX DMA"
+ depends on BSP_USING_SPI2
+ select BSP_SPI2_TX_USING_DMA
+ default n
+
+ config BSP_USING_SPI3
+ bool "Enable SPI3 BUS"
+ default n
+
+ config BSP_SPI3_TX_USING_DMA
+ bool "Enable SPI3 TX DMA"
+ depends on BSP_USING_SPI3
+ default n
+
+ config BSP_SPI3_RX_USING_DMA
+ bool "Enable SPI3 RX DMA"
+ depends on BSP_USING_SPI3
+ select BSP_SPI3_TX_USING_DMA
+ default n
+
+ config BSP_USING_SPI4
+ bool "Enable SPI4 BUS"
+ default n
+
+ config BSP_SPI4_TX_USING_DMA
+ bool "Enable SPI4 TX DMA"
+ depends on BSP_USING_SPI4
+ default n
+
+ config BSP_SPI4_RX_USING_DMA
+ bool "Enable SPI4 RX DMA"
+ depends on BSP_USING_SPI4
+ select BSP_SPI4_TX_USING_DMA
+ default n
+
+ config BSP_USING_SPI5
+ bool "Enable SPI5 BUS"
+ default n
+
+ config BSP_SPI5_RX_USING_DMA
+ bool "Enable SPI5 TX DMA"
+ depends on BSP_USING_SPI5
+ default n
+
+ config BSP_SPI5_RX_USING_DMA
+ bool "Enable SPI5 RX DMA"
+ depends on BSP_USING_SPI5
+ select BSP_SPI5_TX_USING_DMA
+ default n
+
+ config BSP_USING_SPI6
+ bool "Enable SPI6 BUS"
+ default n
+
+ config BSP_SPI6_TX_USING_DMA
+ bool "Enable SPI6 TX DMA"
+ depends on BSP_USING_SPI6
+ default n
+
+ config BSP_SPI6_RX_USING_DMA
+ bool "Enable SPI6 RX DMA"
+ depends on BSP_USING_SPI6
+ select BSP_SPI6_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_RTC
+ bool "Enable RTC"
+ select RT_USING_RTC
+ select RT_USING_LIBC
+ default n
+
+ if BSP_USING_RTC
+ choice
+ prompt "Select clock source"
+ default BSP_RTC_USING_LRC
+
+ config BSP_RTC_USING_XTAL32
+ bool "RTC USING XTAL32"
+
+ config BSP_RTC_USING_LRC
+ bool "RTC USING LRC"
+ endchoice
+ endif
+
+ menuconfig BSP_USING_PWM
+ bool "Enable PWM"
+ default n
+ select RT_USING_PWM
+ if BSP_USING_PWM
+ menuconfig BSP_USING_PWM1
+ bool "Enable timer1 output pwm"
+ default n
+ if BSP_USING_PWM1
+ config BSP_USING_PWM1_CH1
+ bool "Enable PWM1 channel1"
+ default n
+
+ config BSP_USING_PWM1_CH2
+ bool "Enable PWM1 channel2"
+ default n
+
+ config BSP_USING_PWM1_CH3
+ bool "Enable PWM1 channel3"
+ default n
+
+ config BSP_USING_PWM1_CH4
+ bool "Enable PWM1 channel4"
+ default n
+ endif
+
+ menuconfig BSP_USING_PWM2
+ bool "Enable timer2 output pwm"
+ default n
+ if BSP_USING_PWM2
+ config BSP_USING_PWM2_CH1
+ bool "Enable PWM2 channel1"
+ default n
+
+ config BSP_USING_PWM2_CH2
+ bool "Enable PWM2 channel2"
+ default n
+
+ config BSP_USING_PWM2_CH3
+ bool "Enable PWM2 channel3"
+ default n
+
+ config BSP_USING_PWM2_CH4
+ bool "Enable PWM2 channel4"
+ default n
+ endif
+ endif
+
+ menuconfig BSP_USING_TIMER
+ bool "Enable TIMER"
+ default n
+ select RT_USING_HWTIMER
+ if BSP_USING_TIMER
+ config BSP_USING_TIMER5
+ bool "Enable TIMER5"
+ default n
+
+ config BSP_USING_TIMER6
+ bool "Enable TIMER6"
+ default n
+
+ config BSP_USING_TIMER7
+ bool "Enable TIMER7"
+ default n
+
+ config BSP_USING_TIMER8
+ bool "Enable TIMER8"
+ default n
+ endif
+
+ menuconfig BSP_USING_PULSE_ENCODER
+ bool "Enable Pulse Encoder"
+ default n
+ select RT_USING_PULSE_ENCODER
+ if BSP_USING_PULSE_ENCODER
+ config BSP_USING_PULSE_ENCODER9
+ bool "Enable Pulse Encoder9"
+ default n
+
+ config BSP_USING_PULSE_ENCODER10
+ bool "Enable Pulse Encoder10"
+ default n
+
+ config BSP_USING_PULSE_ENCODER11
+ bool "Enable Pulse Encoder11"
+ default n
+
+ config BSP_USING_PULSE_ENCODER12
+ bool "Enable Pulse Encoder12"
+ default n
+ endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
+
diff --git a/bsp/tae32f5300/drivers/SConscript b/bsp/tae32f5300/drivers/SConscript
new file mode 100644
index 0000000000..444957d70f
--- /dev/null
+++ b/bsp/tae32f5300/drivers/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+# add serial driver code
+if GetDepend('BSP_USING_UART') or GetDepend('BSP_USING_UART1'):
+ src += ['drv_uart.c']
+
+# add gpio driver code
+if GetDepend(['BSP_USING_GPIO']):
+ src += ['drv_gpio.c']
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/tae32f5300/drivers/drv_gpio.c b/bsp/tae32f5300/drivers/drv_gpio.c
new file mode 100644
index 0000000000..67a6549cb0
--- /dev/null
+++ b/bsp/tae32f5300/drivers/drv_gpio.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-05 qinweizhong first version
+ */
+#include
+#include
+#include
+#include
+#include
+#include "drv_gpio.h"
+
+#define TAE32_PIN(index, gpio, gpio_index) \
+{ \
+ 0, GPIO##gpio, GPIO_PIN_##gpio_index \
+}
+
+#define TAE32_PIN_DEFAULT \
+{ \
+ -1, 0, 0 \
+}
+
+/* TAE32 GPIO driver */
+struct pin_index
+{
+ int index;
+ GPIO_TypeDef *gpio;
+ uint32_t pin;
+};
+
+static const struct pin_index _pin_map[] =
+{
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN(2, C, 13),
+ TAE32_PIN(3, C, 14),
+ TAE32_PIN(4, C, 15),
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN(10, A, 0),
+ TAE32_PIN(11, A, 1),
+ TAE32_PIN(12, A, 2),
+ TAE32_PIN(13, A, 3),
+ TAE32_PIN(14, A, 4),
+ TAE32_PIN(15, A, 5),
+ TAE32_PIN(16, A, 6),
+ TAE32_PIN(17, A, 7),
+ TAE32_PIN(18, B, 0),
+ TAE32_PIN(19, B, 1),
+ TAE32_PIN(20, B, 2),
+ TAE32_PIN(21, B, 10),
+ TAE32_PIN(22, B, 11),
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN(25, B, 12),
+ TAE32_PIN(26, B, 13),
+ TAE32_PIN(27, B, 14),
+ TAE32_PIN(28, B, 15),
+ TAE32_PIN(29, A, 8),
+ TAE32_PIN(30, A, 9),
+ TAE32_PIN(31, A, 10),
+ TAE32_PIN(32, A, 11),
+ TAE32_PIN(33, A, 12),
+ TAE32_PIN(34, A, 13),
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN(37, A, 14),
+ TAE32_PIN(38, A, 15),
+ TAE32_PIN(39, B, 3),
+ TAE32_PIN(40, B, 4),
+ TAE32_PIN(41, B, 5),
+ TAE32_PIN(42, B, 6),
+ TAE32_PIN(43, B, 7),
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN(45, B, 8),
+ TAE32_PIN(46, B, 9),
+ TAE32_PIN_DEFAULT,
+ TAE32_PIN_DEFAULT,
+};
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+
+const struct pin_index *get_pin(uint8_t pin)
+{
+ const struct pin_index *index;
+
+ if (pin < ITEM_NUM(_pin_map))
+ {
+ index = &_pin_map[pin];
+ if (index->gpio == 0)
+ index = RT_NULL;
+ }
+ else
+ {
+ index = RT_NULL;
+ }
+ return index;
+};
+
+void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+ const struct pin_index *index;
+
+ index = get_pin(pin);
+ if (index == RT_NULL)
+ {
+ return;
+ }
+ if (value == PIN_LOW)
+ {
+ LL_GPIO_WritePin(index->gpio, index->pin, GPIO_PIN_RESET);
+ }
+ else
+ {
+ LL_GPIO_WritePin(index->gpio, index->pin, GPIO_PIN_SET);
+ }
+}
+
+int _pin_read(rt_device_t dev, rt_base_t pin)
+{
+ int value;
+ const struct pin_index *index;
+
+ value = PIN_LOW;
+ index = get_pin(pin);
+ if (index == RT_NULL)
+ {
+ return PIN_LOW;
+ }
+ if (LL_GPIO_ReadPin(index->gpio, index->pin) == GPIO_PIN_RESET)
+ {
+ value = PIN_LOW;
+ }
+ else
+ {
+ value = PIN_HIGH;
+ }
+ return value;
+}
+
+void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+ const struct pin_index *index;
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ index = get_pin(pin);
+ if (index == RT_NULL)
+ {
+ return;
+ }
+ /* Configure GPIO_InitStructure */
+ GPIO_InitStructure.Pin = index->pin;
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT;
+ GPIO_InitStructure.OType = GPIO_OTYPE_PP;
+ GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_LOW;
+ if (mode == PIN_MODE_OUTPUT)
+ {
+ /* output setting */
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT;
+ GPIO_InitStructure.OType = GPIO_OTYPE_PP;
+ }
+ else if (mode == PIN_MODE_OUTPUT_OD)
+ {
+ /* output setting: od. */
+ GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT;
+ GPIO_InitStructure.OType = GPIO_OTYPE_OD;
+ }
+ else if (mode == PIN_MODE_INPUT)
+ {
+ /* input setting: not pull. */
+ GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
+ }
+ else if (mode == PIN_MODE_INPUT_PULLUP)
+ {
+ /* input setting: pull up. */
+ GPIO_InitStructure.Pull = GPIO_PULLUP;
+ GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
+ }
+ else
+ {
+ /* input setting:default. */
+ GPIO_InitStructure.Pull = GPIO_PULLDOWN;
+ GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
+ }
+ LL_GPIO_Init(index->gpio, &GPIO_InitStructure);
+}
+
+rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+ rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+ return -RT_ERROR;
+}
+
+rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+ return -RT_ERROR;
+}
+
+rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
+ rt_uint32_t enabled)
+{
+ return -RT_ERROR;
+}
+
+const static struct rt_pin_ops _pin_ops =
+{
+ _pin_mode,
+ _pin_write,
+ _pin_read,
+ _pin_attach_irq,
+ _pin_detach_irq,
+ _pin_irq_enable,
+ RT_NULL,
+};
+
+int rt_hw_pin_init(void)
+{
+ int result;
+
+ result = rt_device_pin_register("pin", &_pin_ops, RT_NULL);
+ return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
diff --git a/bsp/tae32f5300/drivers/drv_gpio.h b/bsp/tae32f5300/drivers/drv_gpio.h
new file mode 100644
index 0000000000..ef6bd1d00d
--- /dev/null
+++ b/bsp/tae32f5300/drivers/drv_gpio.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-05 qinweizhong first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif
diff --git a/bsp/tae32f5300/drivers/drv_uart.c b/bsp/tae32f5300/drivers/drv_uart.c
new file mode 100644
index 0000000000..0987ac74ac
--- /dev/null
+++ b/bsp/tae32f5300/drivers/drv_uart.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-05 qinweizhong first version
+ */
+#include
+#include "drv_uart.h"
+#include "tae32f53xx_ll.h"
+#include
+#include "drv_uart.h"
+
+/* uart driver */
+struct tae32_uart
+{
+ UART_TypeDef *uart;
+ IRQn_Type irq;
+};
+
+static void uart_init(void)
+{
+ UART_InitTypeDef uart_init;
+ uart_init.baudrate = 115200;
+ uart_init.dat_len = UART_DAT_LEN_8b;
+ uart_init.stop_len = UART_STOP_LEN_1b;
+ uart_init.parity = UART_PARITY_NO;
+ uart_init.tx_tl = UART_TX_EMPTY_TRI_LVL_EMPTY;
+ uart_init.rx_tl = UART_RX_AVL_TRI_LVL_1CHAR;
+ LL_UART_Init(UART0, &uart_init);
+
+ __LL_UART_RxDatAvl_INT_En(UART0);
+}
+
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ struct tae32_uart *uart;
+ UART_InitTypeDef UART_InitStructure;
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+ uart = (struct tae32_uart *)serial->parent.user_data;
+ UART_InitStructure.baudrate = cfg->baud_rate;
+ if (cfg->data_bits == DATA_BITS_8)
+ UART_InitStructure.dat_len = UART_DAT_LEN_8b;
+ if (cfg->stop_bits == STOP_BITS_1)
+ UART_InitStructure.stop_len = UART_STOP_LEN_1b;
+ else if (cfg->stop_bits == STOP_BITS_2)
+ UART_InitStructure.stop_len = UART_STOP_LEN_2b;
+ UART_InitStructure.parity = UART_PARITY_NO;
+ UART_InitStructure.tx_tl = UART_TX_EMPTY_TRI_LVL_EMPTY;
+ UART_InitStructure.rx_tl = UART_RX_AVL_TRI_LVL_1CHAR;
+ LL_UART_Init(uart->uart, &UART_InitStructure);
+
+ return RT_EOK;
+}
+
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ struct tae32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct tae32_uart *)serial->parent.user_data;
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ /* disable rx irq */
+ NVIC_DisableIRQ(uart->irq);
+ __LL_UART_RxDatAvl_INT_Dis(uart->uart);
+ break;
+ case RT_DEVICE_CTRL_SET_INT:
+ /* enable rx irq */
+ NVIC_EnableIRQ(uart->irq);
+ /* enable interrupt */
+ __LL_UART_RxDatAvl_INT_En(uart->uart);
+ break;
+ }
+ return RT_EOK;
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+ struct tae32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct tae32_uart *)serial->parent.user_data;
+ while (!__LL_UART_IsTxFIFONotFull(uart->uart)) {};
+ __LL_UART_TxBuf9bits_Write(uart->uart, (uint16_t)c);
+ return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+ int ch;
+ struct tae32_uart *uart;
+ RT_ASSERT(serial != RT_NULL);
+ uart = (struct tae32_uart *)serial->parent.user_data;
+ ch = -1;
+ if (__LL_UART_IsDatReady(uart->uart))
+ {
+ ch = __LL_UART_RxBuf9bits_Read(uart->uart);
+ }
+ else
+ {
+ rt_thread_mdelay(10);
+ }
+ return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+ _uart_configure,
+ _uart_control,
+ _uart_putc,
+ _uart_getc,
+};
+
+#if defined(BSP_USING_UART0)
+/* UART0 device driver structure */
+static struct tae32_uart uart0;
+struct rt_serial_device serial0;
+void UART0_IRQHandler(void)
+{
+ struct tae32_uart *uart;
+ uart = &uart0;
+ /* enter interrupt */
+ rt_interrupt_enter();
+ if (__LL_UART_INT_ID_Get(uart->uart) == UART_INT_ID_RX_AVL)
+ {
+ rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+ }
+ if (__LL_UART_INT_ID_Get(uart->uart) != UART_INT_ID_RX_AVL)
+ {
+ /* clear interrupt */
+ }
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART1)
+/* UART2 device driver structure */
+static struct tae32_uart uart1;
+struct rt_serial_device serial1;
+void UART1_IRQHandler(void)
+{
+ struct tae32_uart *uart;
+ uart = &uart1;
+ /* enter interrupt */
+ rt_interrupt_enter();
+ if (__LL_UART_INT_ID_Get(uart->uart) == UART_INT_ID_RX_AVL)
+ {
+ rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+ }
+ if (__LL_UART_INT_ID_Get(uart->uart) != UART_INT_ID_RX_AVL)
+ {
+ /* clear interrupt */
+ }
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+int rt_hw_uart_init(void)
+{
+ struct tae32_uart *uart;
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+#ifdef BSP_USING_UART0
+ uart = &uart0;
+ uart->uart = UART0;
+ uart->irq = UART0_IRQn;
+ config.baud_rate = BAUD_RATE_115200;
+ serial0.ops = &_uart_ops;
+ serial0.config = config;
+ uart_init();
+
+ /* register UART1 device */
+ rt_hw_serial_register(&serial0, "uart0",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+ uart);
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+ uart = &uart1;
+ uart->uart = UART1;
+ uart->irq = UART1_IRQn;
+ config.baud_rate = BAUD_RATE_115200;
+ serial2.ops = &_uart_ops;
+ serial2.config = config;
+ /* register UART1 device */
+ rt_hw_serial_register(&serial1, "uart1",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+ uart);
+#endif /* BSP_USING_UART1 */
+ return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/tae32f5300/drivers/drv_uart.h b/bsp/tae32f5300/drivers/drv_uart.h
new file mode 100644
index 0000000000..1b83fb1a55
--- /dev/null
+++ b/bsp/tae32f5300/drivers/drv_uart.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-05 qinweizhong first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif
diff --git a/bsp/tae32f5300/figures/TAE32_EVBorad.png b/bsp/tae32f5300/figures/TAE32_EVBorad.png
new file mode 100644
index 0000000000000000000000000000000000000000..09896cd26feb563d06e9618f212ac5c983883de6
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