Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-09-24 13:13:54 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

convert end of line

Browse Source
This commit is contained in:
Bernard Xiong
2013-01-08 05:05:02 -08:00
parent b3cf278502
commit 72782e9203
229 changed files with 37399 additions and 37399 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libcpu/mips/common/asm.h
+220 -220
View File
@@ -1,220 +1,220 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
*
* Some useful macros for MIPS assembler code
*
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
*/
#ifndef __ASM_H__
#define __ASM_H__
/*
* LEAF - declare leaf routine
*/
#define LEAF(symbol) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp,0,ra
/*
* NESTED - declare nested routine entry point
*/
#define NESTED(symbol, framesize, rpc) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
#define END(function) \
.end function; \
.size function,.-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol,@function; \
symbol:
/*
* Global data declaration with size.
*/
#define EXPORTS(name,sz) \
.globl name; \
.type name,@object; \
.size name,sz; \
name:
/*
* Weak data declaration with size.
*/
#define WEXPORT(name,sz) \
.weakext name; \
.type name,@object; \
.size name,sz; \
name:
/*
* Global data reference with size.
*/
#define IMPORT(name, size) \
.extern name,size
/*
* Global zeroed data.
*/
#define BSS(name,size) \
.type name,@object; \
.comm name,size
/*
* Local zeroed data.
*/
#define LBSS(name,size) \
.lcomm name,size
/*
* ABS - export absolute symbol
*/
#define ABS(symbol,value) \
.globl symbol; \
symbol = value
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
#define ENTRY(name) \
.globl name; \
.align 2; \
.ent name,0; \
name##:
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
/*
* Size of a register
*/
#define SZREG 4
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#define REG_S sw
#define REG_L lw
#define REG_SUBU subu
#define REG_ADDU addu
/*
* How to add/sub/load/store/shift C int variables.
*/
#define INT_ADD add
#define INT_ADDU addu
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
/*
* How to add/sub/load/store/shift C long variables.
*/
#define LONG_ADD add
#define LONG_ADDU addu
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
#define LONG .word
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
/*
* How to add/sub/load/store/shift pointers.
*/
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
#define PTRSIZE 4
#define PTRLOG 2
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
#define MFC0 mfc0
#define MTC0 mtc0
#define SSNOP sll zero, zero, 1
#endif /* end of __ASM_H__ */
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
*
* Some useful macros for MIPS assembler code
*
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
*/
#ifndef __ASM_H__
#define __ASM_H__
/*
* LEAF - declare leaf routine
*/
#define LEAF(symbol) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp,0,ra
/*
* NESTED - declare nested routine entry point
*/
#define NESTED(symbol, framesize, rpc) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
#define END(function) \
.end function; \
.size function,.-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol,@function; \
symbol:
/*
* Global data declaration with size.
*/
#define EXPORTS(name,sz) \
.globl name; \
.type name,@object; \
.size name,sz; \
name:
/*
* Weak data declaration with size.
*/
#define WEXPORT(name,sz) \
.weakext name; \
.type name,@object; \
.size name,sz; \
name:
/*
* Global data reference with size.
*/
#define IMPORT(name, size) \
.extern name,size
/*
* Global zeroed data.
*/
#define BSS(name,size) \
.type name,@object; \
.comm name,size
/*
* Local zeroed data.
*/
#define LBSS(name,size) \
.lcomm name,size
/*
* ABS - export absolute symbol
*/
#define ABS(symbol,value) \
.globl symbol; \
symbol = value
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
#define ENTRY(name) \
.globl name; \
.align 2; \
.ent name,0; \
name##:
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
/*
* Size of a register
*/
#define SZREG 4
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#define REG_S sw
#define REG_L lw
#define REG_SUBU subu
#define REG_ADDU addu
/*
* How to add/sub/load/store/shift C int variables.
*/
#define INT_ADD add
#define INT_ADDU addu
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
/*
* How to add/sub/load/store/shift C long variables.
*/
#define LONG_ADD add
#define LONG_ADDU addu
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
#define LONG .word
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
/*
* How to add/sub/load/store/shift pointers.
*/
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
#define PTRSIZE 4
#define PTRLOG 2
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
#define MFC0 mfc0
#define MTC0 mtc0
#define SSNOP sll zero, zero, 1
#endif /* end of __ASM_H__ */
libcpu/mips/common/cache.c
+114 -114
View File
@@ -1,114 +1,114 @@
/*
* File : cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include "mipscfg.h"
#include "cache.h"
extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
void r4k_cache_init(void)
{
cache_init(dcache_size, cpu_dcache_line_size());
}
void r4k_cache_flush_all(void)
{
blast_dcache16();
blast_icache16();
}
void r4k_icache_flush_all(void)
{
blast_icache16();
}
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
if (size > icache_size)
{
blast_icache16();
}
else
{
rt_ubase_t ic_lsize = cpu_icache_line_size();
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
while (1)
{
flush_icache_line(a);
if (a == end)
break;
a += ic_lsize;
}
}
}
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
rt_ubase_t ic_lsize = cpu_icache_line_size();
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
while (1)
{
lock_icache_line(a);
if (a == end)
break;
a += ic_lsize;
}
}
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
rt_ubase_t dc_lsize = cpu_dcache_line_size();
a = addr & ~(dc_lsize - 1);
end = ((addr + size) - 1) & ~(dc_lsize - 1);
while (1)
{
invalidate_dcache_line(a);
if (a == end)
break;
a += dc_lsize;
}
}
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
if (size >= dcache_size)
{
blast_dcache16();
}
else
{
rt_ubase_t dc_lsize = cpu_dcache_line_size();
a = addr & ~(dc_lsize - 1);
end = ((addr + size) - 1) & ~(dc_lsize - 1);
while (1)
{
flush_dcache_line(a);
if (a == end)
break;
a += dc_lsize;
}
}
}
/*
* File : cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include "mipscfg.h"
#include "cache.h"
extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
void r4k_cache_init(void)
{
cache_init(dcache_size, cpu_dcache_line_size());
}
void r4k_cache_flush_all(void)
{
blast_dcache16();
blast_icache16();
}
void r4k_icache_flush_all(void)
{
blast_icache16();
}
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
if (size > icache_size)
{
blast_icache16();
}
else
{
rt_ubase_t ic_lsize = cpu_icache_line_size();
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
while (1)
{
flush_icache_line(a);
if (a == end)
break;
a += ic_lsize;
}
}
}
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
rt_ubase_t ic_lsize = cpu_icache_line_size();
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
while (1)
{
lock_icache_line(a);
if (a == end)
break;
a += ic_lsize;
}
}
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
rt_ubase_t dc_lsize = cpu_dcache_line_size();
a = addr & ~(dc_lsize - 1);
end = ((addr + size) - 1) & ~(dc_lsize - 1);
while (1)
{
invalidate_dcache_line(a);
if (a == end)
break;
a += dc_lsize;
}
}
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
if (size >= dcache_size)
{
blast_dcache16();
}
else
{
rt_ubase_t dc_lsize = cpu_dcache_line_size();
a = addr & ~(dc_lsize - 1);
end = ((addr + size) - 1) & ~(dc_lsize - 1);
while (1)
{
flush_dcache_line(a);
if (a == end)
break;
a += dc_lsize;
}
}
}
libcpu/mips/common/cache.h
+232 -232
View File
@@ -1,232 +1,232 @@
/*
* Cache operations for the cache instruction.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
*/
#ifndef __CACHE_H__
#define __CACHE_H__
#define KUSEG 0x00000000
#define KSEG0 0x80000000
#define KSEG1 0xa0000000
#define KSEG2 0xc0000000
#define KSEG3 0xe0000000
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Writeback_Inv_D 0x15
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/*
*The lock state is cleared by executing an Index
Invalidate, Index Writeback Invalidate, Hit
Invalidate, or Hit Writeback Invalidate
operation to the locked line, or via an Index
Store Tag operation with the lock bit reset in
the TagLo register.
*/
#define Fetch_And_Lock_I 0x1c
#define Fetch_And_Lock_D 0x1d
/*
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D 0x0d
#define Fill 0x14
/*
* R4000SC and R4400SC-specific cacheops
*/
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_SD 0x1b
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
/*
* R5000-specific cacheops
*/
#define R5K_Page_Invalidate_S 0x17
/*
* RM7000-specific cacheops
*/
#define Page_Invalidate_T 0x16
/*
* R1000-specific cacheops
*
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
#define Index_Writeback_Inv_S 0x03
#define Index_Load_Tag_S 0x07
#define Index_Store_Tag_S 0x0B
#define Hit_Invalidate_S 0x13
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S 0x17
#define Index_Load_Data_I 0x18
#define Index_Load_Data_D 0x19
#define Index_Load_Data_S 0x1b
#define Index_Store_Data_I 0x1c
#define Index_Store_Data_D 0x1d
#define Index_Store_Data_S 0x1f
#ifndef __ASSEMBLER__
#ifndef dcache_size
#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
#endif
#ifndef icache_size
#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
#endif
#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size() g_mips_core.icache_line_size
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size() g_mips_core.icache_line_size
#endif
#define cache_op(op, addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set mips0 \n" \
" .set reorder" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
#define cache16_unroll32(base, op) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips3 \n" \
" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
" .set mips0 \n" \
" .set reorder \n" \
: \
: "r" (base), \
"i" (op));
static inline void flush_icache_line_indexed(rt_ubase_t addr)
{
cache_op(Index_Invalidate_I, addr);
}
static inline void flush_dcache_line_indexed(rt_ubase_t addr)
{
cache_op(Index_Writeback_Inv_D, addr);
}
static inline void flush_icache_line(rt_ubase_t addr)
{
cache_op(Hit_Invalidate_I, addr);
}
static inline void lock_icache_line(rt_ubase_t addr)
{
cache_op(Fetch_And_Lock_I, addr);
}
static inline void lock_dcache_line(rt_ubase_t addr)
{
cache_op(Fetch_And_Lock_D, addr);
}
static inline void flush_dcache_line(rt_ubase_t addr)
{
cache_op(Hit_Writeback_Inv_D, addr);
}
static inline void invalidate_dcache_line(rt_ubase_t addr)
{
cache_op(Hit_Invalidate_D, addr);
}
static inline void blast_dcache16(void)
{
rt_ubase_t start = KSEG0;
rt_ubase_t end = start + dcache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr, Index_Writeback_Inv_D);
}
static inline void inv_dcache16(void)
{
rt_ubase_t start = KSEG0;
rt_ubase_t end = start + dcache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr, Hit_Invalidate_D);
}
static inline void blast_icache16(void)
{
rt_ubase_t start = KSEG0;
rt_ubase_t end = start + icache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr, Index_Invalidate_I);
}
void r4k_cache_init(void);
void r4k_cache_flush_all(void);
void r4k_icache_flush_all(void);
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
#endif /*end of __ASSEMBLER__ */
#endif /* end of __CACHE_H__ */
/*
* Cache operations for the cache instruction.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
*/
#ifndef __CACHE_H__
#define __CACHE_H__
#define KUSEG 0x00000000
#define KSEG0 0x80000000
#define KSEG1 0xa0000000
#define KSEG2 0xc0000000
#define KSEG3 0xe0000000
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Writeback_Inv_D 0x15
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/*
*The lock state is cleared by executing an Index
Invalidate, Index Writeback Invalidate, Hit
Invalidate, or Hit Writeback Invalidate
operation to the locked line, or via an Index
Store Tag operation with the lock bit reset in
the TagLo register.
*/
#define Fetch_And_Lock_I 0x1c
#define Fetch_And_Lock_D 0x1d
/*
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D 0x0d
#define Fill 0x14
/*
* R4000SC and R4400SC-specific cacheops
*/
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_SD 0x1b
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
/*
* R5000-specific cacheops
*/
#define R5K_Page_Invalidate_S 0x17
/*
* RM7000-specific cacheops
*/
#define Page_Invalidate_T 0x16
/*
* R1000-specific cacheops
*
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
#define Index_Writeback_Inv_S 0x03
#define Index_Load_Tag_S 0x07
#define Index_Store_Tag_S 0x0B
#define Hit_Invalidate_S 0x13
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S 0x17
#define Index_Load_Data_I 0x18
#define Index_Load_Data_D 0x19
#define Index_Load_Data_S 0x1b
#define Index_Store_Data_I 0x1c
#define Index_Store_Data_D 0x1d
#define Index_Store_Data_S 0x1f
#ifndef __ASSEMBLER__
#ifndef dcache_size
#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
#endif
#ifndef icache_size
#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
#endif
#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size() g_mips_core.icache_line_size
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size() g_mips_core.icache_line_size
#endif
#define cache_op(op, addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips3\n\t \n" \
" cache %0, %1 \n" \
" .set mips0 \n" \
" .set reorder" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
#define cache16_unroll32(base, op) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips3 \n" \
" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
" .set mips0 \n" \
" .set reorder \n" \
: \
: "r" (base), \
"i" (op));
static inline void flush_icache_line_indexed(rt_ubase_t addr)
{
cache_op(Index_Invalidate_I, addr);
}
static inline void flush_dcache_line_indexed(rt_ubase_t addr)
{
cache_op(Index_Writeback_Inv_D, addr);
}
static inline void flush_icache_line(rt_ubase_t addr)
{
cache_op(Hit_Invalidate_I, addr);
}
static inline void lock_icache_line(rt_ubase_t addr)
{
cache_op(Fetch_And_Lock_I, addr);
}
static inline void lock_dcache_line(rt_ubase_t addr)
{
cache_op(Fetch_And_Lock_D, addr);
}
static inline void flush_dcache_line(rt_ubase_t addr)
{
cache_op(Hit_Writeback_Inv_D, addr);
}
static inline void invalidate_dcache_line(rt_ubase_t addr)
{
cache_op(Hit_Invalidate_D, addr);
}
static inline void blast_dcache16(void)
{
rt_ubase_t start = KSEG0;
rt_ubase_t end = start + dcache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr, Index_Writeback_Inv_D);
}
static inline void inv_dcache16(void)
{
rt_ubase_t start = KSEG0;
rt_ubase_t end = start + dcache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr, Hit_Invalidate_D);
}
static inline void blast_icache16(void)
{
rt_ubase_t start = KSEG0;
rt_ubase_t end = start + icache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr, Index_Invalidate_I);
}
void r4k_cache_init(void);
void r4k_cache_flush_all(void);
void r4k_icache_flush_all(void);
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
#endif /*end of __ASSEMBLER__ */
#endif /* end of __CACHE_H__ */
libcpu/mips/common/exception.h
+166 -166
View File
@@ -1,166 +1,166 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#ifndef __EXCEPTION_H__
#define __EXCEPTION_H__
/*
* important register numbers
*/
#define REG_EPC 37
#define REG_FP 72
#define REG_SP 29
/*
* Stack layout for the GDB exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
#define NUMREGS 90
#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
///*
// * Saved floating point registers
// */
//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
//
//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
//
//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
//
///*
// * Again, CP0 registers
// */
//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */
#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */
#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
/*
* This is the same as above, but for the high-level
* part of the INT stub.
*/
typedef struct pt_regs_s
{
/* Saved main processor registers. */
rt_base_t regs[32];
/* Saved special registers. */
rt_base_t cp0_status;
rt_base_t hi;
rt_base_t lo;
rt_base_t cp0_badvaddr;
rt_base_t cp0_cause;
rt_base_t cp0_epc;
} pt_regs_t;
typedef void (* exception_func_t)(pt_regs_t *regs);
extern exception_func_t sys_exception_handlers[];
exception_func_t rt_set_except_vector(int n, exception_func_t func);
void install_default_execpt_handle(void);
#endif /* end of __EXCEPTION_H__ */
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#ifndef __EXCEPTION_H__
#define __EXCEPTION_H__
/*
* important register numbers
*/
#define REG_EPC 37
#define REG_FP 72
#define REG_SP 29
/*
* Stack layout for the GDB exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
#define NUMREGS 90
#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
///*
// * Saved floating point registers
// */
//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
//
//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
//
//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
//
///*
// * Again, CP0 registers
// */
//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */
#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */
#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
/*
* This is the same as above, but for the high-level
* part of the INT stub.
*/
typedef struct pt_regs_s
{
/* Saved main processor registers. */
rt_base_t regs[32];
/* Saved special registers. */
rt_base_t cp0_status;
rt_base_t hi;
rt_base_t lo;
rt_base_t cp0_badvaddr;
rt_base_t cp0_cause;
rt_base_t cp0_epc;
} pt_regs_t;
typedef void (* exception_func_t)(pt_regs_t *regs);
extern exception_func_t sys_exception_handlers[];
exception_func_t rt_set_except_vector(int n, exception_func_t func);
void install_default_execpt_handle(void);
#endif /* end of __EXCEPTION_H__ */
libcpu/mips/common/mips.inc
+52 -52
View File
@@ -1,52 +1,52 @@
/*
* File : mips.inc
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 sangwei first version
*/
#ifndef __MIPS_INC__
#define __MIPS_INC__
#define zero $0 /* wired zero */
// #define at $1
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* caller saved */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel scratch */
#define k1 $27
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* same like fp! */
#define ra $31 /* return address */
#endif /* end of __MIPS_INC__ */
/*
* File : mips.inc
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 sangwei first version
*/
#ifndef __MIPS_INC__
#define __MIPS_INC__
#define zero $0 /* wired zero */
// #define at $1
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* caller saved */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel scratch */
#define k1 $27
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* same like fp! */
#define ra $31 /* return address */
#endif /* end of __MIPS_INC__ */
libcpu/mips/common/mipscfg.h
+32 -32
View File
@@ -1,32 +1,32 @@
/*
* File : mipscfg.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#ifndef __MIPSCFG_H__
#define __MIPSCFG_H__
typedef struct mips32_core_cfg
{
rt_uint16_t icache_line_size;
rt_uint16_t icache_lines_per_way;
rt_uint16_t icache_ways;
rt_uint16_t dcache_line_size;
rt_uint16_t dcache_lines_per_way;
rt_uint16_t dcache_ways;
rt_uint16_t max_tlb_entries; /* number of tlb entry */
} mips32_core_cfg_t;
extern mips32_core_cfg_t g_mips_core;
#endif /* end of __MIPSCFG_H__ */
/*
* File : mipscfg.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#ifndef __MIPSCFG_H__
#define __MIPSCFG_H__
typedef struct mips32_core_cfg
{
rt_uint16_t icache_line_size;
rt_uint16_t icache_lines_per_way;
rt_uint16_t icache_ways;
rt_uint16_t dcache_line_size;
rt_uint16_t dcache_lines_per_way;
rt_uint16_t dcache_ways;
rt_uint16_t max_tlb_entries; /* number of tlb entry */
} mips32_core_cfg_t;
extern mips32_core_cfg_t g_mips_core;
#endif /* end of __MIPSCFG_H__ */
libcpu/mips/common/mipsregs.h
+616 -616
View File
File diff suppressed because it is too large Load Diff
libcpu/mips/common/stackframe.h
+228 -228
View File
@@ -1,228 +1,228 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
* Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2007 Maciej W. Rozycki
*/
#ifndef __STACKFRAME_H__
#define __STACKFRAME_H__
#include "asm.h"
#include "mipsregs.h"
/*
* Stack layout for the INT exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
//#define PT_R0 (PTRSIZE*6) /* 0 */
#define PT_R0 (0) /* 0 */
#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */
#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */
#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */
#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */
#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */
#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */
#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */
#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */
#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */
#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */
#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */
#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */
#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */
#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */
#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */
#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */
#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */
#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */
#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */
#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */
#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */
#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */
#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */
#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */
#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */
#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */
#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */
#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */
#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */
#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
.macro SAVE_AT
.set push
.set noat
LONG_S $1, PT_R1(sp)
.set pop
.endm
.macro SAVE_TEMP
mfhi v1
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
LONG_S v1, PT_HI(sp)
mflo v1
LONG_S $10, PT_R10(sp)
LONG_S $11, PT_R11(sp)
LONG_S v1, PT_LO(sp)
LONG_S $12, PT_R12(sp)
LONG_S $13, PT_R13(sp)
LONG_S $14, PT_R14(sp)
LONG_S $15, PT_R15(sp)
LONG_S $24, PT_R24(sp)
.endm
.macro SAVE_STATIC
LONG_S $16, PT_R16(sp)
LONG_S $17, PT_R17(sp)
LONG_S $18, PT_R18(sp)
LONG_S $19, PT_R19(sp)
LONG_S $20, PT_R20(sp)
LONG_S $21, PT_R21(sp)
LONG_S $22, PT_R22(sp)
LONG_S $23, PT_R23(sp)
LONG_S $30, PT_R30(sp)
.endm
.macro get_saved_sp
nop
.endm
.macro SAVE_SOME
.set push
.set noat
.set reorder
move k1, sp
8: move k0, sp
PTR_SUBU sp, k1, PT_SIZE
LONG_S k0, PT_R29(sp)
LONG_S $3, PT_R3(sp)
LONG_S $0, PT_R0(sp)
mfc0 v1, CP0_STATUS
LONG_S $2, PT_R2(sp)
LONG_S v1, PT_STATUS(sp)
LONG_S $4, PT_R4(sp)
mfc0 v1, CP0_CAUSE
LONG_S $5, PT_R5(sp)
LONG_S v1, PT_CAUSE(sp)
LONG_S $6, PT_R6(sp)
MFC0 v1, CP0_EPC
LONG_S $7, PT_R7(sp)
LONG_S v1, PT_EPC(sp)
LONG_S $25, PT_R25(sp)
LONG_S $28, PT_R28(sp)
LONG_S $31, PT_R31(sp)
.set pop
.endm
.macro SAVE_ALL
SAVE_SOME
SAVE_AT
SAVE_TEMP
SAVE_STATIC
.endm
.macro RESTORE_AT
.set push
.set noat
LONG_L $1, PT_R1(sp)
.set pop
.endm
.macro RESTORE_TEMP
LONG_L $24, PT_LO(sp)
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
mtlo $24
LONG_L $24, PT_HI(sp)
LONG_L $10, PT_R10(sp)
LONG_L $11, PT_R11(sp)
mthi $24
LONG_L $12, PT_R12(sp)
LONG_L $13, PT_R13(sp)
LONG_L $14, PT_R14(sp)
LONG_L $15, PT_R15(sp)
LONG_L $24, PT_R24(sp)
.endm
.macro RESTORE_STATIC
LONG_L $16, PT_R16(sp)
LONG_L $17, PT_R17(sp)
LONG_L $18, PT_R18(sp)
LONG_L $19, PT_R19(sp)
LONG_L $20, PT_R20(sp)
LONG_L $21, PT_R21(sp)
LONG_L $22, PT_R22(sp)
LONG_L $23, PT_R23(sp)
LONG_L $30, PT_R30(sp)
.endm
.macro RESTORE_SOME
.set push
.set reorder
.set noat
LONG_L v0, PT_STATUS(sp)
mtc0 v0, CP0_STATUS
LONG_L v1, PT_EPC(sp)
MTC0 v1, CP0_EPC
LONG_L $31, PT_R31(sp)
LONG_L $28, PT_R28(sp)
LONG_L $25, PT_R25(sp)
LONG_L $7, PT_R7(sp)
LONG_L $6, PT_R6(sp)
LONG_L $5, PT_R5(sp)
LONG_L $4, PT_R4(sp)
LONG_L $3, PT_R3(sp)
LONG_L $2, PT_R2(sp)
.set pop
.endm
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
.set mips3
eret
.set mips0
.endm
.macro RESTORE_SP
LONG_L sp, PT_R29(sp)
.endm
.macro RESTORE_ALL
RESTORE_TEMP
RESTORE_STATIC
RESTORE_AT
RESTORE_SOME
RESTORE_SP
.endm
.macro RESTORE_ALL_AND_RET
RESTORE_TEMP
RESTORE_STATIC
RESTORE_AT
RESTORE_SOME
RESTORE_SP_AND_RET
.endm
#endif /* end of __STACKFRAME_H__ */
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
* Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2007 Maciej W. Rozycki
*/
#ifndef __STACKFRAME_H__
#define __STACKFRAME_H__
#include "asm.h"
#include "mipsregs.h"
/*
* Stack layout for the INT exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
//#define PT_R0 (PTRSIZE*6) /* 0 */
#define PT_R0 (0) /* 0 */
#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */
#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */
#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */
#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */
#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */
#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */
#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */
#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */
#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */
#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */
#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */
#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */
#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */
#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */
#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */
#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */
#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */
#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */
#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */
#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */
#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */
#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */
#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */
#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */
#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */
#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */
#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */
#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */
#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */
#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
.macro SAVE_AT
.set push
.set noat
LONG_S $1, PT_R1(sp)
.set pop
.endm
.macro SAVE_TEMP
mfhi v1
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
LONG_S v1, PT_HI(sp)
mflo v1
LONG_S $10, PT_R10(sp)
LONG_S $11, PT_R11(sp)
LONG_S v1, PT_LO(sp)
LONG_S $12, PT_R12(sp)
LONG_S $13, PT_R13(sp)
LONG_S $14, PT_R14(sp)
LONG_S $15, PT_R15(sp)
LONG_S $24, PT_R24(sp)
.endm
.macro SAVE_STATIC
LONG_S $16, PT_R16(sp)
LONG_S $17, PT_R17(sp)
LONG_S $18, PT_R18(sp)
LONG_S $19, PT_R19(sp)
LONG_S $20, PT_R20(sp)
LONG_S $21, PT_R21(sp)
LONG_S $22, PT_R22(sp)
LONG_S $23, PT_R23(sp)
LONG_S $30, PT_R30(sp)
.endm
.macro get_saved_sp
nop
.endm
.macro SAVE_SOME
.set push
.set noat
.set reorder
move k1, sp
8: move k0, sp
PTR_SUBU sp, k1, PT_SIZE
LONG_S k0, PT_R29(sp)
LONG_S $3, PT_R3(sp)
LONG_S $0, PT_R0(sp)
mfc0 v1, CP0_STATUS
LONG_S $2, PT_R2(sp)
LONG_S v1, PT_STATUS(sp)
LONG_S $4, PT_R4(sp)
mfc0 v1, CP0_CAUSE
LONG_S $5, PT_R5(sp)
LONG_S v1, PT_CAUSE(sp)
LONG_S $6, PT_R6(sp)
MFC0 v1, CP0_EPC
LONG_S $7, PT_R7(sp)
LONG_S v1, PT_EPC(sp)
LONG_S $25, PT_R25(sp)
LONG_S $28, PT_R28(sp)
LONG_S $31, PT_R31(sp)
.set pop
.endm
.macro SAVE_ALL
SAVE_SOME
SAVE_AT
SAVE_TEMP
SAVE_STATIC
.endm
.macro RESTORE_AT
.set push
.set noat
LONG_L $1, PT_R1(sp)
.set pop
.endm
.macro RESTORE_TEMP
LONG_L $24, PT_LO(sp)
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
mtlo $24
LONG_L $24, PT_HI(sp)
LONG_L $10, PT_R10(sp)
LONG_L $11, PT_R11(sp)
mthi $24
LONG_L $12, PT_R12(sp)
LONG_L $13, PT_R13(sp)
LONG_L $14, PT_R14(sp)
LONG_L $15, PT_R15(sp)
LONG_L $24, PT_R24(sp)
.endm
.macro RESTORE_STATIC
LONG_L $16, PT_R16(sp)
LONG_L $17, PT_R17(sp)
LONG_L $18, PT_R18(sp)
LONG_L $19, PT_R19(sp)
LONG_L $20, PT_R20(sp)
LONG_L $21, PT_R21(sp)
LONG_L $22, PT_R22(sp)
LONG_L $23, PT_R23(sp)
LONG_L $30, PT_R30(sp)
.endm
.macro RESTORE_SOME
.set push
.set reorder
.set noat
LONG_L v0, PT_STATUS(sp)
mtc0 v0, CP0_STATUS
LONG_L v1, PT_EPC(sp)
MTC0 v1, CP0_EPC
LONG_L $31, PT_R31(sp)
LONG_L $28, PT_R28(sp)
LONG_L $25, PT_R25(sp)
LONG_L $7, PT_R7(sp)
LONG_L $6, PT_R6(sp)
LONG_L $5, PT_R5(sp)
LONG_L $4, PT_R4(sp)
LONG_L $3, PT_R3(sp)
LONG_L $2, PT_R2(sp)
.set pop
.endm
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
.set mips3
eret
.set mips0
.endm
.macro RESTORE_SP
LONG_L sp, PT_R29(sp)
.endm
.macro RESTORE_ALL
RESTORE_TEMP
RESTORE_STATIC
RESTORE_AT
RESTORE_SOME
RESTORE_SP
.endm
.macro RESTORE_ALL_AND_RET
RESTORE_TEMP
RESTORE_STATIC
RESTORE_AT
RESTORE_SOME
RESTORE_SP_AND_RET
.endm
#endif /* end of __STACKFRAME_H__ */
libcpu/mips/jz47xx/cache.c
+93 -93
View File
@@ -1,93 +1,93 @@
#include "jz47xx.h"
#include "cache.h"
#define CACHE_SIZE 16*1024
#define CACHE_LINE_SIZE 32
#define KSEG0 0x80000000
#define K0_TO_K1() \
do { \
unsigned long __k0_addr; \
\
__asm__ __volatile__( \
"la %0, 1f\n\t" \
"or %0, %0, %1\n\t" \
"jr %0\n\t" \
"nop\n\t" \
"1: nop\n" \
: "=&r"(__k0_addr) \
: "r" (0x20000000) ); \
} while(0)
#define K1_TO_K0() \
do { \
unsigned long __k0_addr; \
__asm__ __volatile__( \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
"la %0, 1f\n\t" \
"jr %0\n\t" \
"nop\n\t" \
"1: nop\n" \
: "=&r" (__k0_addr)); \
} while (0)
#define INVALIDATE_BTB() \
do { \
unsigned long tmp; \
__asm__ __volatile__( \
".set mips32\n\t" \
"mfc0 %0, $16, 7\n\t" \
"nop\n\t" \
"ori %0, 2\n\t" \
"mtc0 %0, $16, 7\n\t" \
"nop\n\t" \
".set mips2\n\t" \
: "=&r" (tmp)); \
} while (0)
#define SYNC_WB() __asm__ __volatile__ ("sync")
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips32\n\t \n" \
" cache %0, %1 \n" \
" .set mips0 \n" \
" .set reorder" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
void __icache_invalidate_all(void)
{
unsigned int i;
K0_TO_K1();
asm volatile (".set noreorder\n"
".set mips32\n\t"
"mtc0\t$0,$28\n\t"
"mtc0\t$0,$29\n"
".set mips0\n"
".set reorder\n");
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
cache_op(Index_Store_Tag_I, i);
K1_TO_K0();
INVALIDATE_BTB();
}
void __dcache_writeback_all(void)
{
unsigned int i;
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
cache_op(Index_Writeback_Inv_D, i);
SYNC_WB();
}
void rt_hw_cache_init(void)
{
__dcache_writeback_all();
__icache_invalidate_all();
}
#include "jz47xx.h"
#include "cache.h"
#define CACHE_SIZE 16*1024
#define CACHE_LINE_SIZE 32
#define KSEG0 0x80000000
#define K0_TO_K1() \
do { \
unsigned long __k0_addr; \
\
__asm__ __volatile__( \
"la %0, 1f\n\t" \
"or %0, %0, %1\n\t" \
"jr %0\n\t" \
"nop\n\t" \
"1: nop\n" \
: "=&r"(__k0_addr) \
: "r" (0x20000000) ); \
} while(0)
#define K1_TO_K0() \
do { \
unsigned long __k0_addr; \
__asm__ __volatile__( \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
"la %0, 1f\n\t" \
"jr %0\n\t" \
"nop\n\t" \
"1: nop\n" \
: "=&r" (__k0_addr)); \
} while (0)
#define INVALIDATE_BTB() \
do { \
unsigned long tmp; \
__asm__ __volatile__( \
".set mips32\n\t" \
"mfc0 %0, $16, 7\n\t" \
"nop\n\t" \
"ori %0, 2\n\t" \
"mtc0 %0, $16, 7\n\t" \
"nop\n\t" \
".set mips2\n\t" \
: "=&r" (tmp)); \
} while (0)
#define SYNC_WB() __asm__ __volatile__ ("sync")
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips32\n\t \n" \
" cache %0, %1 \n" \
" .set mips0 \n" \
" .set reorder" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
void __icache_invalidate_all(void)
{
unsigned int i;
K0_TO_K1();
asm volatile (".set noreorder\n"
".set mips32\n\t"
"mtc0\t$0,$28\n\t"
"mtc0\t$0,$29\n"
".set mips0\n"
".set reorder\n");
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
cache_op(Index_Store_Tag_I, i);
K1_TO_K0();
INVALIDATE_BTB();
}
void __dcache_writeback_all(void)
{
unsigned int i;
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
cache_op(Index_Writeback_Inv_D, i);
SYNC_WB();
}
void rt_hw_cache_init(void)
{
__dcache_writeback_all();
__icache_invalidate_all();
}
libcpu/mips/jz47xx/cache.h
+40 -40
View File
@@ -1,40 +1,40 @@
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
void rt_hw_cache_init(void);
#endif
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
void rt_hw_cache_init(void);
#endif
libcpu/mips/jz47xx/cache_gcc.S
+42 -42
View File
@@ -1,42 +1,42 @@
/*
* File : cache_init.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include "../common/mips.inc"
#include "../common/mipsregs.h"
#include "../common/stackframe.h"
.text
.set noreorder
.globl cache_init
.ent cache_init
cache_init:
.set noreorder
mtc0 zero, CP0_TAGLO
move t0, a0 // cache total size
move t1, a1 // cache line size
li t2, 0x80000000
addu t3, t0, t2
_cache_init_loop:
cache 8, 0(t2) // icache_index_store_tag
cache 9, 0(t2) // dcache_index_store_tag
addu t2, t1
bne t2, t3, _cache_init_loop
nop
mfc0 t0, CP0_CONFIG
li t1, 0x7
not t1
and t0, t0, t1
or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
mtc0 t0, CP0_CONFIG
jr ra
nop
.set reorder
.end cache_init
/*
* File : cache_init.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include "../common/mips.inc"
#include "../common/mipsregs.h"
#include "../common/stackframe.h"
.text
.set noreorder
.globl cache_init
.ent cache_init
cache_init:
.set noreorder
mtc0 zero, CP0_TAGLO
move t0, a0 // cache total size
move t1, a1 // cache line size
li t2, 0x80000000
addu t3, t0, t2
_cache_init_loop:
cache 8, 0(t2) // icache_index_store_tag
cache 9, 0(t2) // dcache_index_store_tag
addu t2, t1
bne t2, t3, _cache_init_loop
nop
mfc0 t0, CP0_CONFIG
li t1, 0x7
not t1
and t0, t0, t1
or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
mtc0 t0, CP0_CONFIG
jr ra
nop
.set reorder
.end cache_init
libcpu/mips/jz47xx/context_gcc.S
+146 -146
View File
@@ -1,146 +1,146 @@
/*
* File : context_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Jz4755
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "jz47xx.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
.globl system_dump
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
mfc0 t1, CP0_STATUS
and t0, t1
andi t0, 0xff00
beqz t0, spurious_interrupt
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder
/*
* File : context_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Jz4755
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "jz47xx.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
.globl system_dump
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
mfc0 t1, CP0_STATUS
and t0, t1
andi t0, 0xff00
beqz t0, spurious_interrupt
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder
libcpu/mips/jz47xx/cpu.c
+68 -68
View File
@@ -1,68 +1,68 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include <jz4755.h>
/* Watchdog definitions */
#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3)
#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3)
#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3)
#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3)
#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3)
#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3)
#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3)
#define WDT_CLK_EXTAL ( 0x1 << 2)
#define WDT_CLK_RTC ( 0x1 << 1)
#define WDT_CLK_PCLK ( 0x1 << 0)
#define WDT_CLK_MASK ( 7 )
#define WDT_ENABLE ( 1 << 0 )
/**
* @addtogroup Jz47xx
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset()
{
/* open the watch-dog */
WDT_TCSR = WDT_CLK_EXTAL;
WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024;
WDT_TDR = 0x03;
WDT_TCNT = 0x00;
WDT_TCER |= WDT_ENABLE;
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_kprintf("shutdown...\n");
while (1);
}
/*@}*/
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include <jz4755.h>
/* Watchdog definitions */
#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3)
#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3)
#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3)
#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3)
#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3)
#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3)
#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3)
#define WDT_CLK_EXTAL ( 0x1 << 2)
#define WDT_CLK_RTC ( 0x1 << 1)
#define WDT_CLK_PCLK ( 0x1 << 0)
#define WDT_CLK_MASK ( 7 )
#define WDT_ENABLE ( 1 << 0 )
/**
* @addtogroup Jz47xx
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset()
{
/* open the watch-dog */
WDT_TCSR = WDT_CLK_EXTAL;
WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024;
WDT_TDR = 0x03;
WDT_TCNT = 0x00;
WDT_TCER |= WDT_ENABLE;
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_kprintf("shutdown...\n");
while (1);
}
/*@}*/
libcpu/mips/jz47xx/exception.c
+65 -65
View File
@@ -1,65 +1,65 @@
/*
* File : exception.c
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Jz47xx
*/
/*@{*/
/**
* exception handle table
*/
exception_func_t sys_exception_handlers[33];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > 32) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<33; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
/*@}*/
/*
* File : exception.c
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Jz47xx
*/
/*@{*/
/**
* exception handle table
*/
exception_func_t sys_exception_handlers[33];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > 32) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<33; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
/*@}*/
libcpu/mips/jz47xx/interrupt.c
+116 -116
View File
@@ -1,116 +1,116 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
*/
#include <rtthread.h>
#include "jz47xx.h"
#define JZ47XX_MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[JZ47XX_MAX_INTR];
/**
* @addtogroup Jz47xx
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init()
{
rt_int32_t index;
for (index = 0; index < JZ47XX_MAX_INTR; index ++)
{
irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
INTC_IMSR = (1 << vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
INTC_IMCR = (1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
{
if (vector >= 0 && vector < JZ47XX_MAX_INTR)
{
if (old_handler != RT_NULL)
*old_handler = irq_handle_table[vector];
if (new_handler != RT_NULL)
irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
}
}
void rt_interrupt_dispatch(void *ptreg)
{
int i;
rt_isr_handler_t irq_func;
static rt_uint32_t pending = 0;
/* the hardware interrupt */
pending |= INTC_IPR;
if (!pending) return;
for (i = JZ47XX_MAX_INTR; i > 0; --i)
{
if ((pending & (1<<i)))
{
pending &= ~(1<<i);
irq_func = irq_handle_table[i];
/* do interrupt */
(*irq_func)(i);
/* ack interrupt */
INTC_IPR = (1 << i);
}
}
}
/*@}*/
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
*/
#include <rtthread.h>
#include "jz47xx.h"
#define JZ47XX_MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[JZ47XX_MAX_INTR];
/**
* @addtogroup Jz47xx
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init()
{
rt_int32_t index;
for (index = 0; index < JZ47XX_MAX_INTR; index ++)
{
irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
INTC_IMSR = (1 << vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
INTC_IMCR = (1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
{
if (vector >= 0 && vector < JZ47XX_MAX_INTR)
{
if (old_handler != RT_NULL)
*old_handler = irq_handle_table[vector];
if (new_handler != RT_NULL)
irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
}
}
void rt_interrupt_dispatch(void *ptreg)
{
int i;
rt_isr_handler_t irq_func;
static rt_uint32_t pending = 0;
/* the hardware interrupt */
pending |= INTC_IPR;
if (!pending) return;
for (i = JZ47XX_MAX_INTR; i > 0; --i)
{
if ((pending & (1<<i)))
{
pending &= ~(1<<i);
irq_func = irq_handle_table[i];
/* do interrupt */
(*irq_func)(i);
/* ack interrupt */
INTC_IPR = (1 << i);
}
}
}
/*@}*/
libcpu/mips/jz47xx/jz4740.h
+55 -55
View File
@@ -1,55 +1,55 @@
#ifndef __JZ4740_H__
#define __JZ4740_H__
#include "jz47xx.h"
#define WDT_BASE 0xB0002000
/* Watchdog */
#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
/* Clock Gate Register Definitions */
#define CPM_CLKGR_UART1 (1 << 15)
#define CPM_CLKGR_UHC (1 << 14)
#define CPM_CLKGR_IPU (1 << 13)
#define CPM_CLKGR_DMAC (1 << 12)
#define CPM_CLKGR_UDC (1 << 11)
#define CPM_CLKGR_LCD (1 << 10)
#define CPM_CLKGR_CIM (1 << 9)
#define CPM_CLKGR_SADC (1 << 8)
#define CPM_CLKGR_MSC (1 << 7)
#define CPM_CLKGR_AIC1 (1 << 6)
#define CPM_CLKGR_AIC2 (1 << 5)
#define CPM_CLKGR_SSI (1 << 4)
#define CPM_CLKGR_I2C (1 << 3)
#define CPM_CLKGR_RTC (1 << 2)
#define CPM_CLKGR_TCU (1 << 1)
#define CPM_CLKGR_UART0 (1 << 0)
/* Interrupt Definitions */
#define IRQ_I2C 1
#define IRQ_UHC 3
#define IRQ_UART0 9
#define IRQ_SADC 12
#define IRQ_MSC 14
#define IRQ_RTC 15
#define IRQ_SSI 16
#define IRQ_CIM 17
#define IRQ_AIC 18
#define IRQ_ETH 19
#define IRQ_DMAC 20
#define IRQ_TCU2 21
#define IRQ_TCU1 22
#define IRQ_TCU0 23
#define IRQ_UDC 24
#define IRQ_GPIO3 25
#define IRQ_GPIO2 26
#define IRQ_GPIO1 27
#define IRQ_GPIO0 28
#define IRQ_IPU 29
#define IRQ_LCD 30
#endif
#ifndef __JZ4740_H__
#define __JZ4740_H__
#include "jz47xx.h"
#define WDT_BASE 0xB0002000
/* Watchdog */
#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
/* Clock Gate Register Definitions */
#define CPM_CLKGR_UART1 (1 << 15)
#define CPM_CLKGR_UHC (1 << 14)
#define CPM_CLKGR_IPU (1 << 13)
#define CPM_CLKGR_DMAC (1 << 12)
#define CPM_CLKGR_UDC (1 << 11)
#define CPM_CLKGR_LCD (1 << 10)
#define CPM_CLKGR_CIM (1 << 9)
#define CPM_CLKGR_SADC (1 << 8)
#define CPM_CLKGR_MSC (1 << 7)
#define CPM_CLKGR_AIC1 (1 << 6)
#define CPM_CLKGR_AIC2 (1 << 5)
#define CPM_CLKGR_SSI (1 << 4)
#define CPM_CLKGR_I2C (1 << 3)
#define CPM_CLKGR_RTC (1 << 2)
#define CPM_CLKGR_TCU (1 << 1)
#define CPM_CLKGR_UART0 (1 << 0)
/* Interrupt Definitions */
#define IRQ_I2C 1
#define IRQ_UHC 3
#define IRQ_UART0 9
#define IRQ_SADC 12
#define IRQ_MSC 14
#define IRQ_RTC 15
#define IRQ_SSI 16
#define IRQ_CIM 17
#define IRQ_AIC 18
#define IRQ_ETH 19
#define IRQ_DMAC 20
#define IRQ_TCU2 21
#define IRQ_TCU1 22
#define IRQ_TCU0 23
#define IRQ_UDC 24
#define IRQ_GPIO3 25
#define IRQ_GPIO2 26
#define IRQ_GPIO1 27
#define IRQ_GPIO0 28
#define IRQ_IPU 29
#define IRQ_LCD 30
#endif
libcpu/mips/jz47xx/jz4755.h
+83 -83
View File
@@ -1,83 +1,83 @@
#ifndef __JZ4755_H__
#define __JZ4755_H__
#include "jz47xx.h"
#define WDT_BASE 0xB0002000
#define OST_BASE 0xB00020e0
/* Watchdog */
#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
/* OS Timer */
#define OST_DR __REG32(OST_BASE + 0x00) /* OS Timer Data Register */
#define OST_CNT __REG32(OST_BASE + 0x08) /* OS Timer Counter Register */
#define OST_CSR __REG16(OST_BASE + 0x0C) /* OS Timer Control Register */
/* OST Register Definitions */
#define OST_TCSR_EXT_EN ( 0x1 << 2)
#define OST_TCSR_RTC_EN ( 0x1 << 1)
#define OST_TCSR_PCLK_EN ( 0x1 << 0)
/* Clock Gate Register Definitions */
#define CPM_CLKGR_AUX_CPU ( 1 << 24 )
#define CPM_CLKGR_AHB1 ( 1 << 23 )
#define CPM_CLKGR_IDCT ( 1 << 22 )
#define CPM_CLKGR_DB ( 1 << 21 )
#define CPM_CLKGR_ME ( 1 << 20 )
#define CPM_CLKGR_MC ( 1 << 19 )
#define CPM_CLKGR_TVE ( 1 << 18 )
#define CPM_CLKGR_TSSI ( 1 << 17 )
#define CPM_CLKGR_MSC1 ( 1 << 16 )
#define CPM_CLKGR_UART2 ( 1 << 15 )
#define CPM_CLKGR_UART1 ( 1 << 14 )
#define CPM_CLKGR_IPU ( 1 << 13 )
#define CPM_CLKGR_DMAC ( 1 << 12 )
#define CPM_CLKGR_BCH ( 1 << 11 )
#define CPM_CLKGR_UDC ( 1 << 10 )
#define CPM_CLKGR_LCD ( 1 << 9 )
#define CPM_CLKGR_CIM ( 1 << 8 )
#define CPM_CLKGR_SADC ( 1 << 7 )
#define CPM_CLKGR_MSC0 ( 1 << 6 )
#define CPM_CLKGR_AIC ( 1 << 5 )
#define CPM_CLKGR_SSI1 ( 1 << 4 )
#define CPM_CLKGR_I2C ( 1 << 3 )
#define CPM_CLKGR_RTC ( 1 << 2 )
#define CPM_CLKGR_TCU ( 1 << 1 )
#define CPM_CLKGR_UART0 ( 1 << 0 )
/* Interrupt Definitions */
#define IRQ_ETH 0
#define IRQ_SFT 4
#define IRQ_I2C 5
#define IRQ_RTC 6
#define IRQ_UART2 7
#define IRQ_UART1 8
#define IRQ_UART0 9
#define IRQ_AIC 10
#define IRQ_GPIO5 11
#define IRQ_GPIO4 12
#define IRQ_GPIO3 13
#define IRQ_GPIO2 14
#define IRQ_GPIO1 15
#define IRQ_GPIO0 16
#define IRQ_BCH 17
#define IRQ_SADC 18
#define IRQ_CIM 19
#define IRQ_TSSI 20
#define IRQ_TCU2 21
#define IRQ_TCU1 22
#define IRQ_TCU0 23
#define IRQ_MSC1 24
#define IRQ_MSC0 25
#define IRQ_SSI 26
#define IRQ_UDC 27
#define IRQ_DMA1 28 /* Used for DMA channel 4-7 */
#define IRQ_DMA0 29 /* Used for DMA channel 0-3 */
#define IRQ_IPU 30
#define IRQ_LCD 31
#endif
#ifndef __JZ4755_H__
#define __JZ4755_H__
#include "jz47xx.h"
#define WDT_BASE 0xB0002000
#define OST_BASE 0xB00020e0
/* Watchdog */
#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
/* OS Timer */
#define OST_DR __REG32(OST_BASE + 0x00) /* OS Timer Data Register */
#define OST_CNT __REG32(OST_BASE + 0x08) /* OS Timer Counter Register */
#define OST_CSR __REG16(OST_BASE + 0x0C) /* OS Timer Control Register */
/* OST Register Definitions */
#define OST_TCSR_EXT_EN ( 0x1 << 2)
#define OST_TCSR_RTC_EN ( 0x1 << 1)
#define OST_TCSR_PCLK_EN ( 0x1 << 0)
/* Clock Gate Register Definitions */
#define CPM_CLKGR_AUX_CPU ( 1 << 24 )
#define CPM_CLKGR_AHB1 ( 1 << 23 )
#define CPM_CLKGR_IDCT ( 1 << 22 )
#define CPM_CLKGR_DB ( 1 << 21 )
#define CPM_CLKGR_ME ( 1 << 20 )
#define CPM_CLKGR_MC ( 1 << 19 )
#define CPM_CLKGR_TVE ( 1 << 18 )
#define CPM_CLKGR_TSSI ( 1 << 17 )
#define CPM_CLKGR_MSC1 ( 1 << 16 )
#define CPM_CLKGR_UART2 ( 1 << 15 )
#define CPM_CLKGR_UART1 ( 1 << 14 )
#define CPM_CLKGR_IPU ( 1 << 13 )
#define CPM_CLKGR_DMAC ( 1 << 12 )
#define CPM_CLKGR_BCH ( 1 << 11 )
#define CPM_CLKGR_UDC ( 1 << 10 )
#define CPM_CLKGR_LCD ( 1 << 9 )
#define CPM_CLKGR_CIM ( 1 << 8 )
#define CPM_CLKGR_SADC ( 1 << 7 )
#define CPM_CLKGR_MSC0 ( 1 << 6 )
#define CPM_CLKGR_AIC ( 1 << 5 )
#define CPM_CLKGR_SSI1 ( 1 << 4 )
#define CPM_CLKGR_I2C ( 1 << 3 )
#define CPM_CLKGR_RTC ( 1 << 2 )
#define CPM_CLKGR_TCU ( 1 << 1 )
#define CPM_CLKGR_UART0 ( 1 << 0 )
/* Interrupt Definitions */
#define IRQ_ETH 0
#define IRQ_SFT 4
#define IRQ_I2C 5
#define IRQ_RTC 6
#define IRQ_UART2 7
#define IRQ_UART1 8
#define IRQ_UART0 9
#define IRQ_AIC 10
#define IRQ_GPIO5 11
#define IRQ_GPIO4 12
#define IRQ_GPIO3 13
#define IRQ_GPIO2 14
#define IRQ_GPIO1 15
#define IRQ_GPIO0 16
#define IRQ_BCH 17
#define IRQ_SADC 18
#define IRQ_CIM 19
#define IRQ_TSSI 20
#define IRQ_TCU2 21
#define IRQ_TCU1 22
#define IRQ_TCU0 23
#define IRQ_MSC1 24
#define IRQ_MSC0 25
#define IRQ_SSI 26
#define IRQ_UDC 27
#define IRQ_DMA1 28 /* Used for DMA channel 4-7 */
#define IRQ_DMA0 29 /* Used for DMA channel 0-3 */
#define IRQ_IPU 30
#define IRQ_LCD 31
#endif
libcpu/mips/jz47xx/jz47xx.h
+263 -263
View File
File diff suppressed because it is too large Load Diff
libcpu/mips/jz47xx/mipscfg.c
+81 -81
View File
@@ -1,82 +1,82 @@
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}
libcpu/mips/jz47xx/stack.c
+94 -94
View File
@@ -1,94 +1,94 @@
/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
#include <rtthread.h>
/**
* @addtogroup Jz47xx
*/
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x0403;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
#include <rtthread.h>
/**
* @addtogroup Jz47xx
*/
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x0403;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
libcpu/mips/jz47xx/start_gcc.S
+151 -151
View File
@@ -1,151 +1,151 @@
/*
* File : start_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "jz47xx.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* init cp0 registers. */
li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
mtc0 t0, CP0_STATUS
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* init caches, assumes a 4way * 128set * 32byte I/D cache */
li t0, 3 /* enable cache for kseg0 accesses */
mtc0 t0, CP0_CONFIG /* CONFIG reg */
la t0, 0x80000000 /* an idx op should use an unmappable address */
ori t1, t0, 0x4000 /* 16kB cache */
mtc0 zero, CP0_TAGLO /* TAGLO reg */
mtc0 zero, CP0_TAGHI /* TAGHI reg */
_cache_loop:
cache 0x8, 0(t0) /* index store icache tag */
cache 0x9, 0(t0) /* index store dcache tag */
bne t0, t1, _cache_loop
addiu t0, t0, 0x20 /* 32 bytes per cache line */
nop
/* invalidate BTB */
mfc0 t0, CP0_CONFIG
nop
ori t0, 2
mtc0 t0, CP0_CONFIG
nop
/* copy IRAM section */
la t0, _iramcopy
la t1, _iramstart
la t2, _iramend
_iram_loop:
lw t3, 0(t0)
sw t3, 0(t1)
addiu t1, 4
bne t1, t2, _iram_loop
addiu t0, 4
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
mfc0 k1, CP0_CAUSE
andi k1, k1, 0x7c
srl k1, k1, 2
lw k0, sys_exception_handlers(k1)
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/*
* File : start_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "jz47xx.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* init cp0 registers. */
li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
mtc0 t0, CP0_STATUS
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* init caches, assumes a 4way * 128set * 32byte I/D cache */
li t0, 3 /* enable cache for kseg0 accesses */
mtc0 t0, CP0_CONFIG /* CONFIG reg */
la t0, 0x80000000 /* an idx op should use an unmappable address */
ori t1, t0, 0x4000 /* 16kB cache */
mtc0 zero, CP0_TAGLO /* TAGLO reg */
mtc0 zero, CP0_TAGHI /* TAGHI reg */
_cache_loop:
cache 0x8, 0(t0) /* index store icache tag */
cache 0x9, 0(t0) /* index store dcache tag */
bne t0, t1, _cache_loop
addiu t0, t0, 0x20 /* 32 bytes per cache line */
nop
/* invalidate BTB */
mfc0 t0, CP0_CONFIG
nop
ori t0, 2
mtc0 t0, CP0_CONFIG
nop
/* copy IRAM section */
la t0, _iramcopy
la t1, _iramstart
la t2, _iramend
_iram_loop:
lw t3, 0(t0)
sw t3, 0(t1)
addiu t1, 4
bne t1, t2, _iram_loop
addiu t0, 4
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
mfc0 k1, CP0_CAUSE
andi k1, k1, 0x7c
srl k1, k1, 2
lw k0, sys_exception_handlers(k1)
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
libcpu/mips/loongson/cache.c
+188 -188
View File
@@ -1,188 +1,188 @@
#include "../common/mipsregs.h"
#include "cache.h"
#define K0BASE 0x80000000
#define PRID_3210I 0x4200
typedef struct cacheinfo_t {
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t {
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu (void)
{
unsigned int cpu_id;
void invalidate_cache (void);
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_3210I:
rt_kprintf ("CPU:SoC3210\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I;
break;
default:
rt_kprintf ("Unknown CPU type, system halted!\n");
while (1) {}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config = read_c0_config ();
unsigned int icache_size, ic_lsize;
unsigned int dcache_size, dc_lsize;
icache_size = 1 << (12 + ((config >> 9) & 7));
dcache_size = 1 << (12 + ((config >> 6) & 7));
ic_lsize = 16 << ((config >> 5) & 1);
dc_lsize = 16 << ((config >> 4) & 1);
rt_kprintf("DCache %2dkb, linesize %d bytes.\n",
dcache_size >> 10, dc_lsize);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n",
icache_size >> 10, ic_lsize);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = ic_lsize;
pcacheinfo->dcacheline_size = dc_lsize;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
start = K0BASE;
while(start < end) {
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while(start <end){
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while(start < end) {
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all()
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start <end){
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start < end){
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while(start < end) {
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end) {
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end) {
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end) {
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}
#include "../common/mipsregs.h"
#include "cache.h"
#define K0BASE 0x80000000
#define PRID_3210I 0x4200
typedef struct cacheinfo_t {
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t {
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu (void)
{
unsigned int cpu_id;
void invalidate_cache (void);
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_3210I:
rt_kprintf ("CPU:SoC3210\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I;
break;
default:
rt_kprintf ("Unknown CPU type, system halted!\n");
while (1) {}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config = read_c0_config ();
unsigned int icache_size, ic_lsize;
unsigned int dcache_size, dc_lsize;
icache_size = 1 << (12 + ((config >> 9) & 7));
dcache_size = 1 << (12 + ((config >> 6) & 7));
ic_lsize = 16 << ((config >> 5) & 1);
dc_lsize = 16 << ((config >> 4) & 1);
rt_kprintf("DCache %2dkb, linesize %d bytes.\n",
dcache_size >> 10, dc_lsize);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n",
icache_size >> 10, ic_lsize);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = ic_lsize;
pcacheinfo->dcacheline_size = dc_lsize;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
start = K0BASE;
while(start < end) {
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while(start <end){
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while(start < end) {
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all()
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start <end){
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start < end){
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while(start < end) {
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end) {
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end) {
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end) {
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}
libcpu/mips/loongson/cache.h
+47 -47
View File
@@ -1,47 +1,47 @@
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Gc3210I (unsigned int);
extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int);
extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
void rt_hw_cache_init(void);
#endif
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Gc3210I (unsigned int);
extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int);
extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
void rt_hw_cache_init(void);
#endif
libcpu/mips/loongson/cache.inc
+38 -38
View File
@@ -1,38 +1,38 @@
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#endif
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#endif
libcpu/mips/loongson/context_gcc.S
+141 -141
View File
@@ -1,141 +1,141 @@
/*
* File : context_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "soc3210.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder
/*
* File : context_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "soc3210.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder
libcpu/mips/loongson/cpu.c
+50 -50
View File
@@ -1,50 +1,50 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include <soc3210.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WD_CTRL |= 0x01;
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
/*@}*/
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include <soc3210.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WD_CTRL |= 0x01;
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
/*@}*/
libcpu/mips/loongson/exception.c
+83 -83
View File
@@ -1,83 +1,83 @@
/*
* File : exception.c
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup SoC3210
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/
/*
* File : exception.c
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup SoC3210
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/
libcpu/mips/loongson/interrupt.c
+130 -130
View File
@@ -1,130 +1,130 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
*/
#include <rtthread.h>
#include "soc3210.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t index;
for (index = 0; index < MAX_INTR; index ++)
{
irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
INT_EN &= ~(1 << vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
INT_EN |= (1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
{
if (vector >= 0 && vector < MAX_INTR)
{
if (old_handler != RT_NULL)
*old_handler = irq_handle_table[vector];
if (new_handler != RT_NULL)
irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
}
}
void rt_interrupt_dispatch(void *ptreg)
{
int i;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
/* check os timer */
c0_status = read_c0_status();
if (c0_status & 0x8000)
{
rt_hw_timer_handler();
}
if (c0_status & 0x0400)
{
/* the hardware interrupt */
status |= INT_ISR;
if (!status) return;
for (i = MAX_INTR; i > 0; --i)
{
if ((status & (1<<i)))
{
status &= ~(1<<i);
irq_func = irq_handle_table[i];
/* do interrupt */
(*irq_func)(i);
/* ack interrupt */
INT_CLR = (1 << i);
}
}
}
}
/*@}*/
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
*/
#include <rtthread.h>
#include "soc3210.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t index;
for (index = 0; index < MAX_INTR; index ++)
{
irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
INT_EN &= ~(1 << vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
INT_EN |= (1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
{
if (vector >= 0 && vector < MAX_INTR)
{
if (old_handler != RT_NULL)
*old_handler = irq_handle_table[vector];
if (new_handler != RT_NULL)
irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
}
}
void rt_interrupt_dispatch(void *ptreg)
{
int i;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
/* check os timer */
c0_status = read_c0_status();
if (c0_status & 0x8000)
{
rt_hw_timer_handler();
}
if (c0_status & 0x0400)
{
/* the hardware interrupt */
status |= INT_ISR;
if (!status) return;
for (i = MAX_INTR; i > 0; --i)
{
if ((status & (1<<i)))
{
status &= ~(1<<i);
irq_func = irq_handle_table[i];
/* do interrupt */
(*irq_func)(i);
/* ack interrupt */
INT_CLR = (1 << i);
}
}
}
}
/*@}*/
libcpu/mips/loongson/mipscfg.c
+81 -81
View File
@@ -1,82 +1,82 @@
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}
libcpu/mips/loongson/soc3210.h
+172 -172
View File
@@ -1,172 +1,172 @@
#ifndef __SOC3210_H__
#define __SOC3210_H__
#include "../common/mipsregs.h"
/* registers */
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define EMI_BASE 0xBF000000
#define NN_BASE 0xBF000040
#define LCD_BASE 0xBF001000
#define HSB_MISC_BASE 0xBF003200
#define SPI_BASE 0xBF004000
#define PS2_BASE 0xBF004040
#define UART0_BASE 0xBF004080
#define UART1_BASE 0xBF004090
#define I2C_BASE 0xBF0040D0
#define LPB_MISC_BASE 0xBF004100
#define AC97_BASE 0xBF004200
#define AC97_DMA_BASE 0xBF004280
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
#define MAC0_BASE 0xBF005200
#define MAC1_BASE 0xBF005300
/* LCD registers */
#define LCD_CTRL __REG32(LCD_BASE + 0x000)
#define LCD_STAT __REG32(LCD_BASE + 0x004)
#define LCD_HTIM __REG32(LCD_BASE + 0x008)
#define LCD_VTIM __REG32(LCD_BASE + 0x00C)
#define LCD_HVLEN __REG32(LCD_BASE + 0x010)
#define LCD_VBARA __REG32(LCD_BASE + 0x014)
#define LCD_VBARB __REG32(LCD_BASE + 0x018)
#define LCD_PCLT __REG32(LCD_BASE + 0x800)
/* HSB misc registers */
#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00)
#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04)
#define INT_STEER __REG32(HSB_MISC_BASE + 0x08)
#define INT_POL __REG32(HSB_MISC_BASE + 0x0C)
#define INT_SET __REG32(HSB_MISC_BASE + 0x10)
#define INT_CLR __REG32(HSB_MISC_BASE + 0x14)
#define INT_EN __REG32(HSB_MISC_BASE + 0x18)
#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C)
#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20)
#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24)
#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28)
#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C)
#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30)
#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34)
/* SPI registers */
#define SPI_SPCR __REG8(SPI_BASE + 0x00)
#define SPI_SPSR __REG8(SPI_BASE + 0x01)
#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02)
#define SPI_SPER __REG8(SPI_BASE + 0x03)
/* PS/2 registers */
#define PS2_RIBUF __REG8(PS2_BASE + 0x00)
#define PS2_WOBUF __REG8(PS2_BASE + 0x00)
#define PS2_RSR __REG8(PS2_BASE + 0x04)
#define PS2_WSC __REG8(PS2_BASE + 0x04)
#define PS2_DLL __REG8(PS2_BASE + 0x08)
#define PS2_DLH __REG8(PS2_BASE + 0x09)
#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A)
#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B)
/* UART registers */
#define UART_DAT(base) __REG8(base + 0x00)
#define UART_IER(base) __REG8(base + 0x01)
#define UART_IIR(base) __REG8(base + 0x02)
#define UART_FCR(base) __REG8(base + 0x02)
#define UART_LCR(base) __REG8(base + 0x03)
#define UART_MCR(base) __REG8(base + 0x04)
#define UART_LSR(base) __REG8(base + 0x05)
#define UART_MSR(base) __REG8(base + 0x06)
#define UART_LSB(base) __REG8(base + 0x00)
#define UART_MSB(base) __REG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT __REG8(UART0_BASE + 0x00)
#define UART0_IER __REG8(UART0_BASE + 0x01)
#define UART0_IIR __REG8(UART0_BASE + 0x02)
#define UART0_FCR __REG8(UART0_BASE + 0x02)
#define UART0_LCR __REG8(UART0_BASE + 0x03)
#define UART0_MCR __REG8(UART0_BASE + 0x04)
#define UART0_LSR __REG8(UART0_BASE + 0x05)
#define UART0_MSR __REG8(UART0_BASE + 0x06)
#define UART0_LSB __REG8(UART0_BASE + 0x00)
#define UART0_MSB __REG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT __REG8(UART1_BASE + 0x00)
#define UART1_IER __REG8(UART1_BASE + 0x01)
#define UART1_IIR __REG8(UART1_BASE + 0x02)
#define UART1_FCR __REG8(UART1_BASE + 0x02)
#define UART1_LCR __REG8(UART1_BASE + 0x03)
#define UART1_MCR __REG8(UART1_BASE + 0x04)
#define UART1_LSR __REG8(UART1_BASE + 0x05)
#define UART1_MSR __REG8(UART1_BASE + 0x06)
#define UART1_LSB __REG8(UART1_BASE + 0x00)
#define UART1_MSB __REG8(UART1_BASE + 0x01)
/* LPB misc registers */
#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00)
#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01)
#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02)
#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03)
#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10)
#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11)
#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12)
#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13)
#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20)
#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21)
#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22)
#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23)
#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40)
/* MAC0 registers */
#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00)
#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08)
#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10)
#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18)
#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20)
#define MAC0_STATUS __REG32(MAC0_BASE + 0x28)
#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30)
#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38)
#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40)
#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48)
#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50)
#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58)
/* MAC1 registers */
#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00)
#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08)
#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10)
#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18)
#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20)
#define MAC1_STATUS __REG32(MAC1_BASE + 0x28)
#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30)
#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38)
#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40)
#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48)
#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50)
#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58)
/* Peripheral Interrupt Number */
#define IRQ_LCD 0
#define IRQ_MAC1 1
#define IRQ_MAC2 2
#define IRQ_AC97 3
#define IRQ_SPI 8
#define IRQ_KEY 9
#define IRQ_MOUSE 10
#define IRQ_UART0 11
#define IRQ_UART1 12
#define IRQ_I2C 13
#define IRQ_CAN0 14
#define IRQ_CAN1 15
#define IRQ_GPIO15 20
#define IRQ_GPIO14 21
#define IRQ_GPIO13 22
#define IRQ_GPIO12 23
#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
#endif
#ifndef __SOC3210_H__
#define __SOC3210_H__
#include "../common/mipsregs.h"
/* registers */
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define EMI_BASE 0xBF000000
#define NN_BASE 0xBF000040
#define LCD_BASE 0xBF001000
#define HSB_MISC_BASE 0xBF003200
#define SPI_BASE 0xBF004000
#define PS2_BASE 0xBF004040
#define UART0_BASE 0xBF004080
#define UART1_BASE 0xBF004090
#define I2C_BASE 0xBF0040D0
#define LPB_MISC_BASE 0xBF004100
#define AC97_BASE 0xBF004200
#define AC97_DMA_BASE 0xBF004280
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
#define MAC0_BASE 0xBF005200
#define MAC1_BASE 0xBF005300
/* LCD registers */
#define LCD_CTRL __REG32(LCD_BASE + 0x000)
#define LCD_STAT __REG32(LCD_BASE + 0x004)
#define LCD_HTIM __REG32(LCD_BASE + 0x008)
#define LCD_VTIM __REG32(LCD_BASE + 0x00C)
#define LCD_HVLEN __REG32(LCD_BASE + 0x010)
#define LCD_VBARA __REG32(LCD_BASE + 0x014)
#define LCD_VBARB __REG32(LCD_BASE + 0x018)
#define LCD_PCLT __REG32(LCD_BASE + 0x800)
/* HSB misc registers */
#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00)
#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04)
#define INT_STEER __REG32(HSB_MISC_BASE + 0x08)
#define INT_POL __REG32(HSB_MISC_BASE + 0x0C)
#define INT_SET __REG32(HSB_MISC_BASE + 0x10)
#define INT_CLR __REG32(HSB_MISC_BASE + 0x14)
#define INT_EN __REG32(HSB_MISC_BASE + 0x18)
#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C)
#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20)
#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24)
#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28)
#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C)
#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30)
#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34)
/* SPI registers */
#define SPI_SPCR __REG8(SPI_BASE + 0x00)
#define SPI_SPSR __REG8(SPI_BASE + 0x01)
#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02)
#define SPI_SPER __REG8(SPI_BASE + 0x03)
/* PS/2 registers */
#define PS2_RIBUF __REG8(PS2_BASE + 0x00)
#define PS2_WOBUF __REG8(PS2_BASE + 0x00)
#define PS2_RSR __REG8(PS2_BASE + 0x04)
#define PS2_WSC __REG8(PS2_BASE + 0x04)
#define PS2_DLL __REG8(PS2_BASE + 0x08)
#define PS2_DLH __REG8(PS2_BASE + 0x09)
#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A)
#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B)
/* UART registers */
#define UART_DAT(base) __REG8(base + 0x00)
#define UART_IER(base) __REG8(base + 0x01)
#define UART_IIR(base) __REG8(base + 0x02)
#define UART_FCR(base) __REG8(base + 0x02)
#define UART_LCR(base) __REG8(base + 0x03)
#define UART_MCR(base) __REG8(base + 0x04)
#define UART_LSR(base) __REG8(base + 0x05)
#define UART_MSR(base) __REG8(base + 0x06)
#define UART_LSB(base) __REG8(base + 0x00)
#define UART_MSB(base) __REG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT __REG8(UART0_BASE + 0x00)
#define UART0_IER __REG8(UART0_BASE + 0x01)
#define UART0_IIR __REG8(UART0_BASE + 0x02)
#define UART0_FCR __REG8(UART0_BASE + 0x02)
#define UART0_LCR __REG8(UART0_BASE + 0x03)
#define UART0_MCR __REG8(UART0_BASE + 0x04)
#define UART0_LSR __REG8(UART0_BASE + 0x05)
#define UART0_MSR __REG8(UART0_BASE + 0x06)
#define UART0_LSB __REG8(UART0_BASE + 0x00)
#define UART0_MSB __REG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT __REG8(UART1_BASE + 0x00)
#define UART1_IER __REG8(UART1_BASE + 0x01)
#define UART1_IIR __REG8(UART1_BASE + 0x02)
#define UART1_FCR __REG8(UART1_BASE + 0x02)
#define UART1_LCR __REG8(UART1_BASE + 0x03)
#define UART1_MCR __REG8(UART1_BASE + 0x04)
#define UART1_LSR __REG8(UART1_BASE + 0x05)
#define UART1_MSR __REG8(UART1_BASE + 0x06)
#define UART1_LSB __REG8(UART1_BASE + 0x00)
#define UART1_MSB __REG8(UART1_BASE + 0x01)
/* LPB misc registers */
#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00)
#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01)
#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02)
#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03)
#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10)
#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11)
#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12)
#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13)
#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20)
#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21)
#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22)
#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23)
#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40)
/* MAC0 registers */
#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00)
#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08)
#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10)
#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18)
#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20)
#define MAC0_STATUS __REG32(MAC0_BASE + 0x28)
#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30)
#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38)
#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40)
#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48)
#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50)
#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58)
/* MAC1 registers */
#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00)
#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08)
#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10)
#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18)
#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20)
#define MAC1_STATUS __REG32(MAC1_BASE + 0x28)
#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30)
#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38)
#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40)
#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48)
#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50)
#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58)
/* Peripheral Interrupt Number */
#define IRQ_LCD 0
#define IRQ_MAC1 1
#define IRQ_MAC2 2
#define IRQ_AC97 3
#define IRQ_SPI 8
#define IRQ_KEY 9
#define IRQ_MOUSE 10
#define IRQ_UART0 11
#define IRQ_UART1 12
#define IRQ_I2C 13
#define IRQ_CAN0 14
#define IRQ_CAN1 15
#define IRQ_GPIO15 20
#define IRQ_GPIO14 21
#define IRQ_GPIO13 22
#define IRQ_GPIO12 23
#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
#endif
libcpu/mips/loongson/stack.c
+96 -96
View File
@@ -1,96 +1,96 @@
/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
#include <rtthread.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
#include <rtthread.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
libcpu/mips/loongson/start_gcc.S
+130 -130
View File
@@ -1,130 +1,130 @@
/*
* File : start_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "soc3210.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
and t0, 0xfffffffe # By default it will be disabled.
mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
nop
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/*
* File : start_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "soc3210.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
and t0, 0xfffffffe # By default it will be disabled.
mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
nop
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
libcpu/mips/loongson_1b/cache.c
+228 -228
View File
@@ -1,228 +1,228 @@
/*
* File : cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
#define PRID_LS1B 0x4220
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Ls1b(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
typedef struct cacheinfo_t
{
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t
{
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu(void)
{
unsigned int cpu_id;
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_LS1B:
rt_kprintf("CPU:LS1B\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
break;
default:
rt_kprintf("Unknown CPU type, system halted!\n");
while (1)
{
;
}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config1 = read_c0_config1();
unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
if ((icache_line_size = ((config1 >> 19) & 7)))
icache_line_size = 2 << icache_line_size;
else
icache_line_size = icache_line_size;
icache_sets = 64 << ((config1 >> 22) & 7);
icache_ways = 1 + ((config1 >> 16) & 7);
icache_size = icache_sets * icache_ways * icache_line_size;
if ((dcache_line_size = ((config1 >> 10) & 7)))
dcache_line_size = 2 << dcache_line_size;
else
dcache_line_size = dcache_line_size;
dcache_sets = 64 << ((config1 >> 13) & 7);
dcache_ways = 1 + ((config1 >> 7) & 7);
dcache_size = dcache_sets * dcache_ways * dcache_line_size;
rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = icache_line_size;
pcacheinfo->dcacheline_size = dcache_line_size;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}
/*
* File : cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
#define PRID_LS1B 0x4220
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Ls1b(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
typedef struct cacheinfo_t
{
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t
{
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu(void)
{
unsigned int cpu_id;
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_LS1B:
rt_kprintf("CPU:LS1B\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
break;
default:
rt_kprintf("Unknown CPU type, system halted!\n");
while (1)
{
;
}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config1 = read_c0_config1();
unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
if ((icache_line_size = ((config1 >> 19) & 7)))
icache_line_size = 2 << icache_line_size;
else
icache_line_size = icache_line_size;
icache_sets = 64 << ((config1 >> 22) & 7);
icache_ways = 1 + ((config1 >> 16) & 7);
icache_size = icache_sets * icache_ways * icache_line_size;
if ((dcache_line_size = ((config1 >> 10) & 7)))
dcache_line_size = 2 << dcache_line_size;
else
dcache_line_size = dcache_line_size;
dcache_sets = 64 << ((config1 >> 13) & 7);
dcache_ways = 1 + ((config1 >> 7) & 7);
dcache_size = dcache_sets * dcache_ways * dcache_line_size;
rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = icache_line_size;
pcacheinfo->dcacheline_size = dcache_line_size;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}
libcpu/mips/loongson_1b/cache.h
+52 -52
View File
@@ -1,52 +1,52 @@
/*
* File : cache.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#endif
/*
* File : cache.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#endif
libcpu/mips/loongson_1b/context_gcc.S
+149 -149
View File
@@ -1,149 +1,149 @@
/*
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder
/*
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder
libcpu/mips/loongson_1b/cpuport.c
+124 -124
View File
@@ -1,124 +1,124 @@
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include "ls1b.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WDT_SET = 0x01; /* watch dog start */
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include "ls1b.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WDT_SET = 0x01; /* watch dog start */
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
libcpu/mips/loongson_1b/exception.c
+91 -91
View File
@@ -1,91 +1,91 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Loongson
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Loongson
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/
libcpu/mips/loongson_1b/interrupt.c
+170 -170
View File
@@ -1,170 +1,170 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
*/
#include <rtthread.h>
#include "ls1b.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t index;
/* pci active low */
ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq
/* make all interrupts level triggered */
(ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
/* mask all interrupts */
(ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
for (index = 0; index < MAX_INTR; index ++)
{
irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
(ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
(ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
{
if (vector >= 0 && vector < MAX_INTR)
{
if (old_handler != RT_NULL)
*old_handler = irq_handle_table[vector];
if (new_handler != RT_NULL)
irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
}
}
void rt_interrupt_dispatch(void *ptreg)
{
int i;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
rt_uint32_t c0_cause;
volatile rt_uint32_t cause_im;
volatile rt_uint32_t status_im;
rt_uint32_t pending_im;
/* check os timer */
c0_status = read_c0_status();
c0_cause = read_c0_cause();
cause_im = c0_cause & ST0_IM;
status_im = c0_status & ST0_IM;
pending_im = cause_im & status_im;
if (pending_im & CAUSEF_IP7)
{
rt_hw_timer_handler();
}
if (pending_im & CAUSEF_IP2)
{
/* the hardware interrupt */
status = ls1b_hw0_icregs->int_isr;
if (!status)
return;
for (i = MAX_INTR; i > 0; --i)
{
if ((status & (1<<i)))
{
status &= ~(1<<i);
irq_func = irq_handle_table[i];
/* do interrupt */
(*irq_func)(i);
/* ack interrupt */
ls1b_hw0_icregs->int_clr |= (1 << i);
}
}
}
else if (pending_im & CAUSEF_IP3)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP4)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP5)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP6)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
}
/*@}*/
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
*/
#include <rtthread.h>
#include "ls1b.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t index;
/* pci active low */
ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq
/* make all interrupts level triggered */
(ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
/* mask all interrupts */
(ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
for (index = 0; index < MAX_INTR; index ++)
{
irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
(ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
(ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
{
if (vector >= 0 && vector < MAX_INTR)
{
if (old_handler != RT_NULL)
*old_handler = irq_handle_table[vector];
if (new_handler != RT_NULL)
irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
}
}
void rt_interrupt_dispatch(void *ptreg)
{
int i;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
rt_uint32_t c0_cause;
volatile rt_uint32_t cause_im;
volatile rt_uint32_t status_im;
rt_uint32_t pending_im;
/* check os timer */
c0_status = read_c0_status();
c0_cause = read_c0_cause();
cause_im = c0_cause & ST0_IM;
status_im = c0_status & ST0_IM;
pending_im = cause_im & status_im;
if (pending_im & CAUSEF_IP7)
{
rt_hw_timer_handler();
}
if (pending_im & CAUSEF_IP2)
{
/* the hardware interrupt */
status = ls1b_hw0_icregs->int_isr;
if (!status)
return;
for (i = MAX_INTR; i > 0; --i)
{
if ((status & (1<<i)))
{
status &= ~(1<<i);
irq_func = irq_handle_table[i];
/* do interrupt */
(*irq_func)(i);
/* ack interrupt */
ls1b_hw0_icregs->int_clr |= (1 << i);
}
}
}
else if (pending_im & CAUSEF_IP3)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP4)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP5)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP6)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
}
/*@}*/
libcpu/mips/loongson_1b/mipscfg.c
+82 -82
View File
@@ -1,82 +1,82 @@
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}
/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}
libcpu/mips/loongson_1b/start_gcc.S
+137 -137
View File
@@ -1,137 +1,137 @@
/*
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
and t0, 0xfffffffe # By default it will be disabled.
mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
nop
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/*
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
and t0, 0xfffffffe # By default it will be disabled.
mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
nop
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
libcpu/mips/pic32/context_gcc.S
+121 -121
View File
@@ -1,121 +1,121 @@
#include <p32xxxx.h>
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".text", "ax"
.set noat
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS /* v0 = status */
addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */
and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */
mtc0 v1, CP0_STATUS /* status = v1 */
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
/* trigger the soft exception (causes context switch) */
mfc0 t0, CP0_CAUSE /* t0 = Cause */
ori t0, t0, (1<<8) /* t0 |= (1<<8) */
mtc0 t0, CP0_CAUSE /* cause = t0 */
addiu t1, zero, -257 /* t1 = ~(1<<8) */
and t0, t0, t1 /* t0 &= t1 */
mtc0 t0, CP0_CAUSE /* cause = t0 */
jr ra
nop
/*
* void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void)
*/
.section ".text", "ax"
.set noreorder
.set noat
.ent CoreSW0Handler
.globl CoreSW0Handler
CoreSW0Handler:
SAVE_ALL
/* mCS0ClearIntFlag(); */
la t0, IFS0CLR /* t0 = IFS0CLR */
addiu t1,zero,0x02 /* t1 = (1<<2) */
sw t1, 0(t0) /* IFS0CLR = t1 */
la k0, rt_thread_switch_interrupt_flag
sw zero, 0(k0) /* clear flag */
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
RESTORE_ALL_AND_RET
.end CoreSW0Handler
#include <p32xxxx.h>
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".text", "ax"
.set noat
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS /* v0 = status */
addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */
and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */
mtc0 v1, CP0_STATUS /* status = v1 */
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
/* trigger the soft exception (causes context switch) */
mfc0 t0, CP0_CAUSE /* t0 = Cause */
ori t0, t0, (1<<8) /* t0 |= (1<<8) */
mtc0 t0, CP0_CAUSE /* cause = t0 */
addiu t1, zero, -257 /* t1 = ~(1<<8) */
and t0, t0, t1 /* t0 &= t1 */
mtc0 t0, CP0_CAUSE /* cause = t0 */
jr ra
nop
/*
* void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void)
*/
.section ".text", "ax"
.set noreorder
.set noat
.ent CoreSW0Handler
.globl CoreSW0Handler
CoreSW0Handler:
SAVE_ALL
/* mCS0ClearIntFlag(); */
la t0, IFS0CLR /* t0 = IFS0CLR */
addiu t1,zero,0x02 /* t1 = (1<<2) */
sw t1, 0(t0) /* IFS0CLR = t1 */
la k0, rt_thread_switch_interrupt_flag
sw zero, 0(k0) /* clear flag */
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
RESTORE_ALL_AND_RET
.end CoreSW0Handler
libcpu/mips/pic32/cpuport.c
+96 -96
View File
@@ -1,96 +1,96 @@
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 20011-05-23 aozima the first version for PIC32.
* 20011-09-05 aozima merge all of C source code into cpuport.c.
*/
#include <rtthread.h>
/**
* @addtogroup PIC32
*/
/*@{*/
/* exception and interrupt handler table */
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
rt_uint32_t __attribute__((nomips16)) _get_gp(void)
{
rt_uint32_t result;
// get the gp reg
asm volatile("move %0, $28" : "=r"(result));
return result;
}
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */
*(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) 0; /* lo */
*(--stk) = (rt_uint32_t) 0; /* hi */
*(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */
*(--stk) = (rt_uint32_t) texit; /* 31 ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */
*(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */
*(--stk) = (rt_uint32_t) parameter; /* 4 a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */
*(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 20011-05-23 aozima the first version for PIC32.
* 20011-09-05 aozima merge all of C source code into cpuport.c.
*/
#include <rtthread.h>
/**
* @addtogroup PIC32
*/
/*@{*/
/* exception and interrupt handler table */
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
rt_uint32_t __attribute__((nomips16)) _get_gp(void)
{
rt_uint32_t result;
// get the gp reg
asm volatile("move %0, $28" : "=r"(result));
return result;
}
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */
*(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) 0; /* lo */
*(--stk) = (rt_uint32_t) 0; /* hi */
*(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */
*(--stk) = (rt_uint32_t) texit; /* 31 ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */
*(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */
*(--stk) = (rt_uint32_t) parameter; /* 4 a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */
*(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
libcpu/mips/pic32/exceptions.c
+22 -22
View File
@@ -60,7 +60,7 @@ static enum {
static unsigned int _epc_code;
static unsigned int _excep_addr;
#include <rtthread.h>
// this function overrides the normal _weak_ generic handler
void _general_exception_handler(void)
@@ -68,27 +68,27 @@ void _general_exception_handler(void)
asm volatile("mfc0 %0,$13" : "=r" (_excep_code));
asm volatile("mfc0 %0,$14" : "=r" (_excep_addr));
_excep_code = (_excep_code & 0x0000007C) >> 2;
rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code);
rt_kprintf("_excep_addr : %08X\r\n",_excep_addr);
switch(_excep_code)
{
case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break;
case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break;
case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break;
case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break;
case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break;
case EXCEP_Sys:rt_kprintf("syscall\r\n");break;
case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break;
case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break;
case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break;
case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break;
case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break;
case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break;
case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break;
case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break;
default : rt_kprintf("unkown exception\r\n");break;
_excep_code = (_excep_code & 0x0000007C) >> 2;
rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code);
rt_kprintf("_excep_addr : %08X\r\n",_excep_addr);
switch(_excep_code)
{
case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break;
case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break;
case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break;
case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break;
case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break;
case EXCEP_Sys:rt_kprintf("syscall\r\n");break;
case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break;
case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break;
case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break;
case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break;
case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break;
case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break;
case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break;
case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break;
default : rt_kprintf("unkown exception\r\n");break;
}
while (1) {