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This commit is contained in:
Bernard Xiong
2013-01-08 05:05:02 -08:00
parent b3cf278502
commit 72782e9203
229 changed files with 37399 additions and 37399 deletions
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libcpu/arm/AT91SAM7S/AT91SAM7S.h
+40 -40
View File
@@ -57,11 +57,11 @@ extern "C" {
#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */
#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */
/* ========== Register definition for PITC peripheral ========== */
#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
/* ========== Register definition for PITC peripheral ========== */
#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
/* ========== Register definition for UDP peripheral ========== */
#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */
@@ -241,42 +241,42 @@ extern "C" {
#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */
#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */
/******************************************************************************/
/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */
/******************************************************************************/
#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91C_ID_SYS 1 /* System Peripheral */
#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */
/******************************************************************************/
/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */
/******************************************************************************/
#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91C_ID_SYS 1 /* System Peripheral */
#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */
#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */
#define AT91C_ID_US0 6 /* USART 0 */
#define AT91C_ID_US1 7 /* USART 1 */
#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */
#define AT91C_ID_TWI 9 /* Two-Wire Interface */
#define AT91C_ID_PWMC 10 /* PWM Controller */
#define AT91C_ID_UDP 11 /* USB Device Port */
#define AT91C_ID_TC0 12 /* Timer Counter 0 */
#define AT91C_ID_TC1 13 /* Timer Counter 1 */
#define AT91C_ID_TC2 14 /* Timer Counter 2 */
#define AT91C_ID_15 15 /* Reserved */
#define AT91C_ID_16 16 /* Reserved */
#define AT91C_ID_17 17 /* Reserved */
#define AT91C_ID_18 18 /* Reserved */
#define AT91C_ID_19 19 /* Reserved */
#define AT91C_ID_20 20 /* Reserved */
#define AT91C_ID_21 21 /* Reserved */
#define AT91C_ID_22 22 /* Reserved */
#define AT91C_ID_23 23 /* Reserved */
#define AT91C_ID_24 24 /* Reserved */
#define AT91C_ID_25 25 /* Reserved */
#define AT91C_ID_26 26 /* Reserved */
#define AT91C_ID_27 27 /* Reserved */
#define AT91C_ID_28 28 /* Reserved */
#define AT91C_ID_29 29 /* Reserved */
#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */
#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */
#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */
#define AT91C_ID_US0 6 /* USART 0 */
#define AT91C_ID_US1 7 /* USART 1 */
#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */
#define AT91C_ID_TWI 9 /* Two-Wire Interface */
#define AT91C_ID_PWMC 10 /* PWM Controller */
#define AT91C_ID_UDP 11 /* USB Device Port */
#define AT91C_ID_TC0 12 /* Timer Counter 0 */
#define AT91C_ID_TC1 13 /* Timer Counter 1 */
#define AT91C_ID_TC2 14 /* Timer Counter 2 */
#define AT91C_ID_15 15 /* Reserved */
#define AT91C_ID_16 16 /* Reserved */
#define AT91C_ID_17 17 /* Reserved */
#define AT91C_ID_18 18 /* Reserved */
#define AT91C_ID_19 19 /* Reserved */
#define AT91C_ID_20 20 /* Reserved */
#define AT91C_ID_21 21 /* Reserved */
#define AT91C_ID_22 22 /* Reserved */
#define AT91C_ID_23 23 /* Reserved */
#define AT91C_ID_24 24 /* Reserved */
#define AT91C_ID_25 25 /* Reserved */
#define AT91C_ID_26 26 /* Reserved */
#define AT91C_ID_27 27 /* Reserved */
#define AT91C_ID_28 28 /* Reserved */
#define AT91C_ID_29 29 /* Reserved */
#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */
/*****************************/
/* CPU Mode */
libcpu/arm/AT91SAM7S/context_rvds.S
+14 -14
View File
@@ -12,12 +12,12 @@
; * 2009-01-20 Bernard first version
; */
NOINT EQU 0xc0 ; disable interrupt in psr
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
@@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
MSR cpsr_c, r1
BX lr
ENDP
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
MSR cpsr_c, r0
BX lr
ENDP
@@ -63,7 +63,7 @@ rt_hw_context_switch PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
@@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
@@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
STR r1, [r2]
BX lr
ENDP
ENDP
END
libcpu/arm/AT91SAM7S/interrupt.c
+4 -4
View File
@@ -56,11 +56,11 @@ void rt_hw_interrupt_init()
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
{
/* disable interrupt */
AT91C_AIC_IDCR = 1 << vector;
/* clear interrupt */
AT91C_AIC_IDCR = 1 << vector;
/* clear interrupt */
AT91C_AIC_ICCR = 1 << vector;
}
libcpu/arm/AT91SAM7S/serial.c
+325 -325
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/AT91SAM7S/serial.h
+13 -13
View File
@@ -1,14 +1,14 @@
#ifndef __RT_SERIAL_H__
#define __RT_SERIAL_H__
#ifndef AT91C_BASE_US0
#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
#endif
#ifndef AT91C_BASE_US1
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
#endif
#ifndef __RT_SERIAL_H__
#define __RT_SERIAL_H__
#ifndef AT91C_BASE_US0
#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
#endif
#ifndef AT91C_BASE_US1
#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
#endif
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */
@@ -52,5 +52,5 @@
#define MCK 48054857
#define BR 115200 /* Baud Rate */
#define BRD (MCK/16/BR) /* Baud Rate Divisor */
#endif
#endif
libcpu/arm/AT91SAM7S/start_rvds.S
+499 -499
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File diff suppressed because it is too large Load Diff
libcpu/arm/AT91SAM7X/start_rvds.S
+517 -517
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File diff suppressed because it is too large Load Diff
libcpu/arm/AT91SAM7X/trap.c
+4 -4
View File
@@ -36,12 +36,12 @@ void rt_hw_trap_fiq()
{
rt_kprintf("fast interrupt request\n");
}
extern struct rt_thread* rt_current_thread;
void rt_hw_trap_abort()
{
rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
rt_thread_suspend(rt_current_thread);
{
rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
rt_thread_suspend(rt_current_thread);
rt_schedule();
}
libcpu/arm/at91sam926x/cpu.c
+193 -193
View File
@@ -1,193 +1,193 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
*/
#include <rthw.h>
#include <rtthread.h>
#include "at91sam926x.h"
/**
* @addtogroup AT91SAM926X
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
static void at91sam9260_reset(void)
{
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91sam9260_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
rt_kprintf("Restarting system...\n");
at91sam9260_reset();
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/**
* shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
at91sam9260_poweroff();
while (level)
{
RT_ASSERT(0);
}
}
/*@}*/
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
*/
#include <rthw.h>
#include <rtthread.h>
#include "at91sam926x.h"
/**
* @addtogroup AT91SAM926X
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
static void at91sam9260_reset(void)
{
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91sam9260_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
rt_kprintf("Restarting system...\n");
at91sam9260_reset();
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/**
* shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
at91sam9260_poweroff();
while (level)
{
RT_ASSERT(0);
}
}
/*@}*/
libcpu/arm/at91sam926x/mmu.c
+395 -395
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/at91sam926x/serial.h
+76 -76
View File
@@ -1,76 +1,76 @@
#ifndef __RT_HW_SERIAL_H__
#define __RT_HW_SERIAL_H__
#include <rthw.h>
#include <rtthread.h>
#include "at91sam926x.h"
#define RXRDY 0x01
#define TXRDY (1 << 1)
#define BPS 115200 /* serial baudrate */
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_BUFFER_SIZE 64
struct serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct serial_int_tx
{
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
rt_uint32_t write_index, save_index;
};
typedef struct uartport
{
/* USART register offsets */
volatile rt_uint32_t USART_CR;
volatile rt_uint32_t USART_MR;
volatile rt_uint32_t USART_IER;
volatile rt_uint32_t USART_IDR;
volatile rt_uint32_t USART_IMR;
volatile rt_uint32_t USART_CSR;
volatile rt_uint32_t USART_RHR;
volatile rt_uint32_t USART_THR;
volatile rt_uint32_t USART_BRGR;
volatile rt_uint32_t USART_RTOR;
volatile rt_uint32_t USART_TTGR;
volatile rt_uint32_t reseverd0[5];
volatile rt_uint32_t USART_FIDI;
volatile rt_uint32_t USART_NER;
volatile rt_uint32_t USART_XXR;
volatile rt_uint32_t USART_IFR;
volatile rt_uint32_t reserved1[44];
volatile rt_uint32_t USART_RPR;
volatile rt_uint32_t USART_RCR;
volatile rt_uint32_t USART_TPR;
volatile rt_uint32_t USART_TCR;
volatile rt_uint32_t USART_RNPR;
volatile rt_uint32_t USART_RNCR;
volatile rt_uint32_t USART_TNPR;
volatile rt_uint32_t USART_TNCR;
volatile rt_uint32_t USART_PTCR;
volatile rt_uint32_t USART_PTSR;
}uartport;
struct serial_device
{
uartport* uart_device;
/* rx structure */
struct serial_int_rx* int_rx;
/* tx structure */
struct serial_int_tx* int_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
#endif
#ifndef __RT_HW_SERIAL_H__
#define __RT_HW_SERIAL_H__
#include <rthw.h>
#include <rtthread.h>
#include "at91sam926x.h"
#define RXRDY 0x01
#define TXRDY (1 << 1)
#define BPS 115200 /* serial baudrate */
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_BUFFER_SIZE 64
struct serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct serial_int_tx
{
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
rt_uint32_t write_index, save_index;
};
typedef struct uartport
{
/* USART register offsets */
volatile rt_uint32_t USART_CR;
volatile rt_uint32_t USART_MR;
volatile rt_uint32_t USART_IER;
volatile rt_uint32_t USART_IDR;
volatile rt_uint32_t USART_IMR;
volatile rt_uint32_t USART_CSR;
volatile rt_uint32_t USART_RHR;
volatile rt_uint32_t USART_THR;
volatile rt_uint32_t USART_BRGR;
volatile rt_uint32_t USART_RTOR;
volatile rt_uint32_t USART_TTGR;
volatile rt_uint32_t reseverd0[5];
volatile rt_uint32_t USART_FIDI;
volatile rt_uint32_t USART_NER;
volatile rt_uint32_t USART_XXR;
volatile rt_uint32_t USART_IFR;
volatile rt_uint32_t reserved1[44];
volatile rt_uint32_t USART_RPR;
volatile rt_uint32_t USART_RCR;
volatile rt_uint32_t USART_TPR;
volatile rt_uint32_t USART_TCR;
volatile rt_uint32_t USART_RNPR;
volatile rt_uint32_t USART_RNCR;
volatile rt_uint32_t USART_TNPR;
volatile rt_uint32_t USART_TNCR;
volatile rt_uint32_t USART_PTCR;
volatile rt_uint32_t USART_PTSR;
}uartport;
struct serial_device
{
uartport* uart_device;
/* rx structure */
struct serial_int_rx* int_rx;
/* tx structure */
struct serial_int_tx* int_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
#endif
libcpu/arm/at91sam926x/start_rvds.S
+315 -315
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/at91sam926x/system_clock.c
+294 -294
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File diff suppressed because it is too large Load Diff
libcpu/arm/common/backtrace.c
+67 -67
View File
@@ -1,67 +1,67 @@
/*
* File : backtrace.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-07-29 Bernard first version from QiuYi implementation
*/
#include <rtthread.h>
#ifdef __GNUC__
/*
-->High Address,Stack Top
PC<-----|
LR |
IP |
FP |
...... |
PC<-| |
LR | |
IP | |
FP---|-- |
...... |
PC |
LR |
IP |
FP---
-->Low Address,Stack Bottom
*/
void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
{
rt_uint32_t i, pc, func_entry;
pc = *fp;
rt_kprintf("[0x%x]\n", pc-0xC);
for(i=0; i<10; i++)
{
fp = (rt_uint32_t *)*(fp - 3);
pc = *fp ;
func_entry = pc - 0xC;
if(func_entry <= 0x30000000) break;
if((func_entry == thread_entry))
{
rt_kprintf("EntryPoint:0x%x\n", func_entry);
break;
}
rt_kprintf("[0x%x]\n", func_entry);
}
}
#else
void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
{
/* old compiler implementation */
}
#endif
/*
* File : backtrace.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-07-29 Bernard first version from QiuYi implementation
*/
#include <rtthread.h>
#ifdef __GNUC__
/*
-->High Address,Stack Top
PC<-----|
LR |
IP |
FP |
...... |
PC<-| |
LR | |
IP | |
FP---|-- |
...... |
PC |
LR |
IP |
FP---
-->Low Address,Stack Bottom
*/
void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
{
rt_uint32_t i, pc, func_entry;
pc = *fp;
rt_kprintf("[0x%x]\n", pc-0xC);
for(i=0; i<10; i++)
{
fp = (rt_uint32_t *)*(fp - 3);
pc = *fp ;
func_entry = pc - 0xC;
if(func_entry <= 0x30000000) break;
if((func_entry == thread_entry))
{
rt_kprintf("EntryPoint:0x%x\n", func_entry);
break;
}
rt_kprintf("[0x%x]\n", func_entry);
}
}
#else
void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
{
/* old compiler implementation */
}
#endif
libcpu/arm/common/showmem.c
+42 -42
View File
@@ -1,42 +1,42 @@
/*
* File : showmem.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-07-29 Bernard first version from QiuYi implementation
*/
#include <rtthread.h>
void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size)
{
int i = 0, j =0;
RT_ASSERT(addr);
addr = addr & ~0xF;
size = 4*((size + 3)/4);
while(i < size)
{
rt_kprintf("0x%08x: ", addr );
for(j=0; j<4; j++)
{
rt_kprintf("0x%08x ", *(rt_uint32_t *)addr);
addr += 4;
i++;
}
rt_kprintf("\n");
}
return;
}
/*
* File : showmem.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-07-29 Bernard first version from QiuYi implementation
*/
#include <rtthread.h>
void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size)
{
int i = 0, j =0;
RT_ASSERT(addr);
addr = addr & ~0xF;
size = 4*((size + 3)/4);
while(i < size)
{
rt_kprintf("0x%08x: ", addr );
for(j=0; j<4; j++)
{
rt_kprintf("0x%08x ", *(rt_uint32_t *)addr);
addr += 4;
i++;
}
rt_kprintf("\n");
}
return;
}
libcpu/arm/cortex-m0/context_iar.S
+201 -201
View File
@@ -1,201 +1,201 @@
;/*
; * File : context_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r8 - r11.
; */
;/**
; * @addtogroup CORTEX-M0
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
BX LR
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
EXPORT rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOVS r3, #0x1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
EXPORT PendSV_Handler
PendSV_Handler:
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CMP r1, #0x00
BEQ pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOVS r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CMP r1, #0x00
BEQ swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11}
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack
MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
MOV r5, r9
MOV r6, r10
MOV r7, r11
STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack
PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
MOV r9, r5
MOV r10, r6
MOV r11, r7
POP {r4 - r7} ; pop {r4 - r7} from MSP
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
MOVS r0, #0x04
RSBS r0, r0, #0x00
BX r0
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
EXPORT rt_hw_context_switch_to
rt_hw_context_switch_to:
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOVS r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOVS r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read
ORRS r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
NOP
; enable interrupts at processor level
CPSIE I
; never reach here!
; compatible with old version
EXPORT rt_hw_interrupt_thread_switch
rt_hw_interrupt_thread_switch:
BX lr
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler:
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {pc}
END
;/*
; * File : context_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r8 - r11.
; */
;/**
; * @addtogroup CORTEX-M0
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
BX LR
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
EXPORT rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOVS r3, #0x1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
EXPORT PendSV_Handler
PendSV_Handler:
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CMP r1, #0x00
BEQ pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOVS r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CMP r1, #0x00
BEQ swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11}
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack
MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
MOV r5, r9
MOV r6, r10
MOV r7, r11
STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack
PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
MOV r9, r5
MOV r10, r6
MOV r11, r7
POP {r4 - r7} ; pop {r4 - r7} from MSP
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
MOVS r0, #0x04
RSBS r0, r0, #0x00
BX r0
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
EXPORT rt_hw_context_switch_to
rt_hw_context_switch_to:
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOVS r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOVS r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read
ORRS r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
NOP
; enable interrupts at processor level
CPSIE I
; never reach here!
; compatible with old version
EXPORT rt_hw_interrupt_thread_switch
rt_hw_interrupt_thread_switch:
BX lr
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler:
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {pc}
END
libcpu/arm/cortex-m0/context_rvds.S
+210 -210
View File
@@ -1,210 +1,210 @@
;/*
; * File : context_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r8 - r11.
; */
;/**
; * @addtogroup CORTEX-M0
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0
BX LR
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOVS r3, #0x01
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
ENDP
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
PendSV_Handler PROC
EXPORT PendSV_Handler
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CMP r1, #0x00
BEQ pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOVS r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CMP r1, #0x00
BEQ swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11}
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack
MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
MOV r5, r9
MOV r6, r10
MOV r7, r11
STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack
PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
MOV r9, r5
MOV r10, r6
MOV r11, r7
POP {r4 - r7} ; pop {r4 - r7} from MSP
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
MOVS r0, #0x04
RSBS r0, r0, #0x00
BX r0
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOVS r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOVS r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read
ORRS r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
NOP
; enable interrupts at processor level
CPSIE I
; never reach here!
ENDP
; compatible with old version
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
ENDP
IMPORT rt_hw_hard_fault_exception
HardFault_Handler PROC
EXPORT HardFault_Handler
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {pc}
ENDP
END
;/*
; * File : context_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r8 - r11.
; */
;/**
; * @addtogroup CORTEX-M0
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0
BX LR
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOVS r3, #0x01
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
ENDP
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
PendSV_Handler PROC
EXPORT PendSV_Handler
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CMP r1, #0x00
BEQ pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOVS r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CMP r1, #0x00
BEQ swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11}
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack
MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
MOV r5, r9
MOV r6, r10
MOV r7, r11
STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack
PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
MOV r9, r5
MOV r10, r6
MOV r11, r7
POP {r4 - r7} ; pop {r4 - r7} from MSP
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
MOVS r0, #0x04
RSBS r0, r0, #0x00
BX r0
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOVS r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOVS r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read
ORRS r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
NOP
; enable interrupts at processor level
CPSIE I
; never reach here!
ENDP
; compatible with old version
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
ENDP
IMPORT rt_hw_hard_fault_exception
HardFault_Handler PROC
EXPORT HardFault_Handler
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {pc}
ENDP
END
libcpu/arm/cortex-m3/context_gcc.S
+186 -186
View File
@@ -1,186 +1,186 @@
/*
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard First version
* 2010-12-29 onelife Modify for EFM32
* 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S
* 2011-07-12 onelife Add interrupt context check function
*/
.cpu cortex-m3
.fpu softvfp
.syntax unified
.thumb
.text
.equ ICSR, 0xE000ED04 /* interrupt control state register */
.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
.equ SHPR3, 0xE000ED20 /* system priority register (3) */
.equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.global rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
MRS R0, PRIMASK
CPSID I
BX LR
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.global rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
MSR PRIMASK, R0
BX LR
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* R0 --> from
* R1 --> to
*/
.global rt_hw_context_switch_interrupt
.type rt_hw_context_switch_interrupt, %function
.global rt_hw_context_switch
.type rt_hw_context_switch, %function
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
/* set rt_thread_switch_interrupt_flag to 1 */
LDR R2, =rt_thread_switch_interrupt_flag
LDR R3, [R2]
CMP R3, #1
BEQ _reswitch
MOV R3, #1
STR R3, [R2]
LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
STR R0, [R2]
_reswitch:
LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
STR R1, [R2]
LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
LDR R1, =PENDSVSET_BIT
STR R1, [R0]
BX LR
/* R0 --> swith from thread stack
* R1 --> swith to thread stack
* psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
*/
.global PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
/* disable interrupt to protect context switch */
MRS R2, PRIMASK
CPSID I
/* get rt_thread_switch_interrupt_flag */
LDR R0, =rt_thread_switch_interrupt_flag
LDR R1, [R0]
CBZ R1, pendsv_exit /* pendsv aLReady handled */
/* clear rt_thread_switch_interrupt_flag to 0 */
MOV R1, #0
STR R1, [R0]
LDR R0, =rt_interrupt_from_thread
LDR R1, [R0]
CBZ R1, swtich_to_thread /* skip register save at the first time */
MRS R1, PSP /* get from thread stack pointer */
STMFD R1!, {R4 - R11} /* push R4 - R11 register */
LDR R0, [R0]
STR R1, [R0] /* update from thread stack pointer */
swtich_to_thread:
LDR R1, =rt_interrupt_to_thread
LDR R1, [R1]
LDR R1, [R1] /* load thread stack pointer */
LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */
MSR PSP, R1 /* update stack pointer */
pendsv_exit:
/* restore interrupt */
MSR PRIMASK, R2
ORR LR, LR, #0x04
BX LR
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* R0 --> to
*/
.global rt_hw_context_switch_to
.type rt_hw_context_switch_to, %function
rt_hw_context_switch_to:
LDR R1, =rt_interrupt_to_thread
STR R0, [R1]
/* set from thread to 0 */
LDR R1, =rt_interrupt_from_thread
MOV R0, #0
STR R0, [R1]
/* set interrupt flag to 1 */
LDR R1, =rt_thread_switch_interrupt_flag
MOV R0, #1
STR R0, [R1]
/* set the PendSV exception priority */
LDR R0, =SHPR3
LDR R1, =PENDSV_PRI_LOWEST
LDR.W R2, [R0,#0] /* read */
ORR R1, R1, R2 /* modify */
STR R1, [R0] /* write-back */
LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
LDR R1, =PENDSVSET_BIT
STR R1, [R0]
CPSIE I /* enable interrupts at processor level */
/* never reach here! */
/* compatible with old version */
.global rt_hw_interrupt_thread_switch
.type rt_hw_interrupt_thread_switch, %function
rt_hw_interrupt_thread_switch:
BX LR
NOP
.global HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
/* get current context */
MRS R0, PSP /* get fault thread stack pointer */
PUSH {LR}
BL rt_hw_hard_fault_exception
POP {LR}
ORR LR, LR, #0x04
BX LR
/*
* rt_uint32_t rt_hw_interrupt_check(void);
* R0 --> state
*/
.global rt_hw_interrupt_check
.type rt_hw_interrupt_check, %function
rt_hw_interrupt_check:
MRS R0, IPSR
BX LR
/*
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard First version
* 2010-12-29 onelife Modify for EFM32
* 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S
* 2011-07-12 onelife Add interrupt context check function
*/
.cpu cortex-m3
.fpu softvfp
.syntax unified
.thumb
.text
.equ ICSR, 0xE000ED04 /* interrupt control state register */
.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
.equ SHPR3, 0xE000ED20 /* system priority register (3) */
.equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.global rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
MRS R0, PRIMASK
CPSID I
BX LR
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.global rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
MSR PRIMASK, R0
BX LR
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* R0 --> from
* R1 --> to
*/
.global rt_hw_context_switch_interrupt
.type rt_hw_context_switch_interrupt, %function
.global rt_hw_context_switch
.type rt_hw_context_switch, %function
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
/* set rt_thread_switch_interrupt_flag to 1 */
LDR R2, =rt_thread_switch_interrupt_flag
LDR R3, [R2]
CMP R3, #1
BEQ _reswitch
MOV R3, #1
STR R3, [R2]
LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
STR R0, [R2]
_reswitch:
LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
STR R1, [R2]
LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
LDR R1, =PENDSVSET_BIT
STR R1, [R0]
BX LR
/* R0 --> swith from thread stack
* R1 --> swith to thread stack
* psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
*/
.global PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
/* disable interrupt to protect context switch */
MRS R2, PRIMASK
CPSID I
/* get rt_thread_switch_interrupt_flag */
LDR R0, =rt_thread_switch_interrupt_flag
LDR R1, [R0]
CBZ R1, pendsv_exit /* pendsv aLReady handled */
/* clear rt_thread_switch_interrupt_flag to 0 */
MOV R1, #0
STR R1, [R0]
LDR R0, =rt_interrupt_from_thread
LDR R1, [R0]
CBZ R1, swtich_to_thread /* skip register save at the first time */
MRS R1, PSP /* get from thread stack pointer */
STMFD R1!, {R4 - R11} /* push R4 - R11 register */
LDR R0, [R0]
STR R1, [R0] /* update from thread stack pointer */
swtich_to_thread:
LDR R1, =rt_interrupt_to_thread
LDR R1, [R1]
LDR R1, [R1] /* load thread stack pointer */
LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */
MSR PSP, R1 /* update stack pointer */
pendsv_exit:
/* restore interrupt */
MSR PRIMASK, R2
ORR LR, LR, #0x04
BX LR
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* R0 --> to
*/
.global rt_hw_context_switch_to
.type rt_hw_context_switch_to, %function
rt_hw_context_switch_to:
LDR R1, =rt_interrupt_to_thread
STR R0, [R1]
/* set from thread to 0 */
LDR R1, =rt_interrupt_from_thread
MOV R0, #0
STR R0, [R1]
/* set interrupt flag to 1 */
LDR R1, =rt_thread_switch_interrupt_flag
MOV R0, #1
STR R0, [R1]
/* set the PendSV exception priority */
LDR R0, =SHPR3
LDR R1, =PENDSV_PRI_LOWEST
LDR.W R2, [R0,#0] /* read */
ORR R1, R1, R2 /* modify */
STR R1, [R0] /* write-back */
LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
LDR R1, =PENDSVSET_BIT
STR R1, [R0]
CPSIE I /* enable interrupts at processor level */
/* never reach here! */
/* compatible with old version */
.global rt_hw_interrupt_thread_switch
.type rt_hw_interrupt_thread_switch, %function
rt_hw_interrupt_thread_switch:
BX LR
NOP
.global HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
/* get current context */
MRS R0, PSP /* get fault thread stack pointer */
PUSH {LR}
BL rt_hw_hard_fault_exception
POP {LR}
ORR LR, LR, #0x04
BX LR
/*
* rt_uint32_t rt_hw_interrupt_check(void);
* R0 --> state
*/
.global rt_hw_interrupt_check
.type rt_hw_interrupt_check, %function
rt_hw_interrupt_check:
MRS R0, IPSR
BX LR
libcpu/arm/cortex-m3/context_rvds.S
+188 -188
View File
@@ -1,188 +1,188 @@
;/*
; * File : context_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; */
;/**
; * @addtogroup CORTEX-M3
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0
BX LR
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
ENDP
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
PendSV_Handler PROC
EXPORT PendSV_Handler
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
; enable interrupts at processor level
CPSIE I
; never reach here!
ENDP
; compatible with old version
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
NOP
ENDP
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler PROC
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
ENDP
END
;/*
; * File : context_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; */
;/**
; * @addtogroup CORTEX-M3
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0
BX LR
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
ENDP
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
PendSV_Handler PROC
EXPORT PendSV_Handler
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
; enable interrupts at processor level
CPSIE I
; never reach here!
ENDP
; compatible with old version
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
NOP
ENDP
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler PROC
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
ENDP
END
libcpu/arm/cortex-m4/context_gcc.S
+188 -188
View File
@@ -1,188 +1,188 @@
/*
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard first version
* 2012-01-01 aozima support context switch load/store FPU register.
*/
/**
* @addtogroup STM32
*/
/*@{*/
.cpu cortex-m4
.syntax unified
.thumb
.text
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.global rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
BX LR
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.global rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* r0 --> from
* r1 --> to
*/
.global rt_hw_context_switch_interrupt
.type rt_hw_context_switch_interrupt, %function
.global rt_hw_context_switch
.type rt_hw_context_switch, %function
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
/* set rt_thread_switch_interrupt_flag to 1 */
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
STR r0, [r2]
_reswitch:
LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
/* r0 --> swith from thread stack
* r1 --> swith to thread stack
* psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
*/
.global PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
/* disable interrupt to protect context switch */
MRS r2, PRIMASK
CPSID I
/* get rt_thread_switch_interrupt_flag */
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit /* pendsv already handled */
/* clear rt_thread_switch_interrupt_flag to 0 */
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread /* skip register save at the first time */
MRS r1, psp /* get from thread stack pointer */
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
VSTMDB r1!, {d8 - d15} /* push FPU register s16~s31 */
#endif
STMFD r1!, {r4 - r11} /* push r4 - r11 register */
LDR r0, [r0]
STR r1, [r0] /* update from thread stack pointer */
swtich_to_thread:
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] /* load thread stack pointer */
LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
VLDMIA r1!, {d8 - d15} /* pop FPU register s16~s31 */
#endif
MSR psp, r1 /* update stack pointer */
pendsv_exit:
/* restore interrupt */
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* r0 --> to
*/
.global rt_hw_context_switch_to
.type rt_hw_context_switch_to, %function
rt_hw_context_switch_to:
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
/* set from thread to 0 */
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
/* set interrupt flag to 1 */
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
/* set the PendSV exception priority */
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] /* read */
ORR r1,r1,r2 /* modify */
STR r1, [r0] /* write-back */
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
CPSIE I /* enable interrupts at processor level */
/* never reach here! */
/* compatible with old version */
.global rt_hw_interrupt_thread_switch
.type rt_hw_interrupt_thread_switch, %function
rt_hw_interrupt_thread_switch:
BX lr
NOP
.global HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
/* get current context */
MRS r0, psp /* get fault thread stack pointer */
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
/*
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard first version
* 2012-01-01 aozima support context switch load/store FPU register.
*/
/**
* @addtogroup STM32
*/
/*@{*/
.cpu cortex-m4
.syntax unified
.thumb
.text
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.global rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
BX LR
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.global rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* r0 --> from
* r1 --> to
*/
.global rt_hw_context_switch_interrupt
.type rt_hw_context_switch_interrupt, %function
.global rt_hw_context_switch
.type rt_hw_context_switch, %function
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
/* set rt_thread_switch_interrupt_flag to 1 */
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
STR r0, [r2]
_reswitch:
LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
/* r0 --> swith from thread stack
* r1 --> swith to thread stack
* psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
*/
.global PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
/* disable interrupt to protect context switch */
MRS r2, PRIMASK
CPSID I
/* get rt_thread_switch_interrupt_flag */
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit /* pendsv already handled */
/* clear rt_thread_switch_interrupt_flag to 0 */
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread /* skip register save at the first time */
MRS r1, psp /* get from thread stack pointer */
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
VSTMDB r1!, {d8 - d15} /* push FPU register s16~s31 */
#endif
STMFD r1!, {r4 - r11} /* push r4 - r11 register */
LDR r0, [r0]
STR r1, [r0] /* update from thread stack pointer */
swtich_to_thread:
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] /* load thread stack pointer */
LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
VLDMIA r1!, {d8 - d15} /* pop FPU register s16~s31 */
#endif
MSR psp, r1 /* update stack pointer */
pendsv_exit:
/* restore interrupt */
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* r0 --> to
*/
.global rt_hw_context_switch_to
.type rt_hw_context_switch_to, %function
rt_hw_context_switch_to:
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
/* set from thread to 0 */
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
/* set interrupt flag to 1 */
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
/* set the PendSV exception priority */
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] /* read */
ORR r1,r1,r2 /* modify */
STR r1, [r0] /* write-back */
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
CPSIE I /* enable interrupts at processor level */
/* never reach here! */
/* compatible with old version */
.global rt_hw_interrupt_thread_switch
.type rt_hw_interrupt_thread_switch, %function
rt_hw_interrupt_thread_switch:
BX lr
NOP
.global HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
/* get current context */
MRS r0, psp /* get fault thread stack pointer */
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
libcpu/arm/cortex-m4/context_iar.S
+187 -187
View File
@@ -1,187 +1,187 @@
;/*
; * File : context_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; * 2009-09-27 Bernard add protect when contex switch occurs
; * 2012-01-01 aozima support context switch load/store FPU register.
; */
;/**
; * @addtogroup STM32
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
BX LR
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
EXPORT rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
EXPORT PendSV_Handler
PendSV_Handler:
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
#if defined ( __ARMVFP__ )
VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31
#endif
STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
#if defined ( __ARMVFP__ )
VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31
#endif
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
EXPORT rt_hw_context_switch_to
rt_hw_context_switch_to:
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-back
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
CPSIE I ; enable interrupts at processor level
; never reach here!
; compatible with old version
EXPORT rt_hw_interrupt_thread_switch
rt_hw_interrupt_thread_switch:
BX lr
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler:
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
END
;/*
; * File : context_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; * 2009-09-27 Bernard add protect when contex switch occurs
; * 2012-01-01 aozima support context switch load/store FPU register.
; */
;/**
; * @addtogroup STM32
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
BX LR
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
EXPORT rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch
rt_hw_context_switch_interrupt:
rt_hw_context_switch:
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
EXPORT PendSV_Handler
PendSV_Handler:
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
#if defined ( __ARMVFP__ )
VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31
#endif
STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
#if defined ( __ARMVFP__ )
VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31
#endif
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
EXPORT rt_hw_context_switch_to
rt_hw_context_switch_to:
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-back
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
CPSIE I ; enable interrupts at processor level
; never reach here!
; compatible with old version
EXPORT rt_hw_interrupt_thread_switch
rt_hw_interrupt_thread_switch:
BX lr
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler:
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
END
libcpu/arm/cortex-m4/context_rvds.S
+199 -199
View File
@@ -1,199 +1,199 @@
;/*
; * File : context_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version.
; * 2012-01-01 aozima support context switch load/store FPU register.
; */
;/**
; * @addtogroup STM32
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0
BX LR
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
ENDP
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
PendSV_Handler PROC
EXPORT PendSV_Handler
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
IF {FPU} != "SoftVFP"
VSTMFD r1!, {d8 - d15} ; push FPU register s16~s31
ENDIF
STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
IF {FPU} != "SoftVFP"
VLDMFD r1!, {d8 - d15} ; pop FPU register s16~s31
ENDIF
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
; enable interrupts at processor level
CPSIE I
; never reach here!
ENDP
; compatible with old version
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
NOP
ENDP
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler PROC
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
ENDP
END
;/*
; * File : context_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version.
; * 2012-01-01 aozima support context switch load/store FPU register.
; */
;/**
; * @addtogroup STM32
; */
;/*@{*/
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK
CPSID I
BX LR
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0
BX LR
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC
EXPORT rt_hw_context_switch
; set rt_thread_switch_interrupt_flag to 1
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX LR
ENDP
; r0 --> swith from thread stack
; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
PendSV_Handler PROC
EXPORT PendSV_Handler
; disable interrupt to protect context switch
MRS r2, PRIMASK
CPSID I
; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrupt_flag to 0
MOV r1, #0x00
STR r1, [r0]
LDR r0, =rt_interrupt_from_thread
LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer
IF {FPU} != "SoftVFP"
VSTMFD r1!, {d8 - d15} ; push FPU register s16~s31
ENDIF
STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer
swtich_to_thread
LDR r1, =rt_interrupt_to_thread
LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
IF {FPU} != "SoftVFP"
VLDMFD r1!, {d8 - d15} ; pop FPU register s16~s31
ENDIF
MSR psp, r1 ; update stack pointer
pendsv_exit
; restore interrupt
MSR PRIMASK, r2
ORR lr, lr, #0x04
BX lr
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; * this fucntion is used to perform the first thread switch
; */
rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
; set to thread
LDR r1, =rt_interrupt_to_thread
STR r0, [r1]
; set from thread to 0
LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0
STR r0, [r1]
; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrupt_flag
MOV r0, #1
STR r0, [r1]
; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
; enable interrupts at processor level
CPSIE I
; never reach here!
ENDP
; compatible with old version
rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch
BX lr
NOP
ENDP
IMPORT rt_hw_hard_fault_exception
EXPORT HardFault_Handler
HardFault_Handler PROC
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
ENDP
END
libcpu/arm/lpc214x/context_rvds.S
+13 -13
View File
@@ -24,12 +24,12 @@ Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
NOINT EQU 0xc0 ; disable interrupt in psr
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
@@ -38,16 +38,16 @@ rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
MSR cpsr_c, r1
BX lr
ENDP
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
MSR cpsr_c, r0
BX lr
ENDP
@@ -77,7 +77,7 @@ _ARM_MODE
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
ENDP
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
@@ -93,14 +93,14 @@ rt_hw_context_switch_to PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
ENDP
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
@@ -114,9 +114,9 @@ rt_hw_context_switch_interrupt PROC
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
STR r1, [r2]
BX lr
ENDP
ENDP
; /*
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
libcpu/arm/lpc214x/cpuport.c
+72 -72
View File
@@ -1,30 +1,30 @@
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-06-15 aozima the first version for lpc214x
*/
#include <rtthread.h>
#include "lpc214x.h"
#define MAX_HANDLERS 32
#define SVCMODE 0x13
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-06-15 aozima the first version for lpc214x
*/
extern rt_uint32_t rt_interrupt_nest;
#include <rtthread.h>
#include "lpc214x.h"
#define MAX_HANDLERS 32
#define SVCMODE 0x13
extern rt_uint32_t rt_interrupt_nest;
/**
* @addtogroup LPC214x
*/
/*@{*/
/*@{*/
/**
* This function will initialize thread stack
*
@@ -56,25 +56,25 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (unsigned long)parameter; /* r0 : argument */
/* cpsr */
if ((rt_uint32_t)tentry & 0x01)
/* cpsr */
if ((rt_uint32_t)tentry & 0x01)
*(--stk) = SVCMODE | 0x20; /* thumb mode */
else
else
*(--stk) = SVCMODE; /* arm mode */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
}
/* exception and interrupt handler table */
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
/* exception and interrupt handler table */
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
}
/**
* This function will initialize hardware interrupt
@@ -82,21 +82,21 @@ void rt_hw_interrupt_handler(int vector)
void rt_hw_interrupt_init()
{
rt_base_t index;
rt_uint32_t *vect_addr, *vect_ctl;
/* initialize VIC*/
VICIntEnClr = 0xffffffff;
VICVectAddr = 0;
/* set all to IRQ */
VICIntSelect = 0;
rt_uint32_t *vect_addr, *vect_ctl;
/* initialize VIC*/
VICIntEnClr = 0xffffffff;
VICVectAddr = 0;
/* set all to IRQ */
VICIntSelect = 0;
for (index = 0; index < MAX_HANDLERS; index ++)
{
vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2));
vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2));
*vect_addr = (rt_uint32_t)rt_hw_interrupt_handler;
*vect_ctl = 0xF;
vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2));
vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2));
*vect_addr = (rt_uint32_t)rt_hw_interrupt_handler;
*vect_ctl = 0xF;
}
/* init interrupt nest, and context in thread sp */
@@ -104,26 +104,26 @@ void rt_hw_interrupt_init()
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
VICIntEnClr = (1 << vector);
}
{
VICIntEnClr = (1 << vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
{
VICIntEnable = (1 << vector);
}
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
@@ -131,21 +131,21 @@ void rt_hw_interrupt_umask(int vector)
* @param old_handler the old interrupt service routine
*/
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
{
{
if(vector >= 0 && vector < MAX_HANDLERS)
{
/* get VIC address */
rt_uint32_t* vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (vector << 2));
rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2));
/* assign IRQ slot and enable this slot */
*vect_ctl = 0x20 | (vector & 0x1F);
/* get VIC address */
rt_uint32_t* vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (vector << 2));
rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2));
/* assign IRQ slot and enable this slot */
*vect_ctl = 0x20 | (vector & 0x1F);
if (old_handler != RT_NULL) *old_handler = (rt_isr_handler_t) *vect_addr;
if (new_handler != RT_NULL) *vect_addr = (rt_uint32_t) new_handler;
}
}
}
/**
* this function will reset CPU
*
@@ -163,22 +163,22 @@ void rt_hw_cpu_shutdown()
rt_kprintf("shutdown...\n");
while (1);
}
}
void rt_hw_trap_irq()
{
rt_isr_handler_t isr_func;
isr_func = (rt_isr_handler_t) VICVectAddr;
isr_func(0);
/* acknowledge Interrupt */
// VICVectAddr = 0;
{
rt_isr_handler_t isr_func;
isr_func = (rt_isr_handler_t) VICVectAddr;
isr_func(0);
/* acknowledge Interrupt */
// VICVectAddr = 0;
}
void rt_hw_trap_fiq()
{
rt_kprintf("fast interrupt request\n");
}
/*@}*/
libcpu/arm/lpc214x/lpc214x.h
+393 -393
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/lpc214x/start_rvds.S
+464 -464
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/lpc214x/startup_gcc.S
+312 -312
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/lpc24xx/LPC24xx.h
+1201 -1201
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/lpc24xx/context_rvds.S
+24 -24
View File
@@ -13,12 +13,12 @@
; * 2011-07-22 Bernard added thumb mode porting
; */
NOINT EQU 0xc0 ; disable interrupt in psr
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
@@ -27,16 +27,16 @@ rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
MSR cpsr_c, r1
BX lr
ENDP
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
MSR cpsr_c, r0
BX lr
ENDP
@@ -50,24 +50,24 @@ rt_hw_context_switch PROC
STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
STMFD sp!, {r0-r12, lr} ; push lr & register file
MRS r4, cpsr
TST lr, #0x01
BEQ _ARM_MODE
ORR r4, r4, #0x20 ; it's thumb code
_ARM_MODE
MRS r4, cpsr
TST lr, #0x01
BEQ _ARM_MODE
ORR r4, r4, #0x20 ; it's thumb code
_ARM_MODE
STMFD sp!, {r4} ; push cpsr
STR sp, [r0] ; store sp in preempted tasks TCB
LDR sp, [r1] ; get new task stack pointer
LDMFD sp!, {r4} ; pop new task cpsr to spsr
MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task cpsr to spsr
MSR spsr_cxsf, r4
BIC r4, r4, #0x20 ; must be ARM mode
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
ENDP
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
@@ -77,20 +77,20 @@ rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to
LDR sp, [r0] ; get new task stack pointer
LDMFD sp!, {r4} ; pop new task cpsr to spsr
MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task cpsr to spsr
MSR spsr_cxsf, r4
BIC r4, r4, #0x20 ; must be ARM mode
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
ENDP
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
@@ -104,8 +104,8 @@ rt_hw_context_switch_interrupt PROC
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
STR r1, [r2]
BX lr
ENDP
ENDP
END
libcpu/arm/lpc24xx/stack.c
+8 -8
View File
@@ -12,7 +12,7 @@
* 2008-12-11 XuXinming first version
*/
#include <rtthread.h>
#include "LPC24xx.h"
#include "LPC24xx.h"
/**
* @addtogroup LPC2478
@@ -49,13 +49,13 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (unsigned long)parameter; /* r0 : argument */
/* cpsr */
if ((rt_uint32_t)tentry & 0x01)
*(--stk) = SVCMODE | 0x20; /* thumb mode */
else
*(--stk) = SVCMODE; /* arm mode */
*(--stk) = (unsigned long)parameter; /* r0 : argument */
/* cpsr */
if ((rt_uint32_t)tentry & 0x01)
*(--stk) = SVCMODE | 0x20; /* thumb mode */
else
*(--stk) = SVCMODE; /* arm mode */
/* return task's current stack address */
return (rt_uint8_t *)stk;
libcpu/arm/lpc24xx/start_rvds.S
+1632 -1632
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/s3c24x0/context_rvds.S
+14 -14
View File
@@ -12,12 +12,12 @@
; * 2009-01-20 Bernard first version
; */
NOINT EQU 0xc0 ; disable interrupt in psr
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
@@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
MSR cpsr_c, r1
BX lr
ENDP
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
MSR cpsr_c, r0
BX lr
ENDP
@@ -63,7 +63,7 @@ rt_hw_context_switch PROC
MSR spsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
@@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
@@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
STR r1, [r2]
BX lr
ENDP
ENDP
END
libcpu/arm/s3c24x0/cpu.c
+190 -190
View File
@@ -1,190 +1,190 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "s3c24x0.h"
/**
* @addtogroup S3C24X0
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
/* Disable all interrupt except the WDT */
INTMSK = (~((rt_uint32_t)1 << INTWDT));
/* Disable watchdog */
WTCON = 0x0000;
/* Initialize watchdog timer count register */
WTCNT = 0x0001;
/* Enable watchdog timer; assert reset at timer timeout */
WTCON = 0x0021;
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/**
* shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
while (level)
{
RT_ASSERT(0);
}
}
/*@}*/
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "s3c24x0.h"
/**
* @addtogroup S3C24X0
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
/* Disable all interrupt except the WDT */
INTMSK = (~((rt_uint32_t)1 << INTWDT));
/* Disable watchdog */
WTCON = 0x0000;
/* Initialize watchdog timer count register */
WTCNT = 0x0001;
/* Enable watchdog timer; assert reset at timer timeout */
WTCON = 0x0021;
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/**
* shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
while (level)
{
RT_ASSERT(0);
}
}
/*@}*/
libcpu/arm/s3c24x0/mmu.c
+394 -394
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/s3c24x0/rtc.c
+189 -189
View File
@@ -1,189 +1,189 @@
/*
* File : rtc.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-04-26 yi.qiu first version
* 2010-03-18 Gary Lee add functions such as GregorianDay
* and rtc_time_to_tm
* 2009-03-20 yi.qiu clean up
*/
#include <rtthread.h>
#include <time.h>
#include <s3c24x0.h>
// #define RTC_DEBUG
#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */
#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */
#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F))
#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10))
/**
* This function get rtc time
*/
void rt_hw_rtc_get(struct tm *ti)
{
rt_uint8_t sec, min, hour, mday, wday, mon, year;
/* enable access to RTC registers */
RTCCON |= RTC_ENABLE;
/* read RTC registers */
do
{
sec = BCDSEC;
min = BCDMIN;
hour = BCDHOUR;
mday = BCDDATE;
wday = BCDDAY;
mon = BCDMON;
year = BCDYEAR;
} while (sec != BCDSEC);
#ifdef RTC_DEBUG
rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n",
sec, min, hour, mday, wday, mon, year);
#endif
/* disable access to RTC registers */
RTC_DISABLE
ti->tm_sec = BCD2BIN(sec & 0x7F);
ti->tm_min = BCD2BIN(min & 0x7F);
ti->tm_hour = BCD2BIN(hour & 0x3F);
ti->tm_mday = BCD2BIN(mday & 0x3F);
ti->tm_mon = BCD2BIN(mon & 0x1F);
ti->tm_year = BCD2BIN(year);
ti->tm_wday = BCD2BIN(wday & 0x07);
ti->tm_yday = 0;
ti->tm_isdst = 0;
}
/**
* This function set rtc time
*/
void rt_hw_rtc_set(struct tm *ti)
{
rt_uint8_t sec, min, hour, mday, wday, mon, year;
year = BIN2BCD(ti->tm_year);
mon = BIN2BCD(ti->tm_mon);
wday = BIN2BCD(ti->tm_wday);
mday = BIN2BCD(ti->tm_mday);
hour = BIN2BCD(ti->tm_hour);
min = BIN2BCD(ti->tm_min);
sec = BIN2BCD(ti->tm_sec);
/* enable access to RTC registers */
RTC_ENABLE
do{
/* write RTC registers */
BCDSEC = sec;
BCDMIN = min;
BCDHOUR = hour;
BCDDATE = mday;
BCDDAY = wday;
BCDMON = mon;
BCDYEAR = year;
}while (sec != BCDSEC);
/* disable access to RTC registers */
RTC_DISABLE
}
/**
* This function reset rtc
*/
void rt_hw_rtc_reset (void)
{
RTCCON = (RTCCON & ~0x06) | 0x08;
RTCCON &= ~(0x08|0x01);
}
static struct rt_device rtc;
static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
RTC_ENABLE
return RT_EOK;
}
static rt_err_t rtc_close(rt_device_t dev)
{
RTC_DISABLE
return RT_EOK;
}
static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
return RT_EOK;
}
static rt_err_t rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
struct tm tm, *tm_ptr;
time_t *time;
RT_ASSERT(dev != RT_NULL);
time = (time_t *)args;
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
/* read device */
rt_hw_rtc_get(&tm);
*((rt_time_t *)args) = mktime(&tm);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
tm_ptr = localtime(time);
/* write device */
rt_hw_rtc_set(tm_ptr);
break;
}
return RT_EOK;
}
void rt_hw_rtc_init(void)
{
rtc.type = RT_Device_Class_RTC;
/* register rtc device */
rtc.init = RT_NULL;
rtc.open = rtc_open;
rtc.close = rtc_close;
rtc.read = rtc_read;
rtc.write = RT_NULL;
rtc.control = rtc_control;
/* no private */
rtc.user_data = RT_NULL;
rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
}
#ifdef RT_USING_FINSH
#include <finsh.h>
void list_date()
{
time_t time;
rt_device_t device;
device = rt_device_find("rtc");
if (device != RT_NULL)
{
rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time);
rt_kprintf("%d, %s\n", time, ctime(&time));
}
}
FINSH_FUNCTION_EXPORT(list_date, list date);
#endif
/*
* File : rtc.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-04-26 yi.qiu first version
* 2010-03-18 Gary Lee add functions such as GregorianDay
* and rtc_time_to_tm
* 2009-03-20 yi.qiu clean up
*/
#include <rtthread.h>
#include <time.h>
#include <s3c24x0.h>
// #define RTC_DEBUG
#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */
#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */
#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F))
#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10))
/**
* This function get rtc time
*/
void rt_hw_rtc_get(struct tm *ti)
{
rt_uint8_t sec, min, hour, mday, wday, mon, year;
/* enable access to RTC registers */
RTCCON |= RTC_ENABLE;
/* read RTC registers */
do
{
sec = BCDSEC;
min = BCDMIN;
hour = BCDHOUR;
mday = BCDDATE;
wday = BCDDAY;
mon = BCDMON;
year = BCDYEAR;
} while (sec != BCDSEC);
#ifdef RTC_DEBUG
rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n",
sec, min, hour, mday, wday, mon, year);
#endif
/* disable access to RTC registers */
RTC_DISABLE
ti->tm_sec = BCD2BIN(sec & 0x7F);
ti->tm_min = BCD2BIN(min & 0x7F);
ti->tm_hour = BCD2BIN(hour & 0x3F);
ti->tm_mday = BCD2BIN(mday & 0x3F);
ti->tm_mon = BCD2BIN(mon & 0x1F);
ti->tm_year = BCD2BIN(year);
ti->tm_wday = BCD2BIN(wday & 0x07);
ti->tm_yday = 0;
ti->tm_isdst = 0;
}
/**
* This function set rtc time
*/
void rt_hw_rtc_set(struct tm *ti)
{
rt_uint8_t sec, min, hour, mday, wday, mon, year;
year = BIN2BCD(ti->tm_year);
mon = BIN2BCD(ti->tm_mon);
wday = BIN2BCD(ti->tm_wday);
mday = BIN2BCD(ti->tm_mday);
hour = BIN2BCD(ti->tm_hour);
min = BIN2BCD(ti->tm_min);
sec = BIN2BCD(ti->tm_sec);
/* enable access to RTC registers */
RTC_ENABLE
do{
/* write RTC registers */
BCDSEC = sec;
BCDMIN = min;
BCDHOUR = hour;
BCDDATE = mday;
BCDDAY = wday;
BCDMON = mon;
BCDYEAR = year;
}while (sec != BCDSEC);
/* disable access to RTC registers */
RTC_DISABLE
}
/**
* This function reset rtc
*/
void rt_hw_rtc_reset (void)
{
RTCCON = (RTCCON & ~0x06) | 0x08;
RTCCON &= ~(0x08|0x01);
}
static struct rt_device rtc;
static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
RTC_ENABLE
return RT_EOK;
}
static rt_err_t rtc_close(rt_device_t dev)
{
RTC_DISABLE
return RT_EOK;
}
static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
return RT_EOK;
}
static rt_err_t rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
struct tm tm, *tm_ptr;
time_t *time;
RT_ASSERT(dev != RT_NULL);
time = (time_t *)args;
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
/* read device */
rt_hw_rtc_get(&tm);
*((rt_time_t *)args) = mktime(&tm);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
tm_ptr = localtime(time);
/* write device */
rt_hw_rtc_set(tm_ptr);
break;
}
return RT_EOK;
}
void rt_hw_rtc_init(void)
{
rtc.type = RT_Device_Class_RTC;
/* register rtc device */
rtc.init = RT_NULL;
rtc.open = rtc_open;
rtc.close = rtc_close;
rtc.read = rtc_read;
rtc.write = RT_NULL;
rtc.control = rtc_control;
/* no private */
rtc.user_data = RT_NULL;
rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
}
#ifdef RT_USING_FINSH
#include <finsh.h>
void list_date()
{
time_t time;
rt_device_t device;
device = rt_device_find("rtc");
if (device != RT_NULL)
{
rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time);
rt_kprintf("%d, %s\n", time, ctime(&time));
}
}
FINSH_FUNCTION_EXPORT(list_date, list date);
#endif
libcpu/arm/s3c24x0/rtc.h
+21 -21
View File
@@ -1,21 +1,21 @@
/*
* File : rtc.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-03-20 yi.qiu the first version
*/
#ifndef __RTC_H__
#define __RTC_H__
void rt_hw_rtc_init(void);
#endif
/*
* File : rtc.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-03-20 yi.qiu the first version
*/
#ifndef __RTC_H__
#define __RTC_H__
void rt_hw_rtc_init(void);
#endif
libcpu/arm/s3c24x0/s3c24x0.h
+611 -611
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/s3c24x0/serial.h
+58 -58
View File
@@ -1,58 +1,58 @@
#ifndef __RT_HW_SERIAL_H__
#define __RT_HW_SERIAL_H__
#include <rthw.h>
#include <rtthread.h>
#include "s3c24x0.h"
#define USTAT_RCV_READY 0x01 /* receive data ready */
#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */
#define BPS 115200 /* serial baudrate */
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_BUFFER_SIZE 64
struct serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct serial_int_tx
{
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
rt_uint32_t write_index, save_index;
};
typedef struct uartport
{
volatile rt_uint32_t ulcon;
volatile rt_uint32_t ucon;
volatile rt_uint32_t ufcon;
volatile rt_uint32_t umcon;
volatile rt_uint32_t ustat;
volatile rt_uint32_t urxb;
volatile rt_uint32_t ufstat;
volatile rt_uint32_t umstat;
volatile rt_uint32_t utxh;
volatile rt_uint32_t urxh;
volatile rt_uint32_t ubrd;
}uartport;
struct serial_device
{
uartport* uart_device;
/* rx structure */
struct serial_int_rx* int_rx;
/* tx structure */
struct serial_int_tx* int_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
#endif
#ifndef __RT_HW_SERIAL_H__
#define __RT_HW_SERIAL_H__
#include <rthw.h>
#include <rtthread.h>
#include "s3c24x0.h"
#define USTAT_RCV_READY 0x01 /* receive data ready */
#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */
#define BPS 115200 /* serial baudrate */
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_BUFFER_SIZE 64
struct serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct serial_int_tx
{
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
rt_uint32_t write_index, save_index;
};
typedef struct uartport
{
volatile rt_uint32_t ulcon;
volatile rt_uint32_t ucon;
volatile rt_uint32_t ufcon;
volatile rt_uint32_t umcon;
volatile rt_uint32_t ustat;
volatile rt_uint32_t urxb;
volatile rt_uint32_t ufstat;
volatile rt_uint32_t umstat;
volatile rt_uint32_t utxh;
volatile rt_uint32_t urxh;
volatile rt_uint32_t ubrd;
}uartport;
struct serial_device
{
uartport* uart_device;
/* rx structure */
struct serial_int_rx* int_rx;
/* tx structure */
struct serial_int_tx* int_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
#endif
libcpu/arm/s3c24x0/start_rvds.S
+1190 -1190
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/s3c24x0/system_clock.c
+108 -108
View File
@@ -1,108 +1,108 @@
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-04-25 Yi.qiu first version
*/
#include <rtthread.h>
#include "s3c24x0.h"
#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
#if CONFIG_SYS_CLK_FREQ == 12000000
/* MPLL=2*12*100/6=400MHz */
#define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
#define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
#define MPL_SDIV 0 /* s=MPL_SDIV=0 */
/* UPLL=12*64/8=96MHz */
#define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
#define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
#define UPL_SDIV 1 /* s=UPL_SDIV=1 */
/* System clock divider FCLK:HCLK:PCLK=1:4:8 */
#define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
#define HDIVN 0x2 /* HCLK = FCLK / 4 */
#define PDIVN 0x1 /* PCLK = HCLK / 2 */
#endif
rt_uint32_t PCLK;
rt_uint32_t FCLK;
rt_uint32_t HCLK;
rt_uint32_t UCLK;
void rt_hw_get_clock(void)
{
rt_uint32_t val;
rt_uint8_t m, p, s;
val = MPLLCON;
m = (val>>12)&0xff;
p = (val>>4)&0x3f;
s = val&3;
FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
val = CLKDIVN;
m = (val>>1)&3;
p = val&1;
switch (m) {
case 0:
HCLK = FCLK;
break;
case 1:
HCLK = FCLK>>1;
break;
case 2:
if(s&2)
HCLK = FCLK>>3;
else
HCLK = FCLK>>2;
break;
case 3:
if(s&1)
HCLK = FCLK/6;
else
HCLK = FCLK/3;
break;
}
if(p)
PCLK = HCLK>>1;
else
PCLK = HCLK;
}
void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
}
void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}
void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
{
CLKDIVN = (hdivn<<1) | pdivn;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
LOCKTIME = 0xFFFFFFFF;
rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
rt_hw_set_divider(HDIVN, PDIVN);
}
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-04-25 Yi.qiu first version
*/
#include <rtthread.h>
#include "s3c24x0.h"
#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
#if CONFIG_SYS_CLK_FREQ == 12000000
/* MPLL=2*12*100/6=400MHz */
#define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
#define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
#define MPL_SDIV 0 /* s=MPL_SDIV=0 */
/* UPLL=12*64/8=96MHz */
#define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
#define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
#define UPL_SDIV 1 /* s=UPL_SDIV=1 */
/* System clock divider FCLK:HCLK:PCLK=1:4:8 */
#define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
#define HDIVN 0x2 /* HCLK = FCLK / 4 */
#define PDIVN 0x1 /* PCLK = HCLK / 2 */
#endif
rt_uint32_t PCLK;
rt_uint32_t FCLK;
rt_uint32_t HCLK;
rt_uint32_t UCLK;
void rt_hw_get_clock(void)
{
rt_uint32_t val;
rt_uint8_t m, p, s;
val = MPLLCON;
m = (val>>12)&0xff;
p = (val>>4)&0x3f;
s = val&3;
FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
val = CLKDIVN;
m = (val>>1)&3;
p = val&1;
switch (m) {
case 0:
HCLK = FCLK;
break;
case 1:
HCLK = FCLK>>1;
break;
case 2:
if(s&2)
HCLK = FCLK>>3;
else
HCLK = FCLK>>2;
break;
case 3:
if(s&1)
HCLK = FCLK/6;
else
HCLK = FCLK/3;
break;
}
if(p)
PCLK = HCLK>>1;
else
PCLK = HCLK;
}
void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
}
void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}
void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
{
CLKDIVN = (hdivn<<1) | pdivn;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
LOCKTIME = 0xFFFFFFFF;
rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
rt_hw_set_divider(HDIVN, PDIVN);
}
libcpu/arm/s3c24x0/trap.c
+1 -1
View File
@@ -157,7 +157,7 @@ void rt_hw_trap_irq()
/* turn to interrupt service routine */
isr_func(intstat);
/* clear pending register */
/* clear pending register */
/* note: must be the last, if not, may repeat*/
ClearPending(1 << intstat);
}
libcpu/arm/s3c44b0/context_rvds.S
+14 -14
View File
@@ -12,12 +12,12 @@
; * 2009-01-20 Bernard first version
; */
NOINT EQU 0xc0 ; disable interrupt in psr
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
@@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
MSR cpsr_c, r1
BX lr
ENDP
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
MSR cpsr_c, r0
BX lr
ENDP
@@ -63,7 +63,7 @@ rt_hw_context_switch PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
@@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
@@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
STR r1, [r2]
BX lr
ENDP
ENDP
END
libcpu/arm/s3c44b0/s3c44b0.h
+21 -21
View File
@@ -213,27 +213,27 @@ extern "C" {
#define F_ISPR (S3C_REG(0x1e00038))
#define F_ISPC (S3C_REG(0x1e0003c))
/********************************/
/* LCD Controller Registers */
/********************************/
#define LCDCON1 (S3C_REG(0x300000))
#define LCDCON2 (S3C_REG(0x300004))
#define LCDSADDR1 (S3C_REG(0x300008))
#define LCDSADDR2 (S3C_REG(0x30000c))
#define LCDSADDR3 (S3C_REG(0x300010))
#define REDLUT (S3C_REG(0x300014))
#define GREENLUT (S3C_REG(0x300018))
#define BLUELUT (S3C_REG(0x30001c))
#define DP1_2 (S3C_REG(0x300020))
#define DP4_7 (S3C_REG(0x300024))
#define DP3_5 (S3C_REG(0x300028))
#define DP2_3 (S3C_REG(0x30002c))
#define DP5_7 (S3C_REG(0x300030))
#define DP3_4 (S3C_REG(0x300034))
#define DP4_5 (S3C_REG(0x300038))
#define DP6_7 (S3C_REG(0x30003c))
#define LCDCON3 (S3C_REG(0x300040))
#define DITHMODE (S3C_REG(0x300044))
/********************************/
/* LCD Controller Registers */
/********************************/
#define LCDCON1 (S3C_REG(0x300000))
#define LCDCON2 (S3C_REG(0x300004))
#define LCDSADDR1 (S3C_REG(0x300008))
#define LCDSADDR2 (S3C_REG(0x30000c))
#define LCDSADDR3 (S3C_REG(0x300010))
#define REDLUT (S3C_REG(0x300014))
#define GREENLUT (S3C_REG(0x300018))
#define BLUELUT (S3C_REG(0x30001c))
#define DP1_2 (S3C_REG(0x300020))
#define DP4_7 (S3C_REG(0x300024))
#define DP3_5 (S3C_REG(0x300028))
#define DP2_3 (S3C_REG(0x30002c))
#define DP5_7 (S3C_REG(0x300030))
#define DP3_4 (S3C_REG(0x300034))
#define DP4_5 (S3C_REG(0x300038))
#define DP6_7 (S3C_REG(0x30003c))
#define LCDCON3 (S3C_REG(0x300040))
#define DITHMODE (S3C_REG(0x300044))
/* ZDMA0 */
#define ZDCON0 (S3C_REG(0x1e80000))
libcpu/arm/s3c44b0/start_gcc.S
+13 -13
View File
@@ -238,20 +238,20 @@ stack_setup:
.globl led_on
led_on:
ldr r1, =0x1d20014 @ r1<-PDATC
ldr r0, [r1] @ r0<-[r1]
orr r0, r0, #0x0e @ r0=r0 or 0x0e
str r0, [r1] @ r0->[r1]
ldr r1, =0x1d20014 @ r1<-PDATC
ldr r0, [r1] @ r0<-[r1]
orr r0, r0, #0x0e @ r0=r0 or 0x0e
str r0, [r1] @ r0->[r1]
mov pc, lr
.globl led_off
led_off:
ldr r1, =0x1d20010 @ r1<-PCONC
ldr r0, =0x5f555555 @ r0<-0x5f555555
str r0, [r1] @ r0->[r1]
ldr r1, =0x1d20014 @ r1<-PDATC
ldr r0, =0x0 @ r0<-00
str r0, [r1] @ r0->[r1]
mov pc, lr
ldr r1, =0x1d20010 @ r1<-PCONC
ldr r0, =0x5f555555 @ r0<-0x5f555555
str r0, [r1] @ r0->[r1]
ldr r1, =0x1d20014 @ r1<-PDATC
ldr r0, =0x0 @ r0<-00
str r0, [r1] @ r0->[r1]
mov pc, lr
libcpu/arm/s3c44b0/start_rvds.S
+1072 -1072
View File
File diff suppressed because it is too large Load Diff
libcpu/arm/sep4020/clk.c
+112 -112
View File
@@ -1,112 +1,112 @@
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-03-20 zchong first version
*/
#include <rtthread.h>
#include "sep4020.h"
#define CLK_IN 4000000 /* Fin = 4.00MHz */
#define SYSCLK 72000000 /* system clock we want */
#define CLK_ESRAM 0
#define CLK_LCDC 1
#define CLK_PWM 2
#define CLK_DMAC 3
#define CLK_EMI 4
#define CLK_MMCSD 5
#define CLK_SSI 7
#define CLK_UART0 8
#define CLK_UART1 9
#define CLK_UART2 10
#define CLK_UART3 11
#define CLK_USB 12
#define CLK_MAC 13
#define CLK_SMC 14
#define CLK_I2C 15
#define CLK_GPT 16
static void rt_hw_set_system_clock(void)
{
rt_uint8_t pv;
/* pv value*/
pv = SYSCLK/2/CLK_IN;
/* go to normal mode*/
*(RP)PMU_PMDR = 0x01;
/* set the clock */
*(RP)PMU_PMCR = 0x4000 | pv;
/* trige configurate*/
*(RP)PMU_PMCR = 0xc000 | pv;
}
static void rt_hw_set_usb_clock(void)
{
/* set the clock */
*(RP)PMU_PUCR = 0x000c;
/* trige configurate*/
*(RP)PMU_PMCR = 0x800c;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
/* set system clock */
rt_hw_set_system_clock();
/* set usb clock */
rt_hw_set_usb_clock();
}
/**
* @brief Get system clock
*/
rt_uint32_t rt_hw_get_clock(void)
{
rt_uint32_t val;
rt_uint8_t pv, pd, npd;
/* get PMCR value */
val =*(RP) PMU_PMCR;
/* get NPD */
npd = (val >> 14) & 0x01;
/* get PD */
pd = (val >> 10) & 0x0f;
/* get PV */
pv = val & 0x7f;
/* caculate the system clock */
if(npd)
val = 2 * CLK_IN * pv;
else
val = CLK_IN * pv / (pd + 1);
return(val);
}
/**
* @brief Enable module clock
*/
void rt_hw_enable_module_clock(rt_uint8_t module)
{
}
/**
* @brief Disable module clock
*/
void rt_hw_disable_module_clock(rt_uint8_t module)
{
}
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-03-20 zchong first version
*/
#include <rtthread.h>
#include "sep4020.h"
#define CLK_IN 4000000 /* Fin = 4.00MHz */
#define SYSCLK 72000000 /* system clock we want */
#define CLK_ESRAM 0
#define CLK_LCDC 1
#define CLK_PWM 2
#define CLK_DMAC 3
#define CLK_EMI 4
#define CLK_MMCSD 5
#define CLK_SSI 7
#define CLK_UART0 8
#define CLK_UART1 9
#define CLK_UART2 10
#define CLK_UART3 11
#define CLK_USB 12
#define CLK_MAC 13
#define CLK_SMC 14
#define CLK_I2C 15
#define CLK_GPT 16
static void rt_hw_set_system_clock(void)
{
rt_uint8_t pv;
/* pv value*/
pv = SYSCLK/2/CLK_IN;
/* go to normal mode*/
*(RP)PMU_PMDR = 0x01;
/* set the clock */
*(RP)PMU_PMCR = 0x4000 | pv;
/* trige configurate*/
*(RP)PMU_PMCR = 0xc000 | pv;
}
static void rt_hw_set_usb_clock(void)
{
/* set the clock */
*(RP)PMU_PUCR = 0x000c;
/* trige configurate*/
*(RP)PMU_PMCR = 0x800c;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
/* set system clock */
rt_hw_set_system_clock();
/* set usb clock */
rt_hw_set_usb_clock();
}
/**
* @brief Get system clock
*/
rt_uint32_t rt_hw_get_clock(void)
{
rt_uint32_t val;
rt_uint8_t pv, pd, npd;
/* get PMCR value */
val =*(RP) PMU_PMCR;
/* get NPD */
npd = (val >> 14) & 0x01;
/* get PD */
pd = (val >> 10) & 0x0f;
/* get PV */
pv = val & 0x7f;
/* caculate the system clock */
if(npd)
val = 2 * CLK_IN * pv;
else
val = CLK_IN * pv / (pd + 1);
return(val);
}
/**
* @brief Enable module clock
*/
void rt_hw_enable_module_clock(rt_uint8_t module)
{
}
/**
* @brief Disable module clock
*/
void rt_hw_disable_module_clock(rt_uint8_t module)
{
}
libcpu/arm/sep4020/context_rvds.S
+14 -14
View File
@@ -12,12 +12,12 @@
; * 2009-01-20 Bernard first version
; */
NOINT EQU 0xc0 ; disable interrupt in psr
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
@@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
MRS r0, cpsr
ORR r1, r0, #NOINT
MSR cpsr_c, r1
MSR cpsr_c, r1
BX lr
ENDP
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
MSR cpsr_c, r0
MSR cpsr_c, r0
BX lr
ENDP
@@ -63,7 +63,7 @@ rt_hw_context_switch PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
@@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC
MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
ENDP
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT rt_thread_switch_interrupt_flag
IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread
IMPORT rt_interrupt_to_thread
rt_hw_context_switch_interrupt PROC
EXPORT rt_hw_context_switch_interrupt
@@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC
STR r0, [r2]
_reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2]
STR r1, [r2]
BX lr
ENDP
ENDP
END
libcpu/arm/sep4020/cpu.c
+190 -190
View File
@@ -1,190 +1,190 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
*/
#include <rtthread.h>
#include <sep4020.h>
extern rt_uint32_t rt_hw_interrupt_disable(void);
//TODO
#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
/**
* @addtogroup S3C24X0
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
/* enable watchdog */
*(RP)(RTC_CTR) = 0x02;
/*Enable watchdog reset*/
*(RP)(RTC_INT_EN) = 0x20;
/* Initialize watchdog timer count register */
*(RP)(RTC_WD_CNT) = 0x0001;
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/**
* shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_uint32_t UNUSED level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
RT_ASSERT(RT_NULL);
}
/*@}*/
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
*/
#include <rtthread.h>
#include <sep4020.h>
extern rt_uint32_t rt_hw_interrupt_disable(void);
//TODO
#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
/**
* @addtogroup S3C24X0
*/
/*@{*/
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
#ifdef __GNUC__
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
#ifdef __CC_ARM
rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
__asm
{
mrc p15, 0, i, c1, c0, 0
}
return i;
}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
}
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
/* enable watchdog */
*(RP)(RTC_CTR) = 0x02;
/*Enable watchdog reset*/
*(RP)(RTC_INT_EN) = 0x20;
/* Initialize watchdog timer count register */
*(RP)(RTC_WD_CNT) = 0x0001;
while(1); /* loop forever and wait for reset to happen */
/* NEVER REACHED */
}
/**
* shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_uint32_t UNUSED level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
RT_ASSERT(RT_NULL);
}
/*@}*/
libcpu/arm/sep4020/interrupt.c
+34 -34
View File
@@ -40,30 +40,30 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
*/
void rt_hw_interrupt_init()
{
register rt_uint32_t idx;
/*Make sure all intc registers in proper state*/
/*mask all the irq*/
*(RP)(INTC_IMR) = 0xFFFFFFFF;
/*enable all the irq*/
*(RP)(INTC_IER) = 0XFFFFFFFF;
/*Dont use any forced irq*/
*(RP)(INTC_IFR) = 0x0;
/*Disable all the fiq*/
*(RP)(INTC_FIER) = 0x0;
/*Mask all the fiq*/
*(RP)(INTC_FIMR) = 0x0F;
/*Dont use forced fiq*/
*(RP)(INTC_FIFR) = 0x0;
/*Intrrupt priority register*/
*(RP)(INTC_IPLR) = 0x0;
register rt_uint32_t idx;
/*Make sure all intc registers in proper state*/
/*mask all the irq*/
*(RP)(INTC_IMR) = 0xFFFFFFFF;
/*enable all the irq*/
*(RP)(INTC_IER) = 0XFFFFFFFF;
/*Dont use any forced irq*/
*(RP)(INTC_IFR) = 0x0;
/*Disable all the fiq*/
*(RP)(INTC_FIER) = 0x0;
/*Mask all the fiq*/
*(RP)(INTC_FIMR) = 0x0F;
/*Dont use forced fiq*/
*(RP)(INTC_FIFR) = 0x0;
/*Intrrupt priority register*/
*(RP)(INTC_IPLR) = 0x0;
/* init exceptions table */
for(idx=0; idx < MAX_HANDLERS; idx++)
@@ -92,15 +92,15 @@ void rt_hw_interrupt_mask(rt_uint32_t vector)
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(rt_uint32_t vector)
{
if(vector == 16)
{
rt_kprintf("Interrupt vec %d is not used!\n", vector);
}
else
{
if(vector == 16)
{
rt_kprintf("Interrupt vec %d is not used!\n", vector);
}
else
*(RP)(INTC_IMR) &= ~(1 << vector);
}
}
/**
* This function will install a interrupt service routine to a interrupt.
@@ -112,9 +112,9 @@ void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, r
{
if(vector < MAX_HANDLERS)
{
if (*old_handler != RT_NULL)
if (*old_handler != RT_NULL)
*old_handler = isr_table[vector];
if (new_handler != RT_NULL)
if (new_handler != RT_NULL)
isr_table[vector] = new_handler;
}
}
libcpu/arm/sep4020/sep4020.h
+867 -867
View File
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