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modify mini2440/board.c serial device

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modify s3c24x0/clock.c clock initialization

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@225 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
gouqingsong@gmail.com
2009-12-25 10:38:56 +00:00
parent ffd0eecb28
commit 6cd35a87c3
2 changed files with 49 additions and 46 deletions
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libcpu/arm/s3c24x0/clock.c
+34 -3
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@@ -17,6 +17,21 @@
#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
#if CONFIG_SYS_CLK_FREQ == 12000000
/* MPLL=2*12*100/6=400MHz */
#define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
#define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
#define MPL_SDIV 0 /* s=MPL_SDIV=0 */
/* UPLL=12*64/8=96MHz */
#define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
#define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
#define UPL_SDIV 1 /* s=UPL_SDIV=1 */
/* System clock divider FCLK:HCLK:PCLK=1:4:8 */
#define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
#define HDIVN 0x2 /* HCLK = FCLK / 4 */
#define PDIVN 0x1 /* PCLK = HCLK / 2 */
#endif
rt_uint32_t PCLK;
rt_uint32_t FCLK;
rt_uint32_t HCLK;
@@ -65,13 +80,29 @@ void rt_hw_get_clock(void)
PCLK = HCLK;
}
void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
MPLLCON = sdiv | pdiv<<4 | mdiv<<12;
MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
}
void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn)
void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
{
UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
}
void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
{
CLKDIVN = (hdivn<<1) | pdivn;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
LOCKTIME = 0xFFFFFFFF;
rt_hw_set_divider(HDIVN, PDIVN);
rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
}