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1. [bsp][sam9260] Fix the bug that auto reset after boot 20s. Disable watchdog in rt_lovel_level_init function.

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2. [bsp][sam9260] Modify SCONS scripts to support IAR tool chain.
3. [bsp][sam9260] Move link strips in to folder link_scripts.
4. [libcpu][arm926] Add copy right to source file and format code.
This commit is contained in:
ardafu
2015-04-15 16:13:30 +08:00
parent f435a214d4
commit 6aa242645f
18 changed files with 662 additions and 253 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libcpu/arm/arm926/context_iar.S
+2 -1
View File
@@ -19,7 +19,8 @@
; *
; * Change Logs:
; * Date Author Notes
; * 2011-08-14 weety copy from mini2440
; * 2011-08-14 weety copy from mini2440
; * 2015-04-15 ArdaFu convert from context_gcc.s
; */
#define NOINT 0xc0
libcpu/arm/arm926/cpuport.c
+36 -35
View File
@@ -20,6 +20,7 @@
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
* 2015-04-15 ArdaFu Add code for IAR
*/
#include <rthw.h>
@@ -42,24 +43,24 @@ rt_inline rt_uint32_t cp15_rd(void)
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
__asm__ __volatile__(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
__asm__ __volatile__(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
@@ -112,24 +113,24 @@ rt_inline rt_uint32_t cp15_rd(void)
rt_inline void cache_enable(rt_uint32_t bit)
{
asm volatile( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
asm volatile( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
@@ -193,7 +194,7 @@ rt_base_t rt_hw_cpu_dcache_status()
*/
void rt_hw_cpu_reset()
{
rt_kprintf("Restarting system...\n");
machine_reset();
@@ -221,13 +222,13 @@ void rt_hw_cpu_shutdown()
#ifdef RT_USING_CPU_FFS
/**
* This function finds the first bit set (beginning with the least significant bit)
* This function finds the first bit set (beginning with the least significant bit)
* in value and return the index of that bit.
*
* Bits are numbered starting at 1 (the least significant bit). A return value of
* Bits are numbered starting at 1 (the least significant bit). A return value of
* zero from any of these functions means that the argument was zero.
*
* @return return the index of the first bit set. If value is 0, then this function
*
* @return return the index of the first bit set. If value is 0, then this function
* shall return 0.
*/
#if defined(__CC_ARM)
@@ -237,7 +238,7 @@ int __rt_ffs(int value)
if (value == 0)
return value;
__asm
{
rsb x, value, #0
@@ -248,7 +249,7 @@ int __rt_ffs(int value)
return x;
}
#elif defined(__IAR_SYSTEMS_ICC__)
#elif defined(__ICCARM__)
int __rt_ffs(int value)
{
if (value == 0)
libcpu/arm/arm926/mmu.c
+23 -21
View File
@@ -19,6 +19,7 @@
*
* Change Logs:
* Date Author Notes
* 2015-04-15 ArdaFu Add code for IAR
*/
#include "mmu.h"
@@ -28,11 +29,11 @@ void mmu_setttbase(rt_uint32_t i)
{
register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value = 0;
__asm
{
@@ -247,11 +248,11 @@ void mmu_setttbase(register rt_uint32_t i)
{
register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value = 0;
asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
@@ -433,11 +434,11 @@ void mmu_setttbase(register rt_uint32_t i)
{
register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value = 0;
asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
@@ -621,16 +622,18 @@ void mmu_invalidate_dcache_all()
#pragma data_alignment=(16*1024)
static volatile unsigned int _page_table[4*1024];;
#else
static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
static volatile unsigned int _page_table[4*1024] \
__attribute__((aligned(16*1024)));
#endif
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
rt_uint32_t paddrStart, rt_uint32_t attr)
{
volatile rt_uint32_t *pTT;
volatile int nSec;
int i = 0;
pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
for(i=0;i<=nSec;i++)
for(i=0; i<=nSec; i++)
{
*pTT = attr |(((paddrStart>>20)+i)<<20);
pTT++;
@@ -648,8 +651,8 @@ void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
/* set page table */
for (; size > 0; size--)
{
mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
mdesc->paddr_start, mdesc->attr);
mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
mdesc->paddr_start, mdesc->attr);
mdesc++;
}
@@ -668,4 +671,3 @@ void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
mmu_invalidate_icache();
mmu_invalidate_dcache_all();
}
libcpu/arm/arm926/mmu.h
+21 -21
View File
@@ -26,31 +26,32 @@
#include <rtthread.h>
#define CACHE_LINE_SIZE 32
#define CACHE_LINE_SIZE 32
#define DESC_SEC (0x2|(1<<4))
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
#define NCNB (0<<2) //cache_off,WR_BUF off
#define AP_RW (3<<10) //supervisor=RW, user=RW
#define AP_RO (2<<10) //supervisor=RW, user=RO
#define DESC_SEC (0x2|(1<<4))
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
#define NCNB (0<<2) //cache_off,WR_BUF off
#define AP_RW (3<<10) //supervisor=RW, user=RW
#define AP_RO (2<<10) //supervisor=RW, user=RO
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0<<5)
#define DOMAIN1 (0x1<<5)
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0<<5)
#define DOMAIN1 (0x1<<5)
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
struct mem_desc {
struct mem_desc
{
rt_uint32_t vaddr_start;
rt_uint32_t vaddr_end;
rt_uint32_t paddr_start;
@@ -60,4 +61,3 @@ struct mem_desc {
void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
#endif
libcpu/arm/arm926/stack.c
+25 -26
View File
@@ -27,49 +27,48 @@
/* CPU Mode */
/*****************************/
#define USERMODE 0x10
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define ABORTMODE 0x17
#define UNDEFMODE 0x1b
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define ABORTMODE 0x17
#define UNDEFMODE 0x1b
#define MODEMASK 0x1f
#define NOINT 0xc0
#define NOINT 0xc0
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
stk = (rt_uint32_t*)stack_addr;
*(stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0; /* r12 */
*(--stk) = 0; /* r11 */
*(--stk) = 0; /* r10 */
*(--stk) = 0; /* r9 */
*(--stk) = 0; /* r8 */
*(--stk) = 0; /* r7 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r4 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
*(--stk) = SVCMODE; /* cpsr */
*(--stk) = SVCMODE; /* spsr */
*(stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0; /* r12 */
*(--stk) = 0; /* r11 */
*(--stk) = 0; /* r10 */
*(--stk) = 0; /* r9 */
*(--stk) = 0; /* r8 */
*(--stk) = 0; /* r7 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r4 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
*(--stk) = SVCMODE; /* cpsr */
*(--stk) = SVCMODE; /* spsr */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
libcpu/arm/arm926/start_gcc.S
+7 -8
View File
@@ -1,7 +1,7 @@
/*
* File : start.S
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,8 +20,9 @@
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
* 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
*/
#define CONFIG_STACKSIZE 512
#define S_FRAME_SIZE (18*4) //72
@#define S_SPSR (17*4) //SPSR
@@ -55,7 +56,7 @@
.include "rt_low_level_gcc.inc"
@; stack table-----------------------------------------------------------------
@;----------------------- Stack and Heap Definitions ---------------------------
.section .nobss, "w"
.space UND_STK_SIZE
@@ -88,8 +89,7 @@ FIQ_STACK_START:
SYS_STACK_START:
@; Jump vector table-----------------------------------------------------------
@;--------------Jump vector table-----------------------------------------------
.section .init, "ax"
.arm
@@ -179,7 +179,6 @@ Setup_Stack:
MSR CPSR_cxsf, R1 @; SVC mode
LDR SP, =SVC_STACK_START
@; clear .bss
MOV R0, #0 @; get a zero
LDR R1, =__bss_start__ @; bss start
@@ -203,8 +202,8 @@ ctor_loop:
BX R2
LDMFD SP!, {R0-R1}
B ctor_loop
ctor_end:
@; Enter the C code
LDR R0, =main
BLX R0
libcpu/arm/arm926/start_iar.S
+2
View File
@@ -20,6 +20,7 @@
; * Change Logs:
; * Date Author Notes
; * 2011-01-13 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; */
#define S_FRAME_SIZE (18*4) ;72
@@ -55,6 +56,7 @@
#include "rt_low_level_iar.inc"
;----------------------- Stack and Heap Definitions ----------------------------
MODULE ?cstartup
SECTION .noinit:DATA:NOROOT(3)
DATA
libcpu/arm/arm926/start_rvds.S
+4 -12
View File
@@ -20,11 +20,9 @@
; * Change Logs:
; * Date Author Notes
; * 2011-08-14 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
S_FRAME_SIZE EQU (18*4) ;72
;S_SPSR EQU (17*4) ;SPSR
;S_CPSR EQU (16*4) ;CPSR
@@ -58,11 +56,9 @@ MODEMASK EQU 0X1F
NOINT EQU 0xC0
;----------------------- Stack and Heap Definitions ----------------------------
AREA STACK, NOINIT, READWRITE, ALIGN=3
GET rt_low_level_keil.inc
;-------------- stack area -----------------------------------------------------
;----------------------- Stack and Heap Definitions ----------------------------
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem
@@ -103,11 +99,7 @@ Heap_Mem
SPACE Heap_Size
__heap_limit
;----------------------- CODE --------------------------------------------------
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
;--------------Jump vector table------------------------------------------------
EXPORT Entry_Point
AREA RESET, CODE, READONLY
@@ -331,7 +323,7 @@ rt_hw_context_switch_interrupt_do PROC
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + SYS_STK_SIZE)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
libcpu/arm/arm926/trap.c
+100 -79
View File
@@ -1,7 +1,7 @@
/*
* File : trap.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,17 +20,13 @@
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
* 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
*/
#include <rtthread.h>
#include <rthw.h>
#include <interrupt.h>
/**
* @addtogroup AT91SAM926X
*/
/*@{*/
extern struct rt_thread *rt_current_thread;
#ifdef RT_USING_FINSH
@@ -39,24 +35,24 @@ extern long list_thread(void);
struct rt_hw_register
{
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r4;
rt_uint32_t r5;
rt_uint32_t r6;
rt_uint32_t r7;
rt_uint32_t r8;
rt_uint32_t r9;
rt_uint32_t r10;
rt_uint32_t fp;
rt_uint32_t ip;
rt_uint32_t sp;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t cpsr;
rt_uint32_t ORIG_r0;
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r4;
rt_uint32_t r5;
rt_uint32_t r6;
rt_uint32_t r7;
rt_uint32_t r8;
rt_uint32_t r9;
rt_uint32_t r10;
rt_uint32_t fp;
rt_uint32_t ip;
rt_uint32_t sp;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t cpsr;
rt_uint32_t ORIG_r0;
};
/**
@@ -67,13 +63,18 @@ struct rt_hw_register
void rt_hw_show_register (struct rt_hw_register *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n",
regs->r0, regs->r1, regs->r2, regs->r3);
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n",
regs->r4, regs->r5, regs->r6, regs->r7);
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n",
regs->r8, regs->r9, regs->r10);
rt_kprintf("fp :0x%08x ip :0x%08x\n",
regs->fp, regs->ip);
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n",
regs->sp, regs->lr, regs->pc);
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
}
/**
@@ -86,15 +87,15 @@ void rt_hw_show_register (struct rt_hw_register *regs)
*/
void rt_hw_trap_udef(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("undefined instruction\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
rt_kprintf("undefined instruction\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
list_thread();
#endif
rt_hw_cpu_shutdown();
rt_hw_cpu_shutdown();
}
/**
@@ -108,10 +109,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
*/
void rt_hw_trap_swi(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("software interrupt\n");
rt_hw_cpu_shutdown();
rt_kprintf("software interrupt\n");
rt_hw_cpu_shutdown();
}
/**
@@ -124,15 +125,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
*/
void rt_hw_trap_pabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("prefetch abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
rt_kprintf("prefetch abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
list_thread();
#endif
rt_hw_cpu_shutdown();
rt_hw_cpu_shutdown();
}
/**
@@ -145,15 +146,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_dabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("data abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
rt_kprintf("data abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
list_thread();
#endif
rt_hw_cpu_shutdown();
rt_hw_cpu_shutdown();
}
/**
@@ -165,45 +166,65 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_resv(struct rt_hw_register *regs)
{
rt_kprintf("not used\n");
rt_hw_show_register(regs);
rt_hw_cpu_shutdown();
rt_kprintf("not used\n");
rt_hw_show_register(regs);
rt_hw_cpu_shutdown();
}
extern struct rt_irq_desc irq_desc[];
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq, rt_uint32_t* id);
extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq);
void rt_hw_trap_irq()
{
rt_isr_handler_t isr_func;
rt_uint32_t irqstat, irq;
void *param;
//rt_kprintf("irq interrupt request\n");
/* get irq number */
irqstat = rt_hw_interrupt_get_active(INT_IRQ, &irq);
if (irqstat == 0)
{
rt_kprintf("No interrupt occur\n");
rt_hw_interrupt_ack(INT_IRQ);
return;
}
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
rt_isr_handler_t isr_func;
rt_uint32_t irqstat;
rt_uint32_t irq;
void *param;
extern struct rt_irq_desc irq_desc[];
/* turn to interrupt service routine */
isr_func(irq, param);
// EIOCR must be write any value after interrupt,
// or else can't response next interrupt
rt_hw_interrupt_ack(INT_IRQ);
/* get irq number */
irqstat = rt_hw_interrupt_get_active(INT_IRQ, &irq);
if (irqstat == 0)
{
rt_kprintf("No interrupt occur\n");
rt_hw_interrupt_ack(INT_IRQ);
return;
}
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
rt_hw_interrupt_ack(INT_IRQ);
irq_desc[irq].counter ++;
}
void rt_hw_trap_fiq()
{
rt_kprintf("fast interrupt request\n");
}
rt_isr_handler_t isr_func;
rt_uint32_t irqstat;
rt_uint32_t irq;
void *param;
extern struct rt_irq_desc irq_desc[];
/*@}*/
/* get irq number */
irqstat = rt_hw_interrupt_get_active(INT_FIQ, &irq);
if (irqstat == 0)
{
rt_kprintf("No interrupt occur\n");
rt_hw_interrupt_ack(INT_FIQ);
return;
}
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
rt_hw_interrupt_ack(INT_FIQ);
irq_desc[irq].counter ++;
}