[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740)

* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.

libcpu/arm/cortex-a/backtrace.c

@@ -27,7 +27,7 @@
 #define DBG_LVL    DBG_INFO
 #include <rtdbg.h>
 
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
 #include <lwp.h>
 #include <lwp_user_mm.h>
 #include <lwp_arch.h>
@@ -520,7 +520,7 @@ void rt_unwind(struct rt_hw_exp_stack *regs, unsigned int pc_adj)
     e_regs.ARM_sp = regs->sp;
     e_regs.ARM_lr = regs->lr;
     e_regs.ARM_pc = regs->pc - pc_adj;
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     if (!lwp_user_accessable((void *)e_regs.ARM_pc, sizeof (void *)))
     {
         e_regs.ARM_pc = regs->lr - sizeof(void *);

libcpu/arm/cortex-a/cache.c

@@ -154,7 +154,7 @@ rt_base_t rt_hw_cpu_dcache_status(void)
     return 0;
 }
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
 #define ICACHE (1<<0)
 #define DCACHE (1<<1)
 #define BCACHE (ICACHE|DCACHE)

libcpu/arm/cortex-a/context_gcc.S

@@ -45,12 +45,12 @@ rt_hw_context_switch_to:
 #ifdef RT_USING_SMP
     mov     r0, r1
     bl      rt_cpus_lock_status_restore
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     bl      rt_thread_self
     bl      lwp_user_setting_restore
 #endif
 #else
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     bl      rt_thread_self
     mov     r4, r0
     bl      lwp_mmu_switch
@@ -85,7 +85,7 @@ rt_hw_context_switch:
 
     stmfd sp!, {r4}         @ push cpsr
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
     sub sp, #8
 #endif
@@ -108,12 +108,12 @@ rt_hw_context_switch:
 #ifdef RT_USING_SMP
     mov     r0, r2
     bl      rt_cpus_lock_status_restore
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     bl      rt_thread_self
     bl      lwp_user_setting_restore
 #endif
 #else
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     bl      rt_thread_self
     mov     r4, r0
     bl      lwp_mmu_switch
@@ -149,9 +149,9 @@ rt_hw_context_switch_interrupt:
      * r2 :addr of to_thread's sp
      * r3 :to_thread's tcb
      */
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     push {r0 - r3, lr}
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     bl rt_thread_self
     bl lwp_user_setting_save
 #endif
@@ -161,11 +161,11 @@ rt_hw_context_switch_interrupt:
 
     ldr     sp, [r2]
     mov     r0, r3
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     mov     r4, r0
 #endif
     bl      rt_cpus_lock_status_restore
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     mov     r0, r4
     bl      lwp_user_setting_restore
 #endif
@@ -177,7 +177,7 @@ rt_hw_context_switch_interrupt:
      * r2 :from_thread's tcb
      * r3 :to_thread's tcb
      */
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     /* now to_thread(r3) not used */
     ldr ip, =rt_thread_switch_interrupt_flag
     ldr r3, [ip]
@@ -187,7 +187,7 @@ rt_hw_context_switch_interrupt:
     str r0, [r3]
     mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
     str r3, [ip]
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     push {r1, lr}
     mov r0, r2
     bl lwp_user_setting_save
@@ -239,14 +239,14 @@ rt_hw_context_switch_exit:
 1:
 #endif
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */
     add     sp, #8
 #endif
     ldmfd   sp!, {r1}
     msr     spsr_cxsf, r1        /* original mode */
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     and r1, #0x1f
     cmp r1, #0x10
     bne 1f

libcpu/arm/cortex-a/interrupt.c

@@ -69,7 +69,7 @@ void rt_hw_interrupt_init(void)
     rt_memset(isr_table, 0x00, sizeof(isr_table));
 
     /* initialize ARM GIC */
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     gic_dist_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_dist_base(), 0x2000, MMU_MAP_K_RW);
     gic_cpu_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_cpu_base(), 0x1000, MMU_MAP_K_RW);
 #else
@@ -99,7 +99,7 @@ void rt_hw_interrupt_init(void)
     rt_memset(isr_table, 0x00, sizeof(isr_table));
 
     /* initialize ARM GIC */
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     gic_dist_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_dist_base(), 0x2000, MMU_MAP_K_RW);
 #else
     gic_dist_base = platform_get_gic_dist_base();

libcpu/arm/cortex-a/mmu.c

@@ -16,7 +16,7 @@
 #include "cp15.h"
 #include "mmu.h"
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
 #include <lwp_mm.h>
 #include "page.h"
 #endif
@@ -24,7 +24,7 @@
 /* level1 page table, each entry for 1MB memory. */
 volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
 
-#ifndef RT_USING_LWP
+#ifndef RT_USING_SMART
 static rt_mutex_t mm_lock = RT_NULL;
 
 void rt_mm_lock(void)
@@ -323,7 +323,7 @@ int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void* v_address, size_t size)
     return 0;
 }
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
 static size_t find_vaddr(rt_mmu_info *mmu_info, int pages)
 {
     size_t l1_off, l2_off;

libcpu/arm/cortex-a/mmu.h

@@ -19,7 +19,7 @@
 #define SHAREDEVICE    (1<<2)  /* shared device */
 #define STRONGORDER    (0<<2)  /* strong ordered */
 #define XN             (1<<4)  /* eXecute Never */
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
 #define AP_RW          (1<<10) /* supervisor=RW, user=No */
 #define AP_RO          ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */
 #else
@@ -100,7 +100,7 @@ int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size
 int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void* v_address, size_t size);
 void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size);
 
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
 void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr);
 void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr);
 #else

libcpu/arm/cortex-a/stack.c

@@ -56,7 +56,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     else
         *(--stk) = SVCMODE;                 /* arm mode   */
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     *(--stk) = 0;       /* user lr */
     *(--stk) = 0;       /* user sp*/
 #endif

libcpu/arm/cortex-a/start_gcc.S

@@ -22,7 +22,7 @@
 .equ I_Bit,           0x80   /* when I bit is set, IRQ is disabled */
 .equ F_Bit,           0x40   /* when F bit is set, FIQ is disabled */
 
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
 .data
 .align 14
 init_mtbl:
@@ -101,7 +101,7 @@ continue:
     dsb
     isb
 
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     ldr r5, =PV_OFFSET
 
     mov r7, #0x100000
@@ -179,7 +179,7 @@ bss_loop:
     ldr r1, [r1]
     bl rt_hw_init_mmu_table
 
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     ldr r0, =MMUTable     /* vaddr    */
     add r0, r5            /* to paddr */
     bl  rt_hw_mmu_switch
@@ -225,7 +225,7 @@ stack_setup:
 
     bx      lr
 
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
 .align 2
 .global enable_mmu
 enable_mmu:
@@ -331,7 +331,7 @@ vector_irq:
     mrs     r1,  spsr         /* original mode */
     stmfd   r0!, {r1}
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     stmfd   r0, {r13, r14}^   /* usr_sp, usr_lr */
     sub     r0, #8
 #endif
@@ -379,7 +379,7 @@ vector_irq:
     cmp     r1, #1
     beq     rt_hw_context_switch_interrupt_do
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     ldmfd   sp!, {r0-r12,lr}
     cps     #Mode_SVC
     push    {r0-r12}
@@ -430,7 +430,7 @@ rt_hw_context_switch_interrupt_do:
     stmfd   sp!, {r1-r4}        /* push old task's r0-r3 */
     stmfd   sp!, {r0}           /* push old task's cpsr */
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     stmfd   sp, {r13, r14}^     /*push usr_sp, usr_lr */
     sub     sp, #8
 #endif
@@ -457,7 +457,7 @@ rt_hw_context_switch_interrupt_do:
     ldr     sp,  [r6]       /* get new task's stack pointer */
 
     bl      rt_thread_self
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     mov     r4, r0
     bl      lwp_mmu_switch
     mov     r0, r4
@@ -477,7 +477,7 @@ rt_hw_context_switch_interrupt_do:
 1:
 #endif
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     ldmfd sp, {r13, r14}^    /*pop usr_sp, usr_lr */
     add sp, #8
 #endif
@@ -485,7 +485,7 @@ rt_hw_context_switch_interrupt_do:
     ldmfd   sp!, {r4}        /* pop new task's cpsr to spsr */
     msr     spsr_cxsf, r4
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     and     r4, #0x1f
     cmp     r4, #0x10
     bne     1f
@@ -543,7 +543,7 @@ vector_undef:
     .globl  vector_pabt
 vector_pabt:
     push_svc_reg
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     /* cp Mode_ABT stack to SVC */
     sub     sp, sp, #17 * 4     /* Sizeof(struct rt_hw_exp_stack)  */
     mov     lr, r0
@@ -571,7 +571,7 @@ vector_pabt:
     .globl  vector_dabt
 vector_dabt:
     push_svc_reg
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     /* cp Mode_ABT stack to SVC */
     sub     sp, sp, #17 * 4    /* Sizeof(struct rt_hw_exp_stack)  */
     mov     lr, r0
@@ -610,7 +610,7 @@ rt_hw_clz:
 
 .global rt_secondary_cpu_entry
 rt_secondary_cpu_entry:
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     ldr     r5, =PV_OFFSET
 
     ldr     lr, =after_enable_mmu_n
@@ -641,7 +641,7 @@ after_enable_mmu_n:
     bl stack_setup
 
     /* initialize the mmu table and enable mmu */
-#ifndef RT_USING_USERSPACE
+#ifndef RT_USING_SMART
     bl rt_hw_mmu_init
 #endif
 

libcpu/arm/cortex-a/trap.c

@@ -19,7 +19,7 @@
 extern long list_thread(void);
 #endif
 
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
 #include <lwp.h>
 #include <lwp_arch.h>
 
@@ -70,7 +70,7 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
     rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
     rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
     rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     {
         uint32_t v;
         asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(v));
@@ -128,7 +128,7 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
         }
     }
 #endif
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     check_user_fault(regs, 4, "User undefined instruction");
 #endif
     rt_unwind(regs, 4);
@@ -169,7 +169,7 @@ void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
 {
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     if (dbg_check_event(regs, 4))
     {
         return;
@@ -195,7 +195,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
 {
-#ifdef RT_USING_LWP
+#ifdef RT_USING_SMART
     if (dbg_check_event(regs, 8))
     {
         return;

libcpu/arm/cortex-a/vector_gcc.S

@@ -15,7 +15,7 @@
 
 .globl system_vectors
 system_vectors:
-#ifdef RT_USING_USERSPACE
+#ifdef RT_USING_SMART
     b _reset
 #else
     ldr pc, _vector_reset