From 643581be365b33168ac150ed0a1afb28c06ce1c0 Mon Sep 17 00:00:00 2001 From: "shuta.lst" Date: Thu, 26 Feb 2026 16:31:43 +0800 Subject: [PATCH] fix[bsp][ultrarisc]: Add RISC-V Standard Svpbmt Extension macro definition; --- bsp/ultrarisc/arch/ur-cp100/riscv_mmu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/bsp/ultrarisc/arch/ur-cp100/riscv_mmu.h b/bsp/ultrarisc/arch/ur-cp100/riscv_mmu.h index 1048d4bb40..61ad06491f 100644 --- a/bsp/ultrarisc/arch/ur-cp100/riscv_mmu.h +++ b/bsp/ultrarisc/arch/ur-cp100/riscv_mmu.h @@ -19,6 +19,18 @@ #undef PAGE_SIZE +/* + * RISC-V Standard Svpbmt Extension (Bit 61-62) + * 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type) + * 01: NC (Non-cacheable, Weakly-ordered) + * 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent) + * 11: Reserved + */ +#define PTE_PBMT_PMA (0UL << 61) +#define PTE_PBMT_NC (1UL << 61) +#define PTE_PBMT_IO (2UL << 61) +#define PTE_PBMT_MASK (3UL << 61) + #define PAGE_OFFSET_SHIFT 0 #define PAGE_OFFSET_BIT 12 #define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)