mirror of
https://github.com/RT-Thread/rt-thread.git
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[libcpu] remove libcpu/risc-v
This commit is contained in:
liang yongxiang
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// See LICENSE for license details.
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#ifndef _SIFIVE_HIFIVE1_H
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#define _SIFIVE_HIFIVE1_H
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#include <stdint.h>
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/****************************************************************************
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* GPIO Connections
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*****************************************************************************/
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// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
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// These are also mapped to RGB LEDs on the Freedom E300 Arty
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// FPGA
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// Dev Kit.
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#define RED_LED_OFFSET 22
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#define GREEN_LED_OFFSET 19
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#define BLUE_LED_OFFSET 21
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// These are the GPIO bit offsets for the differen digital pins
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// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
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#define PIN_0_OFFSET 16
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#define PIN_1_OFFSET 17
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#define PIN_2_OFFSET 18
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#define PIN_3_OFFSET 19
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#define PIN_4_OFFSET 20
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#define PIN_5_OFFSET 21
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#define PIN_6_OFFSET 22
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#define PIN_7_OFFSET 23
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#define PIN_8_OFFSET 0
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#define PIN_9_OFFSET 1
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#define PIN_10_OFFSET 2
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#define PIN_11_OFFSET 3
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#define PIN_12_OFFSET 4
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#define PIN_13_OFFSET 5
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//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
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#define PIN_15_OFFSET 9
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#define PIN_16_OFFSET 10
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#define PIN_17_OFFSET 11
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#define PIN_18_OFFSET 12
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#define PIN_19_OFFSET 13
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// These are *PIN* numbers, not
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// GPIO Offset Numbers.
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#define PIN_SPI1_SCK (13u)
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#define PIN_SPI1_MISO (12u)
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#define PIN_SPI1_MOSI (11u)
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#define PIN_SPI1_SS0 (10u)
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#define PIN_SPI1_SS1 (14u)
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#define PIN_SPI1_SS2 (15u)
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#define PIN_SPI1_SS3 (16u)
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#define SS_PIN_TO_CS_ID(x) \
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((x==PIN_SPI1_SS0 ? 0 : \
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(x==PIN_SPI1_SS1 ? 1 : \
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(x==PIN_SPI1_SS2 ? 2 : \
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(x==PIN_SPI1_SS3 ? 3 : \
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-1)))))
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// These buttons are present only on the Freedom E300 Arty Dev Kit.
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#ifdef HAS_BOARD_BUTTONS
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#define BUTTON_0_OFFSET 15
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#define BUTTON_1_OFFSET 30
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#define BUTTON_2_OFFSET 31
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#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
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#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
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#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
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#endif
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#define HAS_HFXOSC 1
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#define HAS_LFROSC_BYPASS 1
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#define RTC_FREQ 32768
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void write_hex(int fd, unsigned long int hex);
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#endif /* _SIFIVE_HIFIVE1_H */
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// See LICENSE for license details.
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#ifndef _SIFIVE_PLATFORM_H
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#define _SIFIVE_PLATFORM_H
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// Some things missing from the official encoding.h
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#define MCAUSE_INT 0x80000000
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#define MCAUSE_CAUSE 0x7FFFFFFF
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#include "sifive/const.h"
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#include "sifive/devices/aon.h"
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#include "sifive/devices/clint.h"
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#include "sifive/devices/gpio.h"
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#include "sifive/devices/otp.h"
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#include "sifive/devices/plic.h"
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#include "sifive/devices/prci.h"
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#include "sifive/devices/pwm.h"
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#include "sifive/devices/spi.h"
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#include "sifive/devices/uart.h"
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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// Memory map
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#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
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#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
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#define OTP_MEM_ADDR _AC(0x00020000,UL)
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#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
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#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
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#define AON_CTRL_ADDR _AC(0x10000000,UL)
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#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
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#define OTP_CTRL_ADDR _AC(0x10010000,UL)
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#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
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#define UART0_CTRL_ADDR _AC(0x10013000,UL)
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#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
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#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
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#define UART1_CTRL_ADDR _AC(0x10023000,UL)
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#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
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#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
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#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
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#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
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#define SPI0_MEM_ADDR _AC(0x20000000,UL)
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#define MEM_CTRL_ADDR _AC(0x80000000,UL)
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// IOF masks
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#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
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#define SPI11_NUM_SS (4)
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#define IOF_SPI1_SS0 (2u)
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#define IOF_SPI1_SS1 (8u)
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#define IOF_SPI1_SS2 (9u)
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#define IOF_SPI1_SS3 (10u)
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#define IOF_SPI1_MOSI (3u)
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#define IOF_SPI1_MISO (4u)
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#define IOF_SPI1_SCK (5u)
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#define IOF_SPI1_DQ0 (3u)
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#define IOF_SPI1_DQ1 (4u)
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#define IOF_SPI1_DQ2 (6u)
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#define IOF_SPI1_DQ3 (7u)
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#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
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#define SPI2_NUM_SS (1)
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#define IOF_SPI2_SS0 (26u)
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#define IOF_SPI2_MOSI (27u)
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#define IOF_SPI2_MISO (28u)
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#define IOF_SPI2_SCK (29u)
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#define IOF_SPI2_DQ0 (27u)
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#define IOF_SPI2_DQ1 (28u)
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#define IOF_SPI2_DQ2 (30u)
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#define IOF_SPI2_DQ3 (31u)
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//#define IOF0_I2C_MASK _AC(0x00003000,UL)
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#define IOF0_UART0_MASK _AC(0x00030000, UL)
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#define IOF_UART0_RX (16u)
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#define IOF_UART0_TX (17u)
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#define IOF0_UART1_MASK _AC(0x03000000, UL)
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#define IOF_UART1_RX (24u)
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#define IOF_UART1_TX (25u)
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#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
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#define IOF1_PWM1_MASK _AC(0x00780000, UL)
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#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
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// Interrupt numbers
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#define INT_RESERVED 0
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#define INT_WDOGCMP 1
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#define INT_RTCCMP 2
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#define INT_UART0_BASE 3
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#define INT_UART1_BASE 4
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#define INT_SPI0_BASE 5
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#define INT_SPI1_BASE 6
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#define INT_SPI2_BASE 7
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#define INT_GPIO_BASE 8
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#define INT_PWM0_BASE 40
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#define INT_PWM1_BASE 44
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#define INT_PWM2_BASE 48
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// Helper functions
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#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
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#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
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#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
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#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
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#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
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#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
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#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
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#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
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#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
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#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
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#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
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#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
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#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
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#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
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#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
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#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
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// Misc
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#include <stdint.h>
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#define NUM_GPIO 32
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#define PLIC_NUM_INTERRUPTS 52
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#define PLIC_NUM_PRIORITIES 7
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#include "hifive1.h"
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unsigned long get_cpu_freq(void);
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unsigned long get_timer_freq(void);
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uint64_t get_timer_value(void);
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#endif /* _SIFIVE_PLATFORM_H */
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@@ -1,36 +0,0 @@
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// See LICENSE for license details.
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#ifndef _RISCV_BITS_H
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#define _RISCV_BITS_H
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#define likely(x) __builtin_expect((x), 1)
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#define unlikely(x) __builtin_expect((x), 0)
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#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
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#define ROUNDDOWN(a, b) ((a)/(b)*(b))
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
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#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
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#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
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#define STR(x) XSTR(x)
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#define XSTR(x) #x
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#if __riscv_xlen == 64
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# define SLL32 sllw
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# define STORE sd
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# define LOAD ld
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# define LWU lwu
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# define LOG_REGBYTES 3
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#else
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# define SLL32 sll
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# define STORE sw
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# define LOAD lw
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# define LWU lw
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# define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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#endif
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@@ -1,18 +0,0 @@
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// See LICENSE for license details.
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/* Derived from <linux/const.h> */
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#ifndef _SIFIVE_CONST_H
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#define _SIFIVE_CONST_H
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#ifdef __ASSEMBLER__
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#define _AC(X,Y) X
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#define _AT(T,X) X
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#else
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#define _AC(X,Y) (X##Y)
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#define _AT(T,X) ((T)(X))
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#endif /* !__ASSEMBLER__*/
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#define _BITUL(x) (_AC(1,UL) << (x))
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#define _BITULL(x) (_AC(1,ULL) << (x))
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#endif /* _SIFIVE_CONST_H */
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@@ -1,88 +0,0 @@
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// See LICENSE for license details.
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#ifndef _SIFIVE_AON_H
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#define _SIFIVE_AON_H
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/* Register offsets */
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#define AON_WDOGCFG 0x000
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#define AON_WDOGCOUNT 0x008
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#define AON_WDOGS 0x010
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#define AON_WDOGFEED 0x018
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#define AON_WDOGKEY 0x01C
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#define AON_WDOGCMP 0x020
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#define AON_RTCCFG 0x040
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#define AON_RTCLO 0x048
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#define AON_RTCHI 0x04C
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#define AON_RTCS 0x050
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#define AON_RTCCMP 0x060
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#define AON_BACKUP0 0x080
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#define AON_BACKUP1 0x084
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#define AON_BACKUP2 0x088
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#define AON_BACKUP3 0x08C
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#define AON_BACKUP4 0x090
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#define AON_BACKUP5 0x094
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#define AON_BACKUP6 0x098
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#define AON_BACKUP7 0x09C
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#define AON_BACKUP8 0x0A0
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#define AON_BACKUP9 0x0A4
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#define AON_BACKUP10 0x0A8
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#define AON_BACKUP11 0x0AC
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#define AON_BACKUP12 0x0B0
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#define AON_BACKUP13 0x0B4
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#define AON_BACKUP14 0x0B8
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#define AON_BACKUP15 0x0BC
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|
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#define AON_PMUWAKEUPI0 0x100
|
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#define AON_PMUWAKEUPI1 0x104
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#define AON_PMUWAKEUPI2 0x108
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#define AON_PMUWAKEUPI3 0x10C
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#define AON_PMUWAKEUPI4 0x110
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#define AON_PMUWAKEUPI5 0x114
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#define AON_PMUWAKEUPI6 0x118
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#define AON_PMUWAKEUPI7 0x11C
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#define AON_PMUSLEEPI0 0x120
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#define AON_PMUSLEEPI1 0x124
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#define AON_PMUSLEEPI2 0x128
|
||||
#define AON_PMUSLEEPI3 0x12C
|
||||
#define AON_PMUSLEEPI4 0x130
|
||||
#define AON_PMUSLEEPI5 0x134
|
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#define AON_PMUSLEEPI6 0x138
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#define AON_PMUSLEEPI7 0x13C
|
||||
#define AON_PMUIE 0x140
|
||||
#define AON_PMUCAUSE 0x144
|
||||
#define AON_PMUSLEEP 0x148
|
||||
#define AON_PMUKEY 0x14C
|
||||
|
||||
#define AON_LFROSC 0x070
|
||||
/* Constants */
|
||||
|
||||
#define AON_WDOGKEY_VALUE 0x51F15E
|
||||
#define AON_WDOGFEED_VALUE 0xD09F00D
|
||||
|
||||
#define AON_WDOGCFG_SCALE 0x0000000F
|
||||
#define AON_WDOGCFG_RSTEN 0x00000100
|
||||
#define AON_WDOGCFG_ZEROCMP 0x00000200
|
||||
#define AON_WDOGCFG_ENALWAYS 0x00001000
|
||||
#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
|
||||
#define AON_WDOGCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_RTCCFG_SCALE 0x0000000F
|
||||
#define AON_RTCCFG_ENALWAYS 0x00001000
|
||||
#define AON_RTCCFG_CMPIP 0x10000000
|
||||
|
||||
#define AON_WAKEUPCAUSE_RESET 0x00
|
||||
#define AON_WAKEUPCAUSE_RTC 0x01
|
||||
#define AON_WAKEUPCAUSE_DWAKEUP 0x02
|
||||
#define AON_WAKEUPCAUSE_AWAKEUP 0x03
|
||||
|
||||
#define AON_RESETCAUSE_POWERON 0x0000
|
||||
#define AON_RESETCAUSE_EXTERNAL 0x0100
|
||||
#define AON_RESETCAUSE_WATCHDOG 0x0200
|
||||
|
||||
#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
|
||||
#define AON_PMUCAUSE_RESETCAUSE 0xFF00
|
||||
|
||||
#endif /* _SIFIVE_AON_H */
|
||||
@@ -1,14 +0,0 @@
|
||||
// See LICENSE for license details
|
||||
|
||||
#ifndef _SIFIVE_CLINT_H
|
||||
#define _SIFIVE_CLINT_H
|
||||
|
||||
|
||||
#define CLINT_MSIP 0x0000
|
||||
#define CLINT_MSIP_size 0x4
|
||||
#define CLINT_MTIMECMP 0x4000
|
||||
#define CLINT_MTIMECMP_size 0x8
|
||||
#define CLINT_MTIME 0xBFF8
|
||||
#define CLINT_MTIME_size 0x8
|
||||
|
||||
#endif /* _SIFIVE_CLINT_H */
|
||||
@@ -1,24 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_GPIO_H
|
||||
#define _SIFIVE_GPIO_H
|
||||
|
||||
#define GPIO_INPUT_VAL (0x00)
|
||||
#define GPIO_INPUT_EN (0x04)
|
||||
#define GPIO_OUTPUT_EN (0x08)
|
||||
#define GPIO_OUTPUT_VAL (0x0C)
|
||||
#define GPIO_PULLUP_EN (0x10)
|
||||
#define GPIO_DRIVE (0x14)
|
||||
#define GPIO_RISE_IE (0x18)
|
||||
#define GPIO_RISE_IP (0x1C)
|
||||
#define GPIO_FALL_IE (0x20)
|
||||
#define GPIO_FALL_IP (0x24)
|
||||
#define GPIO_HIGH_IE (0x28)
|
||||
#define GPIO_HIGH_IP (0x2C)
|
||||
#define GPIO_LOW_IE (0x30)
|
||||
#define GPIO_LOW_IP (0x34)
|
||||
#define GPIO_IOF_EN (0x38)
|
||||
#define GPIO_IOF_SEL (0x3C)
|
||||
#define GPIO_OUTPUT_XOR (0x40)
|
||||
|
||||
#endif /* _SIFIVE_GPIO_H */
|
||||
@@ -1,23 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_OTP_H
|
||||
#define _SIFIVE_OTP_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define OTP_LOCK 0x00
|
||||
#define OTP_CK 0x04
|
||||
#define OTP_OE 0x08
|
||||
#define OTP_SEL 0x0C
|
||||
#define OTP_WE 0x10
|
||||
#define OTP_MR 0x14
|
||||
#define OTP_MRR 0x18
|
||||
#define OTP_MPP 0x1C
|
||||
#define OTP_VRREN 0x20
|
||||
#define OTP_VPPEN 0x24
|
||||
#define OTP_A 0x28
|
||||
#define OTP_D 0x2C
|
||||
#define OTP_Q 0x30
|
||||
#define OTP_READ_TIMINGS 0x34
|
||||
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef PLIC_H
|
||||
#define PLIC_H
|
||||
|
||||
#include <sifive/const.h>
|
||||
|
||||
// 32 bits per source
|
||||
#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
|
||||
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
|
||||
// 1 bit per source (1 address)
|
||||
#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
|
||||
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
|
||||
|
||||
//0x80 per target
|
||||
#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
|
||||
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
|
||||
|
||||
|
||||
#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
|
||||
#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
|
||||
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
|
||||
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
|
||||
|
||||
#define PLIC_MAX_SOURCE 1023
|
||||
#define PLIC_SOURCE_MASK 0x3FF
|
||||
|
||||
#define PLIC_MAX_TARGET 15871
|
||||
#define PLIC_TARGET_MASK 0x3FFF
|
||||
|
||||
#endif /* PLIC_H */
|
||||
@@ -1,56 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PRCI_H
|
||||
#define _SIFIVE_PRCI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PRCI_HFROSCCFG (0x0000)
|
||||
#define PRCI_HFXOSCCFG (0x0004)
|
||||
#define PRCI_PLLCFG (0x0008)
|
||||
#define PRCI_PLLDIV (0x000C)
|
||||
#define PRCI_PROCMONCFG (0x00F0)
|
||||
|
||||
/* Fields */
|
||||
#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
|
||||
#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
|
||||
#define ROSC_EN(x) (((x) & 0x1 ) << 30)
|
||||
#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
|
||||
|
||||
#define XOSC_EN(x) (((x) & 0x1) << 30)
|
||||
#define XOSC_RDY(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R(x) (((x) & 0x7) << 0)
|
||||
// single reserved bit for F LSB.
|
||||
#define PLL_F(x) (((x) & 0x3F) << 4)
|
||||
#define PLL_Q(x) (((x) & 0x3) << 10)
|
||||
#define PLL_SEL(x) (((x) & 0x1) << 16)
|
||||
#define PLL_REFSEL(x) (((x) & 0x1) << 17)
|
||||
#define PLL_BYPASS(x) (((x) & 0x1) << 18)
|
||||
#define PLL_LOCK(x) (((x) & 0x1) << 31)
|
||||
|
||||
#define PLL_R_default 0x1
|
||||
#define PLL_F_default 0x1F
|
||||
#define PLL_Q_default 0x3
|
||||
|
||||
#define PLL_REFSEL_HFROSC 0x0
|
||||
#define PLL_REFSEL_HFXOSC 0x1
|
||||
|
||||
#define PLL_SEL_HFROSC 0x0
|
||||
#define PLL_SEL_PLL 0x1
|
||||
|
||||
#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
|
||||
#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
|
||||
|
||||
#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
|
||||
#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
|
||||
#define PROCMON_EN(x) (((x) & 0x1) << 16)
|
||||
#define PROCMON_SEL(x) (((x) & 0x3) << 24)
|
||||
#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
|
||||
|
||||
#define PROCMON_SEL_HFCLK 0
|
||||
#define PROCMON_SEL_HFXOSCIN 1
|
||||
#define PROCMON_SEL_PLLOUTDIV 2
|
||||
#define PROCMON_SEL_PROCMON 3
|
||||
|
||||
#endif // _SIFIVE_PRCI_H
|
||||
@@ -1,37 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_PWM_H
|
||||
#define _SIFIVE_PWM_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define PWM_CFG 0x00
|
||||
#define PWM_COUNT 0x08
|
||||
#define PWM_S 0x10
|
||||
#define PWM_CMP0 0x20
|
||||
#define PWM_CMP1 0x24
|
||||
#define PWM_CMP2 0x28
|
||||
#define PWM_CMP3 0x2C
|
||||
|
||||
/* Constants */
|
||||
|
||||
#define PWM_CFG_SCALE 0x0000000F
|
||||
#define PWM_CFG_STICKY 0x00000100
|
||||
#define PWM_CFG_ZEROCMP 0x00000200
|
||||
#define PWM_CFG_DEGLITCH 0x00000400
|
||||
#define PWM_CFG_ENALWAYS 0x00001000
|
||||
#define PWM_CFG_ONESHOT 0x00002000
|
||||
#define PWM_CFG_CMP0CENTER 0x00010000
|
||||
#define PWM_CFG_CMP1CENTER 0x00020000
|
||||
#define PWM_CFG_CMP2CENTER 0x00040000
|
||||
#define PWM_CFG_CMP3CENTER 0x00080000
|
||||
#define PWM_CFG_CMP0GANG 0x01000000
|
||||
#define PWM_CFG_CMP1GANG 0x02000000
|
||||
#define PWM_CFG_CMP2GANG 0x04000000
|
||||
#define PWM_CFG_CMP3GANG 0x08000000
|
||||
#define PWM_CFG_CMP0IP 0x10000000
|
||||
#define PWM_CFG_CMP1IP 0x20000000
|
||||
#define PWM_CFG_CMP2IP 0x40000000
|
||||
#define PWM_CFG_CMP3IP 0x80000000
|
||||
|
||||
#endif /* _SIFIVE_PWM_H */
|
||||
@@ -1,80 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_SPI_H
|
||||
#define _SIFIVE_SPI_H
|
||||
|
||||
/* Register offsets */
|
||||
|
||||
#define SPI_REG_SCKDIV 0x00
|
||||
#define SPI_REG_SCKMODE 0x04
|
||||
#define SPI_REG_CSID 0x10
|
||||
#define SPI_REG_CSDEF 0x14
|
||||
#define SPI_REG_CSMODE 0x18
|
||||
|
||||
#define SPI_REG_DCSSCK 0x28
|
||||
#define SPI_REG_DSCKCS 0x2a
|
||||
#define SPI_REG_DINTERCS 0x2c
|
||||
#define SPI_REG_DINTERXFR 0x2e
|
||||
|
||||
#define SPI_REG_FMT 0x40
|
||||
#define SPI_REG_TXFIFO 0x48
|
||||
#define SPI_REG_RXFIFO 0x4c
|
||||
#define SPI_REG_TXCTRL 0x50
|
||||
#define SPI_REG_RXCTRL 0x54
|
||||
|
||||
#define SPI_REG_FCTRL 0x60
|
||||
#define SPI_REG_FFMT 0x64
|
||||
|
||||
#define SPI_REG_IE 0x70
|
||||
#define SPI_REG_IP 0x74
|
||||
|
||||
/* Fields */
|
||||
|
||||
#define SPI_SCK_POL 0x1
|
||||
#define SPI_SCK_PHA 0x2
|
||||
|
||||
#define SPI_FMT_PROTO(x) ((x) & 0x3)
|
||||
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
|
||||
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
|
||||
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
|
||||
|
||||
/* TXCTRL register */
|
||||
#define SPI_TXWM(x) ((x) & 0xffff)
|
||||
/* RXCTRL register */
|
||||
#define SPI_RXWM(x) ((x) & 0xffff)
|
||||
|
||||
#define SPI_IP_TXWM 0x1
|
||||
#define SPI_IP_RXWM 0x2
|
||||
|
||||
#define SPI_FCTRL_EN 0x1
|
||||
|
||||
#define SPI_INSN_CMD_EN 0x1
|
||||
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
|
||||
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
|
||||
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
|
||||
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
|
||||
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
|
||||
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
|
||||
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
|
||||
|
||||
#define SPI_TXFIFO_FULL (1 << 31)
|
||||
#define SPI_RXFIFO_EMPTY (1 << 31)
|
||||
|
||||
/* Values */
|
||||
|
||||
#define SPI_CSMODE_AUTO 0
|
||||
#define SPI_CSMODE_HOLD 2
|
||||
#define SPI_CSMODE_OFF 3
|
||||
|
||||
#define SPI_DIR_RX 0
|
||||
#define SPI_DIR_TX 1
|
||||
|
||||
#define SPI_PROTO_S 0
|
||||
#define SPI_PROTO_D 1
|
||||
#define SPI_PROTO_Q 2
|
||||
|
||||
#define SPI_ENDIAN_MSB 0
|
||||
#define SPI_ENDIAN_LSB 1
|
||||
|
||||
|
||||
#endif /* _SIFIVE_SPI_H */
|
||||
@@ -1,27 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _SIFIVE_UART_H
|
||||
#define _SIFIVE_UART_H
|
||||
|
||||
/* Register offsets */
|
||||
#define UART_REG_TXFIFO 0x00
|
||||
#define UART_REG_RXFIFO 0x04
|
||||
#define UART_REG_TXCTRL 0x08
|
||||
#define UART_REG_RXCTRL 0x0c
|
||||
#define UART_REG_IE 0x10
|
||||
#define UART_REG_IP 0x14
|
||||
#define UART_REG_DIV 0x18
|
||||
|
||||
/* TXCTRL register */
|
||||
#define UART_TXEN 0x1
|
||||
#define UART_TXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* RXCTRL register */
|
||||
#define UART_RXEN 0x1
|
||||
#define UART_RXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* IP register */
|
||||
#define UART_IP_TXWM 0x1
|
||||
#define UART_IP_RXWM 0x2
|
||||
|
||||
#endif /* _SIFIVE_UART_H */
|
||||
@@ -1,17 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
#ifndef _SECTIONS_H
|
||||
#define _SECTIONS_H
|
||||
|
||||
extern unsigned char _rom[];
|
||||
extern unsigned char _rom_end[];
|
||||
|
||||
extern unsigned char _ram[];
|
||||
extern unsigned char _ram_end[];
|
||||
|
||||
extern unsigned char _ftext[];
|
||||
extern unsigned char _etext[];
|
||||
extern unsigned char _fbss[];
|
||||
extern unsigned char _ebss[];
|
||||
extern unsigned char _end[];
|
||||
|
||||
#endif /* _SECTIONS_H */
|
||||
@@ -1,65 +0,0 @@
|
||||
#ifndef SIFIVE_SMP
|
||||
#define SIFIVE_SMP
|
||||
|
||||
// The maximum number of HARTs this code supports
|
||||
#ifndef MAX_HARTS
|
||||
#define MAX_HARTS 32
|
||||
#endif
|
||||
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
|
||||
|
||||
// The hart that non-SMP tests should run on
|
||||
#ifndef NONSMP_HART
|
||||
#define NONSMP_HART 0
|
||||
#endif
|
||||
|
||||
/* If your test cannot handle multiple-threads, use this:
|
||||
* smp_disable(reg1)
|
||||
*/
|
||||
#define smp_disable(reg1, reg2) \
|
||||
csrr reg1, mhartid ;\
|
||||
li reg2, NONSMP_HART ;\
|
||||
beq reg1, reg2, hart0_entry ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
j 42b ;\
|
||||
hart0_entry:
|
||||
|
||||
/* If your test needs to temporarily block multiple-threads, do this:
|
||||
* smp_pause(reg1, reg2)
|
||||
* ... single-threaded work ...
|
||||
* smp_resume(reg1, reg2)
|
||||
* ... multi-threaded work ...
|
||||
*/
|
||||
|
||||
#define smp_pause(reg1, reg2) \
|
||||
li reg2, 0x8 ;\
|
||||
csrw mie, reg2 ;\
|
||||
csrr reg2, mhartid ;\
|
||||
bnez reg2, 42f
|
||||
|
||||
#define smp_resume(reg1, reg2) \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
csrr reg2, mip ;\
|
||||
andi reg2, reg2, 0x8 ;\
|
||||
beqz reg2, 42b ;\
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
csrr reg2, mhartid ;\
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b
|
||||
|
||||
#endif
|
||||
@@ -1,81 +0,0 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-07-31 zhangjun copy from mini2440
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk;
|
||||
|
||||
//stk = (rt_uint32_t*)stack_addr;
|
||||
stack_addr += sizeof(rt_uint32_t);
|
||||
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
|
||||
stk = (rt_uint32_t *)stack_addr;
|
||||
|
||||
*(--stk) = (rt_uint32_t)tentry; /* entry point */
|
||||
*(--stk) = (rt_uint32_t)texit; /* ra */
|
||||
*(--stk) = (rt_uint32_t)parameter; /* a0 */
|
||||
*(--stk) = 0xffffffff; /* a1 */
|
||||
*(--stk) = 0xffffffff; /* a2 */
|
||||
*(--stk) = 0xffffffff; /* a3 */
|
||||
*(--stk) = 0xffffffff; /* a4 */
|
||||
*(--stk) = 0xffffffff; /* a5 */
|
||||
*(--stk) = 0xffffffff; /* a6 */
|
||||
*(--stk) = 0xffffffff; /* a7 */
|
||||
*(--stk) = 0xffffffff; /* s0/fp */
|
||||
*(--stk) = 0xffffffff; /* s1 */
|
||||
*(--stk) = 0xffffffff; /* s2 */
|
||||
*(--stk) = 0xffffffff; /* s3 */
|
||||
*(--stk) = 0xffffffff; /* s4 */
|
||||
*(--stk) = 0xffffffff; /* s5 */
|
||||
*(--stk) = 0xffffffff; /* s6 */
|
||||
*(--stk) = 0xffffffff; /* s7 */
|
||||
*(--stk) = 0xffffffff; /* s8 */
|
||||
*(--stk) = 0xffffffff; /* s9 */
|
||||
*(--stk) = 0xffffffff; /* s10*/
|
||||
*(--stk) = 0xffffffff; /* s11*/
|
||||
*(--stk) = 0xffffffff; /* t0 */
|
||||
*(--stk) = 0xffffffff; /* t1 */
|
||||
*(--stk) = 0xffffffff; /* t2 */
|
||||
*(--stk) = 0xffffffff; /* t3 */
|
||||
*(--stk) = 0xffffffff; /* t4 */
|
||||
*(--stk) = 0xffffffff; /* t5 */
|
||||
*(--stk) = 0xffffffff; /* t6 */
|
||||
*(--stk) = 0xffffffff; /* tp */
|
||||
*(--stk) = 0xffffffff; /* gp */
|
||||
*(--stk) = 0x880; /* mie */
|
||||
// *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,55 +0,0 @@
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <platform.h>
|
||||
#include <encoding.h>
|
||||
#include "interrupt.h"
|
||||
extern struct rt_irq_desc irq_desc[];
|
||||
extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
|
||||
void rt_hw_trap_irq()
|
||||
{
|
||||
rt_isr_handler_t isr_func;
|
||||
rt_uint32_t irq;
|
||||
void *param;
|
||||
|
||||
/* get irq number */
|
||||
irq = rt_hw_interrupt_get_active(0);
|
||||
|
||||
/* get interrupt service routine */
|
||||
isr_func = irq_desc[irq].handler;
|
||||
param = irq_desc[irq].param;
|
||||
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(irq, param);
|
||||
rt_hw_interrupt_ack(0, irq);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
irq_desc[irq].counter ++;
|
||||
#endif
|
||||
}
|
||||
void handle_m_ext_interrupt()
|
||||
{
|
||||
}
|
||||
void rt_systick_handler(void)
|
||||
{
|
||||
clear_csr(mie, MIP_MTIP);
|
||||
|
||||
// Reset the timer for 3s in the future.
|
||||
// This also clears the existing timer interrupt.
|
||||
|
||||
volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);
|
||||
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
|
||||
uint64_t now = *mtime;
|
||||
uint64_t then = now + 2 * RTC_FREQ/RT_TICK_PER_SECOND;
|
||||
*mtimecmp = then;
|
||||
rt_tick_increase();
|
||||
|
||||
// read the current value of the LEDS and invert them.
|
||||
/*
|
||||
GPIO_REG(GPIO_OUTPUT_VAL) ^= ((0x1 << RED_LED_OFFSET) |
|
||||
(0x1 << GREEN_LED_OFFSET) |
|
||||
(0x1 << BLUE_LED_OFFSET));
|
||||
*/
|
||||
|
||||
// Re-enable the timer interrupt.
|
||||
set_csr(mie, MIP_MTIP);
|
||||
}
|
||||
Reference in New Issue
Block a user