mirror of
https://github.com/RT-Thread/rt-thread.git
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[libcpu] Add k210 BSP.
This commit is contained in:
Bernard Xiong
@@ -0,0 +1,203 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/01 Bernard The first version
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*/
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#include <rthw.h>
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#include "tick.h"
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#include <plic.h>
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#include <clint.h>
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#include <interrupt.h>
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#define CPU_NUM 2
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#define MAX_HANDLERS IRQN_MAX
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static struct rt_irq_desc irq_desc[CPU_NUM][MAX_HANDLERS];
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static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
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{
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rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
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return RT_NULL;
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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int idx;
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int cpuid;
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cpuid = current_coreid();
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/* Disable all interrupts for the current core. */
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for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++)
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plic->target_enables.target[cpuid].enable[idx] = 0;
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/* Set priorities to zero. */
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for (idx = 0; idx < PLIC_NUM_SOURCES; idx++)
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plic->source_priorities.priority[idx] = 0;
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/* Set the threshold to zero. */
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plic->targets.target[cpuid].priority_threshold = 0;
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/* init exceptions table */
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for (idx = 0; idx < MAX_HANDLERS; idx++)
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{
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rt_hw_interrupt_mask(idx);
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irq_desc[cpuid][idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
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irq_desc[cpuid][idx].param = RT_NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[cpuid][idx].name, RT_NAME_MAX - 1, "default");
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irq_desc[idx][cpuid].counter = 0;
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#endif
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}
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/* Enable machine external interrupts. */
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set_csr(mie, MIP_MEIP);
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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plic_irq_disable(vector);
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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plic_set_priority(vector, 1);
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plic_irq_enable(vector);
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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int cpuid;
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rt_isr_handler_t old_handler = RT_NULL;
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cpuid = current_coreid();
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if(vector < MAX_HANDLERS)
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{
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old_handler = irq_desc[cpuid][vector].handler;
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if (handler != RT_NULL)
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{
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irq_desc[cpuid][vector].handler = (rt_isr_handler_t)handler;
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irq_desc[cpuid][vector].param = param;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[cpuid][vector].name, RT_NAME_MAX - 1, "%s", name);
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irq_desc[cpuid][vector].counter = 0;
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#endif
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}
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}
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return old_handler;
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}
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uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc)
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{
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/*
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* After the highest-priority pending interrupt is claimed by a target
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* and the corresponding IP bit is cleared, other lower-priority
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* pending interrupts might then become visible to the target, and so
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* the PLIC EIP bit might not be cleared after a claim. The interrupt
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* handler can check the local meip/heip/seip/ueip bits before exiting
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* the handler, to allow more efficient service of other interrupts
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* without first restoring the interrupted context and taking another
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* interrupt trap.
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*/
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if (read_csr(mip) & MIP_MEIP)
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{
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/* Get current core id */
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uint64_t core_id = current_coreid();
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/* Get primitive interrupt enable flag */
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uint64_t ie_flag = read_csr(mie);
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/* Get current IRQ num */
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uint32_t int_num = plic->targets.target[core_id].claim_complete;
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/* Get primitive IRQ threshold */
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uint32_t int_threshold = plic->targets.target[core_id].priority_threshold;
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/* Set new IRQ threshold = current IRQ threshold */
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plic->targets.target[core_id].priority_threshold = plic->source_priorities.priority[int_num];
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/* Disable software interrupt and timer interrupt */
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clear_csr(mie, MIP_MTIP | MIP_MSIP);
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if (irq_desc[core_id][int_num].handler)
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{
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irq_desc[core_id][int_num].handler(int_num, irq_desc[core_id][int_num].param);
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}
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/* Perform IRQ complete */
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plic->targets.target[core_id].claim_complete = int_num;
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/* Set MPIE and MPP flag used to MRET instructions restore MIE flag */
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set_csr(mstatus, MSTATUS_MPIE | MSTATUS_MPP);
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/* Restore primitive interrupt enable flag */
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write_csr(mie, ie_flag);
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/* Restore primitive IRQ threshold */
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plic->targets.target[core_id].priority_threshold = int_threshold;
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}
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else
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{
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rt_kprintf("unhandled trap!\n");
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}
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return epc;
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}
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uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
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{
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int cause = mcause & CAUSE_MACHINE_IRQ_REASON_MASK;
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if (mcause & (1UL << 63))
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{
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switch (cause)
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{
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case IRQ_M_SOFT:
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break;
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case IRQ_M_EXT:
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handle_irq_m_ext(mcause, epc);
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break;
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case IRQ_M_TIMER:
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tick_isr();
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break;
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}
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}
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else
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{
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rt_thread_t tid;
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extern long list_thread();
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rt_hw_interrupt_disable();
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tid = rt_thread_self();
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rt_kprintf("\n");
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rt_kprintf("unhandled trap, epc => 0x%08x, INT[%d]\n", epc, rt_interrupt_get_nest());
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rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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while(1);
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}
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return epc;
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}
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@@ -0,0 +1,137 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/02 Bernard The first version
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*/
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#include "cpuport.h"
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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/* save thread context to thread stack */
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addi sp, sp, -32 * REGBYTES
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STORE x1, 1 * REGBYTES(sp)
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li t0, 0x80
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STORE t0, 2 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* switch to interrupt stack */
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move s0, sp
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/* get cpu id */
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csrr t0, mhartid
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/* switch interrupt stack of current cpu */
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la sp, __stack_start__
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addi t1, t0, 1
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li t2, __STACKSIZE__
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mul t1, t1, t2
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add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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/* handle interrupt */
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call rt_interrupt_enter
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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call handle_trap
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call rt_interrupt_leave
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/* switch to from_thread stack */
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move sp, s0
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/* need to switch new thread */
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la s0, rt_thread_switch_interrupt_flag
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lw s2, 0(s0)
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beqz s2, spurious_interrupt
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sw zero, 0(s0)
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csrr a0, mepc
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STORE a0, 0 * REGBYTES(sp)
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la s0, rt_interrupt_from_thread
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LOAD s1, 0(s0)
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STORE sp, 0(s1)
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la s0, rt_interrupt_to_thread
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LOAD s1, 0(s0)
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LOAD sp, 0(s1)
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LOAD a0, 0 * REGBYTES(sp)
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csrw mepc, a0
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spurious_interrupt:
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LOAD x1, 1 * REGBYTES(sp)
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/* Remain in M-mode after mret */
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li t0, 0x00001800
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csrs mstatus, t0
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LOAD t0, 2 * REGBYTES(sp)
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csrs mstatus, t0
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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mret
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@@ -0,0 +1,128 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
|
||||
* Date Author Notes
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* 2018/10/01 Bernard The first version
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*/
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#define MSTATUS_FS 0x00006000U /* initial state of FPU */
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#include <cpuport.h>
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.global _start
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.section ".start", "ax"
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_start:
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j 1f
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.word 0xdeadbeef
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1:
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csrw mideleg, 0
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csrw medeleg, 0
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csrw mie, 0
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csrw mip, 0
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la t0, trap_entry
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csrw mtvec, t0
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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/* set to initial state of FPU and disable interrupt */
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li t0, MSTATUS_FS
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csrs mstatus, t0
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fssr x0
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fmv.d.x f0, x0
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fmv.d.x f1, x0
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fmv.d.x f2, x0
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fmv.d.x f3, x0
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fmv.d.x f4, x0
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fmv.d.x f5, x0
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fmv.d.x f6, x0
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fmv.d.x f7, x0
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fmv.d.x f8, x0
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fmv.d.x f9, x0
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fmv.d.x f10,x0
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fmv.d.x f11,x0
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fmv.d.x f12,x0
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fmv.d.x f13,x0
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fmv.d.x f14,x0
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fmv.d.x f15,x0
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fmv.d.x f16,x0
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fmv.d.x f17,x0
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fmv.d.x f18,x0
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fmv.d.x f19,x0
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fmv.d.x f20,x0
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fmv.d.x f21,x0
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fmv.d.x f22,x0
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fmv.d.x f23,x0
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fmv.d.x f24,x0
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fmv.d.x f25,x0
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fmv.d.x f26,x0
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fmv.d.x f27,x0
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fmv.d.x f28,x0
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fmv.d.x f29,x0
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fmv.d.x f30,x0
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fmv.d.x f31,x0
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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/* get cpu id */
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csrr a0, mhartid
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la sp, __stack_start__
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addi t1, a0, 1
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li t2, __STACKSIZE__
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mul t1, t1, t2
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add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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/* other cpu core, jump to cpu entry directly */
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bnez a0, _cpu_entry
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|
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#if 0
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/* clear bss section */
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la a0, __bss_start
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la a1, __bss_end
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, REGBYTES
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bltu a0, a1, 1b
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2:
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#endif
|
||||
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_cpu_entry:
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csrr a0, mhartid
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||||
j cpu_entry
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||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <encoding.h>
|
||||
#include <clint.h>
|
||||
#include <sysctl.h>
|
||||
|
||||
static volatile unsigned long tick_cycles = 0;
|
||||
int tick_isr(void)
|
||||
{
|
||||
uint64_t core_id = current_coreid();
|
||||
|
||||
clint->mtimecmp[core_id] += tick_cycles;
|
||||
rt_tick_increase();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Sets and enable the timer interrupt */
|
||||
int rt_hw_tick_init(void)
|
||||
{
|
||||
/* Read core id */
|
||||
unsigned long core_id = current_coreid();
|
||||
unsigned long interval = 1000/RT_TICK_PER_SECOND;
|
||||
|
||||
/* Clear the Machine-Timer bit in MIE */
|
||||
clear_csr(mie, MIP_MTIP);
|
||||
|
||||
/* calculate the tick cycles */
|
||||
tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1;
|
||||
/* Set mtimecmp by core id */
|
||||
clint->mtimecmp[core_id] = clint->mtime + tick_cycles;
|
||||
|
||||
/* Enable the Machine-Timer bit in MIE */
|
||||
set_csr(mie, MIP_MTIP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#ifndef TICK_H__
|
||||
#define TICK_H__
|
||||
|
||||
int tick_isr(void);
|
||||
int rt_hw_tick_init(void);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user