feat[bsp][xuantie]: c/r serial cpus support SMP;

.github/ALL_BSP_COMPILE.json

@@ -491,7 +491,7 @@
       "RTT_BSP": "xuantie",
       "RTT_TOOL_CHAIN": "sourcery-Xuantie-900-gcc-elf-newlib",
       "SUB_RTT_BSP": [
-        "xuantie/smartl/e901",
+        "xuantie/smartl/e901plus",
         "xuantie/smartl/e902",
         "xuantie/smartl/e906",
         "xuantie/smartl/e907",
@@ -499,7 +499,7 @@
         "xuantie/xiaohui/c907",
         "xuantie/xiaohui/c908",
         "xuantie/xiaohui/c908x",
-        "xuantie/xiaohui/c910",
+        "xuantie/xiaohui/c920",
         "xuantie/xiaohui/r908",
         "xuantie/xiaohui/r910",
         "xuantie/xiaohui/r920"

bsp/README.md

@@ -773,14 +773,15 @@ This document is based on the RT-Thread mainline repository and categorizes the
 
 | BSP Name | GPIO | UART | ADC | I2C | SPI | WDT |
 |----------|------|------|-----|-----|-----|-----|
-| [e901](xuantie/smartl/e901) | - | ✅ | - | - | - | - |
+| [e901plus](xuantie/smartl/e901plus) | - | ✅ | - | - | - | - |
 | [e902](xuantie/smartl/e902) | - | ✅ | - | - | - | - |
 | [e906](xuantie/smartl/e906) | - | ✅ | - | - | - | - |
 | [e907](xuantie/smartl/e907) | - | ✅ | - | - | - | - |
 | [c906 (RT-Smart)](xuantie/virt64/c906) | - | ✅ | - | - | - | - |
 | [c907](xuantie/xiaohui/c907) | - | ✅ | - | - | - | - |
 | [c908](xuantie/xiaohui/c908) | - | ✅ | - | - | - | - |
-| [c910](xuantie/xiaohui/c910) | - | ✅ | - | - | - | - |
+| [c908x](xuantie/xiaohui/c908x) | - | ✅ | - | - | - | - |
+| [c920](xuantie/xiaohui/c920) | - | ✅ | - | - | - | - |
 | [r908](xuantie/xiaohui/r908) | - | ✅ | - | - | - | - |
 | [r910](xuantie/xiaohui/r910) | - | ✅ | - | - | - | - |
 | [r920](xuantie/xiaohui/r920) | - | ✅ | - | - | - | - |

bsp/xuantie/libraries/xuantie_libraries/SConscript

@@ -7,6 +7,14 @@ cwd = GetCurrentDir()
 objs = []
 list = os.listdir(cwd)
 
+# Include source files in current directory
+src = []
+if GetDepend(['RT_USING_SMP']):
+    src += ['smp_demo.c']
+if src:
+    objs = objs + DefineGroup('xuantie_libraries', src, depend=[''])
+
+# Include subdirectories with SConscript
 for d in list:
     path = os.path.join(cwd, d)
     if os.path.isfile(os.path.join(path, 'SConscript')):

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld

@@ -24,13 +24,13 @@
  ******************************************************************************/
 MEMORY
 {
-    ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x20000   /* ISRAM 128KB*/
+    ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x30000   /* ISRAM 192KB*/
-    DSRAM : ORIGIN = 0x20000000 , LENGTH = 0x80000   /* DSRAM 512KB*/
+    DSRAM : ORIGIN = 0x20000000 , LENGTH = 0xC0000   /* DSRAM 768KB*/
     SRAM :  ORIGIN = 0x60000000 , LENGTH = 0x20000   /* SRAM 128KB, no cacheable*/
 }
 
 __min_heap_size = 0x200;
-PROVIDE (__ram_end  = 0x20080000);
+PROVIDE (__ram_end  = 0x200C0000);
 PROVIDE (__heap_end = __ram_end);
 
 REGION_ALIAS("REGION_TEXT",    ISRAM);
@@ -47,6 +47,7 @@ SECTIONS
   KEEP(*startup.o(*.text))
   KEEP(*startup.o(*.vectors))
   KEEP(*vectors.o(*.text))
+  KEEP(*whetstone.o(*.text))
   KEEP(*(.text.entry))
   *(.text*)
   *(.gnu.warning)
@@ -64,6 +65,12 @@ SECTIONS
   . = ALIGN(0x10) ;
   __etext = . ;
  } > REGION_TEXT
+ .eh_frame_hdr : {
+  *(.eh_frame_hdr)
+ } > REGION_TEXT
+ .eh_frame : ONLY_IF_RO {
+  KEEP (*(.eh_frame))
+ } > REGION_TEXT
  .rodata : {
   . = ALIGN(0x4) ;
   __srodata = .;
@@ -189,7 +196,7 @@ SECTIONS
   KEEP(*(*.post_driver_entry))
   __post_driver_end__ = .;
 /************** end of drivers *********/
-  . = ALIGN(0x4) ;
+  . = ALIGN(0x8) ;
   __erodata = .;
   __rodata_end__ = .;
  } > REGION_RODATA
@@ -231,10 +238,10 @@ SECTIONS
   . = ALIGN(0x4) ;
   __ram_code_end__ = .;
  } > REGION_DATA AT > REGION_RODATA
- .bss : {
+ .bss : ALIGN(0x20) {
-  . = ALIGN(0x4) ;
+  __sbss = . ;
-  __sbss = ALIGN(0x4) ;
   __bss_start__ = . ;
+  KEEP(*linpack.o(*.bss*))
   *(.dynsbss)
   *(.sbss)
   *(.sbss.*)

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h

@@ -25,26 +25,14 @@
 #ifndef __RISCV_ASM_MACRO_H__
 #define __RISCV_ASM_MACRO_H__
 
-#if (!defined(__riscv_flen)) && (CONFIG_CHECK_FPU_DIRTY)
+#include <rtconfig.h>
-#error "this cpu doesn't supprot FPU, but macro 'CONFIG_CHECK_FPU_DIRTY' is defined, please remove it."
-#endif
-
-#if (!defined(__riscv_vector)) && (CONFIG_CHECK_VECTOR_DIRTY)
-#error "this cpu doesn't supprot vector, but macro 'CONFIG_CHECK_VECTOR_DIRTY' is defined, please remove it."
-#endif
-
-#if (!defined(__riscv_matrix) && !defined(__riscv_xtheadmatrix)) && (CONFIG_CHECK_MATRIX_DIRTY)
-#error "this cpu doesn't supprot matrix, but macro 'CONFIG_CHECK_MATRIX_DIRTY' is defined, please remove it."
-#endif
-
 #include "riscv_csr.h"
 
-#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY
 .macro RESTORE_MSTATUS
     /* t0 and t1 are not restored before using */
     /* now, sp is at the top of the stack (the lowest address)*/
     li       t1, 0
-#if __riscv_matrix || __riscv_xtheadmatrix  /* matrix registers */
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */
 #if __riscv_xlen == 64
     addi     t1, t1, (12 + 12)
 #else
@@ -55,7 +43,7 @@
     add      t1, t1, t0
 #endif /* __riscv_matrix || __riscv_xtheadmatrix */
 
-#ifdef __riscv_vector /* vector registers */
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */
     csrr     t0, vlenb
     slli     t0, t0, 5
     add      t1, t1, t0
@@ -66,6 +54,7 @@
 #endif  /* __riscv_xlen */
 #endif  /* __riscv_vector */
 
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64 /* float registers */
 #if __riscv_xlen == 64
     addi     t1, t1, 168
@@ -76,8 +65,9 @@
 #elif __riscv_flen == 32
     addi     t1, t1, 84
 #endif /* __riscv_flen */
+#endif
 
-#ifdef __riscv_dsp  /* vxsat register, 32-bit cpu only */
+#if __riscv_dsp && defined(ARCH_RISCV_DSP) /* vxsat register, 32-bit cpu only */
     addi     t1, t1, 4
 #endif /* __riscv_dsp */
 
@@ -86,19 +76,18 @@
 #elif __riscv_xlen == 32
     addi     t1, t1, 72
 #endif
-    add      sp, sp, t1
+    add      t1, sp, t1
 
-    /* now, sp is the position of mstatus */
+    /* now, t1 is the position of mstatus */
-    load_x   t3, (0)(sp)
+    load_x   t3, (0)(t1)
     csrw     mstatus, t3
-    sub      sp, sp, t1
 .endm
 
 .macro RESTORE_SSTATUS
     /* t0 and t1 are not restored before using */
     /* now, sp is at the top of the stack (the lowest address)*/
     li       t1, 0
-#if __riscv_matrix || __riscv_xtheadmatrix /* matrix registers */
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */
 #if __riscv_xlen == 64
     addi     t1, t1, (12 + 12)
 #else
@@ -109,7 +98,7 @@
     add      t1, t1, t0
 #endif /* __riscv_matrix || __riscv_xtheadmatrix */
 
-#ifdef __riscv_vector /* vector registers */
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */
     csrr     t0, vlenb
     slli     t0, t0, 5
     add      t1, t1, t0
@@ -120,6 +109,7 @@
 #endif  /* __riscv_xlen */
 #endif  /* __riscv_vector */
 
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64 /* float registers */
 #if __riscv_xlen == 64
     addi     t1, t1, 168
@@ -130,26 +120,24 @@
 #elif __riscv_flen == 32
     addi     t1, t1, 84
 #endif /* __riscv_flen */
+#endif
 
 #if __riscv_xlen == 64  /*general purpose registers*/
     addi     t1, t1, (72 + 72)
 #elif __riscv_xlen == 32
     addi     t1, t1, 72
 #endif
-    add      sp, sp, t1
+    add      t1, sp, t1
 
-    /* now, sp is the position of mstatus */
+    /* now, t1 is the position of mstatus */
-    load_x   t3, (0)(sp)
+    load_x   t3, (0)(t1)
     csrw     sstatus, t3
-    sub      sp, sp, t1
 .endm
 
-#endif /* CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY */
-
 .macro SAVE_VECTOR_REGISTERS
     /* t0,t1 saved before using */
     /* mstatus->t3 */
-#ifdef __riscv_vector
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR)
 #if CONFIG_CHECK_VECTOR_DIRTY
     /* check if VS filed of MSTATUS is 'dirty' */
     li       t1, SR_VS_DIRTY
@@ -227,7 +215,7 @@
 
 .macro RESTORE_VECTOR_REGISTERS
     /* t0,t1,t2 not restored before using, mstatus has been restored before using */
-#ifdef __riscv_vector
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR)
 #if CONFIG_CHECK_VECTOR_DIRTY
     /* check if VS filed of MSTATUS is 'dirty' */
     li       t1, SR_VS_DIRTY
@@ -304,6 +292,7 @@
 
 .macro SAVE_FLOAT_REGISTERS
     /* t0, t1 saved before using */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if CONFIG_CHECK_FPU_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
@@ -378,10 +367,12 @@
     fstore_x ft10,72(sp)
     fstore_x ft11,76(sp)
 #endif /*__riscv_flen */
+#endif
 #if CONFIG_CHECK_FPU_DIRTY
     j        2f
 1:
     /* don't store, move sp only */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if __riscv_xlen == 64
     addi     sp, sp, -168
@@ -391,12 +382,14 @@
 #elif __riscv_flen == 32
     addi     sp, sp, -84
 #endif /* __riscv_xlen */
+#endif
 2:
 #endif
 .endm
 
 .macro RESTORE_FLOAT_REGISTERS
     /* t0 and t1 are not restored before using, mstatus has been restored before using */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if CONFIG_CHECK_FPU_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
@@ -472,10 +465,12 @@
     fscsr    t0
     addi     sp, sp, 4
 #endif /*__riscv_flen */
+#endif
 #if CONFIG_CHECK_FPU_DIRTY
     j        2f
 1:
     /* don't restore, move sp only */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if __riscv_xlen == 64
     addi     sp, sp, 168
@@ -485,6 +480,7 @@
 #elif __riscv_flen == 32
     addi     sp, sp, 84
 #endif /* __riscv_flen */
+#endif
 2:
 #endif /* CONFIG_CHECK_FPU_DIRTY */
 .endm
@@ -492,7 +488,7 @@
 .macro SAVE_MATRIX_REGISTERS
     /* t0,t1 saved before using */
 
-#if __riscv_matrix || __riscv_xtheadmatrix
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX)
 #if CONFIG_CHECK_MATRIX_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
     li       t1, SR_MS_DIRTY
@@ -544,7 +540,7 @@
 .macro RESTORE_MATRIX_REGISTERS
     /* t0 and t1 are not restored before using, mstatus has been restored before using */
 
-#if __riscv_matrix || __riscv_xtheadmatrix
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX)
 #if CONFIG_CHECK_MATRIX_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
     li       t1, SR_MS_DIRTY

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h

@@ -69,7 +69,9 @@
 #define SR_FS_CLEAN     0x00004000UL
 #define SR_FS_DIRTY     0x00006000UL
 
-#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R920
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+    || CONFIG_CPU_XUANTIE_R920 \
+    || CONFIG_CPU_XUANTIE_C920
 #define SR_VS          0x01800000
 #define SR_VS_OFF      0x00000000
 #define SR_VS_INITIAL  0x00800000
@@ -128,7 +130,9 @@
 #define MSTATUS_MPP_SHIFT               11
 #define MSTATUS_MPP                     (3 << MSTATUS_MPP_SHIFT)
 
-#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+    || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
+    || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920
 #define MSTATUS_VS_SHIFT                23
 #else
 #define MSTATUS_VS_SHIFT                9
@@ -136,9 +140,16 @@
 #define MSTATUS_FS_SHIFT                13
 #define MSTATUS_MS_SHIFT                25
 
-#define INSERT_FIELD(val, which, fieldval)  (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+#define INSERT_FIELD(val, which, fieldval)    (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
 
-#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V ||CONFIG_CPU_XUANTIE_C908I || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+    || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \
+    || CONFIG_CPU_XUANTIE_C908_V2 || CONFIG_CPU_XUANTIE_C908V_V2 || CONFIG_CPU_XUANTIE_C908I_V2 \
+    || CONFIG_CPU_XUANTIE_C908_CP_V2 || CONFIG_CPU_XUANTIE_C908V_CP_V2 || CONFIG_CPU_XUANTIE_C908I_CP_V2 \
+    || CONFIG_CPU_XUANTIE_C908_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908V_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908I_CP_XT_V2 \
+    || CONFIG_CPU_XUANTIE_C908VK_CP_V2 || CONFIG_CPU_XUANTIE_C908VK_CP_XT_V2 \
+    || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
+    || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920
 #define ATTR_SO                 (1ull << 4)
 #define ATTR_CA                 (1ull << 3)
 #define ATTR_BU                 (1ull << 2)

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/csi_config.h

@@ -0,0 +1,27 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CSI_CONFIG_H__
+#define __CSI_CONFIG_H__
+
+#if CONFIG_KERNEL_RTTHREAD
+#include <rtconfig.h>
+#endif
+
+
+#endif /* end of __CSI_CONFIG_H__ */

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S

@@ -18,10 +18,6 @@
 
 #include <csi_config.h>
 
-.globl  Reset_Handler
-.global __rt_rvstack
-.equ    Mcoret_Handler, SW_handler
-.equ    Mirq_Handler, SW_handler 
 .section .vectors
     .align  6
     .globl  __Vectors
@@ -56,6 +52,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -120,7 +117,7 @@ __exit:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK
 g_top_irqstack:
-__rt_rvstack:
+
 #ifdef CONFIG_KERNEL_NONE
     .align  4
     .global g_base_mainstack

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S

@@ -22,10 +22,6 @@
 #define CONFIG_NR_CPUS 1
 #endif
 
-.globl  Reset_Handler
-.global __rt_rvstack
-.equ    Mcoret_Handler, SW_handler
-.equ    Mirq_Handler, SW_handler 
 .section .vectors
     .align  6
     .globl  __Vectors
@@ -65,6 +61,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -171,7 +168,6 @@ hart_out_of_bounds_loop:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS
 g_top_irqstack:
-__rt_rvstack:
 
 #ifdef CONFIG_KERNEL_NONE
     .align  4

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S

@@ -22,10 +22,6 @@
 #define CONFIG_NR_CPUS 1
 #endif
 
-.globl  Reset_Handler
-.global __rt_rvstack
-.equ    Mcoret_Handler, SW_handler
-.equ    Mirq_Handler, SW_handler 
 .section .vectors
     .align  6
     .globl  __Vectors
@@ -65,6 +61,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -171,7 +168,6 @@ hart_out_of_bounds_loop:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS
 g_top_irqstack:
-__rt_rvstack:
 
 #ifdef CONFIG_KERNEL_NONE
     .align  4

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S

@@ -22,10 +22,6 @@
 #define CONFIG_NR_CPUS 1
 #endif
 
-.globl  Reset_Handler
-.global __rt_rvstack
-.equ    Mcoret_Handler, SW_handler
-.equ    Mirq_Handler, SW_handler 
 .section .vectors
     .align  6
     .globl  __Vectors
@@ -65,6 +61,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -180,7 +177,6 @@ hart_out_of_bounds_loop:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS
 g_top_irqstack:
-__rt_rvstack:
 
 #ifdef CONFIG_KERNEL_NONE
     .align  4

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S

@@ -1,191 +0,0 @@
- /*
- * Copyright (C) 2017-2024 Alibaba Group Holding Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <csi_config.h>
-
-#ifndef CONFIG_NR_CPUS
-#define CONFIG_NR_CPUS 1
-#endif
-
-.globl  Reset_Handler
-.global __rt_rvstack
-.equ    Mcoret_Handler, SW_handler
-.equ    Mirq_Handler, SW_handler 
-.section .vectors
-    .align  6
-    .globl  __Vectors
-    .type   __Vectors, @object
-__Vectors:
-    j   Default_Handler			/* 0 */
-    j   Stspend_Handler			/* 1 */
-    j   Default_Handler			/* 2 */
-    j   Mtspend_Handler			/* 3 */
-    j   Default_Handler			/* 4 */
-    j   Scoret_Handler			/* 5 */
-    j   Default_Handler			/* 6 */
-    j   Mcoret_Handler			/* 7 */
-    j   Default_Handler			/* 8 */
-    j   Sirq_Handler			/* 9 */
-    j   Default_Handler			/* 10 */
-    j   Mirq_Handler			/* 11 */
-    j   Default_Handler			/* 12 */
-    j   Default_Handler			/* 13 */
-    j   Default_Handler			/* 14 */
-    j   Default_Handler			/* 15 */
-#if CONFIG_ECC_L1_ENABLE
-    j   ECC_L1_Handler			/* 16 */
-#else
-    j   Default_Handler			/* 16 */
-#endif
-
- .text
-    .align  2
-    j        Reset_Handler
-    .align   2
-    .long    0x594B5343 /* CSKY ASCII */
-    .long    0x594B5343 /* CSKY ASCII */
-    .align   2
-    .rept    9
-    .long    0
-    .endr
-    .long    Reset_Handler
-_start:
-    .type   Reset_Handler, %function
-Reset_Handler:
-.option push
-.option norelax
-    /* disable ie and clear all interrupts */
-    csrw    mie, zero
-    csrw    mip, zero
-
-    /* Disable MIE to avoid triggering interrupts before the first task starts. */
-    /* This bit is set when a task recovers context. */
-#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE
-    csrc    mstatus, (1 << 1)
-#else
-    csrc    mstatus, (1 << 3)
-#endif
-
-    la      gp, __global_pointer$
-.option pop
-    la      a0, __Vectors
-    li	    a1, 0x1
-    or	    a0, a0,a1
-    csrw    mtvec, a0
-
-    /* get cpu id */
-    csrr a0, mhartid
-
-#if defined(CONFIG_SMP) && CONFIG_SMP
-    /* check if hart is within range */
-    /* tp: hart id */
-    li	t0, CONFIG_NR_CPUS
-    bge	a0, t0, hart_out_of_bounds_loop
-#endif
-
-#ifdef CONFIG_KERNEL_NONE
-    la   sp, g_base_mainstack
-    addi t1, a0, 1
-    li   t2, CONFIG_ARCH_MAINSTACK
-    mul  t1, t1, t2
-    add  sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */
-#else
-    la   sp, g_base_irqstack
-    addi t1, a0, 1
-    li   t2, CONFIG_ARCH_INTERRUPTSTACK
-    mul  t1, t1, t2
-    add  sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */
-#endif
-
-    /* other cpu core, jump to cpu entry directly */
-    bnez a0, secondary_cpu_entry
-
-#ifndef __NO_SYSTEM_INIT
-    la   a0, SystemInit
-    jalr a0
-#endif
-
-#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE
-    la   a0, smode_init
-    jalr a0
-#endif
-
-#ifdef CONFIG_KERNEL_NONE
-    /* Enable interrupt */
-#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE
-    csrs    sstatus, (1 << 1)
-#else
-    csrs    mstatus, (1 << 3)
-#endif
-#endif
-
-    la   a0, rtthread_startup
-    jalr a0
-
-.size   Reset_Handler, . - Reset_Handler
-
-__exit:
-    j      __exit
-
-    .type   secondary_cpu_entry, %function
-secondary_cpu_entry:
-#if defined(CONFIG_SMP) && CONFIG_SMP
-    la a0, secondary_boot_flag
-    ld a0, 0(a0)
-    li a1, 0xa55a
-    beq a0, a1, 1f
-#endif
-    j secondary_cpu_entry
-
-#if defined(CONFIG_SMP) && CONFIG_SMP
-1:
-    jal secondary_cpu_c_start
-
-.size   secondary_cpu_entry, . - secondary_cpu_entry
-
-hart_out_of_bounds_loop:
-    /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
-    wfi
-    j	hart_out_of_bounds_loop
-#endif
-
-.section .stack
-    .align  4
-    .global g_base_irqstack
-    .global g_top_irqstack
-g_base_irqstack:
-    .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS
-g_top_irqstack:
-__rt_rvstack:
-
-#ifdef CONFIG_KERNEL_NONE
-    .align  4
-    .global g_base_mainstack
-    .global g_top_mainstack
-g_base_mainstack:
-    .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS
-g_top_mainstack:
-#endif
-
-#if defined(CONFIG_SMP) && CONFIG_SMP
-.data
-.global secondary_boot_flag
-.align 3
-secondary_boot_flag:
-    .dword 0
-#endif

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/system.c

@@ -1,324 +0,0 @@
- /*
- * Copyright (C) 2017-2024 Alibaba Group Holding Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <soc.h>
-#include <csi_core.h>
-#include <drv/tick.h>
-#include <drv/porting.h>
-#include <drv/irq.h>
-#include "riscv_csr.h"
-
-#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE)
-#error "Please check the current system is baremetal or not!!!"
-#endif
-
-#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP)
-#if CONFIG_NR_CPUS > 1
-#error "Please define CONFIG_NR_CPUS as 1 or do not need define."
-#endif
-#endif
-
-#if CONFIG_ECC_L2_ENABLE
-static csi_dev_t ecc_l2_dev;
-#endif
-
-extern void section_data_copy(void);
-extern void section_ram_code_copy(void);
-extern void section_bss_clear(void);
-
-#ifdef CONFIG_RISCV_SMODE
-extern unsigned long __Vectors;
-unsigned long page_table_l2[512] __attribute__ ((aligned(4096)));
-unsigned long page_table_l1[512] __attribute__ ((aligned(4096)));
-unsigned long page_table_l0[512] __attribute__ ((aligned(4096)));
-
-void _mmu_init(void) __attribute__((noinline));
-void _mmu_init(void)
-{
-#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
-    || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \
-    || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
-    unsigned long status = __get_MXSTATUS();
-    /* open MAEE for thead-mmu extension */
-    status |= (1 << 21);
-    __set_MXSTATUS(status);
-
-    page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10;
-    page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10;
-    /* setup mmu VA(0M ~ 1M-1) <==>  PA(0M ~ 1M-1) */
-    for (unsigned long i = 0; i < 256; i++) {
-        page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-    }
-
-    /* setup mmu VA(2M ~ 1G-1) <==>  PA(2M ~ 1G-1) */
-    for (unsigned long i = 1; i < 512; i++) {
-        page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-    }
-
-    /* setup mmu VA(1G ~ 2G-1) <==>  PA(1G ~ 2G-1) */
-    page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32
-    unsigned long envcfgh = __get_MENVCFGH();
-    /* enable svpbmt */
-    envcfgh |= (1 << 30);
-    __set_MENVCFGH(envcfgh);
-
-    page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10;
-    /* setup mmu VA(0M ~ 1M-1) <==>  PA(0M ~ 1M-1) */
-    for (unsigned long i = 0; i < 256; i++) {
-        page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-    }
-
-    /* setup mmu VA(4M ~ 1G-1) <==>  PA(4M ~ 1G-1) */
-    for (unsigned long i = 1; i < 256; i++) {
-        page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-    }
-
-    /* setup mmu VA(1G ~ 2G-1) <==>  PA(1G ~ 2G-1) */
-    for (unsigned long i = 256; i < 512; i++) {
-        page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-    }
-#else
-    unsigned long envcfg = __get_MENVCFG();
-    /* enable svpbmt */
-    envcfg |= (1ull << 62);
-    __set_MENVCFG(envcfg);
-
-    page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10;
-    page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10;
-    /* setup mmu VA(0M ~ 1M-1) <==>  PA(0M ~ 1M-1) */
-    for (unsigned long i = 0; i < 256; i++) {
-        page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-    }
-
-    /* setup mmu VA(2M ~ 1G-1) <==>  PA(2M ~ 1G-1) */
-    for (unsigned long i = 1; i < 512; i++) {
-        page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-    }
-
-    /* setup mmu VA(1G ~ 2G-1) <==>  PA(1G ~ 2G-1) */
-    page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1;
-#endif
-
-#if __riscv_xlen == 64
-    csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2));
-#endif
-    csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1));
-    csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0));
-    csi_mmu_invalid_tlb_all();
-#if __riscv_xlen == 64
-    __set_SATP(((unsigned long)&page_table_l2 >> 12));
-    csi_mmu_set_mode(MMU_MODE_39);
-    csi_mmu_enable();
-#else
-    __set_SATP(((unsigned long)&page_table_l1 >> 12));
-    csi_mmu_set_mode(MMU_MODE_32);
-    csi_mmu_enable();
-#endif
-}
-
-void _system_switchto_smode(void)
-{
-    unsigned long m_status = __get_MSTATUS();
-    m_status &= ~MSTATUS_TVM_MASK;
-    m_status &= ~MSTATUS_MPP_MASK;
-    m_status |= MSTATUS_MPP_S;
-    __set_MSTATUS(m_status);
-
-    /* setup S-Mode csr regs */
-    __set_STVEC((unsigned long)(&__Vectors) | 0x1);
-    //FIXME:
-    __ASM("auipc a0, 0");
-    __ASM("addi  a0, a0, 14");
-    __ASM("csrw  mepc, a0");
-    __ASM("mret");
-}
-
-void _system_init_for_smode(void)
-{
-    _system_switchto_smode();
-}
-
-void smode_init(void)
-{
-    /* may be not clear after reset on FPGA */
-    csi_mmu_disable();
-    _mmu_init();
-    _system_init_for_smode();
-}
-#endif
-
-/**
-  * @brief  initialize pmp
-  * @param  None
-  * @return None
-  */
-static void pmp_init(void)
-{
-    long addr;
-
-    addr = 0x90000000UL >> 2;
-    __set_PMPADDR0(addr);
-    __set_PMPxCFG(0, 0x8f);
-}
-
-static void interrupt_init(void)
-{
-    int i;
-
-    for (i = 0; i < CONFIG_IRQ_NUM; i++) {
-        PLIC->PLIC_PRIO[i] = 31;
-    }
-
-    for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) {
-        PLIC->PLIC_IP[i] = 0;
-    }
-
-    for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) {
-        PLIC->PLIC_H0_MIE[i] = 0;
-        PLIC->PLIC_H0_SIE[i] = 0;
-    }
-
-    /* set hart threshold 0, enable all interrupt */
-    PLIC->PLIC_H0_MTH = 0;
-    PLIC->PLIC_H0_STH = 0;
-
-    for (i = 0; i < CONFIG_IRQ_NUM; i++) {
-        PLIC->PLIC_H0_MCLAIM = i;
-        PLIC->PLIC_H0_SCLAIM = i;
-    }
-
-    /* set PLIC_PER */
-    PLIC->PLIC_PER = 0x1;
-
-    /* enable MEIE & MTIE & MSIE */
-    uint32_t mie = __get_MIE();
-    mie |= (1 << 11 | 1 << 7 | 1 << 3);
-#if CONFIG_ECC_L1_ENABLE
-    mie |= (1 << 16);
-#endif
-    __set_MIE(mie);
-}
-
-static void section_init(void)
-{
-#if CONFIG_XIP
-    section_data_copy();
-    section_ram_code_copy();
-    csi_dcache_clean();
-    csi_icache_invalid();
-#endif
-
-    section_bss_clear();
-}
-
-static void cache_init(void)
-{
-    /* enable cache */
-    csi_dcache_enable();
-    csi_icache_enable();
-}
-
-/**
-  * @brief  initialize the system
-  *         Initialize the psr and vbr.
-  * @param  None
-  * @return None
-  */
-void SystemInit(void)
-{
-#if CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP
-    /* disable theadisaee & enable MM */
-    unsigned long status = __get_MXSTATUS();
-    status &= ~(1 << 22);
-    status |= (1 << 24 | 1 << 15);
-    __set_MXSTATUS(status);
-#else
-    /* enable theadisaee & MM */
-    unsigned long status = __get_MXSTATUS();
-    status |= (1 << 22 | 1 << 15);
-    __set_MXSTATUS(status);
-#endif
-
-#if __riscv_flen == 64
-    /* enable float ISA */
-    status = __get_MSTATUS();
-    status |= (1 << MSTATUS_FS_SHIFT);
-    __set_MSTATUS(status);
-#endif
-#ifdef __riscv_vector
-    /* enable vector ISA */
-    status = __get_MSTATUS();
-    status |= (1 << MSTATUS_VS_SHIFT);
-    __set_MSTATUS(status);
-#endif
-
-#if CONFIG_ECC_L1_ENABLE
-    /* enable L1 cache ecc */
-    uint64_t mhint = __get_MHINT();
-    mhint |= (0x1 << 19);
-    __set_MHINT(mhint);
-#endif
-
-#if CONFIG_ECC_L2_ENABLE
-    /* enable L2 cache ecc */
-    uint64_t mccr2 = __get_MCCR2();
-    mccr2 |= (0x1 << 1);
-    __set_MCCR2(mccr2);
-#endif
-
-#ifdef CONFIG_RISCV_SMODE
-    /* enable ecall delegate */
-    unsigned long medeleg = __get_MEDELEG();
-    medeleg |= (1 << 9);
-    __set_MEDELEG(medeleg);
-
-    /* enable interrupt delegate */
-    unsigned long mideleg = __get_MIDELEG();
-    mideleg |= 0x222;
-    __set_MIDELEG(mideleg);
-#endif
-
-#ifdef CONFIG_RISCV_SMODE
-    /* enable mcounteren for s-mode */
-    __set_MCOUNTEREN(0xffffffff);
-
-#if CBO_INSN_SUPPORT
-    unsigned long envcfg = __get_MENVCFG();
-    /* enable CBIE & CBCFE & CBZE on lower priviledge */
-    envcfg |= (3 << 4 | 1 << 6 | 1 << 7);
-    __set_MENVCFG(envcfg);
-#endif
-#endif
-
-    cache_init();
-    section_init();
-    pmp_init();
-
-    interrupt_init();
-    soc_set_sys_freq(20000000);
-    csi_tick_init();
-
-#if CONFIG_ECC_L2_ENABLE
-    extern void ecc_l2_irqhandler(void *arg);
-    /* l2 cache ecc interrupt register */
-    ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn;
-    csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev);
-    csi_irq_enable(ecc_l2_dev.irq_num);
-#endif
-}

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/trap_c.c

@@ -1,64 +0,0 @@
- /*
- * Copyright (C) 2017-2024 Alibaba Group Holding Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <csi_core.h>
-#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0)
-#include <debug/dbg.h>
-#else
-#define printk printf
-#endif
-
-void (*trap_c_callback)(void);
-
-void trap_c(uintptr_t *regs)
-{
-    int i;
-    unsigned long vec = 0;
-
-    vec = __get_MCAUSE();
-
-    printk("CPU Exception(mcause);: NO.0x%lx", vec);
-    printk("\n");
-
-    for (i = 0; i < 31; i++) {
-        printk("x%d: %p\t", i + 1, (void *)regs[i]);
-
-        if ((i % 4) == 3) {
-            printk("\n");
-        }
-    }
-
-    printk("\n");
-    printk("mepc   : %p\n", (void *)regs[31]);
-    printk("mstatus: %p\n", (void *)regs[32]);
-
-    if (trap_c_callback) {
-        trap_c_callback();
-    }
-
-    while (1);
-}
-
-__attribute__((weak)) void exceptionHandler(void *context)
-{
-    trap_c((uintptr_t *)context);
-}
-

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/startup.S

@@ -22,8 +22,6 @@
 #define CONFIG_NR_CPUS 1
 #endif
 
-.globl  Reset_Handler
-
 .section .vectors
     .align  6
     .globl  __Vectors
@@ -63,6 +61,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -132,7 +131,7 @@ Reset_Handler:
 #endif
 #endif
 
-    la   a0, pre_main
+    la   a0, rtthread_startup
     jalr a0
 
 .size   Reset_Handler, . - Reset_Handler

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/startup.S

@@ -17,7 +17,7 @@
  */
 
 #include <csi_config.h>
-.global __rt_rvstack 
+
 #ifndef CONFIG_SUPPORT_NON_VECTOR_IRQ
 .section .vectors, "aw", @progbits
     .align  6
@@ -185,7 +185,7 @@ __exit:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK
 g_top_irqstack:
-__rt_rvstack:
+
 #ifdef CONFIG_KERNEL_NONE
     .align  3
     .global g_base_mainstack

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/startup.S

@@ -17,7 +17,8 @@
  */
 
 #include <csi_config.h>
-.global __rt_rvstack 
+
+#if !CONFIG_SUPPORT_NON_VECTOR_IRQ
 .section .vectors, "aw", @progbits
     .align  6
     .globl  __Vectors
@@ -42,6 +43,11 @@ __Vectors:
 
     /* External interrupts */
     .long   Default_IRQHandler
+#if CONFIG_IRQ_LATENCY
+    .long   IRQ_LATENCY_IRQHandler
+#else
+    .long   Default_IRQHandler
+#endif
     .long   Default_IRQHandler
     .long   Default_IRQHandler
     .long   Default_IRQHandler
@@ -72,9 +78,63 @@ __Vectors:
     .long   Default_IRQHandler
     .long   Default_IRQHandler
     .long   Default_IRQHandler
-    .long   Default_IRQHandler
+#else
+.section .vectors, "aw", @progbits
+    .align  6
+    .globl  __Vectors
+    .type   __Vectors, @object
+__Vectors:
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   tspend_handler
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+
+    /* External interrupts */
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+#endif
 
-    .globl   Reset_Handler
     .text
     .align   2
     j        Reset_Handler
@@ -84,7 +144,7 @@ __Vectors:
     .align   2
 _start:
     .text
-    .long    Reset_Handler
+    .globl   Reset_Handler
     .align  2
     .type   Reset_Handler, %function
 Reset_Handler:
@@ -116,14 +176,14 @@ Reset_Handler:
 __exit:
     j      __exit
 
-.section .stack
+.section .stack, "aw", @nobits
     .align  3
     .global g_base_irqstack
     .global g_top_irqstack
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK
 g_top_irqstack:
-__rt_rvstack:
+
 #ifdef CONFIG_KERNEL_NONE
     .align  3
     .global g_base_mainstack

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/system.c

@@ -58,17 +58,17 @@ static void clic_init(void)
 
     for (i = 0; i < 64; i++) {
         CLIC->CLICINT[i].IP = 0;
+#if !CONFIG_SUPPORT_NON_VECTOR_IRQ
         CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
-        csi_vic_set_prio(i, 1);
+#else
-    }
+        CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */
-
-#ifndef CONFIG_KERNEL_NONE
-    /* tspend use lower priority */
-    csi_vic_set_prio(Machine_Software_IRQn, 0);
-    /* tspend use positive interrupt */
-    CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
-    csi_irq_enable(Machine_Software_IRQn);
 #endif
+        csi_vic_set_prio(i, 3);
+    }
+    /* tspend use vector&positive interrupt */
+    CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
+    csi_vic_set_prio(Machine_Software_IRQn, 1);
+    csi_irq_enable(Machine_Software_IRQn);
 }
 
 static void interrupt_init(void)
@@ -87,6 +87,9 @@ static void interrupt_init(void)
   */
 void SystemInit(void)
 {
+    extern int cpu_features_init(void);
+    cpu_features_init();
+
     /* enable theadisaee */
     uint32_t status = __get_MXSTATUS();
     status |= (1 << 22);

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/vectors.S

@@ -18,10 +18,10 @@
 
 #include "riscv_asm_macro.h"
 
-/* Enable interrupts when returning from the handler */
+#define RISCV_MCAUSE_IRQ_POS 31
-#define MSTATUS_PRV1 0x1880
+#define MSTATUS_IEN 8
 
-.section .stack
+.section .stack, "aw", @nobits
     .align  2
     .global g_trapstackbase
     .global g_top_trapstack
@@ -32,11 +32,19 @@ g_top_trapstack:
 #if CONFIG_SUPPORT_IRQ_NESTED
 #define IRQ_NESTED_MAX  (6)
 .section .bss
-irq_nested_level:
+    .align 2
-.long 0
+    irq_nested_level:
+    .long 0
 
-irq_nested_mcause:
+    irq_nested_mcause:
-.long 0, 0, 0, 0, 0, 0
+    .long 0, 0, 0, 0, 0, 0
+#endif
+
+/* for interrupt tail-chaining debug */
+#if CONFIG_DEBUG_TAIL_CHAINING
+    .global g_irq_tailchain_loops
+g_irq_tailchain_loops:
+    .long 0
 #endif
 
 .text
@@ -46,18 +54,24 @@ irq_nested_mcause:
     .weak   Default_IRQHandler
     .type   Default_IRQHandler, %function
 Default_IRQHandler:
+#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
+    addi    sp, sp, -4
+    sw      s0, (sp)
+#endif
     csrw    mscratch, sp
     la      sp, g_top_irqstack
-    addi    sp, sp, -48
+    addi    sp, sp, -52
     sw      t0, 4(sp)
     sw      t1, 8(sp)
+    sw      t2, 12(sp)
     csrr    t0, mepc
     csrr    t1, mcause
+    csrr    t2, mstatus
     sw      t1, 40(sp)
     sw      t0, 44(sp)
+    sw      t2, 48(sp)
 
     sw      ra, 0(sp)
-    sw      t2, 12(sp)
     sw      a0, 16(sp)
     sw      a1, 20(sp)
     sw      a2, 24(sp)
@@ -81,12 +95,12 @@ Default_IRQHandler:
     and     a5, a4, a3
     sb      a5, 0(a2)
 
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
     csrw    mcause, a1
 
     lw      t0, 44(sp)
+    lw      t1, 48(sp)
     csrw    mepc, t0
+    csrw    mstatus, t1
     lw      ra, 0(sp)
     lw      t0, 4(sp)
     lw      t1, 8(sp)
@@ -98,12 +112,17 @@ Default_IRQHandler:
     lw      a4, 32(sp)
     lw      a5, 36(sp)
 
-    addi    sp, sp, 48
+    addi    sp, sp, 52
     csrr    sp, mscratch
+
+#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
+    addi    sp, sp, 4
+#endif
+
     mret
 #else
     .align  2
-    .weak  Default_IRQHandler
+    .weak   Default_IRQHandler
     .type   Default_IRQHandler, %function
 Default_IRQHandler:
     addi    sp, sp, -8
@@ -131,9 +150,12 @@ Default_IRQHandler:
     li      t0, 1
     bgt     t1, t0, .Lnested1
 
-    lw      t0, 0(sp)
+#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
-    lw      t1, 4(sp)
+    addi    sp, sp, -8
-    addi    sp, sp, 8
+    sw      s0, (sp)
+    csrr    t0, mepc
+    sw      t0, 4(sp)
+#endif
 
     csrw    mscratch, sp
     la      sp, g_top_irqstack
@@ -143,18 +165,20 @@ Default_IRQHandler:
     lw      t1, 4(sp)
     addi    sp, sp, 8
 .Lnested2:
-    addi    sp, sp, -48
+    addi    sp, sp, -52
     sw      t0, 4(sp)
     sw      t1, 8(sp)
+    sw      t2, 12(sp)
     csrr    t0, mepc
     csrr    t1, mcause
+    csrr    t2, mstatus
     sw      t1, 40(sp)
     sw      t0, 44(sp)
+    sw      t2, 48(sp)
 
     csrs    mstatus, 8
 
     sw      ra, 0(sp)
-    sw      t2, 12(sp)
     sw      a0, 16(sp)
     sw      a1, 20(sp)
     sw      a2, 24(sp)
@@ -167,7 +191,6 @@ Default_IRQHandler:
 
     csrc    mstatus, 8
 
-
     lw      a1, 40(sp)
     andi    a0, a1, 0x3FF
     slli    a0, a0, 2
@@ -187,12 +210,12 @@ Default_IRQHandler:
     sw      t1, (t0)
     bgt     t1, zero, .Lnested3
 
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
     csrw    mcause, a1
 
     lw      t0, 44(sp)
+    lw      t1, 48(sp)
     csrw    mepc, t0
+    csrw    mstatus, t1
     lw      ra, 0(sp)
     lw      t0, 4(sp)
     lw      t1, 8(sp)
@@ -204,8 +227,14 @@ Default_IRQHandler:
     lw      a4, 32(sp)
     lw      a5, 36(sp)
 
-    addi    sp, sp, 48
+    addi    sp, sp, 52
     csrr    sp, mscratch
+#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
+    addi    sp, sp, 8
+#endif
+    lw      t0, 0(sp)
+    lw      t1, 4(sp)
+    addi    sp, sp, 8
     mret
 
 .Lnested3:
@@ -220,10 +249,9 @@ Default_IRQHandler:
     or      t0, a0, t0
     csrw    mcause, t0
     lw      t0, 44(sp)
+    lw      t1, 48(sp)
     csrw    mepc, t0
-
+    csrw    mstatus, t1
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
 
     lw      ra, 0(sp)
     lw      t0, 4(sp)
@@ -236,10 +264,12 @@ Default_IRQHandler:
     lw      a4, 32(sp)
     lw      a5, 36(sp)
 
-    addi    sp, sp, 48
+    addi    sp, sp, 52
     mret
 #endif
 
+    .size   Default_IRQHandler, . - Default_IRQHandler
+
 /******************************************************************************
  * Functions:
  *     void trap(void);
@@ -281,6 +311,7 @@ trap:
     la      a1, exceptionHandler
     jalr    a1
 
+    .size   trap, . - trap
 
     .align  6
     .weak   Default_Handler
@@ -291,6 +322,10 @@ Default_Handler:
     sw      t0, 0x0(sp)
     sw      t1, 0x4(sp)
     csrr    t0, mcause
+#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED)
+    srli    t1, t0, RISCV_MCAUSE_IRQ_POS
+    bnez    t1, is_interrupt
+#endif
     andi    t0, t0, 0x3FF
     li      t1, 24
     beq     t0, t1, .NMI_Handler
@@ -298,6 +333,82 @@ Default_Handler:
     lw      t1, 0x4(sp)
     addi    sp, sp, 8
     j      trap
+#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED)
+is_interrupt:
+    lw      t0, 0x0(sp)
+    lw      t1, 0x4(sp)
+    addi    sp, sp, 8
+    csrw    mscratch, sp
+    la      sp, g_top_irqstack
+    addi    sp, sp, -52
+    sw      t0, 4(sp)
+    sw      t1, 8(sp)
+    sw      t2, 12(sp)
+    csrr    t0, mepc
+    csrr    t1, mcause
+    csrr    t2, mstatus
+    sw      t1, 40(sp)
+    sw      t0, 44(sp)
+    sw      t2, 48(sp)
+
+    sw      ra, 0(sp)
+    sw      a0, 16(sp)
+    sw      a1, 20(sp)
+    sw      a2, 24(sp)
+    sw      a3, 28(sp)
+    sw      a4, 32(sp)
+    sw      a5, 36(sp)
+
+#if CONFIG_DEBUG_TAIL_CHAINING
+    li       t2, 0
+    la       t1, g_irq_tailchain_loops
+    sw       t2, 0(t1)
+#endif
+
+    csrrsi   t0, mnxti, MSTATUS_IEN
+    beqz     t0, irq_done
+
+irq_loop:
+#if CONFIG_DEBUG_TAIL_CHAINING
+    la       t2, g_irq_tailchain_loops
+    lw       t1, 0(t2)
+    addi     t1, t1, 1
+    sw       t1, 0(t2)
+#endif
+    lw       t1, 0(t0)
+    jalr     t1
+    csrrsi   t0, mnxti, MSTATUS_IEN
+    bnez     t0, irq_loop
+
+#if CONFIG_DEBUG_TAIL_CHAINING
+    li       t2, 0
+    la       a1, g_irq_tailchain_loops
+    sw       t2, 0(a1)
+#endif
+
+irq_done:
+    lw      t0, 40(sp)
+    lw      t1, 44(sp)
+    lw      t2, 48(sp)
+    csrw    mcause, t0
+    csrw    mepc, t1
+    csrw    mstatus, t2
+
+    lw      ra, 0(sp)
+    lw      t0, 4(sp)
+    lw      t1, 8(sp)
+    lw      t2, 12(sp)
+    lw      a0, 16(sp)
+    lw      a1, 20(sp)
+    lw      a2, 24(sp)
+    lw      a3, 28(sp)
+    lw      a4, 32(sp)
+    lw      a5, 36(sp)
+
+    addi    sp, sp, 52
+    csrr    sp, mscratch
+    mret
+#endif /* (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) */
 .NMI_Handler:
     /* mscratch may be used before */
     addi    sp, sp, -4
@@ -306,16 +417,18 @@ Default_Handler:
 
     csrw    mscratch, sp
     la      sp, g_top_trapstack
-    addi    sp, sp, -48
+    addi    sp, sp, -52
     sw      t0, 4(sp)
     sw      t1, 8(sp)
+    sw      t2, 12(sp)
     csrr    t0, mepc
     csrr    t1, mcause
+    csrr    t2, mstatus
     sw      t1, 40(sp)
     sw      t0, 44(sp)
+    sw      t2, 48(sp)
 
     sw      ra, 0(sp)
-    sw      t2, 12(sp)
     sw      a0, 16(sp)
     sw      a1, 20(sp)
     sw      a2, 24(sp)
@@ -339,12 +452,12 @@ Default_Handler:
     and     a5, a4, a3
     sb      a5, 0(a2)
 
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
     csrw    mcause, a1
 
     lw      t0, 44(sp)
+    lw      t1, 48(sp)
     csrw    mepc, t0
+    csrw    mstatus, t1
     lw      ra, 0(sp)
     lw      t0, 4(sp)
     lw      t1, 8(sp)
@@ -356,7 +469,7 @@ Default_Handler:
     lw      a4, 32(sp)
     lw      a5, 36(sp)
 
-    addi    sp, sp, 48
+    addi    sp, sp, 52
     csrr    sp, mscratch
 
     /* restore mscratch */

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/startup.S

@@ -18,7 +18,7 @@
 
 #include <csi_config.h>
 
-.global __rt_rvstack 
+#if !CONFIG_SUPPORT_NON_VECTOR_IRQ
 .section .vectors, "aw", @progbits
     .align  6
     .globl  __Vectors
@@ -106,10 +106,65 @@ __Vectors:
     .long   Default_IRQHandler
     .long   Default_IRQHandler
     .long   Default_IRQHandler
+#else /* CONFIG_SUPPORT_NON_VECTOR_IRQ */
+.section .vectors, "aw", @progbits
+    .align  6
+    .globl  __Vectors
+    .type   __Vectors, @object
+__Vectors:
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   tspend_handler
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+
+    /* External interrupts */
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+#endif /* CONFIG_SUPPORT_NON_VECTOR_IRQ */
 
     .size   __Vectors, . - __Vectors
 
-    .globl   Reset_Handler
     .text
     .align   2
     j        Reset_Handler
@@ -119,8 +174,8 @@ __Vectors:
     .align   2
 _start:
     .text
-    .long    Reset_Handler
     .align  2
+    .global Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -151,14 +206,14 @@ Reset_Handler:
 __exit:
     j      __exit
 
-.section .stack
+.section .stack, "aw", @nobits
     .align  4
     .global g_base_irqstack
     .global g_top_irqstack
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK
 g_top_irqstack:
-__rt_rvstack:
+
 #ifdef CONFIG_KERNEL_NONE
     .align  4
     .global g_base_mainstack

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/system.c

@@ -60,11 +60,16 @@ static void clic_init(void)
 
     for (i = 0; i < 64; i++) {
         CLIC->CLICINT[i].IP = 0;
+#if !CONFIG_SUPPORT_NON_VECTOR_IRQ
         CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+#else
+        CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */
+#endif
+        csi_vic_set_prio(i, 3);
     }
-
+    /* tspend use vector&positive interrupt */
-    /* tspend use positive interrupt */
     CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
+    csi_vic_set_prio(Machine_Software_IRQn, 1);
     csi_irq_enable(Machine_Software_IRQn);
 }
 
@@ -84,6 +89,9 @@ static void interrupt_init(void)
   */
 void SystemInit(void)
 {
+    extern int cpu_features_init(void);
+    cpu_features_init();
+
     /* enable theadisaee & MM */
     uint32_t status = __get_MXSTATUS();
     status |= (1 << 22 | 1 << 15);
@@ -107,7 +115,7 @@ void SystemInit(void)
     cache_init();
     section_init();
     interrupt_init();
-    soc_set_sys_freq(10000000);
+    soc_set_sys_freq(20000000);
     csi_tick_init();
 }
 

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/startup.S

@@ -17,7 +17,8 @@
  */
 
 #include <csi_config.h>
-.global __rt_rvstack 
+
+#if !CONFIG_SUPPORT_NON_VECTOR_IRQ
 .section .vectors, "aw", @progbits
     .align  6
     .globl  __Vectors
@@ -109,10 +110,65 @@ __Vectors:
     .long   Default_IRQHandler
     .long   Default_IRQHandler
     .long   Default_IRQHandler
+#else
+.section .vectors, "aw", @progbits
+    .align  6
+    .globl  __Vectors
+    .type   __Vectors, @object
+__Vectors:
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   tspend_handler
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+
+    /* External interrupts */
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+    .long   do_irq
+#endif
 
     .size   __Vectors, . - __Vectors
 
-    .globl   Reset_Handler
     .text
     .align   2
     j        Reset_Handler
@@ -122,8 +178,8 @@ __Vectors:
     .align   2
 _start:
     .text
-    .long    Reset_Handler
     .align  2
+    .global Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -154,14 +210,13 @@ Reset_Handler:
 __exit:
     j      __exit
 
-.section .stack
+.section .stack, "aw", @nobits
     .align  4
     .global g_base_irqstack
     .global g_top_irqstack
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK
 g_top_irqstack:
-__rt_rvstack:
 #ifdef CONFIG_KERNEL_NONE
     .align  4
     .global g_base_mainstack

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/system.c

@@ -60,11 +60,16 @@ static void clic_init(void)
 
     for (i = 0; i < 64; i++) {
         CLIC->CLICINT[i].IP = 0;
+#if !CONFIG_SUPPORT_NON_VECTOR_IRQ
         CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+#else
+        CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */
+#endif
+        csi_vic_set_prio(i, 3);
     }
-
+    /* tspend use vector&positive interrupt */
-    /* tspend use positive interrupt */
     CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
+    csi_vic_set_prio(Machine_Software_IRQn, 1);
     csi_irq_enable(Machine_Software_IRQn);
 }
 
@@ -84,6 +89,9 @@ static void interrupt_init(void)
   */
 void SystemInit(void)
 {
+    extern int cpu_features_init(void);
+    cpu_features_init();
+
     /* enable theadisaee & MM */
     uint32_t status = __get_MXSTATUS();
     status |= (1 << 22 | 1 << 15);

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S

@@ -21,8 +21,6 @@
 #ifndef CONFIG_NR_CPUS
 #define CONFIG_NR_CPUS 1
 #endif
-.global __rt_rvstack 
-.globl  Reset_Handler
 
 .section .vectors
     .align  6
@@ -158,6 +156,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -273,7 +272,6 @@ hart_out_of_bounds_loop:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS
 g_top_irqstack:
-__rt_rvstack:
 
 #ifdef CONFIG_KERNEL_NONE
     .align  4

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S

@@ -22,10 +22,6 @@
 #define CONFIG_NR_CPUS 1
 #endif
 
-.globl  Reset_Handler
-.global __rt_rvstack
-.equ    Mcoret_Handler, SW_handler
-.equ    Mirq_Handler, SW_handler 
 .section .vectors
     .align  6
     .globl  __Vectors
@@ -65,6 +61,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -171,7 +168,6 @@ hart_out_of_bounds_loop:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS
 g_top_irqstack:
-__rt_rvstack:
 
 #ifdef CONFIG_KERNEL_NONE
     .align  4

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S

@@ -22,10 +22,6 @@
 #define CONFIG_NR_CPUS 1
 #endif
 
-.globl  Reset_Handler
-.global __rt_rvstack
-.equ    Mcoret_Handler, SW_handler
-.equ    Mirq_Handler, SW_handler 
 .section .vectors
     .align  6
     .globl  __Vectors
@@ -65,6 +61,7 @@ __Vectors:
     .endr
     .long    Reset_Handler
 _start:
+    .globl  Reset_Handler
     .type   Reset_Handler, %function
 Reset_Handler:
 .option push
@@ -171,7 +168,6 @@ hart_out_of_bounds_loop:
 g_base_irqstack:
     .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS
 g_top_irqstack:
-__rt_rvstack:
 
 #ifdef CONFIG_KERNEL_NONE
     .align  4

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/feature.c

@@ -18,7 +18,7 @@
 
 #include <csi_core.h>
 
-/* I/D Cache will enable in cache_init */
+// I/D Cache will enable in cache_init
 void cpu_features_init(void)
 {
 #if CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP
@@ -29,7 +29,7 @@ void cpu_features_init(void)
     return;
 #endif
 
-#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT
+#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M
     return;
 #endif
 
@@ -51,8 +51,7 @@ void cpu_features_init(void)
 
     /* As CPUID is a fifo register, try to find
      * the CPUID[0] whose index(bit[31:28]) == 0  */
-    for (i = 0; i < 8; i++)
+    for (i = 0; i < 8; i++) {
-    {
         version[0] = rv_csr_read(CSR_MCPUID);
         if (((version[0]&0xf0000000) >> 28) == 0)
             break;
@@ -62,8 +61,8 @@ void cpu_features_init(void)
         version[i] = rv_csr_read(CSR_MCPUID);
 
     cpu_type    = (version[0] >> 18) & 0xf;
-    cpu_tnmodel = (version[0] >> 14) & 0x1;
+    cpu_tnmodel    = (version[0] >> 14) & 0x1;
-    cpu_ver     = (version[1] >> 12) & 0xffff;
+    cpu_ver        = (version[1] >> 12) & 0xffff;
 
     rv_csr_write(CSR_MCOR, 0x70013);
 
@@ -71,11 +70,9 @@ void cpu_features_init(void)
      * Warning: CSR_MCCR2 contains an L2 cache latency setting,
      * you need to confirm it by your own soc design.
      */
-    switch (cpu_type)
+    switch (cpu_type) {
-    {
     case 0x1:
-        if (cpu_ver >= 0x0)
+        if (cpu_ver >= 0x0) {
-        {
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x638000);
@@ -87,8 +84,7 @@ void cpu_features_init(void)
         }
         break;
     case 0x2:
-        if (cpu_ver >= 0x0)
+        if (cpu_ver >= 0x0) {
-        {
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xa042000a);
             rv_csr_write(CSR_MXSTATUS, 0x438100);
@@ -103,14 +99,12 @@ void cpu_features_init(void)
         }
         break;
     case 0x3:
-        if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf)
+        if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x
-        { /* 1.2.0~1.2.x */
             rv_csr_write(CSR_MCCR2, 0xe0010009);
             rv_csr_write(CSR_MXSTATUS, 0x638000);
             rv_csr_write(CSR_MHINT, 0x6e30c);
             rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
-        } else if (cpu_ver == 0x10ca)
+        } else if (cpu_ver == 0x10ca) { //1.3.10
-        { /* 1.3.10 */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe2490009);
             rv_csr_write(CSR_MXSTATUS, 0x638000);
@@ -118,39 +112,34 @@ void cpu_features_init(void)
             rv_csr_write(CSR_MHCR, 0x17f & (~0x3));
             rv_csr_write(CSR_MHINT2, 0x420000);
             rv_csr_write(CSR_MHINT4, 0x410);
-        } else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f)
+        } else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x
-        { /* 1.4.0~1.4.x */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe2490009);
             rv_csr_write(CSR_MXSTATUS, 0x638000);
             rv_csr_write(CSR_MHINT, 0x16e30c);
             rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
-        } else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f)
+        } else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x
-        { /* 1.5.0~1.5.x */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe2490009);
             rv_csr_write(CSR_MXSTATUS, 0x638000);
             rv_csr_write(CSR_MHINT, 0xe6e30c);
             rv_csr_write(CSR_MHINT2, 0x180);
             rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
-        } else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183)
+        } else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3
-        { /* 1.6.0~1.6.3 */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x638000);
             rv_csr_write(CSR_MHINT, 0x1ee30c);
             rv_csr_write(CSR_MHINT2, 0x180);
             rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
-        } else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f)
+        } else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x
-        { /* 1.6.4~1.8.x */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x638000);
             rv_csr_write(CSR_MHINT, 0x1ee30c);
             rv_csr_write(CSR_MHINT2, 0x180);
             rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
-        } else if (cpu_ver >= 0x2000 && cpu_ver <= 0x200e)
+        } else if (cpu_ver >= 0x2000 && cpu_ver <= 0x200e) { //2.0.0~2.0.14
-        { /* 2.0.0~2.0.14 */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x438000);
@@ -160,8 +149,7 @@ void cpu_features_init(void)
 #if __riscv_xlen == 64
             rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
-        } else if (cpu_ver >= 0x200f && cpu_ver <= 0x2045)
+        } else if (cpu_ver >= 0x200f && cpu_ver <= 0x2045) { //2.0.15~2.1.5
-        { /* 2.0.15~2.1.5 */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x438000);
@@ -171,8 +159,7 @@ void cpu_features_init(void)
 #if __riscv_xlen == 64
             rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
-        } else if (cpu_ver >= 0x2046 && cpu_ver <= 0x20c3)
+        } else if (cpu_ver >= 0x2046 && cpu_ver <= 0x20c3) { //2.1.6~2.3.3
-        { /* 2.1.6~2.3.3 */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x438000);
@@ -182,8 +169,7 @@ void cpu_features_init(void)
 #if __riscv_xlen == 64
             rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
-        } else if (cpu_ver >= 0x20c4 && cpu_ver <= 0x2fff)
+        } else if (cpu_ver >= 0x20c4 && cpu_ver <= 0x2fff) { //2.3.4~2.x.x
-        { /* 2.3.4~2.x.x */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x438100);
@@ -194,8 +180,7 @@ void cpu_features_init(void)
 #if __riscv_xlen == 64
             rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
-        } else if (cpu_ver >= 0x3000 && cpu_ver <= 0x3fff)
+        } else if (cpu_ver >= 0x3000 && cpu_ver <= 0x3fff) { //3.0.0~3.x.x
-        { /* 3.0.0~3.x.x */
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xe249000b);
             rv_csr_write(CSR_MXSTATUS, 0x438100);
@@ -211,8 +196,7 @@ void cpu_features_init(void)
         }
         break;
     case 0x4:
-        if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff)
+        if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) {
-        {
             rv_csr_write(CSR_MHCR, 0x17f & (~0x3));
             rv_csr_write(CSR_MXSTATUS, 0x638000);
             rv_csr_write(CSR_MHINT, 0x650c);
@@ -221,17 +205,14 @@ void cpu_features_init(void)
         }
         break;
     case 0x5:
-        if(cpu_tnmodel == 0)
+        if(cpu_tnmodel == 0) { //c908
-        { /* c908 */
+            if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7
-            if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007)
-            { /* 0.0.0~0.0.7 */
                 rv_csr_write(CSR_MSMPR, 0x1);
                 rv_csr_write(CSR_MCCR2, 0xe0420008);
                 rv_csr_write(CSR_MXSTATUS, 0x638000);
                 rv_csr_write(CSR_MHINT, 0x2c50c);
                 rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
-            } else if (cpu_ver >= 0x0040 && cpu_ver <= 0x1002)
+            } else if (cpu_ver >= 0x0040 && cpu_ver <= 0x1002) { //0.1.0~1.0.2
-            { /* 0.1.0~1.0.2 */
                 rv_csr_write(CSR_MSMPR, 0x1);
                 rv_csr_write(CSR_MCCR2, 0xa042000a);
                 rv_csr_write(CSR_MXSTATUS, 0x438000);
@@ -240,8 +221,7 @@ void cpu_features_init(void)
 #if __riscv_xlen == 64
                 rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
-            } else if (cpu_ver >= 0x1003 && cpu_ver <= 0x100b)
+            } else if (cpu_ver >= 0x1003 && cpu_ver <= 0x100b) { //1.0.3~1.0.11
-            { /* 1.0.3~1.0.11 */
 
                 rv_csr_write(CSR_MSMPR, 0x1);
                 rv_csr_write(CSR_MCCR2, 0xa042000a);
@@ -251,8 +231,7 @@ void cpu_features_init(void)
 #if __riscv_xlen == 64
                 rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
-            } else if (cpu_ver >= 0x100c && cpu_ver <= 0x1fff)
+            } else if (cpu_ver >= 0x100c && cpu_ver <= 0x1fff) { //1.0.12~
-            { /* 1.0.12~ */
                 rv_csr_write(CSR_MSMPR, 0x1);
                 rv_csr_write(CSR_MCCR2, 0xa042000a);
                 rv_csr_write(CSR_MXSTATUS, 0x438100);
@@ -262,8 +241,7 @@ void cpu_features_init(void)
 #if __riscv_xlen == 64
                 rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
-            } else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff)
+            } else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~
-            { /* 2.0.0~ */
                 rv_csr_write(CSR_MSMPR, 0x1);
                 rv_csr_write(CSR_MCCR2, 0xa042000a);
                 rv_csr_write(CSR_MXSTATUS, 0x438100);
@@ -276,10 +254,8 @@ void cpu_features_init(void)
             } else {
                 while(1);
             }
-        } else if (cpu_tnmodel == 1)
+        } else if (cpu_tnmodel == 1) {
-        {
+            if (cpu_ver >= 0x0) {
-            if (cpu_ver >= 0x0)
-            {
                 rv_csr_write(CSR_MSMPR, 0x1);
                 rv_csr_write(CSR_MCCR2, 0xA0420002);
                 rv_csr_write(CSR_MXSTATUS, 0x438100);
@@ -297,8 +273,7 @@ void cpu_features_init(void)
         }
         break;
     case 0x6:
-        if (cpu_ver >= 0x0)
+        if (cpu_ver >= 0x0) {
-        {
             rv_csr_write(CSR_MSMPR, 0x1);
             rv_csr_write(CSR_MCCR2, 0xA0420002);
             rv_csr_write(CSR_MXSTATUS, 0x438000);
@@ -312,8 +287,7 @@ void cpu_features_init(void)
         }
         break;
     default:
-        /* FIXME: maybe qemu */
+        // FIXME: maybe qemu
         break;
     }
 }
-

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c

@@ -55,27 +55,39 @@ void soc_irq_priority(uint32_t irq_num, uint32_t priority)
  */
 uint32_t soc_irq_get_irq_num(void)
 {
-#if CONFIG_CPU_XUANTIE_E9XX
+    int hartid = csi_get_cpu_id();
-    return (__get_MCAUSE() & 0x3FFU);
+#if CONFIG_INTC_CLIC || CONFIG_CPU_XUANTIE_E9XX
+    (void) hartid;
+#if CONFIG_RISCV_SMODE
+    return (__get_SCAUSE() & 0x3FFU);
 #else
+    return (__get_MCAUSE() & 0x3FFU);
+#endif /* CONFIG_RISCV_SMODE */
+#endif /* CONFIG_INTC_CLIC */
+
+#if CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC
     uint32_t num;
-#if CONFIG_INTC_CLIC_PLIC
+#if CONFIG_RISCV_SMODE
+    uint32_t irqn = __get_SCAUSE() & 0x3FFU;
+#else
     uint32_t irqn = __get_MCAUSE() & 0x3FFU;
-    if (irqn == Machine_External_IRQn) {
+#endif /* CONFIG_RISCV_SMODE */
-        num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, csi_get_cpu_id());
+    if (irqn == Machine_External_IRQn || irqn == Supervisor_External_IRQn) {
+#if CONFIG_RISCV_SMODE
+        num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, hartid);
+#else
+        num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, hartid);
+#endif
+#if CONFIG_INTC_CLIC_PLIC
         num += PLIC_IRQ_OFFSET;
+#endif
     } else {
         num = irqn;
     }
-#else
-#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE
-    num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, csi_get_cpu_id());
-#else
-    num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, csi_get_cpu_id());
-#endif
-#endif
     return num;
-#endif /* end exx */
+#endif /* CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC */
+
+    return 0;
 }
 
 void soc_irq_end(uint32_t irq_num)

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/tick.c

@@ -72,10 +72,8 @@ void tick_irq_handler(void *arg)
     extern void xPortSysTickHandler(void);
     xPortSysTickHandler();
 #elif defined(CONFIG_KERNEL_RTTHREAD)
-    rt_interrupt_enter();
     extern void rt_tick_increase(void);
     rt_tick_increase();
-    rt_interrupt_leave();
 #else
 #endif
 #endif /* end CONFIG_AOS_OSAL */

bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_common.h

@@ -68,7 +68,20 @@
 #define __ASM_STR(x)    #x
 #endif
 
+#define     __I      volatile const       /*!< Defines 'read only' permissions */
+#define     __O      volatile             /*!< Defines 'write only' permissions */
+#define     __IO     volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const       /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile             /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile             /*! Defines 'read / write' structure member permissions */
+
 #ifndef __ASSEMBLY__
+
+#define RISCV_FENCE(p, s) \
+    __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
+
 #define rv_csr_read(csr)                                   \
     ({                                                  \
         register unsigned long __v;                     \
@@ -121,69 +134,291 @@
                              : : "rK"(__v)                 \
                              : "memory");                  \
     })
+
+#define rv_csr_read_write(csr, val)                              \
+     ({                                                          \
+         unsigned long __v = (unsigned long)(val);               \
+         __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \
+                              : "=r"(__v)                        \
+                              : "rK"(__v)                        \
+                              : "memory");                       \
+         __v;                                                    \
+     })
+
+ __ALWAYS_STATIC_INLINE uint8_t rv_readb(uintptr_t addr)
+ {
+    uint8_t val;
+
+    val = *(volatile uint8_t *)addr;
+    RISCV_FENCE(ir, ir);
+    return val;
+ }
+
+ __ALWAYS_STATIC_INLINE uint16_t rv_readw(uintptr_t addr)
+ {
+    uint16_t val;
+
+    val = *(volatile uint16_t *)addr;
+    RISCV_FENCE(ir, ir);
+    return val;
+ }
+
+ __ALWAYS_STATIC_INLINE uint32_t rv_readl(uintptr_t addr)
+ {
+    uint32_t val;
+
+    val = *(volatile uint32_t *)addr;
+    RISCV_FENCE(ir, ir);
+    return val;
+ }
+
+ __ALWAYS_STATIC_INLINE uint64_t rv_readq(uintptr_t addr)
+ {
+    uint64_t val;
+
+    val = *(volatile uint64_t *)addr;
+    RISCV_FENCE(ir, ir);
+    return val;
+ }
+
+ __ALWAYS_STATIC_INLINE void rv_writeb(uint8_t val, uintptr_t addr)
+ {
+    *(volatile uint8_t *)addr = val;
+    RISCV_FENCE(ow, ow);
+ }
+
+ __ALWAYS_STATIC_INLINE void rv_writew(uint16_t val, uintptr_t addr)
+ {
+    *(volatile uint16_t *)addr = val;
+    RISCV_FENCE(ow, ow);
+ }
+
+ __ALWAYS_STATIC_INLINE void rv_writel(uint32_t val, uintptr_t addr)
+ {
+    *(volatile uint32_t *)addr = val;
+    RISCV_FENCE(ow, ow);
+ }
+
+ __ALWAYS_STATIC_INLINE void rv_writeq(uint64_t val, uintptr_t addr)
+ {
+    *(volatile uint64_t *)addr = val;
+    RISCV_FENCE(ow, ow);
+ }
+
+/**
+  \brief   Get low 32 bits of MSTATEEN0
+  \details Returns the current value of the MSTATEEN0 register.
+  \return               MSTATEEN0 Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_MSTATEEN0(void)
+{
+    volatile unsigned long result;
+    __ASM volatile("csrr %0, mstateen0" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set low 32 bits of of MSTATEEN0
+  \details Assigns the given value to the MSTATEEN0 register.
+  \param [in]    mstateen0  MSTATEEN0 value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_MSTATEEN0(unsigned long mstateen0)
+{
+    __ASM volatile("csrw mstateen0, %0" : : "r"(mstateen0));
+}
+
+/**
+  \brief   Get high 32 bits of MSTATEEN0
+  \details Returns the current value of the MSTATEEN0H register.
+  \return               MSTATEEN0 Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_MSTATEEN0H(void)
+{
+    volatile unsigned long result;
+    __ASM volatile("csrr %0, mstateen0h" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set high 32 bits of of MSTATEEN0
+  \details Assigns the given value to the MSTATEEN0H register.
+  \param [in]    mstateen0  MSTATEEN0 value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_MSTATEEN0H(unsigned long mstateen0h)
+{
+    __ASM volatile("csrw mstateen0h, %0" : : "r"(mstateen0h));
+}
+
+/**
+  \brief   Get MIREG
+  \details Returns the current value of the MIREG.
+  \return               MIREG Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_MIREG(void)
+{
+    register unsigned long result;
+    __ASM volatile("csrr %0, mireg" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MIREG
+  \details Assigns the given value to the MIREG.
+  \param [in]    mireg  MIREG value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_MIREG(unsigned long mireg)
+{
+    __ASM volatile("csrw mireg, %0" : : "r"(mireg));
+}
+
+/**
+  \brief   Get MIREG2
+  \details Returns the current value of the MIREG2.
+  \return               MIREG2 Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_MIREG2(void)
+{
+    register unsigned long result;
+    __ASM volatile("csrr %0, mireg2" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MIREG2
+  \details Assigns the given value to the MIREG2.
+  \param [in]    mireg2  MIREG2 value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_MIREG2(unsigned long mireg2)
+{
+    __ASM volatile("csrw mireg2, %0" : : "r"(mireg2));
+}
+
+/**
+  \brief   Get SIREG
+  \details Returns the current value of the SIREG.
+  \return               SIREG Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_SIREG(void)
+{
+    register unsigned long result;
+    __ASM volatile("csrr %0, sireg" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set SIREG
+  \details Assigns the given value to the SIREG.
+  \param [in]    sireg  SIREG value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_SIREG(unsigned long sireg)
+{
+    __ASM volatile("csrw sireg, %0" : : "r"(sireg));
+}
+
+/**
+  \brief   Get SIREG2
+  \details Returns the current value of the SIREG2.
+  \return               SIREG2 Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_SIREG2(void)
+{
+    register unsigned long result;
+    __ASM volatile("csrr %0, sireg2" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set SIREG2
+  \details Assigns the given value to the SIREG2.
+  \param [in]    sireg2  SIREG2 value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_SIREG2(unsigned long sireg2)
+{
+    __ASM volatile("csrw sireg2, %0" : : "r"(sireg2));
+}
+
+/**
+  \brief   Get MISELECT
+  \details Returns the current value of the MISELECT.
+  \return               MISELECT Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_MISELECT(void)
+{
+    register unsigned long result;
+    __ASM volatile("csrr %0, miselect" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set MISELECT
+  \details Assigns the given value to the MISELECT.
+  \param [in]    miselect  MISELECT value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_MISELECT(unsigned long miselect)
+{
+    __ASM volatile("csrw miselect, %0" : : "r"(miselect));
+}
+
+/**
+  \brief   Get SISELECT
+  \details Returns the current value of the SISELECT.
+  \return               SISELECT Register value
+  */
+__ALWAYS_STATIC_INLINE unsigned long __get_SISELECT(void)
+{
+    register unsigned long result;
+    __ASM volatile("csrr %0, siselect" : "=r"(result));
+    return (result);
+}
+
+/**
+  \brief   Set SISELECT
+  \details Assigns the given value to the SISELECT.
+  \param [in]    siselect  SISELECT value to set
+  */
+__ALWAYS_STATIC_INLINE void __set_SISELECT(unsigned long siselect)
+{
+    __ASM volatile("csrw siselect, %0" : : "r"(siselect));
+}
+
+__ALWAYS_STATIC_INLINE uint8_t is_power_of_two(uint32_t x)
+{
+    return x && !(x & (x - 1));
+}
+
+__ALWAYS_STATIC_INLINE uint32_t log2_ulong(unsigned long x)
+{
+    uint32_t result = 0;
+    while (x > 1) {
+        x >>= 1;
+        result++;
+    }
+    return result;
+}
+
+__ALWAYS_STATIC_INLINE unsigned long align_to_power_of_two(unsigned long size)
+{
+    if (size <= 1) {
+        return size;
+    }
+
+#if defined(__GNUC__) || defined(__clang__)
+    unsigned long leading_zeros = __builtin_clzl(size - 1);
+    return 1UL << ((sizeof(unsigned long) << 3) - leading_zeros);
+#else
+    unsigned long value = size - 1;
+    value |= value >> 1;
+    value |= value >> 2;
+    value |= value >> 4;
+    value |= value >> 8;
+    value |= value >> 16;
+#if __SIZEOF_LONG__ == 8
+    value |= value >> 32;
 #endif
+    return value + 1;
+#endif
+}
 
-#define CSR_MCOR        0x7c2
+#endif /* __ASSEMBLY__ */
-#define CSR_MHCR        0x7c1
-#define CSR_MCCR2       0x7c3
-#define CSR_MHINT       0x7c5
-#define CSR_MHINT2      0x7cc
-#define CSR_MHINT3      0x7cd
-#define CSR_MHINT4      0x7ce
-#define CSR_MXSTATUS    0x7c0
-#define CSR_PLIC_BASE   0xfc1
-#define CSR_MRMR        0x7c6
-#define CSR_MRVBR       0x7c7
-#define CSR_MCOUNTERWEN 0x7c9
-#define CSR_MSMPR       0x7f3
-
-#define CSR_MARCHID     0xf12
-#define CSR_MIMPID      0xf13
-#define CSR_MHARTID     0xf14
-#define CSR_MCPUID      0xfc0
-
-#define CSR_MSTATUS     0x300
-#define CSR_MISA        0x301
-#define CSR_MEDELEG     0x302
-#define CSR_MIDELEG     0x303
-#define CSR_MIE         0x304
-#define CSR_MTVEC       0x305
-#define CSR_MCOUNTEREN  0x306
-#define CSR_MENVCFG     0x30a
-#define CSR_MSTATUSH    0x310
-#define CSR_MSCRATCH    0x340
-#define CSR_MEPC        0x341
-#define CSR_MCAUSE      0x342
-#define CSR_MTVAL       0x343
-#define CSR_MIP         0x344
-#define CSR_MTINST      0x34a
-#define CSR_MTVAL2      0x34b
-
- /* Machine Memory Protection */
-#define CSR_PMPCFG0     0x3a0
-#define CSR_PMPCFG1     0x3a1
-#define CSR_PMPCFG2     0x3a2
-#define CSR_PMPCFG3     0x3a3
-#define CSR_PMPCFG4     0x3a4
-#define CSR_PMPCFG5     0x3a5
-#define CSR_PMPCFG6     0x3a6
-#define CSR_PMPCFG7     0x3a7
-#define CSR_PMPCFG8     0x3a8
-#define CSR_PMPCFG9     0x3a9
-#define CSR_PMPCFG10    0x3aa
-#define CSR_PMPCFG11    0x3ab
-#define CSR_PMPCFG12    0x3ac
-#define CSR_PMPCFG13    0x3ad
-#define CSR_PMPCFG14    0x3ae
-#define CSR_PMPCFG15    0x3af
-#define CSR_PMPADDR0    0x3b0
-#define CSR_PMPADDR1    0x3b1
-#define CSR_PMPADDR2    0x3b2
-#define CSR_PMPADDR3    0x3b3
-#define CSR_PMPADDR4    0x3b4
-#define CSR_PMPADDR5    0x3b5
-#define CSR_PMPADDR6    0x3b6
-#define CSR_PMPADDR7    0x3b7
 
 #endif /* __CSI_RV_COMMON_H__ */
-

bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h

@@ -52,6 +52,7 @@
 
 #elif defined(__riscv)
 
+#include <core/csi_rv_encoding.h>
 #if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \
     || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP \
     || CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \

bsp/xuantie/libraries/xuantie_libraries/lib_cpu/SConscript

@@ -0,0 +1,17 @@
+from building import *
+import os
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+src = ['cpuport.c', 'interrupt.c']
+src += ['context_gcc.S', 'interrupt_gcc.S']
+
+if GetDepend(['RT_USING_HW_ATOMIC']):
+    src += ['atomic_riscv.c']
+
+if GetDepend(['RT_USING_SMP']):
+    src += ['cpuport_smp.c', 'clint.c']
+
+group = DefineGroup('lib_cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/xuantie/libraries/xuantie_libraries/lib_cpu/atomic_riscv.c

@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-03-14     WangShun     first version
+ */
+
+#include <rtthread.h>
+
+rt_atomic_t rt_hw_atomic_exchange(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+rt_atomic_t rt_hw_atomic_add(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+rt_atomic_t rt_hw_atomic_sub(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t result = 0;
+    val = -val;
+#if __riscv_xlen == 32
+    asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+rt_atomic_t rt_hw_atomic_xor(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoxor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoxor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+rt_atomic_t rt_hw_atomic_and(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoand.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoand.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+rt_atomic_t rt_hw_atomic_or(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+rt_atomic_t rt_hw_atomic_load(volatile rt_atomic_t *ptr)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoxor.w %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoxor.d %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+void rt_hw_atomic_store(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
+#endif
+}
+
+rt_atomic_t rt_hw_atomic_flag_test_and_set(volatile rt_atomic_t *ptr)
+{
+    rt_atomic_t result = 0;
+    rt_atomic_t temp = 1;
+#if __riscv_xlen == 32
+    asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory");
+#endif
+    return result;
+}
+
+void rt_hw_atomic_flag_clear(volatile rt_atomic_t *ptr)
+{
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile ("amoand.w %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory");
+#elif __riscv_xlen == 64
+    asm volatile ("amoand.d %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory");
+#endif
+}
+
+rt_atomic_t rt_hw_atomic_compare_exchange_strong(volatile rt_atomic_t *ptr, rt_atomic_t *old, rt_atomic_t desired)
+{
+    rt_atomic_t tmp = *old;
+    rt_atomic_t result = 0;
+#if __riscv_xlen == 32
+    asm volatile(
+            " fence iorw, ow\n"
+            "1: lr.w.aq  %[result], (%[ptr])\n"
+            "   bne      %[result], %[tmp], 2f\n"
+            "   sc.w.rl  %[tmp], %[desired], (%[ptr])\n"
+            "   bnez     %[tmp], 1b\n"
+            "   li  %[result], 1\n"
+            "   j 3f\n"
+            " 2:sw  %[result], (%[old])\n"
+            "   li  %[result], 0\n"
+            " 3:\n"
+            : [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr)
+            : [desired]"r" (desired), [old]"r"(old)
+            : "memory");
+#elif __riscv_xlen == 64
+    asm volatile(
+            " fence iorw, ow\n"
+            "1: lr.d.aq  %[result], (%[ptr])\n"
+            "   bne      %[result], %[tmp], 2f\n"
+            "   sc.d.rl  %[tmp], %[desired], (%[ptr])\n"
+            "   bnez     %[tmp], 1b\n"
+            "   li  %[result], 1\n"
+            "   j 3f\n"
+            " 2:sd  %[result], (%[old])\n"
+            "   li  %[result], 0\n"
+            " 3:\n"
+            : [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr)
+            : [desired]"r" (desired), [old]"r"(old)
+            : "memory");
+#endif
+    return result;
+}