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feat: arm64: update thread self on sp-switch

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This patch improves the atomicity of context switching by ensuring that
the stack pointer (sp) and thread self updates occur simultaneously.
This enhancement is crucial for maintaining thread safety and
preventing potential inconsistencies during context switches.

Changes:
- Modified `cpuport.h` to use `ARM64_THREAD_REG` for thread self access.
- Added an `update_tidr` macro in `context_gcc.S` to streamline thread ID
  updates.
- Adjusted `rt_hw_context_switch_to` and `rt_hw_context_switch` to call
  `update_tidr`, ensuring atomic updates during context switches.
- Cleaned up `scheduler_mp.c` by removing redundant thread self
  assignments.

Signed-off-by: Shell <smokewood@qq.com>
This commit is contained in:
Shell
2024-10-11 00:09:01 -04:00
committed by Meco Man
parent 906d1caea6
commit 5796e0d646
4 changed files with 17 additions and 5 deletions
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libcpu/aarch64/common/include/armv8.h
+6
View File
@@ -11,6 +11,12 @@
#ifndef __ARMV8_H__
#define __ARMV8_H__
#include <rtconfig.h>
#ifdef ARCH_USING_HW_THREAD_SELF
#define ARM64_THREAD_REG tpidr_el1
#endif /* ARCH_USING_HW_THREAD_SELF */
#ifdef __ASSEMBLY__
/*********************
libcpu/aarch64/common/include/cpuport.h
+2 -2
View File
@@ -57,14 +57,14 @@ void _thread_start(void);
rt_inline struct rt_thread *rt_hw_thread_self(void)
{
struct rt_thread *thread;
__asm__ volatile ("mrs %0, tpidr_el1":"=r"(thread));
__asm__ volatile ("mrs %0, " RT_STRINGIFY(ARM64_THREAD_REG) :"=r"(thread));
return thread;
}
rt_inline void rt_hw_thread_set_self(struct rt_thread *thread)
{
__asm__ volatile ("msr tpidr_el1, %0"::"r"(thread));
__asm__ volatile ("msr " RT_STRINGIFY(ARM64_THREAD_REG) ", %0"::"r"(thread));
}
#endif /* ARCH_USING_HW_THREAD_SELF */